* [linux-sunxi] [PATCH 07/15] dt-bindings: display: sun4i-drm: Add R40 HDMI pipeline
From: Julian Calaby @ 2018-05-20 1:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-8-jernej.skrabec@siol.net>
Hi Jernej,
On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec <jernej.skrabec@siol.net> wrote:
> Missing compatibles and descriptions needed to implement R40 HDMI
> pipeline are added.
>
> For mixers only compatibles are added.
>
> TCON description is expanded with R40 TV TCON compatibles. If the SoC
> has TCON TOP unit, phandle to that unit has to be specified. Additional
> clock has to be specified if SoC has TCON TOP and TCON is TV TCON.
>
> New compatible is added for DWC HDMI PHY, which has additional clock
> specified.
There's a bunch of A64 related stuff mixed in here, is the R40
compatible with the A64's parts? If so, you should probably mention
that in the commit log.
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
> .../bindings/display/sunxi/sun4i-drm.txt | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> index a099957ab62a..634276f713e8 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -111,8 +112,9 @@ Required properties:
> - resets: phandle to the reset controller driving the PHY
> - reset-names: must be "phy"
>
> -H3 HDMI PHY requires additional clock:
> +H3 and A64 HDMI PHY requires additional clocks:
> - pll-0: parent of phy clock
> + - pll-1: second possible phy clock parent (A64 only)
Maybe split this into two:
H3 HDMI PHY ...
- pll-0: ...
A64 HDMI PHY ...
- pll-0: ...
- pll-1: ...
At the moment a quick reading implies that H3 needs pll-1.
Thanks,
--
Julian Calaby
Email: julian.calaby at gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
^ permalink raw reply
* [GIT PULL] ARM: SoC fixes
From: Olof Johansson @ 2018-05-20 1:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
The following changes since commit 67b8d5c7081221efa252e111cd52532ec6d4266f:
Linux 4.17-rc5 (2018-05-13 16:15:17 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/armsoc-fixes
for you to fetch changes up to 709f490d5b594b9548577d2285ffeaad8a278b10:
Merge tag 'tegra-for-4.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into fixes (2018-05-19 17:58:32 -0700)
----------------------------------------------------------------
ARM: SoC fixes for 4.17-rc
A handful of fixes. I've been queuing them up a bit too long so the list
is longer than it otherwise would have been spread out across a few -rcs.
In general, it's a scattering of fixes across several platforms, nothing
truly serious enough to point out.
There's a slightly larger batch of them for the Davinci platforms due
to work to bring them back to life after some time, so there's a handful
of regressions, some of them going back very far, others more recent.
There's also a few patches fixing DT on Renesas platforms since they
changed some bindings without remaining backwards compatible, splitting
up describing LVDS as a proper bridge instead of having it as part of the
display unit. We could push for them to be backwards compatible with old
device trees, but it's likely to regress eventually if nobody's actually
using said compatibility.
----------------------------------------------------------------
Adam Ford (3):
ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues
ARM: dts: logicpd-som-lv: Fix Audio Mute
ARM: dts: logicpd-som-lv: Fix pinmux controller references
Bhadram Varka (1):
arm64: tegra: Make BCM89610 PHY interrupt as active low
Cl?ment P?ron (1):
ARM: dts: cygnus: fix irq type for arm global timer
Dan Carpenter (1):
firmware: arm_scmi: Use after free in scmi_create_protocol_device()
Dmitry Osipenko (1):
ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
Etienne Carriere (1):
tee: check shm references are consistent in offset/size
Fabio Estevam (1):
ARM: dts: imx7s: Pass the 'fsl,sec-era' property
Graeme Smecher (1):
ARM: dts: correct missing "compatible" entry for ti81xx SoCs
Jann Horn (1):
tee: shm: fix use-after-free via temporarily dropped reference
Janusz Krzysztofik (1):
ARM: OMAP1: ams-delta: fix deferred_fiq handler
Laurent Pinchart (3):
ARM: dts: r8a7790: Convert to new LVDS DT bindings
ARM: dts: r8a7791: Convert to new LVDS DT bindings
ARM: dts: r8a7793: Convert to new LVDS DT bindings
Marek Szyprowski (1):
arm64: dts: exynos: Fix interrupt type for I2S1 device on Exynos5433
Masahiro Yamada (3):
arm64: dts: uniphier: fix input delay value for legacy mode of eMMC
reset: uniphier: fix USB clock line for LD20
arm64: dts: uniphier: stabilize ethernet of LD20 reference board
Maxime Chevallier (2):
ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node
Nikita Yushchenko (1):
ARM: dts: imx51-zii-rdu1: fix touchscreen bindings
Olof Johansson (13):
Merge tag 'uniphier-fixes-v4.17' of git://git.kernel.org/.../masahiroy/linux-uniphier into fixes
Merge tag 'renesas-fixes-for-v4.17' of https://git.kernel.org/.../horms/renesas into fixes
Merge tag 'davinci-fixes-for-v4.17' of git://git.kernel.org/.../nsekhar/linux-davinci into fixes
Merge tag 'tegra-for-4.17-fixes' of git://git.kernel.org/.../tegra/linux into fixes
Merge tag 'tee-drv-fixes-for-4.17' of git://git.linaro.org/people/jens.wiklander/linux-tee into fixes
Merge tag 'arm-soc/for-4.17/devicetree-fixes' of https://github.com/Broadcom/stblinux into fixes
Merge tag 'omap-for-v17/fixes-rc4' of git://git.kernel.org/.../tmlind/linux-omap into fixes
Merge tag 'scmi-fixes-4.17' of git://git.kernel.org/.../sudeep.holla/linux into fixes
Merge tag 'imx-fixes-4.17' of git://git.kernel.org/.../shawnguo/linux into fixes
Merge tag 'mvebu-fixes-4.17-1' of git://git.infradead.org/linux-mvebu into fixes
Merge tag 'reset-fixes-for-4.17' of git://git.pengutronix.de/pza/linux into fixes
Merge tag 'davinci-fixes-for-v4.17-part-2' of git://git.kernel.org/.../nsekhar/linux-davinci into fixes
Merge tag 'tegra-for-4.17-fixes-2' of git://git.kernel.org/.../tegra/linux into fixes
Russell King (1):
ARM: keystone: fix platform_domain_notifier array overrun
Sekhar Nori (11):
ARM: dts: da850: get rid of skeleton.dtsi
ARM: dts: da850-lcdk: add unit name for memory node
ARM: dts: da850: fix W=1 warnings with pinmux node
ARM: davinci: board-da830-evm: fix GPIO lookup for MMC/SD
ARM: davinci: board-da850-evm: fix GPIO lookup for MMC/SD
ARM: davinci: board-omapl138-hawk: fix GPIO numbers for MMC/SD lookup
ARM: davinci: board-dm355-evm: fix broken networking
ARM: davinci: fix GPIO lookup for I2C
ARM: davinci: dm646x: fix timer interrupt generation
ARM: davinci: board-dm646x-evm: pass correct I2C adapter id for VPIF
ARM: davinci: board-dm646x-evm: set VPIF capture card name
Tero Kristo (1):
ARM: OMAP2+: powerdomain: use raw_smp_processor_id() for trace
Tony Lindgren (1):
Revert "ARM: dts: logicpd-som-lv: Fix pinmux controller references"
.../devicetree/bindings/net/marvell-pp2.txt | 9 +--
arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +-
arch/arm/boot/dts/da850-lcdk.dts | 4 +-
arch/arm/boot/dts/da850.dtsi | 13 ++++-
arch/arm/boot/dts/dm8148-evm.dts | 2 +-
arch/arm/boot/dts/dm8148-t410.dts | 2 +-
arch/arm/boot/dts/dm8168-evm.dts | 2 +-
arch/arm/boot/dts/dra62x-j5eco-evm.dts | 2 +-
arch/arm/boot/dts/imx51-zii-rdu1.dts | 6 +-
arch/arm/boot/dts/imx7s.dtsi | 1 +
arch/arm/boot/dts/logicpd-som-lv.dtsi | 11 +++-
arch/arm/boot/dts/r8a7790-lager.dts | 22 ++++++--
arch/arm/boot/dts/r8a7790.dtsi | 65 +++++++++++++++++++---
arch/arm/boot/dts/r8a7791-koelsch.dts | 12 +++-
arch/arm/boot/dts/r8a7791-porter.dts | 16 +++++-
arch/arm/boot/dts/r8a7791.dtsi | 36 ++++++++++--
arch/arm/boot/dts/r8a7793-gose.dts | 10 +++-
arch/arm/boot/dts/r8a7793.dtsi | 37 ++++++++++--
arch/arm/boot/dts/tegra20.dtsi | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 9 ++-
arch/arm/mach-davinci/board-da850-evm.c | 9 ++-
arch/arm/mach-davinci/board-dm355-evm.c | 15 ++++-
arch/arm/mach-davinci/board-dm644x-evm.c | 10 +++-
arch/arm/mach-davinci/board-dm646x-evm.c | 5 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 10 +++-
arch/arm/mach-davinci/dm646x.c | 3 +-
arch/arm/mach-keystone/pm_domain.c | 1 +
arch/arm/mach-omap1/ams-delta-fiq.c | 28 +++++-----
arch/arm/mach-omap2/powerdomain.c | 4 +-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 7 ++-
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +-
.../arm64/boot/dts/socionext/uniphier-ld20-ref.dts | 8 +++
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 +-
drivers/firmware/arm_scmi/driver.c | 1 +
drivers/reset/reset-uniphier.c | 6 +-
drivers/tee/tee_core.c | 11 ++++
drivers/tee/tee_shm.c | 5 +-
40 files changed, 300 insertions(+), 96 deletions(-)
^ permalink raw reply
* [GIT PULL] arm64: tegra: Device tree fixes for v4.17
From: Olof Johansson @ 2018-05-20 0:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180517160436.12180-1-thierry.reding@gmail.com>
On Thu, May 17, 2018 at 06:04:36PM +0200, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
>
> Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.17-fixes-2
>
> for you to fetch changes up to 9df50ba76ac1485b844beffa1f3f5d9659d9cdaf:
>
> arm64: tegra: Make BCM89610 PHY interrupt as active low (2018-05-03 11:48:16 +0200)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> arm64: tegra: Device tree fixes for v4.17
>
> This contains a one-line update to the device tree of the Tegra186 P3310
> processor module, fixing the polarity of the PHY interrupt. Originally,
> this was queued to go into v4.18, but the PHY ID matching patch has now
> found its way into v4.17-rc5, which means that the PHY driver will know
> how to identify the PHY on this board and try to use the interrupt. This
> will unfortunately cause networking to break on P3310, hence why I think
> this should go into v4.17.
Merged, thanks.
-Olof
^ permalink raw reply
* [RHEL-8] arm64: add missing early clobber in atomic64_dec_if_positive()
From: Mark Salter @ 2018-05-20 0:17 UTC (permalink / raw)
To: linux-arm-kernel
When running a kernel compiled with gcc8 on a machine using LSE, I
get:
Unable to handle kernel paging request at virtual address 11111122222221
Mem abort info:
ESR = 0x96000021
Exception class = DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
Data abort info:
ISV = 0, ISS = 0x00000021
CM = 0, WnR = 0
[0011111122222221] address between user and kernel address ranges
Internal error: Oops: 96000021 [#1] SMP
...
pstate: 20400009 (nzCv daif +PAN -UAO)
pc : test_atomic64+0x1360/0x155c
lr : 0x1111111122222222
sp : ffff00000bc6fd60
x29: ffff00000bc6fd60 x28: 0000000000000000
x27: 0000000000000000 x26: ffff000008f04460
x25: ffff000008de0584 x24: ffff000008e91060
x23: aaa31337c001d00e x22: 999202269ddfadeb
x21: aaa31337c001d00c x20: bbb42448e223f22f
x19: aaa31337c001d00d x18: 0000000000000010
x17: 0000000000000222 x16: 00000000000010e0
x15: ffffffffffffffff x14: ffff000009233c08
x13: ffff000089925a8f x12: ffff000009925a97
x11: ffff00000927f000 x10: ffff00000bc6fac0
x9 : 00000000ffffffd0 x8 : ffff00000853fdf8
x7 : 00000000deadbeef x6 : ffff00000bc6fda0
x5 : aaa31337c001d00d x4 : deadbeefdeafcafe
x3 : aaa31337c001d00d x2 : aaa31337c001d00e
x1 : 1111111122222222 x0 : 1111111122222221
Process swapper/0 (pid: 1, stack limit = 0x000000008209f908)
Call trace:
test_atomic64+0x1360/0x155c
test_atomics_init+0x10/0x28
do_one_initcall+0x134/0x160
kernel_init_freeable+0x18c/0x21c
kernel_init+0x18/0x108
ret_from_fork+0x10/0x1c
Code: f90023e1 f940001e f10007c0 540000ab (c8fefc00)
---[ end trace 29569e7320c6e926 ]---
The fault happens at the casal insn of inlined atomic64_dec_if_positive().
The inline asm code in that function has:
"1: ldr x30, %[v]\n"
" subs %[ret], x30, #1\n"
" b.lt 2f\n"
" casal x30, %[ret], %[v]\n"
" sub x30, x30, #1\n"
" sub x30, x30, %[ret]\n"
" cbnz x30, 1b\n"
"2:")
: [ret] "+r" (x0), [v] "+Q" (v->counter)
gcc8 used register x0 for both [ret] and [v] and the subs was
clobbering [v] before it was used for casal. Gcc is free to do
this because [ret] lacks an early clobber modifier. So add one
to tell gcc a separate register is needed for [v].
Signed-off-by: Mark Salter <msalter@redhat.com>
---
arch/arm64/include/asm/atomic_lse.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/atomic_lse.h b/arch/arm64/include/asm/atomic_lse.h
index 9ef0797380cb..99fa69c9c3cf 100644
--- a/arch/arm64/include/asm/atomic_lse.h
+++ b/arch/arm64/include/asm/atomic_lse.h
@@ -435,7 +435,7 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
" sub x30, x30, %[ret]\n"
" cbnz x30, 1b\n"
"2:")
- : [ret] "+r" (x0), [v] "+Q" (v->counter)
+ : [ret] "+&r" (x0), [v] "+Q" (v->counter)
:
: __LL_SC_CLOBBERS, "cc", "memory");
--
2.17.0
^ permalink raw reply related
* [PATCH v3 1/2] soc: imx: gpcv2: Do not pass static memory as platform data
From: Andrey Smirnov @ 2018-05-19 22:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180410183210.28052-1-andrew.smirnov@gmail.com>
On Tue, Apr 10, 2018 at 11:32 AM, Andrey Smirnov
<andrew.smirnov@gmail.com> wrote:
> Platform device core assumes the ownership of dev.platform_data as
> well as that it is dynamically allocated and it will try to kfree it
> as a part of platform_device_release(). Change the code to use
> platform_device_add_data() n instead of a pointer to a static memory
> to avoid causing a BUG() when calling platform_device_put().
>
> The problem can be reproduced by artificially enabling the error path
> of platform_device_add() call (around line 357).
>
> Note that this change also allows us to constify imx7_pgc_domains,
> since we no longer need to be able to modify it.
>
Shawn,
What's the status of these two patches? Do I need to change anything
or are they good to go?
Thanks,
Andrey Smirnov
^ permalink raw reply
* [PATCH v2 3/6] ARM: trusted_foundations: do not use naked function
From: Dmitry Osipenko @ 2018-05-19 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507a66ab9ab530a6d71db7a74f11ddfb@agner.ch>
On 16.04.2018 21:21, Stefan Agner wrote:
> On 16.04.2018 18:08, Stephen Warren wrote:
>> On 04/16/2018 09:56 AM, Stefan Agner wrote:
>>> On 27.03.2018 14:16, Dmitry Osipenko wrote:
>>>> On 27.03.2018 14:54, Robin Murphy wrote:
>>>>> On 26/03/18 22:20, Dmitry Osipenko wrote:
>>>>>> On 25.03.2018 21:09, Stefan Agner wrote:
>>>>>>> As documented in GCC naked functions should only use Basic asm
>>>>>>> syntax. The Extended asm or mixture of Basic asm and "C" code is
>>>>>>> not guaranteed. Currently this works because it was hard coded
>>>>>>> to follow and check GCC behavior for arguments and register
>>>>>>> placement.
>>>>>>>
>>>>>>> Furthermore with clang using parameters in Extended asm in a
>>>>>>> naked function is not supported:
>>>>>>> ?? arch/arm/firmware/trusted_foundations.c:47:10: error: parameter
>>>>>>> ?????????? references not allowed in naked functions
>>>>>>> ???????????????? : "r" (type), "r" (arg1), "r" (arg2)
>>>>>>> ??????????????????????? ^
>>>>>>>
>>>>>>> Use a regular function to be more portable. This aligns also with
>>>>>>> the other smc call implementations e.g. in qcom_scm-32.c and
>>>>>>> bcm_kona_smc.c.
>>>>>>>
>>>>>>> Cc: Dmitry Osipenko <digetx@gmail.com>
>>>>>>> Cc: Stephen Warren <swarren@nvidia.com>
>>>>>>> Cc: Thierry Reding <treding@nvidia.com>
>>>>>>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>>>>>>> ---
>>>>>>> Changes in v2:
>>>>>>> - Keep stmfd/ldmfd to avoid potential ABI issues
>>>>>>>
>>>>>>> ? arch/arm/firmware/trusted_foundations.c | 14 +++++++++-----
>>>>>>> ? 1 file changed, 9 insertions(+), 5 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm/firmware/trusted_foundations.c
>>>>>>> b/arch/arm/firmware/trusted_foundations.c
>>>>>>> index 3fb1b5a1dce9..689e6565abfc 100644
>>>>>>> --- a/arch/arm/firmware/trusted_foundations.c
>>>>>>> +++ b/arch/arm/firmware/trusted_foundations.c
>>>>>>> @@ -31,21 +31,25 @@
>>>>>>> ? ? static unsigned long cpu_boot_addr;
>>>>>>> ? -static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
>>>>>>> +static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
>>>>>>> ? {
>>>>>>> +??? register u32 r0 asm("r0") = type;
>>>>>>> +??? register u32 r1 asm("r1") = arg1;
>>>>>>> +??? register u32 r2 asm("r2") = arg2;
>>>>>>> +
>>>>>>> ????? asm volatile(
>>>>>>> ????????? ".arch_extension??? sec\n\t"
>>>>>>> -??????? "stmfd??? sp!, {r4 - r11, lr}\n\t"
>>>>>>> +??????? "stmfd??? sp!, {r4 - r11}\n\t"
>>>>>>> ????????? __asmeq("%0", "r0")
>>>>>>> ????????? __asmeq("%1", "r1")
>>>>>>> ????????? __asmeq("%2", "r2")
>>>>>>> ????????? "mov??? r3, #0\n\t"
>>>>>>> ????????? "mov??? r4, #0\n\t"
>>>>>>> ????????? "smc??? #0\n\t"
>>>>>>> -??????? "ldmfd??? sp!, {r4 - r11, pc}"
>>>>>>> +??????? "ldmfd??? sp!, {r4 - r11}\n\t"
>>>>>>> ????????? :
>>>>>>> -??????? : "r" (type), "r" (arg1), "r" (arg2)
>>>>>>> -??????? : "memory");
>>>>>>> +??????? : "r" (r0), "r" (r1), "r" (r2)
>>>>>>> +??????? : "memory", "r3", "r12", "lr");
>>>>>>
>>>>>> Although seems "lr" won't be affected by SMC invocation because it should be
>>>>>> banked and hence could be omitted entirely from the code. Maybe somebody could
>>>>>> confirm this.
>>>>> Strictly per the letter of the architecture, the SMC could be trapped to Hyp
>>>>> mode, and a hypervisor might clobber LR_usr in the process of forwarding the
>>>>> call to the firmware secure monitor (since Hyp doesn't have a banked LR of its
>>>>> own). Admittedly there are probably no real systems with the appropriate
>>>>> hardware/software combination to hit that, but on the other hand if this gets
>>>>> inlined where the compiler has already created a stack frame then an LR clobber
>>>>> is essentially free, so I reckon we're better off keeping it for reassurance.
>>>>> This isn't exactly a critical fast path anyway.
>>>>
>>>> Okay, thank you for the clarification.
>>>
>>> So it seems this change is fine?
>>>
>>> Stephen, you picked up changes for this driver before, is this patch
>>> going through your tree?
>>
>> You had best ask Thierry; he's taken over Tegra maintenance upstream.
>> But that said, don't files in arch/arm go through Russell?
>
> I think the last patches applied to that file went through your tree.
>
> Thierry, Russel, any preferences?
I've been preparing patches for upstream to add initial support of L2 cache
maintance to TF / Tegra30 and noticed that without this patch I'm getting a hang
early in boot. That is because before this patch registers store / restore was
incorrect, probably the premature return (lr -> pc) causes stack corruption. Not
sure whether it's worth to backport this patch, but I want to see it at least in
-next.
Thierry, please take care of this patch. Thanks.
^ permalink raw reply
* [PATCH 5/6] mtd: rawnand: ams-delta: use GPIO lookup table
From: Janusz Krzysztofik @ 2018-05-19 21:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHp75VcUxjubx=zOGyCjmpjCk5RBLPCaHcaOieDie9LdTCa+5g@mail.gmail.com>
On Saturday, May 19, 2018 8:00:38 PM CEST Andy Shevchenko wrote:
> On Sat, May 19, 2018 at 2:15 AM, Janusz Krzysztofik <jmkrzyszt@gmail.com>
wrote:
> > On Friday, May 18, 2018 11:21:14 PM CEST Andy Shevchenko wrote:
> >> On Sat, May 19, 2018 at 12:09 AM, Janusz Krzysztofik
> >>
> >> <jmkrzyszt@gmail.com> wrote:
> >> > + gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy",
> >> > GPIOD_IN);
> >> > + if (!IS_ERR_OR_NULL(gpiod_rdy)) {
> >>
> >> So, is it optional or not at the end?
> >> If it is, why do we check for NULL?
> >
> > As far as I can understand, nand_chip->dev_ready() callback is optional.
> > That's why I decided to use the _optional variant of devm_gpiod_get(). In
> > case of ams-delta, the dev_ready() callback depends on availability of
> > the 'rdy' GPIO pin. As a consequence, I'm checking for both NULL and ERR
> > in order to decide if dev_ready() will be supported.
> >
> > I can pretty well replace it with the standard form and check for ERR only
> > if the purpose of the _optional form is different.
>
> NULL check in practice discards the _optional part of gpiod_get(). So,
> either you use non-optional variant and decide how to handle an
> errors, or user _optional w/o NULL check.
OK, I'm going to use something like the below while submitting v2:
- gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN);
- if (!IS_ERR_OR_NULL(gpiod_rdy)) {
- this->dev_ready = ams_delta_nand_ready;
- } else {
- this->dev_ready = NULL;
- pr_notice("Couldn't request gpio for Delta NAND ready.\n");
+ priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy",
+ GPIOD_IN);
+ if (IS_ERR(priv->gpiod_rdy)) {
+ err = PTR_ERR(priv->gpiod_nwp);
+ dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err);
+ goto err_gpiod;
}
+ if (priv->gpiod_rdy)
+ this->dev_ready = ams_delta_nand_ready;
>
> >> > +err_gpiod:
> >> > + if (err == -ENODEV || err == -ENOENT)
> >> > + err = -EPROBE_DEFER;
> >>
> >> Hmm...
> >
> > Amstrad Delta uses gpio-mmio driver. Unfortunatelty that driver is not
> > availble before device init phase, unlike other crucial GPIO drivers which
> > are initialized earlier, e.g. during the postcore or at latetst the
> > subsys phase. Hence, devices which depend on GPIO pins provided by
> > gpio-mmio must either be declared late or fail softly so they get another
> > chance of being probed succesfully.
> >
> > I thought of replacing the gpio-mmio platform driver with bgpio functions
> > it exports but for now I haven't implemented it, not even shared the
> > idea.
> >
> > Does it really hurt to return -EPROBE_DEFER if a GPIO pin can't be
> > obtained?
> I'm only concerned if it would be an infinite defer in the case when
> driver will never appear.
> But I don't remember the details.
Deferred probes are handled effectively during late_initcall, no risk of
infinite defer, see drivers/base/dd.c for details.
Thanks,
Janusz
^ permalink raw reply
* [arm:sa1100 80/87] ERROR: "ipaq_micro_tx_msg" [arch/arm/mach-sa1100/h3xxx-sleeve.ko] undefined!
From: kbuild test robot @ 2018-05-19 20:59 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git sa1100
head: 6713179ef01a294e21b4b2ff808a8d30155af2ad
commit: 6b9bc7e8128e38bc39eea71789c6e914f13b6d5a [80/87] ARM: sa1100/h3xxx: sleeve support
config: arm-neponset_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 6b9bc7e8128e38bc39eea71789c6e914f13b6d5a
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> ERROR: "ipaq_micro_tx_msg" [arch/arm/mach-sa1100/h3xxx-sleeve.ko] undefined!
---
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* [arm:zii 12/20] net/dsa/slave.c:1169:26: sparse: incorrect type in initializer (different argument counts)
From: kbuild test robot @ 2018-05-19 20:53 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git zii
head: 58e9ee3ee4dd4574170181ed8751766e234a33a8
commit: 94d9d1358684609c19eceb53aae76f40435b69dc [12/20] net: dsa: Plug in PHYLINK support
reproduce:
# apt-get install sparse
git checkout 94d9d1358684609c19eceb53aae76f40435b69dc
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
net/dsa/slave.c:434:13: sparse: incorrect type in initializer (different address spaces) @@ expected void const [noderef] <asn:3>*__vpp_verify @@ got const [noderef] <asn:3>*__vpp_verify @@
net/dsa/slave.c:434:13: expected void const [noderef] <asn:3>*__vpp_verify
net/dsa/slave.c:434:13: got struct pcpu_sw_netstats *<noident>
net/dsa/slave.c:550:16: sparse: undefined identifier 'phylink_ethtool_get_module_info'
net/dsa/slave.c:558:16: sparse: undefined identifier 'phylink_ethtool_get_module_eeprom'
net/dsa/slave.c:593:21: sparse: incorrect type in initializer (different address spaces) @@ expected void const [noderef] <asn:3>*__vpp_verify @@ got const [noderef] <asn:3>*__vpp_verify @@
net/dsa/slave.c:593:21: expected void const [noderef] <asn:3>*__vpp_verify
net/dsa/slave.c:593:21: got struct pcpu_sw_netstats *<noident>
net/dsa/slave.c:953:21: sparse: incorrect type in initializer (different address spaces) @@ expected void const [noderef] <asn:3>*__vpp_verify @@ got const [noderef] <asn:3>*__vpp_verify @@
net/dsa/slave.c:953:21: expected void const [noderef] <asn:3>*__vpp_verify
net/dsa/slave.c:953:21: got struct pcpu_sw_netstats *<noident>
>> net/dsa/slave.c:1169:26: sparse: incorrect type in initializer (different argument counts) @@ expected void ( *mac_link_down )( ... ) @@ got void ( *mac_link_down )( ... ) @@
net/dsa/slave.c:1169:26: expected void ( *mac_link_down )( ... )
net/dsa/slave.c:1169:26: got void ( *<noident> )( ... )
>> net/dsa/slave.c:1170:24: sparse: incorrect type in initializer (incompatible argument 3 (different base types)) @@ expected void ( *mac_link_up )( ... ) @@ got void ( *mac_link_up )( ... ) @@
net/dsa/slave.c:1170:24: expected void ( *mac_link_up )( ... )
net/dsa/slave.c:1170:24: got void ( *<noident> )( ... )
net/dsa/slave.c:1332:20: sparse: incorrect type in assignment (different address spaces) @@ expected struct pcpu_sw_netstats *stats64 @@ got struct pcpu_sw_nestruct pcpu_sw_netstats *stats64 @@
net/dsa/slave.c:1332:20: expected struct pcpu_sw_netstats *stats64
net/dsa/slave.c:1332:20: got struct pcpu_sw_netstats [noderef] <asn:3>*pcpu_stats
net/dsa/slave.c:1365:22: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:3>*__pdata @@ got stvoid [noderef] <asn:3>*__pdata @@
net/dsa/slave.c:1365:22: expected void [noderef] <asn:3>*__pdata
net/dsa/slave.c:1365:22: got struct pcpu_sw_netstats *stats64
net/dsa/slave.c:1382:22: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:3>*__pdata @@ got stvoid [noderef] <asn:3>*__pdata @@
net/dsa/slave.c:1382:22: expected void [noderef] <asn:3>*__pdata
net/dsa/slave.c:1382:22: got struct pcpu_sw_netstats *stats64
net/dsa/slave.c:550:47: sparse: call with no type!
net/dsa/slave.c:558:49: sparse: call with no type!
net/dsa/slave.c: In function 'dsa_slave_get_module_info':
net/dsa/slave.c:550:9: error: implicit declaration of function 'phylink_ethtool_get_module_info'; did you mean 'phylink_ethtool_get_pauseparam'? [-Werror=implicit-function-declaration]
return phylink_ethtool_get_module_info(dp->pl, modinfo);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
phylink_ethtool_get_pauseparam
net/dsa/slave.c: In function 'dsa_slave_get_module_eeprom':
net/dsa/slave.c:558:9: error: implicit declaration of function 'phylink_ethtool_get_module_eeprom'; did you mean 'phylink_ethtool_get_pauseparam'? [-Werror=implicit-function-declaration]
return phylink_ethtool_get_module_eeprom(dp->pl, ee, buf);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
phylink_ethtool_get_pauseparam
net/dsa/slave.c: At top level:
net/dsa/slave.c:1169:19: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.mac_link_down = dsa_slave_phylink_mac_link_down,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net/dsa/slave.c:1169:19: note: (near initialization for 'dsa_slave_phylink_mac_ops.mac_link_down')
net/dsa/slave.c:1170:17: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.mac_link_up = dsa_slave_phylink_mac_link_up,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net/dsa/slave.c:1170:17: note: (near initialization for 'dsa_slave_phylink_mac_ops.mac_link_up')
cc1: some warnings being treated as errors
vim +1169 net/dsa/slave.c
1163
1164 static const struct phylink_mac_ops dsa_slave_phylink_mac_ops = {
1165 .validate = dsa_slave_phylink_validate,
1166 .mac_link_state = dsa_slave_phylink_mac_link_state,
1167 .mac_config = dsa_slave_phylink_mac_config,
1168 .mac_an_restart = dsa_slave_phylink_mac_an_restart,
> 1169 .mac_link_down = dsa_slave_phylink_mac_link_down,
> 1170 .mac_link_up = dsa_slave_phylink_mac_link_up,
1171 };
1172
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [arm:zii 12/20] net//dsa/slave.c:1169:19: error: initialization from incompatible pointer type
From: kbuild test robot @ 2018-05-19 19:42 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git zii
head: 58e9ee3ee4dd4574170181ed8751766e234a33a8
commit: 94d9d1358684609c19eceb53aae76f40435b69dc [12/20] net: dsa: Plug in PHYLINK support
config: i386-randconfig-x012-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
git checkout 94d9d1358684609c19eceb53aae76f40435b69dc
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
net//dsa/slave.c: In function 'dsa_slave_get_module_info':
net//dsa/slave.c:550:9: error: implicit declaration of function 'phylink_ethtool_get_module_info'; did you mean 'phylink_ethtool_get_pauseparam'? [-Werror=implicit-function-declaration]
return phylink_ethtool_get_module_info(dp->pl, modinfo);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
phylink_ethtool_get_pauseparam
net//dsa/slave.c: In function 'dsa_slave_get_module_eeprom':
net//dsa/slave.c:558:9: error: implicit declaration of function 'phylink_ethtool_get_module_eeprom'; did you mean 'phylink_ethtool_get_pauseparam'? [-Werror=implicit-function-declaration]
return phylink_ethtool_get_module_eeprom(dp->pl, ee, buf);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
phylink_ethtool_get_pauseparam
net//dsa/slave.c: At top level:
>> net//dsa/slave.c:1169:19: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.mac_link_down = dsa_slave_phylink_mac_link_down,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net//dsa/slave.c:1169:19: note: (near initialization for 'dsa_slave_phylink_mac_ops.mac_link_down')
net//dsa/slave.c:1170:17: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.mac_link_up = dsa_slave_phylink_mac_link_up,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net//dsa/slave.c:1170:17: note: (near initialization for 'dsa_slave_phylink_mac_ops.mac_link_up')
cc1: some warnings being treated as errors
vim +1169 net//dsa/slave.c
1163
1164 static const struct phylink_mac_ops dsa_slave_phylink_mac_ops = {
1165 .validate = dsa_slave_phylink_validate,
1166 .mac_link_state = dsa_slave_phylink_mac_link_state,
1167 .mac_config = dsa_slave_phylink_mac_config,
1168 .mac_an_restart = dsa_slave_phylink_mac_an_restart,
> 1169 .mac_link_down = dsa_slave_phylink_mac_link_down,
1170 .mac_link_up = dsa_slave_phylink_mac_link_up,
1171 };
1172
---
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* [xlnx:xlnx_rebase_v4.14 730/935] drivers/crypto/zynqmp-sha.c:133:3: error: implicit declaration of function '__flush_cache_user_range'; did you mean 'clflush_cache_range'?
From: kbuild test robot @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v4.14
head: 6b8ad2b85bb2279d13a436396238f0fd150138d1
commit: 5cccc03f86f27a3e9e76ba7a863eaf2f8506e9e2 [730/935] crypto: zynqmp: Use new firmware ops
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
git checkout 5cccc03f86f27a3e9e76ba7a863eaf2f8506e9e2
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/crypto/zynqmp-sha.c: In function 'zynqmp_sha_update':
>> drivers/crypto/zynqmp-sha.c:133:3: error: implicit declaration of function '__flush_cache_user_range'; did you mean 'clflush_cache_range'? [-Werror=implicit-function-declaration]
__flush_cache_user_range((unsigned long)kbuf,
^~~~~~~~~~~~~~~~~~~~~~~~
clflush_cache_range
cc1: some warnings being treated as errors
vim +133 drivers/crypto/zynqmp-sha.c
3abec383 Nava kishore Manne 2017-09-19 111
3abec383 Nava kishore Manne 2017-09-19 112 static int zynqmp_sha_update(struct ahash_request *req)
3abec383 Nava kishore Manne 2017-09-19 113 {
3abec383 Nava kishore Manne 2017-09-19 114 struct zynqmp_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
3abec383 Nava kishore Manne 2017-09-19 115 struct zynqmp_sha_dev *dd = tctx->dd;
5cccc03f Rajan Vaja 2018-03-01 116 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
3abec383 Nava kishore Manne 2017-09-19 117 char *kbuf;
3abec383 Nava kishore Manne 2017-09-19 118 size_t dma_size = req->nbytes;
3abec383 Nava kishore Manne 2017-09-19 119 dma_addr_t dma_addr;
3abec383 Nava kishore Manne 2017-09-19 120 int ret;
3abec383 Nava kishore Manne 2017-09-19 121
3abec383 Nava kishore Manne 2017-09-19 122 if (!req->nbytes)
3abec383 Nava kishore Manne 2017-09-19 123 return 0;
3abec383 Nava kishore Manne 2017-09-19 124
5cccc03f Rajan Vaja 2018-03-01 125 if (!eemi_ops || !eemi_ops->sha_hash)
5cccc03f Rajan Vaja 2018-03-01 126 return -ENOTSUPP;
5cccc03f Rajan Vaja 2018-03-01 127
3abec383 Nava kishore Manne 2017-09-19 128 kbuf = dma_alloc_coherent(dd->dev, dma_size, &dma_addr, GFP_KERNEL);
3abec383 Nava kishore Manne 2017-09-19 129 if (!kbuf)
3abec383 Nava kishore Manne 2017-09-19 130 return -ENOMEM;
3abec383 Nava kishore Manne 2017-09-19 131
3abec383 Nava kishore Manne 2017-09-19 132 scatterwalk_map_and_copy(kbuf, req->src, 0, req->nbytes, 0);
3abec383 Nava kishore Manne 2017-09-19 @133 __flush_cache_user_range((unsigned long)kbuf,
3abec383 Nava kishore Manne 2017-09-19 134 (unsigned long)kbuf + dma_size);
5cccc03f Rajan Vaja 2018-03-01 135 ret = eemi_ops->sha_hash(dma_addr, req->nbytes, ZYNQMP_SHA3_UPDATE);
3abec383 Nava kishore Manne 2017-09-19 136 dma_free_coherent(dd->dev, dma_size, kbuf, dma_addr);
3abec383 Nava kishore Manne 2017-09-19 137
3abec383 Nava kishore Manne 2017-09-19 138 return ret;
3abec383 Nava kishore Manne 2017-09-19 139 }
3abec383 Nava kishore Manne 2017-09-19 140
:::::: The code at line 133 was first introduced by commit
:::::: 3abec3839538ef5fe79c2873360d84cc92b4df25 crypto: zynqmp-sha: Adopted SHA3 support for ZynqMP Soc
:::::: TO: Nava kishore Manne <nava.manne@xilinx.com>
:::::: CC: Michal Simek <michal.simek@xilinx.com>
---
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* [PATCH 15/15] ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Since HDMI can be considered as main output, most capable mixer is
connected to it (mixer0).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 27d9ccd0ef2f..66b492ad5847 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -58,6 +58,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -93,6 +104,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -101,6 +116,22 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_tcon_tv0: endpoint {
+ remote-endpoint = <&tcon_tv0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -161,6 +192,12 @@
regulator-name = "vcc-wifi";
};
+&mixer0_out {
+ mixer0_out_tcon_tv0: endpoint {
+ remote-endpoint = <&tcon_tv0_in_mixer0>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
@@ -195,6 +232,19 @@
status = "okay";
};
+&tcon_tv0_in {
+ tcon_tv0_in_mixer0: endpoint {
+ remote-endpoint = <&mixer0_out_tcon_tv0>;
+ };
+};
+
+&tcon_tv0_out {
+ tcon_tv0_out_hdmi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon_tv0>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
2.17.0
^ permalink raw reply related
* [PATCH 14/15] ARM: dts: sun8i: r40: Add HDMI pipeline
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Add all entries needed for HDMI to function properly.
Since R40 has highly configurable pipeline, both mixers and both TCON
TVs are added. Board specific DT should then connect them together to
best fit the purpose of the board.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 166 +++++++++++++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 173dcc1652d2..6d5407964997 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -42,8 +42,11 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
#address-cells = <1>;
@@ -99,12 +102,70 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-r40-display-engine",
+ "allwinner,sun8i-h3-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ display_clocks: clock at 1000000 {
+ compatible = "allwinner,sun8i-r40-de2-clk",
+ "allwinner,sun8i-h3-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer at 1100000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-0";
+ reg = <0x01100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ mixer1: mixer at 1200000 {
+ compatible = "allwinner,sun8i-r40-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
nmi_intc: interrupt-controller at 1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@@ -451,6 +512,70 @@
#size-cells = <0>;
};
+ tcon_top: tcon-top at 1c70000 {
+ compatible = "allwinner,sun8i-r40-tcon-top";
+ reg = <0x01c70000 0x1000>;
+ clocks = <&ccu CLK_BUS_TCON_TOP>;
+ clock-names = "bus";
+ resets = <&ccu RST_BUS_TCON_TOP>;
+ reset-names = "rst";
+ #clock-cells = <1>;
+ };
+
+ tcon_tv0: lcd-controller at 1c73000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv-0";
+ reg = <0x01c73000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&ccu CLK_TCON_TV0>,
+ <&tcon_top 1>;
+ clock-names = "ahb", "tcon-ch1", "tcon-top";
+ resets = <&ccu RST_BUS_TCON_TV0>;
+ reset-names = "lcd";
+ allwinner,tcon-top = <&tcon_top>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port at 0 {
+ reg = <0>;
+ };
+
+ tcon_tv0_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon_tv1: lcd-controller at 1c74000 {
+ compatible = "allwinner,sun8i-r40-tcon-tv-1";
+ reg = <0x01c74000 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&ccu CLK_TCON_TV1>,
+ <&tcon_top 2>;
+ clock-names = "ahb", "tcon-ch1", "tcon-top";
+ resets = <&ccu RST_BUS_TCON_TV1>;
+ reset-names = "lcd";
+ allwinner,tcon-top = <&tcon_top>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv1_in: port at 0 {
+ reg = <0>;
+ };
+
+ tcon_tv1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
gic: interrupt-controller at 1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
@@ -461,6 +586,47 @@
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+
+ hdmi: hdmi at 1ee0000 {
+ compatible = "allwinner,sun8i-r40-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port at 0 {
+ reg = <0>;
+ };
+
+ hdmi_out: port at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy at 1ef0000 {
+ compatible = "allwinner,sun8i-r40-hdmi-phy",
+ "allwinner,sun50i-a64-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu 7>, <&ccu 16>;
+ clock-names = "bus", "mod", "pll-0", "pll-1";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
};
timer {
--
2.17.0
^ permalink raw reply related
* [PATCH 13/15] drm/sun4i: Add support for A64 HDMI PHY
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
PHY is the same as in H3, except it can switch between two clock
parents.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 7a911f0a3ae3..0c9d67bb1007 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -396,6 +396,14 @@ static struct regmap_config sun8i_hdmi_phy_regmap_config = {
.name = "phy"
};
+static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
+ .has_phy_clk = true,
+ .has_second_pll = true,
+ .phy_init = &sun8i_hdmi_phy_init_h3,
+ .phy_disable = &sun8i_hdmi_phy_disable_h3,
+ .phy_config = &sun8i_hdmi_phy_config_h3,
+};
+
static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
.phy_init = &sun8i_hdmi_phy_init_a83t,
.phy_disable = &sun8i_hdmi_phy_disable_a83t,
@@ -410,6 +418,10 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
};
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+ {
+ .compatible = "allwinner,sun50i-a64-hdmi-phy",
+ .data = &sun50i_a64_hdmi_phy,
+ },
{
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
.data = &sun8i_a83t_hdmi_phy,
--
2.17.0
^ permalink raw reply related
* [PATCH 12/15] drm/sun4i: Add support for second clock parent to DW HDMI PHY clk driver
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 6 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 29 ++++++-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 90 ++++++++++++++++------
3 files changed, 98 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 801a17222762..aadbe0a10b0c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -98,7 +98,8 @@
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
-#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL BIT(26)
+#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
+#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
@@ -190,6 +191,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
-int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev);
+int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
+ bool second_parent);
#endif /* _SUN8I_DW_HDMI_H_ */
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index deba47ed69d8..7a911f0a3ae3 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
- regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
+ /*
+ * NOTE: We have to be careful not to overwrite PHY parent
+ * clock selection bit and clock divider.
+ */
+ regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
+ ~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
+ pll_cfg1_init);
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
(u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
pll_cfg2_init);
@@ -352,6 +358,10 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
+ /* reset PLL clock configuration */
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
+ regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, 0);
+
/* set HW control of CEC pins */
regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
@@ -481,18 +491,28 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
}
}
- ret = sun8i_phy_clk_create(phy, dev);
+ ret = sun8i_phy_clk_create(phy, dev,
+ phy->variant->has_second_pll);
if (ret) {
dev_err(dev, "Couldn't create the PHY clock\n");
goto err_put_clk_pll1;
}
+
+ /*
+ * Even though HDMI PHY clock doesn't have enable/disable
+ * handlers, we have to enable it. Otherwise it could happen
+ * that parent PLL is not enabled by clock framework in a
+ * highly unlikely event when parent PLL is used solely for
+ * HDMI PHY clock.
+ */
+ clk_prepare_enable(phy->clk_phy);
}
phy->rst_phy = of_reset_control_get_shared(node, "phy");
if (IS_ERR(phy->rst_phy)) {
dev_err(dev, "Could not get phy reset control\n");
ret = PTR_ERR(phy->rst_phy);
- goto err_put_clk_pll1;
+ goto err_disable_clk_phy;
}
ret = reset_control_deassert(phy->rst_phy);
@@ -523,6 +543,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
reset_control_assert(phy->rst_phy);
err_put_rst_phy:
reset_control_put(phy->rst_phy);
+err_disable_clk_phy:
+ clk_disable_unprepare(phy->clk_phy);
err_put_clk_pll1:
clk_put(phy->clk_pll1);
err_put_clk_pll0:
@@ -541,6 +563,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
clk_disable_unprepare(phy->clk_mod);
clk_disable_unprepare(phy->clk_bus);
+ clk_disable_unprepare(phy->clk_phy);
reset_control_assert(phy->rst_phy);
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
index faea449812f8..a4d31fe3abff 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c
@@ -22,35 +22,45 @@ static int sun8i_phy_clk_determine_rate(struct clk_hw *hw,
{
unsigned long rate = req->rate;
unsigned long best_rate = 0;
+ struct clk_hw *best_parent = NULL;
struct clk_hw *parent;
int best_div = 1;
- int i;
+ int i, p;
- parent = clk_hw_get_parent(hw);
-
- for (i = 1; i <= 16; i++) {
- unsigned long ideal = rate * i;
- unsigned long rounded;
-
- rounded = clk_hw_round_rate(parent, ideal);
+ for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
+ parent = clk_hw_get_parent_by_index(hw, p);
+ if (!parent)
+ continue;
- if (rounded == ideal) {
- best_rate = rounded;
- best_div = i;
- break;
+ for (i = 1; i <= 16; i++) {
+ unsigned long ideal = rate * i;
+ unsigned long rounded;
+
+ rounded = clk_hw_round_rate(parent, ideal);
+
+ if (rounded == ideal) {
+ best_rate = rounded;
+ best_div = i;
+ best_parent = parent;
+ break;
+ }
+
+ if (!best_rate ||
+ abs(rate - rounded / i) <
+ abs(rate - best_rate / best_div)) {
+ best_rate = rounded;
+ best_div = i;
+ best_parent = parent;
+ }
}
- if (!best_rate ||
- abs(rate - rounded / i) <
- abs(rate - best_rate / best_div)) {
- best_rate = rounded;
- best_div = i;
- }
+ if (best_rate / best_div == rate)
+ break;
}
req->rate = best_rate / best_div;
req->best_parent_rate = best_rate;
- req->best_parent_hw = parent;
+ req->best_parent_hw = best_parent;
return 0;
}
@@ -95,22 +105,58 @@ static int sun8i_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
+static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)
+{
+ struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
+ u32 reg;
+
+ regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, ®);
+ reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
+ SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;
+
+ return reg;
+}
+
+static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
+
+ if (index > 1)
+ return -EINVAL;
+
+ regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
+ SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
+ index << SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT);
+
+ return 0;
+}
+
static const struct clk_ops sun8i_phy_clk_ops = {
.determine_rate = sun8i_phy_clk_determine_rate,
.recalc_rate = sun8i_phy_clk_recalc_rate,
.set_rate = sun8i_phy_clk_set_rate,
+
+ .get_parent = sun8i_phy_clk_get_parent,
+ .set_parent = sun8i_phy_clk_set_parent,
};
-int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev)
+int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
+ bool second_parent)
{
struct clk_init_data init;
struct sun8i_phy_clk *priv;
- const char *parents[1];
+ const char *parents[2];
parents[0] = __clk_get_name(phy->clk_pll0);
if (!parents[0])
return -ENODEV;
+ if (second_parent) {
+ parents[1] = __clk_get_name(phy->clk_pll1);
+ if (!parents[1])
+ return -ENODEV;
+ }
+
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
@@ -118,7 +164,7 @@ int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev)
init.name = "hdmi-phy-clk";
init.ops = &sun8i_phy_clk_ops;
init.parent_names = parents;
- init.num_parents = 1;
+ init.num_parents = second_parent ? 2 : 1;
init.flags = CLK_SET_RATE_PARENT;
priv->phy = phy;
--
2.17.0
^ permalink raw reply related
* [PATCH 11/15] drm/sun4i: DW HDMI PHY: Add support for second PLL
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Some DW HDMI PHYs like those found in A64 and R40 SoCs, can select
between two clock parents.
Add code which reads second PLL from DT.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 22 ++++++++++++++++------
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 79154f0f674a..801a17222762 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -147,6 +147,7 @@ struct sun8i_hdmi_phy;
struct sun8i_hdmi_phy_variant {
bool has_phy_clk;
+ bool has_second_pll;
void (*phy_init)(struct sun8i_hdmi_phy *phy);
void (*phy_disable)(struct dw_hdmi *hdmi,
struct sun8i_hdmi_phy *phy);
@@ -160,6 +161,7 @@ struct sun8i_hdmi_phy {
struct clk *clk_mod;
struct clk *clk_phy;
struct clk *clk_pll0;
+ struct clk *clk_pll1;
unsigned int rcal;
struct regmap *regs;
struct reset_control *rst_phy;
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index 5a52fc489a9d..deba47ed69d8 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -472,10 +472,19 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
goto err_put_clk_mod;
}
+ if (phy->variant->has_second_pll) {
+ phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
+ if (IS_ERR(phy->clk_pll1)) {
+ dev_err(dev, "Could not get pll-1 clock\n");
+ ret = PTR_ERR(phy->clk_pll1);
+ goto err_put_clk_pll0;
+ }
+ }
+
ret = sun8i_phy_clk_create(phy, dev);
if (ret) {
dev_err(dev, "Couldn't create the PHY clock\n");
- goto err_put_clk_pll0;
+ goto err_put_clk_pll1;
}
}
@@ -483,7 +492,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
if (IS_ERR(phy->rst_phy)) {
dev_err(dev, "Could not get phy reset control\n");
ret = PTR_ERR(phy->rst_phy);
- goto err_put_clk_pll0;
+ goto err_put_clk_pll1;
}
ret = reset_control_deassert(phy->rst_phy);
@@ -514,9 +523,10 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
reset_control_assert(phy->rst_phy);
err_put_rst_phy:
reset_control_put(phy->rst_phy);
+err_put_clk_pll1:
+ clk_put(phy->clk_pll1);
err_put_clk_pll0:
- if (phy->variant->has_phy_clk)
- clk_put(phy->clk_pll0);
+ clk_put(phy->clk_pll0);
err_put_clk_mod:
clk_put(phy->clk_mod);
err_put_clk_bus:
@@ -536,8 +546,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
reset_control_put(phy->rst_phy);
- if (phy->variant->has_phy_clk)
- clk_put(phy->clk_pll0);
+ clk_put(phy->clk_pll0);
+ clk_put(phy->clk_pll1);
clk_put(phy->clk_mod);
clk_put(phy->clk_bus);
}
--
2.17.0
^ permalink raw reply related
* [PATCH 10/15] drm/sun4i: Add support for R40 TV TCONs
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
R40 display pipeline has a lot of possible configurations. HDMI can be
connected to 2 different TCONs (out of 4) and mixers can be connected to
any TCON. All this must be configured in TCON TOP.
Along with definition of TCON capabilities also add mux callback, which
can configure this complex pipeline.
For now, only TCON TV is supported.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 39 ++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index e0c562ce1c22..81b9551e4f78 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -1274,6 +1274,31 @@ static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
return 0;
}
+static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder,
+ int index)
+{
+ if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
+ sun8i_tcon_top_set_hdmi_src(tcon->tcon_top, index);
+
+ sun8i_tcon_top_de_config(tcon->tcon_top, tcon->id,
+ tcon_type_tv, index);
+
+ return 0;
+}
+
+static int sun8i_r40_tcon_tv_set_mux_0(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder)
+{
+ return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 0);
+}
+
+static int sun8i_r40_tcon_tv_set_mux_1(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder)
+{
+ return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 1);
+}
+
static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
.has_channel_0 = true,
.has_channel_1 = true,
@@ -1321,6 +1346,18 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
.has_channel_1 = true,
};
+static const struct sun4i_tcon_quirks sun8i_r40_tv_0_quirks = {
+ .has_channel_1 = true,
+ .needs_tcon_top = true,
+ .set_mux = sun8i_r40_tcon_tv_set_mux_0,
+};
+
+static const struct sun4i_tcon_quirks sun8i_r40_tv_1_quirks = {
+ .has_channel_1 = true,
+ .needs_tcon_top = true,
+ .set_mux = sun8i_r40_tcon_tv_set_mux_1,
+};
+
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
.has_channel_0 = true,
};
@@ -1345,6 +1382,8 @@ const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
+ { .compatible = "allwinner,sun8i-r40-tcon-tv-0", .data = &sun8i_r40_tv_0_quirks },
+ { .compatible = "allwinner,sun8i-r40-tcon-tv-1", .data = &sun8i_r40_tv_1_quirks },
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
--
2.17.0
^ permalink raw reply related
* [PATCH 09/15] drm/sun4i: Add support for R40 mixers
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Both mixers have similar capabilities as others SoCs with DE2.
First mixer has 1 VI and 3 UI planes and supports HW scaling on all
planes.
Second mixer has 1 VI and 1 UI planes and also supports HW scaling on
all planes.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 36d90c76317a..78aa878e305c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -500,6 +500,24 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ .ccsc = 0,
+ .index = 0,
+ .mod_rate = 297000000,
+ .scaler_mask = 0xf,
+ .ui_num = 3,
+ .vi_num = 1,
+};
+
+static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
+ .ccsc = 1,
+ .index = 1,
+ .mod_rate = 297000000,
+ .scaler_mask = 0x3,
+ .ui_num = 1,
+ .vi_num = 1,
+};
+
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.vi_num = 2,
.ui_num = 1,
@@ -521,6 +539,14 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-h3-de2-mixer-0",
.data = &sun8i_h3_mixer0_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-r40-de2-mixer-0",
+ .data = &sun8i_r40_mixer0_cfg,
+ },
+ {
+ .compatible = "allwinner,sun8i-r40-de2-mixer-1",
+ .data = &sun8i_r40_mixer1_cfg,
+ },
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
--
2.17.0
^ permalink raw reply related
* [PATCH 08/15] drm/sun4i: DE2 mixer: Add index quirk
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
When TCON sets up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 126899d6f0d3..36d90c76317a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -353,13 +353,13 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
dev_set_drvdata(dev, mixer);
mixer->engine.ops = &sun8i_engine_ops;
mixer->engine.node = dev->of_node;
- /* The ID of the mixer currently doesn't matter */
- mixer->engine.id = -1;
mixer->cfg = of_device_get_match_data(dev);
if (!mixer->cfg)
return -EINVAL;
+ mixer->engine.id = mixer->cfg->index;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index f34e70c42adf..aeda6e9a7627 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -123,6 +123,7 @@ struct de2_fmt_info {
* are invalid.
* @mod_rate: module clock rate that needs to be set in order to have
* a functional block.
+ * @index: mixer index, needed to properly set TCON TOP
*/
struct sun8i_mixer_cfg {
int vi_num;
@@ -130,6 +131,7 @@ struct sun8i_mixer_cfg {
int scaler_mask;
int ccsc;
unsigned long mod_rate;
+ int index;
};
struct sun8i_mixer {
--
2.17.0
^ permalink raw reply related
* [PATCH 07/15] dt-bindings: display: sun4i-drm: Add R40 HDMI pipeline
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Missing compatibles and descriptions needed to implement R40 HDMI
pipeline are added.
For mixers only compatibles are added.
TCON description is expanded with R40 TV TCON compatibles. If the SoC
has TCON TOP unit, phandle to that unit has to be specified. Additional
clock has to be specified if SoC has TCON TOP and TCON is TV TCON.
New compatible is added for DWC HDMI PHY, which has additional clock
specified.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index a099957ab62a..634276f713e8 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -101,6 +101,7 @@ DWC HDMI PHY
Required properties:
- compatible: value must be one of:
+ * allwinner,sun50i-a64-hdmi-phy
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
- reg: base address and size of memory-mapped region
@@ -111,8 +112,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 HDMI PHY requires additional clock:
+H3 and A64 HDMI PHY requires additional clocks:
- pll-0: parent of phy clock
+ - pll-1: second possible phy clock parent (A64 only)
TV Encoder
----------
@@ -145,6 +147,8 @@ Required properties:
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
* allwinner,sun8i-a83t-tcon-tv
+ * allwinner,sun8i-r40-tcon-tv-0
+ * allwinner,sun8i-r40-tcon-tv-1
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
@@ -179,7 +183,7 @@ For TCONs with channel 0, there is one more clock required:
For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
@@ -187,6 +191,12 @@ And on the A23, A31, A31s and A33, you need one more clock line:
- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
clock, that can be used to drive the LVDS clock
+If SoC has TCON TOP, like R40, TCON has to have phandle to TCON TOP:
+ - 'allwinner,tcon-top': Phandle to TCON TOP unit
+
+TV TCONs which have phandle to TCON TOP need one more clock:
+ - 'tcon-top': TV TCON gate found in TCON TOP unit
+
TCON TOP
--------
@@ -330,6 +340,8 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-0
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
+ * allwinner,sun8i-r40-de2-mixer-0
+ * allwinner,sun8i-r40-de2-mixer-1
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
--
2.17.0
^ permalink raw reply related
* [PATCH 06/15] drm/sun4i: tcon: Add support for tcon-top
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
If SoC has TCON TOP unit, it has to be configured from TCON, since it
has all information needed. Additionally, if it is TCON TV, it must also
enable bus gate inside TCON TOP unit.
Add support for such TCONs.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 28 ++++++++++++++++++++++++++++
drivers/gpu/drm/sun4i/sun4i_tcon.h | 8 ++++++++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 08747fc3ee71..e0c562ce1c22 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -688,6 +688,16 @@ static int sun4i_tcon_init_clocks(struct device *dev,
dev_err(dev, "Couldn't get the TCON bus clock\n");
return PTR_ERR(tcon->clk);
}
+
+ if (tcon->quirks->needs_tcon_top && tcon->quirks->has_channel_1) {
+ tcon->top_clk = devm_clk_get(dev, "tcon-top");
+ if (IS_ERR(tcon->top_clk)) {
+ dev_err(dev, "Couldn't get the TCON TOP bus clock\n");
+ return PTR_ERR(tcon->top_clk);
+ }
+ clk_prepare_enable(tcon->top_clk);
+ }
+
clk_prepare_enable(tcon->clk);
if (tcon->quirks->has_channel_0) {
@@ -712,6 +722,7 @@ static int sun4i_tcon_init_clocks(struct device *dev,
static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
{
clk_disable_unprepare(tcon->clk);
+ clk_disable_unprepare(tcon->top_clk);
}
static int sun4i_tcon_init_irq(struct device *dev,
@@ -980,6 +991,23 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
tcon->id = engine->id;
tcon->quirks = of_device_get_match_data(dev);
+ if (tcon->quirks->needs_tcon_top) {
+ struct device_node *np;
+
+ np = of_parse_phandle(dev->of_node, "allwinner,tcon-top", 0);
+ if (np) {
+ struct platform_device *pdev;
+
+ pdev = of_find_device_by_node(np);
+ if (pdev)
+ tcon->tcon_top = platform_get_drvdata(pdev);
+ of_node_put(np);
+
+ if (!tcon->tcon_top)
+ return -EPROBE_DEFER;
+ }
+ }
+
tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
if (IS_ERR(tcon->lcd_rst)) {
dev_err(dev, "Couldn't get our reset line\n");
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index f6a071cd5a6f..26be0d317a38 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -20,6 +20,8 @@
#include <linux/list.h>
#include <linux/reset.h>
+#include "sun8i_tcon_top.h"
+
#define SUN4I_TCON_GCTL_REG 0x0
#define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31)
#define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
@@ -224,6 +226,7 @@ struct sun4i_tcon_quirks {
bool needs_de_be_mux; /* sun6i needs mux to select backend */
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
bool supports_lvds; /* Does the TCON support an LVDS output? */
+ bool needs_tcon_top; /* TCON TOP holds additional muxing configuration */
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
@@ -249,6 +252,9 @@ struct sun4i_tcon {
u8 dclk_max_div;
u8 dclk_min_div;
+ /* TCON TOP clock */
+ struct clk *top_clk;
+
/* Reset control */
struct reset_control *lcd_rst;
struct reset_control *lvds_rst;
@@ -263,6 +269,8 @@ struct sun4i_tcon {
int id;
+ struct sun8i_tcon_top *tcon_top;
+
/* TCON list management */
struct list_head list;
};
--
2.17.0
^ permalink raw reply related
* [PATCH 05/15] drm/sun4i: Add TCON TOP driver
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
As already described in DT binding, TCON TOP is responsible for
configuring display pipeline. In this initial driver focus is on HDMI
pipeline, so TVE and LCD configuration is not implemented.
Implemented features:
- HDMI source selection
- clock driver (TCON and DSI gating)
- connecting mixers and TCONS
Something similar also existed in previous SoCs, except that it was part
of first TCON.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 256 +++++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 20 ++
include/dt-bindings/clock/sun8i-tcon-top.h | 11 +
4 files changed, 289 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h
create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 2589f4acd5ae..09fbfd6304ba 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -16,7 +16,8 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o
sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
sun8i_vi_layer.o sun8i_ui_scaler.o \
- sun8i_vi_scaler.o sun8i_csc.o
+ sun8i_vi_scaler.o sun8i_csc.o \
+ sun8i_tcon_top.o
sun4i-tcon-y += sun4i_crtc.o
sun4i-tcon-y += sun4i_dotclock.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
new file mode 100644
index 000000000000..075a356a6dfa
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#include <drm/drmP.h>
+
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+#include "sun8i_tcon_top.h"
+
+#define TCON_TOP_PORT_SEL_REG 0x1C
+#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
+#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
+#define TCON_TOP_PORT_TCON_LCD0 0
+#define TCON_TOP_PORT_TCON_LCD1 1
+#define TCON_TOP_PORT_TCON_TV0 2
+#define TCON_TOP_PORT_TCON_TV1 3
+
+#define TCON_TOP_GATE_SRC_REG 0x20
+#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)
+#define TCON_TOP_HDMI_SRC_NONE 0
+#define TCON_TOP_HDMI_SRC_TCON_TV0 1
+#define TCON_TOP_HDMI_SRC_TCON_TV1 2
+#define TCON_TOP_TCON_TV1_GATE 24
+#define TCON_TOP_TCON_TV0_GATE 20
+#define TCON_TOP_TCON_DSI_GATE 16
+
+#define CLK_NUM 3
+
+struct sun8i_tcon_top {
+ struct clk *bus;
+ void __iomem *regs;
+ struct reset_control *rst;
+
+ /*
+ * spinlock is used for locking access to registers from different
+ * places - tcon driver and clk subsystem.
+ */
+ spinlock_t reg_lock;
+};
+
+struct sun8i_tcon_top_gate {
+ const char *name;
+ u8 bit;
+ int index;
+};
+
+static const struct sun8i_tcon_top_gate gates[] = {
+ {"bus-tcon-top-dsi", TCON_TOP_TCON_DSI_GATE, CLK_BUS_TCON_TOP_DSI},
+ {"bus-tcon-top-tv0", TCON_TOP_TCON_TV0_GATE, CLK_BUS_TCON_TOP_TV0},
+ {"bus-tcon-top-tv1", TCON_TOP_TCON_TV1_GATE, CLK_BUS_TCON_TOP_TV1},
+};
+
+void sun8i_tcon_top_set_hdmi_src(struct sun8i_tcon_top *tcon_top, int tcon)
+{
+ unsigned long flags;
+ u32 val;
+
+ if (tcon > 1) {
+ DRM_ERROR("TCON index is too high!\n");
+ return;
+ }
+
+ spin_lock_irqsave(&tcon_top->reg_lock, flags);
+
+ val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG);
+ val &= ~TCON_TOP_HDMI_SRC_MSK;
+ val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK,
+ TCON_TOP_HDMI_SRC_TCON_TV0 + tcon);
+ writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
+
+ spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
+}
+
+void sun8i_tcon_top_de_config(struct sun8i_tcon_top *tcon_top,
+ int mixer, enum tcon_type tcon_type, int tcon)
+{
+ unsigned long flags;
+ u32 val, reg;
+
+ if (mixer > 1) {
+ DRM_ERROR("Mixer index is too high!\n");
+ return;
+ }
+
+ if (tcon > 1) {
+ DRM_ERROR("TCON index is too high!\n");
+ return;
+ }
+
+ switch (tcon_type) {
+ case tcon_type_lcd:
+ val = TCON_TOP_PORT_TCON_LCD0 + tcon;
+ break;
+ case tcon_type_tv:
+ val = TCON_TOP_PORT_TCON_TV0 + tcon;
+ break;
+ default:
+ DRM_ERROR("Invalid TCON type!\n");
+ return;
+ }
+
+ spin_lock_irqsave(&tcon_top->reg_lock, flags);
+
+ reg = readl(tcon_top->regs + TCON_TOP_PORT_SEL_REG);
+ if (mixer == 0) {
+ reg &= ~TCON_TOP_PORT_DE0_MSK;
+ reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, val);
+ } else {
+ reg &= ~TCON_TOP_PORT_DE1_MSK;
+ reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, val);
+ }
+ writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
+
+ spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
+}
+
+static int sun8i_tcon_top_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct sun8i_tcon_top *tcon_top;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int ret, i;
+
+ tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
+ if (!tcon_top)
+ return -ENOMEM;
+
+ clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * CLK_NUM,
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ spin_lock_init(&tcon_top->reg_lock);
+
+ tcon_top->rst = devm_reset_control_get(dev, "rst");
+ if (IS_ERR(tcon_top->rst)) {
+ dev_err(dev, "Couldn't get our reset line\n");
+ return PTR_ERR(tcon_top->rst);
+ }
+
+ tcon_top->bus = devm_clk_get(dev, "bus");
+ if (IS_ERR(tcon_top->bus)) {
+ dev_err(dev, "Couldn't get the bus clock\n");
+ return PTR_ERR(tcon_top->bus);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ tcon_top->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(tcon_top->regs))
+ return PTR_ERR(tcon_top->regs);
+
+ ret = reset_control_deassert(tcon_top->rst);
+ if (ret) {
+ dev_err(dev, "Could not deassert ctrl reset control\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(tcon_top->bus);
+ if (ret) {
+ dev_err(dev, "Could not enable bus clock\n");
+ goto err_assert_reset;
+ }
+
+ /*
+ * Default register values might have some reserved bits set, which
+ * prevents TCON TOP from working properly. Set them to 0 here.
+ */
+ writel(0, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
+ writel(0, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
+
+ for (i = 0; i < CLK_NUM; i++) {
+ const char *parent_name = "bus-tcon-top";
+ struct clk_init_data init;
+ struct clk_gate *gate;
+
+ gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ ret = -ENOMEM;
+ goto err_disable_clock;
+ }
+
+ init.name = gates[i].name;
+ init.ops = &clk_gate_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ gate->reg = tcon_top->regs + TCON_TOP_GATE_SRC_REG;
+ gate->bit_idx = gates[i].bit;
+ gate->lock = &tcon_top->reg_lock;
+ gate->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &gate->hw);
+ if (ret)
+ goto err_disable_clock;
+
+ clk_data->hws[gates[i].index] = &gate->hw;
+ }
+
+ clk_data->num = CLK_NUM;
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+ if (ret)
+ goto err_disable_clock;
+
+ platform_set_drvdata(pdev, tcon_top);
+
+ return 0;
+
+err_disable_clock:
+ clk_disable_unprepare(tcon_top->bus);
+err_assert_reset:
+ reset_control_assert(tcon_top->rst);
+
+ return ret;
+}
+
+static int sun8i_tcon_top_remove(struct platform_device *pdev)
+{
+ struct sun8i_tcon_top *tcon_top = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(tcon_top->bus);
+ reset_control_assert(tcon_top->rst);
+
+ return 0;
+}
+
+const struct of_device_id sun8i_tcon_top_of_table[] = {
+ { .compatible = "allwinner,sun8i-r40-tcon-top" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
+
+static struct platform_driver sun8i_tcon_top_platform_driver = {
+ .probe = sun8i_tcon_top_probe,
+ .remove = sun8i_tcon_top_remove,
+ .driver = {
+ .name = "sun8i-tcon-top",
+ .of_match_table = sun8i_tcon_top_of_table,
+ },
+};
+module_platform_driver(sun8i_tcon_top_platform_driver);
+
+MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
+MODULE_DESCRIPTION("Allwinner R40 TCON TOP driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.h b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
new file mode 100644
index 000000000000..19126e07d2a6
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _SUN8I_TCON_TOP_H_
+#define _SUN8I_TCON_TOP_H_
+
+#include <linux/device.h>
+
+struct sun8i_tcon_top;
+
+enum tcon_type {
+ tcon_type_lcd,
+ tcon_type_tv,
+};
+
+void sun8i_tcon_top_set_hdmi_src(struct sun8i_tcon_top *tcon_top, int tcon);
+void sun8i_tcon_top_de_config(struct sun8i_tcon_top *tcon_top,
+ int mixer, enum tcon_type tcon_type, int tcon);
+
+#endif /* _SUN8I_TCON_TOP_H_ */
diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
new file mode 100644
index 000000000000..c05e92770402
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_BUS_TCON_TOP_DSI 0
+#define CLK_BUS_TCON_TOP_TV0 1
+#define CLK_BUS_TCON_TOP_TV1 2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
--
2.17.0
^ permalink raw reply related
* [PATCH 04/15] dt-bindings: display: sunxi-drm: Add TCON TOP description
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
TCON TOP main purpose is to configure whole display pipeline. It
determines relationships between mixers and TCONs, selects source TCON
for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder
clock source and contains additional TV TCON and DSI gates.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 3346c1e2a7a0..a099957ab62a 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -187,6 +187,26 @@ And on the A23, A31, A31s and A33, you need one more clock line:
- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
clock, that can be used to drive the LVDS clock
+TCON TOP
+--------
+
+TCON TOPs main purpose is to configure whole display pipeline. It determines
+relationships between mixers and TCONs, selects source TCON for HDMI, muxes
+LCD and TV encoder GPIO output, selects TV encoder clock source and contains
+additional TV TCON and DSI gates.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-r40-tcon-top
+ - reg: base address and size of the memory-mapped region.
+ - clocks: phandle to the clocks feeding the TCON TOP
+ * bus: TCON TOP interface clock
+ - clock-names: clock name mentioned above
+ - resets: phandle to the reset line driving the DRC
+ * rst: TCON TOP reset line
+ - reset-names: reset name mentioned above
+ - #clock-cells : must contain 1
+
DRC
---
--
2.17.0
^ permalink raw reply related
* [PATCH 03/15] clk: sunxi-ng: r40: Export video PLLs
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
Export them.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 ++++++--
include/dt-bindings/clock/sun8i-r40-ccu.h | 4 ++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
index 0db8e1e97af8..db2a1243f9ff 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
@@ -25,7 +25,9 @@
#define CLK_PLL_AUDIO_2X 4
#define CLK_PLL_AUDIO_4X 5
#define CLK_PLL_AUDIO_8X 6
-#define CLK_PLL_VIDEO0 7
+
+/* PLL_VIDEO0 is exported */
+
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VE 9
#define CLK_PLL_DDR0 10
@@ -34,7 +36,9 @@
#define CLK_PLL_PERIPH0_2X 13
#define CLK_PLL_PERIPH1 14
#define CLK_PLL_PERIPH1_2X 15
-#define CLK_PLL_VIDEO1 16
+
+/* PLL_VIDEO1 is exported */
+
#define CLK_PLL_VIDEO1_2X 17
#define CLK_PLL_SATA 18
#define CLK_PLL_SATA_OUT 19
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
index 4fa5f69fc297..f9e15a235626 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -43,6 +43,10 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define CLK_PLL_VIDEO0 7
+
+#define CLK_PLL_VIDEO1 16
+
#define CLK_CPU 24
#define CLK_BUS_MIPI_DSI 29
--
2.17.0
^ permalink raw reply related
* [PATCH 02/15] clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
From: Jernej Skrabec @ 2018-05-19 18:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519183127.2718-1-jernej.skrabec@siol.net>
Display related peripherals need precise clocks to operate correctly.
Allow DE2, TCONs and HDMI to set parent clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index c16a62a7bdbd..fa5317719684 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -655,7 +655,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
- 0x104, 0, 4, 24, 3, BIT(31), 0);
+ 0x104, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
0x108, 0, 4, 24, 3, BIT(31), 0);
@@ -667,9 +668,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
- 0x118, 0, 4, 24, 3, BIT(31), 0);
+ 0x118, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
- 0x11c, 0, 4, 24, 3, BIT(31), 0);
+ 0x11c, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-periph0",
"pll-periph1" };
@@ -699,7 +702,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
- 0x150, 0, 4, 24, 2, BIT(31), 0);
+ 0x150, 0, 4, 24, 2, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
0x154, BIT(31), 0);
--
2.17.0
^ permalink raw reply related
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