* [PATCH v6 3/9] docs: Add Generic Counter interface documentation
From: William Breathitt Gray @ 2018-05-21 13:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180520163109.22b11af8@archlinux>
On Sun, May 20, 2018 at 04:31:09PM +0100, Jonathan Cameron wrote:
>On Wed, 16 May 2018 13:51:06 -0400
>William Breathitt Gray <vilhelm.gray@gmail.com> wrote:
>
>> This patch adds high-level documentation about the Generic Counter
>> interface.
>>
>> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
>
>Various comments inline. I've been doing a lot long reviews recently
>(outside of the kernel world) and keep discovering the old rule that
>everytime you read a document you'll find something else to
>improve :(
>
>Jonathan
But it is good too to have multiple eyes on this -- I have found as an
author my brain tends to skip over minor errors while rereading
passages, so having persons reading it for both the first and subsequent
times helps catch those mistakes I may have overlooked in my mind. :)
>> ---
>> Documentation/driver-api/generic-counter.rst | 336 +++++++++++++++++++
>> Documentation/driver-api/index.rst | 1 +
>> MAINTAINERS | 1 +
>> 3 files changed, 338 insertions(+)
>> create mode 100644 Documentation/driver-api/generic-counter.rst
>>
>> diff --git a/Documentation/driver-api/generic-counter.rst b/Documentation/driver-api/generic-counter.rst
>> new file mode 100644
>> index 000000000000..5c6b9c008c06
>> --- /dev/null
>> +++ b/Documentation/driver-api/generic-counter.rst
>> @@ -0,0 +1,336 @@
>> +.. SPDX-License-Identifier: GPL-2.0
>> +
>> +=========================
>> +Generic Counter Interface
>> +=========================
>> +
>> +Introduction
>> +============
>> +
>> +Counter devices are prevalent within a diverse spectrum of industries.
>> +The ubiquitous presence of these devices necessitates a common interface
>> +and standard of interaction and exposure. This driver API attempts to
>> +resolve the issue of duplicate code found among existing counter device
>> +drivers by introducing a generic counter interface for consumption. The
>> +Generic Counter interface enables drivers to support and expose a common
>> +set of components and functionality present in counter devices.
>> +
>> +Theory
>> +======
>> +
>> +Counter devices can vary greatly in design, but regardless of whether
>> +some devices are quadrature encoder counters or tally counters, all
>> +counter devices consist of a core set of components. This core set of
>> +components, shared by all counter devices, is what forms the essence of
>> +the Generic Counter interface.
>> +
>> +There are three core components to a counter:
>
>Enumerate them here. If people are reading this as a paged document (pdf etc)
>then the list of 3 as titles of next few sections may not be clear.
>
>* Count
>
>* Signal
>
>* Synapse
>
>> +
>> +COUNT
>> +-----
>> +A Count represents the count data for a set of Signals. The Generic
>> +Counter interface provides the following available count data types:
>> +
>> +* COUNT_POSITION_UNSIGNED:
>> + Unsigned integer value representing position.
>> +
>> +* COUNT_POSITION_SIGNED:
>> + Signed integer value representing position.
>
>Just a thought: As the '0' position is effectively arbitrary is there any
>actual difference between signed and unsigned? If we defined all counters
>to be unsigned and just offset any signed ones so the range still fitted
>would we end up with a simpler interface - there would be no real loss
>of meaning that I can see.. I suppose it might not be what people expect
>though when they see their counters start at a large positive value...
This is something I've been on the fence about for a while. I would
actually prefer the interface to have simply a COUNT_POSITION data type
to represent position and leave it as unsigned; distinguishing between
signed and unsigned position seems ultimately arbitrary given that it's
mathematically just an offset as you have pointed out.
If we were to go down this route, then we'd have a count value that may
always be represented using an unsigned data type, with an offset value
that may always be represented using a signed data type -- the
relationship being such: position = count + offset. Is that correct?
My reason for giving the option for either signed or unsigned position
was to help minimize the work userspace would have to do in order to get
the value in which they're actually interested. I suppose it was a
question of how abstract I want to make the interface -- although,
making it simpler for userspace put more of a burden on the kernel side.
However, the "offset" value route may actually be more robust in the end
because userspace would have to know whether they want a signed or
unsigned position regardless in order to parse, so with count and offet
defined we know they will always be unsigned and signed respectively.
>
>
>
>
>> +
>> +A Count has a count function mode which represents the update behavior
>> +for the count data. The Generic Counter interface provides the following
>> +available count function modes:
>> +
>> +* Increase:
>> + Accumulated count is incremented.
>> +
>> +* Decrease:
>> + Accumulated count is decremented.
>> +
>> +* Pulse-Direction:
>> + Rising edges on quadrature pair signal A updates the respective count.
>> + The input level of quadrature pair signal B determines direction.
>> +
>Perhaps group the quadrature modes for the point of view of this document?
>Might be slightly easier to read?
>
>* Quadrature Modes
>
> - x1 A: etc.
>
>> +* Quadrature x1 A:
>> + If direction is forward, rising edges on quadrature pair signal A
>> + updates the respective count; if the direction is backward, falling
>> + edges on quadrature pair signal A updates the respective count.
>> + Quadrature encoding determines the direction.
>> +
>> +* Quadrature x1 B:
>> + If direction is forward, rising edges on quadrature pair signal B
>> + updates the respective count; if the direction is backward, falling
>> + edges on quadrature pair signal B updates the respective count.
>> + Quadrature encoding determines the direction.
>> +
>> +* Quadrature x2 A:
>> + Any state transition on quadrature pair signal A updates the
>> + respective count. Quadrature encoding determines the direction.
>> +
>> +* Quadrature x2 B:
>> + Any state transition on quadrature pair signal B updates the
>> + respective count. Quadrature encoding determines the direction.
>> +
>> +* Quadrature x2 Rising:
>> + Rising edges on either quadrature pair signals updates the respective
>> + count. Quadrature encoding determines the direction.
>
>This one I've never met. Really? There are devices who do this form
>of crazy? It gives really uneven counting and I'm failing to see when
>it would ever make sense... References for these odd corner cases
>would be good.
>
>
>__|---|____|-----|____
>____|----|____|-----|____
>
>001122222223334444444
That's the same reaction I had when I discovered this -- in fact the
STM32 LP Timer is the first time I've come across such a quadrature
mode. I'm not sure of the use case for this mode, because positioning
wouldn't be precise as you've pointed out. Perhaps Fabrice or Benjamin
can probe the ST guys responsible for this design choice to figure out
the rationale.
I'm leaving in these modes for now, as they do exist in the STM32 LP
Timer, but it does make me curious what the intentions for them were
(perhaps use cases outside of traditional quadrature encoder
positioning).
>
>
>> +
>> +* Quadrature x2 Falling:
>> + Falling edges on either quadrature pair signals updates the respective
>> + count. Quadrature encoding determines the direction.
>> +
>> +* Quadrature x4:
>> + Any state transition on either quadrature pair signals updates the
>> + respective count. Quadrature encoding determines the direction.
>> +
>> +A Count has a set of one or more associated Signals.
>> +
>> +SIGNAL
>> +------
>> +A Signal represents a counter input data; this is the input data that is
>> +analyzed by the counter to determine the count data; e.g. a quadrature
>> +signal output line of a rotary encoder. Not all counter devices provide
>> +user access to the Signal data.
>> +
>> +The Generic Counter interface provides the following available signal
>> +data types for when the Signal data is available for user access:
>> +
>> +* SIGNAL_LEVEL_LOW:
>> + Signal line is in a low state.
>> +
>> +* SIGNAL_LEVEL_HIGH:
>> + Signal line is in a high state.
>> +
>> +A Signal may be associated with one or more Counts.
>> +
>> +SYNAPSE
>> +-------
>> +A Synapse represents the association of a Signal with a respective
>> +Count. Signal data affects respective Count data, and the Synapse
>> +represents this relationship.
>> +
>> +The Synapse action mode specifies the Signal data condition which
>> +triggers the respective Count's count function evaluation to update the
>> +count data. The Generic Counter interface provides the following
>> +available action modes:
>> +
>> +* None:
>> + Signal does not trigger the count function. In Pulse-Direction count
>> + function mode, this Signal is evaluated as Direction.
>> +
>> +* Rising Edge:
>> + Low state transitions to high state.
>> +
>> +* Falling Edge:
>> + High state transitions to low state.
>> +
>> +* Both Edges:
>> + Any state transition.
>> +
>> +A counter is defined as a set of input signals associated with count
>> +data that are generated by the evaluation of the state of the associated
>> +input signals as defined by the respective count functions. Within the
>> +context of the Generic Counter interface, a counter consists of Counts
>> +each associated with a set of Signals, whose respective Synapse
>> +instances represent the count function update conditions for the
>> +associated Counts.
>> +
>> +Paradigm
>> +========
>> +
>> +The most basic counter device may be expressed as a single Count
>> +associated with a single Signal via a single Synapse. Take for example
>> +a counter device which simply accumulates a count of rising edges on a
>> +source input line::
>> +
>> + Count Synapse Signal
>> + ----- ------- ------
>> + +---------------------+
>> + | Data: Count | Rising Edge ________
>> + | Function: Increase | <------------- / Source \
>> + | | ____________
>> + +---------------------+
>> +
>> +In this example, the Signal is a source input line with a pulsing
>> +voltage, while the Count is a persistent count value which is repeatedly
>> +incremented. The Signal is associated with the respective Count via a
>> +Synapse. The increase function is triggered by the Signal data condition
>> +specified by the Synapse -- in this case a rising edge condition on the
>> +voltage input line. In summary, the counter device existence and
>> +behavior is aptly represented by respective Count, Signal, and Synapse
>> +components: a rising edge condition triggers an increase function on an
>> +accumulating count datum.
>> +
>> +A counter device is not limited to a single Signal; in fact, in theory
>> +many Signals may be associated with even a single Count. For example, a
>> +quadrature encoder counter device can keep track of position based on
>> +the states of two input lines::
>> +
>> + Count Synapse Signal
>> + ----- ------- ------
>> + +-------------------------+
>> + | Data: Position | Both Edges ___
>> + | Function: Quadrature x4 | <------------ / A \
>> + | | _______
>> + | |
>> + | | Both Edges ___
>> + | | <------------ / B \
>> + | | _______
>> + +-------------------------+
>> +
>> +In this example, two Signals (quadrature encoder lines A and B) are
>> +associated with a single Count: a rising or falling edge on either A or
>> +B triggers the "Quadrature x4" function which determines the direction
>> +of movement and updates the respective position data. The "Quadrature
>> +x4" function is likely implemented in the hardware of the quadrature
>> +encoder counter device; the Count, Signals, and Synapses simply
>> +represent this hardware behavior and functionality.
>> +
>> +Signals associated with the same Count can have differing Synapse action
>> +mode conditions. For example, a quadrature encoder counter device
>> +operating in a non-quadrature Pulse-Direction mode could have one input
>> +line dedicated for movement and a second input line dedicated for
>> +direction::
>> +
>> + Count Synapse Signal
>> + ----- ------- ------
>> + +---------------------------+
>> + | Data: Position | Rising Edge ___
>> + | Function: Pulse-Direction | <------------- / A \ (Movement)
>> + | | _______
>> + | |
>> + | | None ___
>> + | | <------------- / B \ (Direction)
>> + | | _______
>> + +---------------------------+
>> +
>> +Only Signal A triggers the "Pulse-Direction" update function, but the
>> +instantaneous state of Signal B is still required in order to know the
>> +direction so that the position data may be properly updated. Ultimately,
>> +both Signals are associated with the same Count via two respective
>> +Synapses, but only one Synapse has an active action mode condition which
>> +triggers the respective count function while the other is left with a
>> +"None" condition action mode to indicate its respective Signal's
>> +availability for state evaluation despite its non-triggering mode.
>> +
>> +Keep in mind that the Signal, Synapse, and Count are abstract
>> +representations which do not need to be closely married to their
>> +respective physical sources. This allows the user of a counter to
>> +divorce themselves from the nuances of physical components (such as
>> +whether an input line is differential or single-ended) and instead focus
>> +on the core idea of what the data and process represent (e.g. position
>> +as interpreted from quadrature encoding data).
>> +
>> +Userspace Interface
>> +===================
>> +
>> +Several sysfs attributes are generated by the Generic Counter interface,
>> +and reside under the /sys/bus/counter/devices/counterX directory, where
>> +counterX refers to the respective counter device. Please see
>> +Documentation/ABI/testing/sys-bus-counter-generic-sysfs for detailed
>> +information on each Generic Counter interface sysfs attribute.
>> +
>> +Through these sysfs attributes, programs and scripts may interact with
>> +the Generic Counter paradigm Counts, Signals, and Synapses of respective
>> +counter devices.
>> +
>> +Driver API
>> +==========
>> +
>> +Driver authors may utilize the Generic Counter interface in their code
>> +by including the include/linux/iio/counter.h header file. This header
>
>Didn't this move?
Yes you are correct, looks like an oversight I made. I'll cleanup this
and the rest with the next revision then.
William Breathitt Gray
>
>> +file provides several core data structures, function prototypes, and
>> +macros for defining a counter device.
>> +
>> +.. kernel-doc:: include/linux/counter.h
>> + :internal:
>> +
>> +.. kernel-doc:: drivers/counter/generic-counter.c
>> + :export:
>> +
>> +Implementation
>> +==============
>> +
>> +To support a counter device, a driver must first allocate the available
>> +Counter Signals via counter_signal structures. These Signals should
>> +be stored as an array and set to the signals array member of an
>> +allocated counter_device structure before the Counter is registered to
>> +the system.
>> +
>> +Counter Counts may be allocated via counter_count structures, and
>> +respective Counter Signal associations (Synapses) made via
>> +counter_synapse structures. Associated counter_synapse structures are
>> +stored as an array and set to the the synapses array member of the
>> +respective counter_count structure. These counter_count structures are
>> +set to the counts array member of an allocated counter_device structure
>> +before the Counter is registered to the system.
>> +
>> +Driver callbacks should be provided to the counter_device structure via
>> +a constant counter_ops structure in order to communicate with the
>> +device: to read and write various Signals and Counts, and to set and get
>> +the "action mode" and "function mode" for various Synapses and Counts
>> +respectively.
>> +
>> +A defined counter_device structure may be registered to the system by
>> +passing it to the counter_register function, and unregistered by passing
>> +it to the counter_unregister function. Similarly, the
>> +devm_counter_register and devm_counter_unregister functions may be used
>> +if device memory-managed registration is desired.
>> +
>> +Extension sysfs attributes can be created for auxiliary functionality
>> +and data by passing in defined counter_device_ext, counter_count_ext,
>> +and counter_signal_ext structures. In these cases, the
>> +counter_device_ext structure is used for global configuration of the
>> +respective Counter device, while the counter_count_ext and
>> +counter_signal_ext structures allow for auxiliary exposure and
>> +configuration of a specific Count or Signal respectively.
>> +
>> +Architecture
>> +============
>> +
>> +When the Generic Counter interface counter module is loaded, the
>> +counter_init function is called which registers a bus_type named
>> +"counter" to the system. Subsequently, when the module is unloaded, the
>> +counter_exit function is called which unregisters the bus_type named
>> +"counter" from the system.
>> +
>> +Counter devices are registered to the system via the counter_register
>> +function, and later removed via the counter_unregister function. The
>> +counter_register function establishes a unique ID for the Counter
>> +device and creates a respective sysfs directory, where X is the
>> +mentioned unique ID:
>> +
>> + /sys/bus/counter/devices/counterX
>> +
>> +Sysfs attributes are created within the counterX directory to expose
>> +functionality, configurations, and data relating to the Counts, Signals,
>> +and Synapses of the Counter device, as well as options and information
>> +for the Counter device itself.
>> +
>> +Each Signal has a directory created to house its relevant sysfs
>> +attributes, where Y is the unique ID of the respective Signal:
>> +
>> + /sys/bus/counter/devices/counterX/signalY
>> +
>> +Similarly, each Count has a directory created to house its relevant
>> +sysfs attributes, where Y is the unique ID of the respective Count:
>> +
>> + /sys/bus/counter/devices/counterX/countY
>> +
>> +For a more detailed breakdown of the available Generic Counter interface
>> +sysfs attributes, please refer to the
>> +Documentation/ABI/testing/sys-bus-counter file.
>> +
>> +The Signals and Counts associated with the Counter device are registered
>> +to the system as well by the counter_register function. The
>> +signal_read/signal_write driver callbacks are associated with their
>> +respective Signal attributes, while the count_read/count_write and
>> +function_get/function_set driver callbacks are associated with their
>> +respective Count attributes; similarly, the same is true for the
>> +action_get/action_set driver callbacks and their respective Synapse
>> +attributes. If a driver callback is left undefined, then the respective
>> +read/write permission is left disabled for the relevant attributes.
>> +
>> +Similarly, extension sysfs attributes are created for the defined
>> +counter_device_ext, counter_count_ext, and counter_signal_ext
>> +structures that are passed in.
>> diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
>> index 6d8352c0f354..5fd747c4f2ce 100644
>> --- a/Documentation/driver-api/index.rst
>> +++ b/Documentation/driver-api/index.rst
>> @@ -25,6 +25,7 @@ available subsections can be seen below.
>> frame-buffer
>> regulator
>> iio/index
>> + generic-counter
>> input
>> usb/index
>> pci
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1413e3eb49e5..7a01aa63fb33 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3674,6 +3674,7 @@ M: William Breathitt Gray <vilhelm.gray@gmail.com>
>> L: linux-iio at vger.kernel.org
>> S: Maintained
>> F: Documentation/ABI/testing/sysfs-bus-counter*
>> +F: Documentation/driver-api/generic-counter.rst
>> F: drivers/counter/
>> F: include/linux/counter.h
>>
>
^ permalink raw reply
* [PATCH 3/3] arm64: dts: renesas: r8a7795: add ccree binding
From: Gilad Ben-Yossef @ 2018-05-21 13:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdVM55S7+PdnKusX-qkTxioc=0kQ6EGSbwv+kbLk5RCUYw@mail.gmail.com>
On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Indeed. From a quick glance, it looks like drivers/crypto/ccree/cc_driver.c
> does not distinguish between the absence of the clock property, and an
> actual error in getting the clock, and never considers any error a failure
> (incl. -PROBE_DEFER).
>
> As of_clk_get() returns -ENOENT for both a missing clock property and a
> missing clock, you should use (devm_)clk_get() instead, and distinguish
> between NULL (no clock property) and IS_ERR() (actual failure -> abort).
>
I was trying to do as you suggested but I didn't quite get what is the
dev_id (2nd) parameter to devm_clk_get parameter is supposed to be.
I see what of_clk_get() is doing, so can replicate that but it seems
an over kill.
Any ideas?
Thanks,
Gilad
--
Gilad Ben-Yossef
Chief Coffee Drinker
"If you take a class in large-scale robotics, can you end up in a
situation where the homework eats your dog?"
-- Jean-Baptiste Queru
^ permalink raw reply
* [PATCH 6/6] arm64: perf: Add support for chaining counters
From: Suzuki K Poulose @ 2018-05-21 13:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5d53fe1d-dbd9-2aad-73bd-0c4284540240@arm.com>
On 18/05/18 16:57, Suzuki K Poulose wrote:
> Hi Robin,
>
> On 18/05/18 14:49, Robin Murphy wrote:
>> On 18/05/18 11:22, Suzuki K Poulose wrote:
>>> Add support for chained event counters. PMUv3 allows chaining
>>> a pair of adjacent PMU counters (with the lower counter number
>>> being always "even"). The low counter is programmed to count
>>> the event of interest and the high counter(odd numbered) is
>>> programmed with a special event code (0x1e - Chain). Thus
>>> we need special allocation schemes to make the full use of
>>> available counters. So, we allocate the counters from either
>>> ends. i.e, chained counters are allocated from the lower
>>> end in pairs of two and the normal counters are allocated
>>> from the higher number. Also makes necessary changes to
>>> handle the chained events as a single event with 2 counters.
>>>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Will Deacon <will.deacon@arm.com>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
>>> ? /*
>>> @@ -845,8 +1016,14 @@ static int __armv8_pmuv3_map_event(struct perf_event *event,
>>> ???????????????????????? &armv8_pmuv3_perf_cache_map,
>>> ???????????????????????? ARMV8_PMU_EVTYPE_EVENT);
>>> -??? if (hw_event_id == ARMV8_PMUV3_PERFCTR_CPU_CYCLES)
>>> +??? if (hw_event_id == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
>>> +??????? /* Prevent chaining for cycle counter */
>>
>> Why? Sure, we want to avoid executing the chaining logic if we're scheduling a cycles event in the dedicated counter (which is perhaps what the comment above wanted to say), but if one ends up allocated into a regular counter (e.g. if the user asks for multiple cycle counts with different filters), then I don't see any reason to forbid that being chained.
>
> Ah, I didn't think about that case. I was under the assumption that the
> cycles are *only* placed on the cycle counter. I will take care of that.
> Thanks for the review.
Robin, Mark, Will
One potential problem I see with allowing chaining of the cycle counter
*and* the promotion of cycle event to 64bit by default is when the user
may actually be able to count 1 less event (due to the promotion of
cycle event to 64bit and thus forcing to use chain, if the cycle counter
is unavailable).
So one option is to drop automatic promotion of the cycle counter to
64bit and do it only when it is requested by the user and use either the
Cycle counter (preferred) or fall back to chaining. That way, the user
has the control over the number of events he can count using the given
set of counters.
Let me know your thoughts.
Suzuki
^ permalink raw reply
* [PATCH] PCI: Do not enable PASID when End-to-End TLP is not supported
From: Sinan Kaya @ 2018-05-21 13:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526748769-701-1-git-send-email-okaya@codeaurora.org>
+iommu folks.
On 5/19/2018 12:52 PM, Sinan Kaya wrote:
> A PCIe endpoint carries the process address space identifier (PASID) in
> the TLP prefix as part of the memory read/write transaction. The address
> information in the TLP is relevant only for a given PASID context.
>
> A translation agent takes PASID value and the address information from the
> TLP to look up the physical address in the system.
>
> If a bridge drops the TLP prefix, the translation agent can resolve the
> address to an incorrect location and cause data corruption. Prevent
> this condition by requiring End-to-End TLP prefix to be supported on the
> entire data path between the endpoint and the root port.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/pci/ats.c | 16 ++++++++++++++++
> include/uapi/linux/pci_regs.h | 1 +
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
> index 89305b5..0bcded5 100644
> --- a/drivers/pci/ats.c
> +++ b/drivers/pci/ats.c
> @@ -265,7 +265,9 @@ EXPORT_SYMBOL_GPL(pci_reset_pri);
> int pci_enable_pasid(struct pci_dev *pdev, int features)
> {
> u16 control, supported;
> + struct pci_dev *bridge;
> int pos;
> + u32 cap;
>
> if (WARN_ON(pdev->pasid_enabled))
> return -EBUSY;
> @@ -274,6 +276,20 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
> if (!pos)
> return -EINVAL;
>
> + bridge = pci_upstream_bridge(pdev);
> + while (bridge) {
> + if (!pci_find_capability(bridge, PCI_CAP_ID_EXP))
> + return -EINVAL;
> +
> + if (pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap))
> + return -EINVAL;
> +
> + if (!(cap & PCI_EXP_DEVCAP2_E2ETLP))
> + return -EINVAL;
> +
> + bridge = pci_upstream_bridge(bridge);
> + }
> +
> pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
> supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 103ba79..d91dea5 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -634,6 +634,7 @@
> #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
> #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
> #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
> +#define PCI_EXP_DEVCAP2_E2ETLP 0x00200000 /* End-to-End TLP Prefix */
> #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
> #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
> #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v9 01/15] soc: qcom: Separate kryo l2 accessors from PMU driver
From: Will Deacon @ 2018-05-21 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526901932-9514-2-git-send-email-ilialin@codeaurora.org>
On Mon, May 21, 2018 at 02:25:18PM +0300, Ilia Lin wrote:
> The driver provides kernel level API for other drivers
> to access the MSM8996 L2 cache registers.
> Separating the L2 access code from the PMU driver and
> making it public to allow other drivers use it.
> The accesses must be separated with a single spinlock,
> maintained in this driver.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 ++++++++++--------------------------
I'm fine with the perf bits:
Acked-by: Will Deacon <will.deacon@arm.com>
Will
^ permalink raw reply
* [PATCH 2/2] arm64: Unify kernel fault reporting
From: Mark Rutland @ 2018-05-21 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521131451.41040-1-mark.rutland@arm.com>
In do_page_fault(), we handle some kernel faults early, and simply
die() with a message. For faults handled later, we dump the faulting
address, decode the ESR, walk the page tables, and perform a number of
steps to ensure that this data is reported.
Let's unify the handling of fatal kernel faults with a new
die_kernel_fault() helper, handling all of these details. This is
largely the same as the existing logic in __do_kernel_fault(), except
that addresses are consistently padded to 16 hex characters, as would be
expected for a 64-bit address.
The messages currently logged in do_page_fault are adjusted to fit into
the die_kernel_fault() message template.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
arch/arm64/mm/fault.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 59990491e72a..27cbe0b38960 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -255,6 +255,22 @@ static inline bool is_el1_permission_fault(unsigned int esr,
return false;
}
+static void die_kernel_fault(const char *msg, unsigned long addr,
+ unsigned int esr, struct pt_regs *regs)
+{
+ bust_spinlocks(1);
+
+ pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg,
+ addr);
+
+ mem_abort_decode(esr);
+
+ show_pte(addr);
+ die("Oops", regs, esr);
+ bust_spinlocks(0);
+ do_exit(SIGKILL);
+}
+
static void __do_kernel_fault(unsigned long addr, unsigned int esr,
struct pt_regs *regs)
{
@@ -267,8 +283,6 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr,
if (!is_el1_instruction_abort(esr) && fixup_exception(regs))
return;
- bust_spinlocks(1);
-
if (is_el1_permission_fault(esr, regs, addr)) {
if (esr & ESR_ELx_WNR)
msg = "write to read-only memory";
@@ -280,15 +294,7 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr,
msg = "paging request";
}
- pr_alert("Unable to handle kernel %s at virtual address %08lx\n", msg,
- addr);
-
- mem_abort_decode(esr);
-
- show_pte(addr);
- die("Oops", regs, esr);
- bust_spinlocks(0);
- do_exit(SIGKILL);
+ die_kernel_fault(msg, addr, esr, regs);
}
static void __do_user_fault(struct siginfo *info, unsigned int esr)
@@ -399,13 +405,16 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
if (addr < TASK_SIZE && is_el1_permission_fault(esr, regs, addr)) {
/* regs->orig_addr_limit may be 0 if we entered from EL0 */
if (regs->orig_addr_limit == KERNEL_DS)
- die("Accessing user space memory with fs=KERNEL_DS", regs, esr);
+ die_kernel_fault("access to user memory with fs=KERNEL_DS",
+ addr, esr, regs);
if (is_el1_instruction_abort(esr))
- die("Attempting to execute userspace memory", regs, esr);
+ die_kernel_fault("execution of user memory",
+ addr, esr, regs);
if (!search_exception_tables(regs->pc))
- die("Accessing user space memory outside uaccess.h routines", regs, esr);
+ die_kernel_fault("access to user memory outside uaccess routines",
+ addr, esr, regs);
}
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] arm64: make is_permission_fault() name clearer
From: Mark Rutland @ 2018-05-21 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521131451.41040-1-mark.rutland@arm.com>
The naming of is_permission_fault() makes it sound like it should return
true for permission faults from EL0, but by design, it only does so for
faults from EL1.
Let's make this clear by dropping el1 in the name, as we do for
is_el1_instruction_abort().
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
arch/arm64/mm/fault.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 4165485e8b6e..59990491e72a 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -235,8 +235,9 @@ static bool is_el1_instruction_abort(unsigned int esr)
return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR;
}
-static inline bool is_permission_fault(unsigned int esr, struct pt_regs *regs,
- unsigned long addr)
+static inline bool is_el1_permission_fault(unsigned int esr,
+ struct pt_regs *regs,
+ unsigned long addr)
{
unsigned int ec = ESR_ELx_EC(esr);
unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE;
@@ -268,7 +269,7 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr,
bust_spinlocks(1);
- if (is_permission_fault(esr, regs, addr)) {
+ if (is_el1_permission_fault(esr, regs, addr)) {
if (esr & ESR_ELx_WNR)
msg = "write to read-only memory";
else
@@ -395,7 +396,7 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr,
mm_flags |= FAULT_FLAG_WRITE;
}
- if (addr < TASK_SIZE && is_permission_fault(esr, regs, addr)) {
+ if (addr < TASK_SIZE && is_el1_permission_fault(esr, regs, addr)) {
/* regs->orig_addr_limit may be 0 if we entered from EL0 */
if (regs->orig_addr_limit == KERNEL_DS)
die("Accessing user space memory with fs=KERNEL_DS", regs, esr);
--
2.11.0
^ permalink raw reply related
* [PATCH 0/2] arm64: fatal kernel fault reporting improvements
From: Mark Rutland @ 2018-05-21 13:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Catalin noticed that do_page_fault() can die() for some faults without
reporting the faulting address, which is unfortunate. We also don't
decode the ESR, or attempt to dump the page tables.
These patches unify the handling of those faults with the ones we handle
in __do_kernel_fault(), making things a little more consistent.
Thanks,
Mark.
Mark Rutland (2):
arm64: make is_permission_fault() name clearer
arm64: Unify kernel fault reporting
arch/arm64/mm/fault.c | 46 ++++++++++++++++++++++++++++------------------
1 file changed, 28 insertions(+), 18 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH v3 2/3] arm64: dts: renesas: draak: Describe CVBS input
From: Laurent Pinchart @ 2018-05-21 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521123340.GA15035@w540>
Hi Jacopo,
On Monday, 21 May 2018 15:33:40 EEST jacopo mondi wrote:
> On Mon, May 21, 2018 at 01:54:55PM +0300, Laurent Pinchart wrote:
> > On Monday, 21 May 2018 12:57:05 EEST jacopo mondi wrote:
> >> On Fri, May 18, 2018 at 06:12:15PM +0300, Laurent Pinchart wrote:
> >>> On Friday, 18 May 2018 17:47:57 EEST Jacopo Mondi wrote:
> >>>> Describe CVBS video input through analog video decoder ADV7180
> >>>> connected to video input interface VIN4.
> >>>>
> >>>> The video input signal path is shared with HDMI video input, and
> >>>> selected by on-board switches SW-53 and SW-54 with CVBS input
> >>>> selected by the default switches configuration.
> >>>>
> >>>> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> >>>> Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
> >>>>
> >>>> ---
> >>>> v2 -> v3:
> >>>> - Add comment to describe the shared input video path
> >>>> - Add my SoB and Niklas' R-b tags
> >>>> ---
> >>>>
> >>>> arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 42 ++++++++++++++++++
> >>>> 1 file changed, 42 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> >>>> b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index
> >>>> 9d73de8..95745fc
> >>>> 100644
> >>>> --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> >>>> +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> >>>> @@ -142,6 +142,11 @@
> >>>> groups = "usb0";
> >>>> function = "usb0";
> >>>> };
> >>>> +
> >>>> + vin4_pins_cvbs: vin4 {
> >>>> + groups = "vin4_data8", "vin4_sync", "vin4_clk";
> >>>> + function = "vin4";
> >>>> + };
> >>>> };
> >>>>
> >>>> &i2c0 {
> >>>> @@ -154,6 +159,23 @@
> >>>> reg = <0x50>;
> >>>> pagesize = <8>;
> >>>> };
> >>>> +
> >>>> + analog-video at 20 {
> >>>> + compatible = "adi,adv7180";
> >>>> + reg = <0x20>;
> >>>> +
> >>>> + port {
> >>>
> >>> The adv7180 DT bindings document the output port as 3 or 6
> >>> (respectively for the CP and ST versions of the chip). You should thus
> >>> number the port. Apart from that the patch looks good.
> >>
> >> I admit I have barely copied this from Gen-2 boards DTS, but reading
> >> the driver code and binding description again, I think this is
> >> correct, as the output port numbering and mandatory input port (which
> >> is missing here) only apply to adv7180cp/st chip versions.
> >>
> >> Here we describe plain adv7180, no need to number output ports afaict.
> >
> > Indeed, my bad.
> >
> > Shouldn't you however use "adi,adv7180cp" as that's the chip we are using
> > ?
> > The "adi,adv7180" has no port documented in its DT bindings, so it
> > shouldn't have any port node at all.
>
> I'm a bit confused here.
>
> The only Gen-2 board using the "adi,adv7180cp" compatible string is
> Gose, which is also the only one I can get schematics for. That board
> indeed feature an ADV7180WBCP32Z, as the Draak does. I cannot get
> schematics for any other Gen-2 board, to compare the ADV7180 variant
> installed there. If anyone can confirm that all other Gen-2 board uses
> a different version (or that all other Gen-2 board DTS file use a
> wrong compatible string value), I'll re-send this with a different
> compatible value and proper port nodes numbering.
Other Gen2 boards use a ADV7180WBCP32Z as well. The issue here isn't that the
chip you're trying to support is different. The DT bindings that were
initially written for the adi,adv7180 didn't have port nodes. When it was time
to add them, we realized that two variants of the chip existed with different
connectivity. We have thus added two new compatible strings to differentiate
them, with different port numbers. The old compatible string should be
deprecated in favour of the new ones.
> >>>> + /*
> >>>> + * The VIN4 video input path is shared between
> >>>> + * CVBS and HDMI inputs through SW[49-54] switches.
> >>>> + *
> >>>> + * CVBS is the default selection, link it to VIN4 here.
> >>>> + */
> >>>> + adv7180_out: endpoint {
> >>>> + remote-endpoint = <&vin4_in>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> };
> >>>>
> >>>> &i2c1 {
> >>>> @@ -246,3 +268,23 @@
> >>>> timeout-sec = <60>;
> >>>> status = "okay";
> >>>> };
>>>> +
> >>>> +&vin4 {
> >>>> + pinctrl-0 = <&vin4_pins_cvbs>;
> >>>> + pinctrl-names = "default";
> >>>> +
> >>>> + status = "okay";
> >>>> +
> >>>> + ports {
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + port at 0 {
> >>>> + reg = <0>;
> >>>> +
> >>>> + vin4_in: endpoint {
> >>>> + remote-endpoint = <&adv7180_out>;
> >>>> + };
> >>>> + };
> >>>> + };
> >>>> +};
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v6 1/9] counter: Introduce the Generic Counter interface
From: William Breathitt Gray @ 2018-05-21 13:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180520160652.1896f5a1@archlinux>
On Sun, May 20, 2018 at 04:06:52PM +0100, Jonathan Cameron wrote:
>On Wed, 16 May 2018 13:50:43 -0400
>William Breathitt Gray <vilhelm.gray@gmail.com> wrote:
>
>> This patch introduces the Generic Counter interface for supporting
>> counter devices.
>>
>> In the context of the Generic Counter interface, a counter is defined as
>> a device that reports one or more "counts" based on the state changes of
>> one or more "signals" as evaluated by a defined "count function."
>>
>> Driver callbacks should be provided to communicate with the device: to
>> read and write various Signals and Counts, and to set and get the
>> "action mode" and "count function" for various Synapses and Counts
>> respectively.
>>
>> To support a counter device, a driver must first allocate the available
>> Counter Signals via counter_signal structures. These Signals should
>> be stored as an array and set to the signals array member of an
>> allocated counter_device structure before the Counter is registered to
>> the system.
>>
>> Counter Counts may be allocated via counter_count structures, and
>> respective Counter Signal associations (Synapses) made via
>> counter_synapse structures. Associated counter_synapse structures are
>> stored as an array and set to the the synapses array member of the
>> respective counter_count structure. These counter_count structures are
>> set to the counts array member of an allocated counter_device structure
>> before the Counter is registered to the system.
>>
>> A counter device is registered to the system by passing the respective
>> initialized counter_device structure to the counter_register function;
>> similarly, the counter_unregister function unregisters the respective
>> Counter. The devm_counter_register and devm_counter_unregister functions
>> serve as device memory-managed versions of the counter_register and
>> counter_unregister functions respectively.
>>
>> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
>
>A few minor comments inline. I do somewhat wonder if we can cut
>back on the huge amount of 'similar' code in here, but there tend to
>be just enough small differences to make that really tricky...
>
>Nothing major enough in here that I really plan on reading it again
>(though you never know if you change lots ;)
>
>Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
These look like quick tidy-up suggestions so I expect to incorporate
them in the next revision without trouble. I'll also look around to
organize the repetitive code into functions for reuse where possible, in
order to help clean up the code and make the logic clearer. In short
though, I don't expect any major changes in the next revision, just
minor formatting and cleanup.
William Breathitt Gray
>> ---
>> MAINTAINERS | 7 +
>> drivers/Kconfig | 2 +
>> drivers/Makefile | 1 +
>> drivers/counter/Kconfig | 18 +
>> drivers/counter/Makefile | 8 +
>> drivers/counter/generic-counter.c | 1541 +++++++++++++++++++++++++++++
>> include/linux/counter.h | 554 +++++++++++
>> 7 files changed, 2131 insertions(+)
>> create mode 100644 drivers/counter/Kconfig
>> create mode 100644 drivers/counter/Makefile
>> create mode 100644 drivers/counter/generic-counter.c
>> create mode 100644 include/linux/counter.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 4b65225d443a..2a016d73ab72 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3669,6 +3669,13 @@ W: http://www.fi.muni.cz/~kas/cosa/
>> S: Maintained
>> F: drivers/net/wan/cosa*
>>
>> +COUNTER SUBSYSTEM
>> +M: William Breathitt Gray <vilhelm.gray@gmail.com>
>> +L: linux-iio at vger.kernel.org
>> +S: Maintained
>> +F: drivers/counter/
>> +F: include/linux/counter.h
>> +
>> CPMAC ETHERNET DRIVER
>> M: Florian Fainelli <f.fainelli@gmail.com>
>> L: netdev at vger.kernel.org
>> diff --git a/drivers/Kconfig b/drivers/Kconfig
>> index 95b9ccc08165..70b3cc88dc0b 100644
>> --- a/drivers/Kconfig
>> +++ b/drivers/Kconfig
>> @@ -165,6 +165,8 @@ source "drivers/memory/Kconfig"
>>
>> source "drivers/iio/Kconfig"
>>
>> +source "drivers/counter/Kconfig"
>> +
>Same comment as below.
>
>> source "drivers/ntb/Kconfig"
>>
>> source "drivers/vme/Kconfig"
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index 24cd47014657..5914c78688c3 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -165,6 +165,7 @@ obj-$(CONFIG_PM_DEVFREQ) += devfreq/
>> obj-$(CONFIG_EXTCON) += extcon/
>> obj-$(CONFIG_MEMORY) += memory/
>> obj-$(CONFIG_IIO) += iio/
>> +obj-$(CONFIG_COUNTER) += counter/
>
>I can see your logic in putting this here, but I think the convention
>is to go at the end rather than grouping.
>
>> obj-$(CONFIG_VME_BUS) += vme/
>> obj-$(CONFIG_IPACK_BUS) += ipack/
>> obj-$(CONFIG_NTB) += ntb/
>> diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
>> new file mode 100644
>> index 000000000000..65fa92abd5a4
>> --- /dev/null
>> +++ b/drivers/counter/Kconfig
>> @@ -0,0 +1,18 @@
>> +#
>> +# Counter devices
>> +#
>> +# When adding new entries keep the list in alphabetical order
>> +
>> +menuconfig COUNTER
>> + tristate "Counter support"
>> + help
>> + Provides Generic Counter interface support for counter devices.
>> +
>> + Counter devices are prevalent within a diverse spectrum of industries.
>> + The ubiquitous presence of these devices necessitates a common
>> + interface and standard of interaction and exposure. This driver API
>> + attempts to resolve the issue of duplicate code found among existing
>> + counter device drivers by providing a generic counter interface for
>> + consumption. The Generic Counter interface enables drivers to support
>> + and expose a common set of components and functionality present in
>> + counter devices.
>> diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
>> new file mode 100644
>> index 000000000000..ad1ba7109cdc
>> --- /dev/null
>> +++ b/drivers/counter/Makefile
>> @@ -0,0 +1,8 @@
>> +#
>> +# Makefile for Counter devices
>> +#
>> +
>> +# When adding new entries keep the list in alphabetical order
>> +
>> +obj-$(CONFIG_COUNTER) += counter.o
>> +counter-y := generic-counter.o
>> diff --git a/drivers/counter/generic-counter.c b/drivers/counter/generic-counter.c
>> new file mode 100644
>> index 000000000000..0d83b862453f
>> --- /dev/null
>> +++ b/drivers/counter/generic-counter.c
>> @@ -0,0 +1,1541 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Generic Counter interface
>> + * Copyright (C) 2017 William Breathitt Gray
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License, version 2, as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * General Public License for more details.
>
>As below, SPDX and license seems silly. Unless you are feeling paranoid
>just drop the license text.
>
>> + */
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/export.h>
>> +#include <linux/fs.h>
>> +#include <linux/gfp.h>
>> +#include <linux/idr.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/module.h>
>> +#include <linux/printk.h>
>> +#include <linux/slab.h>
>> +#include <linux/string.h>
>> +#include <linux/sysfs.h>
>> +#include <linux/types.h>
>> +
>> +#include <linux/counter.h>
>> +
>> +const char *const count_direction_str[2] = {
>> + [COUNT_DIRECTION_FORWARD] = "forward",
>> + [COUNT_DIRECTION_BACKWARD] = "backward"
>> +};
>> +EXPORT_SYMBOL(count_direction_str);
>> +
>> +const char *const count_mode_str[4] = {
>> + [COUNT_MODE_NORMAL] = "normal",
>> + [COUNT_MODE_RANGE_LIMIT] = "range limit",
>> + [COUNT_MODE_NON_RECYCLE] = "non-recycle",
>> + [COUNT_MODE_MODULO_N] = "modulo-n"
>> +};
>> +EXPORT_SYMBOL(count_mode_str);
>> +
>> +ssize_t counter_signal_enum_read(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + char *buf)
>> +{
>> + const struct counter_signal_enum_ext *const e = priv;
>> + int err;
>> + size_t index;
>> +
>> + if (!e->get)
>> + return -EINVAL;
>> +
>> + err = e->get(counter, signal, &index);
>> + if (err)
>> + return err;
>> +
>> + if (index >= e->num_items)
>> + return -EINVAL;
>> +
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", e->items[index]);
>> +}
>> +EXPORT_SYMBOL(counter_signal_enum_read);
>> +
>> +ssize_t counter_signal_enum_write(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_signal_enum_ext *const e = priv;
>> + ssize_t index;
>> + int err;
>> +
>> + if (!e->set)
>> + return -EINVAL;
>> +
>> + index = __sysfs_match_string(e->items, e->num_items, buf);
>> + if (index < 0)
>> + return index;
>> +
>> + err = e->set(counter, signal, index);
>> + if (err)
>> + return err;
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_signal_enum_write);
>> +
>> +ssize_t counter_signal_enum_available_read(struct counter_device *counter,
>> + struct counter_signal *signal,
>> + void *priv, char *buf)
>> +{
>> + const struct counter_signal_enum_ext *const e = priv;
>> + size_t i;
>> + size_t len = 0;
>> +
>> + if (!e->num_items)
>> + return 0;
>> +
>> + for (i = 0; i < e->num_items; i++)
>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%s\n",
>> + e->items[i]);
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_signal_enum_available_read);
>> +
>> +ssize_t counter_count_enum_read(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + char *buf)
>> +{
>> + const struct counter_count_enum_ext *const e = priv;
>> + int err;
>> + size_t index;
>> +
>> + if (!e->get)
>> + return -EINVAL;
>> +
>> + err = e->get(counter, count, &index);
>> + if (err)
>> + return err;
>> +
>> + if (index >= e->num_items)
>> + return -EINVAL;
>> +
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", e->items[index]);
>> +}
>> +EXPORT_SYMBOL(counter_count_enum_read);
>> +
>> +ssize_t counter_count_enum_write(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_count_enum_ext *const e = priv;
>> + ssize_t index;
>> + int err;
>> +
>> + if (!e->set)
>> + return -EINVAL;
>> +
>> + index = __sysfs_match_string(e->items, e->num_items, buf);
>> + if (index < 0)
>> + return index;
>> +
>> + err = e->set(counter, count, index);
>> + if (err)
>> + return err;
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_count_enum_write);
>> +
>> +ssize_t counter_count_enum_available_read(struct counter_device *counter,
>> + struct counter_count *count,
>> + void *priv, char *buf)
>> +{
>> + const struct counter_count_enum_ext *const e = priv;
>> + size_t i;
>> + size_t len = 0;
>> +
>> + if (!e->num_items)
>> + return 0;
>> +
>> + for (i = 0; i < e->num_items; i++)
>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%s\n",
>> + e->items[i]);
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_count_enum_available_read);
>> +
>> +ssize_t counter_device_enum_read(struct counter_device *counter, void *priv,
>> + char *buf)
>> +{
>> + const struct counter_device_enum_ext *const e = priv;
>> + int err;
>> + size_t index;
>> +
>> + if (!e->get)
>> + return -EINVAL;
>> +
>> + err = e->get(counter, &index);
>> + if (err)
>> + return err;
>> +
>> + if (index >= e->num_items)
>> + return -EINVAL;
>> +
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", e->items[index]);
>> +}
>> +EXPORT_SYMBOL(counter_device_enum_read);
>> +
>> +ssize_t counter_device_enum_write(struct counter_device *counter, void *priv,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_enum_ext *const e = priv;
>> + ssize_t index;
>> + int err;
>> +
>> + if (!e->set)
>> + return -EINVAL;
>> +
>> + index = __sysfs_match_string(e->items, e->num_items, buf);
>> + if (index < 0)
>> + return index;
>> +
>> + err = e->set(counter, index);
>> + if (err)
>> + return err;
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_device_enum_write);
>> +
>> +ssize_t counter_device_enum_available_read(struct counter_device *counter,
>> + void *priv, char *buf)
>> +{
>> + const struct counter_device_enum_ext *const e = priv;
>> + size_t i;
>> + size_t len = 0;
>> +
>> + if (!e->num_items)
>> + return 0;
>> +
>> + for (i = 0; i < e->num_items; i++)
>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%s\n",
>> + e->items[i]);
>> +
>> + return len;
>> +}
>> +EXPORT_SYMBOL(counter_device_enum_available_read);
>> +
>> +static const char *const signal_level_str[] = {
>> + [SIGNAL_LEVEL_LOW] = "low",
>> + [SIGNAL_LEVEL_HIGH] = "high"
>> +};
>> +
>> +/**
>> + * set_signal_read_value - set signal_read_value data
>> + * @val: signal_read_value structure to set
>> + * @type: property Signal data represents
>> + * @data: Signal data
>> + *
>> + * This function sets an opaque signal_read_value structure with the provided
>> + * Signal data.
>> + */
>> +void set_signal_read_value(struct signal_read_value *const val,
>> + const enum signal_value_type type, void *const data)
>> +{
>> + if (type == SIGNAL_LEVEL)
>> + val->len = scnprintf(val->buf, PAGE_SIZE, "%s\n",
>> + signal_level_str[*(enum signal_level *)data]);
>> + else
>> + val->len = 0;
>> +}
>> +EXPORT_SYMBOL(set_signal_read_value);
>> +
>> +/**
>> + * set_count_read_value - set count_read_value data
>> + * @val: count_read_value structure to set
>> + * @type: property Count data represents
>> + * @data: Count data
>> + *
>> + * This function sets an opaque count_read_value structure with the provided
>> + * Count data.
>> + */
>> +void set_count_read_value(struct count_read_value *const val,
>> + const enum count_value_type type, void *const data)
>> +{
>> + switch (type) {
>> + case COUNT_POSITION_UNSIGNED:
>> + val->len = scnprintf(val->buf, PAGE_SIZE, "%lu\n",
>> + *(unsigned long *)data);
>> + break;
>> + case COUNT_POSITION_SIGNED:
>> + val->len = scnprintf(val->buf, PAGE_SIZE, "%ld\n",
>> + *(long *)data);
>> + break;
>> + default:
>> + val->len = 0;
>> + }
>> +}
>> +EXPORT_SYMBOL(set_count_read_value);
>> +
>> +/**
>> + * get_count_write_value - get count_write_value data
>> + * @data: Count data
>> + * @type: property Count data represents
>> + * @val: count_write_value structure containing data
>> + *
>> + * This function extracts Count data from the provided opaque count_write_value
>> + * structure and stores it at the address provided by @data.
>> + *
>> + * RETURNS:
>> + * 0 on success, negative error number on failure.
>> + */
>> +int get_count_write_value(void *const data, const enum count_value_type type,
>> + const struct count_write_value *const val)
>> +{
>> + int err;
>> +
>> + switch (type) {
>> + case COUNT_POSITION_UNSIGNED:
>> + err = kstrtoul(val->buf, 0, data);
>> + if (err)
>> + return err;
>> + break;
>> + case COUNT_POSITION_SIGNED:
>> + err = kstrtol(val->buf, 0, data);
>> + if (err)
>> + return err;
>> + break;
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(get_count_write_value);
>> +
>> +struct counter_device_attr {
>> + struct device_attribute dev_attr;
>> + struct list_head l;
>> + void *component;
>> +};
>> +
>> +static int counter_attribute_create(
>> + struct counter_device_attr_group *const group,
>> + const char *const prefix,
>> + const char *const name,
>> + ssize_t (*show)(struct device *dev, struct device_attribute *attr,
>> + char *buf),
>> + ssize_t (*store)(struct device *dev, struct device_attribute *attr,
>> + const char *buf, size_t len),
>> + void *const component)
>> +{
>> + struct counter_device_attr *counter_attr;
>> + struct device_attribute *dev_attr;
>> + int err;
>> + struct list_head *const attr_list = &group->attr_list;
>> +
>> + /* Allocate a Counter device attribute */
>> + counter_attr = kzalloc(sizeof(*counter_attr), GFP_KERNEL);
>> + if (!counter_attr)
>> + return -ENOMEM;
>> + dev_attr = &counter_attr->dev_attr;
>> +
>> + sysfs_attr_init(&dev_attr->attr);
>> +
>> + /* Configure device attribute */
>> + dev_attr->attr.name = kasprintf(GFP_KERNEL, "%s%s", prefix, name);
>> + if (!dev_attr->attr.name) {
>> + err = -ENOMEM;
>> + goto err_free_counter_attr;
>> + }
>> + if (show) {
>> + dev_attr->attr.mode |= 0444;
>> + dev_attr->show = show;
>> + }
>> + if (store) {
>> + dev_attr->attr.mode |= 0200;
>> + dev_attr->store = store;
>> + }
>> +
>> + /* Store associated Counter component with attribute */
>> + counter_attr->component = component;
>> +
>> + /* Keep track of the attribute for later cleanup */
>> + list_add(&counter_attr->l, attr_list);
>> + group->num_attr++;
>> +
>> + return 0;
>> +
>> +err_free_counter_attr:
>> + kfree(counter_attr);
>> + return err;
>> +}
>> +
>> +#define to_counter_attr(_dev_attr) \
>> + container_of(_dev_attr, struct counter_device_attr, dev_attr)
>> +
>> +struct signal_comp_t {
>> + struct counter_signal *signal;
>> +};
>> +
>> +static ssize_t counter_signal_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct signal_comp_t *const component = devattr->component;
>> + struct counter_signal *const signal = component->signal;
>> + int err;
>> + struct signal_read_value val = { .buf = buf };
>> +
>> + err = counter->ops->signal_read(counter, signal, &val);
>> + if (err)
>> + return err;
>> +
>> + return val.len;
>> +}
>> +
>> +struct name_comp_t {
>> + const char *name;
>> +};
>> +
>> +static ssize_t counter_device_attr_name_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + const struct name_comp_t *const comp = to_counter_attr(attr)->component;
>> +
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", comp->name);
>> +}
>> +
>> +static int counter_name_attribute_create(
>> + struct counter_device_attr_group *const group,
>> + const char *const name)
>> +{
>> + struct name_comp_t *name_comp;
>> + int err;
>> +
>> + /* Skip if no name */
>> + if (!name)
>> + return 0;
>> +
>> + /* Allocate name attribute component */
>> + name_comp = kmalloc(sizeof(*name_comp), GFP_KERNEL);
>> + if (!name_comp)
>> + return -ENOMEM;
>> + name_comp->name = name;
>> +
>> + /* Allocate Signal name attribute */
>> + err = counter_attribute_create(group, "", "name",
>> + counter_device_attr_name_show, NULL,
>> + name_comp);
>> + if (err)
>> + goto err_free_name_comp;
>> +
>> + return 0;
>> +
>> +err_free_name_comp:
>> + kfree(name_comp);
>> + return err;
>> +}
>> +
>> +struct signal_ext_comp_t {
>> + struct counter_signal *signal;
>> + const struct counter_signal_ext *ext;
>> +};
>> +
>> +static ssize_t counter_signal_ext_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct signal_ext_comp_t *const comp = devattr->component;
>> + const struct counter_signal_ext *const ext = comp->ext;
>> +
>> + return ext->read(dev_get_drvdata(dev), comp->signal, ext->priv, buf);
>> +}
>> +
>> +static ssize_t counter_signal_ext_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct signal_ext_comp_t *const comp = devattr->component;
>> + const struct counter_signal_ext *const ext = comp->ext;
>> +
>> + return ext->write(dev_get_drvdata(dev), comp->signal, ext->priv, buf,
>> + len);
>> +}
>> +
>> +static void free_counter_device_attr_list(struct list_head *attr_list)
>> +{
>> + struct counter_device_attr *p, *n;
>> +
>> + list_for_each_entry_safe(p, n, attr_list, l) {
>> + kfree(p->dev_attr.attr.name);
>> + kfree(p->component);
>> + list_del(&p->l);
>> + kfree(p);
>> + }
>> +}
>> +
>> +static int counter_signal_ext_register(
>> + struct counter_device_attr_group *const group,
>> + struct counter_signal *const signal)
>> +{
>> + const size_t num_ext = signal->num_ext;
>> + size_t i;
>> + const struct counter_signal_ext *ext;
>> + struct signal_ext_comp_t *signal_ext_comp;
>> + int err;
>> +
>> + /* Create an attribute for each extension */
>> + for (i = 0 ; i < num_ext; i++) {
>> + ext = signal->ext + i;
>> +
>> + /* Allocate signal_ext attribute component */
>> + signal_ext_comp = kmalloc(sizeof(*signal_ext_comp), GFP_KERNEL);
>> + if (!signal_ext_comp) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> + signal_ext_comp->signal = signal;
>> + signal_ext_comp->ext = ext;
>> +
>> + /* Allocate a Counter device attribute */
>> + err = counter_attribute_create(group, "", ext->name,
>> + (ext->read) ? counter_signal_ext_show : NULL,
>> + (ext->write) ? counter_signal_ext_store : NULL,
>> + signal_ext_comp);
>> + if (err) {
>> + kfree(signal_ext_comp);
>> + goto err_free_attr_list;
>> + }
>> + }
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +static int counter_signal_attributes_create(
>> + struct counter_device_attr_group *const group,
>> + const struct counter_device *const counter,
>> + struct counter_signal *const signal)
>> +{
>> + struct signal_comp_t *signal_comp;
>> + int err;
>> +
>> + /* Allocate Signal attribute component */
>> + signal_comp = kmalloc(sizeof(*signal_comp), GFP_KERNEL);
>> + if (!signal_comp)
>> + return -ENOMEM;
>> + signal_comp->signal = signal;
>> +
>> + /* Create main Signal attribute */
>> + err = counter_attribute_create(group, "", "signal",
>> + (counter->ops->signal_read) ? counter_signal_show : NULL, NULL,
>> + signal_comp);
>> + if (err) {
>> + kfree(signal_comp);
>> + return err;
>> + }
>> +
>> + /* Create Signal name attribute */
>> + err = counter_name_attribute_create(group, signal->name);
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + /* Register Signal extension attributes */
>> + err = counter_signal_ext_register(group, signal);
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +static int counter_signals_register(
>> + struct counter_device_attr_group *const groups_list,
>> + const struct counter_device *const counter)
>> +{
>> + const size_t num_signals = counter->num_signals;
>> + size_t i;
>> + struct counter_signal *signal;
>> + const char *name;
>> + int err;
>> +
>> + /* Register each Signal */
>> + for (i = 0; i < num_signals; i++) {
>> + signal = counter->signals + i;
>> +
>> + /* Generate Signal attribute directory name */
>> + name = kasprintf(GFP_KERNEL, "signal%d", signal->id);
>> + if (!name) {
>> + err = -ENOMEM;
>> + goto err_free_attr_groups;
>> + }
>> + groups_list[i].attr_group.name = name;
>> +
>> + /* Create all attributes associated with Signal */
>> + err = counter_signal_attributes_create(groups_list + i, counter,
>> + signal);
>> + if (err)
>> + goto err_free_attr_groups;
>> + }
>> +
>> + return 0;
>> +
>> +err_free_attr_groups:
>> + do {
>> + kfree(groups_list[i].attr_group.name);
>> + free_counter_device_attr_list(&groups_list[i].attr_list);
>> + } while (i--);
>> + return err;
>> +}
>> +
>> +static const char *const synapse_action_str[] = {
>> + [SYNAPSE_ACTION_NONE] = "none",
>> + [SYNAPSE_ACTION_RISING_EDGE] = "rising edge",
>> + [SYNAPSE_ACTION_FALLING_EDGE] = "falling edge",
>> + [SYNAPSE_ACTION_BOTH_EDGES] = "both edges"
>> +};
>> +
>> +struct action_comp_t {
>> + struct counter_synapse *synapse;
>> + struct counter_count *count;
>> +};
>> +
>> +static ssize_t counter_action_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + int err;
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + const struct action_comp_t *const component = devattr->component;
>> + struct counter_count *const count = component->count;
>> + struct counter_synapse *const synapse = component->synapse;
>> + size_t action_index;
>> + enum synapse_action action;
>> +
>> + err = counter->ops->action_get(counter, count, synapse, &action_index);
>> + if (err)
>> + return err;
>> +
>> + synapse->action = action_index;
>> +
>> + action = synapse->actions_list[action_index];
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", synapse_action_str[action]);
>> +}
>> +
>> +static ssize_t counter_action_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct action_comp_t *const component = devattr->component;
>> + struct counter_synapse *const synapse = component->synapse;
>> + size_t action_index;
>> + const size_t num_actions = synapse->num_actions;
>> + enum synapse_action action;
>> + int err;
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + struct counter_count *const count = component->count;
>> +
>> + /* Find requested action mode */
>> + for (action_index = 0; action_index < num_actions; action_index++) {
>> + action = synapse->actions_list[action_index];
>> + if (sysfs_streq(buf, synapse_action_str[action]))
>> + break;
>> + }
>> + /* If requested action mode not found */
>> + if (action_index >= num_actions)
>> + return -EINVAL;
>> +
>> + err = counter->ops->action_set(counter, count, synapse, action_index);
>> + if (err)
>> + return err;
>> +
>> + synapse->action = action_index;
>> +
>> + return len;
>> +}
>> +
>> +struct action_avail_comp_t {
>> + const enum synapse_action *actions_list;
>> + size_t num_actions;
>> +};
>> +
>> +static ssize_t counter_synapse_action_available_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct action_avail_comp_t *const component = devattr->component;
>> + const enum synapse_action *const actions_list = component->actions_list;
>
>I'm not sure this local variable helps much either...
>
>> + const size_t num_actions = component->num_actions;
>
>Local variable adds nothing as far as I can see.. Just use it inline.
>
>
>> + size_t i;
>> + enum synapse_action action;
>> + ssize_t len = 0;
>> +
>> + for (i = 0; i < num_actions; i++) {
>> + action = actions_list[i];
>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%s\n",
>> + synapse_action_str[action]);
>> + }
>> +
>> + return len;
>> +}
>> +
>> +static int counter_synapses_register(
>> + struct counter_device_attr_group *const group,
>> + const struct counter_device *const counter,
>> + struct counter_count *const count, const char *const count_attr_name)
>> +{
>> + const size_t num_synapses = count->num_synapses;
>
>Local variable doesn't add anything. Only used once.
>
>> + size_t i;
>> + struct counter_synapse *synapse;
>> + const char *prefix;
>> + struct action_comp_t *action_comp;
>> + int err;
>> + struct action_avail_comp_t *avail_comp;
>> +
>> + /* Register each Synapse */
>> + for (i = 0; i < num_synapses; i++) {
>> + synapse = count->synapses + i;
>> +
>> + /* Generate attribute prefix */
>> + prefix = kasprintf(GFP_KERNEL, "signal%d_",
>> + synapse->signal->id);
>> + if (!prefix) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> +
>> + /* Allocate action attribute component */
>> + action_comp = kmalloc(sizeof(*action_comp), GFP_KERNEL);
>> + if (!action_comp) {
>> + err = -ENOMEM;
>> + goto err_free_prefix;
>> + }
>> + action_comp->synapse = synapse;
>> + action_comp->count = count;
>> +
>> + /* Create action attribute */
>> + err = counter_attribute_create(group, prefix, "action",
>> + (counter->ops->action_get) ? counter_action_show : NULL,
>> + (counter->ops->action_set) ? counter_action_store : NULL,
>> + action_comp);
>> + if (err) {
>> + kfree(action_comp);
>> + goto err_free_prefix;
>> + }
>> +
>> + /* Allocate action available attribute component */
>> + avail_comp = kmalloc(sizeof(*avail_comp), GFP_KERNEL);
>> + if (!avail_comp) {
>> + err = -ENOMEM;
>> + goto err_free_prefix;
>> + }
>> + avail_comp->actions_list = synapse->actions_list;
>> + avail_comp->num_actions = synapse->num_actions;
>> +
>> + /* Create action_available attribute */
>> + err = counter_attribute_create(group, prefix,
>> + "action_available",
>> + counter_synapse_action_available_show, NULL,
>> + avail_comp);
>> + if (err) {
>> + kfree(avail_comp);
>> + goto err_free_prefix;
>> + }
>> +
>> + kfree(prefix);
>> + }
>> +
>> + return 0;
>> +
>> +err_free_prefix:
>> + kfree(prefix);
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +struct count_comp_t {
>> + struct counter_count *count;
>> +};
>> +
>> +static ssize_t counter_count_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_comp_t *const component = devattr->component;
>> + struct counter_count *const count = component->count;
>> + int err;
>> + struct count_read_value val = { .buf = buf };
>> +
>> + err = counter->ops->count_read(counter, count, &val);
>> + if (err)
>> + return err;
>> +
>> + return val.len;
>> +}
>> +
>> +static ssize_t counter_count_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_comp_t *const component = devattr->component;
>> + struct counter_count *const count = component->count;
>> + int err;
>> + struct count_write_value val = { .buf = buf };
>> +
>> + err = counter->ops->count_write(counter, count, &val);
>> + if (err)
>> + return err;
>> +
>> + return len;
>> +}
>> +
>> +static const char *const count_function_str[] = {
>> + [COUNT_FUNCTION_INCREASE] = "increase",
>> + [COUNT_FUNCTION_DECREASE] = "decrease",
>> + [COUNT_FUNCTION_PULSE_DIRECTION] = "pulse-direction",
>> + [COUNT_FUNCTION_QUADRATURE_X1_A] = "quadrature x1 a",
>> + [COUNT_FUNCTION_QUADRATURE_X1_B] = "quadrature x1 b",
>> + [COUNT_FUNCTION_QUADRATURE_X2_A] = "quadrature x2 a",
>> + [COUNT_FUNCTION_QUADRATURE_X2_B] = "quadrature x2 b",
>> + [COUNT_FUNCTION_QUADRATURE_X2_RISING] = "quadrature x2 rising",
>> + [COUNT_FUNCTION_QUADRATURE_X2_FALLING] = "quadrature x2 falling",
>> + [COUNT_FUNCTION_QUADRATURE_X4] = "quadrature x4"
>> +};
>> +
>> +static ssize_t counter_function_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + int err;
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_comp_t *const component = devattr->component;
>> + struct counter_count *const count = component->count;
>> + size_t func_index;
>> + enum count_function function;
>> +
>> + err = counter->ops->function_get(counter, count, &func_index);
>> + if (err)
>> + return err;
>> +
>> + count->function = func_index;
>> +
>> + function = count->functions_list[func_index];
>> + return scnprintf(buf, PAGE_SIZE, "%s\n", count_function_str[function]);
>> +}
>> +
>> +static ssize_t counter_function_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_comp_t *const component = devattr->component;
>> + struct counter_count *const count = component->count;
>> + const size_t num_functions = count->num_functions;
>> + size_t func_index;
>> + enum count_function function;
>> + int err;
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> +
>> + /* Find requested Count function mode */
>> + for (func_index = 0; func_index < num_functions; func_index++) {
>> + function = count->functions_list[func_index];
>> + if (sysfs_streq(buf, count_function_str[function]))
>> + break;
>> + }
>> + /* Return error if requested Count function mode not found */
>> + if (func_index >= num_functions)
>> + return -EINVAL;
>> +
>> + err = counter->ops->function_set(counter, count, func_index);
>> + if (err)
>> + return err;
>> +
>> + count->function = func_index;
>> +
>> + return len;
>> +}
>> +
>> +struct count_ext_comp_t {
>> + struct counter_count *count;
>> + const struct counter_count_ext *ext;
>> +};
>> +
>> +static ssize_t counter_count_ext_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_ext_comp_t *const comp = devattr->component;
>> + const struct counter_count_ext *const ext = comp->ext;
>> +
>> + return ext->read(dev_get_drvdata(dev), comp->count, ext->priv, buf);
>> +}
>> +
>> +static ssize_t counter_count_ext_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct count_ext_comp_t *const comp = devattr->component;
>> + const struct counter_count_ext *const ext = comp->ext;
>> +
>> + return ext->write(dev_get_drvdata(dev), comp->count, ext->priv, buf,
>> + len);
>> +}
>> +
>> +static int counter_count_ext_register(
>> + struct counter_device_attr_group *const group,
>> + struct counter_count *const count)
>> +{
>> + const size_t num_ext = count->num_ext;
>
>Used in one place, just put it inline?
>
>> + size_t i;
>> + const struct counter_count_ext *ext;
>> + struct count_ext_comp_t *count_ext_comp;
>> + int err;
>> +
>> + /* Create an attribute for each extension */
>> + for (i = 0 ; i < num_ext; i++) {
>> + ext = count->ext + i;
>> +
>> + /* Allocate count_ext attribute component */
>> + count_ext_comp = kmalloc(sizeof(*count_ext_comp), GFP_KERNEL);
>> + if (!count_ext_comp) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> + count_ext_comp->count = count;
>> + count_ext_comp->ext = ext;
>> +
>> + /* Allocate count_ext attribute */
>> + err = counter_attribute_create(group, "", ext->name,
>> + (ext->read) ? counter_count_ext_show : NULL,
>> + (ext->write) ? counter_count_ext_store : NULL,
>> + count_ext_comp);
>> + if (err) {
>> + kfree(count_ext_comp);
>> + goto err_free_attr_list;
>> + }
>> + }
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +struct func_avail_comp_t {
>> + const enum count_function *functions_list;
>> + size_t num_functions;
>> +};
>> +
>> +static ssize_t counter_count_function_available_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct func_avail_comp_t *const component = devattr->component;
>> + const enum count_function *const func_list = component->functions_list;
>> + const size_t num_functions = component->num_functions;
>> + size_t i;
>> + enum count_function function;
>> + ssize_t len = 0;
>> +
>> + for (i = 0; i < num_functions; i++) {
>> + function = func_list[i];
>> + len += scnprintf(buf + len, PAGE_SIZE - len, "%s\n",
>> + count_function_str[function]);
>> + }
>> +
>> + return len;
>> +}
>> +
>> +static int counter_count_attributes_create(
>> + struct counter_device_attr_group *const group,
>> + const struct counter_device *const counter,
>> + struct counter_count *const count)
>> +{
>> + struct count_comp_t *count_comp;
>> + int err;
>> + struct count_comp_t *func_comp;
>> + struct func_avail_comp_t *avail_comp;
>> +
>> + /* Allocate count attribute component */
>> + count_comp = kmalloc(sizeof(*count_comp), GFP_KERNEL);
>> + if (!count_comp)
>> + return -ENOMEM;
>> + count_comp->count = count;
>> +
>> + /* Create main Count attribute */
>> + err = counter_attribute_create(group, "", "count",
>> + (counter->ops->count_read) ? counter_count_show : NULL,
>> + (counter->ops->count_write) ? counter_count_store : NULL,
>> + count_comp);
>> + if (err) {
>> + kfree(count_comp);
>> + return err;
>> + }
>> +
>> + /* Allocate function attribute component */
>> + func_comp = kmalloc(sizeof(*func_comp), GFP_KERNEL);
>> + if (!func_comp) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> + func_comp->count = count;
>> +
>> + /* Create Count function attribute */
>> + err = counter_attribute_create(group, "", "function",
>> + (counter->ops->function_get) ? counter_function_show : NULL,
>> + (counter->ops->function_set) ? counter_function_store : NULL,
>> + func_comp);
>> + if (err) {
>> + kfree(func_comp);
>> + goto err_free_attr_list;
>> + }
>> +
>> + /* Allocate function available attribute component */
>> + avail_comp = kmalloc(sizeof(*avail_comp), GFP_KERNEL);
>> + if (!avail_comp) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> + avail_comp->functions_list = count->functions_list;
>> + avail_comp->num_functions = count->num_functions;
>> +
>> + /* Create Count function_available attribute */
>> + err = counter_attribute_create(group, "", "function_available",
>> + counter_count_function_available_show,
>> + NULL, avail_comp);
>> + if (err) {
>> + kfree(avail_comp);
>> + goto err_free_attr_list;
>> + }
>> +
>> + /* Create Count name attribute */
>> + err = counter_name_attribute_create(group, count->name);
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + /* Register Count extension attributes */
>> + err = counter_count_ext_register(group, count);
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +static int counter_counts_register(
>> + struct counter_device_attr_group *const groups_list,
>> + const struct counter_device *const counter)
>> +{
>> + const size_t num_counts = counter->num_counts;
>
>I think this is only used on one place. Not sure having
>a local variable is worthwhile.
>
>> + size_t i;
>> + struct counter_count *count;
>> + const char *name;
>> + int err;
>> +
>> + /* Register each Count */
>> + for (i = 0; i < num_counts; i++) {
>> + count = counter->counts + i;
>> +
>> + /* Generate Count attribute directory name */
>> + name = kasprintf(GFP_KERNEL, "count%d", count->id);
>> + if (!name) {
>> + err = -ENOMEM;
>> + goto err_free_attr_groups;
>> + }
>> + groups_list[i].attr_group.name = name;
>> +
>> + /* Register the Synapses associated with each Count */
>> + err = counter_synapses_register(groups_list + i, counter, count,
>> + name);
>> + if (err)
>> + goto err_free_attr_groups;
>> +
>> + /* Create all attributes associated with Count */
>> + err = counter_count_attributes_create(groups_list + i, counter,
>> + count);
>> + if (err)
>> + goto err_free_attr_groups;
>> + }
>> +
>> + return 0;
>> +
>> +err_free_attr_groups:
>> + do {
>> + kfree(groups_list[i].attr_group.name);
>> + free_counter_device_attr_list(&groups_list[i].attr_list);
>> + } while (i--);
>> + return err;
>> +}
>> +
>> +struct size_comp_t {
>> + size_t size;
>> +};
>> +
>> +static ssize_t counter_device_attr_size_show(struct device *dev,
>> + struct device_attribute *attr,
>> + char *buf)
>> +{
>> + const struct size_comp_t *const comp = to_counter_attr(attr)->component;
>> +
>> + return scnprintf(buf, PAGE_SIZE, "%zu\n", comp->size);
>> +}
>> +
>> +static int counter_size_attribute_create(
>> + struct counter_device_attr_group *const group,
>> + const size_t size, const char *const name)
>> +{
>> + struct size_comp_t *size_comp;
>> + int err;
>> +
>> + /* Allocate size attribute component */
>> + size_comp = kmalloc(sizeof(*size_comp), GFP_KERNEL);
>> + if (!size_comp)
>> + return -ENOMEM;
>> + size_comp->size = size;
>> +
>> + err = counter_attribute_create(group, "", name,
>> + counter_device_attr_size_show, NULL,
>> + size_comp);
>> + if (err)
>> + goto err_free_size_comp;
>> +
>> + return 0;
>> +
>> +err_free_size_comp:
>> + kfree(size_comp);
>> + return err;
>> +}
>> +
>> +struct ext_comp_t {
>> + const struct counter_device_ext *ext;
>> +};
>> +
>> +static ssize_t counter_device_ext_show(struct device *dev,
>> + struct device_attribute *attr, char *buf)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct ext_comp_t *const component = devattr->component;
>> + const struct counter_device_ext *const ext = component->ext;
>> +
>> + return ext->read(dev_get_drvdata(dev), ext->priv, buf);
>> +}
>> +
>> +static ssize_t counter_device_ext_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf, size_t len)
>> +{
>> + const struct counter_device_attr *const devattr = to_counter_attr(attr);
>> + const struct ext_comp_t *const component = devattr->component;
>> + const struct counter_device_ext *const ext = component->ext;
>> +
>> + return ext->write(dev_get_drvdata(dev), ext->priv, buf, len);
>> +}
>> +
>> +static int counter_device_ext_register(
>> + struct counter_device_attr_group *const group,
>> + struct counter_device *const counter)
>> +{
>> + const size_t num_ext = counter->num_ext;
>
>num_ext only used in one place so if anything the local variable
>is hurting readability.
>
>> + struct ext_comp_t *ext_comp;
>> + size_t i;
>> + const struct counter_device_ext *ext;
>> + int err;
>> +
>> + /* Create an attribute for each extension */
>> + for (i = 0 ; i < num_ext; i++) {
>> + ext = counter->ext + i;
>
>This local variable isn't gaining us much that I can see. Just
>use the value directly.
>
>> +
>> + /* Allocate extension attribute component */
>> + ext_comp = kmalloc(sizeof(*ext_comp), GFP_KERNEL);
>> + if (!ext_comp) {
>> + err = -ENOMEM;
>> + goto err_free_attr_list;
>> + }
>> +
>> + ext_comp->ext = ext;
>> +
>> + /* Allocate extension attribute */
>> + err = counter_attribute_create(group, "", ext->name,
>> + (ext->read) ? counter_device_ext_show : NULL,
>> + (ext->write) ? counter_device_ext_store : NULL,
>> + ext_comp);
>> + if (err) {
>> + kfree(ext_comp);
>> + goto err_free_attr_list;
>> + }
>> + }
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +static int counter_global_attr_register(
>> + struct counter_device_attr_group *const group,
>> + struct counter_device *const counter)
>> +{
>> + int err;
>> +
>> + /* Create name attribute */
>> + err = counter_name_attribute_create(group, counter->name);
>> + if (err)
>> + return err;
>> +
>> + /* Create num_counts attribute */
>> + err = counter_size_attribute_create(group, counter->num_counts,
>> + "num_counts");
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + /* Create num_signals attribute */
>> + err = counter_size_attribute_create(group, counter->num_signals,
>> + "num_signals");
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + /* Register Counter device extension attributes */
>> + err = counter_device_ext_register(group, counter);
>> + if (err)
>> + goto err_free_attr_list;
>> +
>> + return 0;
>> +
>> +err_free_attr_list:
>> + free_counter_device_attr_list(&group->attr_list);
>> + return err;
>> +}
>> +
>> +static void free_counter_device_groups_list(
>> + struct counter_device_attr_group *const groups_list,
>> + const size_t num_groups)
>> +{
>> + struct counter_device_attr_group *group;
>> + size_t i;
>> +
>> + for (i = 0; i < num_groups; i++) {
>> + group = groups_list + i;
>> +
>
>I'd like to see a comment somewhere here on the fact this cleans up both
>the registered per counter stuff and the global attributes (that took
>a bit of chasing to check it did...)
>
>> + kfree(group->attr_group.name);
>> + kfree(group->attr_group.attrs);
>> + free_counter_device_attr_list(&group->attr_list);
>> + }
>> +
>> + kfree(groups_list);
>> +}
>> +
>> +static int prepare_counter_device_groups_list(
>> + struct counter_device *const counter)
>> +{
>> + const size_t total_num_groups =
>> + counter->num_signals + counter->num_counts + 1;
>> + struct counter_device_attr_group *groups_list;
>> + size_t i;
>> + int err;
>> + size_t num_groups = 0;
>> +
>> + /* Allocate space for attribute groups (signals. counts, and ext) */
>> + groups_list = kcalloc(total_num_groups, sizeof(*groups_list),
>> + GFP_KERNEL);
>> + if (!groups_list)
>> + return -ENOMEM;
>> +
>> + /* Initialize attribute lists */
>> + for (i = 0; i < total_num_groups; i++)
>> + INIT_LIST_HEAD(&groups_list[i].attr_list);
>> +
>> + /* Register Signals */
>> + err = counter_signals_register(groups_list, counter);
>> + if (err)
>> + goto err_free_groups_list;
>> + num_groups += counter->num_signals;
>> +
>> + /* Register Counts and respective Synapses */
>> + err = counter_counts_register(groups_list + num_groups, counter);
>> + if (err)
>> + goto err_free_groups_list;
>> + num_groups += counter->num_counts;
>> +
>> + /* Register Counter global attributes */
>> + err = counter_global_attr_register(groups_list + num_groups, counter);
>> + if (err)
>> + goto err_free_groups_list;
>> + num_groups++;
>> +
>> + /* Store groups_list in device_state */
>> + counter->device_state->groups_list = groups_list;
>> + counter->device_state->num_groups = num_groups;
>> +
>> + return 0;
>> +
>> +err_free_groups_list:
>> + free_counter_device_groups_list(groups_list, num_groups);
>
>Consistent naming would be good.
>
>counter_device_groups_list_free.
>
>I would tidy this up throughout. I know from experience that
>you'll probably end up doing so eventually and it is easier whilst
>there isn't too much code.
>
>> + return err;
>> +}
>> +
>> +static int prepare_counter_device_groups(
>> + struct counter_device_state *const device_state)
>> +{
>> + size_t i;
>> + struct counter_device_attr_group *group;
>> + int err;
>> + size_t j;
>
>Tidy this up a little,
>size_t i, j;
>
>> + struct counter_device_attr *p;
>> +
>> + /* Allocate attribute groups for association with device */
>> + device_state->groups = kcalloc(device_state->num_groups + 1,
>> + sizeof(*device_state->groups),
>> + GFP_KERNEL);
>> + if (!device_state->groups)
>> + return -ENOMEM;
>> +
>> + /* Prepare each group of attributes for association */
>> + for (i = 0; i < device_state->num_groups; i++) {
>> + group = device_state->groups_list + i;
>> +
>> + /* Allocate space for attribute pointers in attribute group */
>> + group->attr_group.attrs = kcalloc(group->num_attr + 1,
>> + sizeof(*group->attr_group.attrs), GFP_KERNEL);
>> + if (!group->attr_group.attrs) {
>> + err = -ENOMEM;
>> + goto err_free_groups;
>> + }
>> +
>> + /* Add attribute pointers to attribute group */
>> + j = 0;
>> + list_for_each_entry(p, &group->attr_list, l)
>> + group->attr_group.attrs[j++] = &p->dev_attr.attr;
>> +
>> + /* Group attributes in attribute group */
>> + device_state->groups[i] = &group->attr_group;
>> + }
>> + /* Associate attributes with device */
>> + device_state->dev.groups = device_state->groups;
>> +
>> + return 0;
>> +
>> +err_free_groups:
>
>I'm not convinced this is cleaning up properly. What about
>the kcalloc of group->attr_group.attrs for previous loops?
>
>> + kfree(device_state->groups);
>> + return err;
>> +}
>> +
>> +/* Provides a unique ID for each counter device */
>> +static DEFINE_IDA(counter_ida);
>> +
>> +static void counter_device_release(struct device *dev)
>> +{
>> + struct counter_device *const counter = dev_get_drvdata(dev);
>> + struct counter_device_state *const device_state = counter->device_state;
>> +
>> + kfree(device_state->groups);
>> + free_counter_device_groups_list(device_state->groups_list,
>> + device_state->num_groups);
>> + ida_simple_remove(&counter_ida, device_state->id);
>> + kfree(device_state);
>> +}
>> +
>> +static struct device_type counter_device_type = {
>> + .name = "counter_device",
>> + .release = counter_device_release
>> +};
>> +
>> +static struct bus_type counter_bus_type = {
>> + .name = "counter"
>> +};
>> +
>> +/**
>> + * counter_register - register Counter to the system
>> + * @counter: pointer to Counter to register
>> + *
>> + * This function registers a Counter to the system. A sysfs "counter" directory
>> + * will be created and populated with sysfs attributes correlating with the
>> + * Counter Signals, Synapses, and Counts respectively.
>> + */
>> +int counter_register(struct counter_device *const counter)
>> +{
>> + struct counter_device_state *device_state;
>> + int err;
>> +
>> + /* Allocate internal state container for Counter device */
>> + device_state = kzalloc(sizeof(*device_state), GFP_KERNEL);
>> + if (!device_state)
>> + return -ENOMEM;
>> + counter->device_state = device_state;
>> +
>> + /* Acquire unique ID */
>> + device_state->id = ida_simple_get(&counter_ida, 0, 0, GFP_KERNEL);
>> + if (device_state->id < 0) {
>> + err = device_state->id;
>> + goto err_free_device_state;
>> + }
>> +
>> + /* Configure device structure for Counter */
>> + device_state->dev.type = &counter_device_type;
>> + device_state->dev.bus = &counter_bus_type;
>> + if (counter->parent) {
>> + device_state->dev.parent = counter->parent;
>> + device_state->dev.of_node = counter->parent->of_node;
>> + }
>> + dev_set_name(&device_state->dev, "counter%d", device_state->id);
>> + device_initialize(&device_state->dev);
>> + dev_set_drvdata(&device_state->dev, counter);
>> +
>> + /* Prepare device attributes */
>> + err = prepare_counter_device_groups_list(counter);
>> + if (err)
>> + goto err_free_id;
>> +
>> + /* Organize device attributes to groups and match to device */
>> + err = prepare_counter_device_groups(device_state);
>> + if (err)
>> + goto err_free_groups_list;
>> +
>> + /* Add device to system */
>> + err = device_add(&device_state->dev);
>> + if (err)
>> + goto err_free_groups;
>> +
>> + return 0;
>> +
>> +err_free_groups:
>> + kfree(device_state->groups);
>> +err_free_groups_list:
>> + free_counter_device_groups_list(device_state->groups_list,
>> + device_state->num_groups);
>> +err_free_id:
>> + ida_simple_remove(&counter_ida, device_state->id);
>> +err_free_device_state:
>> + kfree(device_state);
>> + return err;
>> +}
>> +EXPORT_SYMBOL(counter_register);
>> +
>> +/**
>> + * counter_unregister - unregister Counter from the system
>> + * @counter: pointer to Counter to unregister
>> + *
>> + * The Counter is unregistered from the system; all allocated memory is freed.
>> + */
>> +void counter_unregister(struct counter_device *const counter)
>> +{
>> + if (counter)
>> + device_del(&counter->device_state->dev);
>> +}
>> +EXPORT_SYMBOL(counter_unregister);
>> +
>> +static void devm_counter_unreg(struct device *dev, void *res)
>> +{
>> + counter_unregister(*(struct counter_device **)res);
>> +}
>> +
>> +/**
>> + * devm_counter_register - Resource-managed counter_register
>> + * @dev: device to allocate counter_device for
>> + * @counter: pointer to Counter to register
>> + *
>> + * Managed counter_register. The Counter registered with this function is
>> + * automatically unregistered on driver detach. This function calls
>> + * counter_register internally. Refer to that function for more information.
>> + *
>> + * If an Counter registered with this function needs to be unregistered
>> + * separately, devm_counter_unregister must be used.
>> + *
>> + * RETURNS:
>> + * 0 on success, negative error number on failure.
>> + */
>> +int devm_counter_register(struct device *dev,
>> + struct counter_device *const counter)
>> +{
>> + struct counter_device **ptr;
>> + int ret;
>> +
>> + ptr = devres_alloc(devm_counter_unreg, sizeof(*ptr), GFP_KERNEL);
>> + if (!ptr)
>> + return -ENOMEM;
>> +
>> + ret = counter_register(counter);
>> + if (!ret) {
>> + *ptr = counter;
>> + devres_add(dev, ptr);
>> + } else {
>> + devres_free(ptr);
>> + }
>> +
>> + return ret;
>> +}
>> +EXPORT_SYMBOL(devm_counter_register);
>> +
>> +static int devm_counter_match(struct device *dev, void *res, void *data)
>> +{
>> + struct counter_device **r = res;
>> +
>> + if (!r || !*r) {
>> + WARN_ON(!r || !*r);
>> + return 0;
>> + }
>> +
>> + return *r == data;
>> +}
>> +
>> +/**
>> + * devm_counter_unregister - Resource-managed counter_unregister
>> + * @dev: device this counter_device belongs to
>> + * @counter: pointer to Counter associated with the device
>> + *
>> + * Unregister Counter registered with devm_counter_register.
>> + */
>> +void devm_counter_unregister(struct device *dev,
>> + struct counter_device *const counter)
>> +{
>> + int rc;
>> +
>> + rc = devres_release(dev, devm_counter_unreg, devm_counter_match,
>> + counter);
>> + WARN_ON(rc);
>> +}
>> +EXPORT_SYMBOL(devm_counter_unregister);
>> +
>> +static int __init counter_init(void)
>> +{
>> + return bus_register(&counter_bus_type);
>> +}
>> +
>> +static void __exit counter_exit(void)
>> +{
>> + bus_unregister(&counter_bus_type);
>> +}
>> +
>> +subsys_initcall(counter_init);
>> +module_exit(counter_exit);
>> +
>> +MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
>> +MODULE_DESCRIPTION("Generic Counter interface");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/include/linux/counter.h b/include/linux/counter.h
>> new file mode 100644
>> index 000000000000..a0b0349d098a
>> --- /dev/null
>> +++ b/include/linux/counter.h
>> @@ -0,0 +1,554 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Counter interface
>> + * Copyright (C) 2017 William Breathitt Gray
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License, version 2, as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * General Public License for more details.
>
>It's a bit controversial, but most people consider SPDX headers equivalent
>of the license statement. As such you normally don't have both and just
>go for the SPDK header.
>
>I thought we were also standardising on
>// SPDX-...
>
>
>> + */
>> +#ifndef _COUNTER_H_
>> +#define _COUNTER_H_
>> +
>> +#include <linux/device.h>
>> +#include <linux/types.h>
>> +
>> +enum count_direction {
>> + COUNT_DIRECTION_FORWARD = 0,
>> + COUNT_DIRECTION_BACKWARD
>> +};
>> +extern const char *const count_direction_str[2];
>> +
>> +enum count_mode {
>> + COUNT_MODE_NORMAL = 0,
>> + COUNT_MODE_RANGE_LIMIT,
>> + COUNT_MODE_NON_RECYCLE,
>> + COUNT_MODE_MODULO_N
>> +};
>> +extern const char *const count_mode_str[4];
>> +
>> +struct counter_device;
>> +struct counter_signal;
>> +
>> +/**
>> + * struct counter_signal_ext - Counter Signal extensions
>> + * @name: attribute name
>> + * @read: read callback for this attribute; may be NULL
>> + * @write: write callback for this attribute; may be NULL
>> + * @priv: data private to the driver
>> + */
>> +struct counter_signal_ext {
>> + const char *name;
>> + ssize_t (*read)(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + char *buf);
>> + ssize_t (*write)(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + const char *buf, size_t len);
>> + void *priv;
>> +};
>> +
>> +/**
>> + * struct counter_signal - Counter Signal node
>> + * @id: unique ID used to identify signal
>> + * @name: device-specific Signal name; ideally, this should match the name
>> + * as it appears in the datasheet documentation
>> + * @ext: optional array of Counter Signal extensions
>> + * @num_ext: number of Counter Signal extensions specified in @ext
>> + * @priv: optional private data supplied by driver
>> + */
>> +struct counter_signal {
>> + int id;
>> + const char *name;
>> +
>> + const struct counter_signal_ext *ext;
>> + size_t num_ext;
>> +
>> + void *priv;
>> +};
>> +
>> +/**
>> + * struct counter_signal_enum_ext - Signal enum extension attribute
>> + * @items: Array of strings
>> + * @num_items: Number of items specified in @items
>> + * @set: Set callback function; may be NULL
>> + * @get: Get callback function; may be NULL
>> + *
>> + * The counter_signal_enum_ext structure can be used to implement enum style
>> + * Signal extension attributes. Enum style attributes are those which have a set
>> + * of strings that map to unsigned integer values. The Generic Counter Signal
>> + * enum extension helper code takes care of mapping between value and string, as
>> + * well as generating a "_available" file which contains a list of all available
>> + * items. The get callback is used to query the currently active item; the index
>> + * of the item within the respective items array is returned via the 'item'
>> + * parameter. The set callback is called when the attribute is updated; the
>> + * 'item' parameter contains the index of the newly activated item within the
>> + * respective items array.
>> + */
>> +struct counter_signal_enum_ext {
>> + const char * const *items;
>> + size_t num_items;
>> + int (*get)(struct counter_device *counter,
>> + struct counter_signal *signal,
>> + size_t *item);
>> + int (*set)(struct counter_device *counter,
>> + struct counter_signal *signal,
>> + size_t item);
>> +};
>> +
>> +ssize_t counter_signal_enum_read(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + char *buf);
>> +ssize_t counter_signal_enum_write(struct counter_device *counter,
>> + struct counter_signal *signal, void *priv,
>> + const char *buf, size_t len);
>> +
>> +/**
>> + * COUNTER_SIGNAL_ENUM() - Initialize Signal enum extension
>> + * @_name: Attribute name
>> + * @_e: Pointer to a counter_count_enum structure
>> + *
>> + * This should usually be used together with COUNTER_SIGNAL_ENUM_AVAILABLE()
>> + */
>> +#define COUNTER_SIGNAL_ENUM(_name, _e) \
>> +{ \
>> + .name = (_name), \
>> + .read = counter_signal_enum_read, \
>> + .write = counter_signal_enum_write, \
>> + .priv = (_e) \
>> +}
>> +
>> +ssize_t counter_signal_enum_available_read(struct counter_device *counter,
>> + struct counter_signal *signal,
>> + void *priv, char *buf);
>> +
>> +/**
>> + * COUNTER_SIGNAL_ENUM_AVAILABLE() - Initialize Signal enum available extension
>> + * @_name: Attribute name ("_available" will be appended to the name)
>> + * @_e: Pointer to a counter_signal_enum structure
>> + *
>> + * Creates a read only attribute that lists all the available enum items in a
>> + * newline separated list. This should usually be used together with
>> + * COUNTER_SIGNAL_ENUM()
>> + */
>> +#define COUNTER_SIGNAL_ENUM_AVAILABLE(_name, _e) \
>> +{ \
>> + .name = (_name "_available"), \
>> + .read = counter_signal_enum_available_read, \
>> + .priv = (_e) \
>> +}
>> +
>> +enum synapse_action {
>> + SYNAPSE_ACTION_NONE = 0,
>> + SYNAPSE_ACTION_RISING_EDGE,
>> + SYNAPSE_ACTION_FALLING_EDGE,
>> + SYNAPSE_ACTION_BOTH_EDGES
>> +};
>> +
>> +/**
>> + * struct counter_synapse - Counter Synapse node
>> + * @action: index of current action mode
>> + * @actions_list: array of available action modes
>> + * @num_actions: number of action modes specified in @actions_list
>> + * @signal: pointer to associated signal
>> + */
>> +struct counter_synapse {
>> + size_t action;
>> + const enum synapse_action *actions_list;
>> + size_t num_actions;
>> +
>> + struct counter_signal *signal;
>> +};
>> +
>> +struct counter_count;
>> +
>> +/**
>> + * struct counter_count_ext - Counter Count extension
>> + * @name: attribute name
>> + * @read: read callback for this attribute; may be NULL
>> + * @write: write callback for this attribute; may be NULL
>> + * @priv: data private to the driver
>> + */
>> +struct counter_count_ext {
>> + const char *name;
>> + ssize_t (*read)(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + char *buf);
>> + ssize_t (*write)(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + const char *buf, size_t len);
>> + void *priv;
>> +};
>> +
>> +enum count_function {
>> + COUNT_FUNCTION_INCREASE = 0,
>> + COUNT_FUNCTION_DECREASE,
>> + COUNT_FUNCTION_PULSE_DIRECTION,
>> + COUNT_FUNCTION_QUADRATURE_X1_A,
>> + COUNT_FUNCTION_QUADRATURE_X1_B,
>> + COUNT_FUNCTION_QUADRATURE_X2_A,
>> + COUNT_FUNCTION_QUADRATURE_X2_B,
>> + COUNT_FUNCTION_QUADRATURE_X2_RISING,
>> + COUNT_FUNCTION_QUADRATURE_X2_FALLING,
>> + COUNT_FUNCTION_QUADRATURE_X4
>> +};
>> +
>> +/**
>> + * struct counter_count - Counter Count node
>> + * @id: unique ID used to identify Count
>> + * @name: device-specific Count name; ideally, this should match
>> + * the name as it appears in the datasheet documentation
>> + * @function: index of current function mode
>> + * @functions_list: array available function modes
>> + * @num_functions: number of function modes specified in @functions_list
>> + * @synapses: array of synapses for initialization
>> + * @num_synapses: number of synapses specified in @synapses
>> + * @ext: optional array of Counter Count extensions
>> + * @num_ext: number of Counter Count extensions specified in @ext
>> + * @priv: optional private data supplied by driver
>> + */
>> +struct counter_count {
>> + int id;
>> + const char *name;
>> +
>> + size_t function;
>> + const enum count_function *functions_list;
>> + size_t num_functions;
>
>There is a very good illustration here of the issues with using
>tabs to pretty print structure elements. I would drop them entirely as
>personally I'm not sure they help readability and you will forever be having
>more noise in patches because of the need to change the number of tabs
>due to name changes etc.
>
>> +
>> + struct counter_synapse *synapses;
>> + size_t num_synapses;
>> +
>> + const struct counter_count_ext *ext;
>> + size_t num_ext;
>> +
>> + void *priv;
>> +};
>> +
>> +/**
>> + * struct counter_count_enum_ext - Count enum extension attribute
>> + * @items: Array of strings
>> + * @num_items: Number of items specified in @items
>> + * @set: Set callback function; may be NULL
>> + * @get: Get callback function; may be NULL
>> + *
>> + * The counter_count_enum_ext structure can be used to implement enum style
>> + * Count extension attributes. Enum style attributes are those which have a set
>> + * of strings that map to unsigned integer values. The Generic Counter Count
>> + * enum extension helper code takes care of mapping between value and string, as
>> + * well as generating a "_available" file which contains a list of all available
>> + * items. The get callback is used to query the currently active item; the index
>> + * of the item within the respective items array is returned via the 'item'
>> + * parameter. The set callback is called when the attribute is updated; the
>> + * 'item' parameter contains the index of the newly activated item within the
>> + * respective items array.
>> + */
>> +struct counter_count_enum_ext {
>> + const char * const *items;
>> + size_t num_items;
>> + int (*get)(struct counter_device *counter,
>> + struct counter_count *count,
>> + size_t *item);
>> + int (*set)(struct counter_device *counter,
>> + struct counter_count *count,
>> + size_t item);
>> +};
>> +
>> +ssize_t counter_count_enum_read(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + char *buf);
>> +ssize_t counter_count_enum_write(struct counter_device *counter,
>> + struct counter_count *count, void *priv,
>> + const char *buf, size_t len);
>> +
>> +/**
>> + * COUNTER_COUNT_ENUM() - Initialize Count enum extension
>> + * @_name: Attribute name
>> + * @_e: Pointer to a counter_count_enum structure
>> + *
>> + * This should usually be used together with COUNTER_COUNT_ENUM_AVAILABLE()
>> + */
>> +#define COUNTER_COUNT_ENUM(_name, _e) \
>> +{ \
>> + .name = (_name), \
>> + .read = counter_count_enum_read, \
>> + .write = counter_count_enum_write, \
>> + .priv = (_e) \
>> +}
>> +
>> +ssize_t counter_count_enum_available_read(struct counter_device *counter,
>> + struct counter_count *count,
>> + void *priv, char *buf);
>> +
>> +/**
>> + * COUNTER_COUNT_ENUM_AVAILABLE() - Initialize Count enum available extension
>> + * @_name: Attribute name ("_available" will be appended to the name)
>> + * @_e: Pointer to a counter_count_enum structure
>> + *
>> + * Creates a read only attribute that lists all the available enum items in a
>> + * newline separated list. This should usually be used together with
>> + * COUNTER_COUNT_ENUM()
>> + */
>> +#define COUNTER_COUNT_ENUM_AVAILABLE(_name, _e) \
>> +{ \
>> + .name = (_name "_available"), \
>> + .read = counter_count_enum_available_read, \
>> + .priv = (_e) \
>> +}
>> +
>> +/**
>> + * struct counter_device_attr_group - internal container for attribute group
>> + * @attr_group: Counter sysfs attributes group
>> + * @attr_list: list to keep track of created Counter sysfs attributes
>> + * @num_attr: number of Counter sysfs attributes
>> + */
>> +struct counter_device_attr_group {
>> + struct attribute_group attr_group;
>> + struct list_head attr_list;
>> + size_t num_attr;
>> +};
>> +
>> +/**
>> + * struct counter_device_state - internal state container for a Counter device
>> + * @id: unique ID used to identify the Counter
>> + * @dev: internal device structure
>> + * @groups_list attribute groups list (groups for Signals, Counts, and ext)
>
>Run kernel-doc script over these files. You are missing some :s and it would
>have told you that.
>
>> + * @num_groups number of attribute groups containers
>> + * @groups: Counter sysfs attribute groups (used to populate @dev.groups)
>> + */
>> +struct counter_device_state {
>> + int id;
>> + struct device dev;
>> + struct counter_device_attr_group *groups_list;
>> + size_t num_groups;
>> + const struct attribute_group **groups;
>> +};
>> +
>> +/**
>> + * struct signal_read_value - Opaque Signal read value
>> + * @buf: string representation of Signal read value
>> + * @len: length of string in @buf
>> + */
>> +struct signal_read_value {
>> + char *buf;
>> + size_t len;
>> +};
>> +
>> +/**
>> + * struct count_read_value - Opaque Count read value
>> + * @buf: string representation of Count read value
>> + * @len: length of string in @buf
>> + */
>> +struct count_read_value {
>> + char *buf;
>> + size_t len;
>> +};
>> +
>> +/**
>> + * struct count_write_value - Opaque Count write value
>> + * @buf: string representation of Count write value
>> + */
>> +struct count_write_value {
>> + const char *buf;
>> +};
>> +
>> +/**
>> + * struct counter_ops - Callbacks from driver
>> + * @signal_read: optional read callback for Signal attribute. The read
>> + * value of the respective Signal should be passed back via
>> + * the val parameter. val points to an opaque type which
>> + * should be set only via the set_signal_read_value
>> + * function.
>
>This last part had me a little confused. I would make it clear that this
>set_signal_read_value function should be called to set the value within this
>signal_read callback rather than elsewhere...
>
>> + * @count_read: optional read callback for Count attribute. The read
>> + * value of the respective Count should be passed back via
>> + * the val parameter. val points to an opaque type which
>> + * should be set only via the set_count_read_value
>> + * function.
>> + * @count_write: optional write callback for Count attribute. The write
>> + * value for the respective Count is passed in via the val
>> + * parameter. val points to an opaque type which should be
>> + * access only via the get_count_write_value function.
>> + * @function_get: function to get the current count function mode. Returns
>> + * 0 on success and negative error code on error. The index
>> + * of the respective Count's returned function mode should
>> + * be passed back via the function parameter.
>> + * @function_set: function to set the count function mode. function is the
>> + * index of the requested function mode from the respective
>> + * Count's functions_list array.
>> + * @action_get: function to get the current action mode. Returns 0 on
>> + * success and negative error code on error. The index of
>> + * the respective Signal's returned action mode should be
>> + * passed back via the action parameter.
>> + * @action_set: function to set the action mode. action is the index of
>> + * the requested action mode from the respective Synapse's
>> + * actions_list array.
>> + */
>> +struct counter_ops {
>> + int (*signal_read)(struct counter_device *counter,
>> + struct counter_signal *signal,
>> + struct signal_read_value *val);
>> + int (*count_read)(struct counter_device *counter,
>> + struct counter_count *count,
>> + struct count_read_value *val);
>> + int (*count_write)(struct counter_device *counter,
>> + struct counter_count *count,
>> + struct count_write_value *val);
>> + int (*function_get)(struct counter_device *counter,
>> + struct counter_count *count, size_t *function);
>> + int (*function_set)(struct counter_device *counter,
>> + struct counter_count *count, size_t function);
>> + int (*action_get)(struct counter_device *counter,
>> + struct counter_count *count,
>> + struct counter_synapse *synapse, size_t *action);
>> + int (*action_set)(struct counter_device *counter,
>> + struct counter_count *count,
>> + struct counter_synapse *synapse, size_t action);
>> +};
>> +
>> +/**
>> + * struct counter_device_ext - Counter device extension
>> + * @name: attribute name
>> + * @read: read callback for this attribute; may be NULL
>> + * @write: write callback for this attribute; may be NULL
>> + * @priv: data private to the driver
>> + */
>> +struct counter_device_ext {
>> + const char *name;
>> + ssize_t (*read)(struct counter_device *counter, void *priv,
>> + char *buf);
>> + ssize_t (*write)(struct counter_device *counter, void *priv,
>> + const char *buf, size_t len);
>> + void *priv;
>> +};
>> +
>> +/**
>> + * struct counter_device_enum_ext - Counter enum extension attribute
>> + * @items: Array of strings
>> + * @num_items: Number of items specified in @items
>> + * @set: Set callback function; may be NULL
>> + * @get: Get callback function; may be NULL
>> + *
>> + * The counter_device_enum_ext structure can be used to implement enum style
>> + * Counter extension attributes. Enum style attributes are those which have a
>> + * set of strings that map to unsigned integer values. The Generic Counter enum
>> + * extension helper code takes care of mapping between value and string, as well
>> + * as generating a "_available" file which contains a list of all available
>> + * items. The get callback is used to query the currently active item; the index
>> + * of the item within the respective items array is returned via the 'item'
>> + * parameter. The set callback is called when the attribute is updated; the
>> + * 'item' parameter contains the index of the newly activated item within the
>> + * respective items array.
>> + */
>> +struct counter_device_enum_ext {
>> + const char * const *items;
>> + size_t num_items;
>> + int (*get)(struct counter_device *counter,
>> + size_t *item);
>> + int (*set)(struct counter_device *counter,
>> + size_t item);
>> +};
>> +
>> +ssize_t counter_device_enum_read(struct counter_device *counter, void *priv,
>> + char *buf);
>> +ssize_t counter_device_enum_write(struct counter_device *counter, void *priv,
>> + const char *buf, size_t len);
>> +
>> +/**
>> + * COUNTER_DEVICE_ENUM() - Initialize Counter enum extension
>> + * @_name: Attribute name
>> + * @_e: Pointer to a counter_device_enum structure
>> + *
>> + * This should usually be used together with COUNTER_DEVICE_ENUM_AVAILABLE()
>> + */
>> +#define COUNTER_DEVICE_ENUM(_name, _e) \
>> +{ \
>> + .name = (_name), \
>> + .read = counter_device_enum_read, \
>> + .write = counter_device_enum_write, \
>> + .priv = (_e) \
>> +}
>> +
>> +ssize_t counter_device_enum_available_read(struct counter_device *counter,
>> + void *priv, char *buf);
>> +
>> +/**
>> + * COUNTER_DEVICE_ENUM_AVAILABLE() - Initialize Counter enum available extension
>> + * @_name: Attribute name ("_available" will be appended to the name)
>> + * @_e: Pointer to a counter_device_enum structure
>> + *
>> + * Creates a read only attribute that lists all the available enum items in a
>> + * newline separated list. This should usually be used together with
>> + * COUNTER_DEVICE_ENUM()
>> + */
>> +#define COUNTER_DEVICE_ENUM_AVAILABLE(_name, _e) \
>> +{ \
>> + .name = (_name "_available"), \
>> + .read = counter_device_enum_available_read, \
>> + .priv = (_e) \
>> +}
>> +
>> +/**
>> + * struct counter_device - Counter data structure
>> + * @name: name of the device as it appears in the datasheet
>> + * @parent: optional parent device providing the counters
>> + * @device_state: internal device state container
>> + * @ops: callbacks from driver
>> + * @signals: array of Signals
>> + * @num_signals: number of Signals specified in @signals
>> + * @counts: array of Counts
>> + * @num_counts: number of Counts specified in @counts
>> + * @ext: optional array of Counter device extensions
>> + * @num_ext: number of Counter device extensions specified in @ext
>> + * @priv: optional private data supplied by driver
>> + */
>> +struct counter_device {
>> + const char *name;
>> + struct device *parent;
>> + struct counter_device_state *device_state;
>> +
>> + const struct counter_ops *ops;
>> +
>> + struct counter_signal *signals;
>> + size_t num_signals;
>> + struct counter_count *counts;
>> + size_t num_counts;
>> +
>> + const struct counter_device_ext *ext;
>> + size_t num_ext;
>> +
>> + void *priv;
>> +};
>> +
>> +enum signal_level {
>> + SIGNAL_LEVEL_LOW = 0,
>> + SIGNAL_LEVEL_HIGH
>> +};
>> +
>> +enum signal_value_type {
>> + SIGNAL_LEVEL = 0
>> +};
>> +
>> +enum count_value_type {
>> + COUNT_POSITION_UNSIGNED = 0,
>> + COUNT_POSITION_SIGNED
>> +};
>> +
>> +void set_signal_read_value(struct signal_read_value *const val,
>> + const enum signal_value_type type, void *const data);
>> +void set_count_read_value(struct count_read_value *const val,
>> + const enum count_value_type type, void *const data);
>> +int get_count_write_value(void *const data, const enum count_value_type type,
>> + const struct count_write_value *const val);
>
>I wonder if naming wise, we would be better sticking to the
>noun_verb naming format.
>
>signal_read_value_set
>count_read_value_set
>count_write_value_get
>
>for example?
>
>> +
>> +int counter_register(struct counter_device *const counter);
>> +void counter_unregister(struct counter_device *const counter);
>> +int devm_counter_register(struct device *dev,
>> + struct counter_device *const counter);
>> +void devm_counter_unregister(struct device *dev,
>> + struct counter_device *const counter);
>> +
>> +#endif /* _COUNTER_H_ */
>
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: Sudeep Holla @ 2018-05-21 13:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000f01d3f103$3ff78ba0$bfe6a2e0$@codeaurora.org>
On 21/05/18 13:57, ilialin at codeaurora.org wrote:
>
[...]
>>> +#include <linux/cpu.h>
>>> +#include <linux/err.h>
>>> +#include <linux/init.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/nvmem-consumer.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/pm_opp.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/soc/qcom/smem.h>
>>> +
>>> +#define MSM_ID_SMEM 137
>>> +#define SILVER_LEAD 0
>>> +#define GOLD_LEAD 2
>>> +
>>
>> So I gather form other emails, that these are physical cpu number(not even
>> unique identifier like MPIDR). Will this work on parts or platforms that need
>> to boot in GOLD LEAD cpus.
>
> The driver is for Kryo CPU, which (and AFAIK all multicore MSMs)
> always boots on the CPU0.
That may be true and I am not that bothered about it. But assuming
physical ordering from the logical cpu number is *incorrect* and will
break if kernel decides to change the allocation algorithm. Kernel
provides no guarantee on that, so you need to depend on some physical ID
or may be DT to achieve what your want. But the current code as it
stands is wrong.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 00/27] Add multi-channel and overheat IRQ support to Armada thermal driver
From: Zhang Rui @ 2018-05-21 13:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518114935.38d6e883@xps13>
On ?, 2018-05-18 at 11:49 +0200, Miquel Raynal wrote:
> Hi Zhang, Eduardo & Gregory,
>
> On Wed, 16 May 2018 19:28:45 +0200, Gregory CLEMENT
> <gregory.clement@bootlin.com> wrote:
>
> >
> > Hi Miquel,
> > ?
> > ?On sam., avril 21 2018, Miquel Raynal <miquel.raynal@bootlin.com>
> > wrote:
> >
> > >
> > > The only capability of the Armada thermal driver is currently
> > > just to
> > > read one sensor (the default one) per AP and one per CP.
> > >
> > > Actually, there is one sensor per core in the AP806 plus one
> > > sensor in
> > > the thermal IP itself. The CP110 just features one thermal sensor
> > > in its
> > > own thermal IP.
> > >
> > > Also, there is no need for the thermal core to poll the
> > > temperature of
> > > each sensor by software as this IP (at least for AP806 and CP110
> > > compatibles) features an hardware overheat interrupt.
> > >
> > > This series first improves the readability of this driver, then
> > > adds
> > > support for multi-channel thermal IPs, and finally adds support
> > > for the
> > > hardware overheat interrupt. The bindings and the device-trees
> > > are
> > > updated accordingly.
> > >
> > > Please note that the thermal IP raises SEI interrupts, from which
> > > the
> > > support as just been contributed and not merged yet. Applying the
> > > last
> > > DT patches referring to the 'sei' and 'icu_sei' nodes will
> > > require this
> > > feature [1] to have been accepted first.
> > >
> > > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-Ap
> > > ril/572852.html
> > >
> > > Thank you,
> > > Miqu?l
> > >
> > >
> > > Miquel Raynal (27):
> > > ? thermal: armada: add a function that sanitizes the thermal zone
> > > name
> > > ? thermal: armada: remove useless register accesses
> > > ? thermal: armada: remove misleading comments
> > > ? thermal: armada: rename the initialization routine
> > > ? thermal: armada: dissociate a380 and cp110 ->init() hooks
> > > ? thermal: armada: average over samples to avoid glitches
> > > ? thermal: armada: convert driver to syscon register accesses
> > > ? thermal: armada: use the resource managed registration helper
> > > ????alternative
> > > ? thermal: armada: add multi-channel sensors support
> > > ? thermal: armada: remove sensors validity from the IP
> > > initialization
> > > ? thermal: armada: move validity check out of the read function
> > > ? thermal: armada: get rid of the ->is_valid() pointer
> > > ? thermal: armada: add overheat interrupt support
> > > ? dt-bindings: cp110: rename cp110 syscon file
> > > ? dt-bindings: ap806: prepare the syscon file to list other
> > > syscons
> > > ????nodes
> > > ? dt-bindings: cp110: prepare the syscon file to list other
> > > syscons
> > > ????nodes
> > > ? dt-bindings: ap806: add the thermal node in the syscon file
> > > ? dt-bindings: cp110: update documentation since DT de-
> > > duplication
> > > ? dt-bindings: cp110: add the thermal node in the syscon file
> > > ? dt-bindings: thermal: armada: add reference to new bindings
> > > ? arm64: dts: marvell: rename ap806 syscon node
> > > ? arm64: dts: marvell: move AP806/CP110 thermal nodes into a new
> > > syscon
> > > ? arm64: dts: marvell: add thermal-zone node in ap806 DTSI file
> > > ? arm64: dts: marvell: add macro to make distinction between node
> > > names
> > > ? arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
> > > ? arm64: dts: marvell: add interrupt support to ap806 thermal
> > > node
> > > ? arm64: dts: marvell: add interrupt support to cp110 thermal
> > > node
> > >
> > > ?.../arm/marvell/ap806-system-controller.txt????????|??55 +-
> > > ?...controller0.txt => cp110-system-controller.txt} |??66 +-
> > > ?.../devicetree/bindings/thermal/armada-thermal.txt |???5 +
> > > ?arch/arm64/boot/dts/marvell/armada-ap806.dtsi??????|??85 +-
> > > ?arch/arm64/boot/dts/marvell/armada-common.dtsi?????|???1 +
> > > ?arch/arm64/boot/dts/marvell/armada-cp110.dtsi??????|??45 +-
> > > ?drivers/thermal/armada_thermal.c???????????????????| 875
> > > ++++++++++++++++++---
> > > ?7 files changed, 976 insertions(+), 156 deletions(-)
> > > ?rename Documentation/devicetree/bindings/arm/marvell/{cp110-
> > > system-controller0.txt => cp110-system-controller.txt} (83%)??
> > What is the status of this series?
> > I am especially interested in the dt part.
> > Do you expect sending a new series modifying them?
> I have not received any feedback yet on the thermal part, bindings
> have
> been partially acked by Rob (one request, I will probably add a reg
> property in the AP node) so please do not take the DTS changes of
> this iteration.
>
> Zhang, Eduardo, could you please share the status of this series?
>
hmmm, this should go through Eduardo' thermal-soc tree, thus I'd expect
Eduardo to review this patch set.
Eduardo, what's your comments for this series?
thanks,
rui
> Thanks,
> Miqu?l
>
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: ilialin at codeaurora.org @ 2018-05-21 12:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <153cc316-dcb5-972f-5a2f-c91fe0f6348b@arm.com>
> -----Original Message-----
> From: Sudeep Holla <sudeep.holla@arm.com>
> Sent: Monday, May 21, 2018 15:50
> To: Ilia Lin <ilialin@codeaurora.org>; mturquette at baylibre.com;
> sboyd at kernel.org; robh at kernel.org; mark.rutland at arm.com;
> viresh.kumar at linaro.org; nm at ti.com; lgirdwood at gmail.com;
> broonie at kernel.org; andy.gross at linaro.org; david.brown at linaro.org;
> catalin.marinas at arm.com; will.deacon at arm.com; rjw at rjwysocki.net; linux-
> clk at vger.kernel.org
> Cc: Sudeep Holla <sudeep.holla@arm.com>; devicetree at vger.kernel.org;
> linux-kernel at vger.kernel.org; linux-pm at vger.kernel.org; linux-arm-
> msm at vger.kernel.org; linux-soc at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; rnayak at codeaurora.org;
> amit.kucheria at linaro.org; nicolas.dechesne at linaro.org;
> celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH] cpufreq: Add Kryo CPU scaling driver
>
>
>
> On 19/05/18 12:35, Ilia Lin wrote:
> > In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO
> > processors, the CPU frequency subset and voltage value of each OPP
> > varies based on the silicon variant in use. Qualcomm Process Voltage
> > Scaling Tables defines the voltage and frequency value based on the
> > msm-id in SMEM and speedbin blown in the efuse combination.
> > The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the
> > SoC to provide the OPP framework with required information.
> > This is used to determine the voltage and frequency value for each OPP
> > of
> > operating-points-v2 table when it is parsed by the OPP framework.
> >
> > Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> > ---
> > drivers/cpufreq/Kconfig.arm | 10 +++
> > drivers/cpufreq/Makefile | 1 +
> > drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> > drivers/cpufreq/qcom-cpufreq-kryo.c | 164
> > +++++++++++++++++++++++++++++++++++
> > 4 files changed, 178 insertions(+)
> > create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
> >
>
> [..]
>
> > +
> > +/*
> > + * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO
> > +processors,
> > + * the CPU frequency subset and voltage value of each OPP varies
> > + * based on the silicon variant in use. Qualcomm Process Voltage
> > +Scaling Tables
> > + * defines the voltage and frequency value based on the msm-id in
> > +SMEM
> > + * and speedbin blown in the efuse combination.
> > + * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from
> > +the SoC
> > + * to provide the OPP framework with required information.
> > + * This is used to determine the voltage and frequency value for each
> > +OPP of
> > + * operating-points-v2 table when it is parsed by the OPP framework.
> > + */
> > +
> > +#include <linux/cpu.h>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_opp.h>
> > +#include <linux/slab.h>
> > +#include <linux/soc/qcom/smem.h>
> > +
> > +#define MSM_ID_SMEM 137
> > +#define SILVER_LEAD 0
> > +#define GOLD_LEAD 2
> > +
>
> So I gather form other emails, that these are physical cpu number(not even
> unique identifier like MPIDR). Will this work on parts or platforms that need
> to boot in GOLD LEAD cpus.
The driver is for Kryo CPU, which (and AFAIK all multicore MSMs) always boots on the CPU0.
>
> [...]
>
> > +
> > +static int __init qcom_cpufreq_kryo_driver_init(void)
> > +{
> > + struct device *cpu_dev_silver, *cpu_dev_gold;
> > + struct opp_table *opp_silver, *opp_gold;
> > + enum _msm8996_version msm8996_version;
> > + struct nvmem_cell *speedbin_nvmem;
> > + struct platform_device *pdev;
> > + struct device_node *np;
> > + u8 *speedbin;
> > + u32 versions;
> > + size_t len;
> > + int ret;
> > +
> > + cpu_dev_silver = get_cpu_device(SILVER_LEAD);
> > + if (IS_ERR_OR_NULL(cpu_dev_silver))
> > + return PTR_ERR(cpu_dev_silver);
> > +
> > + cpu_dev_gold = get_cpu_device(SILVER_LEAD);
>
> s/SILVER/GOLD/ ?
Yes, you are right. This is already fixed in the respin.
>
> --
> Regards,
> Sudeep
^ permalink raw reply
* [PATCH v2] drivers: base: cacheinfo: use OF property_read_u32 instead of get_property, read_number
From: Sudeep Holla @ 2018-05-21 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526898749-17263-1-git-send-email-sudeep.holla@arm.com>
of_property_read_u32 searches for a property in a device node and read
a 32-bit value from it. Instead of using of_get_property to get the
property and then read 32-bit value using of_read_number, we can
simplify it by using of_property_read_u32.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
drivers/base/cacheinfo.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
Hi Andy,
Ignore my comment on compile errors error with Werror=incompatible-pointer-types
I was so hung up on _u64 version and didn't realise that we were using 32-bit
with of_read_number originally.
Regards,
Sudeep
v1->v2:
- Replaced use of of_property_read_u64 with of_property_read_u32
- Also removed the local variables as Andy initially suggested
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 2880e2ab01f5..5d5b5988e88b 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -74,52 +74,48 @@ static inline int get_cacheinfo_idx(enum cache_type type)
static void cache_size(struct cacheinfo *this_leaf, struct device_node *np)
{
const char *propname;
- const __be32 *cache_size;
int ct_idx;
ct_idx = get_cacheinfo_idx(this_leaf->type);
propname = cache_type_info[ct_idx].size_prop;
- cache_size = of_get_property(np, propname, NULL);
- if (cache_size)
- this_leaf->size = of_read_number(cache_size, 1);
+ if (of_property_read_u32(np, propname, &this_leaf->size))
+ this_leaf->size = 0;
}
/* not cache_line_size() because that's a macro in include/linux/cache.h */
static void cache_get_line_size(struct cacheinfo *this_leaf,
struct device_node *np)
{
- const __be32 *line_size;
int i, lim, ct_idx;
ct_idx = get_cacheinfo_idx(this_leaf->type);
lim = ARRAY_SIZE(cache_type_info[ct_idx].line_size_props);
for (i = 0; i < lim; i++) {
+ int ret;
+ u32 line_size;
const char *propname;
propname = cache_type_info[ct_idx].line_size_props[i];
- line_size = of_get_property(np, propname, NULL);
- if (line_size)
+ ret = of_property_read_u32(np, propname, &line_size);
+ if (!ret) {
+ this_leaf->coherency_line_size = line_size;
break;
+ }
}
-
- if (line_size)
- this_leaf->coherency_line_size = of_read_number(line_size, 1);
}
static void cache_nr_sets(struct cacheinfo *this_leaf, struct device_node *np)
{
const char *propname;
- const __be32 *nr_sets;
int ct_idx;
ct_idx = get_cacheinfo_idx(this_leaf->type);
propname = cache_type_info[ct_idx].nr_sets_prop;
- nr_sets = of_get_property(np, propname, NULL);
- if (nr_sets)
- this_leaf->number_of_sets = of_read_number(nr_sets, 1);
+ if (of_property_read_u32(np, propname, &this_leaf->number_of_sets))
+ this_leaf->number_of_sets = 0;
}
static void cache_associativity(struct cacheinfo *this_leaf)
--
2.7.4
^ permalink raw reply related
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: Sudeep Holla @ 2018-05-21 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526729701-8589-1-git-send-email-ilialin@codeaurora.org>
On 19/05/18 12:35, Ilia Lin wrote:
> In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> the CPU frequency subset and voltage value of each OPP varies
> based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> drivers/cpufreq/Kconfig.arm | 10 +++
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> drivers/cpufreq/qcom-cpufreq-kryo.c | 164 +++++++++++++++++++++++++++++++++++
> 4 files changed, 178 insertions(+)
> create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>
[..]
> +
> +/*
> + * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> + * the CPU frequency subset and voltage value of each OPP varies
> + * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
> + * defines the voltage and frequency value based on the msm-id in SMEM
> + * and speedbin blown in the efuse combination.
> + * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> + * to provide the OPP framework with required information.
> + * This is used to determine the voltage and frequency value for each OPP of
> + * operating-points-v2 table when it is parsed by the OPP framework.
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/slab.h>
> +#include <linux/soc/qcom/smem.h>
> +
> +#define MSM_ID_SMEM 137
> +#define SILVER_LEAD 0
> +#define GOLD_LEAD 2
> +
So I gather form other emails, that these are physical cpu number(not
even unique identifier like MPIDR). Will this work on parts or platforms
that need to boot in GOLD LEAD cpus.
[...]
> +
> +static int __init qcom_cpufreq_kryo_driver_init(void)
> +{
> + struct device *cpu_dev_silver, *cpu_dev_gold;
> + struct opp_table *opp_silver, *opp_gold;
> + enum _msm8996_version msm8996_version;
> + struct nvmem_cell *speedbin_nvmem;
> + struct platform_device *pdev;
> + struct device_node *np;
> + u8 *speedbin;
> + u32 versions;
> + size_t len;
> + int ret;
> +
> + cpu_dev_silver = get_cpu_device(SILVER_LEAD);
> + if (IS_ERR_OR_NULL(cpu_dev_silver))
> + return PTR_ERR(cpu_dev_silver);
> +
> + cpu_dev_gold = get_cpu_device(SILVER_LEAD);
s/SILVER/GOLD/ ?
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver
From: Ganapatrao Kulkarni @ 2018-05-21 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521104008.z6ei5zjve7u5iwho@lakrids.cambridge.arm.com>
On Mon, May 21, 2018 at 4:10 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote:
>> Hi Ganapat,
>>
>>
>> Sorry for the delay in replying; I was away most of last week.
>>
>> On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote:
>> > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni <gklkml16@gmail.com> wrote:
>> > > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> > >> On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
>>
>> > >>> +static int alloc_counter(struct thunderx2_pmu_uncore_channel *pmu_uncore)
>> > >>> +{
>> > >>> + int counter;
>> > >>> +
>> > >>> + raw_spin_lock(&pmu_uncore->lock);
>> > >>> + counter = find_first_zero_bit(pmu_uncore->counter_mask,
>> > >>> + pmu_uncore->uncore_dev->max_counters);
>> > >>> + if (counter == pmu_uncore->uncore_dev->max_counters) {
>> > >>> + raw_spin_unlock(&pmu_uncore->lock);
>> > >>> + return -ENOSPC;
>> > >>> + }
>> > >>> + set_bit(counter, pmu_uncore->counter_mask);
>> > >>> + raw_spin_unlock(&pmu_uncore->lock);
>> > >>> + return counter;
>> > >>> +}
>> > >>> +
>> > >>> +static void free_counter(struct thunderx2_pmu_uncore_channel *pmu_uncore,
>> > >>> + int counter)
>> > >>> +{
>> > >>> + raw_spin_lock(&pmu_uncore->lock);
>> > >>> + clear_bit(counter, pmu_uncore->counter_mask);
>> > >>> + raw_spin_unlock(&pmu_uncore->lock);
>> > >>> +}
>> > >>
>> > >> I don't believe that locking is required in either of these, as the perf
>> > >> core serializes pmu::add() and pmu::del(), where these get called.
>> >
>> > without this locking, i am seeing "BUG: scheduling while atomic" when
>> > i run perf with more events together than the maximum counters
>> > supported
>>
>> Did you manage to get to the bottom of this?
>>
>> Do you have a backtrace?
>>
>> It looks like in your latest posting you reserve counters through the
>> userspace ABI, which doesn't seem right to me, and I'd like to
>> understand the problem.
>
> Looks like I misunderstood -- those are still allocated kernel-side.
>
> I'll follow that up in the v5 posting.
please review v5.
>
> Thanks,
> Mark.
thanks
Ganapat
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: Russell King - ARM Linux @ 2018-05-21 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000d01d3f100$294247e0$7bc6d7a0$@codeaurora.org>
On Mon, May 21, 2018 at 03:35:07PM +0300, ilialin at codeaurora.org wrote:
> There are 2 CPU clusters in the Kryo, CPU 0 and 1 are called Silver Cluster
> and CPU 2 and 3 - Gold Cluster. Each cluster has single clock. The clusters
> differ in terms of speed capabilities, computing power and power
> consumption. Therefore, I define separate OPP table for each cluster, and my
> driver will choose the appropriate OPP subset for each cluster.
> Lead refers to first CPU in the cluster.
Ah, that is really confusing. Lead can means many things. Maybe a
little more verbosity with the names such as SILVER_CLUSTER_LEAD_CPU
would help?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: ilialin at codeaurora.org @ 2018-05-21 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521121140.GO17671@n2100.armlinux.org.uk>
There are 2 CPU clusters in the Kryo, CPU 0 and 1 are called Silver Cluster
and CPU 2 and 3 - Gold Cluster. Each cluster has single clock. The clusters
differ in terms of speed capabilities, computing power and power
consumption. Therefore, I define separate OPP table for each cluster, and my
driver will choose the appropriate OPP subset for each cluster.
Lead refers to first CPU in the cluster.
> -----Original Message-----
> From: Russell King - ARM Linux <linux@armlinux.org.uk>
> Sent: Monday, May 21, 2018 15:12
> To: ilialin at codeaurora.org
> Cc: viresh.kumar at linaro.org; devicetree at vger.kernel.org; linux-
> pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-soc at vger.kernel.org; linux-
> clk at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH] cpufreq: Add Kryo CPU scaling driver
>
> On Mon, May 21, 2018 at 02:05:41PM +0300, ilialin at codeaurora.org wrote:
> > You are right.
> > cpu_dev_silver != cpu_dev_gold, and I found this with my tests as well.
> > Thank you.
> >
> > > -----Original Message-----
> > > From: Russell King - ARM Linux <linux@armlinux.org.uk>
> > > Sent: Monday, May 21, 2018 13:54
> > > To: Ilia Lin <ilialin@codeaurora.org>
> > > Cc: viresh.kumar at linaro.org; devicetree at vger.kernel.org; linux-
> > > pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
> > > kernel at vger.kernel.org; linux-soc at vger.kernel.org; linux-
> > > clk at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> > > Subject: Re: [PATCH] cpufreq: Add Kryo CPU scaling driver
> > >
> > > On Mon, May 21, 2018 at 01:31:30PM +0300, Ilia Lin wrote:
> > > > +#define SILVER_LEAD 0
> > > > +#define GOLD_LEAD 2
> > >
> > > Okay, two different values here, but "GOLD_LEAD" appears unused.
> > >
> > > > + cpu_dev_silver = get_cpu_device(SILVER_LEAD);
> > > > + if (NULL == cpu_dev_silver)
> > > > + return -ENODEV;
> > > > +
> > > > + cpu_dev_gold = get_cpu_device(SILVER_LEAD);
> > > > + if (NULL == cpu_dev_gold)
> > > > + return -ENODEV;
> > >
> > > get_cpu_device() takes the logical CPU number. So the above gets
> > > CPU 0 each time, and so cpu_dev_silver == cpu_dev_gold here. So
> > > what's the point of the second get_cpu_device() ? If it's supposed to
be:
> > >
> > > cpu_dev_gold = get_cpu_device(GOLD_LEAD);
> > >
> > > That would get CPU 2, but in terms of these defines, it doesn't make
> > > that much sense. What exactly does "silver lead" and "gold lead"
> > > refer to in
> > these
> > > definitions?
>
> I think you still need to explain this.
>
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps
> up According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver
From: Ganapatrao Kulkarni @ 2018-05-21 12:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521105511.6ztjk5conf7lfaiz@lakrids.cambridge.arm.com>
Hi Mark,
On Mon, May 21, 2018 at 4:25 PM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote:
>> On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland <mark.rutland@arm.com> wrote:
>> > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
>
>> >> + *
>> >> + * L3 Tile and DMC channel selection is through SMC call
>> >> + * SMC call arguments,
>> >> + * x0 = THUNDERX2_SMC_CALL_ID (Vendor SMC call Id)
>> >> + * x1 = THUNDERX2_SMC_SET_CHANNEL (Id to set DMC/L3C channel)
>> >> + * x2 = Node id
>> >
>> > How do we map Linux node IDs to the firmware's view of node IDs?
>> >
>> > I don't believe the two are necessarily the same -- Linux's node IDs are
>> > a Linux-specific construct.
>>
>> both are same, it is numa node id from ACPI/firmware.
>
> I am very wary about assuming that the Linux nid will always be the same
> as the ACPI node id.
>
> For that to *potentially* be true, this driver should depend on
> CONFIG_NUMA, NUMA must not be disabled on the command line, etc, or the
> node id will always be NUMA_NO_NODE.
ok, i can check the node id which we get from ACPI helpers in probe.
if it is NUMA_NO_NODE, I will init first socket uncore only and nid
param to fw is always zero?
>
> I would be *much* happier if we had an explicit mapping somewhere to the
> ID the FW expects.
>
>> > It would be much nicer if we could pass something based on the MPIDR,
>> > which is a known HW construct, or if this implicitly affected the
>> > current node.
>>
>> IMO, node id is sufficient.
>
> I agree that *a* node ID is sufficient, I just don't think that we're
> guaranteed to have the specific node ID the FW wants.
for thunderx2 which is 2 socket only platform, pxm and nid should be
same(either 0 or 1)
however, i can send PXM id(node_to_pxm) to firmware to make it more sane.
>
>> > It would be vastly more sane for this to not be muxed at all. :/
>>
>> i am helpless due to crappy hw design!
>
> I'm certainly not blaming you for this! :)
>
> I hope the HW designers don't make the same mistake in future, though...
>
> Thanks,
> Mark.
thanks
Ganapat
^ permalink raw reply
* [PATCH v3 2/3] arm64: dts: renesas: draak: Describe CVBS input
From: jacopo mondi @ 2018-05-21 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6943843.2osudLfTFd@avalon>
Hi Laurent,
On Mon, May 21, 2018 at 01:54:55PM +0300, Laurent Pinchart wrote:
> Hi Jacopo,
>
> On Monday, 21 May 2018 12:57:05 EEST jacopo mondi wrote:
> > On Fri, May 18, 2018 at 06:12:15PM +0300, Laurent Pinchart wrote:
> > > On Friday, 18 May 2018 17:47:57 EEST Jacopo Mondi wrote:
> > >> Describe CVBS video input through analog video decoder ADV7180
> > >> connected to video input interface VIN4.
> > >>
> > >> The video input signal path is shared with HDMI video input, and
> > >> selected by on-board switches SW-53 and SW-54 with CVBS input selected
> > >> by the default switches configuration.
> > >>
> > >> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > >> Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
> > >>
> > >> ---
> > >> v2 -> v3:
> > >> - Add comment to describe the shared input video path
> > >> - Add my SoB and Niklas' R-b tags
> > >> ---
> > >>
> > >> arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 42 +++++++++++++++++++
> > >> 1 file changed, 42 insertions(+)
> > >>
> > >> diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > >> b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 9d73de8..95745fc
> > >> 100644
> > >> --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > >> +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > >> @@ -142,6 +142,11 @@
> > >> groups = "usb0";
> > >> function = "usb0";
> > >> };
> > >> +
> > >> + vin4_pins_cvbs: vin4 {
> > >> + groups = "vin4_data8", "vin4_sync", "vin4_clk";
> > >> + function = "vin4";
> > >> + };
> > >> };
> > >>
> > >> &i2c0 {
> > >> @@ -154,6 +159,23 @@
> > >> reg = <0x50>;
> > >> pagesize = <8>;
> > >> };
> > >> +
> > >> + analog-video at 20 {
> > >> + compatible = "adi,adv7180";
> > >> + reg = <0x20>;
> > >> +
> > >> + port {
> > >
> > > The adv7180 DT bindings document the output port as 3 or 6 (respectively
> > > for the CP and ST versions of the chip). You should thus number the port.
> > > Apart from that the patch looks good.
> >
> > I admit I have barely copied this from Gen-2 boards DTS, but reading
> > the driver code and binding description again, I think this is
> > correct, as the output port numbering and mandatory input port (which
> > is missing here) only apply to adv7180cp/st chip versions.
> >
> > Here we describe plain adv7180, no need to number output ports afaict.
>
> Indeed, my bad.
>
> Shouldn't you however use "adi,adv7180cp" as that's the chip we are using ?
> The "adi,adv7180" has no port documented in its DT bindings, so it shouldn't
> have any port node at all.
I'm a bit confused here.
The only Gen-2 board using the "adi,adv7180cp" compatible string is
Gose, which is also the only one I can get schematics for. That board
indeed feature an ADV7180WBCP32Z, as the Draak does. I cannot get
schematics for any other Gen-2 board, to compare the ADV7180 variant
installed there. If anyone can confirm that all other Gen-2 board uses
a different version (or that all other Gen-2 board DTS file use a
wrong compatible string value), I'll re-send this with a different
compatible value and proper port nodes numbering.
Thanks
j
>
> > >> + /*
> > >> + * The VIN4 video input path is shared between
> > >> + * CVBS and HDMI inputs through SW[49-54] switches.
> > >> + *
> > >> + * CVBS is the default selection, link it to VIN4 here.
> > >> + */
> > >> + adv7180_out: endpoint {
> > >> + remote-endpoint = <&vin4_in>;
> > >> + };
> > >> + };
> > >> + };
> > >> };
> > >>
> > >> &i2c1 {
> > >> @@ -246,3 +268,23 @@
> > >> timeout-sec = <60>;
> > >> status = "okay";
> > >> };
> > >> +
> > >> +&vin4 {
> > >> + pinctrl-0 = <&vin4_pins_cvbs>;
> > >> + pinctrl-names = "default";
> > >> +
> > >> + status = "okay";
> > >> +
> > >> + ports {
> > >> + #address-cells = <1>;
> > >> + #size-cells = <0>;
> > >> +
> > >> + port at 0 {
> > >> + reg = <0>;
> > >> +
> > >> + vin4_in: endpoint {
> > >> + remote-endpoint = <&adv7180_out>;
> > >> + };
> > >> + };
> > >> + };
> > >> +};
>
> --
> Regards,
>
> Laurent Pinchart
>
>
>
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^ permalink raw reply
* [reset-control] How to initialize hardware state with the shared reset line?
From: Hans de Goede @ 2018-05-21 12:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNAR1b_F_eLEWAdQc3L=daGz=ttKq0mQP78BkjzTOssaXvw@mail.gmail.com>
Hi,
On 21-05-18 03:27, Masahiro Yamada wrote:
> Hi.
>
>
> 2018-05-20 19:57 GMT+09:00 Martin Blumenstingl
> <martin.blumenstingl@googlemail.com>:
>> Hi,
>>
>> On Thu, May 10, 2018 at 11:16 AM, Masahiro Yamada
>> <yamada.masahiro@socionext.com> wrote:
>> [snip]
>>> I may be missing something, but
>>> one solution might be reset hogging on the
>>> reset provider side. This allows us to describe
>>> the initial state of reset lines in the reset controller.
>>>
>>> The idea for "reset-hog" is similar to:
>>> - "gpio-hog" defined in
>>> Documentation/devicetree/bindings/gpio/gpio.txt
>>> - "assigned-clocks" defined in
>>> Documetation/devicetree/bindings/clock/clock-bindings.txt
>>>
>>>
>>>
>>> For example,
>>>
>>> reset-controller {
>>> ....
>>>
>>> line_a {
>>> reset-hog;
>>> resets = <1>;
>>> reset-assert;
>>> };
>>> }
>>>
>>>
>>> When the reset controller is registered,
>>> the reset ID '1' is asserted.
>>>
>>>
>>> So, all reset consumers that share the reset line '1'
>>> will start from the asserted state
>>> (i.e. defined state machine state).
>> I wonder if a "reset hog" can be board specific:
>> - GPIO hogs are definitely board specific (meson-gxbb-odroidc2.dts for
>> example uses it to take the USB hub out of reset)
>> - assigned-clock-parents (and the like) can also be board specific (I
>> made up a use-case since I don't know of any actual examples: board A
>> uses an external XTAL while board B uses some other internal
>> clock-source because it doesn't have an external XTAL)
>>
>> however, can reset lines be board specific? or in other words: do we
>> need to describe them in device-tree?
>
> Indeed.
>
> I did not come up with board-specific cases.
>
> The problem we are discussing is SoC-specific,
> and reset-controller drivers are definitely SoC-specific.
>
> So, I think the initial state can be coded in drivers instead of DT.
>
>
>> we could extend struct reset_controller_dev (= reset controller
>> driver) if they are not board specific:
>> - either assert all reset lines by default except if they are listed
>> in a new field (may break backwards compatibility, requires testing of
>> all reset controller drivers)
>
> This is quite simple, but I am afraid there are some cases where the forcible
> reset-assert is not preferred.
>
> For example, the earlycon. When we use earlycon, we would expect it has been
> initialized by a boot-loader, or something.
> If it is reset-asserted on the while, the console output
> will not be good.
>
>
>
>> - specify a list of reset lines and their desired state (or to keep it
>> easy: specify a list of reset lines that should be asserted)
>> (I must admit that this is basically your idea but the definition is
>> moved from device-tree to the reset controller driver)
>
> Yes, I think the list of "reset line ID" and "init state" pairs
> would be nicer.
>
>
>> any "chip" specific differences could be expressed by using a
>> different of_device_id
>>
>> one the other hand: your "reset hog" solution looks fine to me if
>> reset lines can be board specific
>>
>>> From the discussion with Martin Blumenstingl
>>> (https://lkml.org/lkml/2018/4/28/115),
>>> the problem for Amlogic is that
>>> the reset line is "de-asserted" by default.
>>> If so, the 'reset-hog' would fix the problem,
>>> and DWC3 driver would be able to use
>>> shared, level reset, I think.
>> I think you are right: if we could control the initial state then we
>> should be able to use level resets
>
>
> Even further, can we drop the shared reset_control_reset() support, maybe?
> (in other words, revert commit 7da33a37b48f11)
At least one some Allwinner ships shared-reset support accurately
models how the hardware works. It seems that the case you are
trying to fix is actually a special version of shared reset support,
you want shared reset behavior, combined with making sure the reset
is asserted at reset-controller-driver load time.
Regards,
Hans
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: Russell King - ARM Linux @ 2018-05-21 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <000b01d3f0f3$aa961cc0$ffc25640$@codeaurora.org>
On Mon, May 21, 2018 at 02:05:41PM +0300, ilialin at codeaurora.org wrote:
> You are right.
> cpu_dev_silver != cpu_dev_gold, and I found this with my tests as well.
> Thank you.
>
> > -----Original Message-----
> > From: Russell King - ARM Linux <linux@armlinux.org.uk>
> > Sent: Monday, May 21, 2018 13:54
> > To: Ilia Lin <ilialin@codeaurora.org>
> > Cc: viresh.kumar at linaro.org; devicetree at vger.kernel.org; linux-
> > pm at vger.kernel.org; linux-arm-msm at vger.kernel.org; linux-
> > kernel at vger.kernel.org; linux-soc at vger.kernel.org; linux-
> > clk at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> > Subject: Re: [PATCH] cpufreq: Add Kryo CPU scaling driver
> >
> > On Mon, May 21, 2018 at 01:31:30PM +0300, Ilia Lin wrote:
> > > +#define SILVER_LEAD 0
> > > +#define GOLD_LEAD 2
> >
> > Okay, two different values here, but "GOLD_LEAD" appears unused.
> >
> > > + cpu_dev_silver = get_cpu_device(SILVER_LEAD);
> > > + if (NULL == cpu_dev_silver)
> > > + return -ENODEV;
> > > +
> > > + cpu_dev_gold = get_cpu_device(SILVER_LEAD);
> > > + if (NULL == cpu_dev_gold)
> > > + return -ENODEV;
> >
> > get_cpu_device() takes the logical CPU number. So the above gets CPU 0
> > each time, and so cpu_dev_silver == cpu_dev_gold here. So what's the
> > point of the second get_cpu_device() ? If it's supposed to be:
> >
> > cpu_dev_gold = get_cpu_device(GOLD_LEAD);
> >
> > That would get CPU 2, but in terms of these defines, it doesn't make that
> > much sense. What exactly does "silver lead" and "gold lead" refer to in
> these
> > definitions?
I think you still need to explain this.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH v3 1/6] arm64: cpufeature: Allow early detect of specific features
From: Julien Thierry @ 2018-05-21 12:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180521120644.g527aawkutf3etzq@holly.lan>
On 21/05/18 13:06, Daniel Thompson wrote:
> On Mon, May 21, 2018 at 12:45:22PM +0100, Suzuki K Poulose wrote:
>> On 21/05/18 12:35, Julien Thierry wrote:
>>> From: Daniel Thompson <daniel.thompson@linaro.org>
>>>
>>> Currently it is not possible to detect features of the boot CPU
>>> until the other CPUs have been brought up.
>>>
>>> This prevents us from reacting to features of the boot CPU until
>>> fairly late in the boot process. To solve this we allow a subset
>>> of features (that are likely to be common to all clusters) to be
>>> detected based on the boot CPU alone.
>>>
>>> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
>>> [julien.thierry at arm.com: check non-boot cpu missing early features, avoid
>>> duplicates between early features and normal
>>> features]
>>> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will.deacon@arm.com>
>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>> nit: Since this is completely different from what Daniel started with,
>> you could simply reset the author to yourself. The boot CPU feature was
>> added keeping this user in mind.
>
> Agree! It's no longer my patch.
>
> If you want to retain any credit than Suggested-by: would make quite
> sufficient.
>
Good point, I didn't think of that.
I'll change this after I get other reviews for this version.
Thanks,
>
>>
>> The patch as such looks good to me.
>>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>
>>> ---
>>> arch/arm64/kernel/cpufeature.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>>> index 9d1b06d..e03e897 100644
>>> --- a/arch/arm64/kernel/cpufeature.c
>>> +++ b/arch/arm64/kernel/cpufeature.c
>>> @@ -1030,7 +1030,7 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
>>> {
>>> .desc = "GIC system register CPU interface",
>>> .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
>>> - .type = ARM64_CPUCAP_SYSTEM_FEATURE,
>>> + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
>>> .matches = has_useable_gicv3_cpuif,
>>> .sys_reg = SYS_ID_AA64PFR0_EL1,
>>> .field_pos = ID_AA64PFR0_GIC_SHIFT,
>>> --
>>> 1.9.1
>>>
>>
--
Julien Thierry
^ permalink raw reply
* [PATCH v3 1/6] arm64: cpufeature: Allow early detect of specific features
From: Daniel Thompson @ 2018-05-21 12:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <697af68e-3cee-4d0d-8493-106cc42eed3b@arm.com>
On Mon, May 21, 2018 at 12:45:22PM +0100, Suzuki K Poulose wrote:
> On 21/05/18 12:35, Julien Thierry wrote:
> > From: Daniel Thompson <daniel.thompson@linaro.org>
> >
> > Currently it is not possible to detect features of the boot CPU
> > until the other CPUs have been brought up.
> >
> > This prevents us from reacting to features of the boot CPU until
> > fairly late in the boot process. To solve this we allow a subset
> > of features (that are likely to be common to all clusters) to be
> > detected based on the boot CPU alone.
> >
> > Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
> > [julien.thierry at arm.com: check non-boot cpu missing early features, avoid
> > duplicates between early features and normal
> > features]
> > Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> nit: Since this is completely different from what Daniel started with,
> you could simply reset the author to yourself. The boot CPU feature was
> added keeping this user in mind.
Agree! It's no longer my patch.
If you want to retain any credit than Suggested-by: would make quite
sufficient.
Daniel.
>
> The patch as such looks good to me.
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> > ---
> > arch/arm64/kernel/cpufeature.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 9d1b06d..e03e897 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -1030,7 +1030,7 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
> > {
> > .desc = "GIC system register CPU interface",
> > .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
> > - .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> > + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
> > .matches = has_useable_gicv3_cpuif,
> > .sys_reg = SYS_ID_AA64PFR0_EL1,
> > .field_pos = ID_AA64PFR0_GIC_SHIFT,
> > --
> > 1.9.1
> >
>
^ permalink raw reply
* [GIT PULL] Allwinner clock changes for 4.18
From: Maxime Ripard @ 2018-05-21 11:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike, Stephen,
Please merge the following changes for the next merge window, thanks!
Maxime
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git tags/sunxi-clk-for-4.18
for you to fetch changes up to 17de4c857b1f74b90967f7e7fd5ff81be61dc044:
clk: sunxi-ng: r40: export a regmap to access the GMAC register (2018-05-17 14:02:07 +0800)
----------------------------------------------------------------
Allwinner clock changes for 4.18
Not a lot of changes for this release, but two quite important features
were added: the H6 PRCM clock support, and the needed changes to the R40
clock driver to allow for the EMAC to operate.
----------------------------------------------------------------
Icenowy Zheng (3):
clk: sunxi-ng: add support for H6 PRCM CCU
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: r40: export a regmap to access the GMAC register
.../devicetree/bindings/clock/sunxi-ccu.txt | 3 +-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 207 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 19 ++
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 72 +++++--
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 +++
include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 ++
8 files changed, 336 insertions(+), 12 deletions(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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