* [PATCH v7 4/9] dt-bindings: input: touchscreen: resistive-adc-touch: create bindings
From: Eugen Hristev @ 2018-05-22 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526975559-18966-1-git-send-email-eugen.hristev@microchip.com>
Added bindings for generic resistive touchscreen ADC.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- changed property name touchscreen-threshold-pressure to
touchscreen-min-pressure
Changes in v3:
- renamed file and compatible to exclude "generic" keyword
- removed the pressure threshold property, added it as a common
touchscreen property in the touchscreen common bindings in a separate
commit.
Changes in v2:
- modified bindings to have a generic resistive touchscreen adc driver
instead of specific architecture one.
.../input/touchscreen/resistive-adc-touch.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt
diff --git a/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt
new file mode 100644
index 0000000..51456c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt
@@ -0,0 +1,30 @@
+Generic resistive touchscreen ADC
+
+Required properties:
+
+ - compatible: must be "resistive-adc-touch"
+The device must be connected to an ADC device that provides channels for
+position measurement and optional pressure.
+Refer to ../iio/iio-bindings.txt for details
+ - iio-channels: must have at least two channels connected to an ADC device.
+These should correspond to the channels exposed by the ADC device and should
+have the right index as the ADC device registers them. These channels
+represent the relative position on the "x" and "y" axes.
+ - iio-channel-names: must have all the channels' names. Mandatory channels
+are "x" and "y".
+
+Optional properties:
+ - iio-channels: The third channel named "pressure" is optional and can be
+used if the ADC device also measures pressure besides position.
+If this channel is missing, pressure will be ignored and the touchscreen
+will only report position.
+ - iio-channel-names: optional channel named "pressure".
+
+Example:
+
+ resistive_touch: resistive_touch {
+ compatible = "resistive-adc-touch";
+ touchscreen-min-pressure = <50000>;
+ io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
+ io-channel-names = "x", "y", "pressure";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v7 3/9] dt-bindings: input: touchscreen: add minimum pressure touchscreen property
From: Eugen Hristev @ 2018-05-22 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526975559-18966-1-git-send-email-eugen.hristev@microchip.com>
Add a common touchscreen optional property that will specify
the minimum pressure applied to the screen that is needed
such that the driver will report the touch event.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- Modified property name to touchscreen-min-pressure from
touchscreen-threshold-property
Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
index 537643e..d092d5d 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
@@ -7,6 +7,9 @@ Optional properties for Touchscreens:
(in pixels)
- touchscreen-max-pressure : maximum reported pressure (arbitrary range
dependent on the controller)
+ - touchscreen-min-pressure : minimum pressure on the touchscreen to be
+ achieved in order for the touchscreen
+ driver to report a touch event.
- touchscreen-fuzz-x : horizontal noise value of the absolute input
device (in pixels)
- touchscreen-fuzz-y : vertical noise value of the absolute input
--
2.7.4
^ permalink raw reply related
* [PATCH v7 2/9] iio: Add channel for Position Relative
From: Eugen Hristev @ 2018-05-22 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526975559-18966-1-git-send-email-eugen.hristev@microchip.com>
Add new channel type for relative position on a pad.
These type of analog sensor offers the position of a pen
on a touchpad, and is represented as a voltage, which can be
converted to a position on X and Y axis on the pad.
The channel will hand the relative position on the pad in both directions.
The channel can then be consumed by a touchscreen driver or
read as-is for a raw indication of the touchpen on a touchpad.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
Changes in v2:
- modified channel name to relative position as suggested.
- modified kernel version to 4.18 (presumable)
Documentation/ABI/testing/sysfs-bus-iio | 12 ++++++++++++
drivers/iio/industrialio-core.c | 1 +
include/uapi/linux/iio/types.h | 1 +
tools/iio/iio_event_monitor.c | 2 ++
4 files changed, 16 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
index 6a5f34b..42a9287 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio
+++ b/Documentation/ABI/testing/sysfs-bus-iio
@@ -190,6 +190,18 @@ Description:
but should match other such assignments on device).
Units after application of scale and offset are m/s^2.
+What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_x_raw
+What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_y_raw
+KernelVersion: 4.18
+Contact: linux-iio at vger.kernel.org
+Description:
+ Relative position in direction x or y on a pad (may be
+ arbitrarily assigned but should match other such assignments on
+ device).
+ Units after application of scale and offset are milli percents
+ from the pad's size in both directions. Should be calibrated by
+ the consumer.
+
What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_x_raw
What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_y_raw
What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_z_raw
diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c
index 19bdf3d..14bf3d24 100644
--- a/drivers/iio/industrialio-core.c
+++ b/drivers/iio/industrialio-core.c
@@ -85,6 +85,7 @@ static const char * const iio_chan_type_name_spec[] = {
[IIO_COUNT] = "count",
[IIO_INDEX] = "index",
[IIO_GRAVITY] = "gravity",
+ [IIO_POSITIONRELATIVE] = "positionrelative",
};
static const char * const iio_modifier_names[] = {
diff --git a/include/uapi/linux/iio/types.h b/include/uapi/linux/iio/types.h
index 4213cdf..033c7d2 100644
--- a/include/uapi/linux/iio/types.h
+++ b/include/uapi/linux/iio/types.h
@@ -44,6 +44,7 @@ enum iio_chan_type {
IIO_COUNT,
IIO_INDEX,
IIO_GRAVITY,
+ IIO_POSITIONRELATIVE,
};
enum iio_modifier {
diff --git a/tools/iio/iio_event_monitor.c b/tools/iio/iio_event_monitor.c
index b61245e..148f69d 100644
--- a/tools/iio/iio_event_monitor.c
+++ b/tools/iio/iio_event_monitor.c
@@ -58,6 +58,7 @@ static const char * const iio_chan_type_name_spec[] = {
[IIO_PH] = "ph",
[IIO_UVINDEX] = "uvindex",
[IIO_GRAVITY] = "gravity",
+ [IIO_POSITIONRELATIVE] = "positionrelative",
};
static const char * const iio_ev_type_text[] = {
@@ -151,6 +152,7 @@ static bool event_is_known(struct iio_event_data *event)
case IIO_PH:
case IIO_UVINDEX:
case IIO_GRAVITY:
+ case IIO_POSITIONRELATIVE:
break;
default:
return false;
--
2.7.4
^ permalink raw reply related
* [PATCH v7 1/9] MAINTAINERS: add generic resistive touchscreen adc
From: Eugen Hristev @ 2018-05-22 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526975559-18966-1-git-send-email-eugen.hristev@microchip.com>
Add MAINTAINERS entry for generic resistive touchscreen adc
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
Changes in v3:
- Changed source file name
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260..ce9720f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5943,6 +5943,12 @@ F: drivers/base/power/domain*.c
F: include/linux/pm_domain.h
F: Documentation/devicetree/bindings/power/power_domain.txt
+GENERIC RESISTIVE TOUCHSCREEN ADC DRIVER
+M: Eugen Hristev <eugen.hristev@microchip.com>
+L: linux-input at vger.kernel.org
+S: Maintained
+F: drivers/input/touchscreen/resistive-adc-touch.c
+
GENERIC UIO DRIVER FOR PCI DEVICES
M: "Michael S. Tsirkin" <mst@redhat.com>
L: kvm at vger.kernel.org
--
2.7.4
^ permalink raw reply related
* [PATCH v7 0/9] Add support for SAMA5D2 touchscreen
From: Eugen Hristev @ 2018-05-22 7:52 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This patch series is a rework of my previous series named:
[PATCH 00/14] iio: triggers: add consumer support
This is the version 7 of the series, and addresses the received feedback
on the v2 series named:
[PATCH v2 00/10] Add support for SAMA5D2 touchscreen
and the v3 series named
[PATCH v3 00/11] Add support for SAMA5D2 touchscreen
and the v4 series named
[PATCH v4 0/9] Add support for SAMA5D2 touchscreen
and fixes one bug found in series named
[PATCH v5 0/9] Add support for SAMA5D2 touchscreen
and addresses comments in series named
[PATCH v6 0/9] Add support for SAMA5D2 touchscreen
This series applies on top of fixes-togreg branch of iio.git,
specifically on top of commit:
"f0c8d1f" : iio: adc: at91-sama5d2_adc:
fix channel configuration for differential channels
Jonathan, if you need me to rebase this on top of testing, let me know.
Changes in previous versions are presented at the end of the cover letter below.
Thanks everyone for the feedback. Below is the original v2 cover letter:
In few words, this is the implementation of splitting the functionality
of the IP block ADC device in SAMA5D2 SoC from ADC with touchscreen
support. In order to avoid having a MFD device, two separate
drivers that would work on same register base and split the IRQ,etc,
as advised on the mailing list, I created a consumer driver for the
channels, that will connect to the ADC as described in the device tree.
I have collected feedback from everyone and here is the result:
I have added a new generic resistive touchscreen driver, which acts
as a iio consumer for the given channels and will create an input
device and report the events. It uses a callback buffer to register
to the IIO device and waits for data to be pushed.
Inside the IIO device, I have kept a similar approach with the first version
of the series, except that now the driver can take multiple buffers, and
will configure the touchscreen part of the hardware device if the specific
channels are requested.
The SAMA5D2 ADC driver registers three new channels: two for the
position on the X and Y axis, and one for the touch pressure.
When channels are requested, it will check if the touchscreen channel mask
includes the requested channels (it is possible that the consumer driver
will not request pressure for example). If it's the case, it will work
in touchscreen mode, and will refuse to do usual analog-digital conversion,
because we have a single trigger and the touchscreen needs it.
When the scan mask will include only old channels, the driver will function
in the same way as before. If the scan mask somehow is a mix of the two (the
masks intersect), the driver will refuse to work whatsoever (cannot have both
in the same time).
The driver allows reading raw data for the new channels, if claim direct
mode works: no touchscreen driver requested anything. The new channels can
act like the old ones. However, when requesting these channels, the usual
trigger will not work and will not be enabled. The touchscreen channels
require special trigger and irq configuration: pen detect, no pen detect
and a periodic trigger to sample the touchscreen position and pressure.
If the user attempts to use another trigger while there is a buffer
that already requested the touchscreen channels (thus the trigger), the
driver will refuse to comply.
In order to have defines for the channel numbers, I added a bindings include
file that goes on a separate commit :
dt-bindings: iio: adc: at91-sama5d2_adc: add channel specific consumer info
This should go in the same tree with the following commits :
ARM: dts: at91: sama5d2: add channel cells for ADC device
ARM: dts: at91: sama5d2: Add resistive touch device
as build will break because these commits depend on the binding one
which creates the included header file.
V5 update: After discussing with Alexandre Belloni on Mailing list, the two
DTS patches are to be taken in the next version after bindings reach mainline.
Changes in v7:
- Addressed some feedback from Dmitry, explained in input driver patch
changelog.
- Added Acked-by Dmitry.
Changes in v6:
- Fixed a crash in ADC driver , explained in driver patch changelog.
- changed a dev_err to dev_dbg in input driver.
- added Reviewed-by Rob Herring.
Changes in v5:
- renamed property touchscreen-threshold-pressure to touchscreen-min-pressure
- added one return in touchscreen driver
Changes in v4:
- removed patch for inkern module get/set kref
- addressed feedback on both the ADC and the touchscreen driver. each
patch has a history inside the patch file for the specific changes.
- patch that fixes the channel fix
[PATCH v3 01/11] iio: adc: at91-sama5d2_adc:
fix channel configuration for differential channels
was accepted in fixes-togreg branch thus removed from this series.
- added Reviewed-by for the bindings by Rob Herring
Changes in v3:
- changed input driver name according to feedback and reworked in commits
to adapt to binding changes and new name.
- moved channel index fix in at91-sama5d2_adc at the beginning of the series
(PATCH 01/11)
- created a new optional binding for the touchscreen as a separate commit
and added it to the series :
[PATCH v3 04/11] dt-bindings: input: touchscreen: add pressure
threshold touchscreen property
- changed at91-sama5d2_adc driver patch to address the comments. Exact changes
are in the patch file for the driver source file.
Eugen Hristev (9):
MAINTAINERS: add generic resistive touchscreen adc
iio: Add channel for Position Relative
dt-bindings: input: touchscreen: add minimum pressure touchscreen
property
dt-bindings: input: touchscreen: resistive-adc-touch: create bindings
iio: adc: at91-sama5d2_adc: add support for position and pressure
channels
input: touchscreen: resistive-adc-touch: add generic resistive ADC
touchscreen
dt-bindings: iio: adc: at91-sama5d2_adc: add channel specific consumer
info
ARM: dts: at91: sama5d2: add channel cells for ADC device
ARM: dts: at91: sama5d2: Add resistive touch device
Documentation/ABI/testing/sysfs-bus-iio | 12 +
.../bindings/iio/adc/at91-sama5d2_adc.txt | 9 +
.../input/touchscreen/resistive-adc-touch.txt | 30 +
.../bindings/input/touchscreen/touchscreen.txt | 3 +
MAINTAINERS | 6 +
arch/arm/boot/dts/sama5d2.dtsi | 12 +
drivers/iio/adc/at91-sama5d2_adc.c | 609 +++++++++++++++++++--
drivers/iio/industrialio-core.c | 1 +
drivers/input/touchscreen/Kconfig | 13 +
drivers/input/touchscreen/Makefile | 1 +
drivers/input/touchscreen/resistive-adc-touch.c | 204 +++++++
include/dt-bindings/iio/adc/at91-sama5d2_adc.h | 16 +
include/uapi/linux/iio/types.h | 1 +
tools/iio/iio_event_monitor.c | 2 +
14 files changed, 861 insertions(+), 58 deletions(-)
create mode 100644 Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt
create mode 100644 drivers/input/touchscreen/resistive-adc-touch.c
create mode 100644 include/dt-bindings/iio/adc/at91-sama5d2_adc.h
--
2.7.4
^ permalink raw reply
* [PATCH 3/3] arm64: dts: renesas: r8a7795: add ccree binding
From: Geert Uytterhoeven @ 2018-05-22 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOtvUMcf-fHduThORv3cbcN16wEm_Si27OjSjAmSc9g5eK4PJw@mail.gmail.com>
Hi Gilad,
On Mon, May 21, 2018 at 3:43 PM, Gilad Ben-Yossef <gilad@benyossef.com> wrote:
> On Thu, May 17, 2018 at 1:16 PM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
>> Indeed. From a quick glance, it looks like drivers/crypto/ccree/cc_driver.c
>> does not distinguish between the absence of the clock property, and an
>> actual error in getting the clock, and never considers any error a failure
>> (incl. -PROBE_DEFER).
>>
>> As of_clk_get() returns -ENOENT for both a missing clock property and a
>> missing clock, you should use (devm_)clk_get() instead, and distinguish
>> between NULL (no clock property) and IS_ERR() (actual failure -> abort).
>
> I was trying to do as you suggested but I didn't quite get what is the
> dev_id (2nd) parameter to devm_clk_get parameter is supposed to be.
It's the (optional) name of the clock, helpful in case there is more than one.
In your case, NULL is fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 1/1] drm/mediatek: Add support for mediatek SOC MT2712
From: Stu Hsieh @ 2018-05-22 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526351429.29995.21.camel@mtksdaap41>
Hi, CK:
I've some reply for comment
On Tue, 2018-05-15 at 10:30 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comments.
>
> On Mon, 2018-05-14 at 17:59 +0800, Stu Hsieh wrote:
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 77 ++++++++++++++++++++++++++---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 44 +++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++-
> > 5 files changed, 127 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 8130f3dab661..641f4361b006 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -29,6 +29,8 @@
> > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4
> > #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> > #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> >
> > @@ -41,6 +43,7 @@
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
> >
> > #define INT_MUTEX BIT(1)
> >
> > @@ -60,6 +63,25 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> > #define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
> > +#define MT2712_MUTEX_MOD_DISP_AAL BIT(20)
> > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > +#define MT2712_MUTEX_MOD_DISP_OD BIT(25)
> > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */
> > +#define MT2712_MUTEX_MOD2_DISP_AAL1 (BIT(1) | BIT(31))
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > +
>
> It looks like that MUTEX_MOD definition varies for each SoC. I think
> such definition should be passed from dts to prevent modify driver for
> each SoC. For example, the clock definition varies for each SoC, and its
> definition is placed in [1]. The dts [2] include the header file and
> pass the clock definition to driver.
> [1]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/include/dt-bindings/clock/mt2712-clk.h
> [2]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>
This idea is good but weak relation for this MT2712 patch
In the future, we would commit other patch serial for this issue
> > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > #define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
> > @@ -74,6 +96,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR0 0x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > #define UFOE_MOUT_EN_DSI0 0x1
> > #define COLOR0_SEL_IN_OVL0 0x1
> > #define OVL1_MOUT_EN_COLOR1 0x1
> > @@ -108,6 +131,26 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> > };
> >
> > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL] = MT2712_MUTEX_MOD_DISP_AAL,
> > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
> > + [DDP_COMPONENT_OD] = MT2712_MUTEX_MOD_DISP_OD,
> > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
> > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
> > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
> > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
> > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
> > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
> > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
> > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
> > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> > +};
> > +
> > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
> > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> > @@ -150,6 +193,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
>
> I think this should be moved to an independent patch and its title is
> 'add connection from OD1 to RDMA1'.
ok
>
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> > value = RDMA1_MOUT_DPI0;
> > @@ -278,6 +324,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> > mutex[mutex->id]);
> > unsigned int reg;
> > + unsigned int offset;
> >
> > WARN_ON(&ddp->mutex[mutex->id] != mutex);
> >
> > @@ -292,9 +339,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> > reg = MUTEX_SOF_DPI0;
> > break;
> > default:
> > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> > - reg |= ddp->mutex_mod[id];
> > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> > + if (ddp->mutex_mod[id] <= BIT(31)) {
>
> You could reduce one byte if you write as
ok
> if (ddp->mutex_mod[id] < BIT(32))
>
> > + offset = DISP_REG_MUTEX_MOD(mutex->id);
> > + reg = readl_relaxed(ddp->regs + offset);
> > + reg |= ddp->mutex_mod[id];
> > + writel_relaxed(reg, ddp->regs + offset);
> > + } else {
> > + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > + reg = readl_relaxed(ddp->regs + offset);
> > + reg |= (ddp->mutex_mod[id] & ~BIT(31));
> > + writel_relaxed(reg, ddp->regs + offset);
> > + }
>
> I think this should be moved to an independent patch and its title is
> 'support maximum 64 mutex mod'.
ok
>
> > return;
> > }
> >
> > @@ -307,6 +362,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> > struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> > mutex[mutex->id]);
> > unsigned int reg;
> > + unsigned int offset;
> >
> > WARN_ON(&ddp->mutex[mutex->id] != mutex);
> >
> > @@ -318,9 +374,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> > ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
> > break;
> > default:
> > - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> > - reg &= ~(ddp->mutex_mod[id]);
> > - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> > + if (ddp->mutex_mod[id] <= BIT(31)) {
> > + offset = DISP_REG_MUTEX_MOD(mutex->id);
> > + reg = readl_relaxed(ddp->regs + offset);
> > + reg &= ~(ddp->mutex_mod[id]);
> > + writel_relaxed(reg, ddp->regs + offset);
> > + } else {
> > + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > + reg = readl_relaxed(ddp->regs + offset);
> > + reg &= ~(ddp->mutex_mod[id] & ~BIT(31));
> > + writel_relaxed(reg, ddp->regs + offset);
> > + }
> > break;
> > }
> > }
> > @@ -407,6 +471,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
> >
> > static const struct of_device_id ddp_driver_dt_match[] = {
> > { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
> > + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
> > { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
> > {},
> > };
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 4672317e3ad1..ebe8f0018b31 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -219,6 +219,7 @@ struct mtk_ddp_comp_match {
> >
> > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
> > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
>
> For the naming consistency, there are COLOR0 and COLOR1, so after you
> add 'AAL1', you should change AAL to AAL0. And this modification should
> be an independent patch.
ok
>
> > [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> > [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
> > [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
> > @@ -227,9 +228,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
> > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> > [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
> > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
>
> Ditto.
ok
>
> > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
> > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
> > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> > [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
> > [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
> > [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0828cf8bf85c..43100f9215ae 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -42,6 +42,7 @@ enum mtk_ddp_comp_type {
> >
> > enum mtk_ddp_comp_id {
> > DDP_COMPONENT_AAL,
> > + DDP_COMPONENT_AAL1,
> > DDP_COMPONENT_BLS,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > @@ -50,10 +51,12 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_GAMMA,
> > DDP_COMPONENT_OD,
> > + DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
> > DDP_COMPONENT_OVL1,
> > DDP_COMPONENT_PWM0,
> > DDP_COMPONENT_PWM1,
> > + DDP_COMPONENT_PWM2,
> > DDP_COMPONENT_RDMA0,
> > DDP_COMPONENT_RDMA1,
> > DDP_COMPONENT_RDMA2,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index a2ca90fc403c..41baf6653bfc 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -146,6 +146,32 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> > DDP_COMPONENT_DPI0,
> > };
> >
> > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
> > + DDP_COMPONENT_OVL0,
> > + DDP_COMPONENT_COLOR0,
> > + DDP_COMPONENT_AAL,
> > + DDP_COMPONENT_OD,
> > + DDP_COMPONENT_RDMA0,
> > + DDP_COMPONENT_DPI0,
> > + DDP_COMPONENT_PWM0,
> > +};
> > +
> > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
> > + DDP_COMPONENT_OVL1,
> > + DDP_COMPONENT_COLOR1,
> > + DDP_COMPONENT_AAL1,
> > + DDP_COMPONENT_OD1,
> > + DDP_COMPONENT_RDMA1,
> > + DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_PWM1,
> > +};
> > +
> > +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> > + DDP_COMPONENT_RDMA2,
> > + DDP_COMPONENT_DSI2,
> > + DDP_COMPONENT_PWM2,
> > +};
> > +
>
> It looks like that the path definition varies for each SoC. I think such
> definition should be passed from dts to prevent modify driver for each
> SoC. In [3], it define the partial connection in device tree, but I
> would like this to be more general. My idea is:
>
> 1. Each component has one or two endpoint in device tree. The first and
> the last has one, and the others has two.
> 2. Remove mtxxxx_mtk_ddp_main[] and mtxxxx_mtk_ddp_ext[], use multiple
> link list (One display path has one link list, two display path has two
> link list) to generate it by parsing device tree in mtk_drm_probe().
>
> [3] https://patchwork.kernel.org/patch/10397337/
>
In the future, we would commit other patch serial for this issue.
Moreover, in addition to using dts and link list to establish the ddp
path, we want to design a new mechanism to add/remove the component into
this ddp path for run time
> > static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> > DDP_COMPONENT_OVL0,
> > DDP_COMPONENT_COLOR0,
> > @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> > .shadow_register = true,
> > };
> >
> > +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> > + .main_path = mt2712_mtk_ddp_main,
> > + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
> > + .ext_path = mt2712_mtk_ddp_ext,
> > + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
> > + .third_path = mt2712_mtk_ddp_third,
> > + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> > +};
> > +
> > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> > .main_path = mt8173_mtk_ddp_main,
> > .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> > @@ -232,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> > if (ret < 0)
> > goto err_component_unbind;
> >
> > + ret = mtk_drm_crtc_create(drm, private->data->third_path,
> > + private->data->third_len);
> > + if (ret < 0)
> > + goto err_component_unbind;
> > +
> > /* Use OVL device for all DMA memory allocations */
> > np = private->comp_node[private->data->main_path[0]] ?:
> > private->comp_node[private->data->ext_path[0]];
> > @@ -372,8 +412,10 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI },
> > { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt2712-dpi", .data = (void *)MTK_DPI },
>
> Move this modification to the patch which modify the dpi driver for
> mt2712.
ok
>
> > { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> > + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
> > { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
> > @@ -552,6 +594,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> > static const struct of_device_id mtk_drm_of_ids[] = {
> > { .compatible = "mediatek,mt2701-mmsys",
> > .data = &mt2701_mmsys_driver_data},
> > + { .compatible = "mediatek,mt2712-mmsys",
> > + .data = &mt2712_mmsys_driver_data},
> > { .compatible = "mediatek,mt8173-mmsys",
> > .data = &mt8173_mmsys_driver_data},
> > { }
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c3378c452c0a..e821342bc2d3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -17,8 +17,8 @@
> > #include <linux/io.h>
> > #include "mtk_drm_ddp_comp.h"
> >
> > -#define MAX_CRTC 2
> > -#define MAX_CONNECTOR 2
> > +#define MAX_CRTC 3
> > +#define MAX_CONNECTOR 3
> >
> > struct device;
> > struct device_node;
> > @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
> > unsigned int main_len;
> > const enum mtk_ddp_comp_id *ext_path;
> > unsigned int ext_len;
> > + enum mtk_ddp_comp_id *third_path;
> > + unsigned int third_len;
> > +
> > bool shadow_register;
> > };
> >
>
> Regards,
> CK
>
Regards,
Stu
^ permalink raw reply
* [PATCH v6 5/5] drm/rockchip: support dp training outside dp firmware
From: Enric Balletbo Serra @ 2018-05-22 7:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f3d7e6c7-0291-b909-4f0e-a55bc0cad603@rock-chips.com>
Hi Lin
2018-05-22 3:08 GMT+02:00 hl <hl@rock-chips.com>:
> Hi Enric,
>
>
>
>
> On Monday, May 21, 2018 11:22 PM, Enric Balletbo Serra wrote:
>>
>> Hi Lin,
>>
>> 2018-05-21 11:37 GMT+02:00 Lin Huang <hl@rock-chips.com>:
>>>
>>> DP firmware uses fixed phy config values to do training, but some
>>> boards need to adjust these values to fit for their unique hardware
>>> design. So get phy config values from dts and use software link training
>>> instead of relying on firmware, if software training fail, keep firmware
>>> training as a fallback if sw training fails.
>>>
>>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>>> Reviewed-by: Sean Paul <seanpaul@chromium.org>
>>> ---
>>> Changes in v2:
>>> - update patch following Enric suggest
>>> Changes in v3:
>>> - use variable fw_training instead sw_training_success
>>> - base on DP SPCE, if training fail use lower link rate to retry training
>>> Changes in v4:
>>> - improve cdn_dp_get_lower_link_rate() and cdn_dp_software_train_link()
>>> follow Sean suggest
>>> Changes in v5:
>>> - fix some whitespcae issue
>>> Changes in v6:
>>> - None
>>>
>>> drivers/gpu/drm/rockchip/Makefile | 3 +-
>>> drivers/gpu/drm/rockchip/cdn-dp-core.c | 24 +-
>>> drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +
>>> drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 420
>>> ++++++++++++++++++++++++
>>> drivers/gpu/drm/rockchip/cdn-dp-reg.c | 31 +-
>>> drivers/gpu/drm/rockchip/cdn-dp-reg.h | 38 ++-
>>> 6 files changed, 505 insertions(+), 13 deletions(-)
>>> create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-link-training.c
>>>
>>> diff --git a/drivers/gpu/drm/rockchip/Makefile
>>> b/drivers/gpu/drm/rockchip/Makefile
>>> index a314e21..b932f62 100644
>>> --- a/drivers/gpu/drm/rockchip/Makefile
>>> +++ b/drivers/gpu/drm/rockchip/Makefile
>>> @@ -9,7 +9,8 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
>>> rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
>>>
>>> rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>>> -rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
>>> +rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o \
>>> + cdn-dp-link-training.o
>>> rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
>>> rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
>>> rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
>>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
>>> b/drivers/gpu/drm/rockchip/cdn-dp-core.c
>>> index cce64c1..d9d0d4d 100644
>>> --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
>>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
>>> @@ -629,11 +629,13 @@ static void cdn_dp_encoder_enable(struct
>>> drm_encoder *encoder)
>>> goto out;
>>> }
>>> }
>>> -
>>> - ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_IDLE);
>>> - if (ret) {
>>> - DRM_DEV_ERROR(dp->dev, "Failed to idle video %d\n", ret);
>>> - goto out;
>>> + if (dp->use_fw_training == true) {
>>
>> You don't need to compare to true. Simply do:
>>
>> if (dp->use_fw_training)
>>
>>> + ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_IDLE);
>>> + if (ret) {
>>> + DRM_DEV_ERROR(dp->dev,
>>> + "Failed to idle video %d\n", ret);
>>> + goto out;
>>> + }
>>> }
>>>
>>> ret = cdn_dp_config_video(dp);
>>> @@ -642,11 +644,15 @@ static void cdn_dp_encoder_enable(struct
>>> drm_encoder *encoder)
>>> goto out;
>>> }
>>>
>>> - ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_VALID);
>>> - if (ret) {
>>> - DRM_DEV_ERROR(dp->dev, "Failed to valid video %d\n",
>>> ret);
>>> - goto out;
>>> + if (dp->use_fw_training == true) {
>>
>> if (dp->use_fw_training)
>>
>>> + ret = cdn_dp_set_video_status(dp, CONTROL_VIDEO_VALID);
>>> + if (ret) {
>>> + DRM_DEV_ERROR(dp->dev,
>>> + "Failed to valid video %d\n", ret);
>>> + goto out;
>>> + }
>>> }
>>> +
>>> out:
>>> mutex_unlock(&dp->lock);
>>> }
>>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h
>>> b/drivers/gpu/drm/rockchip/cdn-dp-core.h
>>> index 46159b2..77a9793 100644
>>> --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h
>>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h
>>> @@ -84,6 +84,7 @@ struct cdn_dp_device {
>>> bool connected;
>>> bool active;
>>> bool suspended;
>>> + bool use_fw_training;
>>>
>>> const struct firmware *fw; /* cdn dp firmware */
>>> unsigned int fw_version; /* cdn fw version */
>>> @@ -106,6 +107,7 @@ struct cdn_dp_device {
>>> u8 ports;
>>> u8 lanes;
>>> int active_port;
>>> + u8 train_set[4];
>>>
>>> u8 dpcd[DP_RECEIVER_CAP_SIZE];
>>> bool sink_has_audio;
>>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
>>> b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
>>> new file mode 100644
>>> index 0000000..73c3290
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
>>> @@ -0,0 +1,420 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>>> + * Author: Chris Zhong <zyw@rock-chips.com>
>>> + */
>>> +
>>> +#include <linux/device.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <soc/rockchip/rockchip_phy_typec.h>
>>> +
>>> +#include "cdn-dp-core.h"
>>> +#include "cdn-dp-reg.h"
>>> +
>>> +static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
>>> +{
>>> + struct cdn_dp_port *port = dp->port[dp->active_port];
>>> + struct rockchip_typec_phy *tcphy = phy_get_drvdata(port->phy);
>>> +
>>> + int rate = drm_dp_bw_code_to_link_rate(dp->link.rate);
>>> + u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
>>> + DP_TRAIN_VOLTAGE_SWING_SHIFT;
>>> + u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
>>> + >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
>>> +
>>> + tcphy->typec_phy_config(port->phy, rate, dp->link.num_lanes,
>>> + swing, pre_emphasis);
>>> +}
>>> +
>>> +static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t
>>> dp_train_pat)
>>> +{
>>> + u32 phy_config, global_config;
>>> + int ret;
>>> + uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
>>> +
>>> + global_config = NUM_LANES(dp->link.num_lanes - 1) | SST_MODE |
>>> + GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
>>> +
>>> + phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
>>> + DP_TX_PHY_SKEW_BYPASS(0) |
>>> + DP_TX_PHY_DISPARITY_RST(0) |
>>> + DP_TX_PHY_LANE0_SKEW(0) |
>>> + DP_TX_PHY_LANE1_SKEW(1) |
>>> + DP_TX_PHY_LANE2_SKEW(2) |
>>> + DP_TX_PHY_LANE3_SKEW(3) |
>>> + DP_TX_PHY_10BIT_ENABLE(0);
>>> +
>>> + if (pattern != DP_TRAINING_PATTERN_DISABLE) {
>>> + global_config |= NO_VIDEO;
>>> + phy_config |= DP_TX_PHY_TRAINING_ENABLE(1) |
>>> + DP_TX_PHY_SCRAMBLER_BYPASS(1) |
>>> + DP_TX_PHY_TRAINING_PATTERN(pattern);
>>> + }
>>> +
>>> + ret = cdn_dp_reg_write(dp, DP_FRAMER_GLOBAL_CONFIG,
>>> global_config);
>>> + if (ret) {
>>> + DRM_ERROR("fail to set DP_FRAMER_GLOBAL_CONFIG, error:
>>> %d\n",
>>> + ret);
>>> + return ret;
>>> + }
>>> +
>>> + ret = cdn_dp_reg_write(dp, DP_TX_PHY_CONFIG_REG, phy_config);
>>> + if (ret) {
>>> + DRM_ERROR("fail to set DP_TX_PHY_CONFIG_REG, error:
>>> %d\n",
>>> + ret);
>>> + return ret;
>>> + }
>>> +
>>> + ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->link.num_lanes)
>>> - 1);
>>> + if (ret) {
>>> + DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + if (drm_dp_enhanced_frame_cap(dp->dpcd))
>>> + ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 1);
>>> + else
>>> + ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 0);
>>> + if (ret)
>>> + DRM_ERROR("failed to set DPTX_ENHNCD, error: %x\n", ret);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static u8 cdn_dp_pre_emphasis_max(u8 voltage_swing)
>>> +{
>>> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>>> + return DP_TRAIN_PRE_EMPH_LEVEL_3;
>>> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
>>> + return DP_TRAIN_PRE_EMPH_LEVEL_2;
>>> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
>>> + return DP_TRAIN_PRE_EMPH_LEVEL_1;
>>> + default:
>>> + return DP_TRAIN_PRE_EMPH_LEVEL_0;
>>> + }
>>> +}
>>> +
>>> +static void cdn_dp_get_adjust_train(struct cdn_dp_device *dp,
>>> + uint8_t
>>> link_status[DP_LINK_STATUS_SIZE])
>>> +{
>>> + int i;
>>> + uint8_t v = 0, p = 0;
>>> + uint8_t preemph_max;
>>> +
>>> + for (i = 0; i < dp->link.num_lanes; i++) {
>>> + v = max(v, drm_dp_get_adjust_request_voltage(link_status,
>>> i));
>>> + p = max(p,
>>> drm_dp_get_adjust_request_pre_emphasis(link_status,
>>> + i));
>>> + }
>>> +
>>> + if (v >= VOLTAGE_LEVEL_2)
>>> + v = VOLTAGE_LEVEL_2 | DP_TRAIN_MAX_SWING_REACHED;
>>> +
>>> + preemph_max = cdn_dp_pre_emphasis_max(v);
>>> + if (p >= preemph_max)
>>> + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
>>> +
>>> + for (i = 0; i < dp->link.num_lanes; i++)
>>> + dp->train_set[i] = v | p;
>>> +}
>>> +
>>> +/*
>>> + * Pick training pattern for channel equalization. Training Pattern 3
>>> for HBR2
>>> + * or 1.2 devices that support it, Training Pattern 2 otherwise.
>>> + */
>>> +static u32 cdn_dp_select_chaneq_pattern(struct cdn_dp_device *dp)
>>> +{
>>> + u32 training_pattern = DP_TRAINING_PATTERN_2;
>>> +
>>> + /*
>>> + * cdn dp support HBR2 also support TPS3. TPS3 support is also
>>> mandatory
>>> + * for downstream devices that support HBR2. However, not all
>>> sinks
>>> + * follow the spec.
>>> + */
>>> + if (drm_dp_tps3_supported(dp->dpcd))
>>> + training_pattern = DP_TRAINING_PATTERN_3;
>>> + else
>>> + DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3
>>> support\n");
>>> +
>>> + return training_pattern;
>>> +}
>>> +
>>> +
>>> +static bool cdn_dp_link_max_vswing_reached(struct cdn_dp_device *dp)
>>> +{
>>> + int lane;
>>> +
>>> + for (lane = 0; lane < dp->link.num_lanes; lane++)
>>> + if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) ==
>>> 0)
>>> + return false;
>>> +
>>> + return true;
>>> +}
>>> +
>>> +static int cdn_dp_update_link_train(struct cdn_dp_device *dp)
>>> +{
>>> + int ret;
>>> +
>>> + cdn_dp_set_signal_levels(dp);
>>> +
>>> + ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
>>> + dp->train_set, dp->link.num_lanes);
>>> + if (ret != dp->link.num_lanes)
>>> + return -EINVAL;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int cdn_dp_set_link_train(struct cdn_dp_device *dp,
>>> + uint8_t dp_train_pat)
>>> +{
>>> + uint8_t buf[sizeof(dp->train_set) + 1];
>>> + int ret, len;
>>> +
>>> + buf[0] = dp_train_pat;
>>> + if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
>>> + DP_TRAINING_PATTERN_DISABLE) {
>>> + /* don't write DP_TRAINING_LANEx_SET on disable */
>>> + len = 1;
>>> + } else {
>>> + /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET
>>> */
>>> + memcpy(buf + 1, dp->train_set, dp->link.num_lanes);
>>> + len = dp->link.num_lanes + 1;
>>> + }
>>> +
>>> + ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
>>> + buf, len);
>>> + if (ret != len)
>>> + return -EINVAL;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int cdn_dp_reset_link_train(struct cdn_dp_device *dp,
>>> + uint8_t dp_train_pat)
>>> +{
>>> + int ret;
>>> +
>>> + memset(dp->train_set, 0, sizeof(dp->train_set));
>>> +
>>> + cdn_dp_set_signal_levels(dp);
>>> +
>>> + ret = cdn_dp_set_pattern(dp, dp_train_pat);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return cdn_dp_set_link_train(dp, dp_train_pat);
>>> +}
>>> +
>>> +/* Enable corresponding port and start training pattern 1 */
>>> +static int cdn_dp_link_training_clock_recovery(struct cdn_dp_device *dp)
>>> +{
>>> + u8 voltage;
>>> + u8 link_status[DP_LINK_STATUS_SIZE];
>>> + u32 voltage_tries, max_vswing_tries;
>>> + int ret;
>>> +
>>> + /* clock recovery */
>>> + ret = cdn_dp_reset_link_train(dp, DP_TRAINING_PATTERN_1 |
>>> + DP_LINK_SCRAMBLING_DISABLE);
>>> + if (ret) {
>>> + DRM_ERROR("failed to start link train\n");
>>> + return ret;
>>> + }
>>> +
>>> + voltage_tries = 1;
>>> + max_vswing_tries = 0;
>>> + for (;;) {
>>> + drm_dp_link_train_clock_recovery_delay(dp->dpcd);
>>> + if (drm_dp_dpcd_read_link_status(&dp->aux, link_status)
>>> !=
>>> + DP_LINK_STATUS_SIZE) {
>>> + DRM_ERROR("failed to get link status\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if (drm_dp_clock_recovery_ok(link_status,
>>> dp->link.num_lanes)) {
>>> + DRM_DEBUG_KMS("clock recovery OK\n");
>>> + return 0;
>>> + }
>>> +
>>> + if (voltage_tries >= 5) {
>>> + DRM_DEBUG_KMS("Same voltage tried 5 times\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if (max_vswing_tries >= 1) {
>>> + DRM_DEBUG_KMS("Max Voltage Swing reached\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
>>> +
>>> + /* Update training set as requested by target */
>>> + cdn_dp_get_adjust_train(dp, link_status);
>>> + if (cdn_dp_update_link_train(dp)) {
>>> + DRM_ERROR("failed to update link training\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
>>> + voltage)
>>> + ++voltage_tries;
>>> + else
>>> + voltage_tries = 1;
>>> +
>>> + if (cdn_dp_link_max_vswing_reached(dp))
>>> + ++max_vswing_tries;
>>> + }
>>> +}
>>> +
>>> +static int cdn_dp_link_training_channel_equalization(struct
>>> cdn_dp_device *dp)
>>> +{
>>> + int tries, ret;
>>> + u32 training_pattern;
>>> + uint8_t link_status[DP_LINK_STATUS_SIZE];
>>> +
>>> + training_pattern = cdn_dp_select_chaneq_pattern(dp);
>>> + training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
>>> +
>>> + ret = cdn_dp_set_pattern(dp, training_pattern);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + ret = cdn_dp_set_link_train(dp, training_pattern);
>>> + if (ret) {
>>> + DRM_ERROR("failed to start channel equalization\n");
>>> + return ret;
>>> + }
>>> +
>>> + for (tries = 0; tries < 5; tries++) {
>>> + drm_dp_link_train_channel_eq_delay(dp->dpcd);
>>> + if (drm_dp_dpcd_read_link_status(&dp->aux, link_status)
>>> !=
>>> + DP_LINK_STATUS_SIZE) {
>>> + DRM_ERROR("failed to get link status\n");
>>> + break;
>>> + }
>>> +
>>> + /* Make sure clock is still ok */
>>> + if (!drm_dp_clock_recovery_ok(link_status,
>>> + dp->link.num_lanes)) {
>>> + DRM_DEBUG_KMS("Clock recovery check failed\n");
>>> + break;
>>> + }
>>> +
>>> + if (drm_dp_channel_eq_ok(link_status,
>>> dp->link.num_lanes)) {
>>> + DRM_DEBUG_KMS("Channel EQ done\n");
>>> + return 0;
>>> + }
>>> +
>>> + /* Update training set as requested by target */
>>> + cdn_dp_get_adjust_train(dp, link_status);
>>> + if (cdn_dp_update_link_train(dp)) {
>>> + DRM_ERROR("failed to update link training\n");
>>> + break;
>>> + }
>>> + }
>>> +
>>> + /* Try 5 times, else fail and try at lower BW */
>>> + if (tries == 5)
>>> + DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
>>> +
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int cdn_dp_stop_link_train(struct cdn_dp_device *dp)
>>> +{
>>> + int ret = cdn_dp_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
>>> +
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return cdn_dp_set_link_train(dp, DP_TRAINING_PATTERN_DISABLE);
>>> +}
>>> +
>>> +static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
>>> +{
>>> + switch (dp->link.rate) {
>>> + case DP_LINK_BW_1_62:
>>> + return -EINVAL;
>>> + case DP_LINK_BW_2_7:
>>> + dp->link.rate = DP_LINK_BW_1_62;
>>> + break;
>>> + case DP_LINK_BW_5_4:
>>> + dp->link.rate = DP_LINK_BW_2_7;
>>> + break;
>>> + default:
>>> + dp->link.rate = DP_LINK_BW_5_4;
>>> + break;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int cdn_dp_software_train_link(struct cdn_dp_device *dp)
>>> +{
>>> + int ret, stop_err;
>>> + u8 link_config[2];
>>> + u32 rate, sink_max, source_max;
>>> +
>>> + ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
>>> + sizeof(dp->dpcd));
>>> + if (ret < 0) {
>>> + DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + source_max = dp->lanes;
>>> + sink_max = drm_dp_max_lane_count(dp->dpcd);
>>> + dp->link.num_lanes = min(source_max, sink_max);
>>> +
>>> + source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
>>> + sink_max = drm_dp_max_link_rate(dp->dpcd);
>>> + rate = min(source_max, sink_max);
>>> + dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
>>> +
>>> + link_config[0] = 0;
>>> + link_config[1] = 0;
>>> + if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
>>> + link_config[1] = DP_SET_ANSI_8B10B;
>>> + drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>>> +
>>> + while (true) {
>>> +
>>> + /* Write the link configuration data */
>>> + link_config[0] = dp->link.rate;
>>> + link_config[1] = dp->link.num_lanes;
>>> + if (drm_dp_enhanced_frame_cap(dp->dpcd))
>>> + link_config[1] |=
>>> DP_LANE_COUNT_ENHANCED_FRAME_EN;
>>> + drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config,
>>> 2);
>>> +
>>> + ret = cdn_dp_link_training_clock_recovery(dp);
>>> + if (ret) {
>>> + if (!cdn_dp_get_lower_link_rate(dp))
>>> + continue;
>>> +
>>> + DRM_ERROR("training clock recovery failed: %d\n",
>>> ret);
>>> + break;
>>> + }
>>> +
>>> + ret = cdn_dp_link_training_channel_equalization(dp);
>>> + if (ret) {
>>> + if (!cdn_dp_get_lower_link_rate(dp))
>>> + continue;
>>> +
>>> + DRM_ERROR("training channel eq failed: %d\n",
>>> ret);
>>> + break;
>>> + }
>>> +
>>> + break;
>>> + }
>>> +
>>> + stop_err = cdn_dp_stop_link_train(dp);
>>> + if (stop_err) {
>>> + DRM_ERROR("stop training fail, error: %d\n", stop_err);
>>> + return stop_err;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
>>> b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
>>> index 979355d..e1273e6 100644
>>> --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
>>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.c
>>> @@ -17,7 +17,9 @@
>>> #include <linux/delay.h>
>>> #include <linux/io.h>
>>> #include <linux/iopoll.h>
>>> +#include <linux/phy/phy.h>
>>> #include <linux/reset.h>
>>> +#include <soc/rockchip/rockchip_phy_typec.h>
>>>
>>> #include "cdn-dp-core.h"
>>> #include "cdn-dp-reg.h"
>>> @@ -189,7 +191,7 @@ static int cdn_dp_mailbox_send(struct cdn_dp_device
>>> *dp, u8 module_id,
>>> return 0;
>>> }
>>>
>>> -static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
>>> +int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
>>> {
>>> u8 msg[6];
>>>
>>> @@ -609,6 +611,31 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
>>> {
>>> int ret;
>>>
>>> + /*
>>> + * DP firmware uses fixed phy config values to do training, but
>>> some
>>> + * boards need to adjust these values to fit for their unique
>>> hardware
>>> + * design. So if the phy is using custom config values, do
>>> software
>>> + * link training instead of relying on firmware, if software
>>> training
>>> + * fail, keep firmware training as a fallback if sw training
>>> fails.
>>> + */
>>> + ret = cdn_dp_software_train_link(dp);
>>> + if (ret) {
>>> + DRM_DEV_ERROR(dp->dev,
>>> + "Failed to do software training %d\n", ret);
>>> + goto do_fw_training;
>>> + }
>>
>> If I understand correctly you are changing current behavior. Before
>> this patch, we use always firmware link training, and after this
>> patch, we always use software link training. If fails we use the
>> firmware link training.
>>
>> AFAIK my Samsung Chromebook Plus works well with firmware link
>> training, so there are any benefits of use software link training
>> instead of firmware link training?
>>
>> Looks to me that we should only do software link training on these
>> platforms that need it, so on those that define the phy-config
>> property in their DT and use by default firmware link training.
>
> Sean and me have discussed about that, and we all agree to use sw training
> instead the
> fw training to keep training process consistent, and we do not need add a
> varialbe in
> struct rockchip_typec_phy(like use_sw_training before) to distinguish sw and
> fw training.
> If training process implement correctly, sw training not different with fw
> training, and as my
> test so far, sw training work well on Kevin, ofcourse, we need keep testing
> it.
>
Ok, I can also confirm that software training works well on kevin.
Could you mention this change of behavior in the commit message? I
think that after these patches the firmware training is unlikely to
happen.
Thanks,
Enric
>>> + ret = cdn_dp_reg_write(dp, SOURCE_HDTX_CAR, 0xf);
>>> + if (ret) {
>>> + DRM_DEV_ERROR(dp->dev,
>>> + "Failed to write SOURCE_HDTX_CAR register %d\n", ret);
>>> + goto do_fw_training;
>>> + }
>>> + dp->use_fw_training = false;
>>> + return 0;
>>> +
>>> +do_fw_training:
>>> + dp->use_fw_training = true;
>>> + DRM_DEV_DEBUG_KMS(dp->dev, "use fw training\n");
>>> ret = cdn_dp_training_start(dp);
>>> if (ret) {
>>> DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n",
>>> ret);
>>> @@ -623,7 +650,7 @@ int cdn_dp_train_link(struct cdn_dp_device *dp)
>>>
>>> DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n",
>>> dp->link.rate,
>>> dp->link.num_lanes);
>>> - return ret;
>>> + return 0;
>>> }
>>>
>>> int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
>>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
>>> b/drivers/gpu/drm/rockchip/cdn-dp-reg.h
>>> index 6580b11..3420771 100644
>>> --- a/drivers/gpu/drm/rockchip/cdn-dp-reg.h
>>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-reg.h
>>> @@ -137,7 +137,7 @@
>>> #define HPD_EVENT_MASK 0x211c
>>> #define HPD_EVENT_DET 0x2120
>>>
>>> -/* dpyx framer addr */
>>> +/* dptx framer addr */
>>> #define DP_FRAMER_GLOBAL_CONFIG 0x2200
>>> #define DP_SW_RESET 0x2204
>>> #define DP_FRAMER_TU 0x2208
>>> @@ -431,6 +431,40 @@
>>> /* Reference cycles when using lane clock as reference */
>>> #define LANE_REF_CYC 0x8000
>>>
>>> +/* register CM_VID_CTRL */
>>> +#define LANE_VID_REF_CYC(x) (((x) & (BIT(24) - 1)) <<
>>> 0)
>>> +#define NMVID_MEAS_TOLERANCE(x) (((x) & 0xf) <<
>>> 24)
>>> +
>>> +/* register DP_TX_PHY_CONFIG_REG */
>>> +#define DP_TX_PHY_TRAINING_ENABLE(x) ((x) & 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_PRBS7 (0 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_TPS1 (1 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_TPS2 (2 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_TPS3 (3 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_TPS4 (4 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_PLTPAT (5 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_D10_2 (6 << 1)
>>> +#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT (8 << 1)
>>> +#define DP_TX_PHY_TRAINING_PATTERN(x) ((x) << 1)
>>> +#define DP_TX_PHY_SCRAMBLER_BYPASS(x) (((x) & 1) << 5)
>>> +#define DP_TX_PHY_ENCODER_BYPASS(x) (((x) & 1) << 6)
>>> +#define DP_TX_PHY_SKEW_BYPASS(x) (((x) & 1) << 7)
>>> +#define DP_TX_PHY_DISPARITY_RST(x) (((x) & 1) << 8)
>>> +#define DP_TX_PHY_LANE0_SKEW(x) (((x) & 7) << 9)
>>> +#define DP_TX_PHY_LANE1_SKEW(x) (((x) & 7) << 12)
>>> +#define DP_TX_PHY_LANE2_SKEW(x) (((x) & 7) << 15)
>>> +#define DP_TX_PHY_LANE3_SKEW(x) (((x) & 7) << 18)
>>> +#define DP_TX_PHY_10BIT_ENABLE(x) (((x) & 1) << 21)
>>> +
>>> +/* register DP_FRAMER_GLOBAL_CONFIG */
>>> +#define NUM_LANES(x) ((x) & 3)
>>> +#define SST_MODE (0 << 2)
>>> +#define RG_EN (0 << 4)
>>> +#define GLOBAL_EN BIT(3)
>>> +#define NO_VIDEO BIT(5)
>>> +#define ENC_RST_DIS BIT(6)
>>> +#define WR_VHSYNC_FALL BIT(7)
>>> +
>>> enum voltage_swing_level {
>>> VOLTAGE_LEVEL_0,
>>> VOLTAGE_LEVEL_1,
>>> @@ -476,6 +510,7 @@ int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8
>>> lanes, bool flip);
>>> int cdn_dp_event_config(struct cdn_dp_device *dp);
>>> u32 cdn_dp_get_event(struct cdn_dp_device *dp);
>>> int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
>>> +int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
>>> ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
>>> u8 *data, u16 len);
>>> ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
>>> @@ -489,4 +524,5 @@ int cdn_dp_config_video(struct cdn_dp_device *dp);
>>> int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info
>>> *audio);
>>> int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
>>> int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info
>>> *audio);
>>> +int cdn_dp_software_train_link(struct cdn_dp_device *dp);
>>> #endif /* _CDN_DP_REG_H */
>>> --
>>> 2.7.4
>>>
>>
>>
>
>
^ permalink raw reply
* [PATCH v2 4/7] Bluetooth: Add new quirk for non-persistent setup settings
From: Marcel Holtmann @ 2018-05-22 7:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1d6097f538b3182b2876ad48225ecd6e2d1b128c.1526374087.git.sean.wang@mediatek.com>
Hi Sean,
> Add a new quirk HCI_QUIRK_NON_PERSISTENT_SETUP allowing that a quirk that
> runs setup() after every open() and not just after the first open().
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
> include/net/bluetooth/hci.h | 9 +++++++++
> net/bluetooth/hci_core.c | 3 ++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
> index 1668211..b37d973 100644
> --- a/include/net/bluetooth/hci.h
> +++ b/include/net/bluetooth/hci.h
> @@ -183,6 +183,15 @@ enum {
> * during the hdev->setup vendor callback.
> */
> HCI_QUIRK_NON_PERSISTENT_DIAG,
> +
> + /* When this quirk is set, setup() would be run after every
> + * open() and not just after the first open().
> + *
> + * This quirk can be set before hci_register_dev is called or
> + * during the hdev->setup vendor callback.
> + *
> + */
> + HCI_QUIRK_NON_PERSISTENT_SETUP,
> };
>
> /* HCI device flags */
> diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
> index 40d260f..7de712e2 100644
> --- a/net/bluetooth/hci_core.c
> +++ b/net/bluetooth/hci_core.c
> @@ -1377,7 +1377,8 @@ static int hci_dev_do_open(struct hci_dev *hdev)
> atomic_set(&hdev->cmd_cnt, 1);
> set_bit(HCI_INIT, &hdev->flags);
>
> - if (hci_dev_test_flag(hdev, HCI_SETUP)) {
> + if (hci_dev_test_flag(hdev, HCI_SETUP) ||
> + test_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks)) {
> hci_sock_dev_event(hdev, HCI_DEV_SETUP);
I am not 100% sure that we want to send the HCI_DEV_SETUP event also multiple times. That is a userspace change that I would need to think about. We need to check create_monitor_event() and see what the btmon trace for this looks like. Can you send me a btmon -w trace.log when this change is active.
Regards
Marcel
^ permalink raw reply
* [PATCH v1] dma: imx-sdma: add virt-dma support
From: Robin Gong @ 2018-05-22 7:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522065534.GD18351@vkoul-mobl>
Ok, I'll resend it after rebase and test.
On ?, 2018-05-22 at 12:25 +0530, Vinod wrote:
> On 22-05-18, 06:16, Robin Gong wrote:
> >
> > Ping.
> Looks like I missed this one, can you please rebase and resend.
> While at it, modify the subject to dmaengine, as thats the subsystem
> name
>
^ permalink raw reply
* [PATCH 6/7 v5] bus: fsl-mc: set coherent dma mask for devices on fsl-mc bus
From: Laurentiu Tudor @ 2018-05-22 7:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526824191-7000-7-git-send-email-nipun.gupta@nxp.com>
On 05/20/2018 04:49 PM, Nipun Gupta wrote:
> of_dma_configure() API expects coherent_dma_mask to be correctly
> set in the devices. This patch does the needful.
>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
Best Regards, Laurentiu
> ---
> drivers/bus/fsl-mc/fsl-mc-bus.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c
> index fa43c7d..624828b 100644
> --- a/drivers/bus/fsl-mc/fsl-mc-bus.c
> +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c
> @@ -627,6 +627,7 @@ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc,
> mc_dev->icid = parent_mc_dev->icid;
> mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
> mc_dev->dev.dma_mask = &mc_dev->dma_mask;
> + mc_dev->dev.coherent_dma_mask = mc_dev->dma_mask;
> dev_set_msi_domain(&mc_dev->dev,
> dev_get_msi_domain(&parent_mc_dev->dev));
> }
>
^ permalink raw reply
* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: ilialin at codeaurora.org @ 2018-05-22 6:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2ace10bc-e1c4-2060-94d3-eb71e966ffbe@arm.com>
> -----Original Message-----
> From: Sudeep Holla <sudeep.holla@arm.com>
> Sent: Monday, May 21, 2018 16:05
> To: ilialin at codeaurora.org; mturquette at baylibre.com; sboyd at kernel.org;
> robh at kernel.org; mark.rutland at arm.com; viresh.kumar at linaro.org;
> nm at ti.com; lgirdwood at gmail.com; broonie at kernel.org;
> andy.gross at linaro.org; david.brown at linaro.org; catalin.marinas at arm.com;
> will.deacon at arm.com; rjw at rjwysocki.net; linux-clk at vger.kernel.org
> Cc: Sudeep Holla <sudeep.holla@arm.com>; devicetree at vger.kernel.org;
> linux-kernel at vger.kernel.org; linux-pm at vger.kernel.org; linux-arm-
> msm at vger.kernel.org; linux-soc at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; rnayak at codeaurora.org;
> amit.kucheria at linaro.org; nicolas.dechesne at linaro.org;
> celster at codeaurora.org; tfinkel at codeaurora.org
> Subject: Re: [PATCH] cpufreq: Add Kryo CPU scaling driver
>
>
>
> On 21/05/18 13:57, ilialin at codeaurora.org wrote:
> >
> [...]
>
> >>> +#include <linux/cpu.h>
> >>> +#include <linux/err.h>
> >>> +#include <linux/init.h>
> >>> +#include <linux/kernel.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/nvmem-consumer.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/pm_opp.h>
> >>> +#include <linux/slab.h>
> >>> +#include <linux/soc/qcom/smem.h>
> >>> +
> >>> +#define MSM_ID_SMEM 137
> >>> +#define SILVER_LEAD 0
> >>> +#define GOLD_LEAD 2
> >>> +
> >>
> >> So I gather form other emails, that these are physical cpu number(not
> >> even unique identifier like MPIDR). Will this work on parts or
> >> platforms that need to boot in GOLD LEAD cpus.
> >
> > The driver is for Kryo CPU, which (and AFAIK all multicore MSMs)
> > always boots on the CPU0.
>
>
> That may be true and I am not that bothered about it. But assuming physical
> ordering from the logical cpu number is *incorrect* and will break if kernel
> decides to change the allocation algorithm. Kernel provides no guarantee on
> that, so you need to depend on some physical ID or may be DT to achieve
> what your want. But the current code as it stands is wrong.
Got your point. In fact CPUs are numbered 0-3 and ordered into 2 clusters in the DT:
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu at 0 {
...
reg = <0x0 0x0>;
...
};
CPU1: cpu at 1 {
...
reg = <0x0 0x1>;
...
};
CPU2: cpu at 100 {
...
reg = <0x0 0x100>;
...
};
CPU3: cpu at 101 {
...
reg = <0x0 0x101>;
...
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
};
core1 {
cpu = <&CPU3>;
};
};
};
};
As far, as I understand, they are probed in the same order. However, to be certain that the physical CPU is the one I intend to configure, I have to fetch the device structure pointer for the cpu-map -> clusterX -> core0 -> cpu path. Could you suggest a kernel API to do that?
>
> --
> Regards,
> Sudeep
^ permalink raw reply
* [PATCH v1] dma: imx-sdma: add virt-dma support
From: Vinod @ 2018-05-22 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR04MB32230F836E366C6D0AA7A44489940@DB6PR04MB3223.eurprd04.prod.outlook.com>
On 22-05-18, 06:16, Robin Gong wrote:
> Ping.
Looks like I missed this one, can you please rebase and resend.
While at it, modify the subject to dmaengine, as thats the subsystem name
--
~Vinod
^ permalink raw reply
* [PATCH v3 3/3] ARM: dts: imx6ull-colibri-wifi: remove operating points
From: Sébastien Szymanski @ 2018-05-22 6:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522062853.24799-1-sebastien.szymanski@armadeus.com>
Operating points are now defined in the imx6ull.dtsi file so remove
them from board device trees.
Signed-off-by: S?bastien Szymanski <sebastien.szymanski@armadeus.com>
---
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 3dffbcd50bf6..183193e8580d 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -20,20 +20,6 @@
&cpu0 {
clock-frequency = <792000000>;
- operating-points = <
- /* kHz uV */
- 792000 1225000
- 528000 1175000
- 396000 1025000
- 198000 950000
- >;
- fsl,soc-operating-points = <
- /* KHz uV */
- 792000 1175000
- 528000 1175000
- 396000 1175000
- 198000 1175000
- >;
};
&iomuxc {
--
2.16.1
^ permalink raw reply related
* [PATCH v3 2/3] ARM: dts: imx6ull: add operating points
From: Sébastien Szymanski @ 2018-05-22 6:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522062853.24799-1-sebastien.szymanski@armadeus.com>
i.MX6ULL has different operating ranges than i.MX6UL so add the
operating points for the i.MX6ULL. A 25mV offset is added to the minimum
allowed values like for the i.MX6UL.
Signed-off-by: S?bastien Szymanski <sebastien.szymanski@armadeus.com>
---
Changes for v3:
- none
Changes for v2:
- Fix soc-operating-points voltage for 792MHz and 900MHz
arch/arm/boot/dts/imx6ull.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 571ddd71cdba..530d5526b890 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -46,6 +46,25 @@
/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
/delete-node/ &uart8;
+&cpu0 {
+ operating-points = <
+ /* kHz uV */
+ 900000 1275000
+ 792000 1225000
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 900000 1175000
+ 792000 1175000
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+};
+
/ {
soc {
aips3: aips-bus at 2200000 {
--
2.16.1
^ permalink raw reply related
* [PATCH v3 1/3] cpufreq: imx6q: check speed grades for i.MX6ULL
From: Sébastien Szymanski @ 2018-05-22 6:28 UTC (permalink / raw)
To: linux-arm-kernel
Check the max speed supported from the fuses for i.MX6ULL and update the
operating points table accordingly.
Signed-off-by: S?bastien Szymanski <sebastien.szymanski@armadeus.com>
---
Changes for v3:
- none
Changes for v2:
- none
drivers/cpufreq/imx6q-cpufreq.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 83cf631fc9bc..f094687cae52 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -266,6 +266,8 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
}
#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
+#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
+#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
static void imx6ul_opp_check_speed_grading(struct device *dev)
{
@@ -287,16 +289,30 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
* Speed GRADING[1:0] defines the max speed of ARM:
* 2b'00: Reserved;
* 2b'01: 528000000Hz;
- * 2b'10: 696000000Hz;
- * 2b'11: Reserved;
+ * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
+ * 2b'11: 900000000Hz on i.MX6ULL only;
* We need to set the max speed of ARM according to fuse map.
*/
val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
- if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
- if (dev_pm_opp_disable(dev, 696000000))
- dev_warn(dev, "failed to disable 696MHz OPP\n");
+
+ if (of_machine_is_compatible("fsl,imx6ul")) {
+ if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+ if (dev_pm_opp_disable(dev, 696000000))
+ dev_warn(dev, "failed to disable 696MHz OPP\n");
+ }
+
+ if (of_machine_is_compatible("fsl,imx6ull")) {
+ if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
+ if (dev_pm_opp_disable(dev, 792000000))
+ dev_warn(dev, "failed to disable 792MHz OPP\n");
+
+ if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
+ if (dev_pm_opp_disable(dev, 900000000))
+ dev_warn(dev, "failed to disable 900MHz OPP\n");
+ }
+
iounmap(base);
put_node:
of_node_put(np);
@@ -356,7 +372,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
goto put_reg;
}
- if (of_machine_is_compatible("fsl,imx6ul"))
+ if (of_machine_is_compatible("fsl,imx6ul") ||
+ of_machine_is_compatible("fsl,imx6ull"))
imx6ul_opp_check_speed_grading(cpu_dev);
else
imx6q_opp_check_speed_grading(cpu_dev);
--
2.16.1
^ permalink raw reply related
* [PATCH v1] dma: imx-sdma: add virt-dma support
From: Robin Gong @ 2018-05-22 6:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1521735499-29138-1-git-send-email-yibin.gong@nxp.com>
Ping.
-----Original Message-----
From: Robin Gong
Sent: 2018?3?23? 0:18
To: dan.j.williams at intel.com; vinod.koul at intel.com
Cc: dmaengine at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
Subject: [PATCH v1] dma: imx-sdma: add virt-dma support
The legacy sdma driver has below limitations or drawbacks:
1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc
one page size for one channel regardless of only few BDs needed
most time. But in few cases, the max PAGE_SIZE maybe not enough.
2. One SDMA channel can't stop immediatley once channel disabled which
means SDMA interrupt may come in after this channel terminated.There
are some patches for this corner case such as commit "2746e2c389f9",
but not cover non-cyclic.
The common virt-dma overcomes the above limitations. It can alloc bd dynamically and free bd once this tx transfer done. No memory wasted or maximum limititation here, only depends on how many memory can be requested from kernel. For No.2, such issue can be workaround by checking if there is available descript("sdmac->desc") now once the unwanted interrupt coming. At last the common virt-dma is easier for sdma driver maintain.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/Kconfig | 1 +
drivers/dma/imx-sdma.c | 395 +++++++++++++++++++++++++++++++------------------
2 files changed, 253 insertions(+), 143 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 27df3e2..c4ce43c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -247,6 +247,7 @@ config IMX_SDMA
tristate "i.MX SDMA support"
depends on ARCH_MXC
select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
help
Support the i.MX SDMA engine. This engine is integrated into
Freescale i.MX25/31/35/51/53/6 chips.
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index ccd03c3..df79e73 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -48,6 +48,7 @@
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include "dmaengine.h"
+#include "virt-dma.h"
/* SDMA registers */
#define SDMA_H_C0PTR 0x000
@@ -291,10 +292,19 @@ struct sdma_context_data {
u32 scratch7;
} __attribute__ ((packed));
-#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
-
struct sdma_engine;
+struct sdma_desc {
+ struct virt_dma_desc vd;
+ struct list_head node;
+ unsigned int num_bd;
+ dma_addr_t bd_phys;
+ unsigned int buf_tail;
+ unsigned int buf_ptail;
+ struct sdma_channel *sdmac;
+ struct sdma_buffer_descriptor *bd;
+};
+
/**
* struct sdma_channel - housekeeping for a SDMA channel
*
@@ -310,19 +320,17 @@ struct sdma_engine;
* @num_bd max NUM_BD. number of descriptors currently handling
*/
struct sdma_channel {
+ struct virt_dma_chan vc;
+ struct list_head pending;
struct sdma_engine *sdma;
+ struct sdma_desc *desc;
unsigned int channel;
enum dma_transfer_direction direction;
enum sdma_peripheral_type peripheral_type;
unsigned int event_id0;
unsigned int event_id1;
enum dma_slave_buswidth word_size;
- unsigned int buf_tail;
- unsigned int buf_ptail;
- unsigned int num_bd;
unsigned int period_len;
- struct sdma_buffer_descriptor *bd;
- dma_addr_t bd_phys;
unsigned int pc_from_device, pc_to_device;
unsigned int device_to_device;
unsigned long flags;
@@ -330,15 +338,12 @@ struct sdma_channel {
unsigned long event_mask[2];
unsigned long watermark_level;
u32 shp_addr, per_addr;
- struct dma_chan chan;
- spinlock_t lock;
- struct dma_async_tx_descriptor desc;
enum dma_status status;
unsigned int chn_count;
unsigned int chn_real_count;
- struct tasklet_struct tasklet;
struct imx_dma_data data;
bool enabled;
+ u32 bd_size_sum;
};
#define IMX_DMA_SG_LOOP BIT(0)
@@ -398,6 +403,9 @@ struct sdma_engine {
u32 spba_start_addr;
u32 spba_end_addr;
unsigned int irq;
+ /* channel0 bd */
+ dma_addr_t bd0_phys;
+ struct sdma_buffer_descriptor *bd0;
};
static struct sdma_driver_data sdma_imx31 = { @@ -553,6 +561,8 @@ MODULE_DEVICE_TABLE(of, sdma_dt_ids);
#define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
+static void sdma_start_desc(struct sdma_channel *sdmac);
+
static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) {
u32 chnenbl0 = sdma->drvdata->chnenbl0; @@ -597,14 +607,7 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
static void sdma_enable_channel(struct sdma_engine *sdma, int channel) {
- unsigned long flags;
- struct sdma_channel *sdmac = &sdma->channel[channel];
-
writel(BIT(channel), sdma->regs + SDMA_H_START);
-
- spin_lock_irqsave(&sdmac->lock, flags);
- sdmac->enabled = true;
- spin_unlock_irqrestore(&sdmac->lock, flags);
}
/*
@@ -632,7 +635,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma) static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
u32 address)
{
- struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
+ struct sdma_buffer_descriptor *bd0 = sdma->bd0;
void *buf_virt;
dma_addr_t buf_phys;
int ret;
@@ -691,23 +694,16 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) static void sdma_update_channel_loop(struct sdma_channel *sdmac) {
struct sdma_buffer_descriptor *bd;
+ struct sdma_desc *desc = sdmac->desc;
int error = 0;
enum dma_status old_status = sdmac->status;
- unsigned long flags;
-
- spin_lock_irqsave(&sdmac->lock, flags);
- if (!sdmac->enabled) {
- spin_unlock_irqrestore(&sdmac->lock, flags);
- return;
- }
- spin_unlock_irqrestore(&sdmac->lock, flags);
/*
* loop mode. Iterate over descriptors, re-setup them and
* call callback function.
*/
- while (1) {
- bd = &sdmac->bd[sdmac->buf_tail];
+ while (desc) {
+ bd = &desc->bd[desc->buf_tail];
if (bd->mode.status & BD_DONE)
break;
@@ -726,8 +722,8 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
sdmac->chn_real_count = bd->mode.count;
bd->mode.status |= BD_DONE;
bd->mode.count = sdmac->period_len;
- sdmac->buf_ptail = sdmac->buf_tail;
- sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
+ desc->buf_ptail = desc->buf_tail;
+ desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
/*
* The callback is called from the interrupt context in order @@ -735,15 +731,16 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
* SDMA transaction status by the time the client tasklet is
* executed.
*/
-
- dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
+ spin_unlock(&sdmac->vc.lock);
+ dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
+ spin_lock(&sdmac->vc.lock);
if (error)
sdmac->status = old_status;
}
}
-static void mxc_sdma_handle_channel_normal(unsigned long data)
+static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
{
struct sdma_channel *sdmac = (struct sdma_channel *) data;
struct sdma_buffer_descriptor *bd;
@@ -754,8 +751,8 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
* non loop mode. Iterate over all descriptors, collect
* errors and call callback function
*/
- for (i = 0; i < sdmac->num_bd; i++) {
- bd = &sdmac->bd[i];
+ for (i = 0; i < sdmac->desc->num_bd; i++) {
+ bd = &sdmac->desc->bd[i];
if (bd->mode.status & (BD_DONE | BD_RROR))
error = -EIO;
@@ -766,10 +763,6 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
sdmac->status = DMA_ERROR;
else
sdmac->status = DMA_COMPLETE;
-
- dma_cookie_complete(&sdmac->desc);
-
- dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
}
static irqreturn_t sdma_int_handler(int irq, void *dev_id) @@ -785,13 +778,24 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
while (stat) {
int channel = fls(stat) - 1;
struct sdma_channel *sdmac = &sdma->channel[channel];
-
- if (sdmac->flags & IMX_DMA_SG_LOOP)
- sdma_update_channel_loop(sdmac);
- else
- tasklet_schedule(&sdmac->tasklet);
+ struct sdma_desc *desc;
+
+ spin_lock(&sdmac->vc.lock);
+ desc = sdmac->desc;
+ if (desc) {
+ if (sdmac->flags & IMX_DMA_SG_LOOP) {
+ sdma_update_channel_loop(sdmac);
+ } else {
+ mxc_sdma_handle_channel_normal(sdmac);
+ vchan_cookie_complete(&desc->vd);
+ if (!list_empty(&sdmac->pending))
+ list_del(&desc->node);
+ sdma_start_desc(sdmac);
+ }
+ }
__clear_bit(channel, &stat);
+ spin_unlock(&sdmac->vc.lock);
}
return IRQ_HANDLED;
@@ -897,7 +901,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
int channel = sdmac->channel;
int load_address;
struct sdma_context_data *context = sdma->context;
- struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
+ struct sdma_buffer_descriptor *bd0 = sdma->bd0;
int ret;
unsigned long flags;
@@ -946,7 +950,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
static struct sdma_channel *to_sdma_chan(struct dma_chan *chan) {
- return container_of(chan, struct sdma_channel, chan);
+ return container_of(chan, struct sdma_channel, vc.chan);
}
static int sdma_disable_channel(struct dma_chan *chan) @@ -954,15 +958,10 @@ static int sdma_disable_channel(struct dma_chan *chan)
struct sdma_channel *sdmac = to_sdma_chan(chan);
struct sdma_engine *sdma = sdmac->sdma;
int channel = sdmac->channel;
- unsigned long flags;
writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
sdmac->status = DMA_ERROR;
- spin_lock_irqsave(&sdmac->lock, flags);
- sdmac->enabled = false;
- spin_unlock_irqrestore(&sdmac->lock, flags);
-
return 0;
}
@@ -1097,42 +1096,101 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac,
return 0;
}
-static int sdma_request_channel(struct sdma_channel *sdmac)
+static int sdma_alloc_bd(struct sdma_desc *desc)
{
- struct sdma_engine *sdma = sdmac->sdma;
- int channel = sdmac->channel;
- int ret = -EBUSY;
+ u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
+ int ret = 0;
+ unsigned long flags;
- sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
+ desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
GFP_KERNEL);
- if (!sdmac->bd) {
+ if (!desc->bd) {
ret = -ENOMEM;
goto out;
}
- sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
- sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
+ spin_lock_irqsave(&desc->sdmac->vc.lock, flags);
+ desc->sdmac->bd_size_sum += bd_size;
+ spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags);
- sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
- return 0;
out:
-
return ret;
}
-static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
+static void sdma_free_bd(struct sdma_desc *desc)
{
+ u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
unsigned long flags;
- struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
- dma_cookie_t cookie;
- spin_lock_irqsave(&sdmac->lock, flags);
+ if (desc->bd) {
+ dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
+
+ spin_lock_irqsave(&desc->sdmac->vc.lock, flags);
+ desc->sdmac->bd_size_sum -= bd_size;
+ spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags);
+ }
+}
+
+static int sdma_request_channel0(struct sdma_engine *sdma) {
+ int ret = 0;
+
+ sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
+ GFP_KERNEL);
+ if (!sdma->bd0) {
+ ret = -ENOMEM;
+ goto out;
+ }
- cookie = dma_cookie_assign(tx);
+ sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
+ sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
- spin_unlock_irqrestore(&sdmac->lock, flags);
+ sdma_set_channel_priority(&sdma->channel[0],
+MXC_SDMA_DEFAULT_PRIORITY);
+out:
- return cookie;
+ return ret;
+}
+
+static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor
+*t) {
+ return container_of(t, struct sdma_desc, vd.tx); }
+
+static void sdma_desc_free(struct virt_dma_desc *vd) {
+ struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
+
+ if (desc) {
+ sdma_free_bd(desc);
+ kfree(desc);
+ }
+}
+
+static int sdma_terminate_all(struct dma_chan *chan) {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&sdmac->vc.lock, flags);
+ vchan_get_all_descriptors(&sdmac->vc, &head);
+ while (!list_empty(&sdmac->pending)) {
+ struct sdma_desc *desc = list_first_entry(&sdmac->pending,
+ struct sdma_desc, node);
+
+ list_del(&desc->node);
+ spin_unlock_irqrestore(&sdmac->vc.lock, flags);
+ sdmac->vc.desc_free(&desc->vd);
+ spin_lock_irqsave(&sdmac->vc.lock, flags);
+ }
+
+ if (sdmac->desc)
+ sdmac->desc = NULL;
+ spin_unlock_irqrestore(&sdmac->vc.lock, flags);
+ vchan_dma_desc_free_list(&sdmac->vc, &head);
+ sdma_disable_channel_with_delay(chan);
+
+ return 0;
}
static int sdma_alloc_chan_resources(struct dma_chan *chan) @@ -1168,18 +1226,11 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
if (ret)
goto disable_clk_ipg;
- ret = sdma_request_channel(sdmac);
- if (ret)
- goto disable_clk_ahb;
-
ret = sdma_set_channel_priority(sdmac, prio);
if (ret)
goto disable_clk_ahb;
- dma_async_tx_descriptor_init(&sdmac->desc, chan);
- sdmac->desc.tx_submit = sdma_tx_submit;
- /* txd.flags will be overwritten in prep funcs */
- sdmac->desc.flags = DMA_CTRL_ACK;
+ sdmac->bd_size_sum = 0;
return 0;
@@ -1195,7 +1246,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
struct sdma_channel *sdmac = to_sdma_chan(chan);
struct sdma_engine *sdma = sdmac->sdma;
- sdma_disable_channel(chan);
+ sdma_terminate_all(chan);
if (sdmac->event_id0)
sdma_event_disable(sdmac, sdmac->event_id0); @@ -1207,12 +1258,43 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
sdma_set_channel_priority(sdmac, 0);
- dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
-
clk_disable(sdma->clk_ipg);
clk_disable(sdma->clk_ahb);
}
+static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
+ enum dma_transfer_direction direction, u32 bds) {
+ struct sdma_desc *desc;
+
+ desc = kzalloc((sizeof(*desc)), GFP_KERNEL);
+ if (!desc)
+ goto err_out;
+
+ sdmac->status = DMA_IN_PROGRESS;
+ sdmac->direction = direction;
+ sdmac->flags = 0;
+ sdmac->chn_count = 0;
+ sdmac->chn_real_count = 0;
+
+ desc->sdmac = sdmac;
+ desc->num_bd = bds;
+ INIT_LIST_HEAD(&desc->node);
+
+ if (sdma_alloc_bd(desc))
+ goto err_desc_out;
+
+ if (sdma_load_context(sdmac))
+ goto err_desc_out;
+
+ return desc;
+
+err_desc_out:
+ kfree(desc);
+err_out:
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
struct dma_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, enum dma_transfer_direction direction, @@ -1223,35 +1305,24 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
int ret, i, count;
int channel = sdmac->channel;
struct scatterlist *sg;
+ struct sdma_desc *desc;
- if (sdmac->status == DMA_IN_PROGRESS)
+ if (!chan)
return NULL;
- sdmac->status = DMA_IN_PROGRESS;
-
- sdmac->flags = 0;
- sdmac->buf_tail = 0;
- sdmac->buf_ptail = 0;
- sdmac->chn_real_count = 0;
+ desc = sdma_transfer_init(sdmac, direction, sg_len);
+ if (!desc)
+ goto err_out;
dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
sg_len, channel);
- sdmac->direction = direction;
ret = sdma_load_context(sdmac);
if (ret)
goto err_out;
- if (sg_len > NUM_BD) {
- dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
- channel, sg_len, NUM_BD);
- ret = -EINVAL;
- goto err_out;
- }
-
- sdmac->chn_count = 0;
for_each_sg(sgl, sg, sg_len, i) {
- struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
+ struct sdma_buffer_descriptor *bd = &desc->bd[i];
int param;
bd->buffer_addr = sg->dma_address;
@@ -1262,7 +1333,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
channel, count, 0xffff);
ret = -EINVAL;
- goto err_out;
+ goto err_bd_out;
}
bd->mode.count = count;
@@ -1307,10 +1378,11 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
bd->mode.status = param;
}
- sdmac->num_bd = sg_len;
- sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
+ return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
- return &sdmac->desc;
+err_bd_out:
+ sdma_free_bd(desc);
+ kfree(desc);
err_out:
sdmac->status = DMA_ERROR;
return NULL;
@@ -1326,39 +1398,32 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
int num_periods = buf_len / period_len;
int channel = sdmac->channel;
int ret, i = 0, buf = 0;
+ struct sdma_desc *desc;
dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
- if (sdmac->status == DMA_IN_PROGRESS)
- return NULL;
-
- sdmac->status = DMA_IN_PROGRESS;
+ /* Now allocate and setup the descriptor. */
+ desc = sdma_transfer_init(sdmac, direction, num_periods);
+ if (!desc)
+ goto err_out;
- sdmac->buf_tail = 0;
- sdmac->buf_ptail = 0;
- sdmac->chn_real_count = 0;
+ desc->buf_tail = 0;
+ desc->buf_ptail = 0;
sdmac->period_len = period_len;
-
sdmac->flags |= IMX_DMA_SG_LOOP;
- sdmac->direction = direction;
+
ret = sdma_load_context(sdmac);
if (ret)
goto err_out;
- if (num_periods > NUM_BD) {
- dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
- channel, num_periods, NUM_BD);
- goto err_out;
- }
-
if (period_len > 0xffff) {
dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
channel, period_len, 0xffff);
- goto err_out;
+ goto err_bd_out;
}
while (buf < buf_len) {
- struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
+ struct sdma_buffer_descriptor *bd = &desc->bd[i];
int param;
bd->buffer_addr = dma_addr;
@@ -1366,7 +1431,7 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
bd->mode.count = period_len;
if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
- goto err_out;
+ goto err_bd_out;
if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
bd->mode.command = 0;
else
@@ -1389,10 +1454,10 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
i++;
}
- sdmac->num_bd = num_periods;
- sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
-
- return &sdmac->desc;
+ return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
+err_bd_out:
+ sdma_free_bd(desc);
+ kfree(desc);
err_out:
sdmac->status = DMA_ERROR;
return NULL;
@@ -1432,26 +1497,74 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan, {
struct sdma_channel *sdmac = to_sdma_chan(chan);
u32 residue;
+ struct virt_dma_desc *vd;
+ struct sdma_desc *desc;
+ enum dma_status ret;
+ unsigned long flags;
- if (sdmac->flags & IMX_DMA_SG_LOOP)
- residue = (sdmac->num_bd - sdmac->buf_ptail) *
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE && txstate) {
+ residue = sdmac->chn_count - sdmac->chn_real_count;
+ return ret;
+ }
+
+ spin_lock_irqsave(&sdmac->vc.lock, flags);
+ vd = vchan_find_desc(&sdmac->vc, cookie);
+ desc = to_sdma_desc(&vd->tx);
+ if (vd) {
+ if (sdmac->flags & IMX_DMA_SG_LOOP)
+ residue = (desc->num_bd - desc->buf_ptail) *
sdmac->period_len - sdmac->chn_real_count;
- else
+ else
+ residue = sdmac->chn_count - sdmac->chn_real_count;
+ } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
residue = sdmac->chn_count - sdmac->chn_real_count;
+ } else {
+ residue = 0;
+ }
+ ret = sdmac->status;
+ spin_unlock_irqrestore(&sdmac->vc.lock, flags);
dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
residue);
- return sdmac->status;
+ return ret;
+}
+
+static void sdma_start_desc(struct sdma_channel *sdmac) {
+ struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
+ struct sdma_desc *desc;
+ struct sdma_engine *sdma = sdmac->sdma;
+ int channel = sdmac->channel;
+
+ if (!vd) {
+ sdmac->desc = NULL;
+ return;
+ }
+ sdmac->desc = desc = to_sdma_desc(&vd->tx);
+ /*
+ * Do not delete the node in desc_issued list in cyclic mode, otherwise
+ * the desc alloced will never be freed in vchan_dma_desc_free_list
+ */
+ if (!(sdmac->flags & IMX_DMA_SG_LOOP)) {
+ list_add_tail(&sdmac->desc->node, &sdmac->pending);
+ list_del(&vd->node);
+ }
+ sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
+ sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
+ sdma_enable_channel(sdma, sdmac->channel);
}
static void sdma_issue_pending(struct dma_chan *chan) {
struct sdma_channel *sdmac = to_sdma_chan(chan);
- struct sdma_engine *sdma = sdmac->sdma;
+ unsigned long flags;
- if (sdmac->status == DMA_IN_PROGRESS)
- sdma_enable_channel(sdma, sdmac->channel);
+ spin_lock_irqsave(&sdmac->vc.lock, flags);
+ if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
+ sdma_start_desc(sdmac);
+ spin_unlock_irqrestore(&sdmac->vc.lock, flags);
}
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
@@ -1657,7 +1770,7 @@ static int sdma_init(struct sdma_engine *sdma)
for (i = 0; i < MAX_DMA_CHANNELS; i++)
writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
- ret = sdma_request_channel(&sdma->channel[0]);
+ ret = sdma_request_channel0(sdma);
if (ret)
goto err_dma_alloc;
@@ -1819,22 +1932,17 @@ static int sdma_probe(struct platform_device *pdev)
struct sdma_channel *sdmac = &sdma->channel[i];
sdmac->sdma = sdma;
- spin_lock_init(&sdmac->lock);
-
- sdmac->chan.device = &sdma->dma_device;
- dma_cookie_init(&sdmac->chan);
sdmac->channel = i;
-
- tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
- (unsigned long) sdmac);
+ sdmac->status = DMA_IN_PROGRESS;
+ sdmac->vc.desc_free = sdma_desc_free;
+ INIT_LIST_HEAD(&sdmac->pending);
/*
* Add the channel to the DMAC list. Do not add channel 0 though
* because we need it internally in the SDMA driver. This also means
* that channel 0 in dmaengine counting matches sdma channel 1.
*/
if (i)
- list_add_tail(&sdmac->chan.device_node,
- &sdma->dma_device.channels);
+ vchan_init(&sdmac->vc, &sdma->dma_device);
}
ret = sdma_init(sdma);
@@ -1879,7 +1987,7 @@ static int sdma_probe(struct platform_device *pdev)
sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
sdma->dma_device.device_config = sdma_config;
- sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
+ sdma->dma_device.device_terminate_all = sdma_terminate_all;
sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; @@ -1939,7 +2047,8 @@ static int sdma_remove(struct platform_device *pdev)
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
struct sdma_channel *sdmac = &sdma->channel[i];
- tasklet_kill(&sdmac->tasklet);
+ tasklet_kill(&sdmac->vc.task);
+ sdma_free_chan_resources(&sdmac->vc.chan);
}
platform_set_drvdata(pdev, NULL);
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/2] cpufreq: imx6q: check speed grades for i.MX6ULL
From: Sébastien Szymanski @ 2018-05-22 6:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOh2x==MCPnANhww2JYhGkaALcAPZe_qAUcbZmhyCDwPjOjT2Q@mail.gmail.com>
On 04/19/2018 11:09 AM, Viresh Kumar wrote:
> On Thu, Apr 19, 2018 at 12:49 PM, S?bastien Szymanski
> <sebastien.szymanski@armadeus.com> wrote:
>> Check the max speed supported from the fuses for i.MX6ULL and update the
>> operating points table accordingly.
>>
>> Signed-off-by: S?bastien Szymanski <sebastien.szymanski@armadeus.com>
>> ---
>>
>> Changes for v2:
>> - none
>
> Please cc all the maintainers present in MAINTAINERS file. You missed cc'ing me
> and I missed V1 earlier.
Ok.
>
>> drivers/cpufreq/imx6q-cpufreq.c | 29 +++++++++++++++++++++++------
>> 1 file changed, 23 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 83cf631fc9bc..f094687cae52 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -266,6 +266,8 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
>> }
>>
>> #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
>> +#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
>> +#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
>
> Looking at the wording everywhere, this represents the maximum
> supported frequency ?
Yes.
> In that case ...
>
>>
>> static void imx6ul_opp_check_speed_grading(struct device *dev)
>> {
>> @@ -287,16 +289,30 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
>> * Speed GRADING[1:0] defines the max speed of ARM:
>> * 2b'00: Reserved;
>> * 2b'01: 528000000Hz;
>> - * 2b'10: 696000000Hz;
>> - * 2b'11: Reserved;
>> + * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
>> + * 2b'11: 900000000Hz on i.MX6ULL only;
>> * We need to set the max speed of ARM according to fuse map.
>> */
>> val = readl_relaxed(base + OCOTP_CFG3);
>> val >>= OCOTP_CFG3_SPEED_SHIFT;
>> val &= 0x3;
>> - if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
>> - if (dev_pm_opp_disable(dev, 696000000))
>> - dev_warn(dev, "failed to disable 696MHz OPP\n");
>> +
>> + if (of_machine_is_compatible("fsl,imx6ul")) {
>> + if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
>> + if (dev_pm_opp_disable(dev, 696000000))
>> + dev_warn(dev, "failed to disable 696MHz OPP\n");
>> + }
>> +
>> + if (of_machine_is_compatible("fsl,imx6ull")) {
>> + if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
>> + if (dev_pm_opp_disable(dev, 792000000))
>> + dev_warn(dev, "failed to disable 792MHz OPP\n");
>> +
>> + if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
>> + if (dev_pm_opp_disable(dev, 900000000))
>> + dev_warn(dev, "failed to disable 900MHz OPP\n");
>
> ... this looks wrong to me as you will end up disabling 792 MHz if max speed is
> 900 MHz.
The datasheet of the 900 MHz i.MX6ULL version [1] does not list 792 MHz
as an operating range, that's why 792 MHz is disabled when max speed is
900 MHz.
[1] https://www.nxp.com/docs/en/data-sheet/IMX6ULLCEC.pdf (page 24,
table 10. "Operating Ranges")
Regards,
>
>> + }
>> +
>> iounmap(base);
>> put_node:
>> of_node_put(np);
>> @@ -356,7 +372,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
>> goto put_reg;
>> }
>>
>> - if (of_machine_is_compatible("fsl,imx6ul"))
>> + if (of_machine_is_compatible("fsl,imx6ul") ||
>> + of_machine_is_compatible("fsl,imx6ull"))
>> imx6ul_opp_check_speed_grading(cpu_dev);
>> else
>> imx6q_opp_check_speed_grading(cpu_dev);
>> --
>> 2.16.1
>>
--
S?bastien Szymanski
Software engineer, Armadeus Systems
Tel: +33 (0)9 72 29 41 44
Fax: +33 (0)9 72 28 79 26
^ permalink raw reply
* [PATCH V2] ARM: davinci_all_defconfig: set CONFIG_BACKLIGHT_PWM=m
From: Sekhar Nori @ 2018-05-22 5:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518180953.9860-1-aford173@gmail.com>
On Friday 18 May 2018 11:39 PM, Adam Ford wrote:
> The da850-evm came with an LCD with a backlight tied to a pwm. This
> enables CONFIG_BACKLIGHT_PWM as a module so the PWM backlight can be
> used to maintain brightness control of the backlight.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Applied for v4.19.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] ARM: dts: da850-evm: Enable SATA port
From: Sekhar Nori @ 2018-05-22 5:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518204339.14298-1-aford173@gmail.com>
On Saturday 19 May 2018 02:13 AM, Adam Ford wrote:
> The DA850-EVM from Logic PD has a SATA port and the module that went
> with the kit support it as well. This patch will enable the SATA
> controller.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
Applied for v4.19
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 12/33] clk: bcm2835: use match_string() helper
From: Yisheng Xie @ 2018-05-22 3:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHp75Vf6rDpFQCt+qG3DSWKZm36F1hkAVPtGzr6NHPuQg4vhXQ@mail.gmail.com>
Hi Andy,
On 2018/5/22 5:50, Andy Shevchenko wrote:
> On Mon, May 21, 2018 at 2:57 PM, Yisheng Xie <xieyisheng1@huawei.com> wrote:
>> match_string() returns the index of an array for a matching string,
>> which can be used intead of open coded variant.
>>
>> Cc: Michael Turquette <mturquette@baylibre.com>
>> Cc: Stephen Boyd <sboyd@kernel.org>
>> Cc: Eric Anholt <eric@anholt.net>
>> Cc: Stefan Wahren <stefan.wahren@i2se.com>
>> Cc: linux-clk at vger.kernel.org
>> Cc: linux-rpi-kernel at lists.infradead.org
>> Cc: linux-arm-kernel at lists.infradead.org
>> Signed-off-by: Yisheng Xie <xieyisheng1@huawei.com>
>
>> - size_t i, j;
>> - int ret;
>> + int i, ret;
>
> I do not see any need to change type for i.
Right, I just want to smaller the line of code, for unsinged int is also OK for i.
Anyway, I can change it as your suggestion in next version.
Thanks
Yisheng
>
>> + ret = match_string(cprman_parent_names,
>> + ARRAY_SIZE(cprman_parent_names),
>> + parents[i]);
>> + if (ret >= 0)
>> + parents[i] = cprman->real_parent_names[ret];
>
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
From: Anson Huang @ 2018-05-22 3:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com>
i.MX6UL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972..405e068 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -437,6 +437,7 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -450,6 +451,7 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -462,6 +464,7 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -474,6 +477,7 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -486,6 +490,7 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] clk: imx6ul: add GPIO clock gates
From: Anson Huang @ 2018-05-22 3:25 UTC (permalink / raw)
To: linux-arm-kernel
i.MX6UL has GPIO clock gates in CCM CCGR, add
them into clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
drivers/clk/imx/clk-imx6ul.c | 5 +++++
include/dt-bindings/clock/imx6ul-clock.h | 31 ++++++++++++++++++-------------
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index ba563ba..3ea2d97 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
if (clk_on_imx6ull())
clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
+ clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
/* CCGR1 */
clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
@@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
+ clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
+ clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
/* CCGR2 */
if (clk_on_imx6ull()) {
@@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
+ clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
@@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
+ clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index 9564597..1291328 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -242,20 +242,25 @@
#define IMX6UL_CLK_CKO2_PODF 229
#define IMX6UL_CLK_CKO2 230
#define IMX6UL_CLK_CKO 231
+#define IMX6UL_CLK_GPIO1 232
+#define IMX6UL_CLK_GPIO2 233
+#define IMX6UL_CLK_GPIO3 234
+#define IMX6UL_CLK_GPIO4 235
+#define IMX6UL_CLK_GPIO5 236
/* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED 232
-#define IMX6ULL_CLK_ESAI_PODF 233
-#define IMX6ULL_CLK_ESAI_EXTAL 234
-#define IMX6ULL_CLK_ESAI_MEM 235
-#define IMX6ULL_CLK_ESAI_IPG 236
-#define IMX6ULL_CLK_DCP_CLK 237
-#define IMX6ULL_CLK_EPDC_PRE_SEL 238
-#define IMX6ULL_CLK_EPDC_SEL 239
-#define IMX6ULL_CLK_EPDC_PODF 240
-#define IMX6ULL_CLK_EPDC_ACLK 241
-#define IMX6ULL_CLK_EPDC_PIX 242
-#define IMX6ULL_CLK_ESAI_SEL 243
-#define IMX6UL_CLK_END 244
+#define IMX6ULL_CLK_ESAI_PRED 237
+#define IMX6ULL_CLK_ESAI_PODF 238
+#define IMX6ULL_CLK_ESAI_EXTAL 239
+#define IMX6ULL_CLK_ESAI_MEM 240
+#define IMX6ULL_CLK_ESAI_IPG 241
+#define IMX6ULL_CLK_DCP_CLK 242
+#define IMX6ULL_CLK_EPDC_PRE_SEL 243
+#define IMX6ULL_CLK_EPDC_SEL 244
+#define IMX6ULL_CLK_EPDC_PODF 245
+#define IMX6ULL_CLK_EPDC_ACLK 246
+#define IMX6ULL_CLK_EPDC_PIX 247
+#define IMX6ULL_CLK_ESAI_SEL 248
+#define IMX6UL_CLK_END 249
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
--
2.7.4
^ permalink raw reply related
* [PATCH 12/14] ARM: spectre-v2: KVM: invalidate icache on guest exit for Brahma B15
From: Florian Fainelli @ 2018-05-22 3:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fKjFj-00064b-62@rmk-PC.armlinux.org.uk>
On 05/21/2018 04:45 AM, Russell King wrote:
> Include Brahma B15 in the Spectre v2 KVM workarounds.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* [PATCH 06/14] ARM: spectre-v2: harden branch predictor on context switches
From: Florian Fainelli @ 2018-05-22 3:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fKjFD-00063u-Q5@rmk-PC.armlinux.org.uk>
On 05/21/2018 04:44 AM, Russell King wrote:
> Harden the branch predictor against Spectre v2 attacks on context
> switches for ARMv7 and later CPUs. We do this by:
>
> Cortex A9, A12, A17, A73, A75: invalidating the BTB.
> Cortex A15, Brahma B15: invalidating the instruction cache.
>
> Cortex A57 and Cortex A72 are not addressed in this patch.
>
> Cortex R7 and Cortex R8 are also not addressed as we do not enforce
> memory protection on these cores.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
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