* [PATCH] cpufreq: Add Kryo CPU scaling driver
From: Viresh Kumar @ 2018-05-22 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <001401d3f1a2$c7328850$559798f0$@codeaurora.org>
On 22-05-18, 10:59, ilialin at codeaurora.org wrote:
> OK, I think I found out the way. Would this be correct?
> -----------------------------------------------------------------------------------------------
> extern struct cpu_topology cpu_topology[NR_CPUS];
>
> static struct device *qcom_cpufreq_kryo_get_cluster_lead(int cluster)
> {
> unsigned cpu;
>
> for_each_possible_cpu(cpu) {
> if ((cluster == cpu_topology[cpu].cluster_id) &&
> (0 == cpu_topology[cpu].core_id))
> return get_cpu_device(cpu);
> }
>
> return NULL;
> }
Okay, this is what you should do IMHO.
for_each_possible_cpu(cpu) {
cpu_dev = xxx..
ret = dev_pm_opp_set_supported_hw(cpu_dev, xxx, xxx);
if (ret && ret != -EBUSY)
error-out.
}
This would require a trivial patch for the OPP core to not throw an
error message with -EBUSY. I can do that separately.
--
viresh
^ permalink raw reply
* Re: [PATCH v11 00/27] ARM: davinci: convert to common clock framework
From: Sekhar Nori @ 2018-05-22 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518164829.27052-1-david@lechnology.com>
Hi David,
On Friday 18 May 2018 10:18 PM, David Lechner wrote:
> This series converts mach-davinci to use the common clock framework.
>
> The series works like this, the first 3 patches fix some issues with the clock
> drivers that have already been accepted into the mainline kernel.
>
> Then, starting with "ARM: davinci: pass clock as parameter to
> davinci_timer_init()", we get the mach code ready for the switch by adding the
> code needed for the new clock drivers and adding #ifndef CONFIG_COMMON_CLK
> around the legacy clocks so that we can switch easily between the old and the
> new.
>
> "ARM: davinci: switch to common clock framework" actually flips the switch
> to start using the new clock drivers. Then the next 8 patches remove all
> of the old clock code.
>
> The final four patches add device tree clock support to the one SoC that
> supports it.
>
> This series has been tested on TI OMAP-L138 LCDK (both device tree and legacy
> board file).
If you do end up sending a v12, you can leave out the mach-davinci
portions unless there are any changes you need to make. I will pick them
up from this series once the driver dependencies are merged.
I do hope the drivers/clk/* changes can be merged from v4.18.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v2 00/16] Add System Error Interrupt support to Armada SoCs
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired
inputs. Its purpose is to aggregate all CP interrupts and report them to
the AP through MSIs. The ICU writes into GIC registers (AP side) by way
of the interconnect. These interrupts can be of several groups:
- SecuRe (SR);
- Non-SecuRe (NSR);
- System Error Interrupts (SEI);
- RAM Error Interrupts (REI);
- ...
Each ICU wired interrupt can be of any of these groups. The group is
encoded in the MSI payload.
Until now, only the non-secure interrupts (NSR) were handled by the ICU
driver. Interrupts of another group could work by chance because the
ICU driver does not erase all ATF configuration; it only erases the
configuration for NSR interrupts.
This series aims at adding support for the System Error Interrupts
(SEI). For this purpose, the ICU driver is a bit reworked to separate
the ICU 'generic' configuration from the NSR-related handling. Then,
the SEI driver (part of the GIC) is introduced and finally, support for
SEI interrupts are also added to the ICU driver.
The SEI driver is a bit different than its cousin the GICP because it
must handle MSIs from the CPs, as well as wired interrupts from the AP
itself. MSIs and wired interrupts will automatically update two
registers (GICP_SECR0/GICP_SECR1) that will trigger a single top-level
interrupt (SPI #32).
As this is my first contribution in the IRQ subsystem I might have
missed some specificities or misunderstood the API, please do not
hesitate to correct me if I'm wrong.
Also, for the sake of understandability (and because I love ASCII art),
this is a try to explain the ICU/SEI architecture:
+----------------------------------------------------------------------+
| |
| |
| SPIa SPIb SPIz SPI 32 |
| ^ ^ ^ ^ |
| | | . . . | | |
| | | | | |
| | | . . . | | |
| +------------------------+ +---------------------------------+ |
| | | | | | | | | |
| | | | | | | SEI | | |
| | | | . . . | | | ________|_______ | |
| | | | | | | /___SEI_SECR_____\ | |
| | |____|___________| | | / | \\ | |
| | \_GICP_SETSPI _/ | | / | \\ | |
| | || | | / ... | \\ | |
| | GICP || | | | | \\ | |
| +----------------||------+ +--|----------|------------||-----+ |
| || | | || |
| || | ... | || |
| || | | || |
| || | | || |
| \\_______ int 0 ... int 20 // |
| \_NSR__ \ // |
| \\ ____________________// |
| \\ /________SEI_________/ |
| AP 806 \\// |
| || |
+---------------------------------||-----------------------------------+
||
|| Interconnect
||\
||\\______
|| \______ <---> Others CP 110
||
+---------------------------------||-----------------------------------+
| || |
| CP 110 || |
| || |
| +-------------------------||------------------------+ |
| | || MSI | |
| | ICU || | |
| | /--------------/ \------\ | |
| | / /-------/ \ | |
| | / / / \ | |
| | / / / . . . \ | |
| | / / / \ | |
| | NSR NSR SEI NSR | |
| | | | | | | |
| +----^-------^-------^-----------------^------------+ |
| | | | | |
| | | | . . . | |
| | | | | |
| int 0 int 1 int 2 int 206 |
| |
| |
+----------------------------------------------------------------------+
Thank you,
Miqu?l
Changes since v1:
=================
General
-------
* Spelling/function names/comments.
* Added Reviewed-by tags.
* Rebased on top of Marc Zyngier level-MSI series (tip:irq/core).
SEI
---
* Change the license for GPL-2.0 only in irq-mvebu-sei.c C file.
* Used alphabetic ordering when adding SEI driver in Makefile.
* Re-ordered register definitions by increasing offset.
* s/NB/COUNT/ in register definitions.
* avoid enabling all interrupt by default.
* fixed mask/unmask functions using the wrong hwirq number.
* removed hackish doorbell mechanism.
* Removed the ->xlate hook assigned for CP MSIs.
* Used devm_*() helpers.
* s/top_level_spi/parent_irq/ in probe.
* Added forgotten of_node_put(child).
* Reset the SEI registers before registering the IRQ domains.
* Introduced new DT property "marvell,sei-ranges" instead of using
"reg" to declare the range of MSI interrupts vs. wired interrupts in
the SEI subnodes.
* Finally did not change the ->alloc() about the fwspec->param[1]
line (to be checked by Marc).
ICU
---
* Updated the ICU documentation so the legacy bindings are still
documented somewhere.
* Added stable tags on the commit fixing the CP110 ICU node size.
* Removed the "syscon" compatible from the ICU node, instead the
syscon is created at probe time.
* s/user data/private data/ in the title of commit
"irqchip/irq-mvebu-icu: fix wrong user data retrieval"
Miquel Raynal (16):
dt-bindings/interrupt-controller: fix Marvell ICU length in the
example
arm64: dts: marvell: fix CP110 ICU node size
irqchip/irq-mvebu-icu: fix wrong private data retrieval
irqchip/irq-mvebu-icu: clarify the reset operation of configured
interrupts
irqchip/irq-mvebu-icu: switch to regmap
irqchip/irq-mvebu-icu: make irq_domain local
irqchip/irq-mvebu-icu: disociate ICU and NSR
irqchip/irq-mvebu-icu: support ICU subnodes
irqchip/irq-mvebu-sei: add new driver for Marvell SEI
arm64: marvell: enable SEI driver
irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI)
dt-bindings/interrupt-controller: update Marvell ICU bindings
dt-bindings/interrupt-controller: add documentation for Marvell SEI
controller
arm64: dts: marvell: add AP806 SEI subnode
arm64: dts: marvell: use new bindings for CP110 interrupts
arm64: dts: marvell: add CP110 ICU SEI subnode
.../bindings/interrupt-controller/marvell,icu.txt | 83 +++-
.../bindings/interrupt-controller/marvell,sei.txt | 50 +++
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 123 +++---
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mvebu-icu.c | 301 ++++++++++++---
drivers/irqchip/irq-mvebu-sei.c | 422 +++++++++++++++++++++
9 files changed, 872 insertions(+), 131 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
create mode 100644 drivers/irqchip/irq-mvebu-sei.c
--
2.14.1
^ permalink raw reply
* [PATCH v2 01/16] dt-bindings/interrupt-controller: fix Marvell ICU length in the example
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
index aa8bf2ec8905..649b7ec9d9b1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
@@ -39,7 +39,7 @@ Example:
icu: interrupt-controller at 1e0000 {
compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x10>;
+ reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 02/16] arm64: dts: marvell: fix CP110 ICU node size
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).
Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Cc: stable at vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 48cad7919efa..9fa41c54f69c 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -146,7 +146,7 @@
CP110_LABEL(icu): interrupt-controller at 1e0000 {
compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x10>;
+ reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
--
2.14.1
^ permalink raw reply related
* [PATCH v2 03/16] irqchip/irq-mvebu-icu: fix wrong private data retrieval
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
The irq_domain structure has an host_data pointer that just stores
private data. It is meant to not be touched by the IRQ core. However,
when it comes to MSI, the MSI layer adds its own private data there
with a structure that also has a host_data pointer.
Because this IRQ domain is an MSI domain, to access private data we
should do a d->host_data->host_data, also wrapped as
'platform_msi_get_host_data()'.
This bug was lying there silently because the 'icu' structure retrieved
this way was just called by dev_err(), only producing a
'(NULL device *):' output on the console.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 13063339b416..a2a3acd74491 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -105,7 +105,7 @@ static int
mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
unsigned long *hwirq, unsigned int *type)
{
- struct mvebu_icu *icu = d->host_data;
+ struct mvebu_icu *icu = platform_msi_get_host_data(d);
unsigned int icu_group;
/* Check the count of the parameters in dt */
--
2.14.1
^ permalink raw reply related
* [PATCH v2 04/16] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Rewrite a small section to clarify the reset operation of interrupts
already configured by ATF that we want to handle in the driver. This
will simplify the introduction of System Error Interrupts support.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index a2a3acd74491..0f2655d7f19e 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -258,8 +258,12 @@ static int mvebu_icu_probe(struct platform_device *pdev)
* avoid unpredictable SPI assignments done by firmware.
*/
for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
- u32 icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i));
- if ((icu_int >> ICU_GROUP_SHIFT) == ICU_GRP_NSR)
+ u32 icu_int, icu_grp;
+
+ icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i));
+ icu_grp = icu_int >> ICU_GROUP_SHIFT;
+
+ if (icu_grp == ICU_GRP_NSR)
writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
}
--
2.14.1
^ permalink raw reply related
* [PATCH v2 05/16] irqchip/irq-mvebu-icu: switch to regmap
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Before splitting the code to support multiple platform devices to
be probed (one for the ICU, one per interrupt group), let's switch to
regmap first by creating one in the ->probe().
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 45 +++++++++++++++++++++++++++--------------
1 file changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 0f2655d7f19e..3694c0d73c0d 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -18,6 +18,8 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
@@ -38,7 +40,7 @@
struct mvebu_icu {
struct irq_chip irq_chip;
- void __iomem *base;
+ struct regmap *regmap;
struct irq_domain *domain;
struct device *dev;
atomic_t initialized;
@@ -56,10 +58,10 @@ static void mvebu_icu_init(struct mvebu_icu *icu, struct msi_msg *msg)
return;
/* Set Clear/Set ICU SPI message address in AP */
- writel_relaxed(msg[0].address_hi, icu->base + ICU_SETSPI_NSR_AH);
- writel_relaxed(msg[0].address_lo, icu->base + ICU_SETSPI_NSR_AL);
- writel_relaxed(msg[1].address_hi, icu->base + ICU_CLRSPI_NSR_AH);
- writel_relaxed(msg[1].address_lo, icu->base + ICU_CLRSPI_NSR_AL);
+ regmap_write(icu->regmap, ICU_SETSPI_NSR_AH, msg[0].address_hi);
+ regmap_write(icu->regmap, ICU_SETSPI_NSR_AL, msg[0].address_lo);
+ regmap_write(icu->regmap, ICU_CLRSPI_NSR_AH, msg[1].address_hi);
+ regmap_write(icu->regmap, ICU_CLRSPI_NSR_AL, msg[1].address_lo);
}
static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
@@ -82,7 +84,7 @@ static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
icu_int = 0;
}
- writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
+ regmap_write(icu->regmap, ICU_INT_CFG(d->hwirq), icu_int);
/*
* The SATA unit has 2 ports, and a dedicated ICU entry per
@@ -94,10 +96,10 @@ static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
* configured (regardless of which port is actually in use).
*/
if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
- writel_relaxed(icu_int,
- icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
- writel_relaxed(icu_int,
- icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
+ regmap_write(icu->regmap, ICU_INT_CFG(ICU_SATA0_ICU_ID),
+ icu_int);
+ regmap_write(icu->regmap, ICU_INT_CFG(ICU_SATA1_ICU_ID),
+ icu_int);
}
}
@@ -204,12 +206,20 @@ static const struct irq_domain_ops mvebu_icu_domain_ops = {
.free = mvebu_icu_irq_domain_free,
};
+static struct regmap_config mvebu_icu_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "mvebu_icu",
+};
+
static int mvebu_icu_probe(struct platform_device *pdev)
{
struct mvebu_icu *icu;
struct device_node *node = pdev->dev.of_node;
struct device_node *gicp_dn;
struct resource *res;
+ void __iomem *regs;
int i;
icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
@@ -220,12 +230,17 @@ static int mvebu_icu_probe(struct platform_device *pdev)
icu->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- icu->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(icu->base)) {
+ regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(regs)) {
dev_err(&pdev->dev, "Failed to map icu base address.\n");
- return PTR_ERR(icu->base);
+ return PTR_ERR(regs);
}
+ icu->regmap = devm_regmap_init_mmio(icu->dev, regs,
+ &mvebu_icu_regmap_config);
+ if (IS_ERR(icu->regmap))
+ return PTR_ERR(icu->regmap);
+
icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"ICU.%x",
(unsigned int)res->start);
@@ -260,11 +275,11 @@ static int mvebu_icu_probe(struct platform_device *pdev)
for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
u32 icu_int, icu_grp;
- icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i));
+ regmap_read(icu->regmap, ICU_INT_CFG(i), &icu_int);
icu_grp = icu_int >> ICU_GROUP_SHIFT;
if (icu_grp == ICU_GRP_NSR)
- writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
+ regmap_write(icu->regmap, ICU_INT_CFG(i), 0);
}
icu->domain =
--
2.14.1
^ permalink raw reply related
* [PATCH v2 06/16] irqchip/irq-mvebu-icu: make irq_domain local
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Make the current MSI irq_domain local to ease the split between ICU
platform device code and NSR platform device code.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 3694c0d73c0d..607948870a14 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -41,7 +41,6 @@
struct mvebu_icu {
struct irq_chip irq_chip;
struct regmap *regmap;
- struct irq_domain *domain;
struct device *dev;
atomic_t initialized;
};
@@ -218,6 +217,7 @@ static int mvebu_icu_probe(struct platform_device *pdev)
struct mvebu_icu *icu;
struct device_node *node = pdev->dev.of_node;
struct device_node *gicp_dn;
+ struct irq_domain *irq_domain;
struct resource *res;
void __iomem *regs;
int i;
@@ -282,11 +282,11 @@ static int mvebu_icu_probe(struct platform_device *pdev)
regmap_write(icu->regmap, ICU_INT_CFG(i), 0);
}
- icu->domain =
+ irq_domain =
platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
mvebu_icu_write_msg,
&mvebu_icu_domain_ops, icu);
- if (!icu->domain) {
+ if (!irq_domain) {
dev_err(&pdev->dev, "Failed to create ICU domain\n");
return -ENOMEM;
}
--
2.14.1
^ permalink raw reply related
* [PATCH v2 07/16] irqchip/irq-mvebu-icu: disociate ICU and NSR
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
NSR (non-secure interrupts) are handled in the ICU driver like if there
was only this type of interrupt in the ICU. Change this behavior to
prepare the introduction of SEI (System Error Interrupts) support by
moving the NSR code in a separate function. This is done under the form
of a 'probe' function to ease future migration to NSR/SEI being platform
devices part of the ICU.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 58 +++++++++++++++++++++++------------------
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 607948870a14..24d45186eb6b 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -205,6 +205,37 @@ static const struct irq_domain_ops mvebu_icu_domain_ops = {
.free = mvebu_icu_irq_domain_free,
};
+static int mvebu_icu_subset_probe(struct platform_device *pdev)
+{
+ struct device_node *msi_parent_dn;
+ struct irq_domain *irq_domain;
+ struct mvebu_icu *icu;
+
+ icu = dev_get_drvdata(&pdev->dev);
+ if (!icu)
+ return -ENODEV;
+
+ pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, pdev->dev.of_node,
+ DOMAIN_BUS_PLATFORM_MSI);
+ if (!pdev->dev.msi_domain)
+ return -EPROBE_DEFER;
+
+ msi_parent_dn = irq_domain_get_of_node(pdev->dev.msi_domain);
+ if (!msi_parent_dn)
+ return -ENODEV;
+
+ irq_domain = platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
+ mvebu_icu_write_msg,
+ &mvebu_icu_domain_ops,
+ icu);
+ if (!irq_domain) {
+ dev_err(&pdev->dev, "Failed to create ICU MSI domain\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
static struct regmap_config mvebu_icu_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -215,9 +246,6 @@ static struct regmap_config mvebu_icu_regmap_config = {
static int mvebu_icu_probe(struct platform_device *pdev)
{
struct mvebu_icu *icu;
- struct device_node *node = pdev->dev.of_node;
- struct device_node *gicp_dn;
- struct irq_domain *irq_domain;
struct resource *res;
void __iomem *regs;
int i;
@@ -255,19 +283,6 @@ static int mvebu_icu_probe(struct platform_device *pdev)
icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent;
#endif
- /*
- * We're probed after MSI domains have been resolved, so force
- * resolution here.
- */
- pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, node,
- DOMAIN_BUS_PLATFORM_MSI);
- if (!pdev->dev.msi_domain)
- return -EPROBE_DEFER;
-
- gicp_dn = irq_domain_get_of_node(pdev->dev.msi_domain);
- if (!gicp_dn)
- return -ENODEV;
-
/*
* Clean all ICU interrupts with type SPI_NSR, required to
* avoid unpredictable SPI assignments done by firmware.
@@ -282,16 +297,9 @@ static int mvebu_icu_probe(struct platform_device *pdev)
regmap_write(icu->regmap, ICU_INT_CFG(i), 0);
}
- irq_domain =
- platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
- mvebu_icu_write_msg,
- &mvebu_icu_domain_ops, icu);
- if (!irq_domain) {
- dev_err(&pdev->dev, "Failed to create ICU domain\n");
- return -ENOMEM;
- }
+ platform_set_drvdata(pdev, icu);
- return 0;
+ return mvebu_icu_subset_probe(pdev);
}
static const struct of_device_id mvebu_icu_of_match[] = {
--
2.14.1
^ permalink raw reply related
* [PATCH v2 08/16] irqchip/irq-mvebu-icu: support ICU subnodes
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
The ICU can handle several type of interrupt, each of them being handled
differently on AP side. On CP side, the ICU should be able to make the
distinction between each interrupt group by pointing to the right parent.
This is done through the introduction of new bindings, presenting the ICU
node as the parent of multiple ICU sub-nodes, each of them being an
interrupt type with a different interrupt parent. ICU interrupt 'clients'
now directly point to the right sub-node, avoiding the need for the extra
ICU_GRP_* parameter.
ICU subnodes are probed automatically with devm_platform_populate(). If
the node as no child, the probe function for NSRs will still be called
'manually' in order to preserve backward compatibility with DT using the
old binding.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 90 ++++++++++++++++++++++++++++++++++-------
1 file changed, 75 insertions(+), 15 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 24d45186eb6b..977e47b2716f 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -43,6 +43,7 @@ struct mvebu_icu {
struct regmap *regmap;
struct device *dev;
atomic_t initialized;
+ bool legacy_bindings;
};
struct mvebu_icu_irq_data {
@@ -51,6 +52,30 @@ struct mvebu_icu_irq_data {
unsigned int type;
};
+static struct mvebu_icu *mvebu_icu_dev_get_drvdata(struct platform_device *pdev)
+{
+ struct mvebu_icu *icu;
+
+ /*
+ * Device data being populated means we should be using legacy bindings.
+ * Using the _parent_ device data means we should be using new bindings.
+ */
+ icu = dev_get_drvdata(&pdev->dev);
+ if (icu) {
+ if (!icu->legacy_bindings)
+ return ERR_PTR(-EINVAL);
+ } else {
+ icu = dev_get_drvdata(pdev->dev.parent);
+ if (!icu)
+ return ERR_PTR(-ENODEV);
+
+ if (icu->legacy_bindings)
+ return ERR_PTR(-EINVAL);
+ }
+
+ return icu;
+}
+
static void mvebu_icu_init(struct mvebu_icu *icu, struct msi_msg *msg)
{
if (atomic_cmpxchg(&icu->initialized, false, true))
@@ -107,31 +132,35 @@ mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
unsigned long *hwirq, unsigned int *type)
{
struct mvebu_icu *icu = platform_msi_get_host_data(d);
- unsigned int icu_group;
+ unsigned int param_count = icu->legacy_bindings ? 3 : 2;
/* Check the count of the parameters in dt */
- if (WARN_ON(fwspec->param_count < 3)) {
+ if (WARN_ON(fwspec->param_count != param_count)) {
dev_err(icu->dev, "wrong ICU parameter count %d\n",
fwspec->param_count);
return -EINVAL;
}
- /* Only ICU group type is handled */
- icu_group = fwspec->param[0];
- if (icu_group != ICU_GRP_NSR && icu_group != ICU_GRP_SR &&
- icu_group != ICU_GRP_SEI && icu_group != ICU_GRP_REI) {
- dev_err(icu->dev, "wrong ICU group type %x\n", icu_group);
- return -EINVAL;
+ if (icu->legacy_bindings) {
+ *hwirq = fwspec->param[1];
+ *type = fwspec->param[2];
+ if (fwspec->param[0] != ICU_GRP_NSR) {
+ dev_err(icu->dev, "wrong ICU group type %x\n",
+ fwspec->param[0]);
+ return -EINVAL;
+ }
+ } else {
+ *hwirq = fwspec->param[0];
+ *type = fwspec->param[1];
}
- *hwirq = fwspec->param[1];
if (*hwirq >= ICU_MAX_IRQS) {
dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
return -EINVAL;
}
/* Mask the type to prevent wrong DT configuration */
- *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+ *type &= IRQ_TYPE_SENSE_MASK;
return 0;
}
@@ -157,7 +186,10 @@ mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
goto free_irqd;
}
- icu_irqd->icu_group = fwspec->param[0];
+ if (icu->legacy_bindings)
+ icu_irqd->icu_group = fwspec->param[0];
+ else
+ icu_irqd->icu_group = ICU_GRP_NSR;
icu_irqd->icu = icu;
err = platform_msi_domain_alloc(domain, virq, nr_irqs);
@@ -211,9 +243,9 @@ static int mvebu_icu_subset_probe(struct platform_device *pdev)
struct irq_domain *irq_domain;
struct mvebu_icu *icu;
- icu = dev_get_drvdata(&pdev->dev);
- if (!icu)
- return -ENODEV;
+ icu = mvebu_icu_dev_get_drvdata(pdev);
+ if (IS_ERR(icu))
+ return PTR_ERR(icu);
pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, pdev->dev.of_node,
DOMAIN_BUS_PLATFORM_MSI);
@@ -236,6 +268,22 @@ static int mvebu_icu_subset_probe(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id mvebu_icu_subset_of_match[] = {
+ {
+ .compatible = "marvell,cp110-icu-nsr",
+ },
+ {},
+};
+
+static struct platform_driver mvebu_icu_subset_driver = {
+ .probe = mvebu_icu_subset_probe,
+ .driver = {
+ .name = "mvebu-icu-subset",
+ .of_match_table = mvebu_icu_subset_of_match,
+ },
+};
+builtin_platform_driver(mvebu_icu_subset_driver);
+
static struct regmap_config mvebu_icu_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -275,6 +323,15 @@ static int mvebu_icu_probe(struct platform_device *pdev)
if (!icu->irq_chip.name)
return -ENOMEM;
+ /*
+ * Legacy bindings: ICU is one node with one MSI parent: force manually
+ * the probe of the NSR interrupts side.
+ * New bindings: ICU node has children, one per interrupt controller
+ * having its own MSI parent: call platform_populate().
+ */
+ if (!of_get_child_count(pdev->dev.of_node))
+ icu->legacy_bindings = true;
+
icu->irq_chip.irq_mask = irq_chip_mask_parent;
icu->irq_chip.irq_unmask = irq_chip_unmask_parent;
icu->irq_chip.irq_eoi = irq_chip_eoi_parent;
@@ -299,7 +356,10 @@ static int mvebu_icu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, icu);
- return mvebu_icu_subset_probe(pdev);
+ if (icu->legacy_bindings)
+ return mvebu_icu_subset_probe(pdev);
+ else
+ return devm_of_platform_populate(&pdev->dev);
}
static const struct of_device_id mvebu_icu_of_match[] = {
--
2.14.1
^ permalink raw reply related
* [PATCH v2 09/16] irqchip/irq-mvebu-sei: add new driver for Marvell SEI
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
This is a cascaded interrupt controller in the AP806 GIC that collapses
SEIs (System Error Interrupt) coming from the AP and the CPs (through
the ICU).
The SEI handles up to 64 interrupts. The first 21 interrupts are wired
and come from the AP. The next 43 interrupts are from the CPs and are
triggered through MSI messages. To handle this complexity, the driver
has to declare to the upper layer: one IRQ domain for the wired
interrupts, one IRQ domain for the MSIs; and acts as a MSI server
('parent') by declaring an MSI domain.
Suggested-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mvebu-sei.c | 422 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 426 insertions(+)
create mode 100644 drivers/irqchip/irq-mvebu-sei.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e9233db16e03..922e2a919cf3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -310,6 +310,9 @@ config MVEBU_ODMI
config MVEBU_PIC
bool
+config MVEBU_SEI
+ bool
+
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
depends on PCI && PCI_MSI
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 15f268f646bf..69d2ccb454ef 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
+obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
diff --git a/drivers/irqchip/irq-mvebu-sei.c b/drivers/irqchip/irq-mvebu-sei.c
new file mode 100644
index 000000000000..d9abd5e10741
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-sei.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) "mvebu-sei: " fmt
+
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/msi.h>
+#include <linux/platform_device.h>
+#include <linux/irqchip.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/* Cause register */
+#define GICP_SECR(idx) (0x0 + (idx * 0x4))
+/* Mask register */
+#define GICP_SEMR(idx) (0x20 + (idx * 0x4))
+#define GICP_SET_SEI_OFFSET 0x30
+
+#define SEI_IRQ_COUNT_PER_REG 32
+#define SEI_IRQ_REG_COUNT 2
+#define SEI_IRQ_COUNT (SEI_IRQ_COUNT_PER_REG * SEI_IRQ_REG_COUNT)
+#define SEI_IRQ_REG_IDX(irq_id) (irq_id / SEI_IRQ_COUNT_PER_REG)
+#define SEI_IRQ_REG_BIT(irq_id) (irq_id % SEI_IRQ_COUNT_PER_REG)
+
+struct mvebu_sei_interrupt_range {
+ u32 first;
+ u32 number;
+};
+
+struct mvebu_sei {
+ struct device *dev;
+ void __iomem *base;
+ struct resource *res;
+ struct irq_domain *ap_domain;
+ struct irq_domain *cp_domain;
+ struct mvebu_sei_interrupt_range ap_interrupts;
+ struct mvebu_sei_interrupt_range cp_interrupts;
+ /* Lock on MSI allocations/releases */
+ spinlock_t cp_msi_lock;
+ DECLARE_BITMAP(cp_msi_bitmap, SEI_IRQ_COUNT);
+};
+
+static int mvebu_sei_domain_to_sei_irq(struct mvebu_sei *sei,
+ struct irq_domain *domain,
+ irq_hw_number_t hwirq)
+{
+ if (domain == sei->ap_domain)
+ return sei->ap_interrupts.first + hwirq;
+ else
+ return sei->cp_interrupts.first + hwirq;
+}
+
+static void mvebu_sei_reset(struct mvebu_sei *sei)
+{
+ u32 reg_idx;
+
+ /* Clear IRQ cause registers */
+ for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++)
+ writel(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
+}
+
+static void mvebu_sei_mask_irq(struct irq_data *d)
+{
+ struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
+ u32 sei_irq = mvebu_sei_domain_to_sei_irq(sei, d->domain, d->hwirq);
+ u32 reg_idx = SEI_IRQ_REG_IDX(sei_irq);
+ u32 reg;
+
+ /* 1 disables the interrupt */
+ reg = readl(sei->base + GICP_SEMR(reg_idx));
+ reg |= BIT(SEI_IRQ_REG_BIT(sei_irq));
+ writel(reg, sei->base + GICP_SEMR(reg_idx));
+}
+
+static void mvebu_sei_unmask_irq(struct irq_data *d)
+{
+ struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
+ u32 sei_irq = mvebu_sei_domain_to_sei_irq(sei, d->domain, d->hwirq);
+ u32 reg_idx = SEI_IRQ_REG_IDX(sei_irq);
+ u32 reg;
+
+ /* 0 enables the interrupt */
+ reg = readl(sei->base + GICP_SEMR(reg_idx));
+ reg &= ~BIT(SEI_IRQ_REG_BIT(sei_irq));
+ writel(reg, sei->base + GICP_SEMR(reg_idx));
+}
+
+static void mvebu_sei_compose_msi_msg(struct irq_data *data,
+ struct msi_msg *msg)
+{
+ struct mvebu_sei *sei = data->chip_data;
+ phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET;
+
+ msg->data = mvebu_sei_domain_to_sei_irq(sei, data->domain, data->hwirq);
+ msg->address_lo = lower_32_bits(set);
+ msg->address_hi = upper_32_bits(set);
+}
+
+static struct irq_chip mvebu_sei_ap_wired_irq_chip = {
+ .name = "AP wired SEI",
+ .irq_mask = mvebu_sei_mask_irq,
+ .irq_unmask = mvebu_sei_unmask_irq,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+};
+
+static struct irq_chip mvebu_sei_cp_msi_irq_chip = {
+ .name = "CP MSI SEI",
+ .irq_mask = mvebu_sei_mask_irq,
+ .irq_unmask = mvebu_sei_unmask_irq,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+ .irq_compose_msi_msg = mvebu_sei_compose_msi_msg,
+};
+
+static int mvebu_sei_irq_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *args)
+{
+ struct mvebu_sei *sei = domain->host_data;
+ struct irq_fwspec *fwspec = args;
+ struct irq_chip *irq_chip;
+ int sei_hwirq, hwirq;
+ int ret;
+
+ /* Software only supports single allocations for now */
+ if (nr_irqs != 1)
+ return -ENOTSUPP;
+
+ if (domain == sei->ap_domain) {
+ irq_chip = &mvebu_sei_ap_wired_irq_chip;
+ hwirq = fwspec->param[0];
+ } else {
+ irq_chip = &mvebu_sei_cp_msi_irq_chip;
+ spin_lock(&sei->cp_msi_lock);
+ hwirq = bitmap_find_free_region(sei->cp_msi_bitmap,
+ SEI_IRQ_COUNT, 0);
+ spin_unlock(&sei->cp_msi_lock);
+ if (hwirq < 0)
+ return -ENOSPC;
+ }
+
+ sei_hwirq = mvebu_sei_domain_to_sei_irq(sei, domain, hwirq);
+
+ fwspec->fwnode = domain->parent->fwnode;
+ fwspec->param_count = 3;
+ fwspec->param[0] = GIC_SPI;
+ fwspec->param[1] = sei_hwirq;
+ fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, fwspec);
+ if (ret)
+ goto release_region;
+
+ ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, irq_chip, sei);
+ if (ret)
+ goto free_irq_parents;
+
+ return 0;
+
+free_irq_parents:
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+release_region:
+ if (domain == sei->cp_domain) {
+ spin_lock(&sei->cp_msi_lock);
+ bitmap_release_region(sei->cp_msi_bitmap, hwirq, 0);
+ spin_unlock(&sei->cp_msi_lock);
+ }
+
+ return ret;
+}
+
+static void mvebu_sei_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct mvebu_sei *sei = domain->host_data;
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ u32 irq_nb = sei->ap_interrupts.number + sei->cp_interrupts.number;
+
+ if (nr_irqs != 1 || d->hwirq >= irq_nb) {
+ dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq);
+ return;
+ }
+
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+
+ spin_lock(&sei->cp_msi_lock);
+ bitmap_release_region(sei->cp_msi_bitmap, d->hwirq, 0);
+ spin_unlock(&sei->cp_msi_lock);
+}
+
+static const struct irq_domain_ops mvebu_sei_ap_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .alloc = mvebu_sei_irq_domain_alloc,
+ .free = mvebu_sei_irq_domain_free,
+};
+
+static const struct irq_domain_ops mvebu_sei_cp_domain_ops = {
+ .alloc = mvebu_sei_irq_domain_alloc,
+ .free = mvebu_sei_irq_domain_free,
+};
+
+static struct irq_chip mvebu_sei_msi_irq_chip = {
+ .name = "SEI",
+ .irq_set_type = irq_chip_set_type_parent,
+};
+
+static struct msi_domain_ops mvebu_sei_msi_ops = {
+};
+
+static struct msi_domain_info mvebu_sei_msi_domain_info = {
+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS,
+ .ops = &mvebu_sei_msi_ops,
+ .chip = &mvebu_sei_msi_irq_chip,
+};
+
+static void mvebu_sei_handle_cascade_irq(struct irq_desc *desc)
+{
+ struct mvebu_sei *sei = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long irqmap, irq_bit;
+ u32 reg_idx, virq, irqn;
+
+ chained_irq_enter(chip, desc);
+
+ /* Read both SEI cause registers (64 bits) */
+ for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) {
+ irqmap = readl_relaxed(sei->base + GICP_SECR(reg_idx));
+
+ /* Call handler for each set bit */
+ for_each_set_bit(irq_bit, &irqmap, SEI_IRQ_COUNT_PER_REG) {
+ /* Cause Register gives the SEI number */
+ irqn = irq_bit + reg_idx * SEI_IRQ_COUNT_PER_REG;
+ /*
+ * Finding Linux mapping (virq) needs the right domain
+ * and the relative hwirq (which start at 0 in both
+ * cases, while irqn is relative to all SEI interrupts).
+ */
+ if (irqn < sei->ap_interrupts.number) {
+ virq = irq_find_mapping(sei->ap_domain, irqn);
+ } else {
+ irqn -= sei->ap_interrupts.number;
+ virq = irq_find_mapping(sei->cp_domain, irqn);
+ }
+
+ /* Call IRQ handler */
+ generic_handle_irq(virq);
+ }
+
+ /* Clear interrupt indication by writing 1 to it */
+ writel(irqmap, sei->base + GICP_SECR(reg_idx));
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int mvebu_sei_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node, *parent, *child;
+ struct irq_domain *parent_domain, *plat_domain;
+ struct mvebu_sei *sei;
+ const __be32 *property;
+ u32 parent_irq, size;
+ int ret;
+
+ sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL);
+ if (!sei)
+ return -ENOMEM;
+
+ sei->dev = &pdev->dev;
+
+ spin_lock_init(&sei->cp_msi_lock);
+
+ sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ sei->base = devm_ioremap_resource(sei->dev, sei->res);
+ if (!sei->base) {
+ dev_err(sei->dev, "Failed to remap SEI resource\n");
+ return -ENODEV;
+ }
+
+ mvebu_sei_reset(sei);
+
+ /*
+ * Reserve the single (top-level) parent SPI IRQ from which all the
+ * interrupts handled by this driver will be signaled.
+ */
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (parent_irq <= 0) {
+ dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n");
+ return -ENODEV;
+ }
+
+ irq_set_chained_handler(parent_irq, mvebu_sei_handle_cascade_irq);
+ irq_set_handler_data(parent_irq, sei);
+
+ /*
+ * SEIs in the range [ 0; 20] are wired and come from the AP.
+ * SEIs in the range [21; 63] are CP SEI and are triggered through MSIs.
+ *
+ * Each SEI 'domain' is represented as a subnode.
+ */
+
+ /* Get a reference to the parent domain to create a hierarchy */
+ parent = of_irq_find_parent(node);
+ if (!parent) {
+ dev_err(sei->dev, "Failed to find parent IRQ node\n");
+ ret = -ENODEV;
+ goto dispose_irq;
+ }
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ dev_err(sei->dev, "Failed to find parent IRQ domain\n");
+ ret = -ENODEV;
+ goto dispose_irq;
+ }
+
+ /* Create the 'wired' hierarchy */
+ child = of_find_node_by_name(node, "sei-wired-controller");
+ if (!child) {
+ dev_err(sei->dev, "Missing 'sei-wired-controller' subnode\n");
+ ret = -ENODEV;
+ goto dispose_irq;
+ }
+
+ property = of_get_property(child, "marvell,sei-ranges", &size);
+ if (!property || size != (2 * sizeof(u32))) {
+ dev_err(sei->dev, "Missing 'marvell,sei-ranges' property\n");
+ of_node_put(child);
+ ret = -ENODEV;
+ goto dispose_irq;
+ }
+
+ sei->ap_interrupts.first = be32_to_cpu(property[0]);
+ sei->ap_interrupts.number = be32_to_cpu(property[1]);
+ sei->ap_domain = irq_domain_create_hierarchy(parent_domain, 0,
+ sei->ap_interrupts.number,
+ of_node_to_fwnode(child),
+ &mvebu_sei_ap_domain_ops,
+ sei);
+ of_node_put(child);
+ if (!sei->ap_domain) {
+ dev_err(sei->dev, "Failed to create AP IRQ domain\n");
+ ret = -ENOMEM;
+ goto dispose_irq;
+ }
+
+ /* Create the 'MSI' hierarchy */
+ child = of_find_node_by_name(node, "sei-msi-controller");
+ if (!child) {
+ dev_err(sei->dev, "Missing 'sei-msi-controller' subnode\n");
+ ret = -ENODEV;
+ goto remove_ap_domain;
+ }
+
+ property = of_get_property(child, "marvell,sei-ranges", &size);
+ if (!property || size != (2 * sizeof(u32))) {
+ dev_err(sei->dev, "Missing 'marvell,sei-ranges' property\n");
+ of_node_put(child);
+ ret = -ENODEV;
+ goto remove_ap_domain;
+ }
+
+ sei->cp_interrupts.first = be32_to_cpu(property[0]);
+ sei->cp_interrupts.number = be32_to_cpu(property[1]);
+ sei->cp_domain = irq_domain_create_hierarchy(parent_domain, 0,
+ sei->cp_interrupts.number,
+ of_node_to_fwnode(child),
+ &mvebu_sei_cp_domain_ops,
+ sei);
+ if (!sei->cp_domain) {
+ pr_err("Failed to create CPs IRQ domain\n");
+ of_node_put(child);
+ ret = -ENOMEM;
+ goto remove_ap_domain;
+ }
+
+ plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(child),
+ &mvebu_sei_msi_domain_info,
+ sei->cp_domain);
+ of_node_put(child);
+ if (!plat_domain) {
+ pr_err("Failed to create CPs MSI domain\n");
+ ret = -ENOMEM;
+ goto remove_cp_domain;
+ }
+
+ platform_set_drvdata(pdev, sei);
+
+ return 0;
+
+remove_cp_domain:
+ irq_domain_remove(sei->cp_domain);
+remove_ap_domain:
+ irq_domain_remove(sei->ap_domain);
+dispose_irq:
+ irq_dispose_mapping(parent_irq);
+
+ return ret;
+}
+
+static const struct of_device_id mvebu_sei_of_match[] = {
+ { .compatible = "marvell,armada-8k-sei", },
+ {},
+};
+
+static struct platform_driver mvebu_sei_driver = {
+ .probe = mvebu_sei_probe,
+ .driver = {
+ .name = "mvebu-sei",
+ .of_match_table = mvebu_sei_of_match,
+ },
+};
+builtin_platform_driver(mvebu_sei_driver);
--
2.14.1
^ permalink raw reply related
* [PATCH v2 10/16] arm64: marvell: enable SEI driver
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Enable the newly introduced Marvell SEI driver for the 64-bit Marvell
EBU platforms.
Suggested-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2b1535cdeb7c..dc3c42938051 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -121,6 +121,7 @@ config ARCH_MVEBU
select MVEBU_ICU
select MVEBU_ODMI
select MVEBU_PIC
+ select MVEBU_SEI
select OF_GPIO
select PINCTRL
select PINCTRL_ARMADA_37XX
--
2.14.1
^ permalink raw reply related
* [PATCH v2 11/16] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI)
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
An SEI driver provides an MSI domain through which it is possible to
raise SEIs.
Handle the NSR probe function in a more generic way to support other
type of interrupts (ie. the SEIs).
For clarity we do not use tree IRQ domains for now but linear ones
instead, allocating the 207 ICU lines for each interrupt group.
Reallocating an ICU slot is prevented by the use of an ICU-wide bitmap.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/irqchip/irq-mvebu-icu.c | 126 ++++++++++++++++++++++++++++++++++------
1 file changed, 108 insertions(+), 18 deletions(-)
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
index 977e47b2716f..6ad6236d6ff1 100644
--- a/drivers/irqchip/irq-mvebu-icu.c
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -28,6 +28,10 @@
#define ICU_SETSPI_NSR_AH 0x14
#define ICU_CLRSPI_NSR_AL 0x18
#define ICU_CLRSPI_NSR_AH 0x1c
+#define ICU_SET_SEI_AL 0x50
+#define ICU_SET_SEI_AH 0x54
+#define ICU_CLR_SEI_AL 0x58
+#define ICU_CLR_SEI_AH 0x5C
#define ICU_INT_CFG(x) (0x100 + 4 * (x))
#define ICU_INT_ENABLE BIT(24)
#define ICU_IS_EDGE BIT(28)
@@ -38,12 +42,28 @@
#define ICU_SATA0_ICU_ID 109
#define ICU_SATA1_ICU_ID 107
+struct mvebu_icu_subset_data {
+ unsigned int icu_group;
+ unsigned int offset_set_ah;
+ unsigned int offset_set_al;
+ unsigned int offset_clr_ah;
+ unsigned int offset_clr_al;
+};
+
struct mvebu_icu {
struct irq_chip irq_chip;
struct regmap *regmap;
struct device *dev;
- atomic_t initialized;
bool legacy_bindings;
+ /* Lock on interrupt allocations/releases */
+ spinlock_t msi_lock;
+ DECLARE_BITMAP(msi_bitmap, ICU_MAX_IRQS);
+};
+
+struct mvebu_icu_msi_data {
+ struct mvebu_icu *icu;
+ atomic_t initialized;
+ const struct mvebu_icu_subset_data *subset_data;
};
struct mvebu_icu_irq_data {
@@ -76,16 +96,25 @@ static struct mvebu_icu *mvebu_icu_dev_get_drvdata(struct platform_device *pdev)
return icu;
}
-static void mvebu_icu_init(struct mvebu_icu *icu, struct msi_msg *msg)
+static void mvebu_icu_init(struct mvebu_icu *icu, struct irq_domain *d,
+ struct msi_msg *msg)
{
- if (atomic_cmpxchg(&icu->initialized, false, true))
+ struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d);
+ const struct mvebu_icu_subset_data *subset = msi_data->subset_data;
+
+ if (atomic_cmpxchg(&msi_data->initialized, false, true))
+ return;
+
+ /* Set 'SET' ICU SPI message address in AP */
+ regmap_write(icu->regmap, subset->offset_set_ah, msg[0].address_hi);
+ regmap_write(icu->regmap, subset->offset_set_al, msg[0].address_lo);
+
+ if (subset->icu_group != ICU_GRP_NSR)
return;
- /* Set Clear/Set ICU SPI message address in AP */
- regmap_write(icu->regmap, ICU_SETSPI_NSR_AH, msg[0].address_hi);
- regmap_write(icu->regmap, ICU_SETSPI_NSR_AL, msg[0].address_lo);
- regmap_write(icu->regmap, ICU_CLRSPI_NSR_AH, msg[1].address_hi);
- regmap_write(icu->regmap, ICU_CLRSPI_NSR_AL, msg[1].address_lo);
+ /* Set 'CLEAR' ICU SPI message address in AP (level-MSI only) */
+ regmap_write(icu->regmap, subset->offset_clr_ah, msg[1].address_hi);
+ regmap_write(icu->regmap, subset->offset_clr_al, msg[1].address_lo);
}
static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
@@ -96,8 +125,8 @@ static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
unsigned int icu_int;
if (msg->address_lo || msg->address_hi) {
- /* One off initialization */
- mvebu_icu_init(icu, msg);
+ /* One off initialization per domain */
+ mvebu_icu_init(icu, d->domain, msg);
/* Configure the ICU with irq number & type */
icu_int = msg->data | ICU_INT_ENABLE;
if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
@@ -131,7 +160,8 @@ static int
mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
unsigned long *hwirq, unsigned int *type)
{
- struct mvebu_icu *icu = platform_msi_get_host_data(d);
+ struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d);
+ struct mvebu_icu *icu = msi_data->icu;
unsigned int param_count = icu->legacy_bindings ? 3 : 2;
/* Check the count of the parameters in dt */
@@ -172,7 +202,9 @@ mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
int err;
unsigned long hwirq;
struct irq_fwspec *fwspec = args;
- struct mvebu_icu *icu = platform_msi_get_host_data(domain);
+ struct mvebu_icu_msi_data *msi_data =
+ platform_msi_get_host_data(domain);
+ struct mvebu_icu *icu = msi_data->icu;
struct mvebu_icu_irq_data *icu_irqd;
icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
@@ -186,16 +218,22 @@ mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
goto free_irqd;
}
+ spin_lock(&icu->msi_lock);
+ err = bitmap_allocate_region(icu->msi_bitmap, hwirq, 0);
+ spin_unlock(&icu->msi_lock);
+ if (err < 0)
+ goto free_irqd;
+
if (icu->legacy_bindings)
icu_irqd->icu_group = fwspec->param[0];
else
- icu_irqd->icu_group = ICU_GRP_NSR;
+ icu_irqd->icu_group = msi_data->subset_data->icu_group;
icu_irqd->icu = icu;
err = platform_msi_domain_alloc(domain, virq, nr_irqs);
if (err) {
dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
- goto free_irqd;
+ goto free_bitmap;
}
/* Make sure there is no interrupt left pending by the firmware */
@@ -214,6 +252,10 @@ mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
free_msi:
platform_msi_domain_free(domain, virq, nr_irqs);
+free_bitmap:
+ spin_lock(&icu->msi_lock);
+ bitmap_release_region(icu->msi_bitmap, hwirq, 0);
+ spin_unlock(&icu->msi_lock);
free_irqd:
kfree(icu_irqd);
return err;
@@ -223,12 +265,19 @@ static void
mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs)
{
+ struct mvebu_icu_msi_data *msi_data =
+ platform_msi_get_host_data(domain);
+ struct mvebu_icu *icu = msi_data->icu;
struct irq_data *d = irq_get_irq_data(virq);
struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
kfree(icu_irqd);
platform_msi_domain_free(domain, virq, nr_irqs);
+
+ spin_lock(&icu->msi_lock);
+ bitmap_release_region(icu->msi_bitmap, d->hwirq, 0);
+ spin_unlock(&icu->msi_lock);
}
static const struct irq_domain_ops mvebu_icu_domain_ops = {
@@ -239,14 +288,29 @@ static const struct irq_domain_ops mvebu_icu_domain_ops = {
static int mvebu_icu_subset_probe(struct platform_device *pdev)
{
+ const struct mvebu_icu_subset_data *subset;
+ struct mvebu_icu_msi_data *msi_data;
struct device_node *msi_parent_dn;
struct irq_domain *irq_domain;
struct mvebu_icu *icu;
+ msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
+ if (!msi_data)
+ return -ENOMEM;
+
icu = mvebu_icu_dev_get_drvdata(pdev);
if (IS_ERR(icu))
return PTR_ERR(icu);
+ subset = of_device_get_match_data(&pdev->dev);
+ if (!subset) {
+ dev_err(&pdev->dev, "Could not retrieve subset data\n");
+ return -EINVAL;
+ }
+
+ msi_data->icu = icu;
+ msi_data->subset_data = subset;
+
pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, pdev->dev.of_node,
DOMAIN_BUS_PLATFORM_MSI);
if (!pdev->dev.msi_domain)
@@ -259,7 +323,7 @@ static int mvebu_icu_subset_probe(struct platform_device *pdev)
irq_domain = platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
mvebu_icu_write_msg,
&mvebu_icu_domain_ops,
- icu);
+ msi_data);
if (!irq_domain) {
dev_err(&pdev->dev, "Failed to create ICU MSI domain\n");
return -ENOMEM;
@@ -268,9 +332,30 @@ static int mvebu_icu_subset_probe(struct platform_device *pdev)
return 0;
}
+static const struct mvebu_icu_subset_data mvebu_icu_nsr_subset_data = {
+ .icu_group = ICU_GRP_NSR,
+ .offset_set_ah = ICU_SETSPI_NSR_AH,
+ .offset_set_al = ICU_SETSPI_NSR_AL,
+ .offset_clr_ah = ICU_CLRSPI_NSR_AH,
+ .offset_clr_al = ICU_CLRSPI_NSR_AL,
+};
+
+static const struct mvebu_icu_subset_data mvebu_icu_sei_subset_data = {
+ .icu_group = ICU_GRP_SEI,
+ .offset_set_ah = ICU_SET_SEI_AH,
+ .offset_set_al = ICU_SET_SEI_AL,
+ .offset_clr_ah = ICU_CLR_SEI_AH,
+ .offset_clr_al = ICU_CLR_SEI_AL,
+};
+
static const struct of_device_id mvebu_icu_subset_of_match[] = {
{
.compatible = "marvell,cp110-icu-nsr",
+ .data = &mvebu_icu_nsr_subset_data,
+ },
+ {
+ .compatible = "marvell,cp110-icu-sei",
+ .data = &mvebu_icu_sei_subset_data,
},
{},
};
@@ -317,6 +402,8 @@ static int mvebu_icu_probe(struct platform_device *pdev)
if (IS_ERR(icu->regmap))
return PTR_ERR(icu->regmap);
+ spin_lock_init(&icu->msi_lock);
+
icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"ICU.%x",
(unsigned int)res->start);
@@ -341,7 +428,7 @@ static int mvebu_icu_probe(struct platform_device *pdev)
#endif
/*
- * Clean all ICU interrupts with type SPI_NSR, required to
+ * Clean all ICU interrupts of type NSR and SEI, required to
* avoid unpredictable SPI assignments done by firmware.
*/
for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
@@ -350,7 +437,8 @@ static int mvebu_icu_probe(struct platform_device *pdev)
regmap_read(icu->regmap, ICU_INT_CFG(i), &icu_int);
icu_grp = icu_int >> ICU_GROUP_SHIFT;
- if (icu_grp == ICU_GRP_NSR)
+ if (icu_grp == ICU_GRP_NSR ||
+ (icu_grp == ICU_GRP_SEI && !icu->legacy_bindings))
regmap_write(icu->regmap, ICU_INT_CFG(i), 0);
}
@@ -363,7 +451,9 @@ static int mvebu_icu_probe(struct platform_device *pdev)
}
static const struct of_device_id mvebu_icu_of_match[] = {
- { .compatible = "marvell,cp110-icu", },
+ {
+ .compatible = "marvell,cp110-icu",
+ },
{},
};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 12/16] dt-bindings/interrupt-controller: update Marvell ICU bindings
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Change the documentation to reflect the new bindings used for Marvell
ICU. This involves describing each interrupt group as a subnode of the
ICU node. Each of them having their own compatible.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/interrupt-controller/marvell,icu.txt | 81 ++++++++++++++++++----
1 file changed, 69 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
index 649b7ec9d9b1..6f7e4355b3d8 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
@@ -5,6 +5,8 @@ The Marvell ICU (Interrupt Consolidation Unit) controller is
responsible for collecting all wired-interrupt sources in the CP and
communicating them to the GIC in the AP, the unit translates interrupt
requests on input wires to MSG memory mapped transactions to the GIC.
+These messages will access a different GIC memory area depending on
+their type (NSR, SR, SEI, REI, etc).
Required properties:
@@ -12,20 +14,19 @@ Required properties:
- reg: Should contain ICU registers location and length.
+Subnodes: Each group of interrupt is declared as a subnode of the ICU,
+with their own compatible.
+
+Required properties for the icu_nsr/icu_sei subnodes:
+
+- compatible: Should be "marvell,cp110-icu-nsr" or "marvell,cp110-icu-sei".
+
- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. The value shall be 3.
+ interrupt source. The value shall be 2.
- The 1st cell is the group type of the ICU interrupt. Possible group
- types are:
+ The 1st cell is the index of the interrupt in the ICU unit.
- ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
- ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
- ICU_GRP_SEI (0x4) : System error interrupt
- ICU_GRP_REI (0x5) : RAM error interrupt
-
- The 2nd cell is the index of the interrupt in the ICU unit.
-
- The 3rd cell is the type of the interrupt. See arm,gic.txt for
+ The 2nd cell is the type of the interrupt. See arm,gic.txt for
details.
- interrupt-controller: Identifies the node as an interrupt
@@ -35,17 +36,73 @@ Required properties:
that allows to trigger interrupts using MSG memory mapped
transactions.
+Note: each 'interrupts' property referring to any 'icu_xxx' node shall
+ have a different number within [0:206].
+
Example:
icu: interrupt-controller at 1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
+
+ CP110_LABEL(icu_nsr): icu-nsr {
+ compatible = "marvell,cp110-icu-nsr";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP110_LABEL(icu_sei): icu-sei {
+ compatible = "marvell,cp110-icu-sei";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&sei>;
+ };
+};
+
+node1 {
+ interrupt-parent = <&icu_nsr>;
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+node2 {
+ interrupt-parent = <&icu_sei>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+/* Would not work with the above nodes */
+node3 {
+ interrupt-parent = <&icu_nsr>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+Note on legacy bindings:
+Before using a subnode for each domain, only NSR were
+supported. Bindings were different in this way:
+
+- #interrupt-cells: The value was 3.
+ The 1st cell was the group type of the ICU interrupt. Possible
+ group types were:
+ ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
+ ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
+ ICU_GRP_SEI (0x4) : System error interrupt
+ ICU_GRP_REI (0x5) : RAM error interrupt
+ The 2nd cell was the index of the interrupt in the ICU unit.
+ The 3rd cell was the type of the interrupt. See arm,gic.txt for
+ details.
+
+Example:
+
+icu: interrupt-controller at 1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
-usb3h0: usb3 at 500000 {
+node1 {
interrupt-parent = <&icu>;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.14.1
^ permalink raw reply related
* [PATCH v2 13/16] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Describe the System Error Interrupt (SEI) controller. It aggregates two
types of interrupts, wired and MSIs from respectively the AP and the
CPs, into a single SPI interrupt.
Suggested-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/interrupt-controller/marvell,sei.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
new file mode 100644
index 000000000000..689981036c30
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
@@ -0,0 +1,50 @@
+Marvell SEI (System Error Interrupt) Controller
+-----------------------------------------------
+
+Marvell SEI (System Error Interrupt) controller is an interrupt
+aggregator. It receives interrupts from several sources and aggregates
+them to a single interrupt line (an SPI) on the parent interrupt
+controller.
+
+This interrupt controller can handle up to 64 SEIs, a set comes from the
+AP and is wired while a second set comes from the CPs by the mean of
+MSIs. Each 'domain' is represented as a subnode.
+
+Required properties:
+
+- compatible: should be "marvell,armada-8k-sei".
+- reg: SEI registers location and length.
+- interrupts: identifies the parent IRQ that will be triggered.
+
+Child node 'sei-wired-controller' required properties:
+
+- marvell,sei-ranges: ranges of wired interrupts.
+- #interrupt-cells: number of cells to define an SEI wired interrupt
+ coming from the AP, should be 1. The cell is the IRQ
+ number.
+- interrupt-controller: identifies the node as an interrupt controller.
+
+Child node 'sei-msi-controller' required properties:
+
+- marvell,sei-ranges: ranges of non-wired interrupts triggered by way of
+ MSIs.
+- msi-controller: identifies the node as an MSI controller.
+
+Example:
+
+ sei: sei at 3f0200 {
+ compatible = "marvell,armada-8k-sei";
+ reg = <0x3f0200 0x40>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+
+ sei_wired_controller: sei-wired-controller at 0 {
+ marvell,sei-ranges = <0 21>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ sei_msi_controller: sei-msi-controller at 21 {
+ marvell,sei-ranges = <21 43>;
+ msi-controller;
+ };
+ };
--
2.14.1
^ permalink raw reply related
* [PATCH v2 14/16] arm64: dts: marvell: add AP806 SEI subnode
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Add the System Error Interrupt node, representing an IRQ chip which is
part of the GIC. The SEI node has two subnodes, one for each interrupt
domain: wired (from the AP) and not-wired (MSIs from the CPs).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 176e38d54872..40204a3b893a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -124,6 +124,25 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
+ sei: sei at 3f0200 {
+ compatible = "marvell,armada-8k-sei";
+ reg = <0x3f0200 0x40>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sei_wired_controller: sei-wired-controller {
+ marvell,sei-ranges = <0 21>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ sei_msi_controller: sei-msi-controller {
+ marvell,sei-ranges = <21 43>;
+ msi-controller;
+ };
+ };
+
xor at 400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
--
2.14.1
^ permalink raw reply related
* [PATCH v2 15/16] arm64: dts: marvell: use new bindings for CP110 interrupts
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter.
Move all DT110 nodes to use these new bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 114 +++++++++++++-------------
1 file changed, 59 insertions(+), 55 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 9fa41c54f69c..5637ff2601c9 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -25,7 +25,7 @@
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&CP110_LABEL(icu)>;
+ interrupt-parent = <&CP110_LABEL(icu_nsr)>;
ranges;
config-space at CP110_BASE {
@@ -46,12 +46,12 @@
dma-coherent;
CP110_LABEL(eth0): eth0 {
- interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+ <43 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <51 IRQ_TYPE_LEVEL_HIGH>,
+ <55 IRQ_TYPE_LEVEL_HIGH>,
+ <129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
@@ -60,12 +60,12 @@
};
CP110_LABEL(eth1): eth1 {
- interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+ <44 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>,
+ <52 IRQ_TYPE_LEVEL_HIGH>,
+ <56 IRQ_TYPE_LEVEL_HIGH>,
+ <128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
@@ -74,12 +74,12 @@
};
CP110_LABEL(eth2): eth2 {
- interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+ <45 IRQ_TYPE_LEVEL_HIGH>,
+ <49 IRQ_TYPE_LEVEL_HIGH>,
+ <53 IRQ_TYPE_LEVEL_HIGH>,
+ <57 IRQ_TYPE_LEVEL_HIGH>,
+ <127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
@@ -147,16 +147,20 @@
CP110_LABEL(icu): interrupt-controller at 1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
- #interrupt-cells = <3>;
- interrupt-controller;
- msi-parent = <&gicp>;
+
+ CP110_LABEL(icu_nsr): icu-nsr {
+ compatible = "marvell,cp110-icu-nsr";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
};
CP110_LABEL(rtc): rtc at 284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(thermal): thermal at 400078 {
@@ -182,10 +186,10 @@
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
- interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+ <85 IRQ_TYPE_LEVEL_HIGH>,
+ <84 IRQ_TYPE_LEVEL_HIGH>,
+ <83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -197,10 +201,10 @@
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
- interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+ <81 IRQ_TYPE_LEVEL_HIGH>,
+ <80 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
@@ -210,7 +214,7 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 22>,
<&CP110_LABEL(clk) 1 16>;
@@ -222,7 +226,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 23>,
<&CP110_LABEL(clk) 1 16>;
@@ -233,7 +237,7 @@
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
status = "disabled";
@@ -286,7 +290,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@@ -298,7 +302,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@@ -309,7 +313,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702000 0x100>;
reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -321,7 +325,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702100 0x100>;
reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -333,7 +337,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702200 0x100>;
reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -345,7 +349,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702300 0x100>;
reg-shift = <2>;
- interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -364,7 +368,7 @@
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 2>,
<&CP110_LABEL(clk) 1 17>;
@@ -376,7 +380,7 @@
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 25>,
<&CP110_LABEL(clk) 1 17>;
@@ -386,7 +390,7 @@
CP110_LABEL(sdhci0): sdhci at 780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
- interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
dma-coherent;
@@ -396,12 +400,12 @@
CP110_LABEL(crypto): crypto at 800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
- <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+ <88 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <90 IRQ_TYPE_LEVEL_HIGH>,
+ <91 IRQ_TYPE_LEVEL_HIGH>,
+ <92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clock-names = "core", "reg";
@@ -430,8 +434,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
@@ -457,8 +461,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
@@ -485,8 +489,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
--
2.14.1
^ permalink raw reply related
* [PATCH v2 16/16] arm64: dts: marvell: add CP110 ICU SEI subnode
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 5637ff2601c9..0038a922e7db 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -154,6 +154,13 @@
interrupt-controller;
msi-parent = <&gicp>;
};
+
+ CP110_LABEL(icu_sei): icu-sei {
+ compatible = "marvell,cp110-icu-sei";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&sei>;
+ };
};
CP110_LABEL(rtc): rtc at 284000 {
--
2.14.1
^ permalink raw reply related
* [PATCH 2/6] arm_pmu: Change API to support 64bit counter values
From: Suzuki K Poulose @ 2018-05-22 9:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201805220546.ySDTMDEX%fengguang.wu@intel.com>
On 22/05/18 00:30, kbuild test robot wrote:
> Hi Suzuki,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on tip/perf/core]
> [also build test ERROR on v4.17-rc6 next-20180517]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Suzuki-K-Poulose/arm64-perf-Support-for-chaining-event-counters/20180521-102117
> config: arm-corgi_defconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
> All errors (new ones prefixed by >>):
>
> arch/arm/kernel/perf_event_xscale.c: In function 'xscale2pmu_init':
>>> arch/arm/kernel/perf_event_xscale.c:741:24: error: assignment from incompatible pointer type [-Werror=incompatible-pointer-types]
> cpu_pmu->read_counter = xscale2pmu_read_counter;
> ^
> arch/arm/kernel/perf_event_xscale.c:742:25: error: assignment from incompatible pointer type [-Werror=incompatible-pointer-types]
> cpu_pmu->write_counter = xscale2pmu_write_counter;
> ^
> cc1: some warnings being treated as errors
Thanks for the report, I have fixed this for the next version.
Suzuki
^ permalink raw reply
* [PATCH 1/2] drm/fourcc: add a 10bits fully packed variant of NV12
From: Randy Li @ 2018-05-22 9:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <303c89b8-e24f-cacb-c305-65d17c58c597@linux.intel.com>
On 05/22/2018 05:26 PM, Maarten Lankhorst wrote:
> Op 20-05-18 om 19:17 schreef Randy Li:
>> This pixel format is a fully packed and 10bits variant of NV12.
>> A luma pixel would take 10bits in memory, without any
>> filled bits between pixels in a stride. The color gamut
>> follows the BT.2020 standard.
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 1 +
>> include/uapi/drm/drm_fourcc.h | 3 +++
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 5ca6395cd4d3..1f43967c4013 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -173,6 +173,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
>> + { .format = DRM_FORMAT_NV12_10LE40, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
> Hm, the cpp value might give problems because it rounds down, not sure how we should handle that? Set to zero?
It is default behavior that using the filed "cpp"? to calculate the
pixel in many drivers. I would suggest use a new filed called bits per
pixel (bpp) instead of the old cpp.
The one used in the Gstreamer is more complex:
https://gstreamer.freedesktop.org/data/doc/gstreamer/head/gst-plugins-base-libs/html/gst-plugins-base-libs-GstVideoAlignment.html#GstVideoFormatInfo
As the struct drm_format_info only a kernel internal data structure, it
doesn't need to update the user-space interface like libdrm.
>> };
>>
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index e04613d30a13..8eabf01e966f 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -140,6 +140,9 @@ extern "C" {
>> #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
>> #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>> +/* A fully packed variant of NV12_10LE32 */
>> +#define DRM_FORMAT_NV12_10LE40 fourcc_code('R', 'K', '2', '0') /* 2x2 subsampled Cr:Cb plane */
>> +
>>
>> /*
>> * 3 plane YCbCr
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH] arm64: dts: renesas: r8a77980: add SMP support
From: Geert Uytterhoeven @ 2018-05-22 9:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522085430.eqhan4njajnp5hkk@verge.net.au>
On Tue, May 22, 2018 at 10:54 AM, Simon Horman <horms@verge.net.au> wrote:
> On Sat, May 19, 2018 at 08:38:13PM +0300, Sergei Shtylyov wrote:
>> On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:
>>
>> >> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
>> >> delivery masks for the ARM GIC and Architectured Timer.
>> >>
>> >> Based on the original (and large) patch by Vladimir Barinov.
>> >>
>> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> >
>> > Thanks for your patch!
>> >
>> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> >> @@ -30,6 +30,36 @@
>> >> enable-method = "psci";
>> >> };
>> >>
>> >> + a53_1: cpu at 1 {
>> >> + device_type = "cpu";
>> >> + compatible = "arm,cortex-a53","arm,armv8";
>> >
>> > Please stop copying spaceless lists ;-)
>>
>> Oops! Simon, do I need to re-post?
>
> No, but Geert, are you otherwise ok with this patch?
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [RFT v2 1/4] perf cs-etm: Generate sample for missed packets
From: Leo Yan @ 2018-05-22 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522083920.GD31075@leoy-ThinkPad-X240s>
On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote:
[...]
Rather than the patch I posted in my previous email, I think below new
patch is more reasonable for me.
In the below change, 'etmq->prev_packet' is only used to store the
previous CS_ETM_RANGE packet, we don't need to save CS_ETM_TRACE_ON
packet into 'etmq->prev_packet'.
On the other hand, cs_etm__flush() can use 'etmq->period_instructions'
to indicate if need to generate instruction sample or not. If it's
non-zero, then generate instruction sample and
'etmq->period_instructions' will be cleared; so next time if there
have more tracing CS_ETM_TRACE_ON packet, it can skip to generate
instruction sample due 'etmq->period_instructions' is zero.
How about you think for this?
Thanks,
Leo Yan
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 822ba91..dd354ad 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -495,6 +495,13 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq)
static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet)
{
/*
+ * The packet is the start tracing packet if the end_addr is zero,
+ * returns 0 for this case.
+ */
+ if (!packet->end_addr)
+ return 0;
+
+ /*
* The packet records the execution range with an exclusive end address
*
* A64 instructions are constant size, so the last executed
@@ -897,13 +904,27 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
etmq->period_instructions = instrs_over;
}
- if (etm->sample_branches &&
- etmq->prev_packet &&
- etmq->prev_packet->sample_type == CS_ETM_RANGE &&
- etmq->prev_packet->last_instr_taken_branch) {
- ret = cs_etm__synth_branch_sample(etmq);
- if (ret)
- return ret;
+ if (etm->sample_branches && etmq->prev_packet) {
+ bool generate_sample = false;
+
+ /* Generate sample for start tracing packet */
+ if (etmq->prev_packet->sample_type == 0)
+ generate_sample = true;
+
+ /* Generate sample for exception packet */
+ if (etmq->prev_packet->exc == true)
+ generate_sample = true;
+
+ /* Generate sample for normal branch packet */
+ if (etmq->prev_packet->sample_type == CS_ETM_RANGE &&
+ etmq->prev_packet->last_instr_taken_branch)
+ generate_sample = true;
+
+ if (generate_sample) {
+ ret = cs_etm__synth_branch_sample(etmq);
+ if (ret)
+ return ret;
+ }
}
if (etm->sample_branches || etm->synth_opts.last_branch) {
@@ -922,11 +943,12 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
static int cs_etm__flush(struct cs_etm_queue *etmq)
{
int err = 0;
- struct cs_etm_packet *tmp;
if (etmq->etm->synth_opts.last_branch &&
etmq->prev_packet &&
- etmq->prev_packet->sample_type == CS_ETM_RANGE) {
+ etmq->prev_packet->sample_type == CS_ETM_RANGE &&
+ etmq->period_instructions) {
+
/*
* Generate a last branch event for the branches left in the
* circular buffer at the end of the trace.
@@ -940,14 +962,6 @@ static int cs_etm__flush(struct cs_etm_queue *etmq)
etmq, addr,
etmq->period_instructions);
etmq->period_instructions = 0;
-
- /*
- * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for
- * the next incoming packet.
- */
- tmp = etmq->packet;
- etmq->packet = etmq->prev_packet;
- etmq->prev_packet = tmp;
}
return err;
--
2.7.4
^ permalink raw reply related
* [PATCH 06/14] ARM: spectre-v2: harden branch predictor on context switches
From: Russell King - ARM Linux @ 2018-05-22 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <61e24c59-9905-8524-92ba-98cdbadb3011@gmail.com>
On Mon, May 21, 2018 at 08:21:58PM -0700, Florian Fainelli wrote:
>
>
> On 05/21/2018 04:44 AM, Russell King wrote:
> > Harden the branch predictor against Spectre v2 attacks on context
> > switches for ARMv7 and later CPUs. We do this by:
> >
> > Cortex A9, A12, A17, A73, A75: invalidating the BTB.
> > Cortex A15, Brahma B15: invalidating the instruction cache.
> >
> > Cortex A57 and Cortex A72 are not addressed in this patch.
> >
> > Cortex R7 and Cortex R8 are also not addressed as we do not enforce
> > memory protection on these cores.
> >
> > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
It does need this additional patch to avoid some build errors - I'm
surprised that my autobuilder found it before the 0-day builder...
diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
index 0c37e6a2830d..526d07ab6b7a 100644
--- a/arch/arm/mm/proc-v7-bugs.c
+++ b/arch/arm/mm/proc-v7-bugs.c
@@ -127,4 +127,8 @@ void cpu_v7_bugs_init(void)
pr_info("CPU: Spectre v2: using %s workaround\n",
spectre_v2_method);
}
+#else
+void cpu_v7_bugs_init(void)
+{
+}
#endif
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply related
* [PATCH v1] dma: imx-sdma: add virt-dma support
From: Sascha Hauer @ 2018-05-22 10:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1521735499-29138-1-git-send-email-yibin.gong@nxp.com>
Hi Robin,
Several comments inside.
Sascha
On Fri, Mar 23, 2018 at 12:18:19AM +0800, Robin Gong wrote:
> The legacy sdma driver has below limitations or drawbacks:
> 1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc
> one page size for one channel regardless of only few BDs needed
> most time. But in few cases, the max PAGE_SIZE maybe not enough.
> 2. One SDMA channel can't stop immediatley once channel disabled which
> means SDMA interrupt may come in after this channel terminated.There
> are some patches for this corner case such as commit "2746e2c389f9",
> but not cover non-cyclic.
>
> The common virt-dma overcomes the above limitations. It can alloc bd
> dynamically and free bd once this tx transfer done. No memory wasted or
> maximum limititation here, only depends on how many memory can be requested
> from kernel. For No.2, such issue can be workaround by checking if there
> is available descript("sdmac->desc") now once the unwanted interrupt
> coming. At last the common virt-dma is easier for sdma driver maintain.
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
> ---
> drivers/dma/Kconfig | 1 +
> drivers/dma/imx-sdma.c | 395 +++++++++++++++++++++++++++++++------------------
> 2 files changed, 253 insertions(+), 143 deletions(-)
>
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 27df3e2..c4ce43c 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -247,6 +247,7 @@ config IMX_SDMA
> tristate "i.MX SDMA support"
> depends on ARCH_MXC
> select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
> help
> Support the i.MX SDMA engine. This engine is integrated into
> Freescale i.MX25/31/35/51/53/6 chips.
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index ccd03c3..df79e73 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -48,6 +48,7 @@
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
>
> #include "dmaengine.h"
> +#include "virt-dma.h"
>
> /* SDMA registers */
> #define SDMA_H_C0PTR 0x000
> @@ -291,10 +292,19 @@ struct sdma_context_data {
> u32 scratch7;
> } __attribute__ ((packed));
>
> -#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
> -
> struct sdma_engine;
>
> +struct sdma_desc {
> + struct virt_dma_desc vd;
> + struct list_head node;
> + unsigned int num_bd;
> + dma_addr_t bd_phys;
> + unsigned int buf_tail;
> + unsigned int buf_ptail;
> + struct sdma_channel *sdmac;
> + struct sdma_buffer_descriptor *bd;
> +};
> +
> /**
> * struct sdma_channel - housekeeping for a SDMA channel
> *
> @@ -310,19 +320,17 @@ struct sdma_engine;
> * @num_bd max NUM_BD. number of descriptors currently handling
> */
> struct sdma_channel {
> + struct virt_dma_chan vc;
> + struct list_head pending;
> struct sdma_engine *sdma;
> + struct sdma_desc *desc;
> unsigned int channel;
> enum dma_transfer_direction direction;
> enum sdma_peripheral_type peripheral_type;
> unsigned int event_id0;
> unsigned int event_id1;
> enum dma_slave_buswidth word_size;
> - unsigned int buf_tail;
> - unsigned int buf_ptail;
> - unsigned int num_bd;
> unsigned int period_len;
> - struct sdma_buffer_descriptor *bd;
> - dma_addr_t bd_phys;
> unsigned int pc_from_device, pc_to_device;
> unsigned int device_to_device;
> unsigned long flags;
> @@ -330,15 +338,12 @@ struct sdma_channel {
> unsigned long event_mask[2];
> unsigned long watermark_level;
> u32 shp_addr, per_addr;
> - struct dma_chan chan;
> - spinlock_t lock;
> - struct dma_async_tx_descriptor desc;
> enum dma_status status;
> unsigned int chn_count;
> unsigned int chn_real_count;
> - struct tasklet_struct tasklet;
> struct imx_dma_data data;
> bool enabled;
Usage of this variable is removed in this patch, but not the variable
itself.
> + u32 bd_size_sum;
This variable is never used for anything.
> };
>
> #define IMX_DMA_SG_LOOP BIT(0)
> @@ -398,6 +403,9 @@ struct sdma_engine {
> u32 spba_start_addr;
> u32 spba_end_addr;
> unsigned int irq;
> + /* channel0 bd */
> + dma_addr_t bd0_phys;
> + struct sdma_buffer_descriptor *bd0;
> };
>
> static struct sdma_driver_data sdma_imx31 = {
> @@ -553,6 +561,8 @@ MODULE_DEVICE_TABLE(of, sdma_dt_ids);
> #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
> #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
>
> +static void sdma_start_desc(struct sdma_channel *sdmac);
> +
> static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
> {
> u32 chnenbl0 = sdma->drvdata->chnenbl0;
> @@ -597,14 +607,7 @@ static int sdma_config_ownership(struct sdma_channel *sdmac,
>
> static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
> {
> - unsigned long flags;
> - struct sdma_channel *sdmac = &sdma->channel[channel];
> -
> writel(BIT(channel), sdma->regs + SDMA_H_START);
> -
> - spin_lock_irqsave(&sdmac->lock, flags);
> - sdmac->enabled = true;
> - spin_unlock_irqrestore(&sdmac->lock, flags);
> }
>
> /*
> @@ -632,7 +635,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
> static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
> u32 address)
> {
> - struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
> + struct sdma_buffer_descriptor *bd0 = sdma->bd0;
This change seems to be an orthogonal change. Please make this a
separate patch.
> void *buf_virt;
> dma_addr_t buf_phys;
> int ret;
> @@ -691,23 +694,16 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
> static void sdma_update_channel_loop(struct sdma_channel *sdmac)
> {
> struct sdma_buffer_descriptor *bd;
> + struct sdma_desc *desc = sdmac->desc;
> int error = 0;
> enum dma_status old_status = sdmac->status;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&sdmac->lock, flags);
> - if (!sdmac->enabled) {
> - spin_unlock_irqrestore(&sdmac->lock, flags);
> - return;
> - }
> - spin_unlock_irqrestore(&sdmac->lock, flags);
>
> /*
> * loop mode. Iterate over descriptors, re-setup them and
> * call callback function.
> */
> - while (1) {
> - bd = &sdmac->bd[sdmac->buf_tail];
> + while (desc) {
'desc' seems to be used as a loop counter here, but this variable is
never assigned another value, so I assume it's just another way to say
"skip the loop if desc is NULL". When 'desc' NULL you won't get into
this function at all though, so this check for desc seems rather pointless.
> + bd = &desc->bd[desc->buf_tail];
>
> if (bd->mode.status & BD_DONE)
> break;
> @@ -726,8 +722,8 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
> sdmac->chn_real_count = bd->mode.count;
> bd->mode.status |= BD_DONE;
> bd->mode.count = sdmac->period_len;
> - sdmac->buf_ptail = sdmac->buf_tail;
> - sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
> + desc->buf_ptail = desc->buf_tail;
> + desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
>
> /*
> * The callback is called from the interrupt context in order
> @@ -735,15 +731,16 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
> * SDMA transaction status by the time the client tasklet is
> * executed.
> */
> -
> - dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
> + spin_unlock(&sdmac->vc.lock);
> + dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
> + spin_lock(&sdmac->vc.lock);
>
> if (error)
> sdmac->status = old_status;
> }
> }
>
> -static void mxc_sdma_handle_channel_normal(unsigned long data)
> +static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
> {
> struct sdma_channel *sdmac = (struct sdma_channel *) data;
> struct sdma_buffer_descriptor *bd;
> @@ -754,8 +751,8 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
> * non loop mode. Iterate over all descriptors, collect
> * errors and call callback function
> */
> - for (i = 0; i < sdmac->num_bd; i++) {
> - bd = &sdmac->bd[i];
> + for (i = 0; i < sdmac->desc->num_bd; i++) {
> + bd = &sdmac->desc->bd[i];
>
> if (bd->mode.status & (BD_DONE | BD_RROR))
> error = -EIO;
> @@ -766,10 +763,6 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
> sdmac->status = DMA_ERROR;
> else
> sdmac->status = DMA_COMPLETE;
> -
> - dma_cookie_complete(&sdmac->desc);
> -
> - dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
> }
>
> static irqreturn_t sdma_int_handler(int irq, void *dev_id)
> @@ -785,13 +778,24 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
> while (stat) {
> int channel = fls(stat) - 1;
> struct sdma_channel *sdmac = &sdma->channel[channel];
> -
> - if (sdmac->flags & IMX_DMA_SG_LOOP)
> - sdma_update_channel_loop(sdmac);
> - else
> - tasklet_schedule(&sdmac->tasklet);
> + struct sdma_desc *desc;
> +
> + spin_lock(&sdmac->vc.lock);
> + desc = sdmac->desc;
> + if (desc) {
> + if (sdmac->flags & IMX_DMA_SG_LOOP) {
> + sdma_update_channel_loop(sdmac);
> + } else {
> + mxc_sdma_handle_channel_normal(sdmac);
> + vchan_cookie_complete(&desc->vd);
> + if (!list_empty(&sdmac->pending))
> + list_del(&desc->node);
What does this list_empty check protect you from? It looks like when the
list really is empty then it's a bug in your internal driver logic.
> + sdma_start_desc(sdmac);
Whitespace damage here.
> + }
> + }
>
> __clear_bit(channel, &stat);
> + spin_unlock(&sdmac->vc.lock);
> }
>
> return IRQ_HANDLED;
> @@ -897,7 +901,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
> int channel = sdmac->channel;
> int load_address;
> struct sdma_context_data *context = sdma->context;
> - struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
> + struct sdma_buffer_descriptor *bd0 = sdma->bd0;
> int ret;
> unsigned long flags;
>
> @@ -946,7 +950,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
>
> static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
> {
> - return container_of(chan, struct sdma_channel, chan);
> + return container_of(chan, struct sdma_channel, vc.chan);
> }
>
> static int sdma_disable_channel(struct dma_chan *chan)
> @@ -954,15 +958,10 @@ static int sdma_disable_channel(struct dma_chan *chan)
> struct sdma_channel *sdmac = to_sdma_chan(chan);
> struct sdma_engine *sdma = sdmac->sdma;
> int channel = sdmac->channel;
> - unsigned long flags;
>
> writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
> sdmac->status = DMA_ERROR;
>
> - spin_lock_irqsave(&sdmac->lock, flags);
> - sdmac->enabled = false;
> - spin_unlock_irqrestore(&sdmac->lock, flags);
> -
> return 0;
> }
>
> @@ -1097,42 +1096,101 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac,
> return 0;
> }
>
> -static int sdma_request_channel(struct sdma_channel *sdmac)
> +static int sdma_alloc_bd(struct sdma_desc *desc)
> {
> - struct sdma_engine *sdma = sdmac->sdma;
> - int channel = sdmac->channel;
> - int ret = -EBUSY;
> + u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
> + int ret = 0;
> + unsigned long flags;
>
> - sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
> + desc->bd = dma_zalloc_coherent(NULL, bd_size, &desc->bd_phys,
> GFP_KERNEL);
> - if (!sdmac->bd) {
> + if (!desc->bd) {
> ret = -ENOMEM;
> goto out;
> }
>
> - sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
> - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
> + spin_lock_irqsave(&desc->sdmac->vc.lock, flags);
> + desc->sdmac->bd_size_sum += bd_size;
> + spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags);
>
> - sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
> - return 0;
> out:
> -
> return ret;
> }
>
> -static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
> +static void sdma_free_bd(struct sdma_desc *desc)
> {
> + u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
> unsigned long flags;
> - struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
> - dma_cookie_t cookie;
>
> - spin_lock_irqsave(&sdmac->lock, flags);
> + if (desc->bd) {
> + dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
> +
> + spin_lock_irqsave(&desc->sdmac->vc.lock, flags);
> + desc->sdmac->bd_size_sum -= bd_size;
> + spin_unlock_irqrestore(&desc->sdmac->vc.lock, flags);
> + }
> +}
> +
> +static int sdma_request_channel0(struct sdma_engine *sdma)
> +{
> + int ret = 0;
> +
> + sdma->bd0 = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
> + GFP_KERNEL);
> + if (!sdma->bd0) {
> + ret = -ENOMEM;
> + goto out;
> + }
>
> - cookie = dma_cookie_assign(tx);
> + sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
> + sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
>
> - spin_unlock_irqrestore(&sdmac->lock, flags);
> + sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
> +out:
>
> - return cookie;
> + return ret;
> +}
> +
> +static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
> +{
> + return container_of(t, struct sdma_desc, vd.tx);
> +}
> +
> +static void sdma_desc_free(struct virt_dma_desc *vd)
> +{
> + struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
> +
> + if (desc) {
Depending on the position of 'vd' in struct sdma_desc 'desc' will always
be non-NULL, even if 'vd' is NULL.
I think this test is unnecessary since this function should never be
called with an invalid pointer. If it is, then the caller really
deserved the resulting crash.
> + sdma_free_bd(desc);
> + kfree(desc);
> + }
> +}
> +
> +static int sdma_terminate_all(struct dma_chan *chan)
> +{
> + struct sdma_channel *sdmac = to_sdma_chan(chan);
> + unsigned long flags;
> + LIST_HEAD(head);
> +
> + spin_lock_irqsave(&sdmac->vc.lock, flags);
> + vchan_get_all_descriptors(&sdmac->vc, &head);
> + while (!list_empty(&sdmac->pending)) {
> + struct sdma_desc *desc = list_first_entry(&sdmac->pending,
> + struct sdma_desc, node);
> +
> + list_del(&desc->node);
> + spin_unlock_irqrestore(&sdmac->vc.lock, flags);
> + sdmac->vc.desc_free(&desc->vd);
> + spin_lock_irqsave(&sdmac->vc.lock, flags);
> + }
list_for_each_entry_safe?
> +
> + if (sdmac->desc)
> + sdmac->desc = NULL;
The test is unnecesary.
> + spin_unlock_irqrestore(&sdmac->vc.lock, flags);
> + vchan_dma_desc_free_list(&sdmac->vc, &head);
> + sdma_disable_channel_with_delay(chan);
> +
> + return 0;
> }
>
> static int sdma_alloc_chan_resources(struct dma_chan *chan)
> @@ -1168,18 +1226,11 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
> if (ret)
> goto disable_clk_ipg;
>
> - ret = sdma_request_channel(sdmac);
> - if (ret)
> - goto disable_clk_ahb;
> -
> ret = sdma_set_channel_priority(sdmac, prio);
> if (ret)
> goto disable_clk_ahb;
>
> - dma_async_tx_descriptor_init(&sdmac->desc, chan);
> - sdmac->desc.tx_submit = sdma_tx_submit;
> - /* txd.flags will be overwritten in prep funcs */
> - sdmac->desc.flags = DMA_CTRL_ACK;
> + sdmac->bd_size_sum = 0;
>
> return 0;
>
> @@ -1195,7 +1246,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
> struct sdma_channel *sdmac = to_sdma_chan(chan);
> struct sdma_engine *sdma = sdmac->sdma;
>
> - sdma_disable_channel(chan);
> + sdma_terminate_all(chan);
>
> if (sdmac->event_id0)
> sdma_event_disable(sdmac, sdmac->event_id0);
> @@ -1207,12 +1258,43 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
>
> sdma_set_channel_priority(sdmac, 0);
>
> - dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
> -
> clk_disable(sdma->clk_ipg);
> clk_disable(sdma->clk_ahb);
> }
>
> +static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
> + enum dma_transfer_direction direction, u32 bds)
> +{
> + struct sdma_desc *desc;
> +
> + desc = kzalloc((sizeof(*desc)), GFP_KERNEL);
> + if (!desc)
> + goto err_out;
> +
> + sdmac->status = DMA_IN_PROGRESS;
> + sdmac->direction = direction;
> + sdmac->flags = 0;
> + sdmac->chn_count = 0;
> + sdmac->chn_real_count = 0;
> +
> + desc->sdmac = sdmac;
> + desc->num_bd = bds;
> + INIT_LIST_HEAD(&desc->node);
> +
> + if (sdma_alloc_bd(desc))
> + goto err_desc_out;
> +
> + if (sdma_load_context(sdmac))
> + goto err_desc_out;
> +
> + return desc;
> +
> +err_desc_out:
> + kfree(desc);
> +err_out:
> + return NULL;
> +}
> +
> static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
> struct dma_chan *chan, struct scatterlist *sgl,
> unsigned int sg_len, enum dma_transfer_direction direction,
> @@ -1223,35 +1305,24 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
> int ret, i, count;
> int channel = sdmac->channel;
> struct scatterlist *sg;
> + struct sdma_desc *desc;
>
> - if (sdmac->status == DMA_IN_PROGRESS)
> + if (!chan)
> return NULL;
> - sdmac->status = DMA_IN_PROGRESS;
> -
> - sdmac->flags = 0;
>
> - sdmac->buf_tail = 0;
> - sdmac->buf_ptail = 0;
> - sdmac->chn_real_count = 0;
> + desc = sdma_transfer_init(sdmac, direction, sg_len);
> + if (!desc)
> + goto err_out;
>
> dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
> sg_len, channel);
>
> - sdmac->direction = direction;
> ret = sdma_load_context(sdmac);
> if (ret)
> goto err_out;
>
> - if (sg_len > NUM_BD) {
> - dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
> - channel, sg_len, NUM_BD);
> - ret = -EINVAL;
> - goto err_out;
> - }
> -
> - sdmac->chn_count = 0;
> for_each_sg(sgl, sg, sg_len, i) {
> - struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
> + struct sdma_buffer_descriptor *bd = &desc->bd[i];
> int param;
>
> bd->buffer_addr = sg->dma_address;
> @@ -1262,7 +1333,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
> dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
> channel, count, 0xffff);
> ret = -EINVAL;
> - goto err_out;
> + goto err_bd_out;
> }
>
> bd->mode.count = count;
> @@ -1307,10 +1378,11 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
> bd->mode.status = param;
> }
>
> - sdmac->num_bd = sg_len;
> - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
> + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
>
> - return &sdmac->desc;
> +err_bd_out:
> + sdma_free_bd(desc);
> + kfree(desc);
> err_out:
> sdmac->status = DMA_ERROR;
> return NULL;
> @@ -1326,39 +1398,32 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
> int num_periods = buf_len / period_len;
> int channel = sdmac->channel;
> int ret, i = 0, buf = 0;
> + struct sdma_desc *desc;
>
> dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
>
> - if (sdmac->status == DMA_IN_PROGRESS)
> - return NULL;
> -
> - sdmac->status = DMA_IN_PROGRESS;
> + /* Now allocate and setup the descriptor. */
> + desc = sdma_transfer_init(sdmac, direction, num_periods);
> + if (!desc)
> + goto err_out;
>
> - sdmac->buf_tail = 0;
> - sdmac->buf_ptail = 0;
> - sdmac->chn_real_count = 0;
> + desc->buf_tail = 0;
> + desc->buf_ptail = 0;
> sdmac->period_len = period_len;
> -
> sdmac->flags |= IMX_DMA_SG_LOOP;
> - sdmac->direction = direction;
> +
> ret = sdma_load_context(sdmac);
> if (ret)
> goto err_out;
>
> - if (num_periods > NUM_BD) {
> - dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
> - channel, num_periods, NUM_BD);
> - goto err_out;
> - }
> -
> if (period_len > 0xffff) {
> dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
> channel, period_len, 0xffff);
> - goto err_out;
> + goto err_bd_out;
> }
>
> while (buf < buf_len) {
> - struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
> + struct sdma_buffer_descriptor *bd = &desc->bd[i];
> int param;
>
> bd->buffer_addr = dma_addr;
> @@ -1366,7 +1431,7 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
> bd->mode.count = period_len;
>
> if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
> - goto err_out;
> + goto err_bd_out;
> if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
> bd->mode.command = 0;
> else
> @@ -1389,10 +1454,10 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
> i++;
> }
>
> - sdmac->num_bd = num_periods;
> - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
> -
> - return &sdmac->desc;
> + return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
> +err_bd_out:
> + sdma_free_bd(desc);
> + kfree(desc);
> err_out:
> sdmac->status = DMA_ERROR;
> return NULL;
> @@ -1432,26 +1497,74 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
> {
> struct sdma_channel *sdmac = to_sdma_chan(chan);
> u32 residue;
> + struct virt_dma_desc *vd;
> + struct sdma_desc *desc;
> + enum dma_status ret;
> + unsigned long flags;
>
> - if (sdmac->flags & IMX_DMA_SG_LOOP)
> - residue = (sdmac->num_bd - sdmac->buf_ptail) *
> + ret = dma_cookie_status(chan, cookie, txstate);
> + if (ret == DMA_COMPLETE && txstate) {
> + residue = sdmac->chn_count - sdmac->chn_real_count;
> + return ret;
> + }
> +
> + spin_lock_irqsave(&sdmac->vc.lock, flags);
> + vd = vchan_find_desc(&sdmac->vc, cookie);
> + desc = to_sdma_desc(&vd->tx);
You should use 'vd' only after you have made sure it is valid (though I
see it causes no harm in this case, but let's be nice to the readers of
this code)
> + if (vd) {
> + if (sdmac->flags & IMX_DMA_SG_LOOP)
> + residue = (desc->num_bd - desc->buf_ptail) *
> sdmac->period_len - sdmac->chn_real_count;
> - else
> + else
> + residue = sdmac->chn_count - sdmac->chn_real_count;
> + } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
> residue = sdmac->chn_count - sdmac->chn_real_count;
> + } else {
> + residue = 0;
> + }
> + ret = sdmac->status;
> + spin_unlock_irqrestore(&sdmac->vc.lock, flags);
>
> dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
> residue);
>
> - return sdmac->status;
> + return ret;
> +}
> +
> +static void sdma_start_desc(struct sdma_channel *sdmac)
> +{
> + struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
> + struct sdma_desc *desc;
> + struct sdma_engine *sdma = sdmac->sdma;
> + int channel = sdmac->channel;
> +
> + if (!vd) {
> + sdmac->desc = NULL;
> + return;
> + }
> + sdmac->desc = desc = to_sdma_desc(&vd->tx);
> + /*
> + * Do not delete the node in desc_issued list in cyclic mode, otherwise
> + * the desc alloced will never be freed in vchan_dma_desc_free_list
> + */
> + if (!(sdmac->flags & IMX_DMA_SG_LOOP)) {
> + list_add_tail(&sdmac->desc->node, &sdmac->pending);
> + list_del(&vd->node);
> + }
> + sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
> + sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
> + sdma_enable_channel(sdma, sdmac->channel);
> }
>
> static void sdma_issue_pending(struct dma_chan *chan)
> {
> struct sdma_channel *sdmac = to_sdma_chan(chan);
> - struct sdma_engine *sdma = sdmac->sdma;
> + unsigned long flags;
>
> - if (sdmac->status == DMA_IN_PROGRESS)
> - sdma_enable_channel(sdma, sdmac->channel);
> + spin_lock_irqsave(&sdmac->vc.lock, flags);
> + if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
> + sdma_start_desc(sdmac);
> + spin_unlock_irqrestore(&sdmac->vc.lock, flags);
> }
>
> #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
> @@ -1657,7 +1770,7 @@ static int sdma_init(struct sdma_engine *sdma)
> for (i = 0; i < MAX_DMA_CHANNELS; i++)
> writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
>
> - ret = sdma_request_channel(&sdma->channel[0]);
> + ret = sdma_request_channel0(sdma);
> if (ret)
> goto err_dma_alloc;
>
> @@ -1819,22 +1932,17 @@ static int sdma_probe(struct platform_device *pdev)
> struct sdma_channel *sdmac = &sdma->channel[i];
>
> sdmac->sdma = sdma;
> - spin_lock_init(&sdmac->lock);
> -
> - sdmac->chan.device = &sdma->dma_device;
> - dma_cookie_init(&sdmac->chan);
> sdmac->channel = i;
> -
> - tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
> - (unsigned long) sdmac);
> + sdmac->status = DMA_IN_PROGRESS;
> + sdmac->vc.desc_free = sdma_desc_free;
> + INIT_LIST_HEAD(&sdmac->pending);
> /*
> * Add the channel to the DMAC list. Do not add channel 0 though
> * because we need it internally in the SDMA driver. This also means
> * that channel 0 in dmaengine counting matches sdma channel 1.
> */
> if (i)
> - list_add_tail(&sdmac->chan.device_node,
> - &sdma->dma_device.channels);
> + vchan_init(&sdmac->vc, &sdma->dma_device);
> }
>
> ret = sdma_init(sdma);
> @@ -1879,7 +1987,7 @@ static int sdma_probe(struct platform_device *pdev)
> sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
> sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
> sdma->dma_device.device_config = sdma_config;
> - sdma->dma_device.device_terminate_all = sdma_disable_channel_with_delay;
> + sdma->dma_device.device_terminate_all = sdma_terminate_all;
> sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
> sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
> sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
> @@ -1939,7 +2047,8 @@ static int sdma_remove(struct platform_device *pdev)
> for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> struct sdma_channel *sdmac = &sdma->channel[i];
>
> - tasklet_kill(&sdmac->tasklet);
> + tasklet_kill(&sdmac->vc.task);
> + sdma_free_chan_resources(&sdmac->vc.chan);
> }
>
> platform_set_drvdata(pdev, NULL);
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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