* [PATCHv4 06/10] arm64: add basic pointer authentication support
From: Adam Wallis @ 2018-05-22 19:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503132031.25705-7-mark.rutland@arm.com>
On 5/3/2018 9:20 AM, Mark Rutland wrote:
> This patch adds basic support for pointer authentication, allowing
> userspace to make use of APIAKey. The kernel maintains an APIAKey value
> for each process (shared by all threads within), which is initialised to
> a random value at exec() time.
>
> To describe that address authentication instructions are available, the
> ID_AA64ISAR0.{APA,API} fields are exposed to userspace. A new hwcap,
> APIA, is added to describe that the kernel manages APIAKey.
>
> Instructions using other keys (APIBKey, APDAKey, APDBKey) are disabled,
> and will behave as NOPs. These may be made use of in future patches.
>
> No support is added for the generic key (APGAKey), though this cannot be
> trapped or made to behave as a NOP. Its presence is not advertised with
> a hwcap.
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
Mark, I was able to verify that a buffer overflow exploit results in a segfault
with these PAC patches. When I compile the same binary without
"-msign-return-address=none", I am able to successfully overflow the stack and
execute malicious code.
Thanks
Adam
Tested-by: Adam Wallis <awallis@codeaurora.org>
--
Adam Wallis
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCHv2 06/12] arm64: add basic pointer authentication support
From: Adam Wallis @ 2018-05-22 19:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171127163806.31435-7-mark.rutland@arm.com>
On 11/27/2017 11:38 AM, Mark Rutland wrote:
> This patch adds basic support for pointer authentication, allowing
> userspace to make use of APIAKey. The kernel maintains an APIAKey value
> for each process (shared by all threads within), which is initialised to
> a random value at exec() time.
>
> To describe that address authentication instructions are available, the
> ID_AA64ISAR0.{APA,API} fields are exposed to userspace. A new hwcap,
> APIA, is added to describe that the kernel manages APIAKey.
>
> Instructions using other keys (APIBKey, APDAKey, APDBKey) are disabled,
> and will behave as NOPs. These may be made use of in future patches.
>
> No support is added for the generic key (APGAKey), though this cannot be
> trapped or made to behave as a NOP. Its presence is not advertised with
> a hwcap.
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm64/include/asm/mmu.h | 5 ++
> arch/arm64/include/asm/mmu_context.h | 25 +++++++++-
> arch/arm64/include/asm/pointer_auth.h | 89 +++++++++++++++++++++++++++++++++++
> arch/arm64/include/uapi/asm/hwcap.h | 1 +
> arch/arm64/kernel/cpufeature.c | 17 ++++++-
> arch/arm64/kernel/cpuinfo.c | 1 +
> 6 files changed, 134 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm64/include/asm/pointer_auth.h
Mark, I was able to verify that a buffer overflow exploit results in a segfault
with these PAC patches. When I compile the same binary without
"-msign-return-address=none", I am able to successfully overflow the stack and
execute malicious code.
Thanks
Adam
Tested-by: Adam Wallis <awallis@codeaurora.org>
--
Adam Wallis
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH] arm64: dts: stingray: move common board components to stingray-board-base
From: Scott Branden @ 2018-05-22 18:55 UTC (permalink / raw)
To: linux-arm-kernel
Move common board components from base bcm958742 dtsi file to new
stingray-board-base dtsi file so they can be shared between many stingray
boards following common design.
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
---
.../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 35 +--------------
.../dts/broadcom/stingray/stingray-board-base.dtsi | 51 ++++++++++++++++++++++
2 files changed, 52 insertions(+), 34 deletions(-)
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
index cacc25e..d74f6df 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -30,20 +30,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "stingray.dtsi"
+#include "stingray-board-base.dtsi"
/ {
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart0;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio0_vddo_ctrl_reg";
@@ -67,23 +56,6 @@
};
};
-&memory { /* Default DRAM banks */
- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
- <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
-};
-
-&mdio_mux_iproc {
- mdio at 10 {
- gphy0: eth-phy at 10 {
- reg = <0x10>;
- };
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
&pwm {
status = "okay";
};
@@ -111,8 +83,6 @@
};
&enet {
- phy-mode = "rgmii-id";
- phy-handle = <&gphy0>;
status = "okay";
};
@@ -133,13 +103,10 @@
&sdio0 {
vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
- non-removable;
- full-pwr-cycle;
status = "okay";
};
&sdio1 {
vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
- full-pwr-cycle;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi
new file mode 100644
index 0000000..82a2471
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
+/*
+ * Copyright(c) 2016-2018 Broadcom
+ */
+
+#include "stingray.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&memory { /* Default DRAM banks */
+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
+ <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
+};
+
+&enet {
+ phy-mode = "rgmii-id";
+ phy-handle = <&gphy0>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&sdio0 {
+ non-removable;
+ full-pwr-cycle;
+};
+
+&sdio1 {
+ full-pwr-cycle;
+};
+
+&mdio_mux_iproc {
+ mdio at 10 {
+ gphy0: eth-phy at 10 {
+ reg = <0x10>;
+ };
+ };
+};
--
2.5.0
^ permalink raw reply related
* [PATCH 5/5] arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527014840-21236-1-git-send-email-ray.jui@broadcom.com>
Enable the SP805 watchdog timer
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecf6137..3fe5eb5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -351,6 +351,7 @@ CONFIG_ROCKCHIP_THERMAL=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
--
2.1.4
^ permalink raw reply related
* [PATCH 4/5] arm64: dt: set initial SR watchdog timeout to 60 seconds
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527014840-21236-1-git-send-email-ray.jui@broadcom.com>
Set initial Stingray watchdog timeout to 60 seconds
By the time when the userspace watchdog daemon is ready and taking
control over, the watchdog timeout will then be reset to what's
configured in the daemon
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 99aaff0..1e1cf49 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -420,6 +420,7 @@
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdogclk", "apb_pclk";
+ timeout-sec = <60>;
};
gpio_hsls: gpio at d0000 {
--
2.1.4
^ permalink raw reply related
* [PATCH 3/5] watchdog: sp805: set WDOG_HW_RUNNING when appropriate
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527014840-21236-1-git-send-email-ray.jui@broadcom.com>
If the watchdog hardware is already enabled during the boot process,
when the Linux watchdog driver loads, it should reset the watchdog and
tell the watchdog framework. As a result, ping can be generated from
the watchdog framework, until the userspace watchdog daemon takes over
control
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
drivers/watchdog/sp805_wdt.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 1484609..408ffbe 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -42,6 +42,7 @@
/* control register masks */
#define INT_ENABLE (1 << 0)
#define RESET_ENABLE (1 << 1)
+ #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
#define WDTINTCLR 0x00C
#define WDTRIS 0x010
#define WDTMIS 0x014
@@ -74,6 +75,18 @@ module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Set to 1 to keep watchdog running after device release");
+/* returns true if wdt is running; otherwise returns false */
+static bool wdt_is_running(struct watchdog_device *wdd)
+{
+ struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
+
+ if ((readl_relaxed(wdt->base + WDTCONTROL) & ENABLE_MASK) ==
+ ENABLE_MASK)
+ return true;
+ else
+ return false;
+}
+
/* This routine finds load value that will reset system in required timout */
static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
{
@@ -239,6 +252,15 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
wdt_setload(&wdt->wdd, wdt->wdd.timeout);
+ /*
+ * If HW is already running, enable/reset the wdt and set the running
+ * bit to tell the wdt subsystem
+ */
+ if (wdt_is_running(&wdt->wdd)) {
+ wdt_enable(&wdt->wdd);
+ set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
+ }
+
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
--
2.1.4
^ permalink raw reply related
* [PATCH 2/5] watchdog: sp805: add 'timeout-sec' DT property support
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527014840-21236-1-git-send-email-ray.jui@broadcom.com>
Add support for optional devicetree property 'timeout-sec'.
'timeout-sec' is used in the driver if specified in devicetree.
Otherwise, fall back to driver default, i.e., 60 seconds
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
drivers/watchdog/sp805_wdt.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 03805bc..1484609 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -230,7 +230,14 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
spin_lock_init(&wdt->lock);
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_set_drvdata(&wdt->wdd, wdt);
- wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
+
+ /*
+ * If 'timeout-sec' devicetree property is specified, use that.
+ * Otherwise, use DEFAULT_TIMEOUT
+ */
+ wdt->wdd.timeout = DEFAULT_TIMEOUT;
+ watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
+ wdt_setload(&wdt->wdd, wdt->wdd.timeout);
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
--
2.1.4
^ permalink raw reply related
* [PATCH 1/5] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527014840-21236-1-git-send-email-ray.jui@broadcom.com>
Update the SP805 binding document to add optional 'timeout-sec'
devicetree property
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
index edc4f0e..f898a86 100644
--- a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
@@ -19,6 +19,8 @@ Required properties:
Optional properties:
- interrupts : Should specify WDT interrupt number.
+- timeout-sec : Should specify default WDT timeout in seconds. If unset, the
+ default timeout is 30 seconds
Examples:
--
2.1.4
^ permalink raw reply related
* [PATCH 0/5] Enhance support for the SP805 WDT
From: Ray Jui @ 2018-05-22 18:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch series enhances the support for the SP805 watchdog timer.
First of all, 'timeout-sec' devicetree property is added. In addition,
support is also added to allow the driver to reset the watchdog if it
has been detected that watchdot has been started in the bootloader. In
this case, the driver will initiate the ping service from the kernel
watchdog subsystem, before a user mode daemon takes over. This series
also enables SP805 in the default ARM64 defconfig
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sp805-wdt-v1
Ray Jui (5):
Documentation: DT: Add optional 'timeout-sec' property for sp805
watchdog: sp805: add 'timeout-sec' DT property support
watchdog: sp805: set WDOG_HW_RUNNING when appropriate
arm64: dt: set initial SR watchdog timeout to 60 seconds
arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
.../devicetree/bindings/watchdog/sp805-wdt.txt | 2 ++
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
arch/arm64/configs/defconfig | 1 +
drivers/watchdog/sp805_wdt.c | 31 +++++++++++++++++++++-
4 files changed, 34 insertions(+), 1 deletion(-)
--
2.1.4
^ permalink raw reply
* [PATCH v7 2/2] drivers: soc: Add LLCC driver
From: rishabhb at codeaurora.org @ 2018-05-22 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHp75VdO7+u-PQ+RBH71sxHHG0WkAyEVxv0BNPaycbcRnrZang@mail.gmail.com>
On 2018-05-18 14:01, Andy Shevchenko wrote:
> On Wed, May 16, 2018 at 8:43 PM, Rishabh Bhatnagar
> <rishabhb@codeaurora.org> wrote:
>> LLCC (Last Level Cache Controller) provides additional cache memory
>> in the system. LLCC is partitioned into multiple slices and each
>> slice gets its own priority, size, ID and other config parameters.
>> LLCC driver programs these parameters for each slice. Clients that
>> are assigned to use LLCC need to get information such size & ID of the
>> slice they get and activate or deactivate the slice as needed. LLCC
>> driver
>> provides API for the clients to perform these operations.
>
>> +static const struct of_device_id sdm845_qcom_llcc_of_match[] = {
>> + { .compatible = "qcom,sdm845-llcc", },
>
>> + { },
>
> Slightly better w/o comma
Changed
>
>> +};
>
>> +static struct platform_driver sdm845_qcom_llcc_driver = {
>> + .driver = {
>> + .name = "sdm845-llcc",
>
>> + .owner = THIS_MODULE,
>
> No need. See below.
>
>> + .of_match_table = sdm845_qcom_llcc_of_match,
>> + },
>> + .probe = sdm845_qcom_llcc_probe,
>> +};
>
>> +
>> +static int __init sdm845_init_qcom_llcc_init(void)
>> +{
>> + return platform_driver_register(&sdm845_qcom_llcc_driver);
>> +}
>> +module_init(sdm845_init_qcom_llcc_init);
>> +
>> +static void __exit sdm845_exit_qcom_llcc_exit(void)
>> +{
>> + platform_driver_unregister(&sdm845_qcom_llcc_driver);
>> +}
>> +module_exit(sdm845_exit_qcom_llcc_exit);
>
> Why not to use module_platform_driver() macro?
Done
>
>> +#define ACTIVATE 0x1
>> +#define DEACTIVATE 0x2
>> +#define ACT_CTRL_OPCODE_ACTIVATE 0x1
>> +#define ACT_CTRL_OPCODE_DEACTIVATE 0x2
>> +#define ACT_CTRL_ACT_TRIG 0x1
>
> Are these bits? Perhaps BIT() ?
>
isn't it just better to use fixed size as u suggest in the next comment?
>> +#define ACT_CTRL_OPCODE_SHIFT 0x1
>> +#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x2
>> +#define ATTR1_FIXED_SIZE_SHIFT 0x3
>> +#define ATTR1_PRIORITY_SHIFT 0x4
>> +#define ATTR1_MAX_CAP_SHIFT 0x10
>
> Better to use fixed size pattern, i.e. 0x01, 0x02, 0x03, 0x04, 0x10.
>
>> +#define ATTR0_RES_WAYS_MASK 0x00000fff
>> +#define ATTR0_BONUS_WAYS_MASK 0x0fff0000
>
> GENMASK()
Done
>
>> +#define LLCC_LB_CNT_MASK 0xf0000000
>
> Ditto.
>
>> +#define MAX_CAP_TO_BYTES(n) (n * 1024)
>
> (n * SZ_1K) ?
Done
>
>> +#define LLCC_TRP_ACT_CTRLn(n) (n * 0x1000)
>
> SZ_4K ?
>
>> +#define LLCC_TRP_STATUSn(n) (4 + n * 0x1000)
>
> Ditto.
>
>> +struct llcc_slice_desc *llcc_slice_getd(u32 uid)
>> +{
>> + const struct llcc_slice_config *cfg;
>> + struct llcc_slice_desc *desc;
>> + u32 sz, count = 0;
>> +
>> + cfg = drv_data->cfg;
>> + sz = drv_data->cfg_size;
>> +
>
>> + while (cfg && count < sz) {
>> + if (cfg->usecase_id == uid)
>> + break;
>> + cfg++;
>> + count++;
>> + }
>> + if (cfg == NULL || count == sz)
>> + return ERR_PTR(-ENODEV);
>
> if (!cfg)
> return ERR_PTR(-ENODEV);
>
> while (cfg->... != uid) {
> cfg++;
> count++;
> }
>
> if (count == sz)
> return ...
>
> Though I would rather put it to for () loop.
>
In each while loop iteration the cfg pointer needs to be checked for
NULL. What if the usecase id never matches the uid passed by client
and we keep iterating. At some point it will crash.
>> +static int llcc_update_act_ctrl(u32 sid,
>> + u32 act_ctrl_reg_val, u32 status)
>> +{
>> + u32 act_ctrl_reg;
>> + u32 status_reg;
>> + u32 slice_status;
>
>> + int ret = 0;
>
> Useless assignment. Check entire patch series for a such.
Checked and removed these.
>
>> + ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
>> + slice_status, !(slice_status & status), 0,
>> LLCC_STATUS_READ_DELAY);
>
> Wrong indentation.
Corrected
>
>> + return ret;
>> +}
>
>> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
>> + DEACTIVATE);
>
> Perhaps one line (~83 characters here is OK) ?
The checkpatch script complains about such lines.
>
>> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
>> + ACTIVATE);
>
> Ditto.
>
>> + attr1_cfg = bcast_off +
>> +
>> LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
>> + attr0_cfg = bcast_off +
>> +
>> LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
>
> Ditto.
>
>> + attr1_val |= llcc_table[i].probe_target_ways <<
>> + ATTR1_PROBE_TARGET_WAYS_SHIFT;
>> + attr1_val |= llcc_table[i].fixed_size <<
>> + ATTR1_FIXED_SIZE_SHIFT;
>> + attr1_val |= llcc_table[i].priority <<
>> ATTR1_PRIORITY_SHIFT;
>
> foo |=
> bar << SHIFT;
>
> would look slightly better.
>
>> +int qcom_llcc_probe(struct platform_device *pdev,
>> + const struct llcc_slice_config *llcc_cfg, u32
>> sz)
>> +{
>
>> + drv_data->offsets = devm_kzalloc(dev, num_banks * sizeof(u32),
>> + GFP_KERNEL);
>> + if (!drv_data->offsets)
>> + return -ENOMEM;
>
> devm_kcalloc() ?
changed
>> +
>> + for (i = 0; i < num_banks; i++)
>> + drv_data->offsets[i] = (i * BANK_OFFSET_STRIDE);
>
> Pointless parens.
Removed
>
>> + drv_data->bitmap = devm_kcalloc(dev,
>> + BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
>> + GFP_KERNEL);
>> + if (!drv_data->bitmap)
>> + return -ENOMEM;
>
> Perhaps at some point someone will add
> bitmap_alloc()
> devm_bitmap_alloc()
>
>> + bitmap_zero(drv_data->bitmap, drv_data->max_slices);
>
> Pointless
Removed
^ permalink raw reply
* [PATCH] arm64: kvm: use -fno-jump-tables with clang
From: Nick Desaulniers @ 2018-05-22 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAAeHK+z2LmMYasYtRTt2U=QF8Pe_i10RA3-SkLzGXXByZqLh1w@mail.gmail.com>
On Fri, May 18, 2018 at 11:13 AM Marc Zyngier <marc.zyngier@arm.com> wrote:
> > - you have checked that with a released version of the compiler, you
On Tue, May 22, 2018 at 10:58 AM Andrey Konovalov <andreyknvl@google.com>
wrote:
> Tested-by: Andrey Konovalov <andreyknvl@google.com>
Hi Andrey,
Thank you very much for this report. Can you confirm as well the version
of Clang that you were using? If it's not a binary release (built from
source), would you be able to re-confirm with a released version?
--
Thanks,
~Nick Desaulniers
^ permalink raw reply
* [PATCH 07/14] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit
From: Tony Lindgren @ 2018-05-22 18:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fKjFJ-000641-5N@rmk-PC.armlinux.org.uk>
* Russell King <rmk+kernel@armlinux.org.uk> [180521 12:09]:
> When the branch predictor hardening is enabled, firmware must have set
> the IBE bit in the auxiliary control register. If this bit has not
> been set, the Spectre workarounds will not be functional.
>
> Add validation that this bit is set, and print a warning at alert level
> if this is not the case.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Yup the alert is working:
Tested-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH 06/14] ARM: spectre-v2: harden branch predictor on context switches
From: Tony Lindgren @ 2018-05-22 18:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fKjFD-00063u-Q5@rmk-PC.armlinux.org.uk>
* Russell King <rmk+kernel@armlinux.org.uk> [180521 12:06]:
> Harden the branch predictor against Spectre v2 attacks on context
> switches for ARMv7 and later CPUs. We do this by:
>
> Cortex A9, A12, A17, A73, A75: invalidating the BTB.
> Cortex A15, Brahma B15: invalidating the instruction cache.
>
> Cortex A57 and Cortex A72 are not addressed in this patch.
>
> Cortex R7 and Cortex R8 are also not addressed as we do not enforce
> memory protection on these cores.
Not seeing regressions so:
Tested-by: Tony Lindgren <tony@atomide.com>
^ permalink raw reply
* [PATCH v2] OMAP: CLK: CLKSRC: Add suspend resume hooks
From: Keerthy @ 2018-05-22 18:22 UTC (permalink / raw)
To: linux-arm-kernel
Add the save and restore for clksrc as part of suspend and resume
so that it saves the counter value and restores. This is needed in
modes like rtc+ddr in self-refresh not doing this stalls the time.
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
Changes in v2:
* Instead of everytime looking up for clksrc hwmod doing it once during init
* Tested on am437x-gp-evm
Probably too late for 4.18!
arch/arm/mach-omap2/timer.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5a70ab6..98ed5ac 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -70,6 +70,9 @@
/* Clockevent hwmod for am335x and am437x suspend */
static struct omap_hwmod *clockevent_gpt_hwmod;
+/* Clockesource hwmod for am437x suspend */
+static struct omap_hwmod *clocksource_gpt_hwmod;
+
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static unsigned long arch_timer_freq;
@@ -478,6 +481,26 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
return ret;
}
+static unsigned int omap2_gptimer_clksrc_load;
+
+static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
+{
+ omap2_gptimer_clksrc_load =
+ __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
+
+ omap_hwmod_idle(clocksource_gpt_hwmod);
+}
+
+static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
+{
+ omap_hwmod_enable(clocksource_gpt_hwmod);
+
+ __omap_dm_timer_load_start(&clksrc,
+ OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
+ omap2_gptimer_clksrc_load,
+ OMAP_TIMER_NONPOSTED);
+}
+
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
const char *fck_source,
const char *property)
@@ -490,6 +513,15 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
res = omap_dm_timer_init_one(&clksrc, fck_source, property,
&clocksource_gpt.name,
OMAP_TIMER_NONPOSTED);
+
+ if (soc_is_am43xx()) {
+ clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
+ clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
+
+ clocksource_gpt_hwmod =
+ omap_hwmod_lookup(clocksource_gpt.name);
+ }
+
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
--
1.9.1
^ permalink raw reply related
* [PATCH v2] ARM: AM43XX: Add functions to save/restore am43xx control registers
From: Keerthy @ 2018-05-22 18:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Tero Kristo <t-kristo@ti.com>
These registers are part of the wkup domain and are lost during RTC only
suspend and also hibernation, so storing/restoring their state is
necessary.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
Changes in v2:
* Introduced cpu_pm notifier instead of direct calls from pm33xx code.
* Tested on am437x-gp-evm
Probably too late for 4.18!
arch/arm/mach-omap2/control.c | 112 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/control.h | 61 +++++++++++++++++++++++
2 files changed, 173 insertions(+)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 180da403..0bbfb20 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -17,6 +17,7 @@
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
+#include <linux/cpu_pm.h>
#include "soc.h"
#include "iomap.h"
@@ -621,6 +622,110 @@ void __init omap3_ctrl_init(void)
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+static unsigned long am43xx_control_reg_offsets[] = {
+ AM33XX_CONTROL_SYSCONFIG_OFFSET,
+ AM33XX_CONTROL_STATUS_OFFSET,
+ AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
+ AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
+ AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
+ AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
+ AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
+ AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
+ AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
+ AM33XX_CONTROL_MOSC_CTRL_OFFSET,
+ AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
+ AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
+ AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
+ AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
+ AM33XX_CONTROL_TPTC_CFG_OFFSET,
+ AM33XX_CONTROL_USB_CTRL0_OFFSET,
+ AM33XX_CONTROL_USB_CTRL1_OFFSET,
+ AM43XX_CONTROL_USB_CTRL2_OFFSET,
+ AM43XX_CONTROL_GMII_SEL_OFFSET,
+ AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
+ AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
+ AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
+ AM33XX_CONTROL_MREQPRIO_0_OFFSET,
+ AM33XX_CONTROL_MREQPRIO_1_OFFSET,
+ AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
+ AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
+ AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
+ AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
+ AM33XX_CONTROL_SMRT_CTRL_OFFSET,
+ AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
+ AM43XX_CONTROL_CQDETECT_STS_OFFSET,
+ AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
+ AM43XX_CONTROL_VTP_CTRL_OFFSET,
+ AM33XX_CONTROL_VREF_CTRL_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
+ AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
+ AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
+ AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
+ AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
+ AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
+ AM33XX_CONTROL_RESET_ISO_OFFSET,
+};
+
+static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)];
+
+/**
+ * am43xx_control_save_context - Save the wakeup domain registers
+ *
+ * Save the wkup domain registers
+ */
+void am43xx_control_save_context(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
+ am33xx_control_vals[i] =
+ omap_ctrl_readl(am43xx_control_reg_offsets[i]);
+}
+
+/**
+ * am43xx_control_restore_context - Restore the wakeup domain registers
+ *
+ * Restore the wkup domain registers
+ */
+void am43xx_control_restore_context(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
+ omap_ctrl_writel(am33xx_control_vals[i],
+ am43xx_control_reg_offsets[i]);
+}
+
+static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_ENTER:
+ if (enable_off_mode)
+ am43xx_control_save_context();
+ break;
+ case CPU_CLUSTER_PM_EXIT:
+ if (enable_off_mode)
+ am43xx_control_restore_context();
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
struct control_init_data {
int index;
void __iomem *mem;
@@ -699,6 +804,7 @@ int __init omap_control_init(void)
const struct omap_prcm_init_data *data;
int ret;
struct regmap *syscon;
+ static struct notifier_block nb;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
data = match->data;
@@ -731,6 +837,12 @@ int __init omap_control_init(void)
}
}
+ /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
+ if (soc_is_am43xx()) {
+ nb.notifier_call = cpu_notifier;
+ cpu_pm_register_notifier(&nb);
+ }
+
return 0;
}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index ec406bc..393b421 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -409,6 +409,67 @@
#define AM33XX_DEV_FEATURE 0x604
#define AM33XX_SGX_MASK BIT(29)
+/* Additional AM33XX/AM43XX CONTROL registers */
+#define AM33XX_CONTROL_SYSCONFIG_OFFSET 0x0010
+#define AM33XX_CONTROL_STATUS_OFFSET 0x0040
+#define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET 0x01e0
+#define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET 0x041c
+#define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET 0x0428
+#define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET 0x042c
+#define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
+#define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET 0x0448
+#define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET 0x044c
+#define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
+#define AM33XX_CONTROL_MOSC_CTRL_OFFSET 0x0468
+#define AM33XX_CONTROL_RCOSC_CTRL_OFFSET 0x046c
+#define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET 0x0470
+#define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET 0x0534
+#define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET 0x0608
+#define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET 0x060c
+#define AM33XX_CONTROL_MMU_CFG_OFFSET 0x0610
+#define AM33XX_CONTROL_TPTC_CFG_OFFSET 0x0614
+#define AM33XX_CONTROL_USB_CTRL0_OFFSET 0x0620
+#define AM33XX_CONTROL_USB_CTRL1_OFFSET 0x0628
+#define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET 0x0648
+#define AM43XX_CONTROL_USB_CTRL2_OFFSET 0x064c
+#define AM43XX_CONTROL_GMII_SEL_OFFSET 0x0650
+#define AM43XX_CONTROL_MPUSS_CTRL_OFFSET 0x0654
+#define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET 0x0658
+#define AM43XX_CONTROL_PWMSS_CTRL_OFFSET 0x0664
+#define AM33XX_CONTROL_MREQPRIO_0_OFFSET 0x0670
+#define AM33XX_CONTROL_MREQPRIO_1_OFFSET 0x0674
+#define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET 0x0690
+#define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET 0x0694
+#define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET 0x0698
+#define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET 0x069c
+#define AM33XX_CONTROL_SMRT_CTRL_OFFSET 0x06a0
+#define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET 0x06a4
+#define AM43XX_CONTROL_CQDETECT_STS_OFFSET 0x0e00
+#define AM43XX_CONTROL_CQDETECT_STS2_OFFSET 0x0e08
+#define AM43XX_CONTROL_VTP_CTRL_OFFSET 0x0e0c
+#define AM33XX_CONTROL_VREF_CTRL_OFFSET 0x0e14
+#define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET 0x0f90
+#define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET 0x0f94
+#define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET 0x0f98
+#define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET 0x0f9c
+#define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET 0x0fa0
+#define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET 0x0fa4
+#define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET 0x0fa8
+#define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET 0x0fac
+#define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET 0x0fb0
+#define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET 0x0fb4
+#define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET 0x0fb8
+#define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET 0x0fbc
+#define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET 0x0fc0
+#define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET 0x0fc4
+#define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET 0x0fc8
+#define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET 0x0fcc
+#define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET 0x0fd0
+#define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET 0x0fd4
+#define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET 0x0fd8
+#define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET 0x0fdc
+#define AM33XX_CONTROL_RESET_ISO_OFFSET 0x1000
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
--
1.9.1
^ permalink raw reply related
* [PATCH v2 3/3] ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
From: Dmitry Torokhov @ 2018-05-22 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180520130528.GC26863@dragon>
On Sun, May 20, 2018 at 09:05:30PM +0800, Shawn Guo wrote:
> On Thu, May 17, 2018 at 11:05:52AM +0200, Daniel Mack wrote:
> > The touchscreen driver no longer configures the device as wakeup source by
> > default. A "wakeup-source" property is needed.
> >
> > To avoid regressions, this patch changes the DTS files for the only two
> > users of this driver that didn't have this property yet.
> >
> > Signed-off-by: Daniel Mack <daniel@zonque.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
>
> Applied this one, thanks.
I think there are few more that need "wakeup-source" added:
arch/arm/boot/dts/am437x-sk-evm.dts
arch/arm/boot/dts/imx6q-var-dt6customboard.dts
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
Thanks.
--
Dmitry
^ permalink raw reply
* [PATCH 08/14] ARM: spectre-v2: harden user aborts in kernel space
From: Florian Fainelli @ 2018-05-22 18:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522181246.GU17671@n2100.armlinux.org.uk>
On 05/22/2018 11:12 AM, Russell King - ARM Linux wrote:
> On Tue, May 22, 2018 at 06:56:03PM +0100, Russell King - ARM Linux wrote:
>> On Tue, May 22, 2018 at 06:15:02PM +0100, Marc Zyngier wrote:
>>> On 21/05/18 12:45, Russell King wrote:
>>>> In order to prevent aliasing attacks on the branch predictor,
>>>> invalidate the BTB or instruction cache on CPUs that are known to be
>>>> affected when taking an abort on a address that is outside of a user
>>>> task limit:
>>>>
>>>> Cortex A8, A9, A12, A17, A73, A75: flush BTB.
>>>> Cortex A15, Brahma B15: invalidate icache.
>>>>
>>>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>>>> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
>>>> ---
>>>> arch/arm/include/asm/cp15.h | 3 +++
>>>> arch/arm/include/asm/system_misc.h | 8 ++++++
>>>> arch/arm/mm/fault.c | 3 +++
>>>> arch/arm/mm/proc-v7-bugs.c | 51 ++++++++++++++++++++++++++++++++++++++
>>>> arch/arm/mm/proc-v7.S | 8 +++---
>>>> 5 files changed, 70 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
>>>> index 4c9fa72b59f5..07e27f212dc7 100644
>>>> --- a/arch/arm/include/asm/cp15.h
>>>> +++ b/arch/arm/include/asm/cp15.h
>>>> @@ -65,6 +65,9 @@
>>>> #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
>>>> #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
>>>>
>>>> +#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
>>>> +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
>>>> +
>>>> extern unsigned long cr_alignment; /* defined in entry-armv.S */
>>>>
>>>> static inline unsigned long get_cr(void)
>>>> diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
>>>> index 78f6db114faf..3cfe010c5734 100644
>>>> --- a/arch/arm/include/asm/system_misc.h
>>>> +++ b/arch/arm/include/asm/system_misc.h
>>>> @@ -15,6 +15,14 @@ void soft_restart(unsigned long);
>>>> extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
>>>> extern void (*arm_pm_idle)(void);
>>>>
>>>> +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
>>>> +extern void (*harden_branch_predictor)(void);
>>>> +#define harden_branch_predictor() \
>>>> + do { if (harden_branch_predictor) harden_branch_predictor(); } while (0)
>>>> +#else
>>>> +#define harden_branch_predictor() do { } while (0)
>>>> +#endif
>>>> +
>>>> #define UDBG_UNDEFINED (1 << 0)
>>>> #define UDBG_SYSCALL (1 << 1)
>>>> #define UDBG_BADABORT (1 << 2)
>>>> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
>>>> index b75eada23d0a..3b1ba003c4f9 100644
>>>> --- a/arch/arm/mm/fault.c
>>>> +++ b/arch/arm/mm/fault.c
>>>> @@ -163,6 +163,9 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr,
>>>> {
>>>> struct siginfo si;
>>>>
>>>> + if (addr > TASK_SIZE)
>>>> + harden_branch_predictor();
>>>> +
>>>> #ifdef CONFIG_DEBUG_USER
>>>> if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) ||
>>>> ((user_debug & UDBG_BUS) && (sig == SIGBUS))) {
>>>> diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
>>>> index a32ce13479d9..65a9b8141f86 100644
>>>> --- a/arch/arm/mm/proc-v7-bugs.c
>>>> +++ b/arch/arm/mm/proc-v7-bugs.c
>>>> @@ -2,6 +2,12 @@
>>>> #include <linux/kernel.h>
>>>> #include <linux/smp.h>
>>>>
>>>> +#include <asm/cp15.h>
>>>> +#include <asm/cputype.h>
>>>> +#include <asm/system_misc.h>
>>>> +
>>>> +void cpu_v7_bugs_init(void);
>>>> +
>>>> static __maybe_unused void cpu_v7_check_auxcr_set(u32 mask, const char *msg)
>>>> {
>>>> u32 aux_cr;
>>>> @@ -21,9 +27,54 @@ static void check_spectre_auxcr(u32 bit)
>>>> void cpu_v7_ca8_ibe(void)
>>>> {
>>>> check_spectre_auxcr(BIT(6));
>>>> + cpu_v7_bugs_init();
>>>> }
>>>>
>>>> void cpu_v7_ca15_ibe(void)
>>>> {
>>>> check_spectre_auxcr(BIT(0));
>>>> + cpu_v7_bugs_init();
>>>> +}
>>>> +
>>>> +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
>>>> +void (*harden_branch_predictor)(void);
>>>> +
>>>> +static void harden_branch_predictor_bpiall(void)
>>>> +{
>>>> + write_sysreg(0, BPIALL);
>>>> +}
>>>> +
>>>> +static void harden_branch_predictor_iciallu(void)
>>>> +{
>>>> + write_sysreg(0, ICIALLU);
>>>> +}
>>>> +
>>>> +void cpu_v7_bugs_init(void)
>>>> +{
>>>> + const char *spectre_v2_method = NULL;
>>>> +
>>>> + if (harden_branch_predictor)
>>>> + return;
>>>
>>> How does it work on a big-little systems where two CPUs have diverging
>>> mitigation methods? Let's say an hypothetical A15/A17 system? Or even a
>>> more common A15/A7 system, where the small core doesn't require the
>>> mitigation?
>>
>> Hmm, I'd forgotten about those, because I don't have them.
>>
>> We don't have the ability to mitigate this on such systems at all at
>> present, it would require a per-CPU cpu_switch_mm() implementation, and
>> the code has no structure to support that at present without considerable
>> rewrite of the CPU glue support.
>>
>> I'm not even sure it could without checking deeper - I think there's some
>> situations where we call this before we're sufficiently setup.
>
> Confirmed. We can't access per_cpu variables via cpu_switch_mm()
> because it is used prior to the per_cpu offset being initialised in
> the CPU. Eg,
>
> secondary_start_kernel
> {
> ...
> cpu_switch_mm(mm->pgd, mm);
> ...
> cpu_init(); /* <== per cpu setup */
> }
>
> However, we can change harden_branch_predictor() to be a per-cpu
> function pointer to solve some of your concern, but it's still
> insufficient.
I hate to play that card, but we have all been waiting for these patches
to land in Linus' tree, so on one hand, waiting for the next merge
window is probably doable, since nothing is there. On the other hand,
does this absolutely needs to be addressed right now?
--
Florian
^ permalink raw reply
* [PATCH 08/14] ARM: spectre-v2: harden user aborts in kernel space
From: Russell King - ARM Linux @ 2018-05-22 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522175603.GS17671@n2100.armlinux.org.uk>
On Tue, May 22, 2018 at 06:56:03PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 22, 2018 at 06:15:02PM +0100, Marc Zyngier wrote:
> > On 21/05/18 12:45, Russell King wrote:
> > > In order to prevent aliasing attacks on the branch predictor,
> > > invalidate the BTB or instruction cache on CPUs that are known to be
> > > affected when taking an abort on a address that is outside of a user
> > > task limit:
> > >
> > > Cortex A8, A9, A12, A17, A73, A75: flush BTB.
> > > Cortex A15, Brahma B15: invalidate icache.
> > >
> > > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> > > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> > > ---
> > > arch/arm/include/asm/cp15.h | 3 +++
> > > arch/arm/include/asm/system_misc.h | 8 ++++++
> > > arch/arm/mm/fault.c | 3 +++
> > > arch/arm/mm/proc-v7-bugs.c | 51 ++++++++++++++++++++++++++++++++++++++
> > > arch/arm/mm/proc-v7.S | 8 +++---
> > > 5 files changed, 70 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> > > index 4c9fa72b59f5..07e27f212dc7 100644
> > > --- a/arch/arm/include/asm/cp15.h
> > > +++ b/arch/arm/include/asm/cp15.h
> > > @@ -65,6 +65,9 @@
> > > #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
> > > #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
> > >
> > > +#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
> > > +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
> > > +
> > > extern unsigned long cr_alignment; /* defined in entry-armv.S */
> > >
> > > static inline unsigned long get_cr(void)
> > > diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
> > > index 78f6db114faf..3cfe010c5734 100644
> > > --- a/arch/arm/include/asm/system_misc.h
> > > +++ b/arch/arm/include/asm/system_misc.h
> > > @@ -15,6 +15,14 @@ void soft_restart(unsigned long);
> > > extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
> > > extern void (*arm_pm_idle)(void);
> > >
> > > +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
> > > +extern void (*harden_branch_predictor)(void);
> > > +#define harden_branch_predictor() \
> > > + do { if (harden_branch_predictor) harden_branch_predictor(); } while (0)
> > > +#else
> > > +#define harden_branch_predictor() do { } while (0)
> > > +#endif
> > > +
> > > #define UDBG_UNDEFINED (1 << 0)
> > > #define UDBG_SYSCALL (1 << 1)
> > > #define UDBG_BADABORT (1 << 2)
> > > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > > index b75eada23d0a..3b1ba003c4f9 100644
> > > --- a/arch/arm/mm/fault.c
> > > +++ b/arch/arm/mm/fault.c
> > > @@ -163,6 +163,9 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr,
> > > {
> > > struct siginfo si;
> > >
> > > + if (addr > TASK_SIZE)
> > > + harden_branch_predictor();
> > > +
> > > #ifdef CONFIG_DEBUG_USER
> > > if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) ||
> > > ((user_debug & UDBG_BUS) && (sig == SIGBUS))) {
> > > diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
> > > index a32ce13479d9..65a9b8141f86 100644
> > > --- a/arch/arm/mm/proc-v7-bugs.c
> > > +++ b/arch/arm/mm/proc-v7-bugs.c
> > > @@ -2,6 +2,12 @@
> > > #include <linux/kernel.h>
> > > #include <linux/smp.h>
> > >
> > > +#include <asm/cp15.h>
> > > +#include <asm/cputype.h>
> > > +#include <asm/system_misc.h>
> > > +
> > > +void cpu_v7_bugs_init(void);
> > > +
> > > static __maybe_unused void cpu_v7_check_auxcr_set(u32 mask, const char *msg)
> > > {
> > > u32 aux_cr;
> > > @@ -21,9 +27,54 @@ static void check_spectre_auxcr(u32 bit)
> > > void cpu_v7_ca8_ibe(void)
> > > {
> > > check_spectre_auxcr(BIT(6));
> > > + cpu_v7_bugs_init();
> > > }
> > >
> > > void cpu_v7_ca15_ibe(void)
> > > {
> > > check_spectre_auxcr(BIT(0));
> > > + cpu_v7_bugs_init();
> > > +}
> > > +
> > > +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
> > > +void (*harden_branch_predictor)(void);
> > > +
> > > +static void harden_branch_predictor_bpiall(void)
> > > +{
> > > + write_sysreg(0, BPIALL);
> > > +}
> > > +
> > > +static void harden_branch_predictor_iciallu(void)
> > > +{
> > > + write_sysreg(0, ICIALLU);
> > > +}
> > > +
> > > +void cpu_v7_bugs_init(void)
> > > +{
> > > + const char *spectre_v2_method = NULL;
> > > +
> > > + if (harden_branch_predictor)
> > > + return;
> >
> > How does it work on a big-little systems where two CPUs have diverging
> > mitigation methods? Let's say an hypothetical A15/A17 system? Or even a
> > more common A15/A7 system, where the small core doesn't require the
> > mitigation?
>
> Hmm, I'd forgotten about those, because I don't have them.
>
> We don't have the ability to mitigate this on such systems at all at
> present, it would require a per-CPU cpu_switch_mm() implementation, and
> the code has no structure to support that at present without considerable
> rewrite of the CPU glue support.
>
> I'm not even sure it could without checking deeper - I think there's some
> situations where we call this before we're sufficiently setup.
Confirmed. We can't access per_cpu variables via cpu_switch_mm()
because it is used prior to the per_cpu offset being initialised in
the CPU. Eg,
secondary_start_kernel
{
...
cpu_switch_mm(mm->pgd, mm);
...
cpu_init(); /* <== per cpu setup */
}
However, we can change harden_branch_predictor() to be a per-cpu
function pointer to solve some of your concern, but it's still
insufficient.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync@8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH] arm64: dts: specify 1.8V EMMC capabilities for bcm958742t
From: Florian Fainelli @ 2018-05-22 18:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527008499-4120-1-git-send-email-scott.branden@broadcom.com>
On Tue, 22 May 2018 10:01:39 -0700, Scott Branden <scott.branden@broadcom.com> wrote:
> Specify 1.8V EMMC capabilities for bcm958742t board to indicate support
> for UHS mode.
>
> Fixes: d4b4aba6be8a ("arm64: dts: Initial DTS files for Broadcom Stingray SOC")
> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
> ---
Applied to devicetree-arm64/fixes, thanks!
--
Florian
^ permalink raw reply
* [PATCH v3 0/4] Introduce STM32MP1 RTC
From: Alexandre Belloni @ 2018-05-22 18:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526558666-24243-1-git-send-email-amelie.delaunay@st.com>
On 17/05/2018 14:04:22+0200, Amelie Delaunay wrote:
> This series introduces STM32MP1 RTC.
> On STM32MP1:
> - two clocks are needed, plck and rtc_ck;
> - to wakeup the system, a wakeup alarm interrupt is needed;
> - some registers or bits have moved, but the operation is the same;
> - the Backup Domain Protection (DBP) is not managed by RTC driver.
>
> ---
> Changes in v3:
> * Move cleanup changes in a separate patch
> * Replace regs and evts by pointers to ensure no copy is made
> * Set all registers offset as u16 instead of u8 and u16
> * Fix Kbuild smatch warning:
> drivers/rtc/rtc-stm32.c:827 stm32_rtc_probe()
> warn: always true condition '(regs.verr != ~0) => (0-u16max != (-1))'
>
> Changes in v2:
> * One compatible per line in bindings file
> * Remove unnecessary comment under rtc_ck as this clock is required for all
> * Remove interrupts-extended and add stm32mp1 rtc alarm wakeup interrupt in
> interrupts property description
>
> Amelie Delaunay (4):
> rtc: stm32: fix misspelling and misalignment issues
> rtc: stm32: rework register management to prepare other version of RTC
> dt-bindings: rtc: update stm32-rtc documentation for stm32mp1 rtc
> rtc: stm32: add stm32mp1 rtc support
>
> .../devicetree/bindings/rtc/st,stm32-rtc.txt | 27 +-
> drivers/rtc/rtc-stm32.c | 273 ++++++++++++++++-----
> 2 files changed, 229 insertions(+), 71 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v2 14/26] dt-bindings: display: Add compatible for A64 HDMI
From: Rob Herring @ 2018-05-22 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-15-jagan@amarulasolutions.com>
On Fri, May 18, 2018 at 03:15:24PM +0530, Jagan Teki wrote:
> HDMI on Allwinner A64 has similar like H3/H5/A83T.
>
> Add compatible a64 and update A83T compatible as fallback.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - Add fallback compatible
>
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2 07/26] dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks
From: Rob Herring @ 2018-05-22 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-8-jagan@amarulasolutions.com>
On Fri, May 18, 2018 at 03:15:17PM +0530, Jagan Teki wrote:
> Allwinner A64 has DE2 pipeline with tcon0 and tcon1 block
> which is similar Allwinner A83T.
>
> This patch adds dt-binding documentation for A64 DE2 tcon1 blocks.
>
> Mixer1 has different configuration for A64 so use separate compatible
> but tcon1 has similar behaviour with A83T so add fallback compatible.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v2:
> - Add fallback compatible for tcon1
> - Add separate compatible for mixer1
>
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] arm64: alternative:flush cache with unpatched code
From: Rohit Khanna @ 2018-05-22 18:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f2db11aa-1a88-0447-6139-435536de2c61@arm.com>
Thanks Suzuki, I have modified the patch and will send it for review.
Thanks
Rohit
________________________________________
From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Sent: Tuesday, May 22, 2018 8:09 AM
To: Rohit Khanna; catalin.marinas at arm.com; robin.murphy at arm.com; mark.rutland at arm.com
Cc: Bo Yan; Alexander Van Brunt; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH] arm64: alternative:flush cache with unpatched code
Rohit,
On 22/05/18 02:27, Rohit Khanna wrote:
> In the current implementation, __apply_alternatives patches
> flush_icache_range and then executes it without invalidating the icache.
> Thus, icache can contain some of the old instructions for
> flush_icache_range. This can cause unpredictable behavior as during
> execution we can get a mix of old and new instructions for
> flush_icache_range.
>
> This patch :
>
> 1. Adds a new function flush_cache_kernel_range for flushing kernel
> memory range. This function is not patched during boot and can be safely
> used to flush cache during code patching.
>
> 2. Modifies __apply_alternatives so that it uses
> flush_cache_kernel_range to flush the cache range after patching code.
>
> Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
> ---
> arch/arm64/include/asm/cacheflush.h | 1 +
> arch/arm64/kernel/alternative.c | 2 +-
> arch/arm64/mm/cache.S | 42 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 44 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> index 0094c6653b06..54692fabdf74 100644
> --- a/arch/arm64/include/asm/cacheflush.h
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -73,6 +73,7 @@
> */
> extern void flush_icache_range(unsigned long start, unsigned long end);
> extern int invalidate_icache_range(unsigned long start, unsigned long end);
> +extern void flush_cache_kernel_range(unsigned long start, unsigned long end);
> extern void __flush_dcache_area(void *addr, size_t len);
> extern void __inval_dcache_area(void *addr, size_t len);
> extern void __clean_dcache_area_poc(void *addr, size_t len);
> diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
> index 5c4bce4ac381..a5408a3c297a 100644
> --- a/arch/arm64/kernel/alternative.c
> +++ b/arch/arm64/kernel/alternative.c
> @@ -155,7 +155,7 @@ static void __apply_alternatives(void *alt_region, bool use_linear_alias)
>
> alt_cb(alt, origptr, updptr, nr_inst);
>
> - flush_icache_range((uintptr_t)origptr,
> + flush_cache_kernel_range((uintptr_t)origptr,
> (uintptr_t)(origptr + nr_inst));
> }
> }
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index 30334d81b021..4dd09352a044 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -81,6 +81,48 @@ ENDPROC(flush_icache_range)
> ENDPROC(__flush_cache_user_range)
>
> /*
> + * flush_cache_kernel_range(start,end)
> + *
> + * Ensure that the I and D caches are coherent within specified kernel
> + * region.
> + * This is typically used when code has been written to a kernel memory
> + * region and will be executed.
> + *
> + * NOTE - This macro cannot have "alternatives" applied to it as its
> + * used to update alternatives
> + *
> + * - start - virtual start address of region
> + * - end - virtual end address of region
> + */
> +ENTRY(flush_cache_kernel_range)
> + dcache_line_size x2, x3
...
> + icache_line_size x2, x3
You must use raw_{d,i}cache_line_size helpers above to avoid
using hot-patched code. The above helpers are patched if you
have mismatched cache line sizes.
Suzuki
^ permalink raw reply
* [PATCH] arm64: alternative:flush cache with unpatched code
From: Rohit Khanna @ 2018-05-22 18:07 UTC (permalink / raw)
To: linux-arm-kernel
In the current implementation, __apply_alternatives patches
flush_icache_range and then executes it without invalidating the icache.
Thus, icache can contain some of the old instructions for
flush_icache_range. This can cause unpredictable behavior as during
execution we can get a mix of old and new instructions for
flush_icache_range.
This patch :
1. Adds a new function flush_cache_kernel_range for flushing kernel
memory range. This function is not patched during boot and can be safely
used to flush cache during code patching.
2. Modifies __apply_alternatives so that it uses
flush_cache_kernel_range to flush the cache range after patching code.
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
---
arch/arm64/include/asm/cacheflush.h | 1 +
arch/arm64/kernel/alternative.c | 2 +-
arch/arm64/mm/cache.S | 42 +++++++++++++++++++++++++++++++++++++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 0094c6653b06..54692fabdf74 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -73,6 +73,7 @@
*/
extern void flush_icache_range(unsigned long start, unsigned long end);
extern int invalidate_icache_range(unsigned long start, unsigned long end);
+extern void flush_cache_kernel_range(unsigned long start, unsigned long end);
extern void __flush_dcache_area(void *addr, size_t len);
extern void __inval_dcache_area(void *addr, size_t len);
extern void __clean_dcache_area_poc(void *addr, size_t len);
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index 5c4bce4ac381..a5408a3c297a 100644
--- a/arch/arm64/kernel/alternative.c
+++ b/arch/arm64/kernel/alternative.c
@@ -155,7 +155,7 @@ static void __apply_alternatives(void *alt_region, bool use_linear_alias)
alt_cb(alt, origptr, updptr, nr_inst);
- flush_icache_range((uintptr_t)origptr,
+ flush_cache_kernel_range((uintptr_t)origptr,
(uintptr_t)(origptr + nr_inst));
}
}
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 30334d81b021..1366f00297c3 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -81,6 +81,48 @@ ENDPROC(flush_icache_range)
ENDPROC(__flush_cache_user_range)
/*
+ * flush_cache_kernel_range(start,end)
+ *
+ * Ensure that the I and D caches are coherent within specified kernel
+ * region.
+ * This is typically used when code has been written to a kernel memory
+ * region and will be executed.
+ *
+ * NOTE - This macro cannot have "alternatives" applied to it as its
+ * used to update alternatives
+ *
+ * - start - virtual start address of region
+ * - end - virtual end address of region
+ */
+ENTRY(flush_cache_kernel_range)
+ raw_dcache_line_size x2, x3
+ sub x3, x2, #1
+ bic x4, x0, x3
+1:
+ dc civac, x4 /* Use civac instead of cvau. This is required
+ * due to ARM errata 826319, 827319, 824069,
+ * 819472 on A53
+ */
+ add x4, x4, x2
+ cmp x4, x1
+ b.lo 1b
+ dsb ish
+
+ raw_icache_line_size x2, x3
+ sub x3, x2, #1
+ bic x4, x0, x3
+1:
+ ic ivau, x4 // invalidate I line PoU
+ add x4, x4, x2
+ cmp x4, x1
+ b.lo 1b
+ dsb ish
+ isb
+ mov x0, #0
+ ret
+ENDPROC(flush_cache_kernel_range)
+
+/*
* invalidate_icache_range(start,end)
*
* Ensure that the I cache is invalid within specified region.
--
2.1.4
^ permalink raw reply related
* [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
From: Peter Rosin @ 2018-05-22 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com>
On 2018-04-11 17:34, Nicolas Ferre wrote:
> On 11/04/2018 at 16:44, Peter Rosin wrote:
>> Hi Nicolas,
>>
>> Boris asked for your input on this (the datasheet difference appears to
>> have no bearing on the issue) elsewhere in the tree of messages. It's
>> now been a week or so and I'm starting to wonder if you missed this
>> altogether or if you are simply out of office or something?
>
> Hi Peter,
>
> I didn't dig into this issue with matrix datasheet reset values and your
> findings below. I'll try to move forward with your detailed explanation
> and with my contacts within the "product" team internally.
Hi again, just checking in to see if there is any progress? If not, maybe
it's time to just take the patch as-is, warts and imperfections included,
and even if we all hate it. But what to do...
Cheers,
Peter
^ permalink raw reply
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