* [PATCH v11 4/8] clk: qcom: Add CPU clock driver for msm8996
From: Ilia Lin @ 2018-05-23 12:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org>
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600MHz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300MHz and 600MHz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Support for this is added in a subsequent patch as well.
ACD stands for Adaptive Clock Distribution and is used to
detect voltage droops.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.h | 6 +
drivers/clk/qcom/clk-cpu-8996.c | 403 +++++++++++++++++++++++++++++++++++++++
4 files changed, 419 insertions(+)
create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e42e1af..866ce1f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -33,6 +33,15 @@ config QCOM_CLK_APCS_MSM8916
Say Y if you want to support CPU frequency scaling on devices
such as msm8916.
+config QCOM_CLK_APCC_MSM8996
+ tristate "MSM8996 CPU Clock Controller"
+ depends on COMMON_CLK_QCOM
+ select QCOM_KRYO_L2_ACCESSORS
+ help
+ Support for the CPU clock controller on msm8996 devices.
+ Say Y if you want to support CPU clock scaling using CPUfreq
+ drivers for dyanmic power management.
+
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7c09ab1..a822fc8 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
+obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index f981b48..9ce2a32 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -50,6 +50,12 @@ struct pll_vco {
u32 val;
};
+#define VCO(a, b, c) { \
+ .val = a,\
+ .min_freq = b,\
+ .max_freq = c,\
+}
+
/**
* struct clk_alpha_pll - phase locked loop (PLL)
* @offset: base address of registers
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
new file mode 100644
index 0000000..d92cad93
--- /dev/null
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+/*
+ * Each of the CPU clusters (Power and Perf) on msm8996 are
+ * clocked via 2 PLLs, a primary and alternate. There are also
+ * 2 Mux'es, a primary and secondary all connected together
+ * as shown below
+ *
+ * +-------+
+ * XO | |
+ * +------------------>0 |
+ * | |
+ * PLL/2 | SMUX +----+
+ * +------->1 | |
+ * | | | |
+ * | +-------+ | +-------+
+ * | +---->0 |
+ * | | |
+ * +---------------+ | +----------->1 | CPU clk
+ * |Primary PLL +----+ PLL_EARLY | | +------>
+ * | +------+-----------+ +------>2 PMUX |
+ * +---------------+ | | | |
+ * | +------+ | +-->3 |
+ * +--^+ ACD +-----+ | +-------+
+ * +---------------+ +------+ |
+ * |Alt PLL | |
+ * | +---------------------------+
+ * +---------------+ PLL_EARLY
+ *
+ * The primary PLL is what drives the CPU clk, except for times
+ * when we are reprogramming the PLL itself (for rate changes) when
+ * we temporarily switch to an alternate PLL. A subsequent patch adds
+ * support to switch between primary and alternate PLL during rate
+ * changes.
+ *
+ * The primary PLL operates on a single VCO range, between 600MHz
+ * and 3GHz. However the CPUs do support OPPs with frequencies
+ * between 300MHz and 600MHz. In order to support running the CPUs
+ * at those frequencies we end up having to lock the PLL at twice
+ * the rate and drive the CPU clk via the PLL/2 output and SMUX.
+ *
+ * So for frequencies above 600MHz we follow the following path
+ * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
+ * and for frequencies between 300MHz and 600MHz we follow
+ * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
+ * Support for this is added in a subsequent patch as well.
+ *
+ * ACD stands for Adaptive Clock Distribution and is used to
+ * detect voltage droops.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-regmap.h"
+
+enum _pmux_input {
+ DIV_2_INDEX = 0,
+ PLL_INDEX,
+ ACD_INDEX,
+ ALT_INDEX,
+ NUM_OF_PMUX_INPUTS
+};
+
+static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL_U] = 0x1c,
+ [PLL_OFF_TEST_CTL] = 0x20,
+ [PLL_OFF_TEST_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+};
+
+static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_USER_CTL_U] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x20,
+ [PLL_OFF_TEST_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+};
+
+/* PLLs */
+
+static const struct alpha_pll_config hfpll_config = {
+ .l = 60,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x006,
+ .pre_div_mask = BIT(12),
+ .post_div_mask = 0x3 << 8,
+ .main_output_mask = BIT(0),
+ .early_output_mask = BIT(3),
+};
+
+static struct clk_alpha_pll perfcl_pll = {
+ .offset = 0x80000,
+ .regs = prim_pll_regs,
+ .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "perfcl_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+};
+
+static struct clk_alpha_pll pwrcl_pll = {
+ .offset = 0x0,
+ .regs = prim_pll_regs,
+ .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pwrcl_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+};
+
+static const struct pll_vco alt_pll_vco_modes[] = {
+ VCO(3, 250000000, 500000000),
+ VCO(2, 500000000, 750000000),
+ VCO(1, 750000000, 1000000000),
+ VCO(0, 1000000000, 2150400000),
+};
+
+static const struct alpha_pll_config altpll_config = {
+ .l = 16,
+ .vco_val = 0x3 << 20,
+ .vco_mask = 0x3 << 20,
+ .config_ctl_val = 0x4001051b,
+ .post_div_mask = 0x3 << 8,
+ .post_div_val = 0x1,
+ .main_output_mask = BIT(0),
+ .early_output_mask = BIT(3),
+};
+
+static struct clk_alpha_pll perfcl_alt_pll = {
+ .offset = 0x80100,
+ .regs = alt_pll_regs,
+ .vco_table = alt_pll_vco_modes,
+ .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
+ .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_alt_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+static struct clk_alpha_pll pwrcl_alt_pll = {
+ .offset = 0x100,
+ .regs = alt_pll_regs,
+ .vco_table = alt_pll_vco_modes,
+ .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
+ .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_alt_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_hwfsm_ops,
+ },
+};
+
+/* Mux'es */
+
+struct clk_cpu_8996_mux {
+ u32 reg;
+ u8 shift;
+ u8 width;
+ struct clk_hw *pll;
+ struct clk_regmap clkr;
+};
+
+static inline
+struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
+{
+ return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
+}
+
+static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
+{
+ u32 val;
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ u32 mask = (u32)GENMASK(cpuclk->width - 1, 0);
+
+ regmap_read(clkr->regmap, cpuclk->reg, &val);
+ val >>= (u32)(cpuclk->shift);
+
+ return (u8)(val & mask);
+}
+
+static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 val;
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1,
+ cpuclk->shift);
+
+ val = (u32)index;
+ val <<= (u32)(cpuclk->shift);
+
+ return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
+}
+
+static int
+clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
+ struct clk_hw *parent = cpuclk->pll;
+
+ req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
+ req->best_parent_hw = parent;
+
+ return 0;
+}
+
+const struct clk_ops clk_cpu_8996_mux_ops = {
+ .set_parent = clk_cpu_8996_mux_set_parent,
+ .get_parent = clk_cpu_8996_mux_get_parent,
+ .determine_rate = clk_cpu_8996_mux_determine_rate,
+};
+
+static struct clk_cpu_8996_mux pwrcl_smux = {
+ .reg = 0x40,
+ .shift = 2,
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_smux",
+ .parent_names = (const char *[]){
+ "xo",
+ "pwrcl_pll_main",
+ },
+ .num_parents = 2,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_cpu_8996_mux perfcl_smux = {
+ .reg = 0x80040,
+ .shift = 2,
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_smux",
+ .parent_names = (const char *[]){
+ "xo",
+ "perfcl_pll_main",
+ },
+ .num_parents = 2,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_cpu_8996_mux pwrcl_pmux = {
+ .reg = 0x40,
+ .shift = 0,
+ .width = 2,
+ .pll = &pwrcl_pll.clkr.hw,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pwrcl_pmux",
+ .parent_names = (const char *[]){
+ "pwrcl_smux",
+ "pwrcl_pll",
+ "pwrcl_pll_acd",
+ "pwrcl_alt_pll",
+ },
+ .num_parents = 4,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static struct clk_cpu_8996_mux perfcl_pmux = {
+ .reg = 0x80040,
+ .shift = 0,
+ .width = 2,
+ .pll = &perfcl_pll.clkr.hw,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "perfcl_pmux",
+ .parent_names = (const char *[]){
+ "perfcl_smux",
+ "perfcl_pll",
+ "perfcl_pll_acd",
+ "perfcl_alt_pll",
+ },
+ .num_parents = 4,
+ .ops = &clk_cpu_8996_mux_ops,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ },
+};
+
+static const struct regmap_config cpu_msm8996_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x80210,
+ .fast_io = true,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+};
+
+struct clk_regmap *clks[] = {
+ &perfcl_pll.clkr,
+ &pwrcl_pll.clkr,
+ &perfcl_alt_pll.clkr,
+ &pwrcl_alt_pll.clkr,
+ &perfcl_smux.clkr,
+ &pwrcl_smux.clkr,
+ &perfcl_pmux.clkr,
+ &pwrcl_pmux.clkr,
+};
+
+static int
+qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap)
+{
+ int i, ret;
+
+ perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
+ "perfcl_pll",
+ CLK_SET_RATE_PARENT, 1, 2);
+
+ pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
+ "pwrcl_pll",
+ CLK_SET_RATE_PARENT, 1, 2);
+
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ ret = devm_clk_register_regmap(dev, clks[i]);
+ if (ret)
+ return ret;
+ }
+
+ clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
+ clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
+ clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
+ clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+
+ return ret;
+}
+
+static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
+{
+ int ret;
+ void __iomem *base;
+ struct resource *res;
+ struct regmap *regmap;
+ struct clk_hw_onecell_data *data;
+ struct device *dev = &pdev->dev;
+
+ data = devm_kzalloc(dev, sizeof(*data) + 2 * sizeof(struct clk_hw *),
+ GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
+ if (ret)
+ return ret;
+
+ data->hws[0] = &pwrcl_pmux.clkr.hw;
+ data->hws[1] = &perfcl_pmux.clkr.hw;
+ data->num = 2;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
+}
+
+static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
+ { .compatible = "qcom,msm8996-apcc" },
+ {}
+};
+
+static struct platform_driver qcom_cpu_clk_msm8996_driver = {
+ .probe = qcom_cpu_clk_msm8996_driver_probe,
+ .driver = {
+ .name = "qcom-msm8996-apcc",
+ .of_match_table = qcom_cpu_clk_msm8996_match_table,
+ },
+};
+module_platform_driver(qcom_cpu_clk_msm8996_driver);
+
+MODULE_ALIAS("platform:msm8996-apcc");
+MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH v11 5/8] dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
From: Ilia Lin @ 2018-05-23 12:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org>
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/clock/qcom,kryocc.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,kryocc.txt b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
new file mode 100644
index 0000000..8458783
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt
@@ -0,0 +1,17 @@
+Qualcomm CPUSS clock controller for Kryo CPUs
+----------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ "qcom,msm8996-apcc"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+
+Example:
+ kryocc: clock-controller at 6400000 {
+ compatible = "qcom,msm8996-apcc";
+ reg = <0x6400000 0x90000>;
+ #clock-cells = <1>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v11 6/8] clk: qcom: cpu-8996: Add support to switch to alternate PLL
From: Ilia Lin @ 2018-05-23 12:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org>
From: Rajendra Nayak <rnayak@codeaurora.org>
Each of the CPU clusters on msm8996 are powered via a primary
PLL and a secondary PLL. The primary PLL is what drives the
CPU clk, except for times when we are reprogramming the PLL
itself, when we temporarily switch to an alternate PLL.
Use clock rate change notifiers to support this.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index d92cad93..620fdc2 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -52,6 +52,7 @@
* detect voltage droops.
*/
+#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -178,10 +179,14 @@ struct clk_cpu_8996_mux {
u32 reg;
u8 shift;
u8 width;
+ struct notifier_block nb;
struct clk_hw *pll;
struct clk_regmap clkr;
};
+#define to_clk_cpu_8996_mux_nb(_nb) \
+ container_of(_nb, struct clk_cpu_8996_mux, nb)
+
static inline
struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
{
@@ -227,6 +232,26 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
return 0;
}
+int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
+ void *data)
+{
+ int ret;
+ struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
+
+ switch (event) {
+ case PRE_RATE_CHANGE:
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
+ break;
+ case POST_RATE_CHANGE:
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return notifier_from_errno(ret);
+};
const struct clk_ops clk_cpu_8996_mux_ops = {
.set_parent = clk_cpu_8996_mux_set_parent,
.get_parent = clk_cpu_8996_mux_get_parent,
@@ -270,6 +295,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
+ .nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
.parent_names = (const char *[]){
@@ -289,6 +315,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
+ .nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
.parent_names = (const char *[]){
@@ -347,6 +374,12 @@ struct clk_regmap *clks[] = {
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+ ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
+ if (ret)
+ return ret;
+
+ ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
+
return ret;
}
--
1.9.1
^ permalink raw reply related
* [PATCH v11 7/8] clk: qcom: cpu-8996: Add support to switch below 600Mhz
From: Ilia Lin @ 2018-05-23 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org>
The CPU clock controller's primary PLL operates on a single VCO range,
between 600MHz and 3GHz. However the CPUs do support OPPs with
frequencies between 300MHz and 600MHz. In order to support running the
CPUs at those frequencies we end up having to lock the PLL at twice the
rate and drive the CPU clk via the PLL/2 output and SMUX.
So for frequencies above 600MHz we follow the following path
Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300MHz and 600MHz we follow
Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 620fdc2..ff5c0a5 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -68,6 +68,8 @@ enum _pmux_input {
NUM_OF_PMUX_INPUTS
};
+#define DIV_2_THRESHOLD 600000000
+
static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
@@ -95,10 +97,11 @@ enum _pmux_input {
static const struct alpha_pll_config hfpll_config = {
.l = 60,
- .config_ctl_val = 0x200d4828,
+ .config_ctl_val = 0x200d4aa8,
.config_ctl_hi_val = 0x006,
.pre_div_mask = BIT(12),
.post_div_mask = 0x3 << 8,
+ .post_div_val = 0x1 << 8,
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
};
@@ -140,7 +143,7 @@ enum _pmux_input {
.vco_mask = 0x3 << 20,
.config_ctl_val = 0x4001051b,
.post_div_mask = 0x3 << 8,
- .post_div_val = 0x1,
+ .post_div_val = 0x1 << 8,
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
};
@@ -181,6 +184,7 @@ struct clk_cpu_8996_mux {
u8 width;
struct notifier_block nb;
struct clk_hw *pll;
+ struct clk_hw *pll_div_2;
struct clk_regmap clkr;
};
@@ -226,6 +230,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
struct clk_hw *parent = cpuclk->pll;
+ if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
+ if (req->rate < (DIV_2_THRESHOLD / 2))
+ return -EINVAL;
+
+ parent = cpuclk->pll_div_2;
+ }
+
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
req->best_parent_hw = parent;
@@ -237,13 +248,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
{
int ret;
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
+ struct clk_notifier_data *cnd = data;
switch (event) {
case PRE_RATE_CHANGE:
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
break;
case POST_RATE_CHANGE:
- ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
+ if (cnd->new_rate < DIV_2_THRESHOLD)
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
+ DIV_2_INDEX);
+ else
+ ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
+ PLL_INDEX);
break;
default:
ret = 0;
@@ -295,6 +312,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
+ .pll_div_2 = &pwrcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_pmux",
@@ -315,6 +333,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
+ .pll_div_2 = &perfcl_smux.clkr.hw,
.nb.notifier_call = cpu_clk_notifier_cb,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_pmux",
--
1.9.1
^ permalink raw reply related
* [PATCH v11 8/8] clk: qcom: Add ACD path to CPU clock driver for msm8996
From: Ilia Lin @ 2018-05-23 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org>
The PMUX for each duplex allows for selection of ACD clock source.
The DVM (Dynamic Variation Monitor) will flag an error
when a voltage droop event is detected. This flagged error
enables ACD to provide a div-by-2 clock, sourced from the primary PLL.
The duplex will be provided the divided clock
until a pre-programmed delay has expired.
This change configures ACD during the probe and switches
the PMUXes to the ACD clock source.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
---
drivers/clk/qcom/clk-cpu-8996.c | 75 +++++++++++++++++++++++++++++++++++------
1 file changed, 65 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index ff5c0a5..0a908d8 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -53,9 +53,11 @@
*/
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <soc/qcom/kryo-l2-accessors.h>
#include "clk-alpha-pll.h"
#include "clk-regmap.h"
@@ -69,6 +71,11 @@ enum _pmux_input {
};
#define DIV_2_THRESHOLD 600000000
+#define PWRCL_REG_OFFSET 0x0
+#define PERFCL_REG_OFFSET 0x80000
+#define MUX_OFFSET 0x40
+#define ALT_PLL_OFFSET 0x100
+#define SSSCTL_OFFSET 0x160
static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_L_VAL] = 0x04,
@@ -107,7 +114,7 @@ enum _pmux_input {
};
static struct clk_alpha_pll perfcl_pll = {
- .offset = 0x80000,
+ .offset = PERFCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
@@ -119,7 +126,7 @@ enum _pmux_input {
};
static struct clk_alpha_pll pwrcl_pll = {
- .offset = 0x0,
+ .offset = PWRCL_REG_OFFSET,
.regs = prim_pll_regs,
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
.clkr.hw.init = &(struct clk_init_data){
@@ -149,7 +156,7 @@ enum _pmux_input {
};
static struct clk_alpha_pll perfcl_alt_pll = {
- .offset = 0x80100,
+ .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
@@ -163,7 +170,7 @@ enum _pmux_input {
};
static struct clk_alpha_pll pwrcl_alt_pll = {
- .offset = 0x100,
+ .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
.regs = alt_pll_regs,
.vco_table = alt_pll_vco_modes,
.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
@@ -176,6 +183,9 @@ enum _pmux_input {
},
};
+void __iomem *base;
+static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base);
+
/* Mux'es */
struct clk_cpu_8996_mux {
@@ -253,6 +263,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
switch (event) {
case PRE_RATE_CHANGE:
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
+ qcom_cpu_clk_msm8996_acd_init(base);
break;
case POST_RATE_CHANGE:
if (cnd->new_rate < DIV_2_THRESHOLD)
@@ -260,7 +271,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
DIV_2_INDEX);
else
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
- PLL_INDEX);
+ ACD_INDEX);
break;
default:
ret = 0;
@@ -276,7 +287,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux pwrcl_smux = {
- .reg = 0x40,
+ .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
@@ -292,7 +303,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux perfcl_smux = {
- .reg = 0x80040,
+ .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
@@ -308,7 +319,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux pwrcl_pmux = {
- .reg = 0x40,
+ .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &pwrcl_pll.clkr.hw,
@@ -329,7 +340,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
};
static struct clk_cpu_8996_mux perfcl_pmux = {
- .reg = 0x80040,
+ .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 0,
.width = 2,
.pll = &perfcl_pll.clkr.hw,
@@ -393,6 +404,10 @@ struct clk_regmap *clks[] = {
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
+ /* Enable alt PLLs */
+ clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
+ clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
+
ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
if (ret)
return ret;
@@ -402,10 +417,48 @@ struct clk_regmap *clks[] = {
return ret;
}
+#define CPU_AFINITY_MASK 0xFFF
+#define PWRCL_CPU_REG_MASK 0x3
+#define PERFCL_CPU_REG_MASK 0x103
+
+#define L2ACDCR_REG 0x580ULL
+#define L2ACDTD_REG 0x581ULL
+#define L2ACDDVMRC_REG 0x584ULL
+#define L2ACDSSCR_REG 0x589ULL
+
+static DEFINE_SPINLOCK(acd_lock);
+
+static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base)
+{
+ u64 hwid;
+ unsigned long flags;
+
+ spin_lock_irqsave(&acd_lock, flags);
+
+ hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
+
+ kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006A11);
+ kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000E0F0F);
+ kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
+
+ if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
+ writel(0xF, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET);
+ wmb();
+ kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD);
+ }
+
+ if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) {
+ kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD);
+ writel(0xF, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET);
+ wmb();
+ }
+
+ spin_unlock_irqrestore(&acd_lock, flags);
+}
+
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
{
int ret;
- void __iomem *base;
struct resource *res;
struct regmap *regmap;
struct clk_hw_onecell_data *data;
@@ -429,6 +482,8 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
if (ret)
return ret;
+ qcom_cpu_clk_msm8996_acd_init(base);
+
data->hws[0] = &pwrcl_pmux.clkr.hw;
data->hws[1] = &perfcl_pmux.clkr.hw;
data->num = 2;
--
1.9.1
^ permalink raw reply related
* [rjarzmik:test/daniel 23/34] sound/arm/pxa2xx-ac97.c:27:10: fatal error: mach/regs-ac97.h: No such file or directory
From: Li, Philip @ 2018-05-23 13:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8545409a-475f-1821-fcef-60b2f85101b6@zonque.org>
> On Wednesday, May 23, 2018 10:46 AM, kbuild test robot wrote:
> > tree: https://github.com/rjarzmik/linux test/daniel
> > head: f495e2dbc482d8f01a1ee20e86284ee9c0c8fa98
> > commit: 4cd654b13b9bcc0f206d414497b798ed42df573a [23/34] HACK: select
> SND_PXA_SOC_SSP for SND_SIMPLE_CARD
>
> This patch is just a local hack in one of my scratch-pad branches and is
> not meant for upstream inclusion. Could you remove the branch or make
> sure it isn't picked up by test robots?
thanks for info, we will exclude it from testing.
>
>
> Thanks,
> Daniel
>
>
> > config: x86_64-randconfig-s3-05231547 (attached as .config)
> > compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
> > reproduce:
> > git checkout 4cd654b13b9bcc0f206d414497b798ed42df573a
> > # save the attached .config to linux build tree
> > make ARCH=x86_64
> >
> > All errors (new ones prefixed by >>):
> >
> >>> sound/arm/pxa2xx-ac97.c:27:10: fatal error: mach/regs-ac97.h: No such file
> or directory
> > #include <mach/regs-ac97.h>
> > ^~~~~~~~~~~~~~~~~~
> > compilation terminated.
> > --
> >>> sound/soc/pxa/pxa2xx-i2s.c:28:10: fatal error: mach/hardware.h: No such file
> or directory
> > #include <mach/hardware.h>
> > ^~~~~~~~~~~~~~~~~
> > compilation terminated.
> >
> > vim +27 sound/arm/pxa2xx-ac97.c
> >
> > 2c484df0 Takashi Iwai 2005-06-30 26
> > 1f017a99 Eric Miao 2008-11-28 @27 #include <mach/regs-ac97.h>
> > a09e64fb Russell King 2008-08-05 28 #include <mach/audio.h>
> > 2c484df0 Takashi Iwai 2005-06-30 29
> >
> > :::::: The code at line 27 was first introduced by commit
> > :::::: 1f017a9964c5b3b9581d3a5732110cb1e0444281 [ARM] pxa: move AC97
> register definitions into dedicated regs-ac97.h
> >
> > :::::: TO: Eric Miao <eric.miao@marvell.com>
> > :::::: CC: Eric Miao <eric.miao@marvell.com>
> >
> > ---
> > 0-DAY kernel test infrastructure Open Source Technology Center
> > https://lists.01.org/pipermail/kbuild-all Intel Corporation
> >
^ permalink raw reply
* [PATCH v11 0/2] CPU scaling support for msm8996 DT
From: Ilia Lin @ 2018-05-23 13:11 UTC (permalink / raw)
To: linux-arm-kernel
[v11]
* Split the series into domains
The series adds OPP tables, thermal and CPU definitions in order to support
the CPU frequency scaling on msm8996 CPUs.
Ilia Lin (2):
dt: qcom: Add opp and thermal to the msm8996
dt: qcom: Add qcom-cpufreq-kryo driver configuration
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 546 +++++++++++++++++++++++++++-
2 files changed, 528 insertions(+), 20 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH v11 1/2] dt: qcom: Add opp and thermal to the msm8996
From: Ilia Lin @ 2018-05-23 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527081091-13389-1-git-send-email-ilialin@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 269 ++++++++++++++++++++++++++++++++--
1 file changed, 260 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 37b7152c..e6cf290 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8996";
@@ -97,6 +98,9 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -109,6 +113,9 @@
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -117,6 +124,9 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -129,6 +139,9 @@
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -155,6 +168,182 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
@@ -163,18 +352,34 @@
thermal-sensors = <&tsens0 3>;
trips {
- cpu_alert0: trip0 {
+ cpu_alert0: cpu_alert0 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn0: cpu_warn0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
- cpu_crit0: trip1 {
+ cpu_crit0: cpu_crit0 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn0>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal1 {
@@ -184,18 +389,34 @@
thermal-sensors = <&tsens0 5>;
trips {
- cpu_alert1: trip0 {
+ cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn1: cpu_warn1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
- cpu_crit1: trip1 {
+ cpu_crit1: cpu_crit1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn1>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal2 {
@@ -205,18 +426,33 @@
thermal-sensors = <&tsens0 8>;
trips {
- cpu_alert2: trip0 {
+ cpu_alert2: cpu_alert2 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn2: cpu_warn2 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
- cpu_crit2: trip1 {
+ cpu_crit2: cpu_crit2 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn2>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal3 {
@@ -226,9 +462,14 @@
thermal-sensors = <&tsens0 10>;
trips {
- cpu_alert3: trip0 {
+ cpu_alert3: cpu_alert3 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn3: cpu_warn3 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
@@ -238,6 +479,16 @@
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert3>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn3>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
};
@@ -414,7 +665,7 @@
};
kryocc: clock-controller at 6400000 {
- compatible = "qcom,apcc-msm8996";
+ compatible = "qcom,msm8996-apcc";
reg = <0x6400000 0x90000>;
#clock-cells = <1>;
};
@@ -1001,7 +1252,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+ pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep>;
vdda-supply = <&pm8994_l28>;
--
1.9.1
^ permalink raw reply related
* [PATCH v11 2/2] dt: qcom: Add qcom-cpufreq-kryo driver configuration
From: Ilia Lin @ 2018-05-23 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527081091-13389-1-git-send-email-ilialin@codeaurora.org>
1. Add NVMEM node for the speedbin
2. Add definitions for all possible MSM8996 CPU OPPs.
The qcom-cpufreq-kryo driver will select the appropriate subset.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 281 ++++++++++++++++++++++++++--
2 files changed, 270 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
index 230e9c8..da23bda 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
@@ -17,5 +17,5 @@
/ {
model = "Qualcomm Technologies, Inc. DB820c";
- compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index e6cf290..d96a112 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1,13 +1,6 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2014-2015, 2018 The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -169,177 +162,436 @@
};
cluster0_opp: opp_table0 {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu",
+ "operating-points-v2";
+ nvmem-cells = <&speedbin_efuse>;
opp-shared;
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x5>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x72>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x5>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x71>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x20>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-supported-hw = <0x10>;
clock-latency-ns = <200000>;
};
};
cluster1_opp: opp_table1 {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
opp-shared;
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1747200000 {
+ opp-hz = /bits/ 64 <1747200000>;
+ opp-supported-hw = <0x70>;
clock-latency-ns = <200000>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-supported-hw = <0x6>;
clock-latency-ns = <200000>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
+ opp-supported-hw = <0x71>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-supported-hw = <0x74>;
clock-latency-ns = <200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-supported-hw = <0x30>;
clock-latency-ns = <200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-supported-hw = <0x30>;
clock-latency-ns = <200000>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
+ opp-supported-hw = <0x31>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2246400000 {
+ opp-hz = /bits/ 64 <2246400000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-supported-hw = <0x10>;
clock-latency-ns = <200000>;
};
};
@@ -917,6 +1169,11 @@
reg = <0x24f 0x1>;
bits = <1 4>;
};
+
+ speedbin_efuse: speedbin at 133 {
+ reg = <0x133 0x1>;
+ bits = <5 3>;
+ };
};
phy at 34000 {
--
1.9.1
^ permalink raw reply related
* [RFT v2 1/4] perf cs-etm: Generate sample for missed packets
From: Leo Yan @ 2018-05-23 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3c9cdb5c-e1e0-f76d-5367-02aaf668b232@arm.com>
Hi Rob,
On Wed, May 23, 2018 at 12:21:18PM +0100, Robert Walker wrote:
> Hi Leo,
>
> On 22/05/18 10:52, Leo Yan wrote:
> >On Tue, May 22, 2018 at 04:39:20PM +0800, Leo Yan wrote:
> >
> >[...]
> >
> >Rather than the patch I posted in my previous email, I think below new
> >patch is more reasonable for me.
> >
> >In the below change, 'etmq->prev_packet' is only used to store the
> >previous CS_ETM_RANGE packet, we don't need to save CS_ETM_TRACE_ON
> >packet into 'etmq->prev_packet'.
> >
> >On the other hand, cs_etm__flush() can use 'etmq->period_instructions'
> >to indicate if need to generate instruction sample or not. If it's
> >non-zero, then generate instruction sample and
> >'etmq->period_instructions' will be cleared; so next time if there
> >have more tracing CS_ETM_TRACE_ON packet, it can skip to generate
> >instruction sample due 'etmq->period_instructions' is zero.
> >
> >How about you think for this?
> >
> >Thanks,
> >Leo Yan
> >
>
> I don't think this covers the cases where CS_ETM_TRACE_ON is used to
> indicate a discontinuity in the trace. For example, there is work in
> progress to configure the ETM so that it only traces a few thousand cycles
> with a gap of many thousands of cycles between each chunk of trace - this
> can be used to sample program execution in the form of instruction events
> with branch stacks for feedback directed optimization (AutoFDO).
>
> In this case, the raw trace is something like:
>
> ...
> I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000007E7B886908;
> I_ATOM_F3 : Atom format 3.; EEN
> I_ATOM_F1 : Atom format 1.; E
> # Trace stops here
>
> # Some time passes, and then trace is turned on again
> I_TRACE_ON : Trace On.
> I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.;
> Addr=0x00000057224322F4; Ctxt: AArch64,EL0, NS;
> I_ATOM_F3 : Atom format 3.; ENN
> I_ATOM_F5 : Atom format 5.; ENENE
> ...
>
> This results in the following packets from the decoder:
>
> CS_ETM_RANGE: [0x7e7b886908-0x7e7b886930] br
> CS_ETM_RANGE: [0x7e7b88699c-0x7e7b8869a4] br
> CS_ETM_RANGE: [0x7e7b8869d8-0x7e7b8869f0]
> CS_ETM_RANGE: [0x7e7b8869f0-0x7e7b8869fc] br
> CS_ETM_TRACE_ON
> CS_ETM_RANGE: [0x57224322f4-0x5722432304] br
> CS_ETM_RANGE: [0x57224320e8-0x57224320ec]
> CS_ETM_RANGE: [0x57224320ec-0x57224320f8]
> CS_ETM_RANGE: [0x57224320f8-0x572243212c] br
> CS_ETM_RANGE: [0x5722439b80-0x5722439bec]
> CS_ETM_RANGE: [0x5722439bec-0x5722439c14] br
> CS_ETM_RANGE: [0x5722437c30-0x5722437c6c]
> CS_ETM_RANGE: [0x5722437c6c-0x5722437c7c] br
>
> Without handling the CS_ETM_TRACE_ON, this would be interpreted as a branch
> from 0x7e7b8869f8 to 0x57224322f4, when there is actually a gap of many
> thousand instructions between these.
>
> I think this patch will break the branch stacks - by removing the
> prev_packet swap from cs_etm__flush(), the next time a CS_ETM_RANGE packet
> is handled, cs_etm__sample() will see prev_packet contains the last
> CS_ETM_RANGE from the previous block of trace, causing an erroneous call to
> cs_etm__update_last_branch_rb(). In the example above, the branch stack
> will contain an erroneous branch from 0x7e7b8869f8 to 0x57224322f4.
>
> I think what you need to do is add a check for the previous packet being a
> CS_ETM_TRACE_ON when determining the generate_sample value.
I still can see there have hole for packets handling with your
suggestion, let's focus on below three packets:
CS_ETM_RANGE: [0x7e7b8869f0-0x7e7b8869fc] br
CS_ETM_TRACE_ON: [0xdeadbeefdeadbeef-0xdeadbeefdeadbeef]
CS_ETM_RANGE: [0x57224322f4-0x5722432304] br
When the CS_ETM_TRACE_ON packet is coming, cs_etm__flush() doesn't
handle for 'etmq->prev_packet' to generate branch sample, this results
in we miss the info for 0x7e7b8869fc, and with packet swapping
'etmq->prev_packet' is assigned to CS_ETM_TRACE_ON packet.
When the last CS_ETM_RANGE packet is coming, cs_etm__sample() will
combine the values from CS_ETM_TRACE_ON packet and the last
CS_ETM_RANGE packet to generate branch sample packet; at the end
we get below sample packets:
packet(n): sample::addr=0x7e7b8869f0
packet(n+1): sample::ip=0xdeadbeefdeadbeeb sample::addr=0x57224322f4
So I think we also need to generate branch sample, and we can get
below results:
packet(n): sample::addr=0x7e7b8869f0
packet(n+1): sample::ip=0x7e7b8869f8 sample::addr=0xdeadbeefdeadbeef
packet(n+2): sample::ip=0xdeadbeefdeadbeeb sample::addr=0x57224322f4
So we also can rely on this to get to know there have one address
range is [0xdeadbeefdeadbeef..0xdeadbeefdeadbeeb] to indicate there
have a discontinuity in the trace.
> Regards
>
> Rob
>
> >
> >diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> >index 822ba91..dd354ad 100644
> >--- a/tools/perf/util/cs-etm.c
> >+++ b/tools/perf/util/cs-etm.c
> >@@ -495,6 +495,13 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq)
> > static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet)
> > {
> > /*
> >+ * The packet is the start tracing packet if the end_addr is zero,
> >+ * returns 0 for this case.
> >+ */
> >+ if (!packet->end_addr)
> >+ return 0;
> >+
> >+ /*
> > * The packet records the execution range with an exclusive end address
> > *
> > * A64 instructions are constant size, so the last executed
> >@@ -897,13 +904,27 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
> > etmq->period_instructions = instrs_over;
> > }
> >- if (etm->sample_branches &&
> >- etmq->prev_packet &&
> >- etmq->prev_packet->sample_type == CS_ETM_RANGE &&
> >- etmq->prev_packet->last_instr_taken_branch) {
> >- ret = cs_etm__synth_branch_sample(etmq);
> >- if (ret)
> >- return ret;
> >+ if (etm->sample_branches && etmq->prev_packet) {
> >+ bool generate_sample = false;
> >+
> >+ /* Generate sample for start tracing packet */
> >+ if (etmq->prev_packet->sample_type == 0)
> >+ generate_sample = true;
>
> Also check for etmq->prev_packet->sample_type == CS_ETM_TRACE_ON here and
> set generate_sample = true.
Agree, will add this.
> >+
> >+ /* Generate sample for exception packet */
> >+ if (etmq->prev_packet->exc == true)
> >+ generate_sample = true;
> >+
> >+ /* Generate sample for normal branch packet */
> >+ if (etmq->prev_packet->sample_type == CS_ETM_RANGE &&
> >+ etmq->prev_packet->last_instr_taken_branch)
> >+ generate_sample = true;
> >+
> >+ if (generate_sample) {
> >+ ret = cs_etm__synth_branch_sample(etmq);
> >+ if (ret)
> >+ return ret;
> >+ }
> > }
> > if (etm->sample_branches || etm->synth_opts.last_branch) {
> >@@ -922,11 +943,12 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
> > static int cs_etm__flush(struct cs_etm_queue *etmq)
> > {
> > int err = 0;
> >- struct cs_etm_packet *tmp;
> > if (etmq->etm->synth_opts.last_branch &&
> > etmq->prev_packet &&
> >- etmq->prev_packet->sample_type == CS_ETM_RANGE) {
> >+ etmq->prev_packet->sample_type == CS_ETM_RANGE &&
> >+ etmq->period_instructions) {
> >+
>
> I don't think this is needed.
Okay, I will keep this.
> > /*
> > * Generate a last branch event for the branches left in the
> > * circular buffer at the end of the trace.
> >@@ -940,14 +962,6 @@ static int cs_etm__flush(struct cs_etm_queue *etmq)
> > etmq, addr,
> > etmq->period_instructions);
> > etmq->period_instructions = 0;
> >-
> >- /*
> >- * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for
> >- * the next incoming packet.
> >- */
> >- tmp = etmq->packet;
> >- etmq->packet = etmq->prev_packet;
> >- etmq->prev_packet = tmp;
>
> This should not be changed as discussed above.
Okay, will keep this. But I suggest we add some change like below:
+ if (etm->sample_branches) {
+ err = cs_etm__synth_branch_sample(etmq);
+ if (err)
+ return err;
+ }
If so, could you review my posted another patch for this?
http://archive.armlinux.org.uk/lurker/message/20180522.083920.184f1f78.en.html
Thanks,
Leo Yan
> > }
> > return err;
> >
^ permalink raw reply
* [PATCH v10 07/18] arm64: fpsimd: Eliminate task->mm checks
From: Dave Martin @ 2018-05-23 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180523114812.GH55598@C02W217FHV2R.local>
On Wed, May 23, 2018 at 01:48:12PM +0200, Christoffer Dall wrote:
> On Tue, May 22, 2018 at 05:05:08PM +0100, Dave Martin wrote:
> > Currently the FPSIMD handling code uses the condition task->mm ==
> > NULL as a hint that task has no FPSIMD register context.
> >
> > The ->mm check is only there to filter out tasks that cannot
> > possibly have FPSIMD context loaded, for optimisation purposes.
> > Also, TIF_FOREIGN_FPSTATE must always be checked anyway before
> > saving FPSIMD context back to memory. For these reasons, the ->mm
> > checks are not useful, providing that that TIF_FOREIGN_FPSTATE is
Hmmm, "that that". I'll fix that.
> > maintained in a consistent way for kernel threads.
> >
> > This is true by construction however: TIF_FOREIGN_FPSTATE is never
> > cleared except when returning to userspace or returning from a
> > signal: thus, for a true kernel thread no FPSIMD context is ever
> > loaded, TIF_FOREIGN_FPSTATE will remain set and no context will
> > ever be saved.
>
> I don't understand this construction proof; from looking at the patch
> below it is not obvious to me why fpsimd_thread_switch() can never have
> !wrong_task && !wrong_cpu and therefore clear TIF_FOREIGN_FPSTATE for a
> kernel thread?
Looking at this again, I think it is poorly worded. This patch aims to
make it true by construction, but it isn't prior to the patch.
I'm tempted to delete the paragraph: the assertion of both untrue and
not the best way to justify that this patch works.
How about:
-8<-
The context switch logic already isolates user threads from each other.
This, it is sufficient for isolating user threads from the kernel,
since the goal either way is to ensure that code executing in userspace
cannot see any FPSIMD state except its own. Thus, there is no special
property of kernel threads that we care about except that it is
pointless to save or load FPSIMD register state for them.
At worst, the removal of all the kernel thread special cases by this
patch would thus spuriously load and save state for kernel threads when
unnecessary.
But the context switch logic is already deliberately optimised to defer
reloads of the regs until ret_to_user (or sigreturn as a special case),
which kernel threads by definition never reach.
->8-
As an aside, I notice that we allow thread.fpsimd_cpu to be initialised
to 0 for the init task. This means that the wrong_cpu check may yield
false for the init task when it shouldn't, because the init task's
FPSIMD state (which doesn't logically exist) is never loaded anywhere.
But the wrong_task check will always yield true for the init task for
the same reason, so this is just an inconsistency in the code rather
than a bug AFAICT.
copy_thread() calls fpsimd_flush_task_state() to make sure that
wrong_cpu is initially true for new tasks. We should do the same for
the init task by adding
.fpsimd_cpu = NR_CPUS,
to INIT_THREAD.
Cheers
---Dave
>
>
> Thanks,
> -Christoffer
>
> >
> > This patch removes the redundant checks and special-case code.
> >
> > Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >
> > ---
> >
> > Changes since v9:
> >
> > * New patch. Introduced during debugging, since the ->mm checks
> > appear bogus and/or redundant, so are likely to be hiding or
> > causing bugs.
> > ---
> > arch/arm64/include/asm/thread_info.h | 1 +
> > arch/arm64/kernel/fpsimd.c | 38 ++++++++++++------------------------
> > 2 files changed, 14 insertions(+), 25 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
> > index 740aa03c..a2ac914 100644
> > --- a/arch/arm64/include/asm/thread_info.h
> > +++ b/arch/arm64/include/asm/thread_info.h
> > @@ -47,6 +47,7 @@ struct thread_info {
> >
> > #define INIT_THREAD_INFO(tsk) \
> > { \
> > + .flags = _TIF_FOREIGN_FPSTATE, \
> > .preempt_count = INIT_PREEMPT_COUNT, \
> > .addr_limit = KERNEL_DS, \
> > }
> > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
> > index 3aa100a..1222491 100644
> > --- a/arch/arm64/kernel/fpsimd.c
> > +++ b/arch/arm64/kernel/fpsimd.c
> > @@ -891,31 +891,21 @@ asmlinkage void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
> >
> > void fpsimd_thread_switch(struct task_struct *next)
> > {
> > + bool wrong_task, wrong_cpu;
> > +
> > if (!system_supports_fpsimd())
> > return;
> > - /*
> > - * Save the current FPSIMD state to memory, but only if whatever is in
> > - * the registers is in fact the most recent userland FPSIMD state of
> > - * 'current'.
> > - */
> > - if (current->mm)
> > - fpsimd_save();
> >
> > - if (next->mm) {
> > - /*
> > - * If we are switching to a task whose most recent userland
> > - * FPSIMD state is already in the registers of *this* cpu,
> > - * we can skip loading the state from memory. Otherwise, set
> > - * the TIF_FOREIGN_FPSTATE flag so the state will be loaded
> > - * upon the next return to userland.
> > - */
> > - bool wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
> > + /* Save unsaved fpsimd state, if any: */
> > + fpsimd_save();
> > +
> > + /* Fix up TIF_FOREIGN_FPSTATE to correctly describe next's state: */
> > + wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
> > &next->thread.uw.fpsimd_state;
> > - bool wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
> > + wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
> >
> > - update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
> > - wrong_task || wrong_cpu);
> > - }
> > + update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
> > + wrong_task || wrong_cpu);
> > }
> >
> > void fpsimd_flush_thread(void)
> > @@ -1120,9 +1110,8 @@ void kernel_neon_begin(void)
> >
> > __this_cpu_write(kernel_neon_busy, true);
> >
> > - /* Save unsaved task fpsimd state, if any: */
> > - if (current->mm)
> > - fpsimd_save();
> > + /* Save unsaved fpsimd state, if any: */
> > + fpsimd_save();
> >
> > /* Invalidate any task state remaining in the fpsimd regs: */
> > fpsimd_flush_cpu_state();
> > @@ -1244,8 +1233,7 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
> > {
> > switch (cmd) {
> > case CPU_PM_ENTER:
> > - if (current->mm)
> > - fpsimd_save();
> > + fpsimd_save();
> > fpsimd_flush_cpu_state();
> > break;
> > case CPU_PM_EXIT:
> > --
> > 2.1.4
[...]
> _______________________________________________
> kvmarm mailing list
> kvmarm at lists.cs.columbia.edu
> https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply
* [PATCH v1] dma: imx-sdma: add virt-dma support
From: Vinod @ 2018-05-23 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180523105612.u4wbezh7fzkv4wfh@pengutronix.de>
On 23-05-18, 12:56, s.hauer at pengutronix.de wrote:
> Well, it's somewhat related to virtual dma support, but that's not my
> point. My point is that this patch is quite big and thus hard to review.
> If we find ways to make it smaller and to split it up in multiple
> patches then we should do so, because it makes it easier to review and
> in case you break something here we raise the chance that a "git bisect"
> lands on a smaller patch which is easier to understand.
>
> Please try and make that a separate change. I haven't really looked into
> it and it may not be possible due to reasons I haven't seen, but please
> at least give it a try.
That is something would help me as well. I have reviewed the patch and am not
sure I fully understand the changes, so breaking up stuff would definitely help
in the review..
--
~Vinod
^ permalink raw reply
* [PATCH] arm64: defconfig: Enable BD9571MWV regulator
From: Geert Uytterhoeven @ 2018-05-23 13:35 UTC (permalink / raw)
To: linux-arm-kernel
From: Dien Pham <dien.pham.ry@renesas.com>
The BD9571 PMIC is present on the Renesas Salvator-X(S) and R-Car
Starter Kit Premier/Pro development boards.
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3a9096bebc74b288..8e430fce8dc97dee 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -363,6 +363,7 @@ CONFIG_MESON_WATCHDOG=m
CONFIG_RENESAS_WDT=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_BCM2835_WDT=y
+CONFIG_MFD_BD9571MWV=y
CONFIG_MFD_AXP20X_RSB=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
@@ -375,6 +376,7 @@ CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_RK808=y
CONFIG_MFD_SEC_CORE=y
CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD9571MWV=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
--
2.7.4
^ permalink raw reply related
* [PATCH v10 01/18] arm64: fpsimd: Fix TIF_FOREIGN_FPSTATE after invalidating cpu regs
From: Alex Bennée @ 2018-05-23 13:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527005119-6842-2-git-send-email-Dave.Martin@arm.com>
Dave Martin <Dave.Martin@arm.com> writes:
> fpsimd_last_state.st is set to NULL as a way of indicating that
> current's FPSIMD registers are no longer loaded in the cpu. In
> particular, this is done when the kernel temporarily uses or
> clobbers the FPSIMD registers for its own purposes, as in CPU PM or
> kernel-mode NEON, resulting in them being populated with garbage
> data not belonging to a task.
<snip>
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>
--
Alex Benn?e
^ permalink raw reply
* [PATCH v10 01/18] arm64: fpsimd: Fix TIF_FOREIGN_FPSTATE after invalidating cpu regs
From: Catalin Marinas @ 2018-05-23 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527005119-6842-2-git-send-email-Dave.Martin@arm.com>
On Tue, May 22, 2018 at 05:05:02PM +0100, Dave P Martin wrote:
> fpsimd_last_state.st is set to NULL as a way of indicating that
> current's FPSIMD registers are no longer loaded in the cpu. In
> particular, this is done when the kernel temporarily uses or
> clobbers the FPSIMD registers for its own purposes, as in CPU PM or
> kernel-mode NEON, resulting in them being populated with garbage
> data not belonging to a task.
>
> Commit 17eed27b02da ("arm64/sve: KVM: Prevent guests from using
> SVE") factors this operation out as a new helper
> fpsimd_flush_cpu_state() to make it clearer what is being done
> here, and on SVE systems this helper is now used, via
> kvm_fpsimd_flush_cpu_state(), to invalidate the registers after KVM
> has run a vcpu. The reason for this is that KVM does not yet
> understand how to restore the full host SVE registers itself after
> loading the guest FPSIMD context into them.
>
> This exposes a particular problem: if fpsimd_last_state.st is set
> to NULL without also setting TIF_FOREIGN_FPSTATE, the kernel may
> continue to think that current's FPSIMD registers are live even
> though they have actually been clobbered.
>
> Prior to the aforementioned commit, the only path where
> fpsimd_last_state.st is set to NULL without setting
> TIF_FOREIGN_FPSTATE is when kernel_neon_begin() is called by a
> kernel thread (where current->mm can be NULL). This does not
> matter, because the only harm is that at context-switch time
> fpsimd_thread_switch() may unnecessarily save the FPSIMD registers
> back to current's thread_struct (even though kernel threads are not
> considered to have any FPSIMD context of their own and the
> registers will never be reloaded).
>
> Note that although CPU_PM_ENTER lacks the TIF_FOREIGN_FPSTATE
> setting, every CPU passing through that path must subsequently pass
> through CPU_PM_EXIT before it can re-enter the kernel proper.
> CPU_PM_EXIT sets the flag.
>
> The sve_flush_cpu_state() function added by commit 17eed27b02da
> also lacks the proper maintenance of TIF_FOREIGN_FPSTATE. This may
> cause the bits of a host task's SVE registers that do not alias the
> FPSIMD register file to spontaneously appear zeroed if a KVM vcpu
> runs in the same task in the meantime. Although this effect is
> hidden by the fact that the non-FPSIMD bits of the SVE registers
> are zeroed by a syscall anyway, it is doubtless a bad idea to rely
> on these different code paths interacting correctly under future
> maintenance.
>
> This patch makes TIF_FOREIGN_FPSTATE an unconditional side-effect
> of fpsimd_flush_cpu_state(), and removes the set_thread_flag()
> calls that become redunant as a result. This ensures that
> TIF_FOREIGN_FPSTATE cannot remain clear if the FPSIMD state in the
> FPSIMD registers is invalid.
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH v10 02/18] thread_info: Add update_thread_flag() helpers
From: Alex Bennée @ 2018-05-23 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527005119-6842-3-git-send-email-Dave.Martin@arm.com>
Dave Martin <Dave.Martin@arm.com> writes:
> There are a number of bits of code sprinkled around the kernel to
> set a thread flag if a certain condition is true, and clear it
> otherwise.
>
> To help make those call sites terser and less cumbersome, this
> patch adds a new family of thread flag manipulators
>
> update*_thread_flag([...,] flag, cond)
>
> which do the equivalent of:
>
> if (cond)
> set*_thread_flag([...,] flag);
> else
> clear*_thread_flag([...,] flag);
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> ---
> include/linux/sched.h | 6 ++++++
> include/linux/thread_info.h | 11 +++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/include/linux/sched.h b/include/linux/sched.h
> index b3d697f..c2c3051 100644
> --- a/include/linux/sched.h
> +++ b/include/linux/sched.h
> @@ -1578,6 +1578,12 @@ static inline void clear_tsk_thread_flag(struct task_struct *tsk, int flag)
> clear_ti_thread_flag(task_thread_info(tsk), flag);
> }
>
> +static inline void update_tsk_thread_flag(struct task_struct *tsk, int flag,
> + bool value)
> +{
> + update_ti_thread_flag(task_thread_info(tsk), flag, value);
> +}
> +
> static inline int test_and_set_tsk_thread_flag(struct task_struct *tsk, int flag)
> {
> return test_and_set_ti_thread_flag(task_thread_info(tsk), flag);
> diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
> index cf2862b..8d8821b 100644
> --- a/include/linux/thread_info.h
> +++ b/include/linux/thread_info.h
> @@ -60,6 +60,15 @@ static inline void clear_ti_thread_flag(struct thread_info *ti, int flag)
> clear_bit(flag, (unsigned long *)&ti->flags);
> }
>
> +static inline void update_ti_thread_flag(struct thread_info *ti, int flag,
> + bool value)
> +{
> + if (value)
> + set_ti_thread_flag(ti, flag);
> + else
> + clear_ti_thread_flag(ti, flag);
> +}
> +
value does seem a bit of vanilla non-informative name for a condition
flag but whatever:
Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>
> static inline int test_and_set_ti_thread_flag(struct thread_info *ti, int flag)
> {
> return test_and_set_bit(flag, (unsigned long *)&ti->flags);
> @@ -79,6 +88,8 @@ static inline int test_ti_thread_flag(struct thread_info *ti, int flag)
> set_ti_thread_flag(current_thread_info(), flag)
> #define clear_thread_flag(flag) \
> clear_ti_thread_flag(current_thread_info(), flag)
> +#define update_thread_flag(flag, value) \
> + update_ti_thread_flag(current_thread_info(), flag, value)
> #define test_and_set_thread_flag(flag) \
> test_and_set_ti_thread_flag(current_thread_info(), flag)
> #define test_and_clear_thread_flag(flag) \
--
Alex Benn?e
^ permalink raw reply
* [PATCH v10 03/18] arm64: Use update{,_tsk}_thread_flag()
From: Alex Bennée @ 2018-05-23 13:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527005119-6842-4-git-send-email-Dave.Martin@arm.com>
Dave Martin <Dave.Martin@arm.com> writes:
> This patch uses the new update_thread_flag() helpers to simplify a
> couple of if () set; else clear; constructs.
>
> No functional change.
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>
> ---
> arch/arm64/kernel/fpsimd.c | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
> index 12e1c96..9d85373 100644
> --- a/arch/arm64/kernel/fpsimd.c
> +++ b/arch/arm64/kernel/fpsimd.c
> @@ -618,10 +618,8 @@ int sve_set_vector_length(struct task_struct *task,
> task->thread.sve_vl = vl;
>
> out:
> - if (flags & PR_SVE_VL_INHERIT)
> - set_tsk_thread_flag(task, TIF_SVE_VL_INHERIT);
> - else
> - clear_tsk_thread_flag(task, TIF_SVE_VL_INHERIT);
> + update_tsk_thread_flag(task, TIF_SVE_VL_INHERIT,
> + flags & PR_SVE_VL_INHERIT);
>
> return 0;
> }
> @@ -910,12 +908,12 @@ void fpsimd_thread_switch(struct task_struct *next)
> * the TIF_FOREIGN_FPSTATE flag so the state will be loaded
> * upon the next return to userland.
> */
> - if (__this_cpu_read(fpsimd_last_state.st) ==
> - &next->thread.uw.fpsimd_state
> - && next->thread.fpsimd_cpu == smp_processor_id())
> - clear_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE);
> - else
> - set_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE);
> + bool wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
> + &next->thread.uw.fpsimd_state;
> + bool wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
> +
> + update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
> + wrong_task || wrong_cpu);
> }
> }
--
Alex Benn?e
^ permalink raw reply
* [PATCH v11 1/8] soc: qcom: Separate kryo l2 accessors from PMU driver
From: Sudeep Holla @ 2018-05-23 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527079981-11179-2-git-send-email-ilialin@codeaurora.org>
On 23/05/18 13:52, Ilia Lin wrote:
> The driver provides kernel level API for other drivers
> to access the MSM8996 L2 cache registers.
> Separating the L2 access code from the PMU driver and
> making it public to allow other drivers use it.
> The accesses must be separated with a single spinlock,
> maintained in this driver.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 ++++++++++--------------------------
> drivers/soc/qcom/Kconfig | 3 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/kryo-l2-accessors.c | 56 ++++++++++++++++++++++
> include/soc/qcom/kryo-l2-accessors.h | 12 +++++
> 6 files changed, 97 insertions(+), 66 deletions(-)
> create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c
> create mode 100644 include/soc/qcom/kryo-l2-accessors.h
>
[..
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 7093fe7..0567dff 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -39,6 +39,9 @@ config QCOM_GSBI
> functions for connecting the underlying serial UART, SPI, and I2C
> devices to the output pins.
>
> +config QCOM_KRYO_L2_ACCESSORS
> + bool
> +
I think kbuild bot complained about this and you haven't addressed it.
This can be enabled on ARM and build breaks due to missing sysreg.h
IIRC. Look at the kbuild report and fix it.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH] ARM: DTS: imx53: Add support for imx53 HSC/DDC boards from K+P
From: Fabio Estevam @ 2018-05-23 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180519140202.3449e3c1@jawa>
Hi Lukasz,
On Sat, May 19, 2018 at 9:02 AM, Lukasz Majewski <lukma@denx.de> wrote:
> After removing imx53-kp-ddc and imx53-kp-common iomux subnodes I do see
> following errors in the dmesg (v4.17-rc5):
>
> imx53-pinctrl 53fa8000.iomuxc: function 'iomuxc' not supported
> imx53-pinctrl 53fa8000.iomuxc: invalid function iomuxc in map table
Could you please investigate this error?
I have just tried the following change on a imx53-qsb:
http://code.bulix.org/ik01yu-339697
and it works as expected:
# dmesg | grep iomux
[ 0.100046] imx53-pinctrl 53fa8000.iomuxc: initialized IMX pinctrl driver
^ permalink raw reply
* [PATCH v10 02/18] thread_info: Add update_thread_flag() helpers
From: Dave Martin @ 2018-05-23 13:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87po1mtrg3.fsf@linaro.org>
On Wed, May 23, 2018 at 02:46:52PM +0100, Alex Benn?e wrote:
>
> Dave Martin <Dave.Martin@arm.com> writes:
>
> > There are a number of bits of code sprinkled around the kernel to
> > set a thread flag if a certain condition is true, and clear it
> > otherwise.
> >
> > To help make those call sites terser and less cumbersome, this
> > patch adds a new family of thread flag manipulators
> >
> > update*_thread_flag([...,] flag, cond)
> >
> > which do the equivalent of:
> >
> > if (cond)
> > set*_thread_flag([...,] flag);
> > else
> > clear*_thread_flag([...,] flag);
> >
> > Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> > Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
> > Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> > Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Ingo Molnar <mingo@redhat.com>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: Oleg Nesterov <oleg@redhat.com>
> > ---
> > include/linux/sched.h | 6 ++++++
> > include/linux/thread_info.h | 11 +++++++++++
> > 2 files changed, 17 insertions(+)
> >
[...]
> > diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
> > index cf2862b..8d8821b 100644
> > --- a/include/linux/thread_info.h
> > +++ b/include/linux/thread_info.h
> > @@ -60,6 +60,15 @@ static inline void clear_ti_thread_flag(struct thread_info *ti, int flag)
> > clear_bit(flag, (unsigned long *)&ti->flags);
> > }
> >
> > +static inline void update_ti_thread_flag(struct thread_info *ti, int flag,
> > + bool value)
> > +{
> > + if (value)
> > + set_ti_thread_flag(ti, flag);
> > + else
> > + clear_ti_thread_flag(ti, flag);
> > +}
> > +
>
> value does seem a bit of vanilla non-informative name for a condition
> flag but whatever:
>
> Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>
I guess, though I couldn't some up with an obviously better name.
I support "condition" would have worked, but it's more verbose.
Thanks for the review
---Dave
^ permalink raw reply
* [PATCH v9 3/4] arm64: Implement page table free interfaces
From: Will Deacon @ 2018-05-23 14:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525074094-25839-4-git-send-email-cpandya@codeaurora.org>
Hi Chintan,
[as a side note: I'm confused on the status of this patch series, as part
of it was reposted separately by Toshi. Please can you work together?]
On Mon, Apr 30, 2018 at 01:11:33PM +0530, Chintan Pandya wrote:
> Implement pud_free_pmd_page() and pmd_free_pte_page().
>
> Implementation requires,
> 1) Clearing off the current pud/pmd entry
> 2) Invalidate TLB which could have previously
> valid but not stale entry
> 3) Freeing of the un-used next level page tables
>
> Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
> ---
> arch/arm64/mm/mmu.c | 29 +++++++++++++++++++++++++----
> 1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index da98828..0f651db 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -45,6 +45,7 @@
> #include <asm/memblock.h>
> #include <asm/mmu_context.h>
> #include <asm/ptdump.h>
> +#include <asm/tlbflush.h>
>
> #define NO_BLOCK_MAPPINGS BIT(0)
> #define NO_CONT_MAPPINGS BIT(1)
> @@ -973,12 +974,32 @@ int pmd_clear_huge(pmd_t *pmdp)
> return 1;
> }
>
> -int pud_free_pmd_page(pud_t *pud, unsigned long addr)
> +int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr)
> {
> - return pud_none(*pud);
> + pmd_t *table;
> +
> + if (pmd_present(READ_ONCE(*pmdp))) {
Might also be worth checking pmd_table here, just in case. (same for pud)
> + table = __va(pmd_val(*pmdp));
Can you avoid dereferencing *pmdp twice, and instead READ_ONCE into a local
variable, please? (same for pud)
> + pmd_clear(pmdp);
> + __flush_tlb_kernel_pgtable(addr);
> + free_page((unsigned long) table);
Shouldn't this be pte_free_kernel, to pair with pte_alloc_kernel which
was used to allocate the page in the first place? (similarly for pud)
> + }
> + return 1;
> }
>
> -int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
> +int pud_free_pmd_page(pud_t *pudp, unsigned long addr)
> {
> - return pmd_none(*pmd);
> + pmd_t *table;
> + int i;
> +
> + if (pud_present(READ_ONCE(*pudp))) {
> + table = __va(pud_val(*pudp));
> + for (i = 0; i < PTRS_PER_PMD; i++)
> + pmd_free_pte_page(&table[i], addr + (i * PMD_SIZE));
I think it would be cleaner to write this as a do { ... } while, for
consistency with the ioremap and vmalloc code.
Will
^ permalink raw reply
* [PATCH v2 09/16] irqchip/irq-mvebu-sei: add new driver for Marvell SEI
From: Marc Zyngier @ 2018-05-23 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522094042.24770-10-miquel.raynal@bootlin.com>
On 22/05/18 10:40, Miquel Raynal wrote:
> This is a cascaded interrupt controller in the AP806 GIC that collapses
> SEIs (System Error Interrupt) coming from the AP and the CPs (through
> the ICU).
>
> The SEI handles up to 64 interrupts. The first 21 interrupts are wired
> and come from the AP. The next 43 interrupts are from the CPs and are
wired to the AP (no interrupts come from it)
> triggered through MSI messages. To handle this complexity, the driver
> has to declare to the upper layer: one IRQ domain for the wired
> interrupts, one IRQ domain for the MSIs; and acts as a MSI server
s/server/controller/
> ('parent') by declaring an MSI domain.
>
> Suggested-by: Haim Boot <hayim@marvell.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/irqchip/Kconfig | 3 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-mvebu-sei.c | 422 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 426 insertions(+)
> create mode 100644 drivers/irqchip/irq-mvebu-sei.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index e9233db16e03..922e2a919cf3 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -310,6 +310,9 @@ config MVEBU_ODMI
> config MVEBU_PIC
> bool
>
> +config MVEBU_SEI
> + bool
> +
> config LS_SCFG_MSI
> def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
> depends on PCI && PCI_MSI
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 15f268f646bf..69d2ccb454ef 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -76,6 +76,7 @@ obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
> obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
> obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
> obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
> +obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
> diff --git a/drivers/irqchip/irq-mvebu-sei.c b/drivers/irqchip/irq-mvebu-sei.c
> new file mode 100644
> index 000000000000..d9abd5e10741
> --- /dev/null
> +++ b/drivers/irqchip/irq-mvebu-sei.c
> @@ -0,0 +1,422 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#define pr_fmt(fmt) "mvebu-sei: " fmt
> +
> +#include <linux/irq.h>
> +#include <linux/interrupt.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/msi.h>
> +#include <linux/platform_device.h>
> +#include <linux/irqchip.h>
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/* Cause register */
> +#define GICP_SECR(idx) (0x0 + (idx * 0x4))
> +/* Mask register */
> +#define GICP_SEMR(idx) (0x20 + (idx * 0x4))
> +#define GICP_SET_SEI_OFFSET 0x30
> +
> +#define SEI_IRQ_COUNT_PER_REG 32
> +#define SEI_IRQ_REG_COUNT 2
> +#define SEI_IRQ_COUNT (SEI_IRQ_COUNT_PER_REG * SEI_IRQ_REG_COUNT)
> +#define SEI_IRQ_REG_IDX(irq_id) (irq_id / SEI_IRQ_COUNT_PER_REG)
> +#define SEI_IRQ_REG_BIT(irq_id) (irq_id % SEI_IRQ_COUNT_PER_REG)
> +
> +struct mvebu_sei_interrupt_range {
> + u32 first;
> + u32 number;
> +};
> +
> +struct mvebu_sei {
> + struct device *dev;
> + void __iomem *base;
> + struct resource *res;
> + struct irq_domain *ap_domain;
> + struct irq_domain *cp_domain;
> + struct mvebu_sei_interrupt_range ap_interrupts;
> + struct mvebu_sei_interrupt_range cp_interrupts;
> + /* Lock on MSI allocations/releases */
> + spinlock_t cp_msi_lock;
> + DECLARE_BITMAP(cp_msi_bitmap, SEI_IRQ_COUNT);
> +};
> +
> +static int mvebu_sei_domain_to_sei_irq(struct mvebu_sei *sei,
> + struct irq_domain *domain,
> + irq_hw_number_t hwirq)
> +{
> + if (domain == sei->ap_domain)
> + return sei->ap_interrupts.first + hwirq;
> + else
> + return sei->cp_interrupts.first + hwirq;
> +}
> +
> +static void mvebu_sei_reset(struct mvebu_sei *sei)
> +{
> + u32 reg_idx;
> +
> + /* Clear IRQ cause registers */
> + for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++)
> + writel(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
> +}
> +
> +static void mvebu_sei_mask_irq(struct irq_data *d)
> +{
> + struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
> + u32 sei_irq = mvebu_sei_domain_to_sei_irq(sei, d->domain, d->hwirq);
> + u32 reg_idx = SEI_IRQ_REG_IDX(sei_irq);
> + u32 reg;
> +
> + /* 1 disables the interrupt */
> + reg = readl(sei->base + GICP_SEMR(reg_idx));
> + reg |= BIT(SEI_IRQ_REG_BIT(sei_irq));
> + writel(reg, sei->base + GICP_SEMR(reg_idx));
> +}
> +
> +static void mvebu_sei_unmask_irq(struct irq_data *d)
> +{
> + struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
> + u32 sei_irq = mvebu_sei_domain_to_sei_irq(sei, d->domain, d->hwirq);
> + u32 reg_idx = SEI_IRQ_REG_IDX(sei_irq);
> + u32 reg;
> +
> + /* 0 enables the interrupt */
> + reg = readl(sei->base + GICP_SEMR(reg_idx));
> + reg &= ~BIT(SEI_IRQ_REG_BIT(sei_irq));
> + writel(reg, sei->base + GICP_SEMR(reg_idx));
> +}
> +
> +static void mvebu_sei_compose_msi_msg(struct irq_data *data,
> + struct msi_msg *msg)
> +{
> + struct mvebu_sei *sei = data->chip_data;
> + phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET;
> +
> + msg->data = mvebu_sei_domain_to_sei_irq(sei, data->domain, data->hwirq);
> + msg->address_lo = lower_32_bits(set);
> + msg->address_hi = upper_32_bits(set);
> +}
> +
> +static struct irq_chip mvebu_sei_ap_wired_irq_chip = {
> + .name = "AP wired SEI",
> + .irq_mask = mvebu_sei_mask_irq,
> + .irq_unmask = mvebu_sei_unmask_irq,
> + .irq_eoi = irq_chip_eoi_parent,
> + .irq_set_affinity = irq_chip_set_affinity_parent,
> + .irq_set_type = irq_chip_set_type_parent,
You seem to assume that this driver is purely dealing with edge
interrupts. And yet you pass the request directly to the parrent. What
does it mean? Shouldn't you at least check that this is an edge request
and fail otherwise?
> +};
> +
> +static struct irq_chip mvebu_sei_cp_msi_irq_chip = {
> + .name = "CP MSI SEI",
> + .irq_mask = mvebu_sei_mask_irq,
> + .irq_unmask = mvebu_sei_unmask_irq,
> + .irq_eoi = irq_chip_eoi_parent,
> + .irq_set_affinity = irq_chip_set_affinity_parent,
> + .irq_set_type = irq_chip_set_type_parent,
Same here.
> + .irq_compose_msi_msg = mvebu_sei_compose_msi_msg,
> +};
> +
> +static int mvebu_sei_irq_domain_alloc(struct irq_domain *domain,
> + unsigned int virq, unsigned int nr_irqs,
> + void *args)
> +{
> + struct mvebu_sei *sei = domain->host_data;
> + struct irq_fwspec *fwspec = args;
> + struct irq_chip *irq_chip;
> + int sei_hwirq, hwirq;
> + int ret;
> +
> + /* Software only supports single allocations for now */
> + if (nr_irqs != 1)
> + return -ENOTSUPP;
> +
> + if (domain == sei->ap_domain) {
That's not great, really. Pushing the management of the two domains into
the same callbacks is pretty ugly, and makes the code rather confusing.
Is there anything really preventing the two domains from being managed
independently?
> + irq_chip = &mvebu_sei_ap_wired_irq_chip;
> + hwirq = fwspec->param[0];
> + } else {
> + irq_chip = &mvebu_sei_cp_msi_irq_chip;
> + spin_lock(&sei->cp_msi_lock);
This could as well be a mutex.
> + hwirq = bitmap_find_free_region(sei->cp_msi_bitmap,
> + SEI_IRQ_COUNT, 0);
It is a bit weird that you're allocating from a 64bit bitmap while you
only have 43 interrupts available... At the 44th interrupt, something
bad is going to happen.
> + spin_unlock(&sei->cp_msi_lock);
> + if (hwirq < 0)
> + return -ENOSPC;
> + }
> +
> + sei_hwirq = mvebu_sei_domain_to_sei_irq(sei, domain, hwirq);
Splitting the callbacks would definitely avoid that kind of horror.
> +
> + fwspec->fwnode = domain->parent->fwnode;
> + fwspec->param_count = 3;
> + fwspec->param[0] = GIC_SPI;
> + fwspec->param[1] = sei_hwirq;
> + fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
> +
> + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, fwspec);
> + if (ret)
> + goto release_region;
> +
> + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, irq_chip, sei);
> + if (ret)
> + goto free_irq_parents;
> +
> + return 0;
> +
> +free_irq_parents:
> + irq_domain_free_irqs_parent(domain, virq, nr_irqs);
> +release_region:
> + if (domain == sei->cp_domain) {
> + spin_lock(&sei->cp_msi_lock);
> + bitmap_release_region(sei->cp_msi_bitmap, hwirq, 0);
> + spin_unlock(&sei->cp_msi_lock);
> + }
> +
> + return ret;
> +}
> +
> +static void mvebu_sei_irq_domain_free(struct irq_domain *domain,
> + unsigned int virq, unsigned int nr_irqs)
> +{
> + struct mvebu_sei *sei = domain->host_data;
> + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> + u32 irq_nb = sei->ap_interrupts.number + sei->cp_interrupts.number;
> +
> + if (nr_irqs != 1 || d->hwirq >= irq_nb) {
> + dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq);
> + return;
> + }
> +
> + irq_domain_free_irqs_parent(domain, virq, nr_irqs);
> +
> + spin_lock(&sei->cp_msi_lock);
> + bitmap_release_region(sei->cp_msi_bitmap, d->hwirq, 0);
> + spin_unlock(&sei->cp_msi_lock);
> +}
> +
> +static const struct irq_domain_ops mvebu_sei_ap_domain_ops = {
> + .xlate = irq_domain_xlate_onecell,
> + .alloc = mvebu_sei_irq_domain_alloc,
> + .free = mvebu_sei_irq_domain_free,
> +};
> +
> +static const struct irq_domain_ops mvebu_sei_cp_domain_ops = {
> + .alloc = mvebu_sei_irq_domain_alloc,
> + .free = mvebu_sei_irq_domain_free,
> +};
> +
> +static struct irq_chip mvebu_sei_msi_irq_chip = {
> + .name = "SEI",
> + .irq_set_type = irq_chip_set_type_parent,
Same question here.
> +};
> +
> +static struct msi_domain_ops mvebu_sei_msi_ops = {
> +};
> +
> +static struct msi_domain_info mvebu_sei_msi_domain_info = {
> + .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS,
> + .ops = &mvebu_sei_msi_ops,
> + .chip = &mvebu_sei_msi_irq_chip,
> +};
> +
> +static void mvebu_sei_handle_cascade_irq(struct irq_desc *desc)
> +{
> + struct mvebu_sei *sei = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + unsigned long irqmap, irq_bit;
> + u32 reg_idx, virq, irqn;
> +
> + chained_irq_enter(chip, desc);
> +
> + /* Read both SEI cause registers (64 bits) */
> + for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) {
> + irqmap = readl_relaxed(sei->base + GICP_SECR(reg_idx));
> +
> + /* Call handler for each set bit */
> + for_each_set_bit(irq_bit, &irqmap, SEI_IRQ_COUNT_PER_REG) {
> + /* Cause Register gives the SEI number */
> + irqn = irq_bit + reg_idx * SEI_IRQ_COUNT_PER_REG;
> + /*
> + * Finding Linux mapping (virq) needs the right domain
> + * and the relative hwirq (which start at 0 in both
> + * cases, while irqn is relative to all SEI interrupts).
> + */
It is a bit odd that you're virtualizing the hwirq number. The whole
point of splitting hwirq from virq is that you don't have to do that and
can use the the raw HW number. You're saving a tiny bit of memory in the
irq_domain, at the expense of more complexity. I don't know if that's
worth it...
> + if (irqn < sei->ap_interrupts.number) {
> + virq = irq_find_mapping(sei->ap_domain, irqn);
> + } else {
> + irqn -= sei->ap_interrupts.number;
> + virq = irq_find_mapping(sei->cp_domain, irqn);
> + }
> +
> + /* Call IRQ handler */
> + generic_handle_irq(virq);
> + }
> +
> + /* Clear interrupt indication by writing 1 to it */
> + writel(irqmap, sei->base + GICP_SECR(reg_idx));
> + }
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> +static int mvebu_sei_probe(struct platform_device *pdev)
> +{
> + struct device_node *node = pdev->dev.of_node, *parent, *child;
> + struct irq_domain *parent_domain, *plat_domain;
> + struct mvebu_sei *sei;
> + const __be32 *property;
> + u32 parent_irq, size;
> + int ret;
> +
> + sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL);
> + if (!sei)
> + return -ENOMEM;
> +
> + sei->dev = &pdev->dev;
> +
> + spin_lock_init(&sei->cp_msi_lock);
> +
> + sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + sei->base = devm_ioremap_resource(sei->dev, sei->res);
> + if (!sei->base) {
> + dev_err(sei->dev, "Failed to remap SEI resource\n");
> + return -ENODEV;
> + }
> +
> + mvebu_sei_reset(sei);
> +
> + /*
> + * Reserve the single (top-level) parent SPI IRQ from which all the
> + * interrupts handled by this driver will be signaled.
> + */
> + parent_irq = irq_of_parse_and_map(node, 0);
> + if (parent_irq <= 0) {
> + dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n");
> + return -ENODEV;
> + }
> +
> + irq_set_chained_handler(parent_irq, mvebu_sei_handle_cascade_irq);
> + irq_set_handler_data(parent_irq, sei);
> +
> + /*
> + * SEIs in the range [ 0; 20] are wired and come from the AP.
> + * SEIs in the range [21; 63] are CP SEI and are triggered through MSIs.
> + *
> + * Each SEI 'domain' is represented as a subnode.
> + */
> +
> + /* Get a reference to the parent domain to create a hierarchy */
> + parent = of_irq_find_parent(node);
> + if (!parent) {
> + dev_err(sei->dev, "Failed to find parent IRQ node\n");
> + ret = -ENODEV;
> + goto dispose_irq;
> + }
> +
> + parent_domain = irq_find_host(parent);
> + if (!parent_domain) {
> + dev_err(sei->dev, "Failed to find parent IRQ domain\n");
> + ret = -ENODEV;
> + goto dispose_irq;
> + }
> +
> + /* Create the 'wired' hierarchy */
> + child = of_find_node_by_name(node, "sei-wired-controller");
> + if (!child) {
> + dev_err(sei->dev, "Missing 'sei-wired-controller' subnode\n");
> + ret = -ENODEV;
> + goto dispose_irq;
> + }
> +
> + property = of_get_property(child, "marvell,sei-ranges", &size);
> + if (!property || size != (2 * sizeof(u32))) {
> + dev_err(sei->dev, "Missing 'marvell,sei-ranges' property\n");
> + of_node_put(child);
> + ret = -ENODEV;
> + goto dispose_irq;
> + }
> +
> + sei->ap_interrupts.first = be32_to_cpu(property[0]);
> + sei->ap_interrupts.number = be32_to_cpu(property[1]);
> + sei->ap_domain = irq_domain_create_hierarchy(parent_domain, 0,
> + sei->ap_interrupts.number,
> + of_node_to_fwnode(child),
> + &mvebu_sei_ap_domain_ops,
> + sei);
> + of_node_put(child);
> + if (!sei->ap_domain) {
> + dev_err(sei->dev, "Failed to create AP IRQ domain\n");
> + ret = -ENOMEM;
> + goto dispose_irq;
> + }
> +
> + /* Create the 'MSI' hierarchy */
> + child = of_find_node_by_name(node, "sei-msi-controller");
> + if (!child) {
> + dev_err(sei->dev, "Missing 'sei-msi-controller' subnode\n");
> + ret = -ENODEV;
> + goto remove_ap_domain;
> + }
> +
> + property = of_get_property(child, "marvell,sei-ranges", &size);
> + if (!property || size != (2 * sizeof(u32))) {
> + dev_err(sei->dev, "Missing 'marvell,sei-ranges' property\n");
> + of_node_put(child);
> + ret = -ENODEV;
> + goto remove_ap_domain;
> + }
> +
> + sei->cp_interrupts.first = be32_to_cpu(property[0]);
> + sei->cp_interrupts.number = be32_to_cpu(property[1]);
> + sei->cp_domain = irq_domain_create_hierarchy(parent_domain, 0,
> + sei->cp_interrupts.number,
> + of_node_to_fwnode(child),
> + &mvebu_sei_cp_domain_ops,
> + sei);
> + if (!sei->cp_domain) {
> + pr_err("Failed to create CPs IRQ domain\n");
> + of_node_put(child);
> + ret = -ENOMEM;
> + goto remove_ap_domain;
> + }
> +
> + plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(child),
> + &mvebu_sei_msi_domain_info,
> + sei->cp_domain);
> + of_node_put(child);
> + if (!plat_domain) {
> + pr_err("Failed to create CPs MSI domain\n");
> + ret = -ENOMEM;
> + goto remove_cp_domain;
> + }
> +
> + platform_set_drvdata(pdev, sei);
> +
> + return 0;
> +
> +remove_cp_domain:
> + irq_domain_remove(sei->cp_domain);
> +remove_ap_domain:
> + irq_domain_remove(sei->ap_domain);
> +dispose_irq:
> + irq_dispose_mapping(parent_irq);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id mvebu_sei_of_match[] = {
> + { .compatible = "marvell,armada-8k-sei", },
> + {},
> +};
> +
> +static struct platform_driver mvebu_sei_driver = {
> + .probe = mvebu_sei_probe,
> + .driver = {
> + .name = "mvebu-sei",
> + .of_match_table = mvebu_sei_of_match,
> + },
> +};
> +builtin_platform_driver(mvebu_sei_driver);
>
It feels like this patch could do with a total split:
- Introduce the wired side of the driver
- then the MSI part
Drop the common domain callbacks, and treat the two domains separately.
I seriously doubt there will be much of an overlap anyway.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* v4.17-rc1: regressions on N900, N950
From: Pavel Machek @ 2018-05-23 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180522215638.GC2299@darkstar.musicnaut.iki.fi>
On Wed 2018-05-23 00:56:38, Aaro Koskinen wrote:
> Hi,
>
> On Tue, May 22, 2018 at 10:58:26PM +0200, Pavel Machek wrote:
> > On Tue 2018-05-22 22:41:39, Aaro Koskinen wrote:
> > > My device worked with v4.17-rc1 (haven't found time to test newer kernels),
> > > but if you say the probe order is random then we must find some proper way
> > > to express the dependency.
> >
> > I started bisect, but.. that will probably not be useful.
> >
> > If your device works ok in v4.17-rc1, it probably works in newer -rcs,
> > too.
>
> Actually, my statement may be bogus... Now I tried again with -rc1
> (and also -rc6) and it fails... But v4.16 works.
>
> > Thanks for the ordering hint, I'll try to figure out what is going on
> > there.
>
> My bisection pointed to 6fa7324ac5489ad43c4b6351355b869bc5458bef which
> doesn't seem to make any sense...?! So maybe there really is something
> random stuff going on? :-(
So... I did some experiments on v4.16.
Swapping tsc2005 at 0 and lcd: acx565akm at 2 entries in the dts does break
stuff.
I thought it might be due to vio regulator, but it does not appear
so... screen still works with tsc2005 driver disabled in .config. (so
there's noone to enable vio regulator).
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [PATCH 07/24] arm64: ilp32: add documentation on the ILP32 ABI for ARM64
From: Pavel Machek @ 2018-05-23 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516081910.10067-8-ynorov@caviumnetworks.com>
On Wed 2018-05-16 11:18:52, Yury Norov wrote:
> Based on Andrew Pinski's patch-series.
>
> Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
So Andrew's signoff should be here?
> ---
> Documentation/arm64/ilp32.txt | 45 +++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/arm64/ilp32.txt
>
> diff --git a/Documentation/arm64/ilp32.txt b/Documentation/arm64/ilp32.txt
> new file mode 100644
> index 000000000000..d0fd5109c4b2
> --- /dev/null
> +++ b/Documentation/arm64/ilp32.txt
> @@ -0,0 +1,45 @@
> +ILP32 AARCH64 SYSCALL ABI
> +=========================
> +
> +This document describes the ILP32 syscall ABI and where it differs
> +from the generic compat linux syscall interface.
I was hoping to learn what ILP32 is / what is it good for, but no,
this does not tell me... it would be good to do a short explanation
here, and maybe reference it from cover letter of the series...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [PATCH v2 4/7] Bluetooth: Add new quirk for non-persistent setup settings
From: Sean Wang @ 2018-05-23 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <B82BB5F4-E197-4915-A543-C5FF9A5A41F1@holtmann.org>
On Wed, 2018-05-23 at 14:31 +0200, Marcel Holtmann wrote:
> Hi Sean,
>
> >>
> >> [ ... ]
> >>
> >>>> - if (hci_dev_test_flag(hdev, HCI_SETUP)) {
> >>>> + if (hci_dev_test_flag(hdev, HCI_SETUP) ||
> >>>> + test_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks)) {
> >>>> hci_sock_dev_event(hdev, HCI_DEV_SETUP);
> >>>
> >>> I am not 100% sure that we want to send the HCI_DEV_SETUP event also multiple times. That is a userspace change that I would need to think about. We need to check create_monitor_event() and see what the btmon trace for this looks like. Can you send me a btmon -w trace.log when this change is active.
> >>>
> >>> Regards
> >>>
> >>> Marcel
> >>>
> >>
> >> Sure, I'll send you the trace.log with the change is active.
> >>
> >> Sean
> >>
> >
> >
> > Attached trace.log was captured when I inputted commands power on and
> > then off in bluetoothctl.
>
> the trace.log is somehow mangled. Something is not fully correct. Can you read it with btmon -r trace.log?
>
> Regards
>
> Marcel
>
Yes, I can read it with btmon -r trace.log.
I post it as plain text as below
Bluetooth monitor ver 5.37
= Note: Linux version 4.16.0-rc1+ (aarch64) 0.641494
= Note: Bluetooth subsystem version 2.22 0.641502
= New Index: 00:00:46:76:22:01 (BR/EDR,UART,hci0) [hci0] 0.641505
* Unknown packet (code 14 len 30) 0.641509
01 00 00 00 02 00 01 0e 00 01 00 00 00 10 62 6c ..............bl
75 65 74 6f 6f 74 68 64 00 00 00 00 00 00 uetoothd......
* Unknown packet (code 14 len 30) 0.641592
02 00 00 00 02 00 01 0e 00 01 00 00 00 10 62 74 ..............bt
6d 6f 6e 00 00 00 00 00 00 00 00 00 00 00 mon...........
* Unknown packet (code 16 len 7) [hci0] 6.536771
01 00 00 00 05 00 01 .......
= Open Index: 00:00:46:76:22:01 [hci0] 6.717019
= Index Info: 00:00:46:76:22:01 (MediaTek, Inc.) [hci0] 6.717030
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.741093
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.742088
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.743102
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.744105
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.745109
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.746104
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.747097
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.748090
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.749078
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.750070
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.751061
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.752054
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.753046
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.754038
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.755031
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.756025
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.757013
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.758006
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.758999
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.759991
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.760983
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.761975
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.762963
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.763956
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.764948
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.765941
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.766933
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.767926
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.768919
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.769914
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.770909
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.771908
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.772904
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.773898
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.774892
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.775890
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.776882
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.777877
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.778871
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.779869
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.780864
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.781858
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.782852
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.783850
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.784845
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.785839
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.786833
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.787831
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.788826
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.789820
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.790814
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.791813
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.792809
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.793803
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.794798
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.795797
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.796791
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.797786
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.798779
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.799778
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.800774
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.801769
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.802763
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.803761
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.804755
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.805749
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.806743
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.807741
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.808737
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.809731
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.810725
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.811725
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.812719
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.813714
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.814708
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.815705
02 01 01 00 00 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.816378
02 01 01 00 00 .....
< HCI Command: Vendor (0x3f|0x006f) plen 5 [hci0] 6.816413
01 07 01 00 04 .....
> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.816536
02 07 01 00 00 .....
< HCI Command: Vendor (0x3f|0x006f) plen 6 [hci0] 8.845071
01 06 02 00 00 01 ......
> HCI Event: Unknown (0xe4) plen 5 [hci0] 8.923456
02 06 01 00 00 .....
< HCI Command: Reset (0x03|0x0003) plen 0 [hci0] 10.861118
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.865763
Reset (0x03|0x0003) ncmd 1
Status: Success (0x00)
< HCI Command: Read Local Supported Fe.. (0x04|0x0003) plen 0 [hci0] 10.865805
> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.865965
Read Local Supported Features (0x04|0x0003) ncmd 1
Status: Success (0x00)
Features: 0xbf 0x3e 0x8d 0xfe 0xdb 0xff 0x7b 0x87
3 slot packets
5 slot packets
Encryption
Slot offset
Timing accuracy
Role switch
Sniff mode
Power control requests
Channel quality driven data rate (CQDDR)
SCO link
HV2 packets
HV3 packets
CVSD synchronous data
Power control
Transparent synchronous data
Broadcast Encryption
Enhanced Data Rate ACL 2 Mbps mode
Enhanced Data Rate ACL 3 Mbps mode
Enhanced inquiry scan
Interlaced inquiry scan
Interlaced page scan
RSSI with inquiry results
Extended SCO link (EV3 packets)
EV4 packets
EV5 packets
AFH capable slave
AFH classification slave
LE Supported (Controller)
3-slot Enhanced Data Rate ACL packets
5-slot Enhanced Data Rate ACL packets
Sniff subrating
Pause encryption
AFH capable master
AFH classification master
Enhanced Data Rate eSCO 2 Mbps mode
Enhanced Data Rate eSCO 3 Mbps mode
3-slot Enhanced Data Rate eSCO packets
Extended Inquiry Response
Simultaneous LE and BR/EDR (Controller)
Secure Simple Pairing
Encapsulated PDU
Erroneous Data Reporting
Non-flushable Packet Boundary Flag
Link Supervision Timeout Changed Event
Inquiry TX Power Level
Enhanced Power Control
Extended features
< HCI Command: Read Local Version Info.. (0x04|0x0001) plen 0 [hci0] 10.865987
> HCI Event: Vendor (0xff) plen 9 [hci0] 10.866259
29 19 09 17 20 48 07 11 00 )... H...
> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.866372
Read Local Version Information (0x04|0x0001) ncmd 1
Status: Success (0x00)
HCI version: Bluetooth 4.2 (0x08) - Revision 4359 (0x1107)
LMP version: Bluetooth 4.2 (0x08) - Subversion 2329 (0x0919)
Manufacturer: MediaTek, Inc. (70)
< HCI Command: Read BD ADDR (0x04|0x0009) plen 0 [hci0] 10.866391
> HCI Event: Command Complete (0x0e) plen 10 [hci0] 10.866539
Read BD ADDR (0x04|0x0009) ncmd 1
Status: Success (0x00)
Address: 00:00:46:76:22:01 (OLIVETTI NORTH AMERICA)
< HCI Command: Read Buffer Size (0x04|0x0005) plen 0 [hci0] 10.866609
> HCI Event: Command Complete (0x0e) plen 11 [hci0] 10.866754
Read Buffer Size (0x04|0x0005) ncmd 1
Status: Success (0x00)
ACL MTU: 1021 ACL max packet: 8
SCO MTU: 184 SCO max packet: 1
< HCI Command: Read Class of Device (0x03|0x0023) plen 0 [hci0] 10.866775
> HCI Event: Command Complete (0x0e) plen 7 [hci0] 10.866920
Read Class of Device (0x03|0x0023) ncmd 1
Status: Success (0x00)
Class: 0x001f00
Major class: Uncategorized, specific device code not specified
Minor class: 0x00
< HCI Command: Read Local Name (0x03|0x0014) plen 0 [hci0] 10.866939
> HCI Event: Command Complete (0x0e) plen 252 [hci0] 10.867256
Read Local Name (0x03|0x0014) ncmd 1
Status: Success (0x00)
Name: MTK MT7622 #1
< HCI Command: Read Voice Setting (0x03|0x0025) plen 0 [hci0] 10.867308
> HCI Event: Command Complete (0x0e) plen 6 [hci0] 10.867447
Read Voice Setting (0x03|0x0025) ncmd 1
Status: Success (0x00)
Setting: 0x0060
Input Coding: Linear
Input Data Format: 2's complement
Input Sample Size: 16-bit
# of bits padding at MSB: 0
Air Coding Format: CVSD
< HCI Command: Read Number of Supporte.. (0x03|0x0038) plen 0 [hci0] 10.867474
> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.867611
Read Number of Supported IAC (0x03|0x0038) ncmd 1
Status: Success (0x00)
Number of IAC: 4
< HCI Command: Read Current IAC LAP (0x03|0x0039) plen 0 [hci0] 10.867678
> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.867865
Read Current IAC LAP (0x03|0x0039) ncmd 1
Status: Success (0x00)
Number of IAC: 1
Access code: 0x9e8b33 (General Inquiry)
< HCI Command: Set Event Filter (0x03|0x0005) plen 1 [hci0] 10.867890
Type: Clear All Filters (0x00)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.868033
Set Event Filter (0x03|0x0005) ncmd 1
Status: Success (0x00)
< HCI Command: Write Connection Accept.. (0x03|0x0016) plen 2 [hci0] 10.868054
Timeout: 20000.000 msec (0x7d00)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.868235
Write Connection Accept Timeout (0x03|0x0016) ncmd 1
Status: Success (0x00)
< HCI Command: LE Read Buffer Size (0x08|0x0002) plen 0 [hci0] 10.868262
> HCI Event: Command Complete (0x0e) plen 7 [hci0] 10.868392
LE Read Buffer Size (0x08|0x0002) ncmd 1
Status: Success (0x00)
Data packet length: 251
Num data packets: 8
< HCI Command: LE Read Local Supported.. (0x08|0x0003) plen 0 [hci0] 10.868413
> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.868587
LE Read Local Supported Features (0x08|0x0003) ncmd 1
Status: Success (0x00)
Features: 0xfd 0x00 0x00 0x00 0x00 0x00 0x00 0x00
LE Encryption
Extended Reject Indication
Slave-initiated Features Exchange
LE Ping
LE Data Packet Length Extension
LL Privacy
Extended Scanner Filter Policies
< HCI Command: LE Read Supported States (0x08|0x001c) plen 0 [hci0] 10.868646
> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.868787
LE Read Supported States (0x08|0x001c) ncmd 1
Status: Success (0x00)
States: 0x000000001fffffff
Non-connectable Advertising State
Scannable Advertising State
Connectable Advertising State
High Duty Cycle Directed Advertising State
Passive Scanning State
Active Scanning State
Initiating State
and Connection State (Master Role)
Connection State (Slave Role)
Non-connectable Advertising State
and Passive Scanning State
Scannable Advertising State
and Passive Scanning State
Connectable Advertising State
and Passive Scanning State
High Duty Cycle Directed Advertising State
and Passive Scanning State
Non-connectable Advertising State
and Active Scanning State
Scannable Advertising State
and Active Scanning State
Connectable Advertising State
and Active Scanning State
High Duty Cycle Directed Advertising State
and Active Scanning State
Non-connectable Advertising State
and Initiating State
Scannable Advertising State
and Initiating State
Non-connectable Advertising State
and Connection State (Master Role)
Scannable Advertising State
and Connection State (Master Role)
Non-connectable Advertising State
and Connection State (Slave Role)
Scannable Advertising State
and Connection State (Slave Role)
Passive Scanning State
and Initiating State
Active Scanning State
and Initiating State
Passive Scanning State
and Connection State (Master Role)
Active Scanning State
and Connection State (Master Role)
Passive Scanning State
and Connection State (Slave Role)
Active Scanning State
and Connection State (Slave Role)
Initiating State
and Connection State (Master Role)
and Master Role & Master Role
< HCI Command: Read Local Supported Co.. (0x04|0x0002) plen 0 [hci0] 10.868807
> HCI Event: Command Complete (0x0e) plen 68 [hci0] 10.868985
Read Local Supported Commands (0x04|0x0002) ncmd 1
Status: Success (0x00)
Commands: 176 entries
Inquiry (Octet 0 - Bit 0)
Inquiry Cancel (Octet 0 - Bit 1)
Periodic Inquiry Mode (Octet 0 - Bit 2)
Exit Periodic Inquiry Mode (Octet 0 - Bit 3)
Create Connection (Octet 0 - Bit 4)
Disconnect (Octet 0 - Bit 5)
Add SCO Connection (Octet 0 - Bit 6)
Create Connection Cancel (Octet 0 - Bit 7)
Accept Connection Request (Octet 1 - Bit 0)
Reject Connection Request (Octet 1 - Bit 1)
Link Key Request Reply (Octet 1 - Bit 2)
Link Key Request Negative Reply (Octet 1 - Bit 3)
PIN Code Request Reply (Octet 1 - Bit 4)
PIN Code Request Negative Reply (Octet 1 - Bit 5)
Change Connection Packet Type (Octet 1 - Bit 6)
Authentication Requested (Octet 1 - Bit 7)
Set Connection Encryption (Octet 2 - Bit 0)
Change Connection Link Key (Octet 2 - Bit 1)
Master Link Key (Octet 2 - Bit 2)
Remote Name Request (Octet 2 - Bit 3)
Remote Name Request Cancel (Octet 2 - Bit 4)
Read Remote Supported Features (Octet 2 - Bit 5)
Read Remote Extended Features (Octet 2 - Bit 6)
Read Remote Version Information (Octet 2 - Bit 7)
Read Clock Offset (Octet 3 - Bit 0)
Read LMP Handle (Octet 3 - Bit 1)
Sniff Mode (Octet 4 - Bit 2)
Exit Sniff Mode (Octet 4 - Bit 3)
QoS Setup (Octet 4 - Bit 6)
Role Discovery (Octet 4 - Bit 7)
Switch Role (Octet 5 - Bit 0)
Read Link Policy Settings (Octet 5 - Bit 1)
Write Link Policy Settings (Octet 5 - Bit 2)
Read Default Link Policy Settings (Octet 5 - Bit 3)
Write Default Link Policy Settings (Octet 5 - Bit 4)
Flow Specification (Octet 5 - Bit 5)
Set Event Mask (Octet 5 - Bit 6)
Reset (Octet 5 - Bit 7)
Set Event Filter (Octet 6 - Bit 0)
Flush (Octet 6 - Bit 1)
Read PIN Type (Octet 6 - Bit 2)
Write PIN Type (Octet 6 - Bit 3)
Create New Unit Key (Octet 6 - Bit 4)
Read Stored Link Key (Octet 6 - Bit 5)
Write Stored Link Key (Octet 6 - Bit 6)
Delete Stored Link Key (Octet 6 - Bit 7)
Write Local Name (Octet 7 - Bit 0)
Read Local Name (Octet 7 - Bit 1)
Read Connection Accept Timeout (Octet 7 - Bit 2)
Write Connection Accept Timeout (Octet 7 - Bit 3)
Read Page Timeout (Octet 7 - Bit 4)
Write Page Timeout (Octet 7 - Bit 5)
Read Scan Enable (Octet 7 - Bit 6)
Write Scan Enable (Octet 7 - Bit 7)
Read Page Scan Activity (Octet 8 - Bit 0)
Write Page Scan Activity (Octet 8 - Bit 1)
Read Inquiry Scan Activity (Octet 8 - Bit 2)
Write Inquiry Scan Activity (Octet 8 - Bit 3)
Read Authentication Enable (Octet 8 - Bit 4)
Write Authentication Enable (Octet 8 - Bit 5)
Read Encryption Mode (Octet 8 - Bit 6)
Write Encryption Mode (Octet 8 - Bit 7)
Read Class of Device (Octet 9 - Bit 0)
Write Class of Device (Octet 9 - Bit 1)
Read Voice Setting (Octet 9 - Bit 2)
Write Voice Setting (Octet 9 - Bit 3)
Read Automatic Flush Timeout (Octet 9 - Bit 4)
Write Automatic Flush Timeout (Octet 9 - Bit 5)
Read Num Broadcast Retransmissions (Octet 9 - Bit 6)
Write Num Broadcast Retransmissions (Octet 9 - Bit 7)
Read Transmit Power Level (Octet 10 - Bit 2)
Read Sync Flow Control Enable (Octet 10 - Bit 3)
Write Sync Flow Control Enable (Octet 10 - Bit 4)
Set Controller To Host Flow Control (Octet 10 - Bit 5)
Host Buffer Size (Octet 10 - Bit 6)
Host Number of Completed Packets (Octet 10 - Bit 7)
Read Link Supervision Timeout (Octet 11 - Bit 0)
Write Link Supervision Timeout (Octet 11 - Bit 1)
Read Number of Supported IAC (Octet 11 - Bit 2)
Read Current IAC LAP (Octet 11 - Bit 3)
Write Current IAC LAP (Octet 11 - Bit 4)
Read Page Scan Mode (Octet 11 - Bit 7)
Write Page Scan Mode (Octet 12 - Bit 0)
Set AFH Host Channel Classification (Octet 12 - Bit 1)
Read Inquiry Scan Type (Octet 12 - Bit 4)
Write Inquiry Scan Type (Octet 12 - Bit 5)
Read Inquiry Mode (Octet 12 - Bit 6)
Write Inquiry Mode (Octet 12 - Bit 7)
Read Page Scan Type (Octet 13 - Bit 0)
Write Page Scan Type (Octet 13 - Bit 1)
Read AFH Channel Assessment Mode (Octet 13 - Bit 2)
Write AFH Channel Assessment Mode (Octet 13 - Bit 3)
Read Local Version Information (Octet 14 - Bit 3)
Read Local Supported Features (Octet 14 - Bit 5)
Read Local Extended Features (Octet 14 - Bit 6)
Read Buffer Size (Octet 14 - Bit 7)
Read Country Code (Octet 15 - Bit 0)
Read BD ADDR (Octet 15 - Bit 1)
Read Failed Contact Counter (Octet 15 - Bit 2)
Reset Failed Contact Counter (Octet 15 - Bit 3)
Read Link Quality (Octet 15 - Bit 4)
Read RSSI (Octet 15 - Bit 5)
Read AFH Channel Map (Octet 15 - Bit 6)
Read Clock (Octet 15 - Bit 7)
Read Loopback Mode (Octet 16 - Bit 0)
Write Loopback Mode (Octet 16 - Bit 1)
Enable Device Under Test Mode (Octet 16 - Bit 2)
Setup Synchronous Connection (Octet 16 - Bit 3)
Accept Synchronous Connection Request (Octet 16 - Bit 4)
Reject Synchronous Connection Request (Octet 16 - Bit 5)
Read Extended Inquiry Response (Octet 17 - Bit 0)
Write Extended Inquiry Response (Octet 17 - Bit 1)
Refresh Encryption Key (Octet 17 - Bit 2)
Sniff Subrating (Octet 17 - Bit 4)
Read Simple Pairing Mode (Octet 17 - Bit 5)
Write Simple Pairing Mode (Octet 17 - Bit 6)
Read Local OOB Data (Octet 17 - Bit 7)
Read Inquiry Response TX Power Level (Octet 18 - Bit 0)
Write Inquiry Transmit Power Level (Octet 18 - Bit 1)
Read Default Erroneous Data Reporting (Octet 18 - Bit 2)
Write Default Erroneous Data Reporting (Octet 18 - Bit 3)
IO Capability Request Reply (Octet 18 - Bit 7)
User Confirmation Request Reply (Octet 19 - Bit 0)
User Confirmation Request Neg Reply (Octet 19 - Bit 1)
User Passkey Request Reply (Octet 19 - Bit 2)
User Passkey Request Negative Reply (Octet 19 - Bit 3)
Remote OOB Data Request Reply (Octet 19 - Bit 4)
Write Simple Pairing Debug Mode (Octet 19 - Bit 5)
Enhanced Flush (Octet 19 - Bit 6)
Remote OOB Data Request Neg Reply (Octet 19 - Bit 7)
Send Keypress Notification (Octet 20 - Bit 2)
IO Capability Request Negative Reply (Octet 20 - Bit 3)
Read Encryption Key Size (Octet 20 - Bit 4)
Set Event Mask Page 2 (Octet 22 - Bit 2)
Read Enhanced Transmit Power Level (Octet 24 - Bit 0)
Enhanced Setup Synchronous Connection (Octet 29 - Bit 3)
Enhanced Accept Synchronous Connection Request (Octet 29 - Bit 4)
Read Local Supported Codecs (Octet 29 - Bit 5)
Set Triggered Clock Capture (Octet 30 - Bit 5)
Truncated Page (Octet 30 - Bit 6)
Truncated Page Cancel (Octet 30 - Bit 7)
Set Connectionless Slave Broadcast (Octet 31 - Bit 0)
Start Synchronization Train (Octet 31 - Bit 2)
Set Reserved LT_ADDR (Octet 31 - Bit 4)
Delete Reserved LT_ADDR (Octet 31 - Bit 5)
Set Connectionless Slave Broadcast Data (Octet 31 - Bit 6)
Read Synchronization Train Parameters (Octet 31 - Bit 7)
Write Synchronization Train Parameters (Octet 32 - Bit 0)
Remote OOB Extended Data Request Reply (Octet 32 - Bit 1)
Read Authenticated Payload Timeout (Octet 32 - Bit 4)
Write Authenticated Payload Timeout (Octet 32 - Bit 5)
Read Local OOB Extended Data (Octet 32 - Bit 6)
Write Secure Connections Test Mode (Octet 32 - Bit 7)
Read Extended Page Timeout (Octet 33 - Bit 0)
Write Extended Page Timeout (Octet 33 - Bit 1)
Read Extended Inquiry Length (Octet 33 - Bit 2)
Write Extended Inquiry Length (Octet 33 - Bit 3)
LE Set Data Length (Octet 33 - Bit 6)
LE Read Suggested Default Data Length (Octet 33 - Bit 7)
LE Write Suggested Default Data Length (Octet 34 - Bit 0)
LE Read Local P-256 Public Key (Octet 34 - Bit 1)
LE Generate DHKey (Octet 34 - Bit 2)
LE Add Device To Resolving List (Octet 34 - Bit 3)
LE Remove Device From Resolving List (Octet 34 - Bit 4)
LE Clear Resolving List (Octet 34 - Bit 5)
LE Read Resolving List Size (Octet 34 - Bit 6)
LE Read Peer Resolvable Address (Octet 34 - Bit 7)
LE Read Local Resolvable Address (Octet 35 - Bit 0)
LE Set Address Resolution Enable (Octet 35 - Bit 1)
LE Set Resolvable Private Address Timeout (Octet 35 - Bit 2)
LE Read Maximum Data Length (Octet 35 - Bit 3)
Octet 35 - Bit 4
Octet 35 - Bit 5
Octet 35 - Bit 6
Octet 35 - Bit 7
Octet 36 - Bit 0
< HCI Command: Write Simple Pairing Mode (0x03|0x0056) plen 1 [hci0] 10.869023
Mode: Enabled (0x01)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869185
Write Simple Pairing Mode (0x03|0x0056) ncmd 1
Status: Success (0x00)
< HCI Command: Write Inquiry Mode (0x03|0x0045) plen 1 [hci0] 10.869239
Mode: Inquiry Result with RSSI or Extended Inquiry Result (0x02)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869371
Write Inquiry Mode (0x03|0x0045) ncmd 1
Status: Success (0x00)
< HCI Command: Read Inquiry Response T.. (0x03|0x0058) plen 0 [hci0] 10.869396
> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.869552
Read Inquiry Response TX Power Level (0x03|0x0058) ncmd 1
Status: Success (0x00)
TX power: -1 dBm
< HCI Command: Read Local Extended Fea.. (0x04|0x0004) plen 1 [hci0] 10.869572
Page: 1
> HCI Event: Command Complete (0x0e) plen 14 [hci0] 10.869729
Read Local Extended Features (0x04|0x0004) ncmd 1
Status: Success (0x00)
Page: 1/2
Features: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Secure Simple Pairing (Host Support)
< HCI Command: Set Event Mask (0x03|0x0001) plen 8 [hci0] 10.869783
Mask: 0x3dbff807fffbffff
Inquiry Complete
Inquiry Result
Connection Complete
Connection Request
Disconnection Complete
Authentication Complete
Remote Name Request Complete
Encryption Change
Change Connection Link Key Complete
Master Link Key Complete
Read Remote Supported Features Complete
Read Remote Version Information Complete
QoS Setup Complete
Command Complete
Command Status
Hardware Error
Flush Occurred
Role Change
Mode Change
Return Link Keys
PIN Code Request
Link Key Request
Link Key Notification
Loopback Command
Data Buffer Overflow
Max Slots Change
Read Clock Offset Complete
Connection Packet Type Changed
QoS Violation
Page Scan Mode Change
Page Scan Repetition Mode Change
Flow Specification Complete
Inquiry Result with RSSI
Read Remote Extended Features Complete
Synchronous Connection Complete
Synchronous Connection Changed
Sniff Subrating
Extended Inquiry Result
Encryption Key Refresh Complete
IO Capability Request
IO Capability Request Reply
User Confirmation Request
User Passkey Request
Remote OOB Data Request
Simple Pairing Complete
Link Supervision Timeout Changed
Enhanced Flush Complete
User Passkey Notification
Keypress Notification
Remote Host Supported Features Notification
LE Meta
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869921
Set Event Mask (0x03|0x0001) ncmd 1
Status: Success (0x00)
< HCI Command: Read Stored Link Key (0x03|0x000d) plen 7 [hci0] 10.869947
Address: 00:00:00:00:00:00 (OUI 00-00-00)
Read all: 0x01
> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.870129
Read Stored Link Key (0x03|0x000d) ncmd 1
Status: Success (0x00)
Max num keys: 4
Num keys: 0
< HCI Command: Write Default Link Poli.. (0x02|0x000f) plen 2 [hci0] 10.870148
Link policy: 0x0005
Enable Role Switch
Enable Sniff Mode
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.870310
Write Default Link Policy Settings (0x02|0x000f) ncmd 1
Status: Success (0x00)
< HCI Command: Read Page Scan Activity (0x03|0x001b) plen 0 [hci0] 10.870331
> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.870485
Read Page Scan Activity (0x03|0x001b) ncmd 1
Status: Success (0x00)
Interval: 1280.000 msec (0x0800)
Window: 11.250 msec (0x0012)
< HCI Command: Read Page Scan Type (0x03|0x0046) plen 0 [hci0] 10.870504
> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.870652
Read Page Scan Type (0x03|0x0046) ncmd 1
Status: Success (0x00)
Type: Standard Scan (0x00)
< HCI Command: LE Set Event Mask (0x08|0x0001) plen 8 [hci0] 10.870671
Mask: 0x0000000000000980
LE Read Local P-256 Public Key Complete
LE Generate DHKey Complete
Unknown mask (0x0000000000000800)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.870839
LE Set Event Mask (0x08|0x0001) ncmd 1
Status: Success (0x00)
< HCI Command: Write LE Host Supported (0x03|0x006d) plen 2 [hci0] 10.870859
Supported: 0x01
Simultaneous: 0x00
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.871028
Write LE Host Supported (0x03|0x006d) ncmd 1
Status: Success (0x00)
< HCI Command: Read Local Extended Fea.. (0x04|0x0004) plen 1 [hci0] 10.871059
Page: 2
> HCI Event: Command Complete (0x0e) plen 14 [hci0] 10.871201
Read Local Extended Features (0x04|0x0004) ncmd 1
Status: Success (0x00)
Page: 2/2
Features: 0x25 0x0b 0x00 0x00 0x00 0x00 0x00 0x00
Connectionless Slave Broadcast - Master
Synchronization Train
Generalized interlaced scan
Secure Connections (Controller Support)
Ping
Train nudging
< HCI Command: Delete Stored Link Key (0x03|0x0012) plen 7 [hci0] 10.871240
Address: 00:00:00:00:00:00 (OUI 00-00-00)
Delete all: 0x01
> HCI Event: Command Complete (0x0e) plen 6 [hci0] 10.871384
Delete Stored Link Key (0x03|0x0012) ncmd 1
Status: Success (0x00)
Num keys: 0
< HCI Command: Set Event Mask Page 2 (0x03|0x0063) plen 8 [hci0] 10.871403
Mask: 0x0000000000b0c000
Triggered Clock Capture
Synchronization Train Complete
Slave Page Response Timeout
Connectionless Slave Broadcast Channel Map Change
Authenticated Payload Timeout Expired
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.871566
Set Event Mask Page 2 (0x03|0x0063) ncmd 1
Status: Success (0x00)
< HCI Command: Read Local Supported Co.. (0x04|0x000b) plen 0 [hci0] 10.871599
> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.871750
Read Local Supported Codecs (0x04|0x000b) ncmd 1
Status: Success (0x00)
Number of supported codecs: 2
Codec: CVSD (0x02)
Codec: Transparent (0x03)
Number of vendor codecs: 0
< HCI Command: Read Synchronization Tr.. (0x03|0x0077) plen 0 [hci0] 10.871769
> HCI Event: Command Complete (0x0e) plen 11 [hci0] 10.871928
Read Synchronization Train Parameters (0x03|0x0077) ncmd 1
Status: Success (0x00)
Interval: 0.000 msec (0x0000)
Timeout: 0.000 msec (0x00000000)
Service data: 0x00
< HCI Command: Write Secure Connection.. (0x03|0x007a) plen 1 [hci0] 10.871947
Support: Enabled (0x01)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872098
Write Secure Connections Host Support (0x03|0x007a) ncmd 1
Status: Success (0x00)
< HCI Command: Unknown (0x08|0x0031) plen 3 [hci0] 10.872156
03 00 00 ...
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872322
Unknown (0x08|0x0031) ncmd 1
Status: Success (0x00)
= Index Info: 00:00:46:76:22:01 (MediaTek, Inc.) [hci0] 10.872361
< HCI Command: LE Set Scan Response D.. (0x08|0x0009) plen 32 [hci0] 10.872431
Length: 10
Name (complete): builder
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872606
LE Set Scan Response Data (0x08|0x0009) ncmd 1
Status: Success (0x00)
< HCI Command: Write Scan Enable (0x03|0x001a) plen 1 [hci0] 10.872627
Scan enable: Page Scan (0x02)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872819
Write Scan Enable (0x03|0x001a) ncmd 1
Status: Success (0x00)
< HCI Command: Write Class of Device (0x03|0x0024) plen 3 [hci0] 10.872841
Class: 0x000000
Major class: Miscellaneous
Minor class: 0x00
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873036
Write Class of Device (0x03|0x0024) ncmd 1
Status: Success (0x00)
* Unknown packet (code 17 len 9) [hci0] 10.873069
02 00 00 00 07 00 00 00 00 .........
* Unknown packet (code 17 len 9) [hci0] 10.873069
01 00 00 00 07 00 00 00 00 .........
< HCI Command: Write Local Name (0x03|0x0013) plen 248 [hci0] 10.873096
Name: builder
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873446
Write Local Name (0x03|0x0013) ncmd 1
Status: Success (0x00)
< HCI Command: Write Extended Inquir.. (0x03|0x0052) plen 241 [hci0] 10.873470
FEC: Not required (0x00)
Name (complete): builder
TX power: -1 dBm
Device ID: USB Implementer's Forum assigned (0x0002)
Vendor: Linux Foundation (0x1d6b)
Product: 0x0246
Version: 5.2.11 (0x052b)
16-bit Service UUIDs (complete): 4 entries
Generic Access Profile (0x1800)
Generic Attribute Profile (0x1801)
A/V Remote Control (0x110e)
A/V Remote Control Target (0x110c)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873857
Write Extended Inquiry Response (0x03|0x0052) ncmd 1
Status: Success (0x00)
* Unknown packet (code 17 len 13) [hci0] 10.873903
01 00 00 00 01 00 05 00 00 d1 0a 00 00 .............
* Unknown packet (code 17 len 10) [hci0] 10.873913
02 00 00 00 06 00 d1 0a 00 00 ..........
* Unknown packet (code 16 len 7) [hci0] 17.803939
01 00 00 00 05 00 00 .......
< HCI Command: Write Scan Enable (0x03|0x001a) plen 1 [hci0] 17.803983
Scan enable: No Scans (0x00)
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 17.804233
Write Scan Enable (0x03|0x001a) ncmd 1
Status: Success (0x00)
< HCI Command: Vendor (0x3f|0x006f) plen 6 [hci0] 17.804282
01 06 02 00 00 00 ......
> HCI Event: Unknown (0xe4) plen 5 [hci0] 17.804636
02 06 01 00 00 .....
* Unknown packet (code 17 len 13) [hci0] 17.811580
01 00 00 00 01 00 05 00 00 d0 0a 00 00 .............
* Unknown packet (code 17 len 10) [hci0] 17.811596
02 00 00 00 06 00 d0 0a 00 00 ..........
= Close Index: 00:00:46:76:22:01 [hci0] 17.811625
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