* [PATCHv5 7/8] defconfig: enable fpga and service layer
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Richard Gong <richard.gong@intel.com>
Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10
Service Layer
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
---
v2: this patch is added in patch set version 2
v3: no change
v4: s/CONFIG_INTEL_SERVICE/CONFIG_STRATIX10_SERVICE/
add CONFIG_OF_FPGA_REGION=y
s/Intel/Stratix10/ in subject line
v5: no change
---
arch/arm64/configs/defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecf6137..5f7a9b7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -180,6 +180,7 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=m
+CONFIG_STRATIX10_SERVICE=y
CONFIG_SRAM=y
CONFIG_EEPROM_AT25=m
# CONFIG_SCSI_PROC_FS is not set
@@ -595,6 +596,11 @@ CONFIG_PHY_TEGRA_XUSB=y
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_MESON_EFUSE=m
+CONFIG_FPGA=y
+CONFIG_FPGA_MGR_STRATIX10_SOC=y
+CONFIG_FPGA_REGION=y
+CONFIG_FPGA_BRIDGE=y
+CONFIG_OF_FPGA_REGION=y
CONFIG_QCOM_QFPROM=y
CONFIG_UNIPHIER_EFUSE=y
CONFIG_TEE=y
--
2.7.4
^ permalink raw reply related
* [PATCHv5 6/8] fpga: add intel stratix10 soc fpga manager driver
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Alan Tull <atull@kernel.org>
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel Service Driver which
does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
---
v2: this patch is added in patch set version 2
v3: change to align to the update of service client APIs, and the
update of fpga_mgr device node
v4: changes to align with stratix10-svc-client API updates
add Richard's signed-off-by
v5: update to align changes at service layer to minimize service
layer thread usages
---
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/stratix10-soc.c | 545 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 552 insertions(+)
create mode 100644 drivers/fpga/stratix10-soc.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index f47ef84..1624a73 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -57,6 +57,12 @@ config FPGA_MGR_ZYNQ_FPGA
help
FPGA manager driver support for Xilinx Zynq FPGAs.
+config FPGA_MGR_STRATIX10_SOC
+ tristate "Intel Stratix10 SoC FPGA Manager"
+ depends on (ARCH_STRATIX10 && STRATIX10_SERVICE)
+ help
+ FPGA manager driver support for the Intel Stratix10 SoC.
+
config FPGA_MGR_XILINX_SPI
tristate "Xilinx Configuration over Slave Serial (SPI)"
depends on SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 3cb276a..6eef670 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
new file mode 100644
index 0000000..d645ef7
--- /dev/null
+++ b/drivers/fpga/stratix10-soc.c
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * FPGA Manager Driver for Intel Stratix10 SoC
+ *
+ * Copyright (C) 2018 Intel Corporation
+ */
+#include <linux/completion.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/stratix10-svc-client.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+/*
+ * FPGA programming requires a higher level of privilege (EL3), per the SoC
+ * design.
+ */
+#define NUM_SVC_BUFS 4
+#define SVC_BUF_SIZE SZ_512K
+
+/* Indicates buffer is in use if set */
+#define SVC_BUF_LOCK 0
+
+/**
+ * struct s10_svc_buf
+ * @buf: virtual address of buf provided by service layer
+ * @lock: locked if buffer is in use
+ */
+struct s10_svc_buf {
+ char *buf;
+ unsigned long lock;
+};
+
+struct s10_priv {
+ struct stratix10_svc_chan *chan;
+ struct stratix10_svc_client client;
+ struct completion status_return_completion;
+ struct s10_svc_buf svc_bufs[NUM_SVC_BUFS];
+ unsigned long status;
+};
+
+static int s10_svc_send_msg(struct s10_priv *priv,
+ enum stratix10_svc_command_code command,
+ void *payload, u32 payload_length)
+{
+ struct stratix10_svc_chan *chan = priv->chan;
+ struct stratix10_svc_client_msg msg;
+ int ret;
+
+ pr_debug("%s cmd=%d payload=%p legnth=%d\n",
+ __func__, command, payload, payload_length);
+
+ msg.command = command;
+ msg.payload = payload;
+ msg.payload_length = payload_length;
+
+ ret = stratix10_svc_send(chan, &msg);
+ pr_debug("stratix10_svc_send returned status %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * s10_free_buffers
+ * Free buffers allocated from the service layer's pool that are not in use.
+ * @mgr: fpga manager struct
+ * Free all buffers that are not in use.
+ * Return true when all buffers are freed.
+ */
+static bool s10_free_buffers(struct fpga_manager *mgr)
+{
+ struct s10_priv *priv = mgr->priv;
+ uint num_free = 0;
+ uint i;
+
+ for (i = 0; i < NUM_SVC_BUFS; i++) {
+ if (!priv->svc_bufs[i].buf) {
+ num_free++;
+ continue;
+ }
+
+ if (!test_and_set_bit_lock(SVC_BUF_LOCK,
+ &priv->svc_bufs[i].lock)) {
+ stratix10_svc_free_memory(priv->chan,
+ priv->svc_bufs[i].buf);
+ priv->svc_bufs[i].buf = NULL;
+ num_free++;
+ }
+ }
+
+ return num_free == NUM_SVC_BUFS;
+}
+
+/**
+ * s10_free_buffer_count
+ * Count how many buffers are not in use.
+ * @mgr: fpga manager struct
+ * Return # of buffers that are not in use.
+ */
+static uint s10_free_buffer_count(struct fpga_manager *mgr)
+{
+ struct s10_priv *priv = mgr->priv;
+ uint num_free = 0;
+ uint i;
+
+ for (i = 0; i < NUM_SVC_BUFS; i++)
+ if (!priv->svc_bufs[i].buf)
+ num_free++;
+
+ return num_free;
+}
+
+/**
+ * s10_unlock_bufs
+ * Given the returned buffer address, match that address to our buffer struct
+ * and unlock that buffer. This marks it as available to be refilled and sent
+ * (or freed).
+ * @priv: private data
+ * @kaddr: kernel address of buffer that was returned from service layer
+ */
+static void s10_unlock_bufs(struct s10_priv *priv, void *kaddr)
+{
+ uint i;
+
+ if (!kaddr)
+ return;
+
+ for (i = 0; i < NUM_SVC_BUFS; i++)
+ if (priv->svc_bufs[i].buf == kaddr) {
+ clear_bit_unlock(SVC_BUF_LOCK,
+ &priv->svc_bufs[i].lock);
+ return;
+ }
+
+ WARN(1, "Unknown buffer returned from service layer %p\n", kaddr);
+}
+
+/**
+ * s10_receive_callback
+ * Callback for service layer to use to provide client (this driver) messages
+ * received through the mailbox.
+ * @client: service layer client struct
+ * @data: message
+ */
+static void s10_receive_callback(struct stratix10_svc_client *client,
+ struct stratix10_svc_cb_data *data)
+{
+ struct s10_priv *priv = client->priv;
+ u32 status;
+ int i;
+
+ WARN_ONCE(!data, "%s: stratix10_svc_rc_data = NULL", __func__);
+
+ status = data->status;
+
+ /*
+ * Here we set status bits as we receive them. Elsewhere, we always use
+ * test_and_clear_bit() to check status in priv->status
+ */
+ for (i = 0; i <= SVC_STATUS_RECONFIG_ERROR; i++)
+ if (status & (1 << i))
+ set_bit(i, &priv->status);
+
+ if (status & BIT(SVC_STATUS_RECONFIG_BUFFER_DONE)) {
+ s10_unlock_bufs(priv, data->kaddr1);
+ s10_unlock_bufs(priv, data->kaddr2);
+ s10_unlock_bufs(priv, data->kaddr3);
+ }
+
+ complete(&priv->status_return_completion);
+}
+
+/**
+ * s10_ops_write_init
+ * Prepare for FPGA reconfiguration by requesting partial reconfig and
+ * allocating buffers from the service layer.
+ * @mgr: fpga manager
+ * @info: fpga image info
+ * @buf: fpga image buffer
+ * @count: size of buf in bytes
+ */
+static int s10_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ struct s10_priv *priv = mgr->priv;
+ struct device *dev = priv->client.dev;
+ unsigned long timeout;
+ struct stratix10_svc_command_reconfig_payload payload;
+ char *kbuf;
+ uint i;
+ int ret;
+
+ if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+ dev_info(dev, "Requesting partial reconfiguration.\n");
+ payload.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
+ } else {
+ dev_info(dev, "Requesting full reconfiguration.\n");
+ }
+
+ reinit_completion(&priv->status_return_completion);
+ ret = s10_svc_send_msg(priv, COMMAND_RECONFIG,
+ &payload, sizeof(payload));
+ if (ret)
+ goto init_done;
+
+ timeout = msecs_to_jiffies(SVC_RECONFIG_REQUEST_TIMEOUT_MS);
+ ret = wait_for_completion_interruptible_timeout(
+ &priv->status_return_completion, timeout);
+ if (!ret) {
+ dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
+ ret = -ETIMEDOUT;
+ goto init_done;
+ }
+ if (ret < 0) {
+ dev_err(dev, "error (%d) waiting for RECONFIG_REQUEST\n", ret);
+ goto init_done;
+ }
+
+ ret = 0;
+ if (!test_and_clear_bit(SVC_STATUS_RECONFIG_REQUEST_OK,
+ &priv->status)) {
+ ret = -ETIMEDOUT;
+ goto init_done;
+ }
+
+ /* Allocate buffers from the service layer's pool. */
+ for (i = 0; i < NUM_SVC_BUFS; i++) {
+ kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE);
+ if (!kbuf) {
+ s10_free_buffers(mgr);
+ ret = -ENOMEM;
+ goto init_done;
+ }
+
+ priv->svc_bufs[i].buf = kbuf;
+ priv->svc_bufs[i].lock = 0;
+ }
+
+init_done:
+ stratix10_svc_done(priv->chan);
+ return ret;
+}
+
+/**
+ * s10_send_buf
+ * Send a buffer to the service layer queue
+ * @mgr: fpga manager struct
+ * @buf_num: index of buffer in svc_bufs array
+ * @buf: fpga image buffer
+ * @count: size of buf in bytes
+ * Returns # of bytes transferred or -errno, never 0
+ */
+static int s10_send_buf(struct fpga_manager *mgr, uint buf_num,
+ const char *buf, size_t count)
+
+{
+ struct s10_priv *priv = mgr->priv;
+ struct device *dev = priv->client.dev;
+ void *svc_buf;
+ size_t xfer_sz;
+ int ret;
+
+ xfer_sz = count < SVC_BUF_SIZE ? count : SVC_BUF_SIZE;
+
+ svc_buf = priv->svc_bufs[buf_num].buf;
+ memcpy(svc_buf, buf, xfer_sz);
+ ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT,
+ svc_buf, xfer_sz);
+ if (ret) {
+ dev_err(dev,
+ "Error while sending data to service layer (%d)", ret);
+ return ret;
+ }
+
+ return xfer_sz;
+}
+
+/**
+ * s10_ops_write
+ * Send a FPGA image to privileged layers to write to the FPGA. When done
+ * sending, free all service layer buffers we allocated in write_init.
+ * @mgr: fpga manager
+ * @buf: fpga image buffer
+ * @count: size of buf in bytes
+ * Returns 0 for success or negative errno.
+ */
+static int s10_ops_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ struct s10_priv *priv = mgr->priv;
+ struct device *dev = priv->client.dev;
+ unsigned long timeout;
+ size_t sent = 0;
+ int ret = 0;
+ uint i;
+
+ timeout = msecs_to_jiffies(SVC_RECONFIG_BUFFER_TIMEOUT_MS);
+
+ /* Buffer loop: either send buffers or free them. */
+ while (1) {
+ reinit_completion(&priv->status_return_completion);
+
+ if (count > 0) {
+ for (i = 0; i < NUM_SVC_BUFS; i++)
+ if (!test_and_set_bit_lock(
+ SVC_BUF_LOCK, &priv->svc_bufs[i].lock))
+ break;
+
+ if (i == NUM_SVC_BUFS)
+ /* wait for a free buffer */
+ continue;
+
+ sent = s10_send_buf(mgr, i, buf, count);
+ /*
+ * If service queue was full, we won't get a callback.
+ * Wait and try again
+ */
+ if (sent < 0)
+ continue;
+
+ count -= sent;
+ buf += sent;
+ } else {
+ s10_free_buffers(mgr);
+ if (s10_free_buffer_count(mgr) == NUM_SVC_BUFS)
+ return 0;
+
+ ret = s10_svc_send_msg(
+ priv, COMMAND_RECONFIG_DATA_CLAIM,
+ NULL, 0);
+ if (ret)
+ break;
+ }
+
+ /*
+ * If callback hasn't already happened, wait for buffers to be
+ * returned from service layer
+ */
+ if (priv->status)
+ ret = 0;
+ else
+ ret = wait_for_completion_interruptible_timeout(
+ &priv->status_return_completion, timeout);
+
+ if (test_and_clear_bit(
+ SVC_STATUS_RECONFIG_BUFFER_DONE, &priv->status))
+ continue;
+
+ if (test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED,
+ &priv->status))
+ continue;
+
+ if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR,
+ &priv->status)) {
+ dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n");
+ ret = -EFAULT;
+ break;
+ }
+
+ if (!ret) {
+ dev_err(dev, "timeout waiting for svc layer buffers\n");
+ ret = -ETIMEDOUT;
+ break;
+ }
+ if (ret < 0) {
+ dev_err(dev,
+ "error (%d) waiting for svc layer buffers\n",
+ ret);
+ break;
+ }
+ }
+
+ s10_free_buffers(mgr);
+ if (s10_free_buffer_count(mgr) != NUM_SVC_BUFS)
+ dev_err(dev, "%s not all buffers were freed\n", __func__);
+
+ return ret;
+}
+
+/**
+ * s10_ops_write_complete
+ * Wait for FPGA configuration to be done
+ * @mgr: fpga manager
+ * @info: fpga image info
+ * Returns 0 for success negative errno.
+ */
+static int s10_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ struct s10_priv *priv = mgr->priv;
+ struct device *dev = priv->client.dev;
+ unsigned long timeout;
+ int ret;
+
+ timeout = usecs_to_jiffies(info->config_complete_timeout_us);
+
+ do {
+ reinit_completion(&priv->status_return_completion);
+
+ ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_STATUS, NULL, 0);
+ if (ret)
+ break;
+
+ ret = wait_for_completion_interruptible_timeout(
+ &priv->status_return_completion, timeout);
+ if (!ret) {
+ dev_err(dev,
+ "timeout waiting for RECONFIG_COMPLETED\n");
+ ret = -ETIMEDOUT;
+ break;
+ }
+ if (ret < 0) {
+ dev_err(dev,
+ "error (%d) waiting for RECONFIG_COMPLETED\n",
+ ret);
+ break;
+ }
+ /* Not error or timeout, so ret is # of jiffies until timeout */
+ timeout = ret;
+ ret = 0;
+
+ if (test_and_clear_bit(SVC_STATUS_RECONFIG_COMPLETED,
+ &priv->status))
+ break;
+
+ if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR,
+ &priv->status)) {
+ dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n");
+ ret = -EFAULT;
+ break;
+ }
+ } while (1);
+
+ stratix10_svc_done(priv->chan);
+ return ret;
+}
+
+static enum fpga_mgr_states s10_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops s10_ops = {
+ .state = s10_ops_state,
+ .write_init = s10_ops_write_init,
+ .write = s10_ops_write,
+ .write_complete = s10_ops_write_complete,
+};
+
+static int s10_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct s10_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->client.dev = dev;
+ priv->client.receive_cb = s10_receive_callback;
+ priv->client.priv = priv;
+
+ priv->chan = stratix10_svc_request_channel_byname(&priv->client,
+ SVC_CLIENT_FPGA);
+ if (IS_ERR(priv->chan)) {
+ dev_err(dev, "couldn't get service channel (%s)\n",
+ SVC_CLIENT_FPGA);
+ return PTR_ERR(priv->chan);
+ }
+
+ init_completion(&priv->status_return_completion);
+
+ ret = fpga_mgr_register(dev, "Stratix10 SOC FPGA Manager",
+ &s10_ops, priv);
+
+ if (ret)
+ stratix10_svc_free_channel(priv->chan);
+
+ return ret;
+}
+
+static int s10_remove(struct platform_device *pdev)
+{
+ struct fpga_manager *mgr = platform_get_drvdata(pdev);
+ struct s10_priv *priv = mgr->priv;
+
+ fpga_mgr_unregister(&pdev->dev);
+ stratix10_svc_free_channel(priv->chan);
+
+ return 0;
+}
+
+static const struct of_device_id s10_of_match[] = {
+ { .compatible = "intel,stratix10-soc-fpga-mgr", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, s10_of_match);
+
+static struct platform_driver s10_driver = {
+ .probe = s10_probe,
+ .remove = s10_remove,
+ .driver = {
+ .name = "Stratix10 SoC FPGA manager",
+ .of_match_table = of_match_ptr(s10_of_match),
+ },
+};
+
+static int __init s10_init(void)
+{
+ struct device_node *fw_np;
+ struct device_node *np;
+ int ret;
+
+ fw_np = of_find_node_by_name(NULL, "svc");
+ if (!fw_np)
+ return -ENODEV;
+
+ np = of_find_matching_node(fw_np, s10_of_match);
+ if (!np) {
+ of_node_put(fw_np);
+ return -ENODEV;
+ }
+
+ of_node_put(np);
+ ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL);
+ of_node_put(fw_np);
+ if (ret)
+ return ret;
+
+ return platform_driver_register(&s10_driver);
+}
+
+static void __exit s10_exit(void)
+{
+ return platform_driver_unregister(&s10_driver);
+}
+
+module_init(s10_init);
+module_exit(s10_exit);
+
+MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
+MODULE_DESCRIPTION("Intel Stratix 10 SOC FPGA Manager");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCHv5 5/8] arm64: dts: stratix10: add fpga manager and region
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Alan Tull <atull@kernel.org>
Add the Stratix10 FPGA manager and a FPGA region to the
device tree.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
v4: s/fpga-mgr at 0/fpga-mgr/ to remove unit_address
add Richard's signed-off-by
v5: no change
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index c257287..8f8f409 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -106,6 +106,14 @@
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
clkmgr: clock-controller at ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
@@ -506,6 +514,10 @@
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
};
};
};
--
2.7.4
^ permalink raw reply related
* [PATCHv5 4/8] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Alan Tull <atull@kernel.org>
Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Richard Gong <richard.gong@intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2: this patch is added in patch set version 2
v3: change to put fpga_mgr node under firmware/svc node
v4: s/fpga-mgr at 0/fpga-mgr/ to remove unit_address
add Richard's signed-off-by
v5: add Reviewed-by Rob Herring
---
.../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
new file mode 100644
index 0000000..6e03f79
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
@@ -0,0 +1,17 @@
+Intel Stratix10 SoC FPGA Manager
+
+Required properties:
+The fpga_mgr node has the following mandatory property, must be located under
+firmware/svc node.
+
+- compatible : should contain "intel,stratix10-soc-fpga-mgr"
+
+Example:
+
+ firmware {
+ svc {
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
+ };
+ };
--
2.7.4
^ permalink raw reply related
* [PATCHv5 3/8] driver, misc: add Intel Stratix10 service layer driver
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Richard Gong <richard.gong@intel.com>
Some features of the Intel Stratix10 SoC require a level of privilege
higher than the kernel is granted. Such secure features include
FPGA programming. In terms of the ARMv8 architecture, the kernel runs
at Exception Level 1 (EL1), access to the features requires
Exception Level 3 (EL3).
The Intel Stratix10 SoC service layer provides an in kernel API for
drivers to request access to the secure features. The requests are queued
and processed one by one. ARM?s SMCCC is used to pass the execution
of the requests on to a secure monitor (EL3).
The header file stratix10-sve-client.h defines the interface between
service providers (FPGA manager is one of them) and service layer.
The header file stratix10-smc.h defines the secure monitor call (SMC)
message protocols used for service layer driver in normal world
(EL1) to communicate with secure monitor SW in secure monitor exception
level 3 (EL3).
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
---
v2: Remove intel-service subdirectory and intel-service.h, move
intel-smc.h and intel-service.c to driver/misc subdirectory
Correct SPDX markers
Change service layer driver be 'default n'
Remove global variables
Add timeout for do..while() loop
Add kernel-doc for the functions and structs, correct multiline comments
Replace kfifo_in/kfifo_out with kfifo_in_spinlocked/kfifo_out_spinlocked
rename struct intel_svc_data (at client header) to intel_svc_client_msg
rename struct intel_svc_private_mem to intel_svc_data
Other corrections/changes from Intel internal code reviews
v3: Change all exported functions with "intel_svc_" as the prefix
Increase timeout values for claiming back submitted buffer(s)
Rename struct intel_command_reconfig_payload to
struct intel_svc_command_reconfig_payload
Add pr_err() to provide the error return value
Other corrections/changes
v4: s/intel/stratix10/ on some variables, structs, functions, and file names
intel-service.c -> stratix10-svc.c
intel-smc.h -> stratix10-smc.h
intel-service-client.h -> stratix10-svc-client.h
Remove non-kernel-doc formatting
v5: add a new API statix10_svc_done() which is called by service client
when client request is completed or error occurs during request
process. Which allows service layer to free its resources.
remove dummy client from service layer client header and service
layer source file.
kernel-doc fixes
---
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/stratix10-smc.h | 205 ++++++++
drivers/misc/stratix10-svc.c | 984 +++++++++++++++++++++++++++++++++++
include/linux/stratix10-svc-client.h | 199 +++++++
5 files changed, 1401 insertions(+)
create mode 100644 drivers/misc/stratix10-smc.h
create mode 100644 drivers/misc/stratix10-svc.c
create mode 100644 include/linux/stratix10-svc-client.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 5d71300..5d5b648 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -138,6 +138,18 @@ config INTEL_MID_PTI
an Intel Atom (non-netbook) mobile device containing a MIPI
P1149.7 standard implementation.
+config STRATIX10_SERVICE
+ tristate "Stratix10 Service Layer"
+ depends on HAVE_ARM_SMCCC
+ default n
+ help
+ Stratix10 service layer runs at privileged exception level, interfaces with
+ the service providers (FPGA manager is one of them) and manages secure
+ monitor call to communicate with secure monitor software at secure monitor
+ exception level.
+
+ Say Y here if you want Stratix10 service layer support.
+
config SGI_IOC4
tristate "SGI IOC4 Base IO support"
depends on PCI
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 20be70c..99fed8b 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o
obj-$(CONFIG_AD525X_DPOT_I2C) += ad525x_dpot-i2c.o
obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_dpot-spi.o
obj-$(CONFIG_INTEL_MID_PTI) += pti.o
+obj-$(CONFIG_STRATIX10_SERVICE) += stratix10-svc.o
obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
obj-$(CONFIG_DUMMY_IRQ) += dummy-irq.o
diff --git a/drivers/misc/stratix10-smc.h b/drivers/misc/stratix10-smc.h
new file mode 100644
index 0000000..94615f4
--- /dev/null
+++ b/drivers/misc/stratix10-smc.h
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018, Intel Corporation
+ */
+
+#ifndef __STRATIX10_SMC_H
+#define __STRATIX10_SMC_H
+
+#include <linux/arm-smccc.h>
+#include <linux/bitops.h>
+
+/**
+ * This file defines the Secure Monitor Call (SMC) message protocol used for
+ * service layer driver in normal world (EL1) to communicate with secure
+ * monitor software in Secure Monitor Exception Level 3 (EL3).
+ *
+ * This file is shared with secure firmware (FW) which is out of kernel tree.
+ *
+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
+ * register values as arguments, and can return up to 4 64-bit register
+ * value. The operation of the secure monitor is determined by the parameter
+ * values passed in through registers.
+ *
+ * EL1 and EL3 communicates pointer as physical address rather than the
+ * virtual address.
+ *
+ * Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has
+ * completed.
+ *
+ * a0..a7 is used as register names in the descriptions below, on arm32
+ * that translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+/**
+ * @func_num: function ID
+ */
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+/**
+ * Return values in INTEL_SIP_SMC_* call
+ *
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
+ * Secure monitor software doesn't recognize the request.
+ *
+ * INTEL_SIP_SMC_STATUS_OK:
+ * FPGA configuration completed successfully,
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software can accept the next chunk of FPGA configuration data.
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software is still processing previous data & can't accept the next chunk
+ * of data. Service driver needs to issue
+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
+ * completed block(s).
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
+ * There is error during the FPGA configuration process.
+ */
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
+#define INTEL_SIP_SMC_STATUS_OK 0x0
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2
+#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
+ *
+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
+ * be prepare to receive a new configuration.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
+ * a1: flag for full or partial configuration. 0 for full and 1 for partial
+ * configuration.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ *
+ * Async call used by service driver at EL1 to provide FPGA configuration data
+ * to secure world.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
+ * a1: 64bit physical address of the configuration data memory block
+ * a2: Size of configuration data block.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block if any completed
+ * block, otherwise zero value.
+ * a2: 64bit physical address of 2nd completed memory block if any completed
+ * block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if any completed
+ * block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
+ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
+ *
+ * Sync call used by service driver at EL1 to track the completed write
+ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block.
+ * a2: 64bit physical address of 2nd completed memory block if
+ * any completed block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if
+ * any completed block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
+INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
+ *
+ * Sync call used by service driver at EL1 to inform secure world that all
+ * data are sent, to check whether or not the secure world had completed
+ * the FPGA configuration process.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
+ *
+ * Sync call used by service driver at EL1 to query the physical address of
+ * memory block reserved by secure monitor software.
+ *
+ * Call register usage:
+ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1: start of physical address of reserved memory block.
+ * a2: size of reserved memory block.
+ * a3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
+
+/**
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
+ *
+ * For SMC loop-back mode only, used for internal integration, debugging
+ * or troubleshooting.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
+#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
+
+#endif
diff --git a/drivers/misc/stratix10-svc.c b/drivers/misc/stratix10-svc.c
new file mode 100644
index 0000000..5d07994
--- /dev/null
+++ b/drivers/misc/stratix10-svc.c
@@ -0,0 +1,984 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018, Intel Corporation
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/genalloc.h>
+#include <linux/stratix10-svc-client.h>
+#include <linux/io.h>
+#include <linux/kfifo.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "stratix10-smc.h"
+
+/**
+ * SVC_NUM_DATA_IN_FIFO - number of struct stratix10_svc_data in the FIFO
+ *
+ * SVC_NUM_CHANNEL - number of channel supported by service layer driver
+ *
+ * FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS - claim back the submitted buffer(s)
+ * from the secure world for FPGA manager to reuse, or to free the buffer(s)
+ * when all bit-stream data had be send.
+ *
+ * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status,
+ * service layer will return error to FPGA manager when timeout occurs,
+ * timeout is set to 30 seconds (30 * 1000) at Intel Stratix10 SoC.
+ */
+#define SVC_NUM_DATA_IN_FIFO 32
+#define SVC_NUM_CHANNEL 1
+#define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 200
+#define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30
+
+typedef void (svc_invoke_fn)(unsigned long, unsigned long, unsigned long,
+ unsigned long, unsigned long, unsigned long,
+ unsigned long, unsigned long,
+ struct arm_smccc_res *);
+struct stratix10_svc_chan;
+
+/**
+ * struct stratix10_svc_sh_memory - service shared memory structure
+ * @sync_complete: state for a completion
+ * @addr: physical address of shared memory block
+ * @size: size of shared memory block
+ * @invoke_fn: function to issue secure monitor or hypervisor call
+ *
+ * This struct is used to save physical address and size of shared memory
+ * block. The shared memory blocked is allocated by secure monitor software
+ * at secure world.
+ *
+ * Service layer driver uses the physical address and size to create a memory
+ * pool, then allocates data buffer from that memory pool for service client.
+ */
+struct stratix10_svc_sh_memory {
+ struct completion sync_complete;
+ unsigned long addr;
+ unsigned long size;
+ svc_invoke_fn *invoke_fn;
+};
+
+/**
+ * struct stratix10_svc_data_mem - service memory structure
+ * @vaddr: virtual address
+ * @paddr: physical address
+ * @size: size of memory
+ * @node: link list head node
+ *
+ * This struct is used in a list that keeps track of buffers which have
+ * been allocated or freed from the memory pool. Service layer driver also
+ * uses this struct to transfer physical address to virtual address.
+ */
+struct stratix10_svc_data_mem {
+ void *vaddr;
+ phys_addr_t paddr;
+ size_t size;
+ struct list_head node;
+};
+
+/**
+ * struct stratix10_svc_data - service data structure
+ * @chan: service channel
+ * @paddr: playload physical address
+ * @size: playload size
+ * @command: service command requested by client
+ *
+ * This struct is used in service FIFO for inter-process communication.
+ */
+struct stratix10_svc_data {
+ struct stratix10_svc_chan *chan;
+ phys_addr_t paddr;
+ size_t size;
+ u32 command;
+};
+
+/**
+ * struct stratix10_svc_controller - service controller
+ * @dev: device
+ * @chans: array of service channels
+ * @num_chans: number of channels in 'chans' array
+ * @num_active_client: number of active service client
+ * @node: list management
+ * @genpool: memory pool pointing to the memory region
+ * @task: pointer to the thread task which handles SMC or HVC call
+ * @svc_fifo: a queue for storing service message data
+ * @complete_status: state for completion
+ * @svc_fifo_lock: protect access to service message data queue
+ * @invoke_fn: function to issue secure monitor call or hypervisor call
+ *
+ * This struct is used to create communication channels for service clients, to
+ * handle secure monitor or hypervisor call.
+ */
+struct stratix10_svc_controller {
+ struct device *dev;
+ struct stratix10_svc_chan *chans;
+ int num_chans;
+ int num_active_client;
+ struct list_head node;
+ struct gen_pool *genpool;
+ struct task_struct *task;
+ struct kfifo svc_fifo;
+ struct completion complete_status;
+ spinlock_t svc_fifo_lock;
+ svc_invoke_fn *invoke_fn;
+};
+
+/**
+ * struct stratix10_svc_chan - service communication channel
+ * @ctrl: pointer to service controller which is the provider of this channel
+ * @scl: pointer to service client which owns the channel
+ * @name: service client name associated with the channel
+ * @lock: protect access to the channel
+ *
+ * This struct is used by service client to communicate with service layer, each
+ * service client has its own channel created by service controller.
+ */
+struct stratix10_svc_chan {
+ struct stratix10_svc_controller *ctrl;
+ struct stratix10_svc_client *scl;
+ char *name;
+ spinlock_t lock;
+};
+
+static LIST_HEAD(svc_ctrl);
+static LIST_HEAD(svc_data_mem);
+
+/**
+ * svc_pa_to_va() - translate physical address to virtual address
+ * @addr: to be translated physical address
+ *
+ * Return: valid virtual address or NULL if the provided physical
+ * address doesn't exist.
+ */
+static void *svc_pa_to_va(unsigned long addr)
+{
+ struct stratix10_svc_data_mem *pmem;
+
+ pr_debug("claim back P-addr=0x%016x\n", (unsigned int)addr);
+ list_for_each_entry(pmem, &svc_data_mem, node) {
+ if (pmem->paddr == addr)
+ return pmem->vaddr;
+ }
+
+ /* physical address is not found */
+ return NULL;
+}
+
+/**
+ * svc_thread_cmd_data_claim() - claim back buffer from the secure world
+ * @ctrl: pointer to service layer controller
+ * @p_data: pointer to service data structure
+ * @cb_data: pointer to callback data structure to service client
+ *
+ * Claim back the submitted buffers from the secure world and pass buffer
+ * back to service client (FPGA manager, etc) for reuse.
+ */
+static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl,
+ struct stratix10_svc_data *p_data,
+ struct stratix10_svc_cb_data *cb_data)
+{
+ struct arm_smccc_res res;
+ unsigned long timeout;
+
+ reinit_completion(&ctrl->complete_status);
+ timeout = msecs_to_jiffies(FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS);
+
+ pr_debug("%s: claim back the submitted buffer\n", __func__);
+ do {
+ ctrl->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ 0, 0, 0, 0, 0, 0, 0, &res);
+
+ if (res.a0 == INTEL_SIP_SMC_STATUS_OK) {
+ if (!res.a1) {
+ complete(&ctrl->complete_status);
+ break;
+ }
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_DONE);
+ cb_data->kaddr1 = svc_pa_to_va(res.a1);
+ cb_data->kaddr2 = (res.a2) ?
+ svc_pa_to_va(res.a2) : NULL;
+ cb_data->kaddr3 = (res.a3) ?
+ svc_pa_to_va(res.a3) : NULL;
+ p_data->chan->scl->receive_cb(p_data->chan->scl,
+ cb_data);
+ } else {
+ pr_debug("%s: secure world busy, polling again\n",
+ __func__);
+ }
+ } while (res.a0 == INTEL_SIP_SMC_STATUS_OK ||
+ res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY ||
+ wait_for_completion_timeout(&ctrl->complete_status, timeout));
+}
+
+/**
+ * svc_thread_cmd_config_status() - check configuration status
+ * @ctrl: pointer to service layer controller
+ * @p_data: pointer to service data structure
+ * @cb_data: pointer to callback data structure to service client
+ *
+ * Check whether the secure firmware at secure world has finished the FPGA
+ * configuration, and then inform FPGA manager the configuration status.
+ */
+static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl,
+ struct stratix10_svc_data *p_data,
+ struct stratix10_svc_cb_data *cb_data)
+{
+ struct arm_smccc_res res;
+ int count_in_sec;
+
+ cb_data->kaddr1 = NULL;
+ cb_data->kaddr2 = NULL;
+ cb_data->kaddr3 = NULL;
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_ERROR);
+
+ pr_debug("%s: polling config status\n", __func__);
+
+ count_in_sec = FPGA_CONFIG_STATUS_TIMEOUT_SEC;
+ while (count_in_sec) {
+ ctrl->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE,
+ 0, 0, 0, 0, 0, 0, 0, &res);
+ if ((res.a0 == INTEL_SIP_SMC_STATUS_OK) ||
+ (res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR))
+ break;
+
+ /*
+ * configuration is still in progress, wait one second then
+ * poll again
+ */
+ msleep(1000);
+ count_in_sec--;
+ };
+
+ if (res.a0 == INTEL_SIP_SMC_STATUS_OK && count_in_sec)
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED);
+
+ p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data);
+}
+
+/**
+ * svc_thread_recv_status_ok() - handle the successful status
+ * @p_data: pointer to service data structure
+ * @cb_data: pointer to callback data structure to service client
+ * @res: result from SMC or HVC call
+ *
+ * Send back the correspond status to the service client (FPGA manager etc).
+ */
+static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data,
+ struct stratix10_svc_cb_data *cb_data,
+ struct arm_smccc_res res)
+{
+ cb_data->kaddr1 = NULL;
+ cb_data->kaddr2 = NULL;
+ cb_data->kaddr3 = NULL;
+
+ switch (p_data->command) {
+ case COMMAND_RECONFIG:
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_REQUEST_OK);
+ break;
+ case COMMAND_RECONFIG_DATA_SUBMIT:
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED);
+ break;
+ case COMMAND_NOOP:
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED);
+ cb_data->kaddr1 = svc_pa_to_va(res.a1);
+ break;
+ case COMMAND_RECONFIG_STATUS:
+ cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED);
+ break;
+ default:
+ break;
+ }
+
+ pr_debug("%s: call receive_cb\n", __func__);
+ p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data);
+}
+
+/**
+ * svc_normal_to_secure_thread() - the function to run in the kthread
+ * @data: data pointer for kthread function
+ *
+ * Service layer driver creates stratix10_svc_smc_hvc_call kthread on CPU
+ * node 0, its function stratix10_svc_secure_call_thread is used to handle
+ * SMC or HVC calls between kernel driver and secure monitor software.
+ *
+ * Return: 0 for success or -ENOMEM on error.
+ */
+static int svc_normal_to_secure_thread(void *data)
+{
+ struct stratix10_svc_controller
+ *ctrl = (struct stratix10_svc_controller *)data;
+ struct stratix10_svc_data *pdata;
+ struct stratix10_svc_cb_data *cbdata;
+ struct arm_smccc_res res;
+ unsigned long a0, a1, a2;
+ int ret_fifo = 0;
+
+ pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ cbdata = kmalloc(sizeof(*cbdata), GFP_KERNEL);
+ if (!cbdata)
+ return -ENOMEM;
+
+ /* default set, to remove build warning */
+ a0 = INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK;
+ a1 = 0;
+ a2 = 0;
+
+ pr_debug("smc_hvc_shm_thread is running\n");
+
+ while (!kthread_should_stop()) {
+ ret_fifo = kfifo_out_spinlocked(&ctrl->svc_fifo,
+ pdata, sizeof(*pdata),
+ &ctrl->svc_fifo_lock);
+
+ if (!ret_fifo)
+ continue;
+
+ pr_debug("get from FIFO pa=0x%016x, command=%u, size=%u\n",
+ (unsigned int)pdata->paddr, pdata->command,
+ (unsigned int)pdata->size);
+
+ switch (pdata->command) {
+ case COMMAND_RECONFIG_DATA_CLAIM:
+ svc_thread_cmd_data_claim(ctrl, pdata, cbdata);
+ continue;
+ case COMMAND_RECONFIG:
+ a0 = INTEL_SIP_SMC_FPGA_CONFIG_START;
+ a1 = 0;
+ a2 = 0;
+ break;
+ case COMMAND_RECONFIG_DATA_SUBMIT:
+ a0 = INTEL_SIP_SMC_FPGA_CONFIG_WRITE;
+ a1 = (unsigned long)pdata->paddr;
+ a2 = (unsigned long)pdata->size;
+ break;
+ case COMMAND_RECONFIG_STATUS:
+ a0 = INTEL_SIP_SMC_FPGA_CONFIG_ISDONE;
+ a1 = 0;
+ a2 = 0;
+ break;
+ default:
+ /* it shouldn't happen */
+ break;
+ }
+ pr_debug("%s: before SMC call -- a0=0x%016x a1=0x%016x",
+ __func__, (unsigned int)a0, (unsigned int)a1);
+ pr_debug(" a2=0x%016x\n", (unsigned int)a2);
+
+ ctrl->invoke_fn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
+
+ pr_debug("%s: after SMC call -- res.a0=0x%016x",
+ __func__, (unsigned int)res.a0);
+ pr_debug(" res.a1=0x%016x, res.a2=0x%016x",
+ (unsigned int)res.a1, (unsigned int)res.a2);
+ pr_debug(" res.a3=0x%016x\n", (unsigned int)res.a3);
+
+ switch (res.a0) {
+ case INTEL_SIP_SMC_STATUS_OK:
+ svc_thread_recv_status_ok(pdata, cbdata, res);
+ break;
+ case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
+ switch (pdata->command) {
+ case COMMAND_RECONFIG_DATA_SUBMIT:
+ svc_thread_cmd_data_claim(ctrl,
+ pdata, cbdata);
+ break;
+ case COMMAND_RECONFIG_STATUS:
+ svc_thread_cmd_config_status(ctrl,
+ pdata, cbdata);
+ break;
+ default:
+ break;
+ }
+ break;
+ case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED:
+ pr_debug("%s: STATUS_REJECTED\n", __func__);
+ break;
+ case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
+ pr_err("%s: STATUS_ERROR\n", __func__);
+ cbdata->status = BIT(SVC_STATUS_RECONFIG_ERROR);
+ cbdata->kaddr1 = NULL;
+ cbdata->kaddr2 = NULL;
+ cbdata->kaddr3 = NULL;
+ pdata->chan->scl->receive_cb(pdata->chan->scl, cbdata);
+ break;
+ default:
+ break;
+ }
+ };
+
+ kfree(cbdata);
+ kfree(pdata);
+
+ return 0;
+}
+
+/**
+ * svc_normal_to_secure_shm_thread() - the function to run in the kthread
+ * @data: data pointer for kthread function
+ *
+ * Service layer driver creates stratix10_svc_smc_hvc_shm kthread on CPU
+ * node 0, its function stratix10_svc_secure_shm_thread is used to query the
+ * physical address of memory block reserved by secure monitor software at
+ * secure world.
+ *
+ * svc_normal_to_secure_shm_thread() calls do_exit() directly since it is a
+ * standlone thread for which no one will call kthread_stop() or return when
+ * 'kthread_should_stop()' is true.
+ */
+static int svc_normal_to_secure_shm_thread(void *data)
+{
+ struct stratix10_svc_sh_memory
+ *sh_mem = (struct stratix10_svc_sh_memory *)data;
+ struct arm_smccc_res res;
+
+ /* SMC or HVC call to get shared memory info from secure world */
+ sh_mem->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM,
+ 0, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0 == INTEL_SIP_SMC_STATUS_OK) {
+ sh_mem->addr = res.a1;
+ sh_mem->size = res.a2;
+ } else {
+ pr_err("%s: after SMC call -- res.a0=0x%016x", __func__,
+ (unsigned int)res.a0);
+ sh_mem->addr = 0;
+ sh_mem->size = 0;
+ }
+
+ complete(&sh_mem->sync_complete);
+ do_exit(0);
+}
+
+/**
+ * svc_get_sh_memory() - get memory block reserved by secure monitor SW
+ * @pdev: pointer to service layer device
+ * @sh_memory: pointer to service shared memory structure
+ *
+ * Return: zero for successfully getting the physical address of memory block
+ * reserved by secure monitor software, or negative value on error.
+ */
+static int svc_get_sh_memory(struct platform_device *pdev,
+ struct stratix10_svc_sh_memory *sh_memory)
+{
+ struct device *dev = &pdev->dev;
+ struct task_struct *sh_memory_task;
+
+ init_completion(&sh_memory->sync_complete);
+
+ /* smc or hvc call happens on cpu 0 bound kthread */
+ sh_memory_task = kthread_create_on_cpu(svc_normal_to_secure_shm_thread,
+ (void *)sh_memory,
+ 0, "svc_smc_hvc_shm_thread");
+ if (IS_ERR(sh_memory_task)) {
+ dev_err(dev, "fail to create stratix10_svc_smc_shm_thread\n");
+ return -EINVAL;
+ }
+
+ wake_up_process(sh_memory_task);
+
+ if (!wait_for_completion_timeout(&sh_memory->sync_complete, 10 * HZ)) {
+ dev_err(dev,
+ "timeout to get sh-memory paras from secure world\n");
+ return -ETIMEDOUT;
+ }
+
+ if (!sh_memory->addr || !sh_memory->size) {
+ dev_err(dev,
+ "fails to get shared memory info from secure world\n");
+ return -ENOMEM;
+ }
+
+ dev_dbg(dev, "SM software provides paddr: 0x%016x, size: 0x%08x\n",
+ (unsigned int)sh_memory->addr,
+ (unsigned int)sh_memory->size);
+
+ return 0;
+}
+
+/**
+ * svc_create_memory_pool() - create a memory pool from reserved memory block
+ * @pdev: pointer to service layer device
+ * @sh_memory: pointer to service shared memory structure
+ *
+ * Return: pool allocated from reserved memory block or ERR_PTR() on error.
+ */
+static struct gen_pool *
+svc_create_memory_pool(struct platform_device *pdev,
+ struct stratix10_svc_sh_memory *sh_memory)
+{
+ struct device *dev = &pdev->dev;
+ struct gen_pool *genpool;
+ unsigned long vaddr;
+ phys_addr_t paddr;
+ size_t size;
+ phys_addr_t begin;
+ phys_addr_t end;
+ void *va;
+ size_t page_mask = PAGE_SIZE - 1;
+ int min_alloc_order = 3;
+ int ret;
+
+ begin = roundup(sh_memory->addr, PAGE_SIZE);
+ end = rounddown(sh_memory->addr + sh_memory->size, PAGE_SIZE);
+ paddr = begin;
+ size = end - begin;
+ va = memremap(paddr, size, MEMREMAP_WC);
+ if (!va) {
+ dev_err(dev, "fail to remap shared memory\n");
+ return ERR_PTR(-EINVAL);
+ }
+ vaddr = (unsigned long)va;
+ dev_dbg(dev,
+ "reserved memory vaddr: %p, paddr: 0x%16x size: 0x%8x\n",
+ va, (unsigned int)paddr, (unsigned int)size);
+ if ((vaddr & page_mask) || (paddr & page_mask) ||
+ (size & page_mask)) {
+ dev_err(dev, "page is not aligned\n");
+ return ERR_PTR(-EINVAL);
+ }
+ genpool = gen_pool_create(min_alloc_order, -1);
+ if (!genpool) {
+ dev_err(dev, "fail to create genpool\n");
+ return ERR_PTR(-ENOMEM);
+ }
+ gen_pool_set_algo(genpool, gen_pool_best_fit, NULL);
+ ret = gen_pool_add_virt(genpool, vaddr, paddr, size, -1);
+ if (ret) {
+ dev_err(dev, "fail to add memory chunk to the pool\n");
+ gen_pool_destroy(genpool);
+ return ERR_PTR(ret);
+ }
+
+ return genpool;
+}
+
+/**
+ * svc_smccc_smc() - secure monitor call between normal and secure world
+ * @a0: argument passed in registers 0
+ * @a1: argument passed in registers 1
+ * @a2: argument passed in registers 2
+ * @a3: argument passed in registers 3
+ * @a4: argument passed in registers 4
+ * @a5: argument passed in registers 5
+ * @a6: argument passed in registers 6
+ * @a7: argument passed in registers 7
+ * @res: result values from register 0 to 3
+ */
+static void svc_smccc_smc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm_smccc_res *res)
+{
+ arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+}
+
+/**
+ * svc_smccc_hvc() - hypervisor call between normal and secure world
+ * @a0: argument passed in registers 0
+ * @a1: argument passed in registers 1
+ * @a2: argument passed in registers 2
+ * @a3: argument passed in registers 3
+ * @a4: argument passed in registers 4
+ * @a5: argument passed in registers 5
+ * @a6: argument passed in registers 6
+ * @a7: argument passed in registers 7
+ * @res: result values from register 0 to 3
+ */
+static void svc_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm_smccc_res *res)
+{
+ arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+}
+
+/**
+ * get_invoke_func() - invoke SMC or HVC call
+ * @dev: pointer to device
+ *
+ * Return: function pointer to svc_smccc_smc or svc_smccc_hvc.
+ */
+static svc_invoke_fn *get_invoke_func(struct device *dev)
+{
+ const char *method;
+
+ if (of_property_read_string(dev->of_node, "method", &method)) {
+ dev_warn(dev, "missing \"method\" property\n");
+ return ERR_PTR(-ENXIO);
+ }
+
+ if (!strcmp(method, "smc"))
+ return svc_smccc_smc;
+ if (!strcmp(method, "hvc"))
+ return svc_smccc_hvc;
+
+ dev_warn(dev, "invalid \"method\" property: %s\n", method);
+
+ return ERR_PTR(-EINVAL);
+}
+
+/**
+ * stratix10_svc_request_channel_byname() - request a service channel
+ * @client: pointer to service client
+ * @name: service client name
+ *
+ * This function is used by service client to request a service channel.
+ *
+ * Return: a pointer to channel assigned to the client on success,
+ * or ERR_PTR() on error.
+ */
+struct stratix10_svc_chan *stratix10_svc_request_channel_byname(
+ struct stratix10_svc_client *client, const char *name)
+{
+ struct device *dev = client->dev;
+ struct stratix10_svc_controller *controller;
+ struct stratix10_svc_chan *chan;
+ unsigned long flag;
+ int i;
+
+ chan = ERR_PTR(-EPROBE_DEFER);
+ if (list_empty(&svc_ctrl))
+ return ERR_PTR(-ENODEV);
+
+ controller = list_first_entry(&svc_ctrl,
+ struct stratix10_svc_controller, node);
+ for (i = 0; i < SVC_NUM_CHANNEL; i++) {
+ if (!strcmp(controller->chans[i].name, name)) {
+ chan = &controller->chans[i];
+ break;
+ }
+ }
+
+ if (chan->scl || !try_module_get(controller->dev->driver->owner)) {
+ dev_dbg(dev, "%s: svc not free\n", __func__);
+ return ERR_PTR(-EBUSY);
+ }
+
+ spin_lock_irqsave(&chan->lock, flag);
+ chan->scl = client;
+ chan->ctrl->num_active_client++;
+ spin_unlock_irqrestore(&chan->lock, flag);
+
+ return chan;
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_request_channel_byname);
+
+/**
+ * stratix10_svc_free_channel() - free service channel
+ * @chan: service channel to be freed
+ *
+ * This function is used by service client to free a service channel.
+ */
+void stratix10_svc_free_channel(struct stratix10_svc_chan *chan)
+{
+ unsigned long flag;
+
+ spin_lock_irqsave(&chan->lock, flag);
+ chan->scl = NULL;
+ chan->ctrl->num_active_client--;
+ module_put(chan->ctrl->dev->driver->owner);
+ spin_unlock_irqrestore(&chan->lock, flag);
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_free_channel);
+
+/**
+ * stratix10_svc_send() - send a message data to the remote
+ * @chan: service channel assigned to the client
+ * @msg: message data to be sent, in the format of
+ * "struct stratix10_svc_client_msg"
+ *
+ * This function is used by service client to add a message to the service
+ * layer driver's queue for being sent to the secure world.
+ *
+ * Return: 0 for success, -ENOMEM or -ENOBUFS on error.
+ */
+int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg)
+{
+ struct stratix10_svc_client_msg
+ *p_msg = (struct stratix10_svc_client_msg *)msg;
+ struct stratix10_svc_data_mem *p_mem;
+ struct stratix10_svc_data *p_data;
+ int ret = 0;
+
+ p_data = kmalloc(sizeof(*p_data), GFP_KERNEL);
+ if (!p_data)
+ return -ENOMEM;
+
+ /* first client will create kernel thread */
+ if (!chan->ctrl->task) {
+ chan->ctrl->task =
+ kthread_create_on_cpu(svc_normal_to_secure_thread,
+ (void *)chan->ctrl, 0,
+ "svc_smc_hvc_thread");
+ if (IS_ERR(chan->ctrl->task)) {
+ dev_err(chan->ctrl->dev,
+ "fails to create svc_smc_hvc_thread\n");
+ return -EINVAL;
+ }
+ wake_up_process(chan->ctrl->task);
+ }
+
+ pr_debug("%s: sent P-va=%p, P-com=%x, P-size=%u\n", __func__,
+ p_msg->payload, p_msg->command,
+ (unsigned int)p_msg->payload_length);
+
+ p_data->paddr = 0;
+ list_for_each_entry(p_mem, &svc_data_mem, node) {
+ if (p_mem->vaddr == p_msg->payload) {
+ p_data->paddr = p_mem->paddr;
+ break;
+ }
+ }
+
+ p_data->command = p_msg->command;
+ p_data->size = p_msg->payload_length;
+ p_data->chan = chan;
+ pr_debug("%s: put to FIFO pa=0x%016x, cmd=%x, size=%u\n", __func__,
+ (unsigned int)p_data->paddr, p_data->command,
+ (unsigned int)p_data->size);
+ ret = kfifo_in_spinlocked(&chan->ctrl->svc_fifo, p_data,
+ sizeof(*p_data),
+ &chan->ctrl->svc_fifo_lock);
+
+ kfree(p_data);
+
+ if (!ret)
+ return -ENOBUFS;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_send);
+
+/**
+ * stratix10_svc_done() - complete service request transactions
+ * @chan: service channel assigned to the client
+ *
+ * This function should be called when client has finished its request
+ * or there is an error in the request process. It allows the service layer
+ * to stop the running thread to have maximize savings in kernel resources.
+ */
+void stratix10_svc_done(struct stratix10_svc_chan *chan)
+{
+ /* stop thread when thread is running AND only one active client */
+ if (chan->ctrl->task && chan->ctrl->num_active_client <= 1) {
+ pr_debug("svc_smc_hvc_shm_thread is stopped\n");
+ kthread_stop(chan->ctrl->task);
+ chan->ctrl->task = NULL;
+ }
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_done);
+
+/**
+ * stratix10_svc_allocate_memory() - allocate memory
+ * @chan: service channel assigned to the client
+ * @size: memory size requested by a specific service client
+ *
+ * Service layer allocates the requested number of bytes buffer from the
+ * memory pool, service client uses this function to get allocated buffers.
+ *
+ * Return: address of allocated memory on success, or ERR_PTR() on error.
+ */
+void *stratix10_svc_allocate_memory(struct stratix10_svc_chan *chan,
+ size_t size)
+{
+ struct stratix10_svc_data_mem *pmem;
+ unsigned long va;
+ phys_addr_t pa;
+ struct gen_pool *genpool = chan->ctrl->genpool;
+ size_t s = roundup(size, 1 << genpool->min_alloc_order);
+
+ pmem = devm_kzalloc(chan->ctrl->dev, sizeof(*pmem), GFP_KERNEL);
+ if (!pmem)
+ return ERR_PTR(-ENOMEM);
+
+ va = gen_pool_alloc(genpool, s);
+ if (!va)
+ return ERR_PTR(-ENOMEM);
+
+ memset((void *)va, 0, s);
+ pa = gen_pool_virt_to_phys(genpool, va);
+
+ pmem->vaddr = (void *)va;
+ pmem->paddr = pa;
+ pmem->size = s;
+ list_add_tail(&pmem->node, &svc_data_mem);
+ pr_debug("%s: va=%p, pa=0x%016x\n", __func__,
+ pmem->vaddr, (unsigned int)pmem->paddr);
+
+ return (void *)va;
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_allocate_memory);
+
+/**
+ * stratix10_svc_free_memory() - free allocated memory
+ * @chan: service channel assigned to the client
+ * @kaddr: memory to be freed
+ *
+ * This function is used by service client to free allocated buffers.
+ */
+void stratix10_svc_free_memory(struct stratix10_svc_chan *chan, void *kaddr)
+{
+ struct stratix10_svc_data_mem *pmem;
+ size_t size = 0;
+
+ list_for_each_entry(pmem, &svc_data_mem, node)
+ if (pmem->vaddr == kaddr) {
+ size = pmem->size;
+ break;
+ }
+
+ gen_pool_free(chan->ctrl->genpool, (unsigned long)kaddr, size);
+ pmem->vaddr = NULL;
+ list_del(&pmem->node);
+}
+EXPORT_SYMBOL_GPL(stratix10_svc_free_memory);
+
+static const struct of_device_id stratix10_svc_drv_match[] = {
+ {.compatible = "intel,stratix10-svc"},
+ {},
+};
+
+static int stratix10_svc_drv_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct stratix10_svc_controller *controller;
+ struct stratix10_svc_chan *chans;
+ struct gen_pool *genpool;
+ struct stratix10_svc_sh_memory *sh_memory;
+ svc_invoke_fn *invoke_fn;
+ size_t fifo_size;
+ int ret;
+
+ /* get SMC or HVC function */
+ invoke_fn = get_invoke_func(dev);
+ if (IS_ERR(invoke_fn))
+ return -EINVAL;
+
+ sh_memory = devm_kzalloc(dev, sizeof(*sh_memory), GFP_KERNEL);
+ if (!sh_memory)
+ return -ENOMEM;
+
+ sh_memory->invoke_fn = invoke_fn;
+ ret = svc_get_sh_memory(pdev, sh_memory);
+ if (ret)
+ return ret;
+
+ genpool = svc_create_memory_pool(pdev, sh_memory);
+ if (!genpool)
+ return -ENOMEM;
+
+ /* allocate service controller and supporting channel */
+ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
+ if (!controller)
+ return -ENOMEM;
+
+ chans = devm_kmalloc_array(dev, SVC_NUM_CHANNEL,
+ sizeof(*chans), GFP_KERNEL | __GFP_ZERO);
+ if (!chans)
+ return -ENOMEM;
+
+ controller->dev = dev;
+ controller->num_chans = SVC_NUM_CHANNEL;
+ controller->num_active_client = 0;
+ controller->chans = chans;
+ controller->genpool = genpool;
+ controller->task = NULL;
+ controller->invoke_fn = invoke_fn;
+ init_completion(&controller->complete_status);
+
+ fifo_size = sizeof(struct stratix10_svc_data) * SVC_NUM_DATA_IN_FIFO;
+ ret = kfifo_alloc(&controller->svc_fifo, fifo_size, GFP_KERNEL);
+ if (ret) {
+ dev_err(dev, "fails to allocate FIFO\n");
+ return ret;
+ }
+ spin_lock_init(&controller->svc_fifo_lock);
+
+ chans[0].scl = NULL;
+ chans[0].ctrl = controller;
+ chans[0].name = SVC_CLIENT_FPGA;
+ spin_lock_init(&chans[0].lock);
+
+ list_add_tail(&controller->node, &svc_ctrl);
+ platform_set_drvdata(pdev, controller);
+
+ pr_info("Intel Service Layer Driver Initialized\n");
+
+ return ret;
+}
+
+static int stratix10_svc_drv_remove(struct platform_device *pdev)
+{
+ struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev);
+
+ kfifo_free(&ctrl->svc_fifo);
+ if (ctrl->task) {
+ kthread_stop(ctrl->task);
+ ctrl->task = NULL;
+ }
+ if (ctrl->genpool)
+ gen_pool_destroy(ctrl->genpool);
+ list_del(&ctrl->node);
+
+ return 0;
+}
+
+static struct platform_driver stratix10_svc_driver = {
+ .probe = stratix10_svc_drv_probe,
+ .remove = stratix10_svc_drv_remove,
+ .driver = {
+ .name = "stratix10-svc",
+ .of_match_table = stratix10_svc_drv_match,
+ },
+};
+
+static int __init stratix10_svc_init(void)
+{
+ struct device_node *fw_np;
+ struct device_node *np;
+ int ret;
+
+ fw_np = of_find_node_by_name(NULL, "firmware");
+ if (!fw_np)
+ return -ENODEV;
+
+ np = of_find_matching_node(fw_np, stratix10_svc_drv_match);
+ if (!np) {
+ of_node_put(fw_np);
+ return -ENODEV;
+ }
+
+ of_node_put(np);
+ ret = of_platform_populate(fw_np, stratix10_svc_drv_match, NULL, NULL);
+ of_node_put(fw_np);
+ if (ret)
+ return ret;
+
+ return platform_driver_register(&stratix10_svc_driver);
+}
+
+static void __exit stratix10_svc_exit(void)
+{
+ return platform_driver_unregister(&stratix10_svc_driver);
+}
+
+subsys_initcall(stratix10_svc_init);
+module_exit(stratix10_svc_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Intel Stratix10 Service Layer Driver");
+MODULE_AUTHOR("Richard Gong <richard.gong@intel.com>");
+MODULE_ALIAS("platform:stratix10-svc");
diff --git a/include/linux/stratix10-svc-client.h b/include/linux/stratix10-svc-client.h
new file mode 100644
index 0000000..0ac6b2c
--- /dev/null
+++ b/include/linux/stratix10-svc-client.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018, Intel Corporation
+ */
+
+#ifndef __STRATIX10_SVC_CLIENT_H
+#define __STRATIX10_SVC_CLIENT_H
+
+/**
+ * Service layer driver supports client names
+ *
+ * fpga: for FPGA configuration
+ */
+#define SVC_CLIENT_FPGA "fpga"
+
+/**
+ * Status of the sent command, in bit number
+ *
+ * SVC_COMMAND_STATUS_RECONFIG_REQUEST_OK:
+ * Secure firmware accepts the request of FPGA reconfiguration.
+ *
+ * SVC_STATUS_RECONFIG_BUFFER_SUBMITTED:
+ * Service client successfully submits FPGA configuration
+ * data buffer to secure firmware.
+ *
+ * SVC_COMMAND_STATUS_RECONFIG_BUFFER_DONE:
+ * Secure firmware completes data process, ready to accept the
+ * next WRITE transaction.
+ *
+ * SVC_COMMAND_STATUS_RECONFIG_COMPLETED:
+ * Secure firmware completes FPGA configuration successfully, FPGA should
+ * be in user mode.
+ *
+ * SVC_COMMAND_STATUS_RECONFIG_BUSY:
+ * FPGA configuration is still in process.
+ *
+ * SVC_COMMAND_STATUS_RECONFIG_ERROR:
+ * Error encountered during FPGA configuration.
+ */
+#define SVC_STATUS_RECONFIG_REQUEST_OK 0
+#define SVC_STATUS_RECONFIG_BUFFER_SUBMITTED 1
+#define SVC_STATUS_RECONFIG_BUFFER_DONE 2
+#define SVC_STATUS_RECONFIG_COMPLETED 3
+#define SVC_STATUS_RECONFIG_BUSY 4
+#define SVC_STATUS_RECONFIG_ERROR 5
+
+/**
+ * Flag bit for COMMAND_RECONFIG
+ *
+ * COMMAND_RECONFIG_FLAG_PARTIAL:
+ * Set to FPGA configuration type (full or partial), the default
+ * is full reconfig.
+ */
+#define COMMAND_RECONFIG_FLAG_PARTIAL 0
+
+/**
+ * Timeout settings for service clients:
+ * timeout value used in Stratix10 FPGA manager driver.
+ */
+#define SVC_RECONFIG_REQUEST_TIMEOUT_MS 100
+#define SVC_RECONFIG_BUFFER_TIMEOUT_MS 240
+
+struct stratix10_svc_chan;
+
+/**
+ * enum stratix10_svc_command_code - supported service commands
+ *
+ * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting
+ *
+ * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status
+ * is SVC_STATUS_RECONFIG_REQUEST_OK
+ *
+ * @COMMAND_RECONFIG_DATA_SUBMIT: submit buffer(s) of bit-stream data for the
+ * FPGA configuration, return status is SVC_STATUS_RECONFIG_BUFFER_SUBMITTED,
+ * or SVC_STATUS_RECONFIG_ERROR
+ *
+ * @COMMAND_RECONFIG_DATA_CLAIM: check the status of the configuration, return
+ * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or
+ * SVC_STATUS_RECONFIG_ERROR
+ *
+ * @COMMAND_RECONFIG_STATUS: check the status of the configuration, return
+ * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or
+ * SVC_STATUS_RECONFIG_ERROR
+ */
+enum stratix10_svc_command_code {
+ COMMAND_NOOP = 0,
+ COMMAND_RECONFIG,
+ COMMAND_RECONFIG_DATA_SUBMIT,
+ COMMAND_RECONFIG_DATA_CLAIM,
+ COMMAND_RECONFIG_STATUS
+};
+
+/**
+ * struct stratix10_svc_client_msg - message sent by client to service
+ * @command: service command
+ * @payload: starting address of data need be processed
+ * @payload_length: data size in bytes
+ */
+struct stratix10_svc_client_msg {
+ void *payload;
+ size_t payload_length;
+ enum stratix10_svc_command_code command;
+};
+
+/**
+ * struct stratix10_svc_command_reconfig_payload - reconfig payload
+ * @flags: flag bit for the type of FPGA configuration
+ */
+struct stratix10_svc_command_reconfig_payload {
+ u32 flags;
+};
+
+/**
+ * struct stratix10_svc_cb_data - callback data structure from service layer
+ * @status: the status of sent command
+ * @kaddr1: address of 1st completed data block
+ * @kaddr2: address of 2nd completed data block
+ * @kaddr3: address of 3rd completed data block
+ */
+struct stratix10_svc_cb_data {
+ u32 status;
+ void *kaddr1;
+ void *kaddr2;
+ void *kaddr3;
+};
+
+/**
+ * struct stratix10_svc_client - service client structure
+ * @dev: the client device
+ * @receive_cb: callback to provide service client the received data
+ * @priv: client private data
+ */
+struct stratix10_svc_client {
+ struct device *dev;
+ void (*receive_cb)(struct stratix10_svc_client *client,
+ struct stratix10_svc_cb_data *cb_data);
+ void *priv;
+};
+
+/**
+ * stratix10_svc_request_channel_byname() - request service channel
+ * @client: identity of the client requesting the channel
+ * @name: supporting client name defined above
+ *
+ * Return: a pointer to channel assigned to the client on success,
+ * or ERR_PTR() on error.
+ */
+struct stratix10_svc_chan
+*stratix10_svc_request_channel_byname(struct stratix10_svc_client *client,
+ const char *name);
+
+/**
+ * stratix10_svc_free_channel() - free service channel.
+ * @chan: service channel to be freed
+ */
+void stratix10_svc_free_channel(struct stratix10_svc_chan *chan);
+
+/**
+ * stratix10_svc_allocate_memory() - allocate the momory
+ * @chan: service channel assigned to the client
+ * @size: number of bytes client requests
+ *
+ * Service layer allocates the requested number of bytes from the memory
+ * pool for the client.
+ *
+ * Return: the starting address of allocated memory on success, or
+ * ERR_PTR() on error.
+ */
+void *stratix10_svc_allocate_memory(struct stratix10_svc_chan *chan,
+ size_t size);
+
+/**
+ * stratix10_svc_free_memory() - free allocated memory
+ * @chan: service channel assigned to the client
+ * @kaddr: starting address of memory to be free back to pool
+ */
+void stratix10_svc_free_memory(struct stratix10_svc_chan *chan, void *kaddr);
+
+/**
+ * stratix10_svc_send() - send a message to the remote
+ * @chan: service channel assigned to the client
+ * @msg: message data to be sent, in the format of
+ * struct stratix10_svc_client_msg
+ *
+ * Return: 0 for success, -ENOMEM or -ENOBUFS on error.
+ */
+int stratix10_svc_send(struct stratix10_svc_chan *chan, void *msg);
+
+/**
+ * intel_svc_done() - complete service request
+ * @chan: service channel assigned to the client
+ *
+ * This function is used by service client to inform service layer that
+ * client's service requests are completed, or there is an error in the
+ * request process.
+ */
+void stratix10_svc_done(struct stratix10_svc_chan *chan);
+#endif
+
--
2.7.4
^ permalink raw reply related
* [PATCHv5 2/8] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Richard Gong <richard.gong@intel.com>
Add Intel Stratix10 service layer to the device tree
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
v3: No change
v4: s/service driver/stratix10 service driver/ in subject line
v5: No change
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index d8c94d5..c257287 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -24,6 +24,19 @@
#address-cells = <2>;
#size-cells = <2>;
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer at 0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -487,5 +500,13 @@
status = "disabled";
};
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCHv5 1/8] dt-bindings, firmware: add Intel Stratix10 service layer binding
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527179600-26441-1-git-send-email-richard.gong@linux.intel.com>
From: Richard Gong <richard.gong@intel.com>
Add a device tree binding for the Intel Stratix10 service layer driver
Signed-off-by: Richard Gong <richard.gong@intel.com>
Signed-off-by: Alan Tull <atull@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2: Change to put service layer driver node under the firmware node
Change compatible to "intel, stratix10-svc"
v3: No change
v4: Add Rob's Reviewed-by
v5: No change
---
.../bindings/firmware/intel,stratix10-svc.txt | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
new file mode 100644
index 0000000..1fa6606
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
@@ -0,0 +1,57 @@
+Intel Service Layer Driver for Stratix10 SoC
+============================================
+Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
+processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
+configured from HPS, there needs to be a way for HPS to notify SDM the
+location and size of the configuration data. Then SDM will get the
+configuration data from that location and perform the FPGA configuration.
+
+To meet the whole system security needs and support virtual machine requesting
+communication with SDM, only the secure world of software (EL3, Exception
+Layer 3) can interface with SDM. All software entities running on other
+exception layers must channel through the EL3 software whenever it needs
+service from SDM.
+
+Intel Stratix10 service layer driver, running at privileged exception level
+(EL1, Exception Layer 1), interfaces with the service providers and provides
+the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
+driver also manages secure monitor call (SMC) to communicate with secure monitor
+code running in EL3.
+
+Required properties:
+-------------------
+The svc node has the following mandatory properties, must be located under
+the firmware node.
+
+- compatible: "intel,stratix10-svc"
+- method: smc or hvc
+ smc - Secure Monitor Call
+ hvc - Hypervisor Call
+- memory-region:
+ phandle to the reserved memory node. See
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+ for details
+
+Example:
+-------
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer at 0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ };
+ };
--
2.7.4
^ permalink raw reply related
* [PATCHv5 0/8] Add Intel Stratix10 FPGA manager and service layer
From: richard.gong at linux.intel.com @ 2018-05-24 16:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Richard Gong <richard.gong@intel.com>
This is the 5th submission of Intel stratix10 service layer patches. Intel
Stratix10 FPGA manager, which is 1st Stratix10 service layer client, is
included in this submission.
Stratix10 service layer patches have been reviewed internally by Alan Tull
and other colleagues at Intel.
Some features of the Intel Stratix10 SoC require a level of privilege
higher than the kernel is granted. Such secure features include
FPGA programming. In terms of the ARMv8 architecture, the kernel runs
at Exception Level 1 (EL1), access to the features requires
Exception Level 3 (EL3).
The Intel Stratix10 service layer provides an in kernel API for drivers to
request access to the secure features. The requests are queued and
processed one by one. ARM?s SMCCC is used to pass the execution of the
requests on to a secure monitor (EL3).
Later the Intel Stratix10 service layer driver will be extended to provide
services for QSPI, Crypto and warm reset.
v2: add patches for FPGA manager, FPGA manager binding, dts and defconfig
remove intel-service subdirectory and intel-service.h, move intel-smc.h
and intel-service.c to driver/misc subdirectory
remove global variables
change service layer driver be 'default n'
correct SPDX markers
add timeout for do..while() loop
add kernel-doc for the functions and structs, correct multiline comments
replace kfifo_in/kfifo_out with kfifo_in_spinlocked/kfifo_out_spinlocked
rename struct intel_svc_data (at client header) to intel_svc_client_msg
rename struct intel_svc_private_mem to intel_svc_data
other corrections/changes from Intel internal code reviews
v3: change all exported functions with "intel_svc_" as the prefix
increase timeout values for claiming back submitted buffer(s)
rename struct intel_command_reconfig_payload to
struct intel_svc_command_reconfig_payload
add pr_err() to provide the error return value
change to put fpga_mgr node under firmware/svc node
change to FPGA manager to align the update of service client APIs, and the
update of fpga_mgr device node
Other corrections/changes
v4: s/intel/stratix10/ on some variables, structs, functions, and file names
intel-service.c -> stratix10-svc.c
intel-smc.h -> stratix10-smc.h
intel-service-client.h -> stratix10-svc-client.h
remove non-kernel-doc formatting
s/fpga-mgr at 0/fpga-mgr/ to remove unit_address at fpga_mgr node
add Rob's Reviewed-by
add Richard's signed-off-by
v5: add a new API statix10_svc_done() which is called by service client
when client request is completed or error occurs during request
process. Which allows service layer to free its resources.
remove dummy client from service layer client header and service layer
source file.
add Rob's Reviewed-by
add a new file stratix10-svc.rst and add that to driver-api/index.rst
kernel-doc fixes
Alan Tull (3):
dt-bindings: fpga: add Stratix10 SoC FPGA manager binding
arm64: dts: stratix10: add fpga manager and region
fpga: add intel stratix10 soc fpga manager driver
Richard Gong (5):
dt-bindings, firmware: add Intel Stratix10 service layer binding
arm64: dts: stratix10: add stratix10 service driver binding to base
dtsi
driver, misc: add Intel Stratix10 service layer driver
defconfig: enable fpga and service layer
Documentation: driver-api: add stratix10 service layer
.../bindings/firmware/intel,stratix10-svc.txt | 57 ++
.../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17 +
Documentation/driver-api/index.rst | 1 +
Documentation/driver-api/stratix10-svc.rst | 32 +
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 33 +
arch/arm64/configs/defconfig | 6 +
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/stratix10-soc.c | 545 ++++++++++++
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/stratix10-smc.h | 205 +++++
drivers/misc/stratix10-svc.c | 984 +++++++++++++++++++++
include/linux/stratix10-svc-client.h | 199 +++++
14 files changed, 2099 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
create mode 100644 Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
create mode 100644 Documentation/driver-api/stratix10-svc.rst
create mode 100644 drivers/fpga/stratix10-soc.c
create mode 100644 drivers/misc/stratix10-smc.h
create mode 100644 drivers/misc/stratix10-svc.c
create mode 100644 include/linux/stratix10-svc-client.h
--
2.7.4
^ permalink raw reply
* [PATCH] arm64: dts: msm8916: fix Coresight ETF graph connections
From: Mathieu Poirier @ 2018-05-24 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524044853.713.23166@silver>
On 23 May 2018 at 22:48, Ivan T. Ivanov <iivanov.xz@gmail.com> wrote:
> Quoting Rob Herring (2018-05-23 23:29:29)
>> On Tue, May 8, 2018 at 10:09 AM, Rob Herring <robh@kernel.org> wrote:
>> > The ETF input should be connected to the funnel output, and the ETF
>> > output should be connected to the replicator input. The labels are wrong
>> > and these got swapped:
>> >
>> > Warning (graph_endpoint): /soc/funnel at 821000/ports/port at 8/endpoint: graph connection to node '/soc/etf at 825000/ports/port at 1/endpoint' is not bidirectional
>> > Warning (graph_endpoint): /soc/replicator at 824000/ports/port at 2/endpoint: graph connection to node '/soc/etf at 825000/ports/port at 0/endpoint' is not bidirectional
>> >
>> > Fixes: 7c10da373698 ("arm64: dts: qcom: Add msm8916 CoreSight components")
>> > Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
>> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> > Cc: Andy Gross <andy.gross@linaro.org>
>> > Cc: David Brown <david.brown@linaro.org>
>> > Cc: linux-arm-msm at vger.kernel.org
>> > Signed-off-by: Rob Herring <robh@kernel.org>
>> > ---
>> > arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
>> > 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> Ping. Still seeing warnings in -next for these.
>>
>
> Hi Rob,
>
> I no longer have access to this hardware and documentation.
> I am sure that Mathieu and friends will take care for verification
> of this patch :-)
The code triggers on the "slave-mode" property rather than the labels,
so this patch has no effect on how a path is established. I've tested
this on a 410c and things look good.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> Regards,
> Ivan
>
^ permalink raw reply
* [PATCH v3 3/6] arm64: irqflags: Use ICC sysregs to implement IRQ masking
From: Marc Zyngier @ 2018-05-24 16:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526902515-13769-4-git-send-email-julien.thierry@arm.com>
Hi Julien,
On 21/05/18 12:35, Julien Thierry wrote:
> From: Daniel Thompson <daniel.thompson@linaro.org>
>
> Currently irqflags is implemented using the PSR's I bit. It is possible
> to implement irqflags by using the co-processor interface to the GIC.
> Using the co-processor interface makes it feasible to simulate NMIs
> using GIC interrupt prioritization.
>
> This patch changes the irqflags macros to modify, save and restore
> ICC_PMR_EL1. This has a substantial knock on effect for the rest of
> the kernel. There are four reasons for this:
>
> 1. The state of the PMR becomes part of the interrupt context and must be
> saved and restored during exceptions. It is saved on the stack as part
> of the saved context when an interrupt/exception is taken.
>
> 2. The hardware automatically masks the I bit (at boot, during traps, etc).
> When the I bit is set by hardware we must add code to switch from I
> bit masking and PMR masking:
> - For IRQs, this is done after the interrupt has been acknowledged
> avoiding the need to unmask.
> - For other exceptions, this is done right after saving the context.
>
> 3. Some instructions, such as wfi, require that the PMR not be used
> for interrupt masking. Before calling these instructions we must
> switch from PMR masking to I bit masking.
> This is also the case when KVM runs a guest, if the CPU receives
> an interrupt from the host, interrupts must not be masked in PMR
> otherwise the GIC will not signal it to the CPU.
>
> 4. We use the alternatives system to allow a single kernel to boot and
> be switched to the alternative masking approach at runtime.
>
> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
> [julien.thierry at arm.com: changes reflected in commit,
> message, fixes, renaming]
> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Christoffer Dall <christoffer.dall@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: James Morse <james.morse@arm.com>
> ---
> arch/arm64/Kconfig | 15 ++++
> arch/arm64/include/asm/arch_gicv3.h | 20 ++++++
> arch/arm64/include/asm/assembler.h | 25 ++++++-
> arch/arm64/include/asm/daifflags.h | 36 +++++++---
> arch/arm64/include/asm/efi.h | 5 ++
> arch/arm64/include/asm/irqflags.h | 125 +++++++++++++++++++++++++++++++++
> arch/arm64/include/asm/kvm_host.h | 14 ++++
> arch/arm64/include/asm/processor.h | 4 ++
> arch/arm64/include/asm/ptrace.h | 14 +++-
> arch/arm64/kernel/asm-offsets.c | 1 +
> arch/arm64/kernel/entry.S | 28 ++++++--
> arch/arm64/kernel/head.S | 37 ++++++++++
> arch/arm64/kernel/process.c | 6 ++
> arch/arm64/kernel/smp.c | 8 +++
> arch/arm64/kvm/hyp/switch.c | 25 +++++++
> arch/arm64/mm/fault.c | 5 +-
> arch/arm64/mm/proc.S | 23 ++++++
> drivers/irqchip/irq-gic-v3-its.c | 2 +-
> drivers/irqchip/irq-gic-v3.c | 82 +++++++++++----------
> include/linux/irqchip/arm-gic-common.h | 6 ++
> include/linux/irqchip/arm-gic.h | 5 --
> 21 files changed, 423 insertions(+), 63 deletions(-)
I've commented about this particular patch offline, but let me state it
on the list:
As it is, this patch is almost impossible to review. It turns the
interrupt masking upside down, messes with the GIC, hacks KVM... Too
many things change at once, and I find it very hard to build a mental
picture of the changes just by staring at it.
Can you please try to split it into related chunks, moving the enabling
of the feature right at the end, so that the reviewers can have a chance
to understand it? It should make it much easier to review.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v3 4/6] watchdog: sp805: set WDOG_HW_RUNNING when appropriate
From: Guenter Roeck @ 2018-05-24 16:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527120924-12131-5-git-send-email-ray.jui@broadcom.com>
On Wed, May 23, 2018 at 05:15:22PM -0700, Ray Jui wrote:
> If the watchdog hardware is already enabled during the boot process,
> when the Linux watchdog driver loads, it should reset the watchdog and
> tell the watchdog framework. As a result, ping can be generated from
> the watchdog framework, until the userspace watchdog daemon takes over
> control
>
> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
> Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
I have one question, though: Is it really correct that both
INT_ENABLE _and_ RESET_ENABLE have to be set to enable the watdog ?
What if only RESET_ENABLE is set ?
Thanks,
Guenter
> ---
> drivers/watchdog/sp805_wdt.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
> index 1484609..d662a6f 100644
> --- a/drivers/watchdog/sp805_wdt.c
> +++ b/drivers/watchdog/sp805_wdt.c
> @@ -42,6 +42,7 @@
> /* control register masks */
> #define INT_ENABLE (1 << 0)
> #define RESET_ENABLE (1 << 1)
> + #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
> #define WDTINTCLR 0x00C
> #define WDTRIS 0x010
> #define WDTMIS 0x014
> @@ -74,6 +75,15 @@ module_param(nowayout, bool, 0);
> MODULE_PARM_DESC(nowayout,
> "Set to 1 to keep watchdog running after device release");
>
> +/* returns true if wdt is running; otherwise returns false */
> +static bool wdt_is_running(struct watchdog_device *wdd)
> +{
> + struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
> + u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
> +
> + return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
> +}
> +
> /* This routine finds load value that will reset system in required timout */
> static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
> {
> @@ -239,6 +249,15 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
> watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
> wdt_setload(&wdt->wdd, wdt->wdd.timeout);
>
> + /*
> + * If HW is already running, enable/reset the wdt and set the running
> + * bit to tell the wdt subsystem
> + */
> + if (wdt_is_running(&wdt->wdd)) {
> + wdt_enable(&wdt->wdd);
> + set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
> + }
> +
> ret = watchdog_register_device(&wdt->wdd);
> if (ret) {
> dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v3 2/6] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Guenter Roeck @ 2018-05-24 16:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527120924-12131-3-git-send-email-ray.jui@broadcom.com>
On Wed, May 23, 2018 at 05:15:20PM -0700, Ray Jui wrote:
> Update the SP805 binding document to add optional 'timeout-sec'
> devicetree property
>
> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
> ---
> Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> index 0fa3629..1debea3 100644
> --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> @@ -19,6 +19,8 @@ Required properties:
>
> Optional properties:
> - interrupts: Should specify WDT interrupt number
> +- timeout-sec: Should specify default WDT timeout in seconds. If unset, the
> + default timeout in the driver is 30 seconds
"... the default timeout is determined by the driver" might be better.
If you want to mandate a default here (not sure if that is a good idea),
I would suggest to use something like "should be 30 seconds".
Guenter
>
> Example:
> watchdog at 66090000 {
> --
> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/5] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Guenter Roeck @ 2018-05-24 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <91d27df4-29d0-de7f-6805-c3e5f329caf3@arm.com>
On Thu, May 24, 2018 at 02:25:34PM +0100, Robin Murphy wrote:
> On 23/05/18 19:10, Guenter Roeck wrote:
> >On Wed, May 23, 2018 at 11:57:25AM +0100, Robin Murphy wrote:
> >>On 22/05/18 19:47, Ray Jui wrote:
> >>>Update the SP805 binding document to add optional 'timeout-sec'
> >>>devicetree property
> >>>
> >>>Signed-off-by: Ray Jui <ray.jui@broadcom.com>
> >>>Reviewed-by: Scott Branden <scott.branden@broadcom.com>
> >>>---
> >>> Documentation/devicetree/bindings/watchdog/sp805-wdt.txt | 2 ++
> >>> 1 file changed, 2 insertions(+)
> >>>
> >>>diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
> >>>index edc4f0e..f898a86 100644
> >>>--- a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
> >>>+++ b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
> >>>@@ -19,6 +19,8 @@ Required properties:
> >>> Optional properties:
> >>> - interrupts : Should specify WDT interrupt number.
> >>>+- timeout-sec : Should specify default WDT timeout in seconds. If unset, the
> >>>+ default timeout is 30 seconds
> >>
> >>According to the SP805 TRM, the default interval is dependent on the rate of
> >>WDOGCLK, but would typically be a lot longer than that :/
> >>
> >Depends on the definition of "default". In the context of watchdog drivers,
> >it is (or should be) a driver default, not a chip default.
>
> DT describes hardware, not driver behaviour.
>
In this case it describes expected system behavior. Most definitely
it does not describe some hardware default.
Please note that I do not engage in discussions I consider bike-shedding.
This is one of those. Dropping out.
Guenter
^ permalink raw reply
* [PATCH v3 5/6] spi: at91-usart: add driver for at91-usart as spi
From: Radu Pirea @ 2018-05-24 16:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180517045437.GE20254@sirena.org.uk>
On 05/17/2018 07:54 AM, Mark Brown wrote:
> On Tue, May 15, 2018 at 12:22:24PM +0300, Radu Pirea wrote:
>> On Mon, 2018-05-14 at 20:38 +0300, Andy Shevchenko wrote:
>
>>> So, what is not going as expected in "SPI core takes care of CSs"
>>> case?
>>> Did you use oscilloscope for that?
>
>> Yes, I used and CSs was not asserted. Anyway, I will will try again.
>
> If the core chip select handling is not working properly for some reason
> then the core chip select handling should be fixed rather than just open
> coding in your driver - probably it's also broken for other users.
>
Hi Mark,
I found the fix for cs-gpios. If I change spi_add_device function like
this(see below) everything is ok.
int spi_add_device(struct spi_device *spi)
...
if (ctlr->cs_gpios){
spi->cs_gpio = ctlr->cs_gpios[spi->chip_select];
if(gpio_is_valid(spi->cs_gpio))
gpio_direction_output(spi->cs_gpio, !(spi->mode &
SPI_CS_HIGH));
}
...
return status;
}
In the subsystem gpio direction of pins is never set and
gpio_set_value() don't set the direction.
In my opinion gpio_direction_output() set direction should be called in
spi_add_device. What do you think? Is ok?
^ permalink raw reply
* [PATCH v4 2/2] arm64: signal: Report signal frame size to userspace via auxv
From: Dave Martin @ 2018-05-24 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524124918.GG8689@arm.com>
On Thu, May 24, 2018 at 01:49:21PM +0100, Will Deacon wrote:
> On Wed, May 23, 2018 at 06:46:56PM +0100, Dave Martin wrote:
> > Stateful CPU architecture extensions may require the signal frame
> > to grow to a size that exceeds the arch's MINSIGSTKSZ #define.
> > However, changing this #define is an ABI break.
> >
> > To allow userspace the option of determining the signal frame size
> > in a more forwards-compatible way, this patch adds a new auxv entry
> > tagged with AT_MINSIGSTKSZ, which provides the maximum signal frame
> > size that the process can observe during its lifetime.
> >
> > If AT_MINSIGSTKSZ is absent from the aux vector, the caller can
> > assume that the MINSIGSTKSZ #define is sufficient. This allows for
> > a consistent interface with older kernels that do not provide
> > AT_MINSIGSTKSZ.
> >
> > The idea is that libc could expose this via sysconf() or some
> > similar mechanism.
> >
> > There is deliberately no AT_SIGSTKSZ. The kernel knows nothing
> > about userspace's own stack overheads and should not pretend to
> > know.
>
> [...]
>
> > diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
> > index fac1c4d..9c18f0e 100644
> > --- a/arch/arm64/include/asm/elf.h
> > +++ b/arch/arm64/include/asm/elf.h
> > @@ -121,6 +121,9 @@
> >
> > #ifndef __ASSEMBLY__
> >
> > +#include <linux/bug.h>
> > +#include <asm/processor.h> /* for signal_minsigstksz, used by ARCH_DLINFO */
> > +
> > typedef unsigned long elf_greg_t;
> >
> > #define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
> > @@ -148,6 +151,14 @@ typedef struct user_fpsimd_state elf_fpregset_t;
> > do { \
> > NEW_AUX_ENT(AT_SYSINFO_EHDR, \
> > (elf_addr_t)current->mm->context.vdso); \
> > + \
> > + /* \
> > + * Should always be nonzero unless there's a kernel bug. If \
> > + * the we haven't determined a sensible value to give to \
>
> "If the we"?
Dang, fixed locally now.
[...]
> > diff --git a/arch/arm64/include/uapi/asm/auxvec.h b/arch/arm64/include/uapi/asm/auxvec.h
> > index ec0a86d..743c0b8 100644
> > --- a/arch/arm64/include/uapi/asm/auxvec.h
> > +++ b/arch/arm64/include/uapi/asm/auxvec.h
> > @@ -19,7 +19,8 @@
> >
> > /* vDSO location */
> > #define AT_SYSINFO_EHDR 33
> > +#define AT_MINSIGSTKSZ 51 /* stack needed for signal delivery */
>
> Curious: but how do we avoid/detect conflicts at -rc1? I guess somebody just
> needs to remember to run grep? (I know you have another series consolidating
> the ID allocations).
We basically can't. These are spread over various arch headers today,
so the solution is to (a) grep, and (b) know that you needed to do that.
This is the main motivation for collecting the definitions together.
Short of having some script that checks these at build-time, I couldn't
see another obvious solution. It's nonetheless a bit ugly because of
things like AT_VECTOR_SIZE_ARCH which is masquerading a tag but isn't
one, and obviously does vary across arches...
[...]
> > diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
> > index 154b7d3..00b9990 100644
> > --- a/arch/arm64/kernel/signal.c
> > +++ b/arch/arm64/kernel/signal.c
[...]
> > @@ -936,3 +949,28 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
> > thread_flags = READ_ONCE(current_thread_info()->flags);
> > } while (thread_flags & _TIF_WORK_MASK);
> > }
> > +
> > +unsigned long __ro_after_init signal_minsigstksz;
> > +
> > +/*
> > + * Determine the stack space required for guaranteed signal devliery.
> > + * This function is used to populate AT_MINSIGSTKSZ at process startup.
> > + * cpufeatures setup is assumed to be complete.
> > + */
> > +void __init minsigstksz_setup(void)
> > +{
> > + struct rt_sigframe_user_layout user;
> > +
> > + init_user_layout(&user);
> > +
> > + /*
> > + * If this fails, SIGFRAME_MAXSZ needs to be enlarged. It won't
> > + * be big enough, but it's our best guess:
> > + */
> > + if (WARN_ON(setup_sigframe_layout(&user, true)))
> > + signal_minsigstksz = SIGFRAME_MAXSZ;
>
> Can we not leave signal_minsigstksz as zero in this case?
I prefer to distinguish the "kernel went wrong" case (where we just omit
AT_MINSIGSTKSZ for backwards compatibilty) from the "sigframe too
large" case.
Thanks to the vagueries of C stack sizing is rarely an exact science,
so there is merit in telling userspace a size that is approimately
correct even if it's not quite big enough. So if the frame would be
larger than SIGFRAME_MAXSZ then it seems preferable to at least steer
userspace towards allocating bigger stacks rather than just letting
userspace fall back to MINSIGSTKSZ (which is likely to be much too
small in this scenario).
These are things that Should Not Happen (tm), so this distinction
might be viewed as overkill, but that was my rationale anyway.
What do you think?
Cheers
---Dave
^ permalink raw reply
* [PATCH 2/4] arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set
From: Catalin Marinas @ 2018-05-24 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180517103548.5622-3-marc.zyngier@arm.com>
On Thu, May 17, 2018 at 11:35:46AM +0100, Marc Zyngier wrote:
> On systems where CTR_EL0.DIC is set, we don't need to perform
> icache invalidation to guarantee that we'll fetch the right
> instruction stream.
>
> This also means that taking a permission fault to invalidate the
> icache is an unnecessary overhead.
>
> On such systems, we can safely leave the page as being executable.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH 1/4] arm64: KVM: Add support for Stage-2 control of memory types and cacheability
From: Catalin Marinas @ 2018-05-24 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180517103548.5622-2-marc.zyngier@arm.com>
On Thu, May 17, 2018 at 11:35:45AM +0100, Marc Zyngier wrote:
> Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
> results in the strongest attribute of the two stages. This means
> that the hypervisor has to perform quite a lot of cache maintenance
> just in case the guest has some non-cacheable mappings around.
>
> ARMv8.4 solves this problem by offering a different mode (FWB) where
> Stage-2 has total control over the memory attribute (this is limited
> to systems where both I/O and instruction caches are coherent with
> the dcache). This is achieved by having a different set of memory
> attributes in the page tables, and a new bit set in HCR_EL2.
>
> On such a system, we can then safely sidestep any form of dcache
> management.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
For the core arm64 bits:
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* [PATCH 3/4] KVM: arm/arm64: Remove unnecessary CMOs when creating HYP page tables
From: Catalin Marinas @ 2018-05-24 15:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180517103548.5622-4-marc.zyngier@arm.com>
On Thu, May 17, 2018 at 11:35:47AM +0100, Marc Zyngier wrote:
> There is no need to perform cache maintenance operations when
> creating the HYP page tables if we have the multiprocessing
> extensions. ARMv7 mandates them with the virtualization support,
> and ARMv8 just mandates them unconditionally.
>
> Let's remove these operations.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> virt/kvm/arm/mmu.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index ba66bf7ae299..acbfea09578c 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -578,7 +578,6 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
> pte = pte_offset_kernel(pmd, addr);
> kvm_set_pte(pte, pfn_pte(pfn, prot));
> get_page(virt_to_page(pte));
> - kvm_flush_dcache_to_poc(pte, sizeof(*pte));
> pfn++;
> } while (addr += PAGE_SIZE, addr != end);
> }
> @@ -605,7 +604,6 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
> }
> pmd_populate_kernel(NULL, pmd, pte);
> get_page(virt_to_page(pmd));
> - kvm_flush_dcache_to_poc(pmd, sizeof(*pmd));
> }
>
> next = pmd_addr_end(addr, end);
> @@ -638,7 +636,6 @@ static int create_hyp_pud_mappings(pgd_t *pgd, unsigned long start,
> }
> pud_populate(NULL, pud, pmd);
> get_page(virt_to_page(pud));
> - kvm_flush_dcache_to_poc(pud, sizeof(*pud));
> }
>
> next = pud_addr_end(addr, end);
> @@ -675,7 +672,6 @@ static int __create_hyp_mappings(pgd_t *pgdp, unsigned long ptrs_per_pgd,
> }
> pgd_populate(NULL, pgd, pud);
> get_page(virt_to_page(pgd));
> - kvm_flush_dcache_to_poc(pgd, sizeof(*pgd));
> }
>
> next = pgd_addr_end(addr, end);
> @@ -685,6 +681,7 @@ static int __create_hyp_mappings(pgd_t *pgdp, unsigned long ptrs_per_pgd,
> pfn += (next - addr) >> PAGE_SHIFT;
> } while (addr = next, addr != end);
> out:
> + dsb(ishst);
> mutex_unlock(&kvm_hyp_pgd_mutex);
Why do we need the DSB here? A comment would help.
If a DMB is sufficient, I think mutex_unlock has release semantics.
--
Catalin
^ permalink raw reply
* [PATCH 9/9] PM / Domains: Add dev_pm_domain_attach_by_id() to manage multi PM domains
From: Jon Hunter @ 2018-05-24 15:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526639490-12167-10-git-send-email-ulf.hansson@linaro.org>
On 18/05/18 11:31, Ulf Hansson wrote:
> The existing dev_pm_domain_attach() function, allows a single PM domain to
> be attached per device. To be able to support devices that are partitioned
> across multiple PM domains, let's introduce a new interface,
> dev_pm_domain_attach_by_id().
>
> The dev_pm_domain_attach_by_id() returns a new allocated struct device with
> the corresponding attached PM domain. This enables for example a driver to
> operate on the new device from a power management point of view. The driver
> may then also benefit from using the received device, to set up so called
> device-links towards its original device. Depending on the situation, these
> links may then be dynamically changed.
>
> The new interface is typically called by drivers during their probe phase,
> in case they manages devices which uses multiple PM domains. If that is the
> case, the driver also becomes responsible of managing the detaching of the
> PM domains, which typically should be done at the remove phase. Detaching
> is done by calling the existing dev_pm_domain_detach() function and for
> each of the received devices from dev_pm_domain_attach_by_id().
>
> Note, currently its only genpd that supports multiple PM domains per
> device, but dev_pm_domain_attach_by_id() can easily by extended to cover
> other PM domain types, if/when needed.
>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
> drivers/base/power/common.c | 33 ++++++++++++++++++++++++++++++++-
> include/linux/pm_domain.h | 7 +++++++
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
> index 7ae62b6..d3db974 100644
> --- a/drivers/base/power/common.c
> +++ b/drivers/base/power/common.c
> @@ -117,13 +117,44 @@ int dev_pm_domain_attach(struct device *dev, bool power_on)
> EXPORT_SYMBOL_GPL(dev_pm_domain_attach);
>
> /**
> + * dev_pm_domain_attach_by_id - Attach a device to one of its PM domains.
Isn't this more of a 'get'?
> + * @index: The index of the PM domain.
> + * @dev: Device to attach.
Isn't this just the device associated with the PM domain we are getting?
> + *
> + * As @dev may only be attached to a single PM domain, the backend PM domain
> + * provider should create a virtual device to attach instead. As attachment
> + * succeeds, the ->detach() callback in the struct dev_pm_domain should be
> + * assigned by the corresponding backend attach function.
> + *
> + * This function should typically be invoked from drivers during probe phase.
> + * Especially for those that manages devices which requires power management
> + * through more than one PM domain.
> + *
> + * Callers must ensure proper synchronization of this function with power
> + * management callbacks.
> + *
> + * Returns the virtual attached device in case successfully attached PM domain,
> + * NULL in case @dev don't need a PM domain, else a PTR_ERR().
Should this be 'NULL in the case where the @dev already has a power-domain'?
> + */
> +struct device *dev_pm_domain_attach_by_id(struct device *dev,
> + unsigned int index)
> +{
> + if (dev->pm_domain)
I wonder if this is worthy of a ...
if (WARN_ON(dev->pm_domain))
> + return NULL;
Don't we consider this an error case? I wonder why not return PTR_ERR
here as well? This would be consistent with dev_pm_domain_attach().
Cheers
Jon
--
nvpublic
^ permalink raw reply
* [PATCH 1/6] coresight: remove CORESIGHT_LINKS_AND_SINKS dependencies and selections
From: Mathieu Poirier @ 2018-05-24 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180523145155.5929dd09c78a056ef19329be@arm.com>
On 23 May 2018 at 13:51, Kim Phillips <kim.phillips@arm.com> wrote:
> On Tue, 22 May 2018 11:31:40 -0600
> Mathieu Poirier <mathieu.poirier@linaro.org> wrote:
>
>> On Thu, May 17, 2018 at 08:20:19PM -0500, Kim Phillips wrote:
>> > A coresight topology doesn't need to include links, i.e., a source can
>> > be directly connected to a sink. As such, selecting and/or depending on
>> > LINKS_AND_SINKS is no longer needed.
>>
>> I'm good with this patch but now the help text for CORESIGHT_LINKS_AND_SINKS no
>> longer match what the config does. I see two ways to fix this:
>
> This patch doesn't change what the config does, it just changes what
> other config options depend on it.
>
>> 1) Rework the help text.
>
> I don't see how, given the above. Here's the text:
>
> config CORESIGHT_LINKS_AND_SINKS
> bool "CoreSight Link and Sink drivers"
> help
> This enables support for CoreSight link and sink drivers that are
> responsible for transporting and collecting the trace data
> respectively. Link and sinks are dynamically aggregated with a trace
> entity at run time to form a complete trace path.
>
> What part of that becomes invalid with this patch?
Looking at the new Kconfig, what sink component depend on
CORESIGHT_LINKS_AND_SINKS?
config CORESIGHT_LINKS
bool "CoreSight Link drivers"
help
This enables support for CoreSight link drivers that are responsible
for transporting trace data from source to sink. Links are
dynamically
aggregated with other traces entities at run time to form a
complete trace
path.
>
>> 2) Rework CORESIGHT_LINKS_AND_SINKS to be CORESIGHT_FUNNEL and move
>> coresight-replicator.o under CORESIGHT_DYNAMIC_REPLICATOR in the Makefile. I
>> really liked your idea of making the replicator driver intelligent enough to
>> deal with both DT and platform declaration, which merges two driver into one.
>>
>> I'm obviously favouring the second option but recognise it doesn't have to be
>> part of this patchet. So for this set please rework the help text for
>> CORESIGHT_LINKS_AND_SINKS. Once we've dealt with this topic we can refactor the
>> replicator driver.
>
> I'd really like to just focus on getting CoreSight to load as modules,
> something for which this patch isn't technically required...
The only thing I'm asking is that the config description and help text
reflect what the Makefile does.
>
> Thanks,
>
> Kim
^ permalink raw reply
* [PATCH v2 4/7] Bluetooth: Add new quirk for non-persistent setup settings
From: Sean Wang @ 2018-05-24 15:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <37400FCE-8F9A-433B-8E3A-DE9CBEB469D7@holtmann.org>
On Thu, 2018-05-24 at 09:47 +0200, Marcel Holtmann wrote:
> Hi Sean,
>
> >>>>
> >>>> [ ... ]
[ ... ]
> > I post it as plain text as below
> >
> >
> > Bluetooth monitor ver 5.37
> > = Note: Linux version 4.16.0-rc1+ (aarch64) 0.641494
> > = Note: Bluetooth subsystem version 2.22 0.641502
> > = New Index: 00:00:46:76:22:01 (BR/EDR,UART,hci0) [hci0] 0.641505
> > * Unknown packet (code 14 len 30) 0.641509
> > 01 00 00 00 02 00 01 0e 00 01 00 00 00 10 62 6c ..............bl
> > 75 65 74 6f 6f 74 68 64 00 00 00 00 00 00 uetoothd......
> > * Unknown packet (code 14 len 30) 0.641592
> > 02 00 00 00 02 00 01 0e 00 01 00 00 00 10 62 74 ..............bt
> > 6d 6f 6e 00 00 00 00 00 00 00 00 00 00 00 mon...........
> > * Unknown packet (code 16 len 7) [hci0] 6.536771
> > 01 00 00 00 05 00 01 .......
> > = Open Index: 00:00:46:76:22:01 [hci0] 6.717019
> > = Index Info: 00:00:46:76:22:01 (MediaTek, Inc.) [hci0] 6.717030
>
> can you try with the latest BlueZ 5.49 or git version. Seems it actually stumbles over the extra packet here. Fun fact is that I can not get a backtrace to pin-point the issue in btmon and why it crashes.
>
I had less experience updating user land BlueZ, but I can try it as possible and see whether Unknown packets still are present at newest version BlueZ. Hopefully I don't misunderstand your point here.
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.741093
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.742088
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.743102
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.744105
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.745109
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.746104
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.747097
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.748090
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.749078
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.750070
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.751061
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.752054
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.753046
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.754038
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.755031
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.756025
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.757013
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.758006
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.758999
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.759991
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.760983
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.761975
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.762963
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.763956
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.764948
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.765941
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.766933
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.767926
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.768919
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.769914
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.770909
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.771908
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.772904
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.773898
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.774892
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.775890
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.776882
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.777877
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.778871
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.779869
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.780864
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.781858
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.782852
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.783850
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.784845
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.785839
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.786833
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.787831
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.788826
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.789820
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.790814
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.791813
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.792809
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.793803
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.794798
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.795797
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.796791
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.797786
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.798779
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.799778
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.800774
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.801769
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.802763
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.803761
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.804755
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.805749
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.806743
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.807741
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.808737
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.809731
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.810725
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.811725
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.812719
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.813714
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.814708
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.815705
> > 02 01 01 00 00 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.816378
> > 02 01 01 00 00 .....
>
> Why do I see only HCI events here? Is this event conveying any useful information. It is kinda complicated that this is 0xe4 event code which is actually reserved for future use by the Bluetooth SIG. Are there any accompanying HCI commands for this and they just not make it into btmon?
>
I have made all vendor HCI commands go through BlueZ core in v2 patch.
And for these HCI events, they are all corresponding to vendor ACL data, applied only to firmware setup packets, but they're not being sent via BlueZ core, so they are not being logged in btmon.
As for its event, where heading 0xe4 refers to a vendor event and is used on notification of that either vendor ACL data or vendor HCI command have been done.
>
>
> > < HCI Command: Vendor (0x3f|0x006f) plen 5 [hci0] 6.816413
> > 01 07 01 00 04 .....
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 6.816536
> > 02 07 01 00 00 .....
> > < HCI Command: Vendor (0x3f|0x006f) plen 6 [hci0] 8.845071
> > 01 06 02 00 00 01 ......
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 8.923456
> > 02 06 01 00 00 .....
>
> Here it looks like you have 0x006f opcode with first octet 0x01 for command and then vendor event 0xe4 with first octet 0x02 for event. I assume the second octet is then the vendor command code for these.
>
Yes, you're right.
> > < HCI Command: Reset (0x03|0x0003) plen 0 [hci0] 10.861118
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.865763
> > Reset (0x03|0x0003) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Local Supported Fe.. (0x04|0x0003) plen 0 [hci0] 10.865805
> >> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.865965
> > Read Local Supported Features (0x04|0x0003) ncmd 1
> > Status: Success (0x00)
> > Features: 0xbf 0x3e 0x8d 0xfe 0xdb 0xff 0x7b 0x87
> > 3 slot packets
> > 5 slot packets
> > Encryption
> > Slot offset
> > Timing accuracy
> > Role switch
> > Sniff mode
> > Power control requests
> > Channel quality driven data rate (CQDDR)
> > SCO link
> > HV2 packets
> > HV3 packets
> > CVSD synchronous data
> > Power control
> > Transparent synchronous data
> > Broadcast Encryption
> > Enhanced Data Rate ACL 2 Mbps mode
> > Enhanced Data Rate ACL 3 Mbps mode
> > Enhanced inquiry scan
> > Interlaced inquiry scan
> > Interlaced page scan
> > RSSI with inquiry results
> > Extended SCO link (EV3 packets)
> > EV4 packets
> > EV5 packets
> > AFH capable slave
> > AFH classification slave
> > LE Supported (Controller)
> > 3-slot Enhanced Data Rate ACL packets
> > 5-slot Enhanced Data Rate ACL packets
> > Sniff subrating
> > Pause encryption
> > AFH capable master
> > AFH classification master
> > Enhanced Data Rate eSCO 2 Mbps mode
> > Enhanced Data Rate eSCO 3 Mbps mode
> > 3-slot Enhanced Data Rate eSCO packets
> > Extended Inquiry Response
> > Simultaneous LE and BR/EDR (Controller)
> > Secure Simple Pairing
> > Encapsulated PDU
> > Erroneous Data Reporting
> > Non-flushable Packet Boundary Flag
> > Link Supervision Timeout Changed Event
> > Inquiry TX Power Level
> > Enhanced Power Control
> > Extended features
> > < HCI Command: Read Local Version Info.. (0x04|0x0001) plen 0 [hci0] 10.865987
> >> HCI Event: Vendor (0xff) plen 9 [hci0] 10.866259
> > 29 19 09 17 20 48 07 11 00 )... H?
>
> Is this meant to happen here?
>
If event received is not expected as the specification defines, I think it's probably incorrect.
But it requires more discussion with firmware people to make it clearer.
> >> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.866372
> > Read Local Version Information (0x04|0x0001) ncmd 1
> > Status: Success (0x00)
> > HCI version: Bluetooth 4.2 (0x08) - Revision 4359 (0x1107)
> > LMP version: Bluetooth 4.2 (0x08) - Subversion 2329 (0x0919)
> > Manufacturer: MediaTek, Inc. (70)
> > < HCI Command: Read BD ADDR (0x04|0x0009) plen 0 [hci0] 10.866391
> >> HCI Event: Command Complete (0x0e) plen 10 [hci0] 10.866539
> > Read BD ADDR (0x04|0x0009) ncmd 1
> > Status: Success (0x00)
> > Address: 00:00:46:76:22:01 (OLIVETTI NORTH AMERICA)
> > < HCI Command: Read Buffer Size (0x04|0x0005) plen 0 [hci0] 10.866609
> >> HCI Event: Command Complete (0x0e) plen 11 [hci0] 10.866754
> > Read Buffer Size (0x04|0x0005) ncmd 1
> > Status: Success (0x00)
> > ACL MTU: 1021 ACL max packet: 8
> > SCO MTU: 184 SCO max packet: 1
> > < HCI Command: Read Class of Device (0x03|0x0023) plen 0 [hci0] 10.866775
> >> HCI Event: Command Complete (0x0e) plen 7 [hci0] 10.866920
> > Read Class of Device (0x03|0x0023) ncmd 1
> > Status: Success (0x00)
> > Class: 0x001f00
> > Major class: Uncategorized, specific device code not specified
> > Minor class: 0x00
> > < HCI Command: Read Local Name (0x03|0x0014) plen 0 [hci0] 10.866939
> >> HCI Event: Command Complete (0x0e) plen 252 [hci0] 10.867256
> > Read Local Name (0x03|0x0014) ncmd 1
> > Status: Success (0x00)
> > Name: MTK MT7622 #1
> > < HCI Command: Read Voice Setting (0x03|0x0025) plen 0 [hci0] 10.867308
> >> HCI Event: Command Complete (0x0e) plen 6 [hci0] 10.867447
> > Read Voice Setting (0x03|0x0025) ncmd 1
> > Status: Success (0x00)
> > Setting: 0x0060
> > Input Coding: Linear
> > Input Data Format: 2's complement
> > Input Sample Size: 16-bit
> > # of bits padding at MSB: 0
> > Air Coding Format: CVSD
> > < HCI Command: Read Number of Supporte.. (0x03|0x0038) plen 0 [hci0] 10.867474
> >> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.867611
> > Read Number of Supported IAC (0x03|0x0038) ncmd 1
> > Status: Success (0x00)
> > Number of IAC: 4
> > < HCI Command: Read Current IAC LAP (0x03|0x0039) plen 0 [hci0] 10.867678
> >> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.867865
> > Read Current IAC LAP (0x03|0x0039) ncmd 1
> > Status: Success (0x00)
> > Number of IAC: 1
> > Access code: 0x9e8b33 (General Inquiry)
> > < HCI Command: Set Event Filter (0x03|0x0005) plen 1 [hci0] 10.867890
> > Type: Clear All Filters (0x00)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.868033
> > Set Event Filter (0x03|0x0005) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write Connection Accept.. (0x03|0x0016) plen 2 [hci0] 10.868054
> > Timeout: 20000.000 msec (0x7d00)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.868235
> > Write Connection Accept Timeout (0x03|0x0016) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: LE Read Buffer Size (0x08|0x0002) plen 0 [hci0] 10.868262
> >> HCI Event: Command Complete (0x0e) plen 7 [hci0] 10.868392
> > LE Read Buffer Size (0x08|0x0002) ncmd 1
> > Status: Success (0x00)
> > Data packet length: 251
> > Num data packets: 8
> > < HCI Command: LE Read Local Supported.. (0x08|0x0003) plen 0 [hci0] 10.868413
> >> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.868587
> > LE Read Local Supported Features (0x08|0x0003) ncmd 1
> > Status: Success (0x00)
> > Features: 0xfd 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> > LE Encryption
> > Extended Reject Indication
> > Slave-initiated Features Exchange
> > LE Ping
> > LE Data Packet Length Extension
> > LL Privacy
> > Extended Scanner Filter Policies
> > < HCI Command: LE Read Supported States (0x08|0x001c) plen 0 [hci0] 10.868646
> >> HCI Event: Command Complete (0x0e) plen 12 [hci0] 10.868787
> > LE Read Supported States (0x08|0x001c) ncmd 1
> > Status: Success (0x00)
> > States: 0x000000001fffffff
> > Non-connectable Advertising State
> > Scannable Advertising State
> > Connectable Advertising State
> > High Duty Cycle Directed Advertising State
> > Passive Scanning State
> > Active Scanning State
> > Initiating State
> > and Connection State (Master Role)
> > Connection State (Slave Role)
> > Non-connectable Advertising State
> > and Passive Scanning State
> > Scannable Advertising State
> > and Passive Scanning State
> > Connectable Advertising State
> > and Passive Scanning State
> > High Duty Cycle Directed Advertising State
> > and Passive Scanning State
> > Non-connectable Advertising State
> > and Active Scanning State
> > Scannable Advertising State
> > and Active Scanning State
> > Connectable Advertising State
> > and Active Scanning State
> > High Duty Cycle Directed Advertising State
> > and Active Scanning State
> > Non-connectable Advertising State
> > and Initiating State
> > Scannable Advertising State
> > and Initiating State
> > Non-connectable Advertising State
> > and Connection State (Master Role)
> > Scannable Advertising State
> > and Connection State (Master Role)
> > Non-connectable Advertising State
> > and Connection State (Slave Role)
> > Scannable Advertising State
> > and Connection State (Slave Role)
> > Passive Scanning State
> > and Initiating State
> > Active Scanning State
> > and Initiating State
> > Passive Scanning State
> > and Connection State (Master Role)
> > Active Scanning State
> > and Connection State (Master Role)
> > Passive Scanning State
> > and Connection State (Slave Role)
> > Active Scanning State
> > and Connection State (Slave Role)
> > Initiating State
> > and Connection State (Master Role)
> > and Master Role & Master Role
> > < HCI Command: Read Local Supported Co.. (0x04|0x0002) plen 0 [hci0] 10.868807
> >> HCI Event: Command Complete (0x0e) plen 68 [hci0] 10.868985
> > Read Local Supported Commands (0x04|0x0002) ncmd 1
> > Status: Success (0x00)
> > Commands: 176 entries
> > Inquiry (Octet 0 - Bit 0)
> > Inquiry Cancel (Octet 0 - Bit 1)
> > Periodic Inquiry Mode (Octet 0 - Bit 2)
> > Exit Periodic Inquiry Mode (Octet 0 - Bit 3)
> > Create Connection (Octet 0 - Bit 4)
> > Disconnect (Octet 0 - Bit 5)
> > Add SCO Connection (Octet 0 - Bit 6)
> > Create Connection Cancel (Octet 0 - Bit 7)
> > Accept Connection Request (Octet 1 - Bit 0)
> > Reject Connection Request (Octet 1 - Bit 1)
> > Link Key Request Reply (Octet 1 - Bit 2)
> > Link Key Request Negative Reply (Octet 1 - Bit 3)
> > PIN Code Request Reply (Octet 1 - Bit 4)
> > PIN Code Request Negative Reply (Octet 1 - Bit 5)
> > Change Connection Packet Type (Octet 1 - Bit 6)
> > Authentication Requested (Octet 1 - Bit 7)
> > Set Connection Encryption (Octet 2 - Bit 0)
> > Change Connection Link Key (Octet 2 - Bit 1)
> > Master Link Key (Octet 2 - Bit 2)
> > Remote Name Request (Octet 2 - Bit 3)
> > Remote Name Request Cancel (Octet 2 - Bit 4)
> > Read Remote Supported Features (Octet 2 - Bit 5)
> > Read Remote Extended Features (Octet 2 - Bit 6)
> > Read Remote Version Information (Octet 2 - Bit 7)
> > Read Clock Offset (Octet 3 - Bit 0)
> > Read LMP Handle (Octet 3 - Bit 1)
> > Sniff Mode (Octet 4 - Bit 2)
> > Exit Sniff Mode (Octet 4 - Bit 3)
> > QoS Setup (Octet 4 - Bit 6)
> > Role Discovery (Octet 4 - Bit 7)
> > Switch Role (Octet 5 - Bit 0)
> > Read Link Policy Settings (Octet 5 - Bit 1)
> > Write Link Policy Settings (Octet 5 - Bit 2)
> > Read Default Link Policy Settings (Octet 5 - Bit 3)
> > Write Default Link Policy Settings (Octet 5 - Bit 4)
> > Flow Specification (Octet 5 - Bit 5)
> > Set Event Mask (Octet 5 - Bit 6)
> > Reset (Octet 5 - Bit 7)
> > Set Event Filter (Octet 6 - Bit 0)
> > Flush (Octet 6 - Bit 1)
> > Read PIN Type (Octet 6 - Bit 2)
> > Write PIN Type (Octet 6 - Bit 3)
> > Create New Unit Key (Octet 6 - Bit 4)
> > Read Stored Link Key (Octet 6 - Bit 5)
> > Write Stored Link Key (Octet 6 - Bit 6)
> > Delete Stored Link Key (Octet 6 - Bit 7)
> > Write Local Name (Octet 7 - Bit 0)
> > Read Local Name (Octet 7 - Bit 1)
> > Read Connection Accept Timeout (Octet 7 - Bit 2)
> > Write Connection Accept Timeout (Octet 7 - Bit 3)
> > Read Page Timeout (Octet 7 - Bit 4)
> > Write Page Timeout (Octet 7 - Bit 5)
> > Read Scan Enable (Octet 7 - Bit 6)
> > Write Scan Enable (Octet 7 - Bit 7)
> > Read Page Scan Activity (Octet 8 - Bit 0)
> > Write Page Scan Activity (Octet 8 - Bit 1)
> > Read Inquiry Scan Activity (Octet 8 - Bit 2)
> > Write Inquiry Scan Activity (Octet 8 - Bit 3)
> > Read Authentication Enable (Octet 8 - Bit 4)
> > Write Authentication Enable (Octet 8 - Bit 5)
> > Read Encryption Mode (Octet 8 - Bit 6)
> > Write Encryption Mode (Octet 8 - Bit 7)
> > Read Class of Device (Octet 9 - Bit 0)
> > Write Class of Device (Octet 9 - Bit 1)
> > Read Voice Setting (Octet 9 - Bit 2)
> > Write Voice Setting (Octet 9 - Bit 3)
> > Read Automatic Flush Timeout (Octet 9 - Bit 4)
> > Write Automatic Flush Timeout (Octet 9 - Bit 5)
> > Read Num Broadcast Retransmissions (Octet 9 - Bit 6)
> > Write Num Broadcast Retransmissions (Octet 9 - Bit 7)
> > Read Transmit Power Level (Octet 10 - Bit 2)
> > Read Sync Flow Control Enable (Octet 10 - Bit 3)
> > Write Sync Flow Control Enable (Octet 10 - Bit 4)
> > Set Controller To Host Flow Control (Octet 10 - Bit 5)
> > Host Buffer Size (Octet 10 - Bit 6)
> > Host Number of Completed Packets (Octet 10 - Bit 7)
> > Read Link Supervision Timeout (Octet 11 - Bit 0)
> > Write Link Supervision Timeout (Octet 11 - Bit 1)
> > Read Number of Supported IAC (Octet 11 - Bit 2)
> > Read Current IAC LAP (Octet 11 - Bit 3)
> > Write Current IAC LAP (Octet 11 - Bit 4)
> > Read Page Scan Mode (Octet 11 - Bit 7)
> > Write Page Scan Mode (Octet 12 - Bit 0)
> > Set AFH Host Channel Classification (Octet 12 - Bit 1)
> > Read Inquiry Scan Type (Octet 12 - Bit 4)
> > Write Inquiry Scan Type (Octet 12 - Bit 5)
> > Read Inquiry Mode (Octet 12 - Bit 6)
> > Write Inquiry Mode (Octet 12 - Bit 7)
> > Read Page Scan Type (Octet 13 - Bit 0)
> > Write Page Scan Type (Octet 13 - Bit 1)
> > Read AFH Channel Assessment Mode (Octet 13 - Bit 2)
> > Write AFH Channel Assessment Mode (Octet 13 - Bit 3)
> > Read Local Version Information (Octet 14 - Bit 3)
> > Read Local Supported Features (Octet 14 - Bit 5)
> > Read Local Extended Features (Octet 14 - Bit 6)
> > Read Buffer Size (Octet 14 - Bit 7)
> > Read Country Code (Octet 15 - Bit 0)
> > Read BD ADDR (Octet 15 - Bit 1)
> > Read Failed Contact Counter (Octet 15 - Bit 2)
> > Reset Failed Contact Counter (Octet 15 - Bit 3)
> > Read Link Quality (Octet 15 - Bit 4)
> > Read RSSI (Octet 15 - Bit 5)
> > Read AFH Channel Map (Octet 15 - Bit 6)
> > Read Clock (Octet 15 - Bit 7)
> > Read Loopback Mode (Octet 16 - Bit 0)
> > Write Loopback Mode (Octet 16 - Bit 1)
> > Enable Device Under Test Mode (Octet 16 - Bit 2)
> > Setup Synchronous Connection (Octet 16 - Bit 3)
> > Accept Synchronous Connection Request (Octet 16 - Bit 4)
> > Reject Synchronous Connection Request (Octet 16 - Bit 5)
> > Read Extended Inquiry Response (Octet 17 - Bit 0)
> > Write Extended Inquiry Response (Octet 17 - Bit 1)
> > Refresh Encryption Key (Octet 17 - Bit 2)
> > Sniff Subrating (Octet 17 - Bit 4)
> > Read Simple Pairing Mode (Octet 17 - Bit 5)
> > Write Simple Pairing Mode (Octet 17 - Bit 6)
> > Read Local OOB Data (Octet 17 - Bit 7)
> > Read Inquiry Response TX Power Level (Octet 18 - Bit 0)
> > Write Inquiry Transmit Power Level (Octet 18 - Bit 1)
> > Read Default Erroneous Data Reporting (Octet 18 - Bit 2)
> > Write Default Erroneous Data Reporting (Octet 18 - Bit 3)
> > IO Capability Request Reply (Octet 18 - Bit 7)
> > User Confirmation Request Reply (Octet 19 - Bit 0)
> > User Confirmation Request Neg Reply (Octet 19 - Bit 1)
> > User Passkey Request Reply (Octet 19 - Bit 2)
> > User Passkey Request Negative Reply (Octet 19 - Bit 3)
> > Remote OOB Data Request Reply (Octet 19 - Bit 4)
> > Write Simple Pairing Debug Mode (Octet 19 - Bit 5)
> > Enhanced Flush (Octet 19 - Bit 6)
> > Remote OOB Data Request Neg Reply (Octet 19 - Bit 7)
> > Send Keypress Notification (Octet 20 - Bit 2)
> > IO Capability Request Negative Reply (Octet 20 - Bit 3)
> > Read Encryption Key Size (Octet 20 - Bit 4)
> > Set Event Mask Page 2 (Octet 22 - Bit 2)
> > Read Enhanced Transmit Power Level (Octet 24 - Bit 0)
> > Enhanced Setup Synchronous Connection (Octet 29 - Bit 3)
> > Enhanced Accept Synchronous Connection Request (Octet 29 - Bit 4)
> > Read Local Supported Codecs (Octet 29 - Bit 5)
> > Set Triggered Clock Capture (Octet 30 - Bit 5)
> > Truncated Page (Octet 30 - Bit 6)
> > Truncated Page Cancel (Octet 30 - Bit 7)
> > Set Connectionless Slave Broadcast (Octet 31 - Bit 0)
> > Start Synchronization Train (Octet 31 - Bit 2)
> > Set Reserved LT_ADDR (Octet 31 - Bit 4)
> > Delete Reserved LT_ADDR (Octet 31 - Bit 5)
> > Set Connectionless Slave Broadcast Data (Octet 31 - Bit 6)
> > Read Synchronization Train Parameters (Octet 31 - Bit 7)
> > Write Synchronization Train Parameters (Octet 32 - Bit 0)
> > Remote OOB Extended Data Request Reply (Octet 32 - Bit 1)
> > Read Authenticated Payload Timeout (Octet 32 - Bit 4)
> > Write Authenticated Payload Timeout (Octet 32 - Bit 5)
> > Read Local OOB Extended Data (Octet 32 - Bit 6)
> > Write Secure Connections Test Mode (Octet 32 - Bit 7)
> > Read Extended Page Timeout (Octet 33 - Bit 0)
> > Write Extended Page Timeout (Octet 33 - Bit 1)
> > Read Extended Inquiry Length (Octet 33 - Bit 2)
> > Write Extended Inquiry Length (Octet 33 - Bit 3)
> > LE Set Data Length (Octet 33 - Bit 6)
> > LE Read Suggested Default Data Length (Octet 33 - Bit 7)
> > LE Write Suggested Default Data Length (Octet 34 - Bit 0)
> > LE Read Local P-256 Public Key (Octet 34 - Bit 1)
> > LE Generate DHKey (Octet 34 - Bit 2)
> > LE Add Device To Resolving List (Octet 34 - Bit 3)
> > LE Remove Device From Resolving List (Octet 34 - Bit 4)
> > LE Clear Resolving List (Octet 34 - Bit 5)
> > LE Read Resolving List Size (Octet 34 - Bit 6)
> > LE Read Peer Resolvable Address (Octet 34 - Bit 7)
> > LE Read Local Resolvable Address (Octet 35 - Bit 0)
> > LE Set Address Resolution Enable (Octet 35 - Bit 1)
> > LE Set Resolvable Private Address Timeout (Octet 35 - Bit 2)
> > LE Read Maximum Data Length (Octet 35 - Bit 3)
> > Octet 35 - Bit 4
> > Octet 35 - Bit 5
> > Octet 35 - Bit 6
> > Octet 35 - Bit 7
> > Octet 36 - Bit 0
>
> So you support the PHY commands, but do not indicate support LE 2M or LE Coded? Also these are Bluetooth 5.0 commands.
>
To be honest. When I ported the device into Bluez core, a unexpected event for LE read local feature would cause a fail at Bluez core, so I made a hack on Bluez core
to allow that I can keeping bring up the device without be blocked by the issue most probably from firmware.
Below code snippet is the only thing I added to avoid a fail at Bluez core to bring up the device.
@@ -927,6 +927,8 @@ static void hci_cc_le_read_local_features(struct hci_dev *hdev,
return;
memcpy(hdev->le_features, rp->features, 8);
+ hdev->le_features[0] = 0;
+ hdev->le_features[1] = 0;
}
> > < HCI Command: Write Simple Pairing Mode (0x03|0x0056) plen 1 [hci0] 10.869023
> > Mode: Enabled (0x01)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869185
> > Write Simple Pairing Mode (0x03|0x0056) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write Inquiry Mode (0x03|0x0045) plen 1 [hci0] 10.869239
> > Mode: Inquiry Result with RSSI or Extended Inquiry Result (0x02)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869371
> > Write Inquiry Mode (0x03|0x0045) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Inquiry Response T.. (0x03|0x0058) plen 0 [hci0] 10.869396
> >> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.869552
> > Read Inquiry Response TX Power Level (0x03|0x0058) ncmd 1
> > Status: Success (0x00)
> > TX power: -1 dBm
> > < HCI Command: Read Local Extended Fea.. (0x04|0x0004) plen 1 [hci0] 10.869572
> > Page: 1
> >> HCI Event: Command Complete (0x0e) plen 14 [hci0] 10.869729
> > Read Local Extended Features (0x04|0x0004) ncmd 1
> > Status: Success (0x00)
> > Page: 1/2
> > Features: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00
> > Secure Simple Pairing (Host Support)
> > < HCI Command: Set Event Mask (0x03|0x0001) plen 8 [hci0] 10.869783
> > Mask: 0x3dbff807fffbffff
> > Inquiry Complete
> > Inquiry Result
> > Connection Complete
> > Connection Request
> > Disconnection Complete
> > Authentication Complete
> > Remote Name Request Complete
> > Encryption Change
> > Change Connection Link Key Complete
> > Master Link Key Complete
> > Read Remote Supported Features Complete
> > Read Remote Version Information Complete
> > QoS Setup Complete
> > Command Complete
> > Command Status
> > Hardware Error
> > Flush Occurred
> > Role Change
> > Mode Change
> > Return Link Keys
> > PIN Code Request
> > Link Key Request
> > Link Key Notification
> > Loopback Command
> > Data Buffer Overflow
> > Max Slots Change
> > Read Clock Offset Complete
> > Connection Packet Type Changed
> > QoS Violation
> > Page Scan Mode Change
> > Page Scan Repetition Mode Change
> > Flow Specification Complete
> > Inquiry Result with RSSI
> > Read Remote Extended Features Complete
> > Synchronous Connection Complete
> > Synchronous Connection Changed
> > Sniff Subrating
> > Extended Inquiry Result
> > Encryption Key Refresh Complete
> > IO Capability Request
> > IO Capability Request Reply
> > User Confirmation Request
> > User Passkey Request
> > Remote OOB Data Request
> > Simple Pairing Complete
> > Link Supervision Timeout Changed
> > Enhanced Flush Complete
> > User Passkey Notification
> > Keypress Notification
> > Remote Host Supported Features Notification
> > LE Meta
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.869921
> > Set Event Mask (0x03|0x0001) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Stored Link Key (0x03|0x000d) plen 7 [hci0] 10.869947
> > Address: 00:00:00:00:00:00 (OUI 00-00-00)
> > Read all: 0x01
> >> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.870129
> > Read Stored Link Key (0x03|0x000d) ncmd 1
> > Status: Success (0x00)
> > Max num keys: 4
> > Num keys: 0
> > < HCI Command: Write Default Link Poli.. (0x02|0x000f) plen 2 [hci0] 10.870148
> > Link policy: 0x0005
> > Enable Role Switch
> > Enable Sniff Mode
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.870310
> > Write Default Link Policy Settings (0x02|0x000f) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Page Scan Activity (0x03|0x001b) plen 0 [hci0] 10.870331
> >> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.870485
> > Read Page Scan Activity (0x03|0x001b) ncmd 1
> > Status: Success (0x00)
> > Interval: 1280.000 msec (0x0800)
> > Window: 11.250 msec (0x0012)
> > < HCI Command: Read Page Scan Type (0x03|0x0046) plen 0 [hci0] 10.870504
> >> HCI Event: Command Complete (0x0e) plen 5 [hci0] 10.870652
> > Read Page Scan Type (0x03|0x0046) ncmd 1
> > Status: Success (0x00)
> > Type: Standard Scan (0x00)
> > < HCI Command: LE Set Event Mask (0x08|0x0001) plen 8 [hci0] 10.870671
> > Mask: 0x0000000000000980
> > LE Read Local P-256 Public Key Complete
> > LE Generate DHKey Complete
> > Unknown mask (0x0000000000000800)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.870839
> > LE Set Event Mask (0x08|0x0001) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write LE Host Supported (0x03|0x006d) plen 2 [hci0] 10.870859
> > Supported: 0x01
> > Simultaneous: 0x00
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.871028
> > Write LE Host Supported (0x03|0x006d) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Local Extended Fea.. (0x04|0x0004) plen 1 [hci0] 10.871059
> > Page: 2
> >> HCI Event: Command Complete (0x0e) plen 14 [hci0] 10.871201
> > Read Local Extended Features (0x04|0x0004) ncmd 1
> > Status: Success (0x00)
> > Page: 2/2
> > Features: 0x25 0x0b 0x00 0x00 0x00 0x00 0x00 0x00
> > Connectionless Slave Broadcast - Master
> > Synchronization Train
> > Generalized interlaced scan
> > Secure Connections (Controller Support)
> > Ping
> > Train nudging
> > < HCI Command: Delete Stored Link Key (0x03|0x0012) plen 7 [hci0] 10.871240
> > Address: 00:00:00:00:00:00 (OUI 00-00-00)
> > Delete all: 0x01
> >> HCI Event: Command Complete (0x0e) plen 6 [hci0] 10.871384
> > Delete Stored Link Key (0x03|0x0012) ncmd 1
> > Status: Success (0x00)
> > Num keys: 0
> > < HCI Command: Set Event Mask Page 2 (0x03|0x0063) plen 8 [hci0] 10.871403
> > Mask: 0x0000000000b0c000
> > Triggered Clock Capture
> > Synchronization Train Complete
> > Slave Page Response Timeout
> > Connectionless Slave Broadcast Channel Map Change
> > Authenticated Payload Timeout Expired
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.871566
> > Set Event Mask Page 2 (0x03|0x0063) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Read Local Supported Co.. (0x04|0x000b) plen 0 [hci0] 10.871599
> >> HCI Event: Command Complete (0x0e) plen 8 [hci0] 10.871750
> > Read Local Supported Codecs (0x04|0x000b) ncmd 1
> > Status: Success (0x00)
> > Number of supported codecs: 2
> > Codec: CVSD (0x02)
> > Codec: Transparent (0x03)
> > Number of vendor codecs: 0
> > < HCI Command: Read Synchronization Tr.. (0x03|0x0077) plen 0 [hci0] 10.871769
> >> HCI Event: Command Complete (0x0e) plen 11 [hci0] 10.871928
> > Read Synchronization Train Parameters (0x03|0x0077) ncmd 1
> > Status: Success (0x00)
> > Interval: 0.000 msec (0x0000)
> > Timeout: 0.000 msec (0x00000000)
> > Service data: 0x00
> > < HCI Command: Write Secure Connection.. (0x03|0x007a) plen 1 [hci0] 10.871947
> > Support: Enabled (0x01)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872098
> > Write Secure Connections Host Support (0x03|0x007a) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Unknown (0x08|0x0031) plen 3 [hci0] 10.872156
> > 03 00 00 ...
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872322
> > Unknown (0x08|0x0031) ncmd 1
> > Status: Success (0x00)
> > = Index Info: 00:00:46:76:22:01 (MediaTek, Inc.) [hci0] 10.872361
>
> This extra index info worries me a little bit. I need to check if that is suppose to happen.
> > < HCI Command: LE Set Scan Response D.. (0x08|0x0009) plen 32 [hci0] 10.872431
> > Length: 10
> > Name (complete): builder
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872606
> > LE Set Scan Response Data (0x08|0x0009) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write Scan Enable (0x03|0x001a) plen 1 [hci0] 10.872627
> > Scan enable: Page Scan (0x02)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.872819
> > Write Scan Enable (0x03|0x001a) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write Class of Device (0x03|0x0024) plen 3 [hci0] 10.872841
> > Class: 0x000000
> > Major class: Miscellaneous
> > Minor class: 0x00
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873036
> > Write Class of Device (0x03|0x0024) ncmd 1
> > Status: Success (0x00)
> > * Unknown packet (code 17 len 9) [hci0] 10.873069
> > 02 00 00 00 07 00 00 00 00 .........
> > * Unknown packet (code 17 len 9) [hci0] 10.873069
> > 01 00 00 00 07 00 00 00 00 .........
> > < HCI Command: Write Local Name (0x03|0x0013) plen 248 [hci0] 10.873096
> > Name: builder
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873446
> > Write Local Name (0x03|0x0013) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Write Extended Inquir.. (0x03|0x0052) plen 241 [hci0] 10.873470
> > FEC: Not required (0x00)
> > Name (complete): builder
> > TX power: -1 dBm
> > Device ID: USB Implementer's Forum assigned (0x0002)
> > Vendor: Linux Foundation (0x1d6b)
> > Product: 0x0246
> > Version: 5.2.11 (0x052b)
> > 16-bit Service UUIDs (complete): 4 entries
> > Generic Access Profile (0x1800)
> > Generic Attribute Profile (0x1801)
> > A/V Remote Control (0x110e)
> > A/V Remote Control Target (0x110c)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 10.873857
> > Write Extended Inquiry Response (0x03|0x0052) ncmd 1
> > Status: Success (0x00)
> > * Unknown packet (code 17 len 13) [hci0] 10.873903
> > 01 00 00 00 01 00 05 00 00 d1 0a 00 00 .............
> > * Unknown packet (code 17 len 10) [hci0] 10.873913
> > 02 00 00 00 06 00 d1 0a 00 00 ..........
> > * Unknown packet (code 16 len 7) [hci0] 17.803939
> > 01 00 00 00 05 00 00 .......
> > < HCI Command: Write Scan Enable (0x03|0x001a) plen 1 [hci0] 17.803983
> > Scan enable: No Scans (0x00)
> >> HCI Event: Command Complete (0x0e) plen 4 [hci0] 17.804233
> > Write Scan Enable (0x03|0x001a) ncmd 1
> > Status: Success (0x00)
> > < HCI Command: Vendor (0x3f|0x006f) plen 6 [hci0] 17.804282
> > 01 06 02 00 00 00 ......
> >> HCI Event: Unknown (0xe4) plen 5 [hci0] 17.804636
> > 02 06 01 00 00 .....
> > * Unknown packet (code 17 len 13) [hci0] 17.811580
> > 01 00 00 00 01 00 05 00 00 d0 0a 00 00 .............
> > * Unknown packet (code 17 len 10) [hci0] 17.811596
> > 02 00 00 00 06 00 d0 0a 00 00 ..........
> > = Close Index: 00:00:46:76:22:01 [hci0] 17.811625
>
> Regards
>
> Marcel
>
^ permalink raw reply
* [PATCH v10 18/18] KVM: arm64: Invoke FPSIMD context switch trap from C
From: Alex Bennée @ 2018-05-24 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527005119-6842-19-git-send-email-Dave.Martin@arm.com>
Dave Martin <Dave.Martin@arm.com> writes:
> The conversion of the FPSIMD context switch trap code to C has added
> some overhead to calling it, due to the need to save registers that
> the procedure call standard defines as caller-saved.
>
> So, perhaps it is no longer worth invoking this trap handler quite
> so early.
>
> Instead, we can invoke it from fixup_guest_exit(), with little
> likelihood of increasing the overhead much further.
>
> As a convenience, this patch gives __hyp_switch_fpsimd() the same
> return semantics fixup_guest_exit(). For now there is no
> possibility of a spurious FPSIMD trap, so the function always
> returns true, but this allows it to be tail-called with a single
> return statement.
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Alex Benn?e <alex.bennee@linaro.org>
> ---
> arch/arm64/kvm/hyp/entry.S | 30 ------------------------------
> arch/arm64/kvm/hyp/hyp-entry.S | 19 -------------------
> arch/arm64/kvm/hyp/switch.c | 15 +++++++++++++--
> 3 files changed, 13 insertions(+), 51 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
> index 40f349b..fad1e16 100644
> --- a/arch/arm64/kvm/hyp/entry.S
> +++ b/arch/arm64/kvm/hyp/entry.S
> @@ -166,33 +166,3 @@ abort_guest_exit_end:
> orr x0, x0, x5
> 1: ret
> ENDPROC(__guest_exit)
> -
> -ENTRY(__fpsimd_guest_restore)
> - // x0: esr
> - // x1: vcpu
> - // x2-x29,lr: vcpu regs
> - // vcpu x0-x1 on the stack
> - stp x2, x3, [sp, #-144]!
> - stp x4, x5, [sp, #16]
> - stp x6, x7, [sp, #32]
> - stp x8, x9, [sp, #48]
> - stp x10, x11, [sp, #64]
> - stp x12, x13, [sp, #80]
> - stp x14, x15, [sp, #96]
> - stp x16, x17, [sp, #112]
> - stp x18, lr, [sp, #128]
> -
> - bl __hyp_switch_fpsimd
> -
> - ldp x4, x5, [sp, #16]
> - ldp x6, x7, [sp, #32]
> - ldp x8, x9, [sp, #48]
> - ldp x10, x11, [sp, #64]
> - ldp x12, x13, [sp, #80]
> - ldp x14, x15, [sp, #96]
> - ldp x16, x17, [sp, #112]
> - ldp x18, lr, [sp, #128]
> - ldp x0, x1, [sp, #144]
> - ldp x2, x3, [sp], #160
> - eret
> -ENDPROC(__fpsimd_guest_restore)
> diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S
> index bffece2..753b9d2 100644
> --- a/arch/arm64/kvm/hyp/hyp-entry.S
> +++ b/arch/arm64/kvm/hyp/hyp-entry.S
> @@ -113,25 +113,6 @@ el1_hvc_guest:
>
> el1_trap:
> get_vcpu_ptr x1, x0
> -
> - mrs x0, esr_el2
> - lsr x0, x0, #ESR_ELx_EC_SHIFT
> - /*
> - * x0: ESR_EC
> - * x1: vcpu pointer
> - */
> -
> - /*
> - * We trap the first access to the FP/SIMD to save the host context
> - * and restore the guest context lazily.
> - * If FP/SIMD is not implemented, handle the trap and inject an
> - * undefined instruction exception to the guest.
> - */
> -alternative_if_not ARM64_HAS_NO_FPSIMD
> - cmp x0, #ESR_ELx_EC_FP_ASIMD
> - b.eq __fpsimd_guest_restore
> -alternative_else_nop_endif
> -
> mov x0, #ARM_EXCEPTION_TRAP
> b __guest_exit
>
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index 4fbee95..2d45bd7 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -328,8 +328,7 @@ static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
> }
> }
>
> -void __hyp_text __hyp_switch_fpsimd(u64 esr __always_unused,
> - struct kvm_vcpu *vcpu)
> +static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
> {
> struct user_fpsimd_state *host_fpsimd = vcpu->arch.host_fpsimd_state;
>
> @@ -369,6 +368,8 @@ void __hyp_text __hyp_switch_fpsimd(u64 esr __always_unused,
> fpexc32_el2);
>
> vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
> +
> + return true;
> }
>
> /*
> @@ -390,6 +391,16 @@ static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
> if (*exit_code != ARM_EXCEPTION_TRAP)
> goto exit;
>
> + /*
> + * We trap the first access to the FP/SIMD to save the host context
> + * and restore the guest context lazily.
> + * If FP/SIMD is not implemented, handle the trap and inject an
> + * undefined instruction exception to the guest.
> + */
> + if (system_supports_fpsimd() &&
> + kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
> + return __hyp_switch_fpsimd(vcpu);
> +
> if (!__populate_fault_info(vcpu))
> return true;
--
Alex Benn?e
^ permalink raw reply
* [PATCH v2 9/9] ARM: dts: silk: Drop MTD partitioning from DT
From: Marek Vasut @ 2018-05-24 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524150721.28964-1-marek.vasut+renesas@gmail.com>
Drop the MTD partitioning from DT, since it does not describe HW
and to give way to a more flexible kernel command line partition
passing.
To retain the original partitioning, assure you have enabled
CONFIG_MTD_CMDLINE_PARTS in your kernel config and add the
following to your kernel command line:
mtdparts=spi0.0:256k(loader),4m(user),-(flash)
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-renesas-soc at vger.kernel.org
---
V2: Drop the @0 anchor from the commit message, use 4m
---
arch/arm/boot/dts/r8a7794-silk.dts | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 7808aaee6644..b8163a0e2190 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -444,27 +444,6 @@
spi-cpol;
spi-cpha;
m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition at 40000 {
- label = "user";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition at 440000 {
- label = "flash";
- reg = <0x00440000 0x03bc0000>;
- };
- };
};
};
--
2.16.2
^ permalink raw reply related
* [PATCH v2 8/9] ARM: dts: alt: Drop MTD partitioning from DT
From: Marek Vasut @ 2018-05-24 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524150721.28964-1-marek.vasut+renesas@gmail.com>
Drop the MTD partitioning from DT, since it does not describe HW
and to give way to a more flexible kernel command line partition
passing.
To retain the original partitioning, assure you have enabled
CONFIG_MTD_CMDLINE_PARTS in your kernel config and add the
following to your kernel command line:
mtdparts=spi0.0:256k(loader),256k(system),-(user)
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-renesas-soc at vger.kernel.org
---
V2: Drop the @0 anchor from the commit message
---
arch/arm/boot/dts/r8a7794-alt.dts | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index e17027532941..1d044ed598f3 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -419,26 +419,5 @@
spi-cpol;
spi-cpha;
m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition at 40000 {
- label = "system";
- reg = <0x00040000 0x00040000>;
- read-only;
- };
- partition at 80000 {
- label = "user";
- reg = <0x00080000 0x03f80000>;
- };
- };
};
};
--
2.16.2
^ permalink raw reply related
* [PATCH v2 7/9] ARM: dts: gose: Drop MTD partitioning from DT
From: Marek Vasut @ 2018-05-24 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524150721.28964-1-marek.vasut+renesas@gmail.com>
Drop the MTD partitioning from DT, since it does not describe HW
and to give way to a more flexible kernel command line partition
passing.
To retain the original partitioning, assure you have enabled
CONFIG_MTD_CMDLINE_PARTS in your kernel config and add the
following to your kernel command line:
mtdparts=spi0.0:256k(loader),4m(user),-(flash)
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-renesas-soc at vger.kernel.org
---
V2: Drop the @0 anchor from the commit message, use 4m
---
arch/arm/boot/dts/r8a7793-gose.dts | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index aa209f6e5d71..b2dd54fbe40c 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -676,27 +676,6 @@
spi-cpol;
spi-cpha;
m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "loader";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition at 40000 {
- label = "user";
- reg = <0x00040000 0x00400000>;
- read-only;
- };
- partition at 440000 {
- label = "flash";
- reg = <0x00440000 0x03bc0000>;
- };
- };
};
};
--
2.16.2
^ permalink raw reply related
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