* [PATCH v3 8/8] drm/mediatek: add third ddp path
From: CK Hu @ 2018-05-25 5:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-9-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch create third crtc by third ddp path
>
Apply this patch before the patch 'Add support for mediatek SOC MT2712'
because this patch is necessary for mt2712.
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b32c4cc8d051..3a866e1d6af4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> if (ret < 0)
> goto err_component_unbind;
>
> + ret = mtk_drm_crtc_create(drm, private->data->third_path,
> + private->data->third_len);
I think you should prevent doing this for mt8173 and mt2701 because that
two SoC has only two ddp path.
Regards,
CK
> + if (ret < 0)
> + goto err_component_unbind;
> +
> /* Use OVL device for all DMA memory allocations */
> np = private->comp_node[private->data->main_path[0]] ?:
> private->comp_node[private->data->ext_path[0]];
^ permalink raw reply
* [PATCH v2 5/5] MAINTAINERS: Add Actions Semi S900 pinctrl entries
From: Manivannan Sadhasivam @ 2018-05-25 5:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <25d1c303-71d7-8c38-880f-7bb0e133a876@suse.de>
Hi Andreas,
On Fri, May 25, 2018 at 06:12:00AM +0200, Andreas F?rber wrote:
> Am 23.05.2018 um 10:40 schrieb Linus Walleij:
> > On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
> > <manivannan.sadhasivam@linaro.org> wrote:
> >
> >> Add S900 pinctrl entries under ARCH_ACTIONS
> >>
> >> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >
> > Patch applied tentatively so we have some maintenance entry for this.
> >
> > Andreas expressed concerns about the driver earlier, so he might want it
> > split from the platform parts and have a separate entry for the pinctrl+GPIO
> > so Manivannan can maintain that part, also it makes sense to list
> > Manivannan as comaintainer of ARCH_ACTIONS with this in.
> >
> > Andreas: how would you like to proceed?
> >
> > I understand that I was a bit pushy or even rude in my last message
> > about the maintenance of this platform and the code structure of
> > the pin control driver. I am sorry if it caused any bad feelings on your
> > side :( social conflicts give me the creeps, I just try my best. Maybe
> > my best isn't always what it should be.
>
> I fail to understand how splitting the MAINTAINERS section is going to
> help with the pinctrl conflict at hand? The problem is that instead of
> refactoring my S500 pinctrl driver to his liking, Mani has submitted a
> competing S900 pinctrl driver that you went on to merge. The human
> aspect is that merging his driver took the credit away from me having
> written the earlier pinctrl driver (based on my rtd1295 pinctrl driver).
> The practical aspect is that I can't drop my pinctrl driver from my work
> branch until there is equivalent functionality in the merged driver. I
> am lacking the time to rewrite S500 pin definitions on top of Mani's
> myself at this time, and I haven't seen S500 patches from him yet.
>
I think we discussed this few more times before and I clearly mentioned this
pinctrl driver confilct in my old pinctrl series cover letter. If you had
submitted your pinctrl driver then Linus would had the option of picking up the
most robust one. But sadly you didn't had any time to complete and submit
yours and since there was only one pinctrl driver floating for Actions, Linus
went and merged mine.
Regarding the S500/S700 support, again I told you that my goal is to set up the
base driver for Actions OWL series SoC first and then adding support for every
other SoC's of the same family later. Now, I have succeeded in setting up the
clock, pinctrl and gpio drivers, so I can now work on extending support for
other SoC's as well.
FYI, I have ordered S700 based Cubieboard and will work on adding support for
that first. I still don't have access to S500 board yet since it is not
available on my region. Will find a way to get this asap.
> Also I had been investing efforts in explaining the upstreaming process
> to Actions, last in November. I see Thomas Liau and Jeff Chen missing in
> CC and I have not seen any Reviewed-by or Acked-by from anyone at
> Actions on this and the preceding series. There are more chips than the
> one on Linaro's 96board, so I would prefer to assure that the design
> works for all. Thus I am very critical of you applying the patches
> without waiting for review by Actions.
>
I don't think Actions would be interested in any upstreaming efforts. It
is our (comunity) responsibility to add support for that in order to
have our boards running mainline kernel and that's what we both have been
doing. Moreover I only saw once David Liau responded to your patchset and
there isn't much further. So how can you expect the subsystem maintainer's
to hold the patch series waiting for a so far silent SoC manufacturer's
response?
We should get move on and since my drivers are completely tested, we can
work on adding more SoC support later. And if something breaks on other
SoC platform, we can always modify the base driver accordingly.
> Other aspects are: The reason I wrote the pinctrl driver is that I
> experienced a UART TX issue on the Sparky board and was hoping a pinctrl
> driver might resolve that, but it didn't. So I still have a mix of
> boards where some are working and some are pretty unusable, without any
> clues on why.
>
> That said, I don't object to having a separate MAINTAINERS section for
> the pinctrl driver(s) as long as I still get CC'ed on changes. We have
> wanted to add Mani as R for Actions overall, so that would probably mean
> adding me as R to an Actions pinctrl section, to avoid syncing the paths
> between two sections. I had previously felt that it does not make sense
> to list Mani as co-maintainer (M) for Actions overall since he can't tag
> and submit from my repo. And for the record I have offered him to take
> over which he didn't want to. I still hope to find some more time to
> review and queue his SPS patches, a driver that I have designed and thus
> understand and am much happier about the incremental additions there.
>
Yes I agree that you offered me to take the Maintainership once through
IRC conversation, but I kind of refused it because I don't want to completely
take over the maintainership role from you since you did a great job in
getting the base SoC support mainlined initially. On the other hand, I
did ask you to add me as Co-Maintainer but you didn't responded to that.
I know that I can't send any pull requests to Arnd, but we should sort
it out IMO. Also, if you are completely swamped, then I take take up the
maintainership role now inorder to keep the things moving. TBH I don't
want my patches to be floating for months without any reason.
> A further side note is that I had reached out about setting up an
> infradead mailing list linux-actions, but there was no response from
> David or anyone. Having an L on the section(s) would avoid messing with
> R and hand-maintained CC lists. Any help with that appreciated.
>
This is something we have to look out for and I will also see the possibility
of setting up the mailing list from my side.
Thanks for all of your great efforts!
Regards,
Mani
> Regards,
> Andreas
>
> --
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
> GF: Felix Imend?rffer, Jane Smithard, Graham Norton
> HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH v9 02/15] clk: mux: Split out register accessors for reuse
From: Sricharan R @ 2018-05-25 5:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524165033.GB14924@minitux>
Hi Bjorn,
On 5/24/2018 10:20 PM, Bjorn Andersson wrote:
> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> We want to reuse the logic in clk-mux.c for other clock drivers
>> that don't use readl as register accessors. Fortunately, there
>> really isn't much to the mux code besides the table indirection
>> and quirk flags if you assume any bit shifting and masking has
>> been done already. Pull that logic out into reusable functions
>> that operate on an optional table and some flags so that other
>> drivers can use the same logic.
>>
>> [Sricharan: Rebased for mainline]
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should read as a log, where the first entry is Stephen stating that
> he acquired or wrote the code and can release it according to the
> license requirements. Then you state that you acquired it, changed it
> and are releasing it according to the license requirements.
>
ok, will fix this to make it more clear.
>
> PS. Please expand your last name.
>
ok. Just that, all my previous patches has so far gone like this :-)
Regards,
Sricharan
> Regards,
> Bjorn
>
>> ---
>> drivers/clk/clk-mux.c | 74 +++++++++++++++++++++++++++----------------
>> drivers/clk/nxp/clk-lpc32xx.c | 21 +++---------
>> include/linux/clk-provider.h | 6 ++++
>> 3 files changed, 57 insertions(+), 44 deletions(-)
>>
>> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
>> index 39cabe1..28223fa 100644
>> --- a/drivers/clk/clk-mux.c
>> +++ b/drivers/clk/clk-mux.c
>> @@ -26,35 +26,25 @@
>> * parent - parent is adjustable through clk_set_parent
>> */
>>
>> -static u8 clk_mux_get_parent(struct clk_hw *hw)
>> +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
>> + unsigned int *table,
>> + unsigned long flags)
>> {
>> - struct clk_mux *mux = to_clk_mux(hw);
>> int num_parents = clk_hw_get_num_parents(hw);
>> - u32 val;
>> -
>> - /*
>> - * FIXME need a mux-specific flag to determine if val is bitwise or numeric
>> - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
>> - * to 0x7 (index starts at one)
>> - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
>> - * val = 0x4 really means "bit 2, index starts at bit 0"
>> - */
>> - val = clk_readl(mux->reg) >> mux->shift;
>> - val &= mux->mask;
>>
>> - if (mux->table) {
>> + if (table) {
>> int i;
>>
>> for (i = 0; i < num_parents; i++)
>> - if (mux->table[i] == val)
>> + if (table[i] == val)
>> return i;
>> return -EINVAL;
>> }
>>
>> - if (val && (mux->flags & CLK_MUX_INDEX_BIT))
>> + if (val && (flags & CLK_MUX_INDEX_BIT))
>> val = ffs(val) - 1;
>>
>> - if (val && (mux->flags & CLK_MUX_INDEX_ONE))
>> + if (val && (flags & CLK_MUX_INDEX_ONE))
>> val--;
>>
>> if (val >= num_parents)
>> @@ -62,23 +52,53 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
>>
>> return val;
>> }
>> +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
>>
>> -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +static u8 _clk_mux_get_parent(struct clk_hw *hw)
>> {
>> struct clk_mux *mux = to_clk_mux(hw);
>> u32 val;
>> - unsigned long flags = 0;
>>
>> - if (mux->table) {
>> - index = mux->table[index];
>> + /*
>> + * FIXME need a mux-specific flag to determine if val is bitwise or
>> + * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
>> + * but ranges from 0x1 to 0x7 (index starts at one)
>> + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
>> + * val = 0x4 really means "bit 2, index starts at bit 0"
>> + */
>> + val = clk_readl(mux->reg) >> mux->shift;
>> + val &= mux->mask;
>> +
>> + return clk_mux_get_parent(hw, val, mux->table, mux->flags);
>> +}
>> +
>> +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
>> + unsigned long flags)
>> +{
>> + unsigned int val = index;
>> +
>> + if (table) {
>> + val = table[val];
>> } else {
>> - if (mux->flags & CLK_MUX_INDEX_BIT)
>> - index = 1 << index;
>> + if (flags & CLK_MUX_INDEX_BIT)
>> + val = 1 << index;
>>
>> - if (mux->flags & CLK_MUX_INDEX_ONE)
>> - index++;
>> + if (flags & CLK_MUX_INDEX_ONE)
>> + val++;
>> }
>>
>> + return val;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_mux_reindex);
>> +
>> +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> + struct clk_mux *mux = to_clk_mux(hw);
>> + u32 val;
>> + unsigned long flags = 0;
>> +
>> + index = clk_mux_reindex(index, mux->table, mux->flags);
>> +
>> if (mux->lock)
>> spin_lock_irqsave(mux->lock, flags);
>> else
>> @@ -102,14 +122,14 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> }
>>
>> const struct clk_ops clk_mux_ops = {
>> - .get_parent = clk_mux_get_parent,
>> + .get_parent = _clk_mux_get_parent,
>> .set_parent = clk_mux_set_parent,
>> .determine_rate = __clk_mux_determine_rate,
>> };
>> EXPORT_SYMBOL_GPL(clk_mux_ops);
>>
>> const struct clk_ops clk_mux_ro_ops = {
>> - .get_parent = clk_mux_get_parent,
>> + .get_parent = _clk_mux_get_parent,
>> };
>> EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
>>
>> diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
>> index f5d815f..9b34150 100644
>> --- a/drivers/clk/nxp/clk-lpc32xx.c
>> +++ b/drivers/clk/nxp/clk-lpc32xx.c
>> @@ -999,29 +999,16 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
>> .set_rate = clk_divider_set_rate,
>> };
>>
>> -static u8 clk_mux_get_parent(struct clk_hw *hw)
>> +static u8 _clk_mux_get_parent(struct clk_hw *hw)
>> {
>> struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
>> - u32 num_parents = clk_hw_get_num_parents(hw);
>> u32 val;
>>
>> regmap_read(clk_regmap, mux->reg, &val);
>> val >>= mux->shift;
>> val &= mux->mask;
>>
>> - if (mux->table) {
>> - u32 i;
>> -
>> - for (i = 0; i < num_parents; i++)
>> - if (mux->table[i] == val)
>> - return i;
>> - return -EINVAL;
>> - }
>> -
>> - if (val >= num_parents)
>> - return -EINVAL;
>> -
>> - return val;
>> + return clk_mux_get_parent(hw, val, mux->table, 0);
>> }
>>
>> static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> @@ -1036,11 +1023,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> }
>>
>> static const struct clk_ops lpc32xx_clk_mux_ro_ops = {
>> - .get_parent = clk_mux_get_parent,
>> + .get_parent = _clk_mux_get_parent,
>> };
>>
>> static const struct clk_ops lpc32xx_clk_mux_ops = {
>> - .get_parent = clk_mux_get_parent,
>> + .get_parent = _clk_mux_get_parent,
>> .set_parent = clk_mux_set_parent,
>> .determine_rate = __clk_mux_determine_rate,
>> };
>> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
>> index f711be6..344ad92 100644
>> --- a/include/linux/clk-provider.h
>> +++ b/include/linux/clk-provider.h
>> @@ -488,6 +488,12 @@ struct clk_mux {
>> extern const struct clk_ops clk_mux_ops;
>> extern const struct clk_ops clk_mux_ro_ops;
>>
>> +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
>> + unsigned int *table,
>> + unsigned long flags);
>> +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
>> + unsigned long flags);
>> +
>> struct clk *clk_register_mux(struct device *dev, const char *name,
>> const char * const *parent_names, u8 num_parents,
>> unsigned long flags,
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH 0/6] arm64: dts: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This fixes missing cooling device properties for CPUs for the ARM64
platforms. This is build tested by the zero day testing infrastructure
as well.
Individual maintainers can pick the patches to their SoC trees or I will
ask ARM SoC maintainers to pick them up later.
--
viresh
Viresh Kumar (6):
arm64: dts: amlogic: Add missing cooling device properties for CPUs
arm64: dts: freescale: Add missing cooling device properties for CPUs
arm64: dts: hisilicon: Add missing cooling device properties for CPUs
arm64: dts: mediatek: Add missing cooling device properties for CPUs
arm64: dts: rockchip: Add missing cooling device properties for CPUs
arm64: dts: socionext: Add missing cooling device properties for CPUs
.../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 24 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 ++++-
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++-
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 +++++++++++
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++--
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
13 files changed, 86 insertions(+), 4 deletions(-)
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply
* [PATCH 1/6] arm64: dts: amlogic: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
.../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index 0868da476e41..313f88f8759e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -209,10 +209,34 @@
#cooling-cells = <2>;
};
+&cpu1 {
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ #cooling-cells = <2>;
+};
+
&cpu4 {
#cooling-cells = <2>;
};
+&cpu5 {
+ #cooling-cells = <2>;
+};
+
+&cpu6 {
+ #cooling-cells = <2>;
+};
+
+&cpu7 {
+ #cooling-cells = <2>;
+};
+
ðmac {
pinctrl-0 = <ð_pins>;
pinctrl-names = "default";
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH 2/6] arm64: dts: freescale: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Do minor rearrangement as well to keep ordering consistent.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 ++++-
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
5 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 1109f22bda5e..630ee47441f2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -80,8 +80,8 @@
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
- #cooling-cells = <2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu at 1 {
@@ -91,6 +91,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 2 {
@@ -100,6 +101,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu3: cpu at 3 {
@@ -109,6 +111,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
l2: l2-cache {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 136ebfa9b333..ee7beab8bfae 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -87,6 +87,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 2 {
@@ -96,6 +97,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu3: cpu at 3 {
@@ -105,6 +107,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
l2: l2-cache {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 1c6556bcfddf..e64823a25158 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -76,6 +76,7 @@
reg = <0x1>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 2 {
@@ -84,6 +85,7 @@
reg = <0x2>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu3: cpu at 3 {
@@ -92,6 +94,7 @@
reg = <0x3>;
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu4: cpu at 100 {
@@ -109,6 +112,7 @@
reg = <0x101>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu6: cpu at 102 {
@@ -117,6 +121,7 @@
reg = <0x102>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu7: cpu at 103 {
@@ -125,6 +130,7 @@
reg = <0x103>;
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
CPU_PH20: cpu-ph20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 8d739301e7b8..c264b6d1bd7f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -65,6 +65,7 @@
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 100 {
@@ -84,6 +85,7 @@
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
+ #cooling-cells = <2>;
};
cpu4: cpu at 200 {
@@ -103,6 +105,7 @@
clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
+ #cooling-cells = <2>;
};
cpu6: cpu at 300 {
@@ -122,6 +125,7 @@
clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
+ #cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 0884e1a77901..b6ea9e96c866 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -65,6 +65,7 @@
clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 100 {
@@ -84,6 +85,7 @@
clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>;
+ #cooling-cells = <2>;
};
cpu4: cpu at 200 {
@@ -103,6 +105,7 @@
clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>;
+ #cooling-cells = <2>;
};
cpu6: cpu at 300 {
@@ -122,6 +125,7 @@
clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>;
+ #cooling-cells = <2>;
};
cluster0_l2: l2-cache0 {
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH 3/6] arm64: dts: hisilicon: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Do minor rearrangement as well to keep ordering consistent.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 586b281cd531..247024df714f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -88,8 +88,8 @@
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
- #cooling-cells = <2>; /* min followed by max */
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <311>;
};
@@ -101,6 +101,8 @@
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu2: cpu at 2 {
@@ -111,6 +113,8 @@
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu3: cpu at 3 {
@@ -121,6 +125,8 @@
next-level-cache = <&CLUSTER0_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu4: cpu at 100 {
@@ -131,6 +137,8 @@
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu5: cpu at 101 {
@@ -141,6 +149,8 @@
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu6: cpu at 102 {
@@ -151,6 +161,8 @@
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
cpu7: cpu at 103 {
@@ -161,6 +173,8 @@
next-level-cache = <&CLUSTER1_L2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-power-coefficient = <311>;
};
CLUSTER0_L2: l2-cache0 {
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: mediatek: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 9213c966c224..d49fe125e770 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -89,6 +89,7 @@
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 94597e33c806..abd2f15a544b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -168,6 +168,7 @@
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ #cooling-cells = <2>;
clocks = <&infracfg CLK_INFRA_CA53SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
@@ -193,6 +194,7 @@
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
+ #cooling-cells = <2>;
clocks = <&infracfg CLK_INFRA_CA57SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH 5/6] arm64: dts: rockchip: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Do minor rearrangement as well to keep ordering consistent.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 ++++++++++++
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++--
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index b8e9da15e00c..902a0907ad34 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -89,6 +89,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@@ -100,6 +101,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
@@ -111,6 +113,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index ad91ced78649..c32f2a551a1f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -122,6 +122,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l2: cpu at 2 {
@@ -129,6 +131,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l3: cpu at 3 {
@@ -136,6 +140,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b0: cpu at 100 {
@@ -152,6 +158,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b2: cpu at 102 {
@@ -159,6 +167,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b3: cpu at 103 {
@@ -166,6 +176,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
+
+ #cooling-cells = <2>; /* min followed by max */
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e0040b648f43..da935383a8f2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -108,8 +108,8 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
- #cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@@ -119,6 +119,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@@ -128,6 +129,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@@ -137,6 +139,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <100>;
};
@@ -145,8 +148,8 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
- #cooling-cells = <2>; /* min followed by max */
clocks = <&cru ARMCLKB>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
};
@@ -156,6 +159,7 @@
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ #cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
};
};
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH 6/6] arm64: dts: socionext: Add missing cooling device properties for CPUs
From: Viresh Kumar @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1527225682.git.viresh.kumar@linaro.org>
The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 3a5ed789c056..10ffb5019013 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -58,6 +58,7 @@
clocks = <&sys_clk 32>;
enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
cpu2: cpu at 100 {
@@ -77,6 +78,7 @@
clocks = <&sys_clk 33>;
enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
};
};
--
2.15.0.194.g9af6a3dea062
^ permalink raw reply related
* [PATCH v9 01/15] ARM: Add Krait L2 register accessor functions
From: Sricharan R @ 2018-05-25 5:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524173926.GC14924@minitux>
Hi Bjorn,
On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> Krait CPUs have a handful of L2 cache controller registers that
>> live behind a cp15 based indirection register. First you program
>> the indirection register (l2cpselr) to point the L2 'window'
>> register (l2cpdr) at what you want to read/write. Then you
>> read/write the 'window' register to do what you want. The
>> l2cpselr register is not banked per-cpu so we must lock around
>> accesses to it to prevent other CPUs from re-pointing l2cpdr
>> underneath us.
>>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>
> This should have your signed-off-by here as well.
>
ok.
> Apart from that:
>
> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>
Thanks.
Regards,
Sricharan
> Regards,
> Bjorn
>
>> ---
>> arch/arm/common/Kconfig | 3 ++
>> arch/arm/common/Makefile | 1 +
>> arch/arm/common/krait-l2-accessors.c | 48 +++++++++++++++++++++++++++++++
>> arch/arm/include/asm/krait-l2-accessors.h | 10 +++++++
>> 4 files changed, 62 insertions(+)
>> create mode 100644 arch/arm/common/krait-l2-accessors.c
>> create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>
>> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
>> index e5ad070..c8e1986 100644
>> --- a/arch/arm/common/Kconfig
>> +++ b/arch/arm/common/Kconfig
>> @@ -7,6 +7,9 @@ config DMABOUNCE
>> bool
>> select ZONE_DMA
>>
>> +config KRAIT_L2_ACCESSORS
>> + bool
>> +
>> config SHARP_LOCOMO
>> bool
>>
>> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
>> index 70b4a14..eec6cd1 100644
>> --- a/arch/arm/common/Makefile
>> +++ b/arch/arm/common/Makefile
>> @@ -7,6 +7,7 @@ obj-y += firmware.o
>>
>> obj-$(CONFIG_SA1111) += sa1111.o
>> obj-$(CONFIG_DMABOUNCE) += dmabounce.o
>> +obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
>> obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
>> obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
>> obj-$(CONFIG_SHARP_SCOOP) += scoop.o
>> diff --git a/arch/arm/common/krait-l2-accessors.c b/arch/arm/common/krait-l2-accessors.c
>> new file mode 100644
>> index 0000000..9a97dda
>> --- /dev/null
>> +++ b/arch/arm/common/krait-l2-accessors.c
>> @@ -0,0 +1,48 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include <linux/spinlock.h>
>> +#include <linux/export.h>
>> +
>> +#include <asm/barrier.h>
>> +#include <asm/krait-l2-accessors.h>
>> +
>> +static DEFINE_RAW_SPINLOCK(krait_l2_lock);
>> +
>> +void krait_set_l2_indirect_reg(u32 addr, u32 val)
>> +{
>> + unsigned long flags;
>> +
>> + raw_spin_lock_irqsave(&krait_l2_lock, flags);
>> + /*
>> + * Select the L2 window by poking l2cpselr, then write to the window
>> + * via l2cpdr.
>> + */
>> + asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
>> + isb();
>> + asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
>> + isb();
>> +
>> + raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
>> +}
>> +EXPORT_SYMBOL(krait_set_l2_indirect_reg);
>> +
>> +u32 krait_get_l2_indirect_reg(u32 addr)
>> +{
>> + u32 val;
>> + unsigned long flags;
>> +
>> + raw_spin_lock_irqsave(&krait_l2_lock, flags);
>> + /*
>> + * Select the L2 window by poking l2cpselr, then read from the window
>> + * via l2cpdr.
>> + */
>> + asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
>> + isb();
>> + asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
>> +
>> + raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
>> +
>> + return val;
>> +}
>> +EXPORT_SYMBOL(krait_get_l2_indirect_reg);
>> diff --git a/arch/arm/include/asm/krait-l2-accessors.h b/arch/arm/include/asm/krait-l2-accessors.h
>> new file mode 100644
>> index 0000000..dd7c474
>> --- /dev/null
>> +++ b/arch/arm/include/asm/krait-l2-accessors.h
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
>> +#define __ASMARM_KRAIT_L2_ACCESSORS_H
>> +
>> +extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
>> +extern u32 krait_get_l2_indirect_reg(u32 addr);
>> +
>> +#endif
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>>
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: Jacky Bai @ 2018-05-25 5:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM0PR04MB42110730C8F91B61CC32168480690@AM0PR04MB4211.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
> > -----Original Message-----
> > From: Jacky Bai
> > Sent: Monday, May 21, 2018 6:47 PM
> > To: shawnguo at kernel.org; robh+dt at kernel.org; kernel at pengutronix.de
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>;
> devicetree at vger.kernel.org;
> > linux-arm-kernel at lists.infradead.org; dl-linux-imx
> > <linux-imx@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> > jacky.baip at gmail.com
> > Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
> >
>
> [...]
>
> [...]
>
> > +
> > + tempmon: temperature-sensor {
> > + compatible = "fsl,imx6sll-tempmon",
> > "fsl,imx6sx-tempmon";
> > + interrupts = <GIC_SPI 49
> > IRQ_TYPE_LEVEL_HIGH>;
> > + fsl,tempmon = <&anatop>;
> > + fsl,tempmon-data = <&ocotp>;
> > + clocks = <&clks
> > IMX6SLL_CLK_PLL3_USB_OTG>;
> > + status = "disabled";
> > + };
> > +
>
> Pls move it out of SoC node to root node.
> See:
> commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of bus")
>
Ok, will move it out.
> And probably we need switch to the new way?
> See:
> commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor support")
>
I prefer to keep it same as other imx6 soc.
BR
Jacky Bai
> Otherwise:
> Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
>
> Regards
> Dong Aisheng
>
> > + usbphy1: usb-phy at 20c9000 {
> > + compatible = "fsl,imx6sll-usbphy",
> > "fsl,imx6ul-usbphy",
> > + "fsl,imx23-usbphy";
> > + reg = <0x020c9000 0x1000>;
> > + interrupts = <GIC_SPI 40
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> > + phy-3p0-supply = <®_3p0>;
> > + fsl,anatop = <&anatop>;
> > + };
> > +
> > + usbphy2: usb-phy at 20ca000 {
> > + compatible = "fsl,imx6sll-usbphy",
> > "fsl,imx6ul-usbphy",
> > + "fsl,imx23-usbphy";
> > + reg = <0x020ca000 0x1000>;
> > + interrupts = <GIC_SPI 41
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> > + phy-reg_3p0-supply = <®_3p0>;
> > + fsl,anatop = <&anatop>;
> > + };
> > +
> > + snvs: snvs at 20cc000 {
> > + compatible = "fsl,sec-v4.0-mon", "syscon",
> > "simple-mfd";
> > + reg = <0x020cc000 0x4000>;
> > +
> > + snvs_rtc: snvs-rtc-lp {
> > + compatible = "fsl,sec-v4.0-mon-rtc-
> > lp";
> > + regmap = <&snvs>;
> > + offset = <0x34>;
> > + interrupts = <GIC_SPI 19
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 20
> > IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + snvs_poweroff: snvs-poweroff {
> > + compatible = "syscon-poweroff";
> > + regmap = <&snvs>;
> > + offset = <0x38>;
> > + mask = <0x61>;
> > + };
> > +
> > + snvs_pwrkey: snvs-powerkey {
> > + compatible = "fsl,sec-v4.0-pwrkey";
> > + regmap = <&snvs>;
> > + interrupts = <GIC_SPI 4
> > IRQ_TYPE_LEVEL_HIGH>;
> > + linux,keycode = <KEY_POWER>;
> > + wakeup-source;
> > + };
> > + };
> > +
> > + src: reset-controller at 20d8000 {
> > + compatible = "fsl,imx6sll-src";
> > + reg = <0x020d8000 0x4000>;
> > + interrupts = <GIC_SPI 91
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 96
> > IRQ_TYPE_LEVEL_HIGH>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + gpc: interrupt-controller at 20dc000 {
> > + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> > gpc";
> > + reg = <0x020dc000 0x4000>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupts = <GIC_SPI 89
> > IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-parent = <&intc>;
> > + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> > 0x0 0x1400640>;
> > + };
> > +
> > + iomuxc: pinctrl at 20e0000 {
> > + compatible = "fsl,imx6sll-iomuxc";
> > + reg = <0x020e0000 0x4000>;
> > + };
> > +
> > + gpr: iomuxc-gpr at 20e4000 {
> > + compatible = "fsl,imx6sll-iomuxc-gpr",
> > + "fsl,imx6q-iomuxc-gpr", "syscon";
> > + reg = <0x020e4000 0x4000>;
> > + };
> > +
> > + csi: csi at 20e8000 {
> > + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> > + reg = <0x020e8000 0x4000>;
> > + interrupts = <GIC_SPI 7
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> > + <&clks IMX6SLL_CLK_CSI>,
> > + <&clks IMX6SLL_CLK_DUMMY>;
> > + clock-names = "disp-axi", "csi_mclk",
> > "disp_dcic";
> > + status = "disabled";
> > + };
> > +
> > + sdma: dma-controller at 20ec000 {
> > + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> > sdma";
> > + reg = <0x020ec000 0x4000>;
> > + interrupts = <GIC_SPI 2
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_SDMA>,
> > + <&clks IMX6SLL_CLK_SDMA>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + iram = <&ocram>;
> > + fsl,sdma-ram-script-name =
> > "imx/sdma/sdma-imx6q.bin";
> > + };
> > +
> > + lcdif: lcd-controller at 20f8000 {
> > + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> > lcdif";
> > + reg = <0x020f8000 0x4000>;
> > + interrupts = <GIC_SPI 39
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> > + <&clks IMX6SLL_CLK_LCDIF_APB>,
> > + <&clks IMX6SLL_CLK_DUMMY>;
> > + clock-names = "pix", "axi", "disp_axi";
> > + status = "disabled";
> > + };
> > +
> > + dcp: dcp at 20fc000 {
> > + compatible = "fsl,imx28-dcp";
> > + reg = <0x020fc000 0x4000>;
> > + interrupts = <GIC_SPI 99
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 100
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 101
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_DCP>;
> > + clock-names = "dcp";
> > + };
> > + };
> > +
> > + aips2: aips-bus at 2100000 {
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + reg = <0x02100000 0x100000>;
> > + ranges;
> > +
> > + usbotg1: usb at 2184000 {
> > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > usb",
> > + "fsl,imx27-usb";
> > + reg = <0x02184000 0x200>;
> > + interrupts = <GIC_SPI 43
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > + fsl,usbphy = <&usbphy1>;
> > + fsl,usbmisc = <&usbmisc 0>;
> > + fsl,anatop = <&anatop>;
> > + ahb-burst-config = <0x0>;
> > + tx-burst-size-dword = <0x10>;
> > + rx-burst-size-dword = <0x10>;
> > + status = "disabled";
> > + };
> > +
> > + usbotg2: usb at 2184200 {
> > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > usb",
> > + "fsl,imx27-usb";
> > + reg = <0x02184200 0x200>;
> > + interrupts = <GIC_SPI 42
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > + fsl,usbphy = <&usbphy2>;
> > + fsl,usbmisc = <&usbmisc 1>;
> > + ahb-burst-config = <0x0>;
> > + tx-burst-size-dword = <0x10>;
> > + rx-burst-size-dword = <0x10>;
> > + status = "disabled";
> > + };
> > +
> > + usbmisc: usbmisc at 2184800 {
> > + #index-cells = <1>;
> > + compatible = "fsl,imx6sll-usbmisc",
> > "fsl,imx6ul-usbmisc",
> > + "fsl,imx6q-usbmisc";
> > + reg = <0x02184800 0x200>;
> > + };
> > +
> > + usdhc1: mmc at 2190000 {
> > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > usdhc";
> > + reg = <0x02190000 0x4000>;
> > + interrupts = <GIC_SPI 22
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> > + <&clks IMX6SLL_CLK_USDHC1>,
> > + <&clks IMX6SLL_CLK_USDHC1>;
> > + clock-names = "ipg", "ahb", "per";
> > + bus-width = <4>;
> > + fsl,tuning-step = <2>;
> > + fsl,tuning-start-tap = <20>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc2: mmc at 2194000 {
> > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > usdhc";
> > + reg = <0x02194000 0x4000>;
> > + interrupts = <GIC_SPI 23
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> > + <&clks IMX6SLL_CLK_USDHC2>,
> > + <&clks IMX6SLL_CLK_USDHC2>;
> > + clock-names = "ipg", "ahb", "per";
> > + bus-width = <4>;
> > + fsl,tuning-step = <2>;
> > + fsl,tuning-start-tap = <20>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc3: mmc at 2198000 {
> > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > usdhc";
> > + reg = <0x02198000 0x4000>;
> > + interrupts = <GIC_SPI 24
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> > + <&clks IMX6SLL_CLK_USDHC3>,
> > + <&clks IMX6SLL_CLK_USDHC3>;
> > + clock-names = "ipg", "ahb", "per";
> > + bus-width = <4>;
> > + fsl,tuning-step = <2>;
> > + fsl,tuning-start-tap = <20>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c at 21a0000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> > + reg = <0x021a0000 0x4000>;
> > + interrupts = <GIC_SPI 36
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_I2C1>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c at 21a4000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > + reg = <0x021a4000 0x4000>;
> > + interrupts = <GIC_SPI 37
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_I2C2>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c at 21a8000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > + reg = <0x021a8000 0x4000>;
> > + interrupts = <GIC_SPI 38
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clks IMX6SLL_CLK_I2C3>;
> > + status = "disabled";
> > + };
> > +
> > + mmdc: memory-controller at 21b0000 {
> > + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> > mmdc";
> > + reg = <0x021b0000 0x4000>;
> > + };
> > +
> > + ocotp: ocotp-ctrl at 21bc000 {
> > + compatible = "fsl,imx6sll-ocotp", "syscon";
> > + reg = <0x021bc000 0x4000>;
> > + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> > + };
> > +
> > + audmux: audmux at 21d8000 {
> > + compatible = "fsl,imx6sll-audmux",
> > "fsl,imx31-audmux";
> > + reg = <0x021d8000 0x4000>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial at 21f4000 {
> > + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> > uart",
> > + "fsl,imx21-uart";
> > + reg = <0x021f4000 0x4000>;
> > + interrupts =<GIC_SPI 30
> > IRQ_TYPE_LEVEL_HIGH>;
> > + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> > + dma-names = "rx", "tx";
> > + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> > + <&clks
> > IMX6SLL_CLK_UART5_SERIAL>;
> > + clock-names = "ipg", "per";
> > + status = "disabled";
> > + };
> > + };
> > + };
> > +};
> > --
> > 1.9.1
^ permalink raw reply
* [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: A.s. Dong @ 2018-05-25 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <HE1PR04MB3113D024D0BCCB6B96F0D8F687690@HE1PR04MB3113.eurprd04.prod.outlook.com>
Hi Jacky,
> -----Original Message-----
> From: Jacky Bai
> Sent: Friday, May 25, 2018 1:44 PM
> To: A.s. Dong <aisheng.dong@nxp.com>; shawnguo at kernel.org;
> robh+dt at kernel.org; kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> jacky.baip at gmail.com
> Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
> > Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > imx6sll
> >
> > > -----Original Message-----
> > > From: Jacky Bai
> > > Sent: Monday, May 21, 2018 6:47 PM
> > > To: shawnguo at kernel.org; robh+dt at kernel.org; kernel at pengutronix.de
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>;
> > devicetree at vger.kernel.org;
> > > linux-arm-kernel at lists.infradead.org; dl-linux-imx
> > > <linux-imx@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> > > jacky.baip at gmail.com
> > > Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > > imx6sll
> > >
> >
> > [...]
> >
> > [...]
> >
> > > +
> > > + tempmon: temperature-sensor {
> > > + compatible = "fsl,imx6sll-tempmon",
> > > "fsl,imx6sx-tempmon";
> > > + interrupts = <GIC_SPI 49
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + fsl,tempmon = <&anatop>;
> > > + fsl,tempmon-data = <&ocotp>;
> > > + clocks = <&clks
> > > IMX6SLL_CLK_PLL3_USB_OTG>;
> > > + status = "disabled";
> > > + };
> > > +
> >
> > Pls move it out of SoC node to root node.
> > See:
> > commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of bus")
> >
> Ok, will move it out.
>
> > And probably we need switch to the new way?
> > See:
> > commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor
> > support")
> >
>
> I prefer to keep it same as other imx6 soc.
>
Would you please check below patch?
commit a6c856e9a8c ("ARM: dts: imx6sx: Use nvmem-cells for tempmon")
If mx6sll has the same issue as mx6sx, then we may have to use nvmem-cells.
If not, I'm ok with old way.
And please make sure the OTP clk used is correct.
Regards
Dong Aisheng
> BR
> Jacky Bai
> > Otherwise:
> > Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
> >
> > Regards
> > Dong Aisheng
> >
> > > + usbphy1: usb-phy at 20c9000 {
> > > + compatible = "fsl,imx6sll-usbphy",
> > > "fsl,imx6ul-usbphy",
> > > + "fsl,imx23-usbphy";
> > > + reg = <0x020c9000 0x1000>;
> > > + interrupts = <GIC_SPI 40
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> > > + phy-3p0-supply = <®_3p0>;
> > > + fsl,anatop = <&anatop>;
> > > + };
> > > +
> > > + usbphy2: usb-phy at 20ca000 {
> > > + compatible = "fsl,imx6sll-usbphy",
> > > "fsl,imx6ul-usbphy",
> > > + "fsl,imx23-usbphy";
> > > + reg = <0x020ca000 0x1000>;
> > > + interrupts = <GIC_SPI 41
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> > > + phy-reg_3p0-supply = <®_3p0>;
> > > + fsl,anatop = <&anatop>;
> > > + };
> > > +
> > > + snvs: snvs at 20cc000 {
> > > + compatible = "fsl,sec-v4.0-mon", "syscon",
> > > "simple-mfd";
> > > + reg = <0x020cc000 0x4000>;
> > > +
> > > + snvs_rtc: snvs-rtc-lp {
> > > + compatible = "fsl,sec-v4.0-mon-rtc-
> > > lp";
> > > + regmap = <&snvs>;
> > > + offset = <0x34>;
> > > + interrupts = <GIC_SPI 19
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 20
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + snvs_poweroff: snvs-poweroff {
> > > + compatible = "syscon-poweroff";
> > > + regmap = <&snvs>;
> > > + offset = <0x38>;
> > > + mask = <0x61>;
> > > + };
> > > +
> > > + snvs_pwrkey: snvs-powerkey {
> > > + compatible = "fsl,sec-v4.0-pwrkey";
> > > + regmap = <&snvs>;
> > > + interrupts = <GIC_SPI 4
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + linux,keycode = <KEY_POWER>;
> > > + wakeup-source;
> > > + };
> > > + };
> > > +
> > > + src: reset-controller at 20d8000 {
> > > + compatible = "fsl,imx6sll-src";
> > > + reg = <0x020d8000 0x4000>;
> > > + interrupts = <GIC_SPI 91
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 96
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + #reset-cells = <1>;
> > > + };
> > > +
> > > + gpc: interrupt-controller at 20dc000 {
> > > + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> > > gpc";
> > > + reg = <0x020dc000 0x4000>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + interrupts = <GIC_SPI 89
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-parent = <&intc>;
> > > + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> > > 0x0 0x1400640>;
> > > + };
> > > +
> > > + iomuxc: pinctrl at 20e0000 {
> > > + compatible = "fsl,imx6sll-iomuxc";
> > > + reg = <0x020e0000 0x4000>;
> > > + };
> > > +
> > > + gpr: iomuxc-gpr at 20e4000 {
> > > + compatible = "fsl,imx6sll-iomuxc-gpr",
> > > + "fsl,imx6q-iomuxc-gpr", "syscon";
> > > + reg = <0x020e4000 0x4000>;
> > > + };
> > > +
> > > + csi: csi at 20e8000 {
> > > + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> > > + reg = <0x020e8000 0x4000>;
> > > + interrupts = <GIC_SPI 7
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> > > + <&clks IMX6SLL_CLK_CSI>,
> > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > + clock-names = "disp-axi", "csi_mclk",
> > > "disp_dcic";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sdma: dma-controller at 20ec000 {
> > > + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> > > sdma";
> > > + reg = <0x020ec000 0x4000>;
> > > + interrupts = <GIC_SPI 2
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_SDMA>,
> > > + <&clks IMX6SLL_CLK_SDMA>;
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + iram = <&ocram>;
> > > + fsl,sdma-ram-script-name =
> > > "imx/sdma/sdma-imx6q.bin";
> > > + };
> > > +
> > > + lcdif: lcd-controller at 20f8000 {
> > > + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> > > lcdif";
> > > + reg = <0x020f8000 0x4000>;
> > > + interrupts = <GIC_SPI 39
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> > > + <&clks IMX6SLL_CLK_LCDIF_APB>,
> > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > + clock-names = "pix", "axi", "disp_axi";
> > > + status = "disabled";
> > > + };
> > > +
> > > + dcp: dcp at 20fc000 {
> > > + compatible = "fsl,imx28-dcp";
> > > + reg = <0x020fc000 0x4000>;
> > > + interrupts = <GIC_SPI 99
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 100
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 101
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_DCP>;
> > > + clock-names = "dcp";
> > > + };
> > > + };
> > > +
> > > + aips2: aips-bus at 2100000 {
> > > + compatible = "fsl,aips-bus", "simple-bus";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + reg = <0x02100000 0x100000>;
> > > + ranges;
> > > +
> > > + usbotg1: usb at 2184000 {
> > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > usb",
> > > + "fsl,imx27-usb";
> > > + reg = <0x02184000 0x200>;
> > > + interrupts = <GIC_SPI 43
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > + fsl,usbphy = <&usbphy1>;
> > > + fsl,usbmisc = <&usbmisc 0>;
> > > + fsl,anatop = <&anatop>;
> > > + ahb-burst-config = <0x0>;
> > > + tx-burst-size-dword = <0x10>;
> > > + rx-burst-size-dword = <0x10>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usbotg2: usb at 2184200 {
> > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > usb",
> > > + "fsl,imx27-usb";
> > > + reg = <0x02184200 0x200>;
> > > + interrupts = <GIC_SPI 42
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > + fsl,usbphy = <&usbphy2>;
> > > + fsl,usbmisc = <&usbmisc 1>;
> > > + ahb-burst-config = <0x0>;
> > > + tx-burst-size-dword = <0x10>;
> > > + rx-burst-size-dword = <0x10>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usbmisc: usbmisc at 2184800 {
> > > + #index-cells = <1>;
> > > + compatible = "fsl,imx6sll-usbmisc",
> > > "fsl,imx6ul-usbmisc",
> > > + "fsl,imx6q-usbmisc";
> > > + reg = <0x02184800 0x200>;
> > > + };
> > > +
> > > + usdhc1: mmc at 2190000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02190000 0x4000>;
> > > + interrupts = <GIC_SPI 22
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> > > + <&clks IMX6SLL_CLK_USDHC1>,
> > > + <&clks IMX6SLL_CLK_USDHC1>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc2: mmc at 2194000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02194000 0x4000>;
> > > + interrupts = <GIC_SPI 23
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> > > + <&clks IMX6SLL_CLK_USDHC2>,
> > > + <&clks IMX6SLL_CLK_USDHC2>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc3: mmc at 2198000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02198000 0x4000>;
> > > + interrupts = <GIC_SPI 24
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> > > + <&clks IMX6SLL_CLK_USDHC3>,
> > > + <&clks IMX6SLL_CLK_USDHC3>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c1: i2c at 21a0000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a0000 0x4000>;
> > > + interrupts = <GIC_SPI 36
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c2: i2c at 21a4000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a4000 0x4000>;
> > > + interrupts = <GIC_SPI 37
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C2>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c3: i2c at 21a8000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a8000 0x4000>;
> > > + interrupts = <GIC_SPI 38
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C3>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + mmdc: memory-controller at 21b0000 {
> > > + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> > > mmdc";
> > > + reg = <0x021b0000 0x4000>;
> > > + };
> > > +
> > > + ocotp: ocotp-ctrl at 21bc000 {
> > > + compatible = "fsl,imx6sll-ocotp", "syscon";
> > > + reg = <0x021bc000 0x4000>;
> > > + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> > > + };
> > > +
> > > + audmux: audmux at 21d8000 {
> > > + compatible = "fsl,imx6sll-audmux",
> > > "fsl,imx31-audmux";
> > > + reg = <0x021d8000 0x4000>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart5: serial at 21f4000 {
> > > + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> > > uart",
> > > + "fsl,imx21-uart";
> > > + reg = <0x021f4000 0x4000>;
> > > + interrupts =<GIC_SPI 30
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> > > + dma-names = "rx", "tx";
> > > + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> > > + <&clks
> > > IMX6SLL_CLK_UART5_SERIAL>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > + };
> > > + };
> > > +};
> > > --
> > > 1.9.1
^ permalink raw reply
* [PATCH v8 00/12] ARM: dts: ipq: updates to enable a few peripherals
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.
[V8]
* Rebased on top of Andy's for-next
[V7]
* Fixed Kbuild git bisectability issue
[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.
[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html
[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
that might break existing users whose u-boot do not
specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
the default serial console specified from DT.
[v3]
* Fixed minor comments from v2,
https://www.spinics.net/lists/arm-kernel/msg641480.html
* Added Abhishek's review tags
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4019: Add a default chosen node
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Enable few peripherals for hk01 board
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 10 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 +++++++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 ++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++++++++++--
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 313 +++++++++++++++++++++++-
11 files changed, 827 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v8 01/12] ARM: dts: ipq4019: Add a default chosen node
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
soc {
rng at 22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index b25daf3..2efc8a2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -272,7 +272,7 @@
regulator;
};
- serial at 78af000 {
+ blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 02/12] ARM: dts: ipq4019: Add a few peripheral nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
2 files changed, 146 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
- spi_0: spi at 78b5000 {
+ spi at 78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2efc8a2..737097e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,8 +40,10 @@
};
aliases {
- spi0 = &spi_0;
- i2c0 = &i2c_0;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
};
cpus {
@@ -120,6 +122,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -165,13 +173,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp_dma: dma at 7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -179,7 +187,7 @@
status = "disabled";
};
- spi_0: spi at 78b5000 {
+ blsp1_spi1: spi at 78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -188,10 +196,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ blsp1_spi2: spi at 78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- i2c_0: i2c at 78b7000 {
+ blsp1_i2c3: i2c at 78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -200,14 +224,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ blsp1_i2c4: i2c at 78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma at 8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
- interrupts = <GIC_SPI 207 0>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -275,7 +314,7 @@
blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- interrupts = <0 107 0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -287,7 +326,7 @@
serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
- interrupts = <0 108 0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -309,6 +348,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci at 40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma at 7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand at 79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand at 0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi at a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
@@ -342,7 +476,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 168 IRQ_TYPE_NONE>;
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
@@ -384,7 +518,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 169 IRQ_TYPE_NONE>;
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 03/12] ARM: dts: ipq4019: Change the max opp frequency
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 737097e..ad61a55 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -63,7 +63,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ spi at 78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pci at 40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ad61a55..7bcd763 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -323,7 +323,7 @@
dma-names = "rx", "tx";
};
- serial at 78b0000 {
+ blsp1_uart2: serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Tested-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+ compatible = "qcom,ipq4019-dk04.1-c1";
+
+ soc {
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ i2c at 78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+ compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+ soc {
+ pci at 40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ spi at 78b6000 {
+ status = "ok";
+ };
+
+ pinctrl at 1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ spi at 78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 0000000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+ compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+ soc {
+ pinctrl at 1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 10/12] ARM: dts: ipq8074: Add peripheral nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 12 ---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +++++++++++++++++++++++++++++-
2 files changed, 155 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..72c5b4a3 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -33,19 +33,7 @@
};
soc {
- pinctrl at 1000000 {
- serial_4_pins: serial4_pinmux {
- mux {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- bias-disable;
- };
- };
- };
-
serial at 78b3000 {
- pinctrl-0 = <&serial_4_pins>;
- pinctrl-names = "default";
status = "ok";
};
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+ serial_4_pins: serial4-pinmux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pins {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ hsuart_pins: hsuart-pins {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ qpic_pins: qpic-pins {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
intc: interrupt-controller at b000000 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp_dma: dma at 7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart1: serial at 78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart3: serial at 78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b1000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>,
+ <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&hsuart_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi at 78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c2: i2c at 78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+ dma-names = "rx", "tx";
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c3: i2c at 78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ qpic_bam: dma at 7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand at 79b0000 {
+ compatible = "qcom,ipq8074-nand";
+ reg = <0x79b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
status = "disabled";
};
};
@@ -175,7 +329,7 @@
pmu {
compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 11/12] ARM: dts: ipq8074: Add pcie nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl at 1000000 {
+ tlmm: pinctrl at 1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+ pcie_phy0: phy at 86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci at 20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000f20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy at 8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci at 10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox