* [PATCH RESEND V4 0/9] clk: add imx7ulp clk support
From: Dong Aisheng @ 2018-05-25 7:51 UTC (permalink / raw)
To: linux-arm-kernel
This is a rebased version of below patch series against latest clk tree.
[PATCH RESEND V3 0/9] clk: add imx7ulp clk support
https://lkml.org/lkml/2018/3/16/310
It only updates the license to SPDX format as well as a minor fix of
pllv4.
This patch series intends to add imx7ulp clk support.
i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
The clocking scheme provides clear separation between M4 domain
and A7 domain. Except for a few clock sources shared between two
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
and and the Fast IRC clock (FIRCLK), clock sources and clock
management are separated and contained within each domain.
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
Note: this series only adds A7 clock domain support as M4 clock
domain will be handled by M4 seperately.
Change Log:
v2->v3:
* Patch 1 changed on: 1) split normal and gate ops 2) fix the possible racy
Others no changes.
v1->v2:
* add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
* use clk_hw apis to register clocks
* use of_clk_add_hw_provider
* split the clocks register process into two parts: early part for possible
timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part for
the left normal peripheral clocks registered by a platform driver.
Dong Aisheng (9):
clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
clk: imx: add pllv4 support
clk: imx: add pfdv2 support
clk: imx: add composite clk support
dt-bindings: clock: add imx7ulp clock binding doc
clk: imx: make mux parent strings const
clk: imx: implement new clk_hw based APIs
clk: imx: add imx7ulp clk driver
.../devicetree/bindings/clock/imx7ulp-clock.txt | 62 ++++++
drivers/clk/clk-divider.c | 152 ++++++++++++++
drivers/clk/clk-fractional-divider.c | 10 +
drivers/clk/imx/Makefile | 6 +-
drivers/clk/imx/clk-busy.c | 2 +-
drivers/clk/imx/clk-composite.c | 85 ++++++++
drivers/clk/imx/clk-fixup-mux.c | 2 +-
drivers/clk/imx/clk-imx7ulp.c | 227 +++++++++++++++++++++
drivers/clk/imx/clk-pfdv2.c | 201 ++++++++++++++++++
drivers/clk/imx/clk-pllv4.c | 182 +++++++++++++++++
drivers/clk/imx/clk.c | 22 ++
drivers/clk/imx/clk.h | 92 ++++++++-
include/dt-bindings/clock/imx7ulp-clock.h | 105 ++++++++++
include/linux/clk-provider.h | 17 ++
14 files changed, 1155 insertions(+), 10 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
create mode 100644 drivers/clk/imx/clk-composite.c
create mode 100644 drivers/clk/imx/clk-imx7ulp.c
create mode 100644 drivers/clk/imx/clk-pfdv2.c
create mode 100644 drivers/clk/imx/clk-pllv4.c
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
--
2.7.4
^ permalink raw reply
* [PATCH V0:net-next 4/4] dt-bindings: stm32: add compatible for syscon
From: Christophe Roullier @ 2018-05-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527234401-15812-1-git-send-email-christophe.roullier@st.com>
This patch describes syscon DT bindings.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++++++++++++++
.../devicetree/bindings/arm/{ => stm32}/stm32.txt | 0
2 files changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
new file mode 100644
index 0000000..99980ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 Platforms System Controller
+
+Properties:
+ - compatible : should contain two values. First value must be :
+ - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
+ second value must be always "syscon".
+ - reg : offset and length of the register set.
+
+ Example:
+ syscfg: syscon at 50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ };
+
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32/stm32.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/stm32.txt
rename to Documentation/devicetree/bindings/arm/stm32/stm32.txt
--
1.9.1
^ permalink raw reply related
* [PATCH V0:net-next 3/4] net: stmmac: add dwmac-4.20a compatible
From: Christophe Roullier @ 2018-05-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527234401-15812-1-git-send-email-christophe.roullier@st.com>
Manage dwmac-4.20a version from synopsys
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index ebd3e5f..6d141f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -472,7 +472,8 @@ struct plat_stmmacenet_data *
}
if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
- of_device_is_compatible(np, "snps,dwmac-4.10a")) {
+ of_device_is_compatible(np, "snps,dwmac-4.10a") ||
+ of_device_is_compatible(np, "snps,dwmac-4.20a")) {
plat->has_gmac4 = 1;
plat->has_gmac = 0;
plat->pmt = 1;
--
1.9.1
^ permalink raw reply related
* [PATCH V0:net-next 2/4] dt-bindings: stm32-dwmac: add support of MPU families
From: Christophe Roullier @ 2018-05-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527234401-15812-1-git-send-email-christophe.roullier@st.com>
Add description for Ethernet MPU families fields
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/net/stm32-dwmac.txt | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
index 489dbcb..1341012 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -6,14 +6,28 @@ Please see stmmac.txt for the other unchanged properties.
The device node has following properties.
Required properties:
-- compatible: Should be "st,stm32-dwmac" to select glue, and
+- compatible: For MCU family should be "st,stm32-dwmac" to select glue, and
"snps,dwmac-3.50a" to select IP version.
+ For MPU family should be "st,stm32mp1-dwmac" to select
+ glue, and "snps,dwmac-4.20a" to select IP version.
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: Should be "stmmaceth" for the host clock.
Should be "mac-clk-tx" for the MAC TX clock.
Should be "mac-clk-rx" for the MAC RX clock.
+ For MPU family need to add also "ethstp" for power mode clock and,
+ "syscfg-clk" for SYSCFG clock.
+- interrupt-names: Should contain a list of interrupt names corresponding to
+ the interrupts in the interrupts property, if available.
+ Should be "macirq" for the main MAC IRQ
+ Should be "eth_wake_irq" for the IT which wake up system
- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register.
+ encompases the glue register, and the offset of the control register.
+
+Optional properties:
+- clock-names: For MPU family "mac-clk-ck" for PHY without quartz
+- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock
+ by RCC
+
Example:
ethernet at 40028000 {
--
1.9.1
^ permalink raw reply related
* [PATCH V0:net-next 1/4] net: ethernet: stmmac: add adaptation for stm32mp157c.
From: Christophe Roullier @ 2018-05-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527234401-15812-1-git-send-email-christophe.roullier@st.com>
Glue codes to support stm32mp157c device and stay
compatible with stm32 mcu familly
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 267 ++++++++++++++++++++--
1 file changed, 252 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 9e6db16..7e2e79d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -16,49 +16,180 @@
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/stmmac.h>
#include "stmmac_platform.h"
-#define MII_PHY_SEL_MASK BIT(23)
+#define SYSCFG_MCU_ETH_MASK BIT(23)
+#define SYSCFG_MP1_ETH_MASK GENMASK(23, 16)
+
+#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16)
+#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17)
+#define SYSCFG_PMCR_ETH_SEL_MII BIT(20)
+#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
+#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
+#define SYSCFG_PMCR_ETH_SEL_GMII 0
+#define SYSCFG_MCU_ETH_SEL_MII 0
+#define SYSCFG_MCU_ETH_SEL_RMII 1
struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
+ struct clk *clk_eth_ck;
+ struct clk *clk_ethstp;
+ struct clk *syscfg_clk;
+ bool int_phyclk; /* Clock from RCC to drive PHY */
u32 mode_reg; /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
+ const struct stm32_ops *ops;
+ struct device *dev;
+};
+
+struct stm32_ops {
+ int (*set_mode)(struct plat_stmmacenet_data *plat_dat);
+ int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
+ int (*suspend)(struct stm32_dwmac *dwmac);
+ void (*resume)(struct stm32_dwmac *dwmac);
+ int (*parse_data)(struct stm32_dwmac *dwmac,
+ struct device *dev);
+ u32 syscfg_eth_mask;
};
static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
- u32 reg = dwmac->mode_reg;
- u32 val;
int ret;
- val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
- ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
- if (ret)
- return ret;
+ if (dwmac->ops->set_mode) {
+ ret = dwmac->ops->set_mode(plat_dat);
+ if (ret)
+ return ret;
+ }
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
- ret = clk_prepare_enable(dwmac->clk_rx);
- if (ret)
- clk_disable_unprepare(dwmac->clk_tx);
+ if (!dwmac->dev->power.is_suspended) {
+ ret = clk_prepare_enable(dwmac->clk_rx);
+ if (ret) {
+ clk_disable_unprepare(dwmac->clk_tx);
+ return ret;
+ }
+ }
+
+ if (dwmac->ops->clk_prepare) {
+ ret = dwmac->ops->clk_prepare(dwmac, true);
+ if (ret) {
+ clk_disable_unprepare(dwmac->clk_rx);
+ clk_disable_unprepare(dwmac->clk_tx);
+ }
+ }
return ret;
}
+static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+ int ret = 0;
+
+ if (prepare) {
+ ret = clk_prepare_enable(dwmac->syscfg_clk);
+ if (ret)
+ return ret;
+
+ if (dwmac->int_phyclk) {
+ ret = clk_prepare_enable(dwmac->clk_eth_ck);
+ if (ret) {
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ return ret;
+ }
+ }
+ } else {
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ if (dwmac->int_phyclk)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
+ }
+ return ret;
+}
+
+static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ u32 reg = dwmac->mode_reg;
+ int val;
+
+ switch (plat_dat->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = SYSCFG_PMCR_ETH_SEL_MII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ val = SYSCFG_PMCR_ETH_SEL_GMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n");
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val = SYSCFG_PMCR_ETH_SEL_RMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ val = SYSCFG_PMCR_ETH_SEL_RGMII;
+ if (dwmac->int_phyclk)
+ val |= SYSCFG_PMCR_ETH_CLK_SEL;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n");
+ break;
+ default:
+ pr_debug("SYSCFG init : Do not manage %d interface\n",
+ plat_dat->interface);
+ /* Do not manage others interfaces */
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(dwmac->regmap, reg,
+ dwmac->ops->syscfg_eth_mask, val);
+}
+
+static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)
+{
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ u32 reg = dwmac->mode_reg;
+ int val;
+
+ switch (plat_dat->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = SYSCFG_MCU_ETH_SEL_MII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n");
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ val = SYSCFG_MCU_ETH_SEL_RMII;
+ pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n");
+ break;
+ default:
+ pr_debug("SYSCFG init : Do not manage %d interface\n",
+ plat_dat->interface);
+ /* Do not manage others interfaces */
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(dwmac->regmap, reg,
+ dwmac->ops->syscfg_eth_mask, val);
+}
+
static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
{
clk_disable_unprepare(dwmac->clk_tx);
clk_disable_unprepare(dwmac->clk_rx);
+
+ if (dwmac->ops->clk_prepare)
+ dwmac->ops->clk_prepare(dwmac, false);
}
static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
@@ -70,15 +201,22 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
/* Get TX/RX clocks */
dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
if (IS_ERR(dwmac->clk_tx)) {
- dev_err(dev, "No tx clock provided...\n");
+ dev_err(dev, "No ETH Tx clock provided...\n");
return PTR_ERR(dwmac->clk_tx);
}
+
dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
if (IS_ERR(dwmac->clk_rx)) {
- dev_err(dev, "No rx clock provided...\n");
+ dev_err(dev, "No ETH Rx clock provided...\n");
return PTR_ERR(dwmac->clk_rx);
}
+ if (dwmac->ops->parse_data) {
+ err = dwmac->ops->parse_data(dwmac, dev);
+ if (err)
+ return err;
+ }
+
/* Get mode register */
dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
if (IS_ERR(dwmac->regmap))
@@ -91,11 +229,46 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
return err;
}
+static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+
+ dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
+
+ /* Check if internal clk from RCC selected */
+ if (dwmac->int_phyclk) {
+ /* Get ETH_CLK clocks */
+ dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
+ if (IS_ERR(dwmac->clk_eth_ck)) {
+ dev_err(dev, "No ETH CK clock provided...\n");
+ return PTR_ERR(dwmac->clk_eth_ck);
+ }
+ }
+
+ /* Clock used for low power mode */
+ dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
+ if (IS_ERR(dwmac->clk_ethstp)) {
+ dev_err(dev, "No ETH peripheral clock provided for CStop mode ...\n");
+ return PTR_ERR(dwmac->clk_ethstp);
+ }
+
+ /* Clock for sysconfig */
+ dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
+ if (IS_ERR(dwmac->syscfg_clk)) {
+ dev_err(dev, "No syscfg clock provided...\n");
+ return PTR_ERR(dwmac->syscfg_clk);
+ }
+
+ return 0;
+}
+
static int stm32_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct stm32_dwmac *dwmac;
+ const struct stm32_ops *data;
int ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -112,6 +285,16 @@ static int stm32_dwmac_probe(struct platform_device *pdev)
goto err_remove_config_dt;
}
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev, "no of match data provided\n");
+ ret = -EINVAL;
+ goto err_remove_config_dt;
+ }
+
+ dwmac->ops = data;
+ dwmac->dev = &pdev->dev;
+
ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Unable to parse OF data\n");
@@ -149,15 +332,48 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
return ret;
}
+static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
+{
+ int ret = 0;
+
+ ret = clk_prepare_enable(dwmac->clk_ethstp);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(dwmac->clk_tx);
+ clk_disable_unprepare(dwmac->syscfg_clk);
+ if (dwmac->int_phyclk)
+ clk_disable_unprepare(dwmac->clk_eth_ck);
+
+ return ret;
+}
+
+static void stm32mp1_resume(struct stm32_dwmac *dwmac)
+{
+ clk_disable_unprepare(dwmac->clk_ethstp);
+}
+
+static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
+{
+ clk_disable_unprepare(dwmac->clk_tx);
+ clk_disable_unprepare(dwmac->clk_rx);
+
+ return 0;
+}
+
#ifdef CONFIG_PM_SLEEP
static int stm32_dwmac_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
+ struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
+
int ret;
ret = stmmac_suspend(dev);
- stm32_dwmac_clk_disable(priv->plat->bsp_priv);
+
+ if (dwmac->ops->suspend)
+ ret = dwmac->ops->suspend(dwmac);
return ret;
}
@@ -166,8 +382,12 @@ static int stm32_dwmac_resume(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
+ struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
int ret;
+ if (dwmac->ops->resume)
+ dwmac->ops->resume(dwmac);
+
ret = stm32_dwmac_init(priv->plat);
if (ret)
return ret;
@@ -181,8 +401,24 @@ static int stm32_dwmac_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
stm32_dwmac_suspend, stm32_dwmac_resume);
+static struct stm32_ops stm32mcu_dwmac_data = {
+ .set_mode = stm32mcu_set_mode,
+ .suspend = stm32mcu_suspend,
+ .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
+};
+
+static struct stm32_ops stm32mp1_dwmac_data = {
+ .set_mode = stm32mp1_set_mode,
+ .clk_prepare = stm32mp1_clk_prepare,
+ .suspend = stm32mp1_suspend,
+ .resume = stm32mp1_resume,
+ .parse_data = stm32mp1_parse_data,
+ .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
+};
+
static const struct of_device_id stm32_dwmac_match[] = {
- { .compatible = "st,stm32-dwmac"},
+ { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
+ { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
{ }
};
MODULE_DEVICE_TABLE(of, stm32_dwmac_match);
@@ -199,5 +435,6 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
module_platform_driver(stm32_dwmac_driver);
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@gmail.com>");
-MODULE_DESCRIPTION("STMicroelectronics MCU DWMAC Specific Glue layer");
+MODULE_AUTHOR("Christophe Roullier <christophe.roullier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics STM32 DWMAC Specific Glue layer");
MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH V0:net-next 0/4] net: ethernet: stmmac: add support for stm32mp1
From: Christophe Roullier @ 2018-05-25 7:46 UTC (permalink / raw)
To: linux-arm-kernel
Patches to have Ethernet support on stm32mp1
Christophe Roullier (4):
net: ethernet: stmmac: add adaptation for stm32mp157c.
dt-bindings: stm32-dwmac: add support of MPU families
net: stmmac: add dwmac-4.20a compatible
dt-bindings: stm32: add compatible for syscon
.../devicetree/bindings/arm/stm32/stm32-syscon.txt | 14 ++
.../devicetree/bindings/arm/{ => stm32}/stm32.txt | 0
.../devicetree/bindings/net/stm32-dwmac.txt | 18 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 267 +++++++++++++++++++--
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +-
5 files changed, 284 insertions(+), 18 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt
rename Documentation/devicetree/bindings/arm/{ => stm32}/stm32.txt (100%)
--
1.9.1
^ permalink raw reply
* [PATCH v7 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK board
From: Bai Ping @ 2018-05-25 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527234127-11991-1-git-send-email-ping.bai@nxp.com>
Add dts file support for imx6sll EVK board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
---
change v3->v4
- update the license indentifier
- remove leading zero of node
- remove unused pin from hog group
change v4->v5
- use generic name for device node
- remove unnecessary hog pin group
change v5->v6
- no
change v6->v7
- move the iomuxc node to the end of dts file
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx6sll-evk.dts | 317 ++++++++++++++++++++++++++
3 files changed, 323 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sll-evk.dts
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index cdb9dd7..8a1baa2 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+i.MX6SLL EVK board
+Required root node properties:
+ - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
Generic i.MX boards
-------------------
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4753b0..f3fb85f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -521,6 +521,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-warp.dtb
+dtb-$(CONFIG_SOC_IMX6SLL) += \
+ imx6sll-evk.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
new file mode 100644
index 0000000..0f5bd16
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+ model = "Freescale i.MX6SLL EVK Board";
+ compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+ memory at 80000000 {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ reg_usb_otg1_vbus: regulator-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator-otg2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_aud3v: regulator-aud3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-boot-on;
+ };
+
+ reg_aud4v: regulator-aud4v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcd>;
+ regulator-name = "lcd-pwr";
+ gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+ soc-supply = <&sw1c_reg>;
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pfuze100: pmic at 8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_sd1_vmmc>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usb_otg1_vbus: vbus1grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+ >;
+ };
+
+ pinctrl_usb_otg2_vbus: vbus2grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+ >;
+ };
+
+ pinctrl_reg_lcd: reglcdgrp {
+ fsl,pins = <
+ MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059
+ >;
+ };
+
+ pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
+ >;
+ };
+};
+
+
--
1.9.1
^ permalink raw reply related
* [RFC][PATCH] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Geert Uytterhoeven @ 2018-05-25 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <80b21f1b-8454-4ed0-b66d-03c298e1c87b@gmail.com>
Hi Marek,
On Fri, May 25, 2018 at 2:30 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> On 02/26/2018 11:39 AM, Geert Uytterhoeven wrote:
>> On Mon, Feb 26, 2018 at 11:17 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>> Rather than hard-coding the quirk topology, which stopped scaling,
>>> parse the information from DT. The code looks for all compatible
>>> PMICs -- da9036 and da9210 -- and checks if their IRQ line is tied
>>> to the same pin. If so, the code sends a matching sequence to the
>>> PMIC to deassert the IRQ.
>>>
>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>>
>> Thanks for your patch!
>>
>> At first sight, the probing part looks good to me. I'll have a closer look,
>> and will give it a try later.
>>
>> A few early comment below.
>>
>>> --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
>>> +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
>>
>>> @@ -88,17 +103,21 @@ static int regulator_quirk_notify(struct notifier_block *nb,
>>> client = to_i2c_client(dev);
>>> dev_dbg(dev, "Detected %s\n", client->name);
>>>
>>> - if ((client->addr == 0x58 && !strcmp(client->name, "da9063")) ||
>>> - (client->addr == 0x68 && !strcmp(client->name, "da9210")) ||
>>> - (client->addr == 0x70 && !strcmp(client->name, "da9210"))) {
>>> - int ret, len;
>>> + list_for_each_entry(pos, &quirk_list, list) {
>>> + if (pos->i2c_msg.addr != client->addr)
>>> + continue;
>>>
>>> - /* There are two DA9210 on Stout, one on the other boards. */
>>> - len = of_machine_is_compatible("renesas,stout") ? 3 : 2;
>>> + if (!of_device_is_compatible(dev->of_node, pos->id->compatible))
>>> + continue;
>>>
>>> - dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
>>> - ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
>>> - if (ret != ARRAY_SIZE(da9xxx_msgs))
>>> + if (!pos->shared)
>>> + continue;
>>> +
>>> + dev_info(&client->dev, "clearing %s at 0x%02x interrupts\n",
>>> + pos->id->compatible, pos->i2c_msg.addr);
>>> +
>>> + ret = i2c_transfer(client->adapter, &pos->i2c_msg, 1);
>>> + if (ret != 1)
>>> dev_err(&client->dev, "i2c error %d\n", ret);
>>> }
>>
>> The loop above sents a clear message to a single device only, right?
>> That won't work, as that will clear the interrupt for that single device only.
>> All other devices may still have their interrupts asserted.
>> Next step in probing will be binding the da9210 or da9063 driver, which will
>> enable the shared irq, and boom!
>>
>> Upon detecting the first affected device, you really have to send clear
>> messages to all devices in the list for which shared == true.
>
> This is even worse, the single-device part can be easily fixed. But what
> if the devices are on different i2c bus ? Do we care about that case or
> do we assume they are on the same bus (they are in the configurations we
> know of).
Until we have to support boards where the offenders are on different buses,
we can limit it to the same bus.
>>> @@ -122,7 +146,14 @@ static struct notifier_block regulator_quirk_nb = {
>>>
>>> static int __init rcar_gen2_regulator_quirk(void)
>>> {
>>> - u32 mon;
>>> + struct device_node *np;
>>> + const struct of_device_id *id;
>>> + struct regulator_quirk *quirk;
>>> + struct regulator_quirk *pos;
>>> + struct of_phandle_args *argsa, *argsb;
>>> + u32 mon, addr, i;
>>> + bool match;
>>> + int ret;
>>>
>>> if (!of_machine_is_compatible("renesas,koelsch") &&
>>> !of_machine_is_compatible("renesas,lager") &&
>>
>>> @@ -130,6 +161,51 @@ static int __init rcar_gen2_regulator_quirk(void)
>>> !of_machine_is_compatible("renesas,gose"))
>>> return -ENODEV;
>>
>> We might drop the checks above, to handle other platforms based on the
>> Renesas reference designs.
>
> Are you sure that's a good idea ?
Why not? Would it hurt?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] mmc: sdhci-*: Don't emit error msg if sdhci_add_host() fails
From: Jisheng Zhang @ 2018-05-25 7:15 UTC (permalink / raw)
To: linux-arm-kernel
I noticed below error msg with sdhci-pxav3 on some berlin platforms:
[.....] sdhci-pxav3 f7ab0000.sdhci failed to add host
It is due to getting related vmmc or vqmmc regulator returns
-EPROBE_DEFER. It doesn't matter at all but it's confusing.
>From another side, if driver probing fails and the error number isn't
-EPROBE_DEFER, the core will tell us something as below:
[.....] sdhci-pxav3: probe of f7ab0000.sdhci failed with error -EXX
So it's not necessary to emit error msg if sdhci_add_host() fails. And
some other sdhci host drivers also have this issue, let's fix them
together.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
drivers/mmc/host/sdhci-bcm-kona.c | 4 +---
drivers/mmc/host/sdhci-pic32.c | 4 +---
drivers/mmc/host/sdhci-pxav2.c | 4 +---
drivers/mmc/host/sdhci-pxav3.c | 4 +---
drivers/mmc/host/sdhci-s3c.c | 4 +---
drivers/mmc/host/sdhci-spear.c | 4 +---
drivers/mmc/host/sdhci-st.c | 4 +---
7 files changed, 7 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c
index 11ca95c60bcf..bdbd4897c0f7 100644
--- a/drivers/mmc/host/sdhci-bcm-kona.c
+++ b/drivers/mmc/host/sdhci-bcm-kona.c
@@ -284,10 +284,8 @@ static int sdhci_bcm_kona_probe(struct platform_device *pdev)
sdhci_bcm_kona_sd_init(host);
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(dev, "Failed sdhci_add_host\n");
+ if (ret)
goto err_reset;
- }
/* if device is eMMC, emulate card insert right here */
if (!mmc_card_is_removable(host->mmc)) {
diff --git a/drivers/mmc/host/sdhci-pic32.c b/drivers/mmc/host/sdhci-pic32.c
index a6caa49ca25a..a11e6397d4ff 100644
--- a/drivers/mmc/host/sdhci-pic32.c
+++ b/drivers/mmc/host/sdhci-pic32.c
@@ -200,10 +200,8 @@ static int pic32_sdhci_probe(struct platform_device *pdev)
}
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "error adding host\n");
+ if (ret)
goto err_base_clk;
- }
dev_info(&pdev->dev, "Successfully added sdhci host\n");
return 0;
diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
index 8986f9d9cf98..2c3827f54927 100644
--- a/drivers/mmc/host/sdhci-pxav2.c
+++ b/drivers/mmc/host/sdhci-pxav2.c
@@ -221,10 +221,8 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
host->ops = &pxav2_sdhci_ops;
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "failed to add host\n");
+ if (ret)
goto disable_clk;
- }
return 0;
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index a34434166ca7..b8e96f392428 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -472,10 +472,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
pm_suspend_ignore_children(&pdev->dev, 1);
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "failed to add host\n");
+ if (ret)
goto err_add_host;
- }
if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
device_init_wakeup(&pdev->dev, 1);
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index cda83ccb2702..9ef89d00970e 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -655,10 +655,8 @@ static int sdhci_s3c_probe(struct platform_device *pdev)
goto err_req_regs;
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(dev, "sdhci_add_host() failed\n");
+ if (ret)
goto err_req_regs;
- }
#ifdef CONFIG_PM
if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
diff --git a/drivers/mmc/host/sdhci-spear.c b/drivers/mmc/host/sdhci-spear.c
index 14511526a3a8..9247d51f2eed 100644
--- a/drivers/mmc/host/sdhci-spear.c
+++ b/drivers/mmc/host/sdhci-spear.c
@@ -126,10 +126,8 @@ static int sdhci_probe(struct platform_device *pdev)
}
ret = sdhci_add_host(host);
- if (ret) {
- dev_dbg(&pdev->dev, "error adding host\n");
+ if (ret)
goto disable_clk;
- }
platform_set_drvdata(pdev, host);
diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index c32daed0d418..8f95647195d9 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -422,10 +422,8 @@ static int sdhci_st_probe(struct platform_device *pdev)
st_mmcss_cconfig(np, host);
ret = sdhci_add_host(host);
- if (ret) {
- dev_err(&pdev->dev, "Failed sdhci_add_host\n");
+ if (ret)
goto err_out;
- }
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
--
2.17.0
^ permalink raw reply related
* [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: Jacky Bai @ 2018-05-25 6:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM0PR04MB4211C9CDBA0C3DBB510B36F380690@AM0PR04MB4211.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
> Hi Jacky,
>
> > -----Original Message-----
> > From: Jacky Bai
> > Sent: Friday, May 25, 2018 1:44 PM
> > To: A.s. Dong <aisheng.dong@nxp.com>; shawnguo at kernel.org;
> > robh+dt at kernel.org; kernel at pengutronix.de
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>;
> devicetree at vger.kernel.org;
> > linux-arm-kernel at lists.infradead.org; dl-linux-imx
> > <linux-imx@nxp.com>; jacky.baip at gmail.com
> > Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > imx6sll
> >
> > > Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > > imx6sll
> > >
> > > > -----Original Message-----
> > > > From: Jacky Bai
> > > > Sent: Monday, May 21, 2018 6:47 PM
> > > > To: shawnguo at kernel.org; robh+dt at kernel.org;
> kernel at pengutronix.de
> > > > Cc: Fabio Estevam <fabio.estevam@nxp.com>;
> > > devicetree at vger.kernel.org;
> > > > linux-arm-kernel at lists.infradead.org; dl-linux-imx
> > > > <linux-imx@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> > > > jacky.baip at gmail.com
> > > > Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > > > imx6sll
> > > >
> > >
> > > [...]
> > >
> > > [...]
> > >
> > > > +
> > > > + tempmon: temperature-sensor {
> > > > + compatible = "fsl,imx6sll-tempmon",
> > > > "fsl,imx6sx-tempmon";
> > > > + interrupts = <GIC_SPI 49
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + fsl,tempmon = <&anatop>;
> > > > + fsl,tempmon-data = <&ocotp>;
> > > > + clocks = <&clks
> > > > IMX6SLL_CLK_PLL3_USB_OTG>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > >
> > > Pls move it out of SoC node to root node.
> > > See:
> > > commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of
> > > bus")
> > >
> > Ok, will move it out.
> >
> > > And probably we need switch to the new way?
> > > See:
> > > commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor
> > > support")
> > >
> >
> > I prefer to keep it same as other imx6 soc.
> >
>
> Would you please check below patch?
> commit a6c856e9a8c ("ARM: dts: imx6sx: Use nvmem-cells for tempmon") If
> mx6sll has the same issue as mx6sx, then we may have to use nvmem-cells.
>
> If not, I'm ok with old way.
> And please make sure the OTP clk used is correct.
OK, I will switch to the new way.
BR
Jacky Bai
>
> Regards
> Dong Aisheng
>
> > BR
> > Jacky Bai
> > > Otherwise:
> > > Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
> > >
> > > Regards
> > > Dong Aisheng
> > >
> > > > + usbphy1: usb-phy at 20c9000 {
> > > > + compatible = "fsl,imx6sll-usbphy",
> > > > "fsl,imx6ul-usbphy",
> > > > + "fsl,imx23-usbphy";
> > > > + reg = <0x020c9000 0x1000>;
> > > > + interrupts = <GIC_SPI 40
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> > > > + phy-3p0-supply = <®_3p0>;
> > > > + fsl,anatop = <&anatop>;
> > > > + };
> > > > +
> > > > + usbphy2: usb-phy at 20ca000 {
> > > > + compatible = "fsl,imx6sll-usbphy",
> > > > "fsl,imx6ul-usbphy",
> > > > + "fsl,imx23-usbphy";
> > > > + reg = <0x020ca000 0x1000>;
> > > > + interrupts = <GIC_SPI 41
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> > > > + phy-reg_3p0-supply = <®_3p0>;
> > > > + fsl,anatop = <&anatop>;
> > > > + };
> > > > +
> > > > + snvs: snvs at 20cc000 {
> > > > + compatible = "fsl,sec-v4.0-mon", "syscon",
> > > > "simple-mfd";
> > > > + reg = <0x020cc000 0x4000>;
> > > > +
> > > > + snvs_rtc: snvs-rtc-lp {
> > > > + compatible = "fsl,sec-v4.0-mon-rtc-
> > > > lp";
> > > > + regmap = <&snvs>;
> > > > + offset = <0x34>;
> > > > + interrupts = <GIC_SPI 19
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 20
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + snvs_poweroff: snvs-poweroff {
> > > > + compatible = "syscon-poweroff";
> > > > + regmap = <&snvs>;
> > > > + offset = <0x38>;
> > > > + mask = <0x61>;
> > > > + };
> > > > +
> > > > + snvs_pwrkey: snvs-powerkey {
> > > > + compatible = "fsl,sec-v4.0-pwrkey";
> > > > + regmap = <&snvs>;
> > > > + interrupts = <GIC_SPI 4
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + linux,keycode = <KEY_POWER>;
> > > > + wakeup-source;
> > > > + };
> > > > + };
> > > > +
> > > > + src: reset-controller at 20d8000 {
> > > > + compatible = "fsl,imx6sll-src";
> > > > + reg = <0x020d8000 0x4000>;
> > > > + interrupts = <GIC_SPI 91
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 96
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + gpc: interrupt-controller at 20dc000 {
> > > > + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> > > > gpc";
> > > > + reg = <0x020dc000 0x4000>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <3>;
> > > > + interrupts = <GIC_SPI 89
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + interrupt-parent = <&intc>;
> > > > + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> > > > 0x0 0x1400640>;
> > > > + };
> > > > +
> > > > + iomuxc: pinctrl at 20e0000 {
> > > > + compatible = "fsl,imx6sll-iomuxc";
> > > > + reg = <0x020e0000 0x4000>;
> > > > + };
> > > > +
> > > > + gpr: iomuxc-gpr at 20e4000 {
> > > > + compatible = "fsl,imx6sll-iomuxc-gpr",
> > > > + "fsl,imx6q-iomuxc-gpr", "syscon";
> > > > + reg = <0x020e4000 0x4000>;
> > > > + };
> > > > +
> > > > + csi: csi at 20e8000 {
> > > > + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> > > > + reg = <0x020e8000 0x4000>;
> > > > + interrupts = <GIC_SPI 7
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> > > > + <&clks IMX6SLL_CLK_CSI>,
> > > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > > + clock-names = "disp-axi", "csi_mclk",
> > > > "disp_dcic";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + sdma: dma-controller at 20ec000 {
> > > > + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> > > > sdma";
> > > > + reg = <0x020ec000 0x4000>;
> > > > + interrupts = <GIC_SPI 2
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_SDMA>,
> > > > + <&clks IMX6SLL_CLK_SDMA>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + iram = <&ocram>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx6q.bin";
> > > > + };
> > > > +
> > > > + lcdif: lcd-controller at 20f8000 {
> > > > + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> > > > lcdif";
> > > > + reg = <0x020f8000 0x4000>;
> > > > + interrupts = <GIC_SPI 39
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> > > > + <&clks IMX6SLL_CLK_LCDIF_APB>,
> > > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > > + clock-names = "pix", "axi", "disp_axi";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + dcp: dcp at 20fc000 {
> > > > + compatible = "fsl,imx28-dcp";
> > > > + reg = <0x020fc000 0x4000>;
> > > > + interrupts = <GIC_SPI 99
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 100
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 101
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_DCP>;
> > > > + clock-names = "dcp";
> > > > + };
> > > > + };
> > > > +
> > > > + aips2: aips-bus at 2100000 {
> > > > + compatible = "fsl,aips-bus", "simple-bus";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + reg = <0x02100000 0x100000>;
> > > > + ranges;
> > > > +
> > > > + usbotg1: usb at 2184000 {
> > > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > > usb",
> > > > + "fsl,imx27-usb";
> > > > + reg = <0x02184000 0x200>;
> > > > + interrupts = <GIC_SPI 43
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > > + fsl,usbphy = <&usbphy1>;
> > > > + fsl,usbmisc = <&usbmisc 0>;
> > > > + fsl,anatop = <&anatop>;
> > > > + ahb-burst-config = <0x0>;
> > > > + tx-burst-size-dword = <0x10>;
> > > > + rx-burst-size-dword = <0x10>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usbotg2: usb at 2184200 {
> > > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > > usb",
> > > > + "fsl,imx27-usb";
> > > > + reg = <0x02184200 0x200>;
> > > > + interrupts = <GIC_SPI 42
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > > + fsl,usbphy = <&usbphy2>;
> > > > + fsl,usbmisc = <&usbmisc 1>;
> > > > + ahb-burst-config = <0x0>;
> > > > + tx-burst-size-dword = <0x10>;
> > > > + rx-burst-size-dword = <0x10>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usbmisc: usbmisc at 2184800 {
> > > > + #index-cells = <1>;
> > > > + compatible = "fsl,imx6sll-usbmisc",
> > > > "fsl,imx6ul-usbmisc",
> > > > + "fsl,imx6q-usbmisc";
> > > > + reg = <0x02184800 0x200>;
> > > > + };
> > > > +
> > > > + usdhc1: mmc at 2190000 {
> > > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > > usdhc";
> > > > + reg = <0x02190000 0x4000>;
> > > > + interrupts = <GIC_SPI 22
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> > > > + <&clks IMX6SLL_CLK_USDHC1>,
> > > > + <&clks IMX6SLL_CLK_USDHC1>;
> > > > + clock-names = "ipg", "ahb", "per";
> > > > + bus-width = <4>;
> > > > + fsl,tuning-step = <2>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc2: mmc at 2194000 {
> > > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > > usdhc";
> > > > + reg = <0x02194000 0x4000>;
> > > > + interrupts = <GIC_SPI 23
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> > > > + <&clks IMX6SLL_CLK_USDHC2>,
> > > > + <&clks IMX6SLL_CLK_USDHC2>;
> > > > + clock-names = "ipg", "ahb", "per";
> > > > + bus-width = <4>;
> > > > + fsl,tuning-step = <2>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc3: mmc at 2198000 {
> > > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > > usdhc";
> > > > + reg = <0x02198000 0x4000>;
> > > > + interrupts = <GIC_SPI 24
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> > > > + <&clks IMX6SLL_CLK_USDHC3>,
> > > > + <&clks IMX6SLL_CLK_USDHC3>;
> > > > + clock-names = "ipg", "ahb", "per";
> > > > + bus-width = <4>;
> > > > + fsl,tuning-step = <2>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c1: i2c at 21a0000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> > > > + reg = <0x021a0000 0x4000>;
> > > > + interrupts = <GIC_SPI 36
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_I2C1>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c2: i2c at 21a4000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > > + reg = <0x021a4000 0x4000>;
> > > > + interrupts = <GIC_SPI 37
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_I2C2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c3: i2c at 21a8000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > > + reg = <0x021a8000 0x4000>;
> > > > + interrupts = <GIC_SPI 38
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clks IMX6SLL_CLK_I2C3>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmdc: memory-controller at 21b0000 {
> > > > + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> > > > mmdc";
> > > > + reg = <0x021b0000 0x4000>;
> > > > + };
> > > > +
> > > > + ocotp: ocotp-ctrl at 21bc000 {
> > > > + compatible = "fsl,imx6sll-ocotp", "syscon";
> > > > + reg = <0x021bc000 0x4000>;
> > > > + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> > > > + };
> > > > +
> > > > + audmux: audmux at 21d8000 {
> > > > + compatible = "fsl,imx6sll-audmux",
> > > > "fsl,imx31-audmux";
> > > > + reg = <0x021d8000 0x4000>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart5: serial at 21f4000 {
> > > > + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> > > > uart",
> > > > + "fsl,imx21-uart";
> > > > + reg = <0x021f4000 0x4000>;
> > > > + interrupts =<GIC_SPI 30
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> > > > + dma-names = "rx", "tx";
> > > > + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> > > > + <&clks
> > > > IMX6SLL_CLK_UART5_SERIAL>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > + };
> > > > + };
> > > > +};
> > > > --
> > > > 1.9.1
^ permalink raw reply
* [PATCH v2 03/40] iommu/sva: Manage process address spaces
From: Ilias Apalodimas @ 2018-05-25 6:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <19e82a74-429a-3f86-119e-32b12082d0ff@arm.com>
On Thu, May 24, 2018 at 04:04:39PM +0100, Jean-Philippe Brucker wrote:
> On 24/05/18 12:50, Ilias Apalodimas wrote:
> >> Interesting, I hadn't thought about this use-case before. At first I
> >> thought you were talking about mdev devices assigned to VMs, but I think
> >> you're referring to mdevs assigned to userspace drivers instead? Out of
> >> curiosity, is it only theoretical or does someone actually need this?
> >
> > There has been some non upstreamed efforts to have mdev and produce userspace
> > drivers. Huawei is using it on what they call "wrapdrive" for crypto devices and
> > we did a proof of concept for ethernet interfaces. At the time we choose not to
> > involve the IOMMU for the reason you mentioned, but having it there would be
> > good.
>
> I'm guessing there were good reasons to do it that way but I wonder, is
> it not simpler to just have the kernel driver create a /dev/foo, with a
> standard ioctl/mmap/poll interface? Here VFIO adds a layer of
> indirection, and since the mediating driver has to implement these
> operations already, what is gained?
The best reason i can come up with is "common code". You already have one API
doing that for you so we replicate it in a /dev file?
The mdev approach still needs extentions to support what we tried to do (i.e
mdev bus might need yo have access on iommu_ops), but as far as i undestand it's
a possible case.
>
> Thanks,
> Jean
^ permalink raw reply
* [PATCH v8 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 72c5b4a3..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
aliases {
serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
};
chosen {
@@ -36,5 +37,58 @@
serial at 78b3000 {
status = "ok";
};
+
+ spi at 78b5000 {
+ status = "ok";
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ serial at 78b1000 {
+ status = "ok";
+ };
+
+ i2c at 78b6000 {
+ status = "ok";
+ };
+
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ nand at 79b0000 {
+ status = "ok";
+
+ nand at 0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
+ phy at 86000 {
+ status = "ok";
+ };
+
+ phy at 8e000 {
+ status = "ok";
+ };
+
+ pci at 20000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+ };
+
+ pci at 10000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+ };
};
};
--
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^ permalink raw reply related
* [PATCH v8 11/12] ARM: dts: ipq8074: Add pcie nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl at 1000000 {
+ tlmm: pinctrl at 1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+ pcie_phy0: phy at 86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci at 20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000f20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy at 8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci at 10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
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^ permalink raw reply related
* [PATCH v8 10/12] ARM: dts: ipq8074: Add peripheral nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 12 ---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +++++++++++++++++++++++++++++-
2 files changed, 155 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..72c5b4a3 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -33,19 +33,7 @@
};
soc {
- pinctrl at 1000000 {
- serial_4_pins: serial4_pinmux {
- mux {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- bias-disable;
- };
- };
- };
-
serial at 78b3000 {
- pinctrl-0 = <&serial_4_pins>;
- pinctrl-names = "default";
status = "ok";
};
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+ serial_4_pins: serial4-pinmux {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pins {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ hsuart_pins: hsuart-pins {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ qpic_pins: qpic-pins {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
intc: interrupt-controller at b000000 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ pinctrl-0 = <&serial_4_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp_dma: dma at 7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart1: serial at 78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart3: serial at 78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b1000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>,
+ <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&hsuart_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi at 78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c2: i2c at 78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+ dma-names = "rx", "tx";
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ blsp1_i2c3: i2c at 78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ qpic_bam: dma at 7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand at 79b0000 {
+ compatible = "qcom,ipq8074-nand";
+ reg = <0x79b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
status = "disabled";
};
};
@@ -175,7 +329,7 @@
pmu {
compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
--
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* [PATCH v8 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 0000000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+ compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+ soc {
+ pinctrl at 1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++++++++++++++++++++++
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+ compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+ soc {
+ pci at 40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ spi at 78b6000 {
+ status = "ok";
+ };
+
+ pinctrl at 1000000 {
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ spi at 78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ i2c at 78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Tested-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+ compatible = "qcom,ipq4019-dk04.1-c1";
+
+ soc {
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ spi at 78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pci at 40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ad61a55..7bcd763 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -323,7 +323,7 @@
dma-names = "rx", "tx";
};
- serial at 78b0000 {
+ blsp1_uart2: serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 03/12] ARM: dts: ipq4019: Change the max opp frequency
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 737097e..ad61a55 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -63,7 +63,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 02/12] ARM: dts: ipq4019: Add a few peripheral nodes
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
2 files changed, 146 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
- spi_0: spi at 78b5000 {
+ spi at 78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2efc8a2..737097e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,8 +40,10 @@
};
aliases {
- spi0 = &spi_0;
- i2c0 = &i2c_0;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
};
cpus {
@@ -120,6 +122,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -165,13 +173,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp_dma: dma at 7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -179,7 +187,7 @@
status = "disabled";
};
- spi_0: spi at 78b5000 {
+ blsp1_spi1: spi at 78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -188,10 +196,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ blsp1_spi2: spi at 78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- i2c_0: i2c at 78b7000 {
+ blsp1_i2c3: i2c at 78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -200,14 +224,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ blsp1_i2c4: i2c at 78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma at 8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
- interrupts = <GIC_SPI 207 0>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -275,7 +314,7 @@
blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- interrupts = <0 107 0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -287,7 +326,7 @@
serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
- interrupts = <0 108 0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -309,6 +348,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci at 40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma at 7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand at 79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand at 0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi at a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
@@ -342,7 +476,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 168 IRQ_TYPE_NONE>;
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
@@ -384,7 +518,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 169 IRQ_TYPE_NONE>;
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 01/12] ARM: dts: ipq4019: Add a default chosen node
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527228682-12285-1-git-send-email-sricharan@codeaurora.org>
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
soc {
rng at 22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index b25daf3..2efc8a2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -272,7 +272,7 @@
regulator;
};
- serial at 78af000 {
+ blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v8 00/12] ARM: dts: ipq: updates to enable a few peripherals
From: Sricharan R @ 2018-05-25 6:11 UTC (permalink / raw)
To: linux-arm-kernel
All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.
[V8]
* Rebased on top of Andy's for-next
[V7]
* Fixed Kbuild git bisectability issue
[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.
[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html
[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
that might break existing users whose u-boot do not
specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
the default serial console specified from DT.
[v3]
* Fixed minor comments from v2,
https://www.spinics.net/lists/arm-kernel/msg641480.html
* Added Abhishek's review tags
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4019: Add a default chosen node
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Enable few peripherals for hk01 board
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 10 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 +++++++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 ++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++++++++++--
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 313 +++++++++++++++++++++++-
11 files changed, 827 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: A.s. Dong @ 2018-05-25 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <HE1PR04MB3113D024D0BCCB6B96F0D8F687690@HE1PR04MB3113.eurprd04.prod.outlook.com>
Hi Jacky,
> -----Original Message-----
> From: Jacky Bai
> Sent: Friday, May 25, 2018 1:44 PM
> To: A.s. Dong <aisheng.dong@nxp.com>; shawnguo at kernel.org;
> robh+dt at kernel.org; kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> jacky.baip at gmail.com
> Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
> > Subject: RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > imx6sll
> >
> > > -----Original Message-----
> > > From: Jacky Bai
> > > Sent: Monday, May 21, 2018 6:47 PM
> > > To: shawnguo at kernel.org; robh+dt at kernel.org; kernel at pengutronix.de
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>;
> > devicetree at vger.kernel.org;
> > > linux-arm-kernel at lists.infradead.org; dl-linux-imx
> > > <linux-imx@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>;
> > > jacky.baip at gmail.com
> > > Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for
> > > imx6sll
> > >
> >
> > [...]
> >
> > [...]
> >
> > > +
> > > + tempmon: temperature-sensor {
> > > + compatible = "fsl,imx6sll-tempmon",
> > > "fsl,imx6sx-tempmon";
> > > + interrupts = <GIC_SPI 49
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + fsl,tempmon = <&anatop>;
> > > + fsl,tempmon-data = <&ocotp>;
> > > + clocks = <&clks
> > > IMX6SLL_CLK_PLL3_USB_OTG>;
> > > + status = "disabled";
> > > + };
> > > +
> >
> > Pls move it out of SoC node to root node.
> > See:
> > commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of bus")
> >
> Ok, will move it out.
>
> > And probably we need switch to the new way?
> > See:
> > commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor
> > support")
> >
>
> I prefer to keep it same as other imx6 soc.
>
Would you please check below patch?
commit a6c856e9a8c ("ARM: dts: imx6sx: Use nvmem-cells for tempmon")
If mx6sll has the same issue as mx6sx, then we may have to use nvmem-cells.
If not, I'm ok with old way.
And please make sure the OTP clk used is correct.
Regards
Dong Aisheng
> BR
> Jacky Bai
> > Otherwise:
> > Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
> >
> > Regards
> > Dong Aisheng
> >
> > > + usbphy1: usb-phy at 20c9000 {
> > > + compatible = "fsl,imx6sll-usbphy",
> > > "fsl,imx6ul-usbphy",
> > > + "fsl,imx23-usbphy";
> > > + reg = <0x020c9000 0x1000>;
> > > + interrupts = <GIC_SPI 40
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> > > + phy-3p0-supply = <®_3p0>;
> > > + fsl,anatop = <&anatop>;
> > > + };
> > > +
> > > + usbphy2: usb-phy at 20ca000 {
> > > + compatible = "fsl,imx6sll-usbphy",
> > > "fsl,imx6ul-usbphy",
> > > + "fsl,imx23-usbphy";
> > > + reg = <0x020ca000 0x1000>;
> > > + interrupts = <GIC_SPI 41
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> > > + phy-reg_3p0-supply = <®_3p0>;
> > > + fsl,anatop = <&anatop>;
> > > + };
> > > +
> > > + snvs: snvs at 20cc000 {
> > > + compatible = "fsl,sec-v4.0-mon", "syscon",
> > > "simple-mfd";
> > > + reg = <0x020cc000 0x4000>;
> > > +
> > > + snvs_rtc: snvs-rtc-lp {
> > > + compatible = "fsl,sec-v4.0-mon-rtc-
> > > lp";
> > > + regmap = <&snvs>;
> > > + offset = <0x34>;
> > > + interrupts = <GIC_SPI 19
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 20
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > + snvs_poweroff: snvs-poweroff {
> > > + compatible = "syscon-poweroff";
> > > + regmap = <&snvs>;
> > > + offset = <0x38>;
> > > + mask = <0x61>;
> > > + };
> > > +
> > > + snvs_pwrkey: snvs-powerkey {
> > > + compatible = "fsl,sec-v4.0-pwrkey";
> > > + regmap = <&snvs>;
> > > + interrupts = <GIC_SPI 4
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + linux,keycode = <KEY_POWER>;
> > > + wakeup-source;
> > > + };
> > > + };
> > > +
> > > + src: reset-controller at 20d8000 {
> > > + compatible = "fsl,imx6sll-src";
> > > + reg = <0x020d8000 0x4000>;
> > > + interrupts = <GIC_SPI 91
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 96
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + #reset-cells = <1>;
> > > + };
> > > +
> > > + gpc: interrupt-controller at 20dc000 {
> > > + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> > > gpc";
> > > + reg = <0x020dc000 0x4000>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + interrupts = <GIC_SPI 89
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-parent = <&intc>;
> > > + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> > > 0x0 0x1400640>;
> > > + };
> > > +
> > > + iomuxc: pinctrl at 20e0000 {
> > > + compatible = "fsl,imx6sll-iomuxc";
> > > + reg = <0x020e0000 0x4000>;
> > > + };
> > > +
> > > + gpr: iomuxc-gpr at 20e4000 {
> > > + compatible = "fsl,imx6sll-iomuxc-gpr",
> > > + "fsl,imx6q-iomuxc-gpr", "syscon";
> > > + reg = <0x020e4000 0x4000>;
> > > + };
> > > +
> > > + csi: csi at 20e8000 {
> > > + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> > > + reg = <0x020e8000 0x4000>;
> > > + interrupts = <GIC_SPI 7
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> > > + <&clks IMX6SLL_CLK_CSI>,
> > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > + clock-names = "disp-axi", "csi_mclk",
> > > "disp_dcic";
> > > + status = "disabled";
> > > + };
> > > +
> > > + sdma: dma-controller at 20ec000 {
> > > + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> > > sdma";
> > > + reg = <0x020ec000 0x4000>;
> > > + interrupts = <GIC_SPI 2
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_SDMA>,
> > > + <&clks IMX6SLL_CLK_SDMA>;
> > > + clock-names = "ipg", "ahb";
> > > + #dma-cells = <3>;
> > > + iram = <&ocram>;
> > > + fsl,sdma-ram-script-name =
> > > "imx/sdma/sdma-imx6q.bin";
> > > + };
> > > +
> > > + lcdif: lcd-controller at 20f8000 {
> > > + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> > > lcdif";
> > > + reg = <0x020f8000 0x4000>;
> > > + interrupts = <GIC_SPI 39
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> > > + <&clks IMX6SLL_CLK_LCDIF_APB>,
> > > + <&clks IMX6SLL_CLK_DUMMY>;
> > > + clock-names = "pix", "axi", "disp_axi";
> > > + status = "disabled";
> > > + };
> > > +
> > > + dcp: dcp at 20fc000 {
> > > + compatible = "fsl,imx28-dcp";
> > > + reg = <0x020fc000 0x4000>;
> > > + interrupts = <GIC_SPI 99
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 100
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 101
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_DCP>;
> > > + clock-names = "dcp";
> > > + };
> > > + };
> > > +
> > > + aips2: aips-bus at 2100000 {
> > > + compatible = "fsl,aips-bus", "simple-bus";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + reg = <0x02100000 0x100000>;
> > > + ranges;
> > > +
> > > + usbotg1: usb at 2184000 {
> > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > usb",
> > > + "fsl,imx27-usb";
> > > + reg = <0x02184000 0x200>;
> > > + interrupts = <GIC_SPI 43
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > + fsl,usbphy = <&usbphy1>;
> > > + fsl,usbmisc = <&usbmisc 0>;
> > > + fsl,anatop = <&anatop>;
> > > + ahb-burst-config = <0x0>;
> > > + tx-burst-size-dword = <0x10>;
> > > + rx-burst-size-dword = <0x10>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usbotg2: usb at 2184200 {
> > > + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> > > usb",
> > > + "fsl,imx27-usb";
> > > + reg = <0x02184200 0x200>;
> > > + interrupts = <GIC_SPI 42
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> > > + fsl,usbphy = <&usbphy2>;
> > > + fsl,usbmisc = <&usbmisc 1>;
> > > + ahb-burst-config = <0x0>;
> > > + tx-burst-size-dword = <0x10>;
> > > + rx-burst-size-dword = <0x10>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usbmisc: usbmisc at 2184800 {
> > > + #index-cells = <1>;
> > > + compatible = "fsl,imx6sll-usbmisc",
> > > "fsl,imx6ul-usbmisc",
> > > + "fsl,imx6q-usbmisc";
> > > + reg = <0x02184800 0x200>;
> > > + };
> > > +
> > > + usdhc1: mmc at 2190000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02190000 0x4000>;
> > > + interrupts = <GIC_SPI 22
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> > > + <&clks IMX6SLL_CLK_USDHC1>,
> > > + <&clks IMX6SLL_CLK_USDHC1>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc2: mmc at 2194000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02194000 0x4000>;
> > > + interrupts = <GIC_SPI 23
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> > > + <&clks IMX6SLL_CLK_USDHC2>,
> > > + <&clks IMX6SLL_CLK_USDHC2>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + usdhc3: mmc at 2198000 {
> > > + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> > > usdhc";
> > > + reg = <0x02198000 0x4000>;
> > > + interrupts = <GIC_SPI 24
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> > > + <&clks IMX6SLL_CLK_USDHC3>,
> > > + <&clks IMX6SLL_CLK_USDHC3>;
> > > + clock-names = "ipg", "ahb", "per";
> > > + bus-width = <4>;
> > > + fsl,tuning-step = <2>;
> > > + fsl,tuning-start-tap = <20>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c1: i2c at 21a0000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a0000 0x4000>;
> > > + interrupts = <GIC_SPI 36
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c2: i2c at 21a4000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a4000 0x4000>;
> > > + interrupts = <GIC_SPI 37
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C2>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + i2c3: i2c at 21a8000 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> > > + reg = <0x021a8000 0x4000>;
> > > + interrupts = <GIC_SPI 38
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clks IMX6SLL_CLK_I2C3>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + mmdc: memory-controller at 21b0000 {
> > > + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> > > mmdc";
> > > + reg = <0x021b0000 0x4000>;
> > > + };
> > > +
> > > + ocotp: ocotp-ctrl at 21bc000 {
> > > + compatible = "fsl,imx6sll-ocotp", "syscon";
> > > + reg = <0x021bc000 0x4000>;
> > > + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> > > + };
> > > +
> > > + audmux: audmux at 21d8000 {
> > > + compatible = "fsl,imx6sll-audmux",
> > > "fsl,imx31-audmux";
> > > + reg = <0x021d8000 0x4000>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + uart5: serial at 21f4000 {
> > > + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> > > uart",
> > > + "fsl,imx21-uart";
> > > + reg = <0x021f4000 0x4000>;
> > > + interrupts =<GIC_SPI 30
> > > IRQ_TYPE_LEVEL_HIGH>;
> > > + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> > > + dma-names = "rx", "tx";
> > > + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> > > + <&clks
> > > IMX6SLL_CLK_UART5_SERIAL>;
> > > + clock-names = "ipg", "per";
> > > + status = "disabled";
> > > + };
> > > + };
> > > + };
> > > +};
> > > --
> > > 1.9.1
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