* [PATCH v5 15/15] ARM: KVM: report support for SMCCC_ARCH_WORKAROUND_1
From: Marc Zyngier @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg24-0005CC-DF@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:55:28 +0100,
Russell King wrote:
>
> Report support for SMCCC_ARCH_WORKAROUND_1 to KVM guests for affected
> CPUs.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v3 5/5] ARM: dts: imx6qdl: add missing compatible and clock properties for EPIT
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add missing compatible and clock properties for EPIT node.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c003e62bf290..75bbaca34cbc 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -844,13 +844,23 @@
};
epit1: epit at 20d0000 { /* EPIT1 */
+ compatible = "fsl,imx6q-epit";
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ status = "disabled";
};
epit2: epit at 20d4000 { /* EPIT2 */
+ compatible = "fsl,imx6q-epit";
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT2>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ status = "disabled";
};
src: src at 20d8000 {
--
2.17.0
^ permalink raw reply related
* [PATCH v3 4/5] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add driver for NXP's EPIT timer used in i.MX 6 family of SoC.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
drivers/clocksource/Kconfig | 12 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 283 +++++++++++++++++++++++++++
3 files changed, 296 insertions(+)
create mode 100644 drivers/clocksource/timer-imx-epit.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10..920a0874f3a4 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -576,6 +576,18 @@ config H8300_TPU
This enables the clocksource for the H8300 platform with the
H8S2678 cpu.
+config CLKSRC_IMX_EPIT
+ bool "Clocksource using i.MX EPIT"
+ depends on ARM && CLKDEV_LOOKUP && OF && (ARCH_MXC || COMPILE_TEST)
+ select TIMER_OF
+ select CLKSRC_MMIO
+ help
+ This enables EPIT support available on some i.MX platforms.
+ Normally you don't have a reason to do so as the EPIT has
+ the same features and uses the same clocks as the GPT.
+ Anyway, on some systems the GPT may be in use for other
+ purposes.
+
config CLKSRC_IMX_GPT
bool "Clocksource using i.MX GPT" if COMPILE_TEST
depends on ARM && CLKDEV_LOOKUP
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 00caf37e52f9..d9426f69ec69 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
+obj-$(CONFIG_CLKSRC_IMX_EPIT) += timer-imx-epit.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
diff --git a/drivers/clocksource/timer-imx-epit.c b/drivers/clocksource/timer-imx-epit.c
new file mode 100644
index 000000000000..87025d5f3a97
--- /dev/null
+++ b/drivers/clocksource/timer-imx-epit.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
+ * Copyright (C) 2018 Cl?ment P?ron <clement.peron@devialet.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0c
+#define EPITCNR 0x10
+
+#define EPITCR_EN BIT(0)
+#define EPITCR_ENMOD BIT(1)
+#define EPITCR_OCIEN BIT(2)
+#define EPITCR_RLD BIT(3)
+#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
+#define EPITCR_SWR BIT(16)
+#define EPITCR_IOVW BIT(17)
+#define EPITCR_DBGEN BIT(18)
+#define EPITCR_WAITEN BIT(19)
+#define EPITCR_RES BIT(20)
+#define EPITCR_STOPEN BIT(21)
+#define EPITCR_OM_DISCON (0 << 22)
+#define EPITCR_OM_TOGGLE (1 << 22)
+#define EPITCR_OM_CLEAR (2 << 22)
+#define EPITCR_OM_SET (3 << 22)
+#define EPITCR_CLKSRC_OFF (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
+#define EPITCR_CLKSRC_REF_LOW (3 << 24)
+
+#define EPITSR_OCIF BIT(0)
+
+struct epit_timer {
+ void __iomem *base;
+ int irq;
+ struct clk *clk_per;
+ struct clock_event_device ced;
+ struct irqaction act;
+};
+
+static void __iomem *sched_clock_reg;
+
+static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
+{
+ return container_of(ced, struct epit_timer, ced);
+}
+
+static inline void epit_irq_disable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static inline void epit_irq_enable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static void epit_irq_acknowledge(struct epit_timer *epittm)
+{
+ writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
+}
+
+static u64 notrace epit_read_sched_clock(void)
+{
+ return ~readl_relaxed(sched_clock_reg);
+}
+
+static int __init epit_clocksource_init(struct epit_timer *epittm)
+{
+ unsigned int c = clk_get_rate(epittm->clk_per);
+
+ sched_clock_reg = epittm->base + EPITCNR;
+ sched_clock_register(epit_read_sched_clock, 32, c);
+
+ return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
+ clocksource_mmio_readl_down);
+}
+
+static int epit_set_next_event(unsigned long cycles,
+ struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long tcmp;
+
+ tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
+ writel_relaxed(tcmp, epittm->base + EPITCMPR);
+
+ return 0;
+}
+
+/* Left event sources disabled, no more interrupts appear */
+static int epit_shutdown(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt */
+ epit_irq_acknowledge(epittm);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int epit_set_oneshot(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt, only while switching mode */
+ if (!clockevent_state_oneshot(ced))
+ epit_irq_acknowledge(epittm);
+
+ /*
+ * Do not put overhead of interrupt enable/disable into
+ * epit_set_next_event(), the core has about 4 minutes
+ * to call epit_set_next_event() or shutdown clock after
+ * mode switching
+ */
+ epit_irq_enable(epittm);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ced = dev_id;
+ struct epit_timer *epittm = to_epit_timer(ced);
+
+ epit_irq_acknowledge(epittm);
+
+ ced->event_handler(ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init epit_clockevent_init(struct epit_timer *epittm)
+{
+ struct clock_event_device *ced = &epittm->ced;
+ struct irqaction *act = &epittm->act;
+
+ ced->name = "epit";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
+ ced->set_state_shutdown = epit_shutdown;
+ ced->tick_resume = epit_shutdown;
+ ced->set_state_oneshot = epit_set_oneshot;
+ ced->set_next_event = epit_set_next_event;
+ ced->rating = 200;
+ ced->cpumask = cpumask_of(0);
+ ced->irq = epittm->irq;
+ clockevents_config_and_register(ced, clk_get_rate(epittm->clk_per),
+ 0xff, 0xfffffffe);
+
+ act->name = "i.MX EPIT Timer Tick",
+ act->flags = IRQF_TIMER | IRQF_IRQPOLL;
+ act->handler = epit_timer_interrupt;
+ act->dev_id = ced;
+
+ /* Make irqs happen */
+ return setup_irq(epittm->irq, act);
+}
+
+static int __init epit_timer_init(struct device_node *np)
+{
+ struct epit_timer *epittm;
+ struct clk *clk_ipg;
+ int ret;
+
+ epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
+ if (!epittm)
+ return -ENOMEM;
+
+ epittm->base = of_iomap(np, 0);
+ if (!epittm->base) {
+ ret = -ENXIO;
+ goto out_kfree;
+ }
+
+ epittm->irq = irq_of_parse_and_map(np, 0);
+ if (!epittm->irq) {
+ ret = -EINVAL;
+ goto out_iounmap;
+ }
+
+ clk_ipg = of_clk_get_by_name(np, "ipg");
+ if (IS_ERR(clk_ipg)) {
+ pr_err("i.MX EPIT: unable to get clk_ipg\n");
+ ret = PTR_ERR(clk_ipg);
+ goto out_iounmap;
+ }
+
+ ret = clk_prepare_enable(clk_ipg);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk_ipg\n");
+ goto out_clk_ipg_disable;
+ }
+
+ epittm->clk_per = of_clk_get_by_name(np, "per");
+ if (IS_ERR(epittm->clk_per)) {
+ pr_err("i.MX EPIT: unable to get clk_per\n");
+ ret = PTR_ERR(epittm->clk_per);
+ goto out_clk_ipg_disable;
+ }
+
+ ret = clk_prepare_enable(epittm->clk_per);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk_per\n");
+ goto out_clk_ipg_disable;
+ }
+
+ /* Initialise to a known state (all timers off, and timing reset) */
+ writel_relaxed(0x0, epittm->base + EPITCR);
+ writel_relaxed(0xffffffff, epittm->base + EPITLR);
+ writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+ epittm->base + EPITCR);
+
+ ret = epit_clocksource_init(epittm);
+ if(ret) {
+ pr_err("i.MX EPIT: failed to init clocksource\n");
+ goto out_clk_per_disable;
+ }
+
+ ret = epit_clockevent_init(epittm);
+ if(ret) {
+ pr_err("i.MX EPIT: failed to init clockevent\n");
+ goto out_clk_per_disable;
+ }
+
+ return 0;
+
+out_clk_per_disable:
+ clk_disable_unprepare(epittm->clk_per);
+out_clk_ipg_disable:
+ clk_disable_unprepare(clk_ipg);
+out_iounmap:
+ iounmap(epittm->base);
+out_kfree:
+ kfree(epittm);
+
+ return ret;
+}
+TIMER_OF_DECLARE(mx6q_timer, "fsl,imx6q-epit", epit_timer_init);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 3/5] Documentation: DT: add i.MX EPIT timer binding
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
Add devicetree binding document for NXP's i.MX SoC specific
EPIT timer driver.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
.../devicetree/bindings/clock/imx6q,epit.txt | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
diff --git a/Documentation/devicetree/bindings/clock/imx6q,epit.txt b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
new file mode 100644
index 000000000000..a84a60c6ae35
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
@@ -0,0 +1,24 @@
+Binding for the i.MX6 EPIT timer
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "fsl,imx6q-epit"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Should contain EPIT controller interrupt
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names : should include entries "ipg", "per"
+
+Example:
+ epit1: epit at 20d0000 {
+ compatible = "fsl,imx6q-epit";
+ reg = <0x020d0000 0x4000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>,
+ <&clks IMX6QDL_CLK_IPG_PER>;
+ clock-names = "ipg", "per";
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/5] clk: imx6: add EPIT clock support
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add EPIT clock support to the i.MX6Q clocking infrastructure.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/clk/imx/clk-imx6q.c | 2 ++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 8d518ad5dc13..b9ea7037e193 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -753,6 +753,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
else
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
+ clk[IMX6QDL_CLK_EPIT1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
+ clk[IMX6QDL_CLK_EPIT2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9cdb5e..7ad171b8f3bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_END 261
+#define IMX6QDL_CLK_EPIT1 261
+#define IMX6QDL_CLK_EPIT2 262
+#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.17.0
^ permalink raw reply related
* [PATCH v3 1/5] ARM: imx: remove inexistant EPIT timer init
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529170436.22711-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
i.MX EPIT timer has been removed but not the init function declaration.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c8d68e918b2f..18aae76fa2da 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -38,7 +38,6 @@ void imx21_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
-void epit_timer_init(void __iomem *base, int irq);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 0/5] Reintroduce i.MX EPIT Timer
From: Clément Péron @ 2018-05-29 17:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Cl?ment Peron <clement.peron@devialet.com>
As suggested in the commit message we have added the device tree support,
proper bindings and we moved the driver into the correct folder.
Moreover we made some changes like use of relaxed IO accesor,
implement sched_clock, delay_timer and reduce the clockevents min_delta.
Changes since v2 (Thanks Fabio Estevam):
- Removed unused "ckil" clock
- Add out_iounmap
- Check and handle if clk_prepare_enable failed
- Fix comment typo
Changes since v1 (Thanks Vladimir Zapolskiy):
- Add OF dependency in Kconfig
- Sort header
- Use BIT macro
- Remove useless comments
- Fix incorrect indent
- Fix memory leak
- Add check and handle possible returned error
Cl?ment Peron (2):
ARM: imx: remove inexistant EPIT timer init
Documentation: DT: add i.MX EPIT timer binding
Colin Didier (3):
clk: imx6: add EPIT clock support
clocksource: add driver for i.MX EPIT timer
ARM: dts: imx6qdl: add missing compatible and clock properties for
EPIT
.../devicetree/bindings/clock/imx6q,epit.txt | 24 ++
arch/arm/boot/dts/imx6qdl.dtsi | 10 +
arch/arm/mach-imx/common.h | 1 -
drivers/clk/imx/clk-imx6q.c | 2 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 283 ++++++++++++++++++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +-
8 files changed, 335 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
create mode 100644 drivers/clocksource/timer-imx-epit.c
--
2.17.0
^ permalink raw reply
* [PATCH v5 14/15] ARM: KVM: Add SMCCC_ARCH_WORKAROUND_1 fast handling
From: Marc Zyngier @ 2018-05-29 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1z-0005C1-92@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:55:23 +0100,
Russell King wrote:
>
> We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
> So let's intercept it as early as we can by testing for the
> function call number as soon as we've identified a HVC call
> coming from the guest.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 13/15] ARM: spectre-v2: KVM: invalidate icache on guest exit for Brahma B15
From: Marc Zyngier @ 2018-05-29 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1u-0005BA-3z@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:55:18 +0100,
Russell King wrote:
>
> Include Brahma B15 in the Spectre v2 KVM workarounds.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 10/15] ARM: spectre-v2: warn about incorrect context switching functions
From: Marc Zyngier @ 2018-05-29 17:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1d-00059d-NR@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:55:01 +0100,
Russell King wrote:
>
> Warn at error level if the context switching function is not what we
> are expecting. This can happen with big.Little systems, which we
> currently do not support.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
I assume this is a temporary situation until the ARM port grows the
necessary infrastructure to support this mitigation on heterogeneous
systems. With that in mind:
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 09/15] ARM: spectre-v2: add firmware based hardening
From: Marc Zyngier @ 2018-05-29 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1Y-00057y-FP@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:56 +0100,
Russell King wrote:
>
> Add firmware based hardening for cores that require more complex
> handling in firmware.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
> ---
> arch/arm/mm/proc-v7-bugs.c | 64 +++++++++++++++++++++++++++++++++++++++++++++-
> arch/arm/mm/proc-v7.S | 21 +++++++++++++++
> 2 files changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
> index 3a03b3824eb0..9e2ae201138b 100644
> --- a/arch/arm/mm/proc-v7-bugs.c
> +++ b/arch/arm/mm/proc-v7-bugs.c
> @@ -1,14 +1,20 @@
> // SPDX-License-Identifier: GPL-2.0
> +#include <linux/arm-smccc.h>
> #include <linux/kernel.h>
> +#include <linux/psci.h>
> #include <linux/smp.h>
>
> #include <asm/cp15.h>
> #include <asm/cputype.h>
> +#include <asm/proc-fns.h>
> #include <asm/system_misc.h>
>
> #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
> DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
>
> +extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> +extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> +
> static void harden_branch_predictor_bpiall(void)
> {
> write_sysreg(0, BPIALL);
> @@ -19,15 +25,27 @@ static void harden_branch_predictor_iciallu(void)
> write_sysreg(0, ICIALLU);
> }
>
> +static void __maybe_unused call_smc_arch_workaround_1(void)
> +{
> + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> +}
> +
> +static void __maybe_unused call_hvc_arch_workaround_1(void)
> +{
> + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> +}
> +
> static void cpu_v7_spectre_init(void)
> {
> const char *spectre_v2_method = NULL;
> int cpu = smp_processor_id();
> + u32 cpuid;
>
> if (per_cpu(harden_branch_predictor_fn, cpu))
> return;
>
> - switch (read_cpuid_part()) {
> + cpuid = read_cpuid_part();
> + switch (cpuid) {
> case ARM_CPU_PART_CORTEX_A8:
> case ARM_CPU_PART_CORTEX_A9:
> case ARM_CPU_PART_CORTEX_A12:
> @@ -45,7 +63,51 @@ static void cpu_v7_spectre_init(void)
> harden_branch_predictor_iciallu;
> spectre_v2_method = "ICIALLU";
> break;
> +
> +#ifdef CONFIG_ARM_PSCI
> + default:
> + /* Other ARM CPUs require no workaround */
> + if (cpuid >> 24 == ARM_CPU_IMP_ARM)
nit: this would probably look slightly less arcane as
(read_cpuid_implementor() == ARM_CPU_IMP_ARM).
> + break;
> + /* fallthrough */
> + /* Cortex A57/A72 require firmware workaround */
> + case ARM_CPU_PART_CORTEX_A57:
> + case ARM_CPU_PART_CORTEX_A72: {
> + struct arm_smccc_res res;
> +
> + if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
> + break;
> +
> + switch (psci_ops.conduit) {
> + case PSCI_CONDUIT_HVC:
> + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> + if ((int)res.a0 != 0)
> + break;
> + per_cpu(harden_branch_predictor_fn, cpu) =
> + call_hvc_arch_workaround_1;
> + processor.switch_mm = cpu_v7_hvc_switch_mm;
> + spectre_v2_method = "hypervisor";
> + break;
> +
> + case PSCI_CONDUIT_SMC:
> + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> + if ((int)res.a0 != 0)
> + break;
> + per_cpu(harden_branch_predictor_fn, cpu) =
> + call_smc_arch_workaround_1;
> + processor.switch_mm = cpu_v7_smc_switch_mm;
> + spectre_v2_method = "firmware";
> + break;
> +
> + default:
> + break;
> + }
> }
> +#endif
> + }
> +
> if (spectre_v2_method)
> pr_info("CPU%u: Spectre v2: using %s workaround\n",
> smp_processor_id(), spectre_v2_method);
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 79510011e7eb..b78d59a1cc05 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -9,6 +9,7 @@
> *
> * This is the "shell" of the ARMv7 processor support.
> */
> +#include <linux/arm-smccc.h>
> #include <linux/init.h>
> #include <linux/linkage.h>
> #include <asm/assembler.h>
> @@ -93,6 +94,26 @@ ENTRY(cpu_v7_dcache_clean_area)
> ret lr
> ENDPROC(cpu_v7_dcache_clean_area)
>
> +#ifdef CONFIG_ARM_PSCI
> + .arch_extension sec
> +ENTRY(cpu_v7_smc_switch_mm)
> + stmfd sp!, {r0 - r3}
> + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
> + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
> + smc #0
> + ldmfd sp!, {r0 - r3}
> + b cpu_v7_switch_mm
> +ENDPROC(cpu_v7_smc_switch_mm)
> + .arch_extension virt
> +ENTRY(cpu_v7_hvc_switch_mm)
> + stmfd sp!, {r0 - r3}
> + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
> + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
> + hvc #0
> + ldmfd sp!, {r0 - r3}
> + b cpu_v7_switch_mm
> +ENDPROC(cpu_v7_smc_switch_mm)
> +#endif
> ENTRY(cpu_v7_iciallu_switch_mm)
> mov r3, #0
> mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
> --
> 2.7.4
>
Otherwise:
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 06/15] ARM: spectre-v2: harden branch predictor on context switches
From: Marc Zyngier @ 2018-05-29 16:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1H-00055Y-W1@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:39 +0100,
Russell King wrote:
>
> Harden the branch predictor against Spectre v2 attacks on context
> switches for ARMv7 and later CPUs. We do this by:
>
> Cortex A9, A12, A17, A73, A75: invalidating the BTB.
> Cortex A15, Brahma B15: invalidating the instruction cache.
>
> Cortex A57 and Cortex A72 are not addressed in this patch.
>
> Cortex R7 and Cortex R8 are also not addressed as we do not enforce
> memory protection on these cores.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 05/15] ARM: spectre: add Kconfig symbol for CPUs vulnerable to Spectre
From: Marc Zyngier @ 2018-05-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg1C-00055N-E1@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:34 +0100,
Russell King wrote:
>
> Add a Kconfig symbol for CPUs which are vulnerable to the Spectre
> attacks.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 04/15] ARM: bugs: add support for per-processor bug checking
From: Marc Zyngier @ 2018-05-29 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg17-00055G-7W@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:29 +0100,
Russell King wrote:
>
> Add support for per-processor bug checking - each processor function
> descriptor gains a function pointer for this check, which must not be
> an __init function. If non-NULL, this will be called whenever a CPU
> enters the kernel via which ever path (boot CPU, secondary CPU startup,
> CPU resuming, etc.)
>
> This allows processor specific bug checks to validate that workaround
> bits are properly enabled by firmware via all entry paths to the kernel.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 03/15] ARM: bugs: hook processor bug checking into SMP and suspend paths
From: Marc Zyngier @ 2018-05-29 16:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg12-000557-3p@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:24 +0100,
Russell King wrote:
>
> Check for CPU bugs when secondary processors are being brought online,
> and also when CPUs are resuming from a low power mode. This gives an
> opportunity to check that processor specific bug workarounds are
> correctly enabled for all paths that a CPU re-enters the kernel.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 02/15] ARM: bugs: prepare processor bug infrastructure
From: Marc Zyngier @ 2018-05-29 16:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg0w-00054e-W3@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:18 +0100,
Russell King wrote:
>
> Prepare the processor bug infrastructure so that it can be expanded to
> check for per-processor bugs.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH v5 01/15] ARM: add more CPU part numbers for Cortex and Brahma B15 CPUs
From: Marc Zyngier @ 2018-05-29 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fNg0r-00054X-MC@rmk-PC.armlinux.org.uk>
On Tue, 29 May 2018 15:54:13 +0100,
Russell King wrote:
>
> Add CPU part numbers for Cortex A53, A57, A72, A73, A75 and the
> Broadcom Brahma B15 CPU.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> Boot-tested-by: Tony Lindgren <tony@atomide.com>
> Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead, it just smell funny.
^ permalink raw reply
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
From: Geert Uytterhoeven @ 2018-05-29 16:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529130504.lpkpgads7lfomois@verge.net.au>
Hi Simon,
On Tue, May 29, 2018 at 3:05 PM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, May 28, 2018 at 11:13:08PM +0300, Sergei Shtylyov wrote:
>> Define the generic R8A77980 parts of the I2C[0-5] device node.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> + i2c3: i2c at e66d0000 {
>> + compatible = "renesas,i2c-r8a77980",
>> + "renesas,rcar-gen3-i2c";
>> + reg = <0 0xe66d0000 0 0x40>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 928>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 928>;
>> + dmas = <&dmac1 0x97>, <&dmac1 0x96>,
>> + <&dmac2 0x97>, <&dmac2 0x96>;
>> + dma-names = "tx", "rx", "tx", "rx";
>> + i2c-scl-internal-delay-ns = <6>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>
> DMA for i2c3 and i2c4 seems unclear in v0.80 and v1.00 of the User's Manual.
> Although what is described here does match v0.55E of the User's Manual.
> Have you been able to confirm what is correct here?
Given they bothered adding rows to the table, I assume they just forgot to
add checkmarks in the V3H column.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add I2C support
From: Geert Uytterhoeven @ 2018-05-29 16:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3675b19f-b800-172f-9472-c47a37760fa9@cogentembedded.com>
On Mon, May 28, 2018 at 10:13 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 parts of the I2C[0-5] device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] kvm: no need to check return value of debugfs_create functions
From: Greg Kroah-Hartman @ 2018-05-29 16:22 UTC (permalink / raw)
To: linux-arm-kernel
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
This cleans up the error handling a lot, as this code will never get
hit.
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Kr?m??" <rkrcmar@redhat.com>
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Cc: Eric Auger <eric.auger@redhat.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: kvm-ppc at vger.kernel.org
Cc: linuxppc-dev at lists.ozlabs.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: kvmarm at lists.cs.columbia.edu
Cc: kvm at vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/kvm/book3s_hv.c | 3 +--
virt/kvm/arm/vgic/vgic-debug.c | 17 ++++-----------
virt/kvm/arm/vgic/vgic.h | 4 ++--
virt/kvm/kvm_main.c | 40 +++++++---------------------------
4 files changed, 15 insertions(+), 49 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 4d07fca5121c..67d7de1470cc 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3950,8 +3950,7 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
*/
snprintf(buf, sizeof(buf), "vm%d", current->pid);
kvm->arch.debugfs_dir = debugfs_create_dir(buf, kvm_debugfs_dir);
- if (!IS_ERR_OR_NULL(kvm->arch.debugfs_dir))
- kvmppc_mmu_debugfs_init(kvm);
+ kvmppc_mmu_debugfs_init(kvm);
return 0;
}
diff --git a/virt/kvm/arm/vgic/vgic-debug.c b/virt/kvm/arm/vgic/vgic-debug.c
index 10b38178cff2..0140b29079b6 100644
--- a/virt/kvm/arm/vgic/vgic-debug.c
+++ b/virt/kvm/arm/vgic/vgic-debug.c
@@ -263,21 +263,12 @@ static const struct file_operations vgic_debug_fops = {
.release = seq_release
};
-int vgic_debug_init(struct kvm *kvm)
+void vgic_debug_init(struct kvm *kvm)
{
- if (!kvm->debugfs_dentry)
- return -ENOENT;
-
- if (!debugfs_create_file("vgic-state", 0444,
- kvm->debugfs_dentry,
- kvm,
- &vgic_debug_fops))
- return -ENOMEM;
-
- return 0;
+ debugfs_create_file("vgic-state", 0444, kvm->debugfs_dentry, kvm,
+ &vgic_debug_fops);
}
-int vgic_debug_destroy(struct kvm *kvm)
+void vgic_debug_destroy(struct kvm *kvm)
{
- return 0;
}
diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
index 830e815748a0..3c38c5349953 100644
--- a/virt/kvm/arm/vgic/vgic.h
+++ b/virt/kvm/arm/vgic/vgic.h
@@ -229,8 +229,8 @@ void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
int vgic_lazy_init(struct kvm *kvm);
int vgic_init(struct kvm *kvm);
-int vgic_debug_init(struct kvm *kvm);
-int vgic_debug_destroy(struct kvm *kvm);
+void vgic_debug_init(struct kvm *kvm);
+void vgic_debug_destroy(struct kvm *kvm);
bool lock_all_vcpus(struct kvm *kvm);
void unlock_all_vcpus(struct kvm *kvm);
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index c7b2e927f699..0ad400f353fc 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -572,10 +572,7 @@ static int kvm_create_vm_debugfs(struct kvm *kvm, int fd)
return 0;
snprintf(dir_name, sizeof(dir_name), "%d-%d", task_pid_nr(current), fd);
- kvm->debugfs_dentry = debugfs_create_dir(dir_name,
- kvm_debugfs_dir);
- if (!kvm->debugfs_dentry)
- return -ENOMEM;
+ kvm->debugfs_dentry = debugfs_create_dir(dir_name, kvm_debugfs_dir);
kvm->debugfs_stat_data = kcalloc(kvm_debugfs_num_entries,
sizeof(*kvm->debugfs_stat_data),
@@ -591,11 +588,8 @@ static int kvm_create_vm_debugfs(struct kvm *kvm, int fd)
stat_data->kvm = kvm;
stat_data->offset = p->offset;
kvm->debugfs_stat_data[p - debugfs_entries] = stat_data;
- if (!debugfs_create_file(p->name, 0644,
- kvm->debugfs_dentry,
- stat_data,
- stat_fops_per_vm[p->kind]))
- return -ENOMEM;
+ debugfs_create_file(p->name, 0644, kvm->debugfs_dentry,
+ stat_data, stat_fops_per_vm[p->kind]);
}
return 0;
}
@@ -3896,29 +3890,18 @@ static void kvm_uevent_notify_change(unsigned int type, struct kvm *kvm)
kfree(env);
}
-static int kvm_init_debug(void)
+static void kvm_init_debug(void)
{
- int r = -EEXIST;
struct kvm_stats_debugfs_item *p;
kvm_debugfs_dir = debugfs_create_dir("kvm", NULL);
- if (kvm_debugfs_dir == NULL)
- goto out;
kvm_debugfs_num_entries = 0;
for (p = debugfs_entries; p->name; ++p, kvm_debugfs_num_entries++) {
- if (!debugfs_create_file(p->name, 0644, kvm_debugfs_dir,
- (void *)(long)p->offset,
- stat_fops[p->kind]))
- goto out_dir;
+ debugfs_create_file(p->name, 0644, kvm_debugfs_dir,
+ (void *)(long)p->offset,
+ stat_fops[p->kind]);
}
-
- return 0;
-
-out_dir:
- debugfs_remove_recursive(kvm_debugfs_dir);
-out:
- return r;
}
static int kvm_suspend(void)
@@ -4046,20 +4029,13 @@ int kvm_init(void *opaque, unsigned vcpu_size, unsigned vcpu_align,
kvm_preempt_ops.sched_in = kvm_sched_in;
kvm_preempt_ops.sched_out = kvm_sched_out;
- r = kvm_init_debug();
- if (r) {
- pr_err("kvm: create debugfs files failed\n");
- goto out_undebugfs;
- }
+ kvm_init_debug();
r = kvm_vfio_ops_init();
WARN_ON(r);
return 0;
-out_undebugfs:
- unregister_syscore_ops(&kvm_syscore_ops);
- misc_deregister(&kvm_dev);
out_unreg:
kvm_async_pf_deinit();
out_free:
--
2.17.0
^ permalink raw reply related
* [PATCH v2 5/5] arm64: dts: renesas: r8a7795: add ccree binding
From: Simon Horman @ 2018-05-29 16:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527171551-21979-6-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:10PM +0100, Gilad Ben-Yossef wrote:
> Add bindings for CryptoCell instance in the SoC.
>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
In so far as I can review the details of this (which is not much) this
looks fine to me. I am, however, a little unclear in when it should be
accepted.
> ---
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index d842940..3ac75db 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -528,6 +528,15 @@
> status = "disabled";
> };
>
> + arm_cc630p: crypto at e6601000 {
> + compatible = "arm,cryptocell-630p-ree";
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0xe6601000 0 0x1000>;
> + clocks = <&cpg CPG_MOD 229>;
> + resets = <&cpg 229>;
> + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> + };
> +
> i2c3: i2c at e66d0000 {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v2 3/5] crypto: ccree: silence debug prints
From: Simon Horman @ 2018-05-29 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527171551-21979-4-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:08PM +0100, Gilad Ben-Yossef wrote:
> The cache parameter register configuration was being too verbose.
> Use dev_dbg() to only provide the information if needed.
>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* [PATCH v2 2/5] crypto: ccree: better clock handling
From: Simon Horman @ 2018-05-29 16:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527171551-21979-3-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:07PM +0100, Gilad Ben-Yossef wrote:
> Use managed clock handling, differentiate between no clock (possibly OK)
> and clock init failure (never OK) and correctly handle clock detection
> being deferred.
>
> Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/crypto/ccree/cc_driver.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
> index 6f93ce7..b266657 100644
> --- a/drivers/crypto/ccree/cc_driver.c
> +++ b/drivers/crypto/ccree/cc_driver.c
> @@ -190,6 +190,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
> u64 dma_mask;
> const struct cc_hw_data *hw_rev;
> const struct of_device_id *dev_id;
> + struct clk *clk;
> int rc = 0;
>
> new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
> @@ -219,7 +220,24 @@ static int init_cc_resources(struct platform_device *plat_dev)
> platform_set_drvdata(plat_dev, new_drvdata);
> new_drvdata->plat_dev = plat_dev;
>
> - new_drvdata->clk = of_clk_get(np, 0);
> + clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(clk))
> + switch (PTR_ERR(clk)) {
> + /* Clock is optional so this might be fine */
> + case -ENOENT:
> + break;
> +
> + /* Clock not available, let's try again soon */
> + case -EPROBE_DEFER:
> + return -EPROBE_DEFER;
> +
> + default:
> + dev_err(dev, "Error getting clock: %ld\n",
> + PTR_ERR(clk));
> + return PTR_ERR(clk);
> + }
> + new_drvdata->clk = clk;
> +
> new_drvdata->coherent = of_dma_is_coherent(np);
>
> /* Get device resources */
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v2 1/5] crypto: ccree: correct host regs offset
From: Simon Horman @ 2018-05-29 16:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527171551-21979-2-git-send-email-gilad@benyossef.com>
On Thu, May 24, 2018 at 03:19:06PM +0100, Gilad Ben-Yossef wrote:
> The product signature and HW revision register have different offset on the
> older HW revisions.
> This fixes the problem of the driver failing sanity check on silicon
> despite working on the FPGA emulation systems.
>
> Fixes: 27b3b22dd98c ("crypto: ccree - add support for older HW revs")
Did the above introduce a regression that is fixed by this patch
or did it add a feature that only works with this patch?
In the case of the latter I would drop the Fixes tag,
but I don't feel strongly about it.
> Cc: stable at vger.kernel.org
> Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Minor not below not withstanding,
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/crypto/ccree/cc_debugfs.c | 7 +++++--
> drivers/crypto/ccree/cc_driver.c | 8 ++++++--
> drivers/crypto/ccree/cc_driver.h | 2 ++
> drivers/crypto/ccree/cc_host_regs.h | 6 ++++--
> 4 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/crypto/ccree/cc_debugfs.c b/drivers/crypto/ccree/cc_debugfs.c
> index 08f8db4..5ca184e 100644
> --- a/drivers/crypto/ccree/cc_debugfs.c
> +++ b/drivers/crypto/ccree/cc_debugfs.c
> @@ -26,7 +26,8 @@ struct cc_debugfs_ctx {
> static struct dentry *cc_debugfs_dir;
>
> static struct debugfs_reg32 debug_regs[] = {
> - CC_DEBUG_REG(HOST_SIGNATURE),
> + { .name = "SIGNATURE" }, /* Must be 0th */
> + { .name = "VERSION" }, /* Must be 1st */
> CC_DEBUG_REG(HOST_IRR),
> CC_DEBUG_REG(HOST_POWER_DOWN_EN),
> CC_DEBUG_REG(AXIM_MON_ERR),
> @@ -34,7 +35,6 @@ static struct debugfs_reg32 debug_regs[] = {
> CC_DEBUG_REG(HOST_IMR),
> CC_DEBUG_REG(AXIM_CFG),
> CC_DEBUG_REG(AXIM_CACHE_PARAMS),
> - CC_DEBUG_REG(HOST_VERSION),
> CC_DEBUG_REG(GPR_HOST),
> CC_DEBUG_REG(AXIM_MON_COMP),
> };
> @@ -58,6 +58,9 @@ int cc_debugfs_init(struct cc_drvdata *drvdata)
> struct debugfs_regset32 *regset;
> struct dentry *file;
>
> + debug_regs[0].offset = drvdata->sig_offset;
> + debug_regs[1].offset = drvdata->ver_offset;
> +
> ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> if (!ctx)
> return -ENOMEM;
> diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
> index 89ce013..6f93ce7 100644
> --- a/drivers/crypto/ccree/cc_driver.c
> +++ b/drivers/crypto/ccree/cc_driver.c
> @@ -207,9 +207,13 @@ static int init_cc_resources(struct platform_device *plat_dev)
> if (hw_rev->rev >= CC_HW_REV_712) {
> new_drvdata->hash_len_sz = HASH_LEN_SIZE_712;
> new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
> + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
> + new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
> } else {
> new_drvdata->hash_len_sz = HASH_LEN_SIZE_630;
> new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
> + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
> + new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
> }
>
> platform_set_drvdata(plat_dev, new_drvdata);
> @@ -276,7 +280,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
> }
>
> /* Verify correct mapping */
> - signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
> + signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
> if (signature_val != hw_rev->sig) {
> dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
> signature_val, hw_rev->sig);
> @@ -287,7 +291,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
>
> /* Display HW versions */
> dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
> - hw_rev->name, cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),
> + hw_rev->name, cc_ioread(new_drvdata, new_drvdata->ver_offset),
> DRV_MODULE_VERSION);
>
> rc = init_cc_regs(new_drvdata, true);
> diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
> index 2048fde..95f82b2 100644
> --- a/drivers/crypto/ccree/cc_driver.h
> +++ b/drivers/crypto/ccree/cc_driver.h
> @@ -129,6 +129,8 @@ struct cc_drvdata {
This patch doesn't make things (much) worse
but struct cc_drvdata has a rather incomplete kdoc.
> enum cc_hw_rev hw_rev;
> u32 hash_len_sz;
> u32 axim_mon_offset;
> + u32 sig_offset;
> + u32 ver_offset;
> };
>
> struct cc_crypto_alg {
> diff --git a/drivers/crypto/ccree/cc_host_regs.h b/drivers/crypto/ccree/cc_host_regs.h
> index f510018..616b2e1 100644
> --- a/drivers/crypto/ccree/cc_host_regs.h
> +++ b/drivers/crypto/ccree/cc_host_regs.h
> @@ -45,7 +45,8 @@
> #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL
> #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL
> #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL
> -#define CC_HOST_SIGNATURE_REG_OFFSET 0xA24UL
> +#define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL
> +#define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL
> #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL
> #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL
> #define CC_HOST_BOOT_REG_OFFSET 0xA28UL
> @@ -105,7 +106,8 @@
> #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL
> #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL
> #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL
> -#define CC_HOST_VERSION_REG_OFFSET 0xA40UL
> +#define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL
> +#define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL
> #define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL
> #define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL
> #define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 3/3] x86/mm: add TLB purge to free pmd/pte page interfaces
From: Kani, Toshi @ 2018-05-29 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180529144438.GM18595@8bytes.org>
On Tue, 2018-05-29 at 16:44 +0200, Joerg Roedel wrote:
> On Wed, May 16, 2018 at 05:32:07PM -0600, Toshi Kani wrote:
> > pmd = (pmd_t *)pud_page_vaddr(*pud);
> > + pmd_sv = (pmd_t *)__get_free_page(GFP_KERNEL);
> > + if (!pmd_sv)
> > + return 0;
>
> So your code still needs to allocate a full page where a simple
> list_head on the stack would do the same job.
Can you explain why you think allocating a page here is a major problem?
As I explained before, pud_free_pmd_page() covers an extremely rare case
which I could not even hit with a huge number of ioremap() calls until
I instrumented alloc_vmap_area() to force this case to happen. I do not
think pages should be listed for such a rare case.
> Ingo, Thomas, can you please just revert the original broken patch for
> now until there is proper fix?
If we just revert, please apply patch 1/3 first. This patch address the
BUG_ON issue on PAE. This is a real issue that needs a fix ASAP.
The page-directory cache issue on x64, which is addressed by patch 3/3,
is a theoretical issue that I could not hit by putting ioremap() calls
into a loop for a whole day. Nobody hit this issue, either.
The simple revert patch Joerg posted a while ago causes
pmd_free_pte_page() to fail on x64. This causes multiple pmd mappings
to fall into pte mappings on my test systems. This can be seen as a
degradation, and I am afraid that it is more harmful than good.
Thanks,
-Toshi
^ permalink raw reply
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