* linux-next: manual merge of the regulator tree with the arm-soc tree
From: Linus Walleij @ 2018-05-30 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530150711.2c7c1fe9@canb.auug.org.au>
On Wed, May 30, 2018 at 7:07 AM, Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> Hi all,
>
> Today's linux-next merge of the regulator tree got a conflict in:
>
> arch/arm/mach-omap1/board-ams-delta.c
>
> between commit:
>
> 0486738928bf ("ARM: OMAP1: ams-delta: add GPIO lookup tables")
>
> from the arm-soc tree and commit:
>
> 6059577cb28d ("regulator: fixed: Convert to use GPIO descriptor only")
>
> from the regulator tree.
>
> I fixed it up (see below - it may be better done) and can carry the fix
> as necessary.
OMG that patch on a patch makes my head spin.
I think I just have to look at the eventual result in linux-next and see if
it makes proper sense, and rely on Janusz to test the result and help
to fix it up.
I was unaware of this concurrent gpiod conversion inside OMAP1 but
I'm happy to see that it happens. We might have some fallout, but I'm
sure Janusz is on top of things.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] PCI: Add pci=safemode option
From: Christoph Hellwig @ 2018-05-30 7:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6c317ed8-cca3-8862-5f3b-12cf14e4d53b@codeaurora.org>
On Tue, May 29, 2018 at 09:41:33PM -0700, Sinan Kaya wrote:
> Bjorn and I discussed the need for such a "safe" mode feature when you
> want to bring up PCI for a platform. You want to turn off everything as
> a starter and just stick to bare minimum.
Can we please make it a config option the instead of adding code
to every kernel? Also maybe the bringup should be in the name
to make this more clear?
^ permalink raw reply
* [xlnx:xlnx_rebase_v4.14 308/940] drivers/usb/dwc3/core.h:1225: multiple definition of `dwc3_simple_wakeup_capable'
From: kbuild test robot @ 2018-05-30 7:37 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v4.14
head: 7a6053b3d256fa5bc23f28a9d9a23d7a2004c5b7
commit: c46d066e5633e178b138742850c37ed262a9af6d [308/940] dwc3: Add support for clock disabling during suspend
config: i386-randconfig-s0-201821 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout c46d066e5633e178b138742850c37ed262a9af6d
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/usb/dwc3/trace.o: In function `dwc3_simple_wakeup_capable':
>> drivers/usb/dwc3/core.h:1225: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1225: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_simple_wakeup_capable':
include/linux/device.h:984: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1225: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_simple_wakeup_capable':
>> drivers/usb/dwc3/core.h:1225: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1225: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_simple_wakeup_capable':
>> drivers/usb/dwc3/core.h:1225: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1225: first defined here
vim +1225 drivers/usb/dwc3/core.h
1214
1215 #if IS_ENABLED(CONFIG_USB_DWC3_OF_SIMPLE)
1216 int dwc3_enable_hw_coherency(struct device *dev);
1217 void dwc3_set_phydata(struct device *dev, struct phy *phy);
1218 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup);
1219 #else
1220 static inline int dwc3_enable_hw_coherency(struct device *dev)
1221 { return 1; }
1222 static inline void dwc3_set_phydata(struct device *dev, struct phy *phy)
1223 { ; }
1224 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup)
> 1225 { ; }
1226 #endif
1227
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v3 3/5] Documentation: DT: add i.MX EPIT timer binding
From: Vladimir Zapolskiy @ 2018-05-30 7:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7f2f8b6b-b7f6-99c1-fc5f-a7628a751fdc@mentor.com>
On 05/30/2018 10:27 AM, Vladimir Zapolskiy wrote:
> Hi Cl?ment,
>
> On 05/29/2018 08:04 PM, Cl?ment P?ron wrote:
>> From: Cl?ment Peron <clement.peron@devialet.com>
>>
>> Add devicetree binding document for NXP's i.MX SoC specific
>> EPIT timer driver.
>>
>> Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
>> ---
>> .../devicetree/bindings/clock/imx6q,epit.txt | 24 +++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/imx6q,epit.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/imx6q,epit.txt b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
>> new file mode 100644
>> index 000000000000..a84a60c6ae35
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/imx6q,epit.txt
>
> The file should be renamed to a more generic name like 'imx,epit.txt'
> or 'imx31,epit.txt'.
>
> Also note that the folder is incorrectly selected, it must be
> Documentation/devicetree/bindings/timer/
>
And linux-clk mailing list for publishing seems to be improper one,
instead please add Daniel Lezcano <daniel.lezcano@linaro.org> and
Thomas Gleixner <tglx@linutronix.de> to the list of addressees,
and the proper mailing list address is linux-kernel at vger.kernel.org
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH] PCI: Add pci=safemode option
From: okaya at codeaurora.org @ 2018-05-30 7:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530073735.GA28793@infradead.org>
On 2018-05-30 00:37, Christoph Hellwig wrote:
> On Tue, May 29, 2018 at 09:41:33PM -0700, Sinan Kaya wrote:
>> Bjorn and I discussed the need for such a "safe" mode feature when you
>> want to bring up PCI for a platform. You want to turn off everything
>> as
>> a starter and just stick to bare minimum.
>
> Can we please make it a config option the instead of adding code
> to every kernel? Also maybe the bringup should be in the name
> to make this more clear?
One other requirement was to have a runtime option rather than compile
time option.
When someone reported a problem, we wanted to be able to say "use this
option and see if system boots" without doing any bisects or
recompilation.
This would be the first step in troubleshooting a system to see if
fundamental features are working.
I don't mind changing the name
Bjorn mentioned safe option. I made it safemode. I am looking at Bjorn
for suggestions at this moment.
^ permalink raw reply
* [PATCH 08/12] drm/bridge: tc358764: Add DSI to LVDS bridge driver
From: kbuild test robot @ 2018-05-30 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527500833-16005-9-git-send-email-m.purski@samsung.com>
Hi Maciej,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20180517]
[cannot apply to drm-exynos/exynos-drm/for-next robh/for-next drm/drm-next v4.17-rc6 v4.17-rc5 v4.17-rc4 v4.17-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Maciej-Purski/Add-TOSHIBA-TC358764-DSI-LVDS-bridge-driver/20180530-011258
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/bridge/tc358764.c:193:14: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [unsigned] [addressable] [usertype] addr @@ got ed] [addressable] [usertype] addr @@
drivers/gpu/drm/bridge/tc358764.c:193:14: expected unsigned short [unsigned] [addressable] [usertype] addr
drivers/gpu/drm/bridge/tc358764.c:193:14: got restricted __le16 [usertype] <noident>
>> drivers/gpu/drm/bridge/tc358764.c:197:24: sparse: cast to restricted __le32
>> drivers/gpu/drm/bridge/tc358764.c:175:5: sparse: symbol 'tc358764_read' was not declared. Should it be static?
>> drivers/gpu/drm/bridge/tc358764.c:204:5: sparse: symbol 'tc358764_write' was not declared. Should it be static?
vim +193 drivers/gpu/drm/bridge/tc358764.c
174
> 175 int tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
176 {
177 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
178 const struct mipi_dsi_host_ops *ops = dsi->host->ops;
179 struct mipi_dsi_msg msg = {
180 .type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
181 .channel = dsi->channel,
182 .flags = MIPI_DSI_MSG_USE_LPM,
183 .tx_buf = &addr,
184 .tx_len = 2,
185 .rx_buf = val,
186 .rx_len = 4
187 };
188 ssize_t ret;
189
190 if (!ops || !ops->transfer)
191 return -EINVAL;
192
> 193 addr = cpu_to_le16(addr);
194
195 ret = ops->transfer(dsi->host, &msg);
196 if (ret >= 0)
> 197 *val = le32_to_cpu(*val);
198
199 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
200
201 return ret;
202 }
203
> 204 int tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
205 {
206 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
207 const struct mipi_dsi_host_ops *ops = dsi->host->ops;
208 u8 data[6];
209 int ret;
210 struct mipi_dsi_msg msg = {
211 .type = MIPI_DSI_GENERIC_LONG_WRITE,
212 .channel = dsi->channel,
213 .flags = MIPI_DSI_MSG_USE_LPM | MIPI_DSI_MSG_REQ_ACK,
214 .tx_buf = data,
215 .tx_len = 6
216 };
217
218 if (!ops || !ops->transfer)
219 return -EINVAL;
220
221 data[0] = addr;
222 data[1] = addr >> 8;
223 data[2] = val;
224 data[3] = val >> 8;
225 data[4] = val >> 16;
226 data[5] = val >> 24;
227
228 ret = ops->transfer(dsi->host, &msg);
229
230 return ret;
231 }
232
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH] PCI: Add pci=safemode option
From: Greg Kroah-Hartman @ 2018-05-30 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6dfe2db8f974d94c9867f30ec83d9333@codeaurora.org>
On Wed, May 30, 2018 at 12:44:29AM -0700, okaya at codeaurora.org wrote:
> On 2018-05-30 00:37, Christoph Hellwig wrote:
> > On Tue, May 29, 2018 at 09:41:33PM -0700, Sinan Kaya wrote:
> > > Bjorn and I discussed the need for such a "safe" mode feature when you
> > > want to bring up PCI for a platform. You want to turn off everything
> > > as
> > > a starter and just stick to bare minimum.
> >
> > Can we please make it a config option the instead of adding code
> > to every kernel? Also maybe the bringup should be in the name
> > to make this more clear?
>
> One other requirement was to have a runtime option rather than compile time
> option.
>
> When someone reported a problem, we wanted to be able to say "use this
> option and see if system boots" without doing any bisects or recompilation.
>
> This would be the first step in troubleshooting a system to see if
> fundamental features are working.
That makes sense, people can not rebuild their kernels for the most
part. Putting it behind a config option would not make sense as it
would always have to be enabled.
> I don't mind changing the name Bjorn mentioned safe option. I made it
> safemode. I am looking at Bjorn for suggestions at this moment.
"minimal"? "basic"? "crippled"?
"my_hardware_is_so_borked_it_needs_this_option"? :)
Naming is hard...
greg k-h
^ permalink raw reply
* [PATCH] PCI: Add pci=safemode option
From: okaya at codeaurora.org @ 2018-05-30 7:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530074822.GB30177@kroah.com>
On 2018-05-30 00:48, Greg Kroah-Hartman wrote:
> On Wed, May 30, 2018 at 12:44:29AM -0700, okaya at codeaurora.org wrote:
>> On 2018-05-30 00:37, Christoph Hellwig wrote:
>> > On Tue, May 29, 2018 at 09:41:33PM -0700, Sinan Kaya wrote:
>> > > Bjorn and I discussed the need for such a "safe" mode feature when you
>> > > want to bring up PCI for a platform. You want to turn off everything
>> > > as
>> > > a starter and just stick to bare minimum.
>> >
>> > Can we please make it a config option the instead of adding code
>> > to every kernel? Also maybe the bringup should be in the name
>> > to make this more clear?
>>
>> One other requirement was to have a runtime option rather than compile
>> time
>> option.
>>
>> When someone reported a problem, we wanted to be able to say "use this
>> option and see if system boots" without doing any bisects or
>> recompilation.
>>
>> This would be the first step in troubleshooting a system to see if
>> fundamental features are working.
>
> That makes sense, people can not rebuild their kernels for the most
> part. Putting it behind a config option would not make sense as it
> would always have to be enabled.
>
Here is where the discussion took place. Last 5-10 messages should
help.
https://bugzilla.kernel.org/show_bug.cgi?id=196197
>> I don't mind changing the name Bjorn mentioned safe option. I made it
>> safemode. I am looking at Bjorn for suggestions at this moment.
>
> "minimal"? "basic"? "crippled"?
> "my_hardware_is_so_borked_it_needs_this_option"? :)
>
> Naming is hard...
>
> greg k-h
^ permalink raw reply
* [PATCH v3 0/2] drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping
From: Thierry Reding @ 2018-05-30 8:03 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
An unfortunate interaction between the 32-bit ARM DMA/IOMMU mapping code
and Tegra SMMU driver changes to support IOMMU groups introduced a boot-
time regression on Tegra124. This was caught very late because none of
the standard configurations that are tested on Tegra enable the ARM DMA/
IOMMU mapping code since it is not needed.
The reason for the failure is that the GPU found on Tegra uses a special
bit in physical addresses to determine whether or not a buffer is mapped
through the SMMU. In order to achieve this, the Nouveau driver needs to
explicitly understand which buffers are mapped through the SMMU and
which aren't. Hiding usage of the SMMU behind the DMA API is bound to
fail because the knowledge doesn't exist. Furthermore, the GPU has its
own IOMMU and in most cases doesn't need buffers to be physically or
virtually contiguous. One notable exception is for compressible buffers
which need to be mapped with large pages, which in turn require all the
small pages in a large page to be contiguous. This can be achieved with
an SMMU mapping, though it isn't currently supported in Nouveau. Since
Translating through the SMMU is unnecessary and can have a negative
impact on performance for the common case, so we want to avoid it when
possible.
This series of patches adds a 32-bit ARM specific API that allows a
driver to detach the device from the DMA/IOMMU mapping so that it can
provide its own implementation for dealing with the SMMU. The second
patch makes use of that new API in the Nouveau driver to fix the
regression.
Thierry
Thierry Reding (2):
ARM: dma-mapping: Implement arm_dma_iommu_detach_device()
drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping
arch/arm/include/asm/dma-mapping.h | 3 +++
arch/arm/mm/dma-mapping-nommu.c | 4 ++++
arch/arm/mm/dma-mapping.c | 16 ++++++++++++++++
.../gpu/drm/nouveau/nvkm/engine/device/tegra.c | 5 +++++
4 files changed, 28 insertions(+)
--
2.17.0
^ permalink raw reply
* [PATCH v3 1/2] ARM: dma-mapping: Implement arm_dma_iommu_detach_device()
From: Thierry Reding @ 2018-05-30 8:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530080345.2353-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Implement this function to enable drivers from detaching from any IOMMU
domains that architecture code might have attached them to so that they
can take exclusive control of the IOMMU via the IOMMU API.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- make API 32-bit ARM specific
- avoid extra local variable
Changes in v2:
- fix compilation
arch/arm/include/asm/dma-mapping.h | 3 +++
arch/arm/mm/dma-mapping-nommu.c | 4 ++++
arch/arm/mm/dma-mapping.c | 16 ++++++++++++++++
3 files changed, 23 insertions(+)
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 8436f6ade57d..5960e9f3a9d0 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -103,6 +103,9 @@ extern void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
#define arch_teardown_dma_ops arch_teardown_dma_ops
extern void arch_teardown_dma_ops(struct device *dev);
+#define arm_dma_iommu_detach_device arm_dma_iommu_detach_device
+extern void arm_dma_iommu_detach_device(struct device *dev);
+
/* do not use this function in a driver */
static inline bool is_device_dma_coherent(struct device *dev)
{
diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
index f448a0663b10..eb781369377b 100644
--- a/arch/arm/mm/dma-mapping-nommu.c
+++ b/arch/arm/mm/dma-mapping-nommu.c
@@ -241,3 +241,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
void arch_teardown_dma_ops(struct device *dev)
{
}
+
+void arm_dma_iommu_detach_device(struct device *dev)
+{
+}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index af27f1c22d93..6d8af08b3e7d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -2400,3 +2400,19 @@ void arch_teardown_dma_ops(struct device *dev)
arm_teardown_iommu_dma_ops(dev);
}
+
+void arm_dma_iommu_detach_device(struct device *dev)
+{
+#ifdef CONFIG_ARM_DMA_USE_IOMMU
+ struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
+
+ if (!mapping)
+ return;
+
+ arm_iommu_release_mapping(mapping);
+ arm_iommu_detach_device(dev);
+
+ set_dma_ops(dev, arm_get_dma_map_ops(dev->archdata.dma_coherent));
+#endif
+}
+EXPORT_SYMBOL(arm_dma_iommu_detach_device);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/2] drm/nouveau: tegra: Detach from ARM DMA/IOMMU mapping
From: Thierry Reding @ 2018-05-30 8:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530080345.2353-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Depending on the kernel configuration, early ARM architecture setup code
may have attached the GPU to a DMA/IOMMU mapping that transparently uses
the IOMMU to back the DMA API. Tegra requires special handling for IOMMU
backed buffers (a special bit in the GPU's MMU page tables indicates the
memory path to take: via the SMMU or directly to the memory controller).
Transparently backing DMA memory with an IOMMU prevents Nouveau from
properly handling such memory accesses and causes memory access faults.
As a side-note: buffers other than those allocated in instance memory
don't need to be physically contiguous from the GPU's perspective since
the GPU can map them into contiguous buffers using its own MMU. Mapping
these buffers through the IOMMU is unnecessary and will even lead to
performance degradation because of the additional translation. One
exception to this are compressible buffers which need large pages. In
order to enable these large pages, multiple small pages will have to be
combined into one large (I/O virtually contiguous) mapping via the
IOMMU. However, that is a topic outside the scope of this fix and isn't
currently supported. An implementation will want to explicitly create
these large pages in the Nouveau driver, so detaching from a DMA/IOMMU
mapping would still be required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- clarify the use of IOMMU mapping for compressible buffers
- squash multiple patches into this
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 78597da6313a..d0538af1b967 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -105,6 +105,11 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev)
unsigned long pgsize_bitmap;
int ret;
+#if IS_ENABLED(CONFIG_ARM)
+ /* make sure we can use the IOMMU exclusively */
+ arm_dma_iommu_detach_device(dev);
+#endif
+
if (!tdev->func->iommu_bit)
return;
--
2.17.0
^ permalink raw reply related
* [PATCH 1/3] arm64:add missing CONFIG_STRICT_KERNEL_RWX for mark_rodata_ro
From: Mark Rutland @ 2018-05-30 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E490CD805F7529488761C40FD9D26EF12A672E03@dggemm507-mbx.china.huawei.com>
On Wed, May 30, 2018 at 03:31:38AM +0000, Nixiaoming wrote:
> Unable to set CONFIG_STRICT_KERNEL_RWX=n by make menuconfig ARCH=arm64
Indeed. Making this mandatory was a deliberate decision, in part because this
allows simplification of code (e.g. removal of #ifdef guards).
> When reading the code, I feel it is more appropriate to add macro control
> here.
I must disagree. I do not think it makes sense to add an #ifdef for a
configuration option that is mandatory.
There are other places in the kernel that should behave differently if
CONFIG_STRICT_KERNEL_RWX were disabled, so this wouldn't be sufficient even if
we were to make CONFIG_STRICT_KERNEL_RWX optional. i.e. the #ifdef would give
the misleading impression that STRICT_KERNEL_RWX *could* be made optional, even
though this might not function correctly.
Having an #ifdef here makes the code more complicated and confusing, for the
benefit of a case which cannot occur.
Thanks,
Mark.
> -----Original Message-----
> From: Will Deacon [mailto:will.deacon at arm.com]
> Sent: Tuesday, May 29, 2018 11:45 PM
> To: Nixiaoming <nixiaoming@huawei.com>
> Cc: catalin.marinas at arm.com; ard.biesheuvel at linaro.org; marc.zyngier at arm.com; james.morse at arm.com; kristina.martsenko at arm.com; steve.capper at arm.com; tglx at linutronix.de; mingo at redhat.com; hpa at zytor.com; akpm at linux-foundation.org; vbabka at suse.cz; mhocko at suse.com; dave.hansen at linux.intel.com; dan.j.williams at intel.com; kirill.shutemov at linux.intel.com; zhang.jia at linux.alibaba.com; schwidefsky at de.ibm.com; heiko.carstens at de.ibm.com; gregkh at linuxfoundation.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; x86 at kernel.org; linux-s390 at vger.kernel.org
> Subject: Re: [PATCH 1/3] arm64:add missing CONFIG_STRICT_KERNEL_RWX for mark_rodata_ro
>
> On Tue, May 29, 2018 at 09:36:15PM +0800, nixiaoming wrote:
> > mark_rodata_ro is only called by the function mark_readonly when
> > CONFIG_STRICT_KERNEL_RWX=y,
> > if CONFIG_STRICT_KERNEL_RWX is not set
> > a compile warning may be triggered: unused function
>
> How are you achieving this configuration? In our Kconfig we select this
> unconditionally.
>
> Will
^ permalink raw reply
* [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver
From: Michel Pollet @ 2018-05-30 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdWv2ZRbX=k5+H_WfAeoQ4QsyQLU9iQ9TJ9OQ0fmwg0GOQ@mail.gmail.com>
On 25 May 2018 10:49, Geert wrote:
> Subject: Re: [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler
> driver
>
> Hi Michel,
Hi Geert,
>
> On Thu, May 24, 2018 at 12:30 PM, Michel Pollet
> <michel.pollet@bp.renesas.com> wrote:
> > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time,
> > it requires a special enable method to get it started.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
>
> Thanks for your patch!
>
> > arch/arm/mach-shmobile/smp-r9a06g032.c | 85
> > ++++++++++++++++++++++++++++++++++
>
> I think you can safely call this driver smp-rzn1d.c, or smp-rzn1.c.
> Source files are not covered by the stable DT ABI, and can be reordered later
> at will.
>
> I expect you will just add more CPU_METHOD_OF_DECLARE() lines later
> (perhaps with a little bit of extra code to handle deviations).
Now I am completely confused -- you had me remove the mention of rzn1
from everywhere it mattered to handle 'family' cases, and now you are
telling me that in *this* case where there is not a single chance of that file
covering another part and there's a clear cut case for it to be part specific
.... I should call it rzn1?!?
I even already renamed the symbols on my tree to match the
rest for v4...
I'd like consistency -- I *thought* I had a consistent naming scheme before,
now I've moved to your part specific one (under duress), I'd rather stick to
something that is consistent and keep everything as r9a06g032 now.
>
> > --- /dev/null
> > +++ b/arch/arm/mach-shmobile/smp-r9a06g032.c
> > @@ -0,0 +1,85 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * RZ/N1D Second CA7 enabler.
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Europe Limited
> > + *
> > + * Michel Pollet <michel.pollet@bp.renesas.com>,
> <buserror@gmail.com>
> > + * Derived from action,s500-smp
> > + */
> > +
> > +#include <linux/delay.h>
>
> Do you need this?
Fixed all the other remarks, thanks for that!
Michel
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply
* [PATCH] PCI: Add pci=safemode option
From: okaya at codeaurora.org @ 2018-05-30 8:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <577f01ada5e7f08c79a28d41020fb019@codeaurora.org>
On 2018-05-30 00:56, okaya at codeaurora.org wrote:
> On 2018-05-30 00:48, Greg Kroah-Hartman wrote:
>> On Wed, May 30, 2018 at 12:44:29AM -0700, okaya at codeaurora.org wrote:
>>> On 2018-05-30 00:37, Christoph Hellwig wrote:
>>> > On Tue, May 29, 2018 at 09:41:33PM -0700, Sinan Kaya wrote:
>>> > > Bjorn and I discussed the need for such a "safe" mode feature when you
>>> > > want to bring up PCI for a platform. You want to turn off everything
>>> > > as
>>> > > a starter and just stick to bare minimum.
>>> >
>>> > Can we please make it a config option the instead of adding code
>>> > to every kernel? Also maybe the bringup should be in the name
>>> > to make this more clear?
>>>
>>> One other requirement was to have a runtime option rather than
>>> compile time
>>> option.
>>>
>>> When someone reported a problem, we wanted to be able to say "use
>>> this
>>> option and see if system boots" without doing any bisects or
>>> recompilation.
>>>
>>> This would be the first step in troubleshooting a system to see if
>>> fundamental features are working.
>>
>> That makes sense, people can not rebuild their kernels for the most
>> part. Putting it behind a config option would not make sense as it
>> would always have to be enabled.
>>
>
> Here is where the discussion took place. Last 5-10 messages should
> help.
>
>
> https://bugzilla.kernel.org/show_bug.cgi?id=196197
>
Some more paper trail for general awareness.
https://lkml.org/lkml/2018/5/3/509
>
>>> I don't mind changing the name Bjorn mentioned safe option. I made it
>>> safemode. I am looking at Bjorn for suggestions at this moment.
>>
>> "minimal"? "basic"? "crippled"?
>> "my_hardware_is_so_borked_it_needs_this_option"? :)
>>
>> Naming is hard...
>>
>> greg k-h
^ permalink raw reply
* [xlnx:xlnx_rebase_v4.14 309/940] drivers/usb/dwc3/core.h:1228: multiple definition of `dwc3_set_simple_data'
From: kbuild test robot @ 2018-05-30 8:24 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v4.14
head: 7a6053b3d256fa5bc23f28a9d9a23d7a2004c5b7
commit: 6b1601e752dd266a096860421d488efc8cffdc1f [309/940] dwc3: Add support for removing vbus when suspended
config: i386-randconfig-s0-201821 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout 6b1601e752dd266a096860421d488efc8cffdc1f
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/usb/dwc3/trace.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1226: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1226: first defined here
drivers/usb/dwc3/trace.o: In function `dwc3_set_simple_data':
>> drivers/usb/dwc3/core.h:1228: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1228: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_simple_wakeup_capable':
include/linux/device.h:984: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1226: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_set_simple_data':
>> drivers/usb/dwc3/core.h:1228: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1228: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1226: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1226: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_set_simple_data':
>> drivers/usb/dwc3/core.h:1228: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1228: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1226: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1226: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_set_simple_data':
>> drivers/usb/dwc3/core.h:1228: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1228: first defined here
vim +1228 drivers/usb/dwc3/core.h
1214
1215 #if IS_ENABLED(CONFIG_USB_DWC3_OF_SIMPLE)
1216 int dwc3_enable_hw_coherency(struct device *dev);
1217 void dwc3_set_phydata(struct device *dev, struct phy *phy);
1218 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup);
1219 void dwc3_set_simple_data(struct dwc3 *dwc);
1220 #else
1221 static inline int dwc3_enable_hw_coherency(struct device *dev)
1222 { return 1; }
1223 static inline void dwc3_set_phydata(struct device *dev, struct phy *phy)
1224 { ; }
1225 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup)
> 1226 { ; }
1227 void dwc3_set_simple_data(struct dwc3 *dwc)
> 1228 { ; }
1229 #endif
1230
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH 08/12] drm/bridge: tc358764: Add DSI to LVDS bridge driver
From: Andrzej Hajda @ 2018-05-30 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201805301553.AcTypuC4%fengguang.wu@intel.com>
Hi Maciej,
On 30.05.2018 09:45, kbuild test robot wrote:
> Hi Maciej,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on next-20180517]
> [cannot apply to drm-exynos/exynos-drm/for-next robh/for-next drm/drm-next v4.17-rc6 v4.17-rc5 v4.17-rc4 v4.17-rc7]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Maciej-Purski/Add-TOSHIBA-TC358764-DSI-LVDS-bridge-driver/20180530-011258
> reproduce:
> # apt-get install sparse
> make ARCH=x86_64 allmodconfig
> make C=1 CF=-D__CHECK_ENDIAN__
>
>
> sparse warnings: (new ones prefixed by >>)
>
>>> drivers/gpu/drm/bridge/tc358764.c:193:14: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [unsigned] [addressable] [usertype] addr @@ got ed] [addressable] [usertype] addr @@
> drivers/gpu/drm/bridge/tc358764.c:193:14: expected unsigned short [unsigned] [addressable] [usertype] addr
> drivers/gpu/drm/bridge/tc358764.c:193:14: got restricted __le16 [usertype] <noident>
>>> drivers/gpu/drm/bridge/tc358764.c:197:24: sparse: cast to restricted __le32
>>> drivers/gpu/drm/bridge/tc358764.c:175:5: sparse: symbol 'tc358764_read' was not declared. Should it be static?
>>> drivers/gpu/drm/bridge/tc358764.c:204:5: sparse: symbol 'tc358764_write' was not declared. Should it be static?
> vim +193 drivers/gpu/drm/bridge/tc358764.c
>
> 174
> > 175 int tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
add static
> 176 {
> 177 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> 178 const struct mipi_dsi_host_ops *ops = dsi->host->ops;
> 179 struct mipi_dsi_msg msg = {
> 180 .type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
> 181 .channel = dsi->channel,
> 182 .flags = MIPI_DSI_MSG_USE_LPM,
> 183 .tx_buf = &addr,
> 184 .tx_len = 2,
> 185 .rx_buf = val,
> 186 .rx_len = 4
> 187 };
> 188 ssize_t ret;
> 189
> 190 if (!ops || !ops->transfer)
> 191 return -EINVAL;
> 192
> > 193 addr = cpu_to_le16(addr);
It should be changed to:
cpu_to_le16s(&addr);
> 194
> 195 ret = ops->transfer(dsi->host, &msg);
> 196 if (ret >= 0)
> > 197 *val = le32_to_cpu(*val);
le32_to_cpus(val);
> 198
> 199 dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
> 200
> 201 return ret;
> 202 }
> 203
> > 204 int tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
add static
Regards
Andrzej
> 205 {
> 206 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> 207 const struct mipi_dsi_host_ops *ops = dsi->host->ops;
> 208 u8 data[6];
> 209 int ret;
> 210 struct mipi_dsi_msg msg = {
> 211 .type = MIPI_DSI_GENERIC_LONG_WRITE,
> 212 .channel = dsi->channel,
> 213 .flags = MIPI_DSI_MSG_USE_LPM | MIPI_DSI_MSG_REQ_ACK,
> 214 .tx_buf = data,
> 215 .tx_len = 6
> 216 };
> 217
> 218 if (!ops || !ops->transfer)
> 219 return -EINVAL;
> 220
> 221 data[0] = addr;
> 222 data[1] = addr >> 8;
> 223 data[2] = val;
> 224 data[3] = val >> 8;
> 225 data[4] = val >> 16;
> 226 data[5] = val >> 24;
> 227
> 228 ret = ops->transfer(dsi->host, &msg);
> 229
> 230 return ret;
> 231 }
> 232
>
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
>
>
>
^ permalink raw reply
* [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver
From: Geert Uytterhoeven @ 2018-05-30 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <OSBPR01MB20546AE06422C9AD896F8F60D26C0@OSBPR01MB2054.jpnprd01.prod.outlook.com>
Hi Michel,
On Wed, May 30, 2018 at 10:19 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> On 25 May 2018 10:49, Geert wrote:
>> On Thu, May 24, 2018 at 12:30 PM, Michel Pollet
>> <michel.pollet@bp.renesas.com> wrote:
>> > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time,
>> > it requires a special enable method to get it started.
>> >
>> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
>>
>> Thanks for your patch!
>>
>> > arch/arm/mach-shmobile/smp-r9a06g032.c | 85
>> > ++++++++++++++++++++++++++++++++++
>>
>> I think you can safely call this driver smp-rzn1d.c, or smp-rzn1.c.
>> Source files are not covered by the stable DT ABI, and can be reordered later
>> at will.
>>
>> I expect you will just add more CPU_METHOD_OF_DECLARE() lines later
>> (perhaps with a little bit of extra code to handle deviations).
>
> Now I am completely confused -- you had me remove the mention of rzn1
> from everywhere it mattered to handle 'family' cases, and now you are
> telling me that in *this* case where there is not a single chance of that file
> covering another part and there's a clear cut case for it to be part specific
> .... I should call it rzn1?!?
Sorry for confusing you.
There's a difference between stable DT ABI and (non-existing) kernel stable ABI.
A driver that handles multiple SoCs can be named after the SoC family.
I agree this one is a bit special, as only RZ/N1D has the dual Cortex A7
(RZ/N1S has a single A7, RZ/N1L has no A7), so for now[*] there's no need
to use it on anything but r9a06g032 aka RZ/N1D.
> I'd like consistency -- I *thought* I had a consistent naming scheme before,
> now I've moved to your part specific one (under duress), I'd rather stick to
> something that is consistent and keep everything as r9a06g032 now.
OK for me. Driver names can be changed any time.
[*] Until e.g. a quad A7 arrives :-)
Perhaps this can also be used to enable the A7s on both RZ/N1D and
RZ/N1S when running Linux on the Cortex M3?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v9 00/12] Support PPTT for ARM64
From: Morten Rasmussen @ 2018-05-30 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdWgsRTqrgwi5Z_xyNXmzS1h4gxLaawdFAL_DGF+Yt8s-A@mail.gmail.com>
On Tue, May 29, 2018 at 05:50:47PM +0200, Geert Uytterhoeven wrote:
> Hi Sudeep,
>
> On Tue, May 29, 2018 at 3:18 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> > On 29/05/18 12:56, Geert Uytterhoeven wrote:
> >> On Tue, May 29, 2018 at 1:14 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> >>> On 29/05/18 11:48, Geert Uytterhoeven wrote:
> >>>> On Thu, May 17, 2018 at 7:05 PM, Catalin Marinas
> >>>> <catalin.marinas@arm.com> wrote:
> >>>>> On Fri, May 11, 2018 at 06:57:55PM -0500, Jeremy Linton wrote:
> >>>>>> Jeremy Linton (12):
> >>>>>> arm64: topology: divorce MC scheduling domain from core_siblings
> >>>>>
> >>>>> Queued for 4.18 (without Sudeep's latest property_read_u64 cacheinfo
> >>>>> patch - http://lkml.kernel.org/r/20180517154701.GA20281 at e107155-lin; I
> >>>>> can add it separately).
> >>>>
> >>>> This is now commit 37c3ec2d810f87ea ("arm64: topology: divorce MC
> >>>> scheduling domain from core_siblings") in arm64/for-next/core, causing
> >>>> system suspend on big.LITTLE systems to hang after shutting down the first
> >>>> CPU:
> >>>>
> >>>> $ echo mem > /sys/power/state
> >>>> PM: suspend entry (deep)
> >>>> PM: Syncing filesystems ... done.
> >>>> Freezing user space processes ... (elapsed 0.001 seconds) done.
> >>>> OOM killer disabled.
> >>>> Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
> >>>> Disabling non-boot CPUs ...
> >>>> CPU1: shutdown
> >>>> psci: CPU1 killed.
> >>>
> >>> Is it OK to assume the suspend failed just after shutting down one CPU
> >>> or it's failing during resume ? It depends on whether you had console
> >>> disabled or not.
> >>
> >> I have no-console-suspend enabled.
> >> It's failing during suspend, the next lines should be:
> >>
> >> CPU2: shutdown
> >> psci: CPU2 killed.
> >> ...
> >
> > OK, I was hoping to be something during resume as this patch has nothing
> > executed during suspend. Do you see any change in topology before and
> > after this patch applied. I am interested in the output of:
> >
> > $ grep "" /sys/devices/system/cpu/cpu*/topology/*
>
> /sys/devices/system/cpu/cpu0/topology/core_id:0
> /sys/devices/system/cpu/cpu0/topology/core_siblings:0f
> /sys/devices/system/cpu/cpu0/topology/core_siblings_list:0-3
> /sys/devices/system/cpu/cpu0/topology/physical_package_id:0
> /sys/devices/system/cpu/cpu0/topology/thread_siblings:01
> /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0
> /sys/devices/system/cpu/cpu1/topology/core_id:1
> /sys/devices/system/cpu/cpu1/topology/core_siblings:0f
> /sys/devices/system/cpu/cpu1/topology/core_siblings_list:0-3
> /sys/devices/system/cpu/cpu1/topology/physical_package_id:0
> /sys/devices/system/cpu/cpu1/topology/thread_siblings:02
> /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:1
> /sys/devices/system/cpu/cpu2/topology/core_id:2
> /sys/devices/system/cpu/cpu2/topology/core_siblings:0f
> /sys/devices/system/cpu/cpu2/topology/core_siblings_list:0-3
> /sys/devices/system/cpu/cpu2/topology/physical_package_id:0
> /sys/devices/system/cpu/cpu2/topology/thread_siblings:04
> /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2
> /sys/devices/system/cpu/cpu3/topology/core_id:3
> /sys/devices/system/cpu/cpu3/topology/core_siblings:0f
> /sys/devices/system/cpu/cpu3/topology/core_siblings_list:0-3
> /sys/devices/system/cpu/cpu3/topology/physical_package_id:0
> /sys/devices/system/cpu/cpu3/topology/thread_siblings:08
> /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:3
> /sys/devices/system/cpu/cpu4/topology/core_id:0
> /sys/devices/system/cpu/cpu4/topology/core_siblings:f0
> /sys/devices/system/cpu/cpu4/topology/core_siblings_list:4-7
> /sys/devices/system/cpu/cpu4/topology/physical_package_id:1
> /sys/devices/system/cpu/cpu4/topology/thread_siblings:10
> /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
> /sys/devices/system/cpu/cpu5/topology/core_id:1
> /sys/devices/system/cpu/cpu5/topology/core_siblings:f0
> /sys/devices/system/cpu/cpu5/topology/core_siblings_list:4-7
> /sys/devices/system/cpu/cpu5/topology/physical_package_id:1
> /sys/devices/system/cpu/cpu5/topology/thread_siblings:20
> /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
> /sys/devices/system/cpu/cpu6/topology/core_id:2
> /sys/devices/system/cpu/cpu6/topology/core_siblings:f0
> /sys/devices/system/cpu/cpu6/topology/core_siblings_list:4-7
> /sys/devices/system/cpu/cpu6/topology/physical_package_id:1
> /sys/devices/system/cpu/cpu6/topology/thread_siblings:40
> /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
> /sys/devices/system/cpu/cpu7/topology/core_id:3
> /sys/devices/system/cpu/cpu7/topology/core_siblings:f0
> /sys/devices/system/cpu/cpu7/topology/core_siblings_list:4-7
> /sys/devices/system/cpu/cpu7/topology/physical_package_id:1
> /sys/devices/system/cpu/cpu7/topology/thread_siblings:80
> /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
>
> No change before/after (both match my view of the hardware).
There shouldn't be any change in the reported topology with this patch
as that the topology_* functions are not touched by the patch.
The patch should only affect the topology used by the scheduler which
isn't necessarily the same as the user-space visible one.
Morten
^ permalink raw reply
* [PATCH 1/4] arm64: capabilities: add nopti command line argument
From: Suzuki K Poulose @ 2018-05-30 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524190932.32118-2-mlangsdo@redhat.com>
Hi Mark,
On 24/05/18 20:09, Mark Langsdorf wrote:
> The x86 kernel and the documentation use 'nopti' as the kernel command
> line argument to disable kernel page table isolation, so add nopti to
> the arm64 kernel for compatibility.
>
> Signed-off-by: Mark Langsdorf <mlangsdo@redhat.com>
> ---
> Documentation/admin-guide/kernel-parameters.txt | 6 +++---
> arch/arm64/kernel/cpufeature.c | 11 ++++++++++-
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index f2040d4..a987725 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -3342,8 +3342,8 @@
> pt. [PARIDE]
> See Documentation/blockdev/paride.txt.
>
> - pti= [X86_64] Control Page Table Isolation of user and
> - kernel address spaces. Disabling this feature
> + pti= [X86_64, ARM64] Control Page Table Isolation of user
> + and kernel address spaces. Disabling this feature
> removes hardening, but improves performance of
> system calls and interrupts.
...
>
> @@ -3354,7 +3354,7 @@
>
> Not specifying this option is equivalent to pti=auto.
>
> - nopti [X86_64]
> + nopti [X86_64, ARM64]
> Equivalent to pti=off
>
> pty.legacy_count=
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 9d1b06d..7c5d8712 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -934,10 +934,19 @@ static int __init parse_kpti(char *str)
> if (ret)
> return ret;
>
> - __kpti_forced = enabled ? 1 : -1;
> + if (!__kpti_forced)
> + __kpti_forced = enabled ? 1 : -1;
> return 0;
> }
> __setup("kpti=", parse_kpti);
The arm64 kernel parameter is named "kpti", while the Documentation update above
says "pti". We may want to keep both in sync here.
> +
> +/* for compatibility with documentation and x86 nopti command line arg */
> +static int __init force_nokpti(char *arg)
> +{
> + __kpti_forced = -1;
> + return 0;
> +}
> +early_param("nopti", force_nokpti);
> #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
>
> #ifdef CONFIG_ARM64_HW_AFDBM
>
Suzuki
^ permalink raw reply
* [PATCH] arm64: alternative:flush cache with unpatched code
From: Will Deacon @ 2018-05-30 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527617488-5693-1-git-send-email-rokhanna@nvidia.com>
Hi Rohit,
Please keep me on cc for future versions of this patch. Comments inline.
On Tue, May 29, 2018 at 11:11:28AM -0700, Rohit Khanna wrote:
> In the current implementation, __apply_alternatives patches
> flush_icache_range and then executes it without invalidating the icache.
> Thus, icache can contain some of the old instructions for
> flush_icache_range. This can cause unpredictable behavior as during
> execution we can get a mix of old and new instructions for
> flush_icache_range.
>
> This patch :
> 1. Adds a new function flush_cache_kernel_range for flushing kernel
> memory range. This function uses non hot-patched code and can be
> safely used to flush cache during code patching.
>
> 2. Modifies __apply_alternatives so that it uses
> flush_cache_kernel_range to flush the cache range after patching code.
>
> Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
> ---
> arch/arm64/kernel/alternative.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
> index 5c4bce4ac381..e93cfd26a314 100644
> --- a/arch/arm64/kernel/alternative.c
> +++ b/arch/arm64/kernel/alternative.c
> @@ -122,6 +122,33 @@ static void patch_alternative(struct alt_instr *alt,
> }
> }
>
> +/* This is used for flushing kernel memory range after
> + * __apply_alternatives has patched kernel code
> + */
> +static void flush_cache_kernel_range(void *start, void *end)
> +{
How about something like clean_dcache_range_nopatch instead?
> + u64 d_start, i_start, d_size, i_size;
> +
> + /* use sanitized value of ctr_el0 rather than raw value from CPU */
> + d_size = 4 << ((arm64_ftr_reg_ctrel0.sys_val >> 0x10) & 0xF); /* bytes */
> + i_size = 4 << (arm64_ftr_reg_ctrel0.sys_val & 0xF); /* bytes */
You should be able to use read_sanitised_ftr_reg() and
cpuid_feature_extract_unsigned_field() here.
> + d_start = (u64)start & ~(d_size - 1);
> + while (d_start <= (u64)end) {
Please add a comment about the A53 erratum this is handling by using
clean+inv.
> + asm volatile("dc civac, %0" : : "r" (d_start));
> + d_start += d_size;
> + }
> + dsb(ish);
> +
> + i_start = (u64)start & ~(i_size - 1);
> + while (i_start <= (u64)end) {
> + asm volatile("ic ivau, %0" : : "r" (i_start));
> + i_start += i_size;
> + }
> + dsb(ish);
> + isb();
As I mentioned before, I think it would be simpler just to avoid doing the
I-cache invalidation by range and instead call __flush_icache_all once we've
exiting the loop in __apply_alternatives.
Will
^ permalink raw reply
* [PATCH 1/3] arm64:add missing CONFIG_STRICT_KERNEL_RWX for mark_rodata_ro
From: Nixiaoming @ 2018-05-30 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530080816.f74elebj4demiohl@salmiak>
Because CONFIG_STRICT_KERNEL_RWX=n cannot be set by make menuconfig on arm64/x86/s390 architecture
So, these three patches should not be necessary
Sorry to disturb everyone
Thank you for your guidance
Thanks
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, May 30, 2018 4:08 PM
To: Nixiaoming <nixiaoming@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>; catalin.marinas at arm.com; ard.biesheuvel at linaro.org; marc.zyngier at arm.com; james.morse at arm.com; kristina.martsenko at arm.com; steve.capper at arm.com; tglx at linutronix.de; mingo at redhat.com; hpa at zytor.com; akpm at linux-foundation.org; vbabka at suse.cz; mhocko at suse.com; dave.hansen at linux.intel.com; dan.j.williams at intel.com; kirill.shutemov at linux.intel.com; zhang.jia at linux.alibaba.com; schwidefsky at de.ibm.com; heiko.carstens at de.ibm.com; gregkh at linuxfoundation.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; x86 at kernel.org; linux-s390 at vger.kernel.org
Subject: Re: [PATCH 1/3] arm64:add missing CONFIG_STRICT_KERNEL_RWX for mark_rodata_ro
On Wed, May 30, 2018 at 03:31:38AM +0000, Nixiaoming wrote:
> Unable to set CONFIG_STRICT_KERNEL_RWX=n by make menuconfig ARCH=arm64
Indeed. Making this mandatory was a deliberate decision, in part because this
allows simplification of code (e.g. removal of #ifdef guards).
> When reading the code, I feel it is more appropriate to add macro control
> here.
I must disagree. I do not think it makes sense to add an #ifdef for a
configuration option that is mandatory.
There are other places in the kernel that should behave differently if
CONFIG_STRICT_KERNEL_RWX were disabled, so this wouldn't be sufficient even if
we were to make CONFIG_STRICT_KERNEL_RWX optional. i.e. the #ifdef would give
the misleading impression that STRICT_KERNEL_RWX *could* be made optional, even
though this might not function correctly.
Having an #ifdef here makes the code more complicated and confusing, for the
benefit of a case which cannot occur.
Thanks,
Mark.
> -----Original Message-----
> From: Will Deacon [mailto:will.deacon at arm.com]
> Sent: Tuesday, May 29, 2018 11:45 PM
> To: Nixiaoming <nixiaoming@huawei.com>
> Cc: catalin.marinas at arm.com; ard.biesheuvel at linaro.org; marc.zyngier at arm.com; james.morse at arm.com; kristina.martsenko at arm.com; steve.capper at arm.com; tglx at linutronix.de; mingo at redhat.com; hpa at zytor.com; akpm at linux-foundation.org; vbabka at suse.cz; mhocko at suse.com; dave.hansen at linux.intel.com; dan.j.williams at intel.com; kirill.shutemov at linux.intel.com; zhang.jia at linux.alibaba.com; schwidefsky at de.ibm.com; heiko.carstens at de.ibm.com; gregkh at linuxfoundation.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; x86 at kernel.org; linux-s390 at vger.kernel.org
> Subject: Re: [PATCH 1/3] arm64:add missing CONFIG_STRICT_KERNEL_RWX for mark_rodata_ro
>
> On Tue, May 29, 2018 at 09:36:15PM +0800, nixiaoming wrote:
> > mark_rodata_ro is only called by the function mark_readonly when
> > CONFIG_STRICT_KERNEL_RWX=y,
> > if CONFIG_STRICT_KERNEL_RWX is not set
> > a compile warning may be triggered: unused function
>
> How are you achieving this configuration? In our Kconfig we select this
> unconditionally.
>
> Will
^ permalink raw reply
* [xlnx:xlnx_rebase_v4.14 310/940] drivers/usb/dwc3/core.h:1231: multiple definition of `dwc3_simple_check_quirks'
From: kbuild test robot @ 2018-05-30 9:09 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v4.14
head: 7a6053b3d256fa5bc23f28a9d9a23d7a2004c5b7
commit: 2f495929d82aae1cbd308f22d4cf46ca2937530e [310/940] dwc3: Correct errors when dwc3 loaded as module
config: i386-randconfig-s0-201821 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout 2f495929d82aae1cbd308f22d4cf46ca2937530e
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/usb/dwc3/trace.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/trace.o: In function `dwc3_set_simple_data':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/trace.o: In function `dwc3_simple_check_quirks':
>> drivers/usb/dwc3/core.h:1231: multiple definition of `dwc3_simple_check_quirks'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1231: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_simple_wakeup_capable':
include/linux/device.h:984: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_set_simple_data':
include/linux/device.h:984: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/host.o: In function `dwc3_simple_check_quirks':
>> drivers/usb/dwc3/core.h:1231: multiple definition of `dwc3_simple_check_quirks'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1231: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_set_simple_data':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/ulpi.o: In function `dwc3_simple_check_quirks':
>> drivers/usb/dwc3/core.h:1231: multiple definition of `dwc3_simple_check_quirks'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1231: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_simple_wakeup_capable':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_simple_wakeup_capable'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_set_simple_data':
drivers/usb/dwc3/core.h:1227: multiple definition of `dwc3_set_simple_data'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1227: first defined here
drivers/usb/dwc3/debugfs.o: In function `dwc3_simple_check_quirks':
>> drivers/usb/dwc3/core.h:1231: multiple definition of `dwc3_simple_check_quirks'
drivers/usb/dwc3/core.o:drivers/usb/dwc3/core.h:1231: first defined here
vim +1231 drivers/usb/dwc3/core.h
1214
1215 #if IS_ENABLED(CONFIG_USB_DWC3_OF_SIMPLE)
1216 int dwc3_enable_hw_coherency(struct device *dev);
1217 void dwc3_set_phydata(struct device *dev, struct phy *phy);
1218 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup);
1219 void dwc3_set_simple_data(struct dwc3 *dwc);
1220 void dwc3_simple_check_quirks(struct dwc3 *dwc);
1221 #else
1222 static inline int dwc3_enable_hw_coherency(struct device *dev)
1223 { return 1; }
1224 static inline void dwc3_set_phydata(struct device *dev, struct phy *phy)
1225 { ; }
1226 void dwc3_simple_wakeup_capable(struct device *dev, bool wakeup)
> 1227 { ; }
1228 void dwc3_set_simple_data(struct dwc3 *dwc)
1229 { ; }
1230 void dwc3_simple_check_quirks(struct dwc3 *dwc)
> 1231 { ; }
1232 #endif
1233
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH 0/8] add UniPhier DVB Frontend system support
From: Katsuhiro Suzuki @ 2018-05-30 9:09 UTC (permalink / raw)
To: linux-arm-kernel
This series adds support for DVB Frontend system named HSC support
for UniPhier LD11/LD20 SoCs. This driver supports MPEG2-TS serial
signal input from external demodulator and DMA MPEG2-TS stream data
onto memory.
UniPhier HSC driver provides many ports of TS input. Since the HSC
has mixed register map for those ports. It hard to split each register
areas.
Katsuhiro Suzuki (8):
media: uniphier: add DT bindings documentation for UniPhier HSC
media: uniphier: add headers of HSC MPEG2-TS I/O driver
media: uniphier: add submodules of HSC MPEG2-TS I/O driver
media: uniphier: add common module of HSC MPEG2-TS I/O driver
media: uniphier: add LD11/LD20 HSC support
media: uniphier: add common module of DVB adapter drivers
media: uniphier: add LD11 adapter driver for ISDB
media: uniphier: add LD20 adapter driver for ISDB
.../bindings/media/uniphier,hsc.txt | 38 ++
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/uniphier/Kconfig | 37 ++
drivers/media/platform/uniphier/Makefile | 12 +
drivers/media/platform/uniphier/hsc-core.c | 506 ++++++++++++++++++
drivers/media/platform/uniphier/hsc-css.c | 258 +++++++++
drivers/media/platform/uniphier/hsc-dma.c | 302 +++++++++++
drivers/media/platform/uniphier/hsc-ld11.c | 219 ++++++++
drivers/media/platform/uniphier/hsc-reg.h | 491 +++++++++++++++++
drivers/media/platform/uniphier/hsc-ts.c | 99 ++++
drivers/media/platform/uniphier/hsc-ucode.c | 436 +++++++++++++++
drivers/media/platform/uniphier/hsc.h | 480 +++++++++++++++++
.../platform/uniphier/ld11-mn884433-helene.c | 265 +++++++++
.../platform/uniphier/ld20-mn884434-helene.c | 274 ++++++++++
.../platform/uniphier/uniphier-adapter.c | 54 ++
.../platform/uniphier/uniphier-adapter.h | 42 ++
17 files changed, 3516 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/uniphier,hsc.txt
create mode 100644 drivers/media/platform/uniphier/Kconfig
create mode 100644 drivers/media/platform/uniphier/Makefile
create mode 100644 drivers/media/platform/uniphier/hsc-core.c
create mode 100644 drivers/media/platform/uniphier/hsc-css.c
create mode 100644 drivers/media/platform/uniphier/hsc-dma.c
create mode 100644 drivers/media/platform/uniphier/hsc-ld11.c
create mode 100644 drivers/media/platform/uniphier/hsc-reg.h
create mode 100644 drivers/media/platform/uniphier/hsc-ts.c
create mode 100644 drivers/media/platform/uniphier/hsc-ucode.c
create mode 100644 drivers/media/platform/uniphier/hsc.h
create mode 100644 drivers/media/platform/uniphier/ld11-mn884433-helene.c
create mode 100644 drivers/media/platform/uniphier/ld20-mn884434-helene.c
create mode 100644 drivers/media/platform/uniphier/uniphier-adapter.c
create mode 100644 drivers/media/platform/uniphier/uniphier-adapter.h
--
2.17.0
^ permalink raw reply
* [PATCH 1/8] media: uniphier: add DT bindings documentation for UniPhier HSC
From: Katsuhiro Suzuki @ 2018-05-30 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530090946.1635-1-suzuki.katsuhiro@socionext.com>
This patch adds DT binding documentation for UniPhier HSC which is
MPEG2-TS input/output and demux subsystem.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
---
.../bindings/media/uniphier,hsc.txt | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/uniphier,hsc.txt
diff --git a/Documentation/devicetree/bindings/media/uniphier,hsc.txt b/Documentation/devicetree/bindings/media/uniphier,hsc.txt
new file mode 100644
index 000000000000..4242483b2ecc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/uniphier,hsc.txt
@@ -0,0 +1,38 @@
+Socionext UniPhier HSC (High-speed Stream Controller)
+
+The Socionext UniPhier HSC subsystem consists of MPEG2-TS input/output and
+demultiplexer cores in the same register space.
+
+This interface is support TS serial signals (clock, valid, sync, data) from
+external demodulators.
+
+Required properties:
+- compatible : should be one of the following:
+ "socionext,uniphier-ld11-hsc"
+ "socionext,uniphier-ld20-hsc"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain DMA and TSI error interrupt.
+- pinctrl-names : should be "default".
+- pinctrl-0 : defined TS serial signal pins for external demodulators.
+- clock-names : should include following entries:
+ "hsc", "stdmac"
+- clocks : a list of phandle, should contain an entry for each
+ entry in clock-names.
+- reset-names : should include following entries:
+ "hsc", "stdmac"
+- resets : a list of phandle, should contain an entry for each
+ entry in reset-names.
+
+Example:
+ hsc {
+ compatible = "socionext,uniphier-ld20-hsc";
+ reg = <0x5c000000 0x100000>;
+ interrupts = <0 100 4>, <0 101 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hscin2_s>,
+ <&pinctrl_hscin3_s>;
+ clock-names = "stdmac", "hsc";
+ clocks = <&sys_clk 8>, <&sys_clk 9>;
+ reset-names = "stdmac", "hsc";
+ resets = <&sys_rst 8>, <&sys_rst 9>;
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH 2/8] media: uniphier: add headers of HSC MPEG2-TS I/O driver
From: Katsuhiro Suzuki @ 2018-05-30 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180530090946.1635-1-suzuki.katsuhiro@socionext.com>
This patch adds register definitions of HSC (High speed Stream
Controller) driver for Socionext UniPhier SoCs. The HSC enables to
input and output MPEG2-TS stream from/to outer world of SoC.
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/uniphier/Kconfig | 9 +
drivers/media/platform/uniphier/Makefile | 1 +
drivers/media/platform/uniphier/hsc-reg.h | 491 ++++++++++++++++++++++
drivers/media/platform/uniphier/hsc.h | 480 +++++++++++++++++++++
6 files changed, 984 insertions(+)
create mode 100644 drivers/media/platform/uniphier/Kconfig
create mode 100644 drivers/media/platform/uniphier/Makefile
create mode 100644 drivers/media/platform/uniphier/hsc-reg.h
create mode 100644 drivers/media/platform/uniphier/hsc.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 2728376b04b5..289ab4dfd30e 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -525,6 +525,7 @@ menuconfig DVB_PLATFORM_DRIVERS
if DVB_PLATFORM_DRIVERS
source "drivers/media/platform/sti/c8sectpfe/Kconfig"
+source "drivers/media/platform/uniphier/Kconfig"
endif #DVB_PLATFORM_DRIVERS
menuconfig CEC_PLATFORM_DRIVERS
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 04bc1502a30e..08d5052119ef 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -93,3 +93,5 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss-8x16/
obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
obj-y += meson/
+
+obj-$(CONFIG_DVB_UNIPHIER) += uniphier/
diff --git a/drivers/media/platform/uniphier/Kconfig b/drivers/media/platform/uniphier/Kconfig
new file mode 100644
index 000000000000..1b4543ec1e3c
--- /dev/null
+++ b/drivers/media/platform/uniphier/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+config DVB_UNIPHIER
+ tristate "Socionext UniPhier Frontend"
+ depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
+ depends on ARCH_UNIPHIER
+ help
+ Driver for UniPhier frontend for MPEG2-TS input/output,
+ demux and descramble.
+ Say Y when you want to support this frontend.
diff --git a/drivers/media/platform/uniphier/Makefile b/drivers/media/platform/uniphier/Makefile
new file mode 100644
index 000000000000..f66554cd5c45
--- /dev/null
+++ b/drivers/media/platform/uniphier/Makefile
@@ -0,0 +1 @@
+# SPDX-License-Identifier: GPL-2.0
diff --git a/drivers/media/platform/uniphier/hsc-reg.h b/drivers/media/platform/uniphier/hsc-reg.h
new file mode 100644
index 000000000000..5f0a9b86cf49
--- /dev/null
+++ b/drivers/media/platform/uniphier/hsc-reg.h
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Socionext UniPhier DVB driver for High-speed Stream Controller (HSC).
+ *
+ * Copyright (c) 2018 Socionext Inc.
+ */
+
+#ifndef DVB_UNIPHIER_HSC_REG_H__
+#define DVB_UNIPHIER_HSC_REG_H__
+
+/*
+ * CH_0 : CIP-R8, W9
+ * CH_1 : CIP-R10,W11
+ * CH_2 : CIP-R12,W13
+ * CH_3 : CIP-R14,W15
+ * CH_4 : CIP-R16,W17
+ */
+enum HSC_CIP_FILE_NO {
+ HSC_CIP_FILE_NO_0 = 0x0,
+ HSC_CIP_FILE_NO_1,
+ HSC_CIP_FILE_NO_2,
+ HSC_CIP_FILE_NO_3,
+ HSC_CIP_FILE_NO_4,
+ HSC_CIP_FILE_NO_END,
+ HSC_CIP_FILE_NO_DISABLE,
+};
+
+#define HSC_CIP_FILE_TO_CIPR(i) ((i) * 2 + 0)
+#define HSC_CIP_FILE_TO_CIPW(i) ((i) * 2 + 1)
+#define HSC_CIP_FILE_TO_CIPR_DMCH(i) (HSC_CIP_FILE_TO_CIPR(i) + 8)
+#define HSC_CIP_FILE_TO_CIPW_DMCH(i) (HSC_CIP_FILE_TO_CIPW(i) + 8)
+
+/* RAM Address */
+#define FLT_PATN_RAM_TOP_ADDR 0x0a000
+#define FLT_MASK_RAM_TOP_ADDR 0x0b000
+#define SHARE_MEMORY_0_NORMAL 0x10000
+#define SHARE_MEMORY_1_NORMAL 0x11000
+#define SHARE_MEMORY_2_NORMAL 0x12000
+#define SHARE_MEMORY_3_NORMAL 0x13000
+#define SHARE_MEMORY_4_NORMAL 0x14000
+#define SHARE_MEMORY_5_NORMAL 0x15000
+#define SHARE_MEMORY_6_NORMAL 0x16000
+#define SHARE_MEMORY_7_NORMAL 0x17000
+
+/* RAM size */
+#define FLT_PATN_RAM_SIZE 0x0800
+#define FLT_MASK_RAM_SIZE 0x0800
+#define FLT_PIDPATTERN_SIZE 0x0160
+#define SHARE_MEMORY_0_SIZE 0x1000
+#define SHARE_MEMORY_1_SIZE 0x1000
+#define SHARE_MEMORY_2_SIZE 0x1000
+#define SHARE_MEMORY_3_SIZE 0x1000
+#define SHARE_MEMORY_4_SIZE 0x1000
+#define SHARE_MEMORY_5_SIZE 0x1000
+#define SHARE_MEMORY_6_SIZE 0x1000
+#define SHARE_MEMORY_7_SIZE 0x1000
+
+/* CIP SPU Stream */
+#define CIP_S_ID 0x14c0
+#define CIP_S_MODE 0x14c4
+#define CIP_S_CTRL 0x14c8
+#define CIP_S_SIZE 0x14cc
+#define CIP_S_BASE 0x14f8
+#define CIP_DEBUG 0x14fc
+
+/* CIP SPU HDC */
+#define HDC_CTRL 0x1520
+#define HDC_PTS 0x1524
+#define HDC_STAT 0x1528
+#define HDC_SPN_STAT 0x152c
+#define HDC_SPN 0x1530
+#define HDC_PATTERN 0x1534
+#define HDC_RESULT 0x1538
+#define HDC_RESULT_POS 0x153c
+
+/* CIP SPU File */
+#define CIP_F_ID 0x1540
+#define CIP_F_MODE 0x1544
+#define CIP_F_CTRL 0x1548
+#define CIP_F_SKIP 0x154c
+#define CIP_F_PAYLOAD 0x1560
+#define CIP_F_AUX0 0x156c
+#define CIP_F_AUX1 0x1570
+#define CIP_F_AUX2 0x1574
+#define CIP_F_REMAIN 0x1578
+#define CIP_F_EPNVERIFY1 0x157c
+#define CIP_F_EPNVERIFY2 0x1580
+#define CIP_F_EPNCNT 0x1584
+#define CIP_F_PKTCNT 0x1588
+#define CIP_F_STAT 0x1590
+#define CIP_F_SIZE 0x1594
+#define CIP_F_IBUF 0x1598
+#define CIP_F_OBUF 0x159c
+#define CIP_F_BASE 0x15b8
+#define CIP_F_BASEDIVX 0x15bc
+
+/* FLT1 SPU, FLT2 HOST */
+#define FLT_CTRL1 0x15c0
+#define FLT_CTRL2 0x15c4
+#define FLT_CTRL3 0x15c8
+#define FLT_CTRL4 0x15cc
+#define FLT_STATUS 0x15d0
+#define FLT_INTENABLE 0x15d4
+#define FLT_INTSTATUS 0x15d8
+#define FLT_LINE(i) (0x15e0 + (i) * 0x04)
+#define FLT_LENMODE 0x15f8
+#define FLT_LEN 0x15fc
+#define FLT_TRNUM 0x1600
+#define FLT_COUNT1 0x1604
+#define FLT_COUNT2 0x1608
+#define FLT_BUFCOUNT 0x160c
+#define FLT_INBUF(i) (0x1610 + (i) * 0x04)
+#define FLT_CRC 0x1624
+#define FLT_CRCCALC 0x1628
+#define FLT_SECNUM 0x1630
+#define FLT_COMP 0x1634
+#define FLT_SWACE 0x163c
+
+#define FLT_ATR(i) (0x1d00 + (i) * 0x04)
+#define FLT_PIDNUM 0x1d24
+
+/* SBC1, 2 */
+#define SBC_ACE_DMA_EN 0x6000
+#define SBC_DMAPARAM21 0x6004
+#define SBC_ACE_INTREN 0x6008
+#define SBC_ACE_INTRST 0x600c
+#define SBC_DMA_STATUS0 0x6010
+#define SBC_DMA_STATUS1 0x6014
+#define SBC_DMAPARAMA(i) (0x6018 + (i) * 0x04)
+#define SBC_DMAPARAMA_OFFSET_MASK GENMASK(31, 29)
+#define SBC_DMAPARAMA_LOOPADDR_MASK GENMASK(28, 23)
+#define SBC_DMAPARAMA_COUNT_MASK GENMASK(7, 0)
+#define SBC_DMAPARAMB(i) (0x6038 + (i) * 0x04)
+
+#define SBC_INTRENABLE0 0x60a0
+#define SBC_INTRSTATUS0 0x60a4
+#define SBC_INTRENABLE1 0x60a8
+#define SBC_INTRSTATUS1 0x60ac
+
+#define SBC_CONFIG0 0x60c0
+#define SBC_PARREGION0 0x60c4
+#define SBC_PARREGION1 0x60c8
+
+/* IOB1, 2, 3 */
+#define IOB_PKTCNT 0x1740
+#define IOB_PKTCNTRST 0x1744
+#define IOB_PKTCNTST 0x1744
+#define IOB_DUMMY_ENABLE 0x1748
+#define IOB_FORMATCHANGE_EN 0x174c
+#define IOB_UASSIST0 0x1750
+#define IOB_UASSIST1 0x1754
+#define IOB_URESERVE(i) (0x1758 + (i) * 0x4)
+#define IOB_PCRRECEN IOB_URESERVE(2)
+#define IOB_UPARTIAL(i) (0x1768 + (i) * 0x4)
+#define IOB_SPUINTREN 0x1778
+
+#define IOB_HSCREV 0x1a00
+#define IOB_SECCLK(i) (0x1a08 + (i) * 0x6c)
+#define IOB_SECTIMEH(i) (0x1a0c + (i) * 0x6c)
+#define IOB_SECTIMEL(i) (0x1a10 + (i) * 0x6c)
+#define IOB_RESET0 0x1a14
+#define IOB_RESET0_APCORE BIT(20)
+#define IOB_RESET1 0x1a18
+#define IOB_CLKSTOP 0x1a1c
+#define IOB_DEBUG 0x1a20
+#define IOB_DEBUG_SPUHALT BIT(0)
+#define IOB_INTREN(i) (0x1a24 + (i) * 0x8)
+#define IOB_INTRST(i) (0x1a28 + (i) * 0x8)
+#define IOB_INTREN0 0x1a24
+#define IOB_INTRST0 0x1a28
+#define IOB_INTREN0_1 0x1a2c
+#define IOB_INTRST0_1 0x1a30
+#define IOB_INTREN0_2 0x1a34
+#define IOB_INTRST0_2 0x1a38
+#define IOB_INTREN1 0x1a3c
+#define IOB_INTRST1 0x1a40
+#define IOB_INTREN1_1 0x1a44
+#define IOB_INTRST1_1 0x1a48
+#define IOB_INTREN2 0x1a4c
+#define IOB_INTRST2 0x1a50
+#define INTR2_DRV BIT(31)
+#define INTR2_CIP_FRMT(i) BIT((i) + 16)
+#define INTR2_CIP_NORMAL BIT(16)
+#define INTR2_SEC_CLK_A BIT(15)
+#define INTR2_SEC_CLK_S BIT(14)
+#define INTR2_MBC_CIP_W(i) BIT((i) + 9)
+#define INTR2_MBC_CIP_R(i) BIT((i) + 4)
+#define INTR2_CIP_AUTH_A BIT(1)
+#define INTR2_CIP_AUTH_S BIT(0)
+#define IOB_INTREN3 0x1a54
+#define IOB_INTRST3 0x1a58
+#define INTR3_DRV BIT(31)
+#define INTR3_CIP_FRMT(i) BIT((i) + 16)
+#define INTR3_SEC_CLK_A BIT(15)
+#define INTR3_SEC_CLK_S BIT(14)
+#define INTR3_MBC_CIP_W(i) BIT((i) + 9)
+#define INTR3_MBC_CIP_R(i) BIT((i) + 4)
+#define INTR3_CIP_AUTH_A BIT(1)
+#define INTR3_CIP_AUTH_S BIT(0)
+#define IOB_INTREN4 0x1a5c
+#define IOB_INTRST4 0x1a60
+#define IOB_CGCTRL 0x1a64
+#define IOB_VCXOCTL 0x1a68
+#define IOB_IO_ATTRIBUTE 0x1a6c
+
+#define IOB_MONDAT 0x5000
+#define IOB_MONDAT2 0x5004
+#define IOB_TESTMODE 0x5008
+#define IOB_TESTMODE2 0x500c
+#define IOB_DEBUGTCERT 0x5010
+
+/* MBC1-7 Common */
+#define CDMBC_STRT(i) (0x2300 + ((i) - 1) * 0x4)
+#define CDMBC_PERFCNFG 0x230c
+#define CDMBC_STAT(i) (0x2320 + (i) * 0x4)
+#define CDMBC_PARTRESET(i) (0x234c + (i) * 0x4)
+#define CDMBC_MONNUM 0x2358
+#define CDMBC_MONDAT 0x235c
+#define CDMBC_PRC0CHIE0 0x2380
+#define CDMBC_PRC0RBIE0 0x2384
+#define CDMBC_PRC1CHIE0 0x2388
+#define CDMBC_PRC2CHIE0 0x2390
+#define CDMBC_PRC2RBIE0 0x2394
+#define CDMBC_SOFTFLRQ 0x239c
+#define CDMBC_TDSTRT 0x23a0
+
+#define INTR_MBC_CH_END BIT(15)
+#define INTR_MBC_CH_STOP BIT(13)
+#define INTR_MBC_CH_ADDR BIT(6)
+#define INTR_MBC_CH_IWDONE BIT(3)
+#define INTR_MBC_CH_WDONE BIT(1)
+
+/* MBC
+ * i: channel number
+ * 1- 3: Record0,1,2
+ * 19-21: Record3,4,5
+ */
+#define CDMBC_CHTDCTRLH(i) (((i) < 19) ? \
+ (0x23a4 + ((i) - 1) * 0x20) : \
+ (0x23b4 + ((i) - 19) * 0x20))
+#define CDMBC_CHTDCTRLH_STREM_MASK GENMASK(20, 16)
+#define CDMBC_CHTDCTRLH_NOT_FLT BIT(7)
+#define CDMBC_CHTDCTRLH_ALL_EN BIT(6)
+#define CDMBC_CHTDCTRLU(i) (((i) < 19) ? \
+ (0x23a8 + ((i) - 1) * 0x20) : \
+ (0x23b8 + ((i) - 19) * 0x20))
+
+#define CDMBC_TDSTAT 0x23f8
+#define CDMBC_TDIR 0x23fc
+#define CDMBC_REPRATECTRL 0x2400
+#define CDMBC_ATRIBUTE0 0x24e8
+#define CDMBC_ATRIBUTE1 0x24ec
+#define CDMBC_ATRIBUTE2 0x24f0
+#define CDMBC_ATRIBUTE3 0x24f4
+#define CDMBC_ATRIBUTE4 0x24f8
+#define CDMBC_CIPMODE(i) (0x24fc + (i) * 0x4)
+#define CDMBC_CIPMODE_PUSH BIT(0)
+#define CDMBC_CIPPRIORITY(i) (0x2510 + (i) * 0x4)
+#define CDMBC_CIPPRIORITY_PRIOR_MASK GENMASK(1, 0)
+#define CDMBC_CH18ATTRIBUTE (0x2524)
+
+/* MBC Channel
+ * i: channel number
+ * 0 : Section
+ * 1- 3: Record0,1,2
+ * 4 : Partial
+ * 5- 7: Replay0,1,2
+ * 8-17: Even: CIP-Read
+ * Odd : CIP-Write
+ * 18 : AM32
+ * 19-21: Record3,4,5
+ * 22-24: Replay3,4,5
+ */
+#define CDMBC_CHCTRL1(i) (0x2540 + (i) * 0x50)
+#define CDMBC_CHCTRL1_LINKCH1_MASK GENMASK(12, 10)
+#define CDMBC_CHCTRL1_STATSEL_MASK GENMASK(9, 7)
+#define CDMBC_CHCTRL1_TYPE_INTERMIT BIT(1)
+#define CDMBC_CHCTRL1_IND_SIZE_UND BIT(0)
+#define CDMBC_CHCTRL2(i) (0x2544 + (i) * 0x50)
+#define CDMBC_CHDDR(i) (0x2548 + (i) * 0x50)
+#define CDMBC_CHDDR_REG_LOAD_ON BIT(4)
+#define CDMBC_CHDDR_AT_CHEN_ON BIT(3)
+#define CDMBC_CHDDR_SET_MCB_MASK GENMASK(2, 1)
+#define CDMBC_CHDDR_SET_MCB_WR (0x0 << 1)
+#define CDMBC_CHDDR_SET_MCB_RD (0x3 << 1)
+#define CDMBC_CHDDR_SET_DDR_1 BIT(0)
+#define CDMBC_CHCAUSECTRL(i) (0x254c + (i) * 0x50)
+#define CDMBC_CHCAUSECTRL_MODE_MASK BIT(31)
+#define CDMBC_CHCAUSECTRL_CSEL2_MASK GENMASK(20, 12)
+#define CDMBC_CHCAUSECTRL_CSEL1_MASK GENMASK(8, 0)
+#define CDMBC_CHSTAT(i) (0x2550 + (i) * 0x50)
+#define CDMBC_CHIR(i) (0x2554 + (i) * 0x50)
+#define CDMBC_CHIE(i) (0x2558 + (i) * 0x50)
+#define CDMBC_CHID(i) (0x255c + (i) * 0x50)
+#define CDMBC_CHI_STOPPED BIT(13)
+#define CDMBC_CHI_TRANSIT BIT(6)
+#define CDMBC_CHI_STARTING BIT(1)
+#define CDMBC_CHSRCAMODE(i) (0x2560 + (i) * 0x50)
+#define CDMBC_CHDSTAMODE(i) (0x2564 + (i) * 0x50)
+#define CDMBC_CHAMODE_TUNIT_MASK GENMASK(29, 28)
+#define CDMBC_CHAMODE_ENDIAN_MASK GENMASK(17, 16)
+#define CDMBC_CHAMODE_AUPDT_MASK GENMASK(5, 4)
+#define CDMBC_CHAMODE_TYPE_RB BIT(2)
+#define CDMBC_CHSRCSTRTADRSD(i) (0x2568 + (i) * 0x50)
+#define CDMBC_CHSRCSTRTADRSU(i) (0x256c + (i) * 0x50)
+#define CDMBC_CHDSTSTRTADRSD(i) (0x2570 + (i) * 0x50)
+#define CDMBC_CHDSTSTRTADRSU(i) (0x2574 + (i) * 0x50)
+#define CDMBC_CHDSTSTRTADRS_TID_MASK GENMASK(31, 28)
+#define CDMBC_CHDSTSTRTADRS_ID1_EN_MASK BIT(15)
+#define CDMBC_CHDSTSTRTADRS_KEY_ID1_MASK GENMASK(12, 8)
+#define CDMBC_CHDSTSTRTADRS_KEY_ID0_MASK GENMASK(4, 0)
+#define CDMBC_CHSIZE(i) (0x2578 + (i) * 0x50)
+#define CDMBC_CHIRADRSD(i) (0x2580 + (i) * 0x50)
+#define CDMBC_CHIRADRSU(i) (0x2584 + (i) * 0x50)
+#define CDMBC_CHDST1STUSIZE(i) (0x258C + (i) * 0x50)
+
+/* MBC DMA
+ * i: channel number
+ * 5- 7: Replay0,1,2
+ * 8-17: Even: CIP-Read
+ * Odd : CIP-Write
+ * 22-24: Replay3-5
+ */
+static inline int HSC_IT_INT(int i)
+{
+ if (i > 21)
+ return i - 9;
+
+ return i - 5;
+}
+
+#define CDMBC_ITCTRL(i) (0x3000 + HSC_IT_INT(i) * 0x20)
+#define CDMBC_ITSTEPS(i) (0x3018 + HSC_IT_INT(i) * 0x20)
+
+/* MBC Ring buffer
+ * i: channel number
+ * 0 : Section (RB0)
+ * 1- 3: Record0,1,2 (RB1-3)
+ * 5- 7: Replay0,1,2 (RB4-6)
+ * 8-17: Even: CIP-Read
+ * Odd : CIP-Write (RB7-16)
+ * 19-21: Record3-4 (RB17-19)
+ * 22-24: Replay3-4 (RB20-22)
+ */
+static inline int HSC_INT(int i)
+{
+ if (i > 18)
+ return i - 2;
+ if (i > 4)
+ return i - 1;
+
+ return i;
+}
+
+#define CDMBC_RBBGNADRS(i) (0x3200 + HSC_INT(i) * 0x40)
+#define CDMBC_RBBGNADRSD(i) (0x3200 + HSC_INT(i) * 0x40)
+#define CDMBC_RBBGNADRSU(i) (0x3204 + HSC_INT(i) * 0x40)
+#define CDMBC_RBENDADRS(i) (0x3208 + HSC_INT(i) * 0x40)
+#define CDMBC_RBENDADRSD(i) (0x3208 + HSC_INT(i) * 0x40)
+#define CDMBC_RBENDADRSU(i) (0x320C + HSC_INT(i) * 0x40)
+#define CDMBC_RBIR(i) (0x3214 + HSC_INT(i) * 0x40)
+#define CDMBC_RBIE(i) (0x3218 + HSC_INT(i) * 0x40)
+#define CDMBC_RBID(i) (0x321c + HSC_INT(i) * 0x40)
+#define CDMBC_RBRDPTR(i) (0x3220 + HSC_INT(i) * 0x40)
+#define CDMBC_RBRDPTRD(i) (0x3220 + HSC_INT(i) * 0x40)
+#define CDMBC_RBRDPTRU(i) (0x3224 + HSC_INT(i) * 0x40)
+#define CDMBC_RBWRPTR(i) (0x3228 + HSC_INT(i) * 0x40)
+#define CDMBC_RBWRPTRD(i) (0x3228 + HSC_INT(i) * 0x40)
+#define CDMBC_RBWRPTRU(i) (0x322C + HSC_INT(i) * 0x40)
+#define CDMBC_RBERRCNFG(i) (0x3238 + HSC_INT(i) * 0x40)
+
+/* MBC Rate */
+#define CDMBC_RCNMSKCYC(i) (MBC6_TOP_ADDR + 0x000 + (i) * 0x04)
+
+/* MBC Address Transfer */
+#define CDMBC_CHPSIZE(i) (0x3c00 + ((i) - 1) * 0x48)
+#define CDMBC_CHATCTRL(i) (0x3c04 + ((i) - 1) * 0x48)
+#define CDMBC_CHBTPAGE(i, j) (0x3c08 + ((i) - 1) * 0x48 + (j) * 0x10)
+#define CDMBC_CHBTPAGED(i, j) (0x3c08 + ((i) - 1) * 0x48 + (j) * 0x10)
+#define CDMBC_CHBTPAGEU(i, j) (0x3c0C + ((i) - 1) * 0x48 + (j) * 0x10)
+#define CDMBC_CHATPAGE(i, j) (0x3c10 + ((i) - 1) * 0x48 + (j) * 0x10)
+#define CDMBC_CHATPAGED(i, j) (0x3c10 + ((i) - 1) * 0x48 + (j) * 0x10)
+#define CDMBC_CHATPAGEU(i, j) (0x3c14 + ((i) - 1) * 0x48 + (j) * 0x10)
+
+/* CSS */
+#define CSS_PTSOCONFIG 0x1c00
+#define CSS_PTSISIGNALPOL 0x1c04
+#define CSS_SIGNALPOLCH(i) (0x1c08 + (i) * 0x4)
+#define CSS_OUTPUTENABLE 0x1c10
+#define CSS_OUTPUTCTRL(i) (0x1c14 + (i) * 0x4)
+#define CSS_STSOCONFIG 0x1c2c
+#define CSS_STSOSIGNALPOL 0x1c30
+#define CSS_DMDSIGNALPOL 0x1c34
+#define CSS_PTSOSIGNALPOL 0x1c38
+#define CSS_PF0CONFIG 0x1c3c
+#define CSS_PF1CONFIG 0x1c40
+#define CSS_PFINTENABLE 0x1c44
+#define CSS_PFINTSTATUS 0x1c48
+#define CSS_AVOUTPUTCTRL(i) (0x1c4c + (i) * 0x4)
+#define CSS_DPCTRL(i) (0x1c54 + (i) * 0x4)
+#define CSS_DPCTRL_DPSEL_MASK GENMASK(22, 0)
+#define CSS_DPCTRL_DPSEL_PLAY5 BIT(15)
+#define CSS_DPCTRL_DPSEL_PLAY4 BIT(14)
+#define CSS_DPCTRL_DPSEL_PLAY3 BIT(13)
+#define CSS_DPCTRL_DPSEL_PLAY2 BIT(12)
+#define CSS_DPCTRL_DPSEL_PLAY1 BIT(11)
+#define CSS_DPCTRL_DPSEL_PLAY0 BIT(10)
+#define CSS_DPCTRL_DPSEL_TSI4 BIT(4)
+#define CSS_DPCTRL_DPSEL_TSI3 BIT(3)
+#define CSS_DPCTRL_DPSEL_TSI2 BIT(2)
+#define CSS_DPCTRL_DPSEL_TSI1 BIT(1)
+#define CSS_DPCTRL_DPSEL_TSI0 BIT(0)
+
+/* TSI */
+#define TSI_SYNCCNTROL(i) (0x7100 + (i) * 0x70)
+#define TSI_SYNCCNTROL_FRAME_MASK GENMASK(18, 16)
+#define TSI_SYNCCNTROL_FRAME_EXTSYNC1 (0x0 << 16)
+#define TSI_SYNCCNTROL_FRAME_EXTSYNC2 (0x1 << 16)
+#define TSI_CONFIG(i) (0x7104 + (i) * 0x70)
+#define TSI_CONFIG_ATSMD_MASK GENMASK(22, 21)
+#define TSI_CONFIG_ATSMD_PCRPLL0 (0x0 << 21)
+#define TSI_CONFIG_ATSMD_PCRPLL1 (0x1 << 21)
+#define TSI_CONFIG_ATSMD_DPLL (0x3 << 21)
+#define TSI_CONFIG_ATSADD_ON BIT(20)
+#define TSI_CONFIG_STCMD_MASK GENMASK(7, 6)
+#define TSI_CONFIG_STCMD_PCRPLL0 (0x0 << 6)
+#define TSI_CONFIG_STCMD_PCRPLL1 (0x1 << 6)
+#define TSI_CONFIG_STCMD_DPLL (0x3 << 6)
+#define TSI_CONFIG_CHEN_START BIT(0)
+#define TSI_RATEUPLMT(i) (0x7108 + (i) * 0x70)
+#define TSI_RATELOWLMT(i) (0x710c + (i) * 0x70)
+#define TSI_CNTINTR(i) (0x7110 + (i) * 0x70)
+#define TSI_INTREN(i) (0x7114 + (i) * 0x70)
+#define TSI_INTR_NTP BIT(13)
+#define TSI_INTR_NTPCNT BIT(12)
+#define TSI_INTR_PKTEND BIT(11)
+#define TSI_INTR_PCR BIT(9)
+#define TSI_INTR_LOAD BIT(8)
+#define TSI_INTR_SERR BIT(7)
+#define TSI_INTR_SOF BIT(6)
+#define TSI_INTR_TOF BIT(5)
+#define TSI_INTR_UL BIT(4)
+#define TSI_INTR_LL BIT(3)
+#define TSI_INTR_CNT BIT(2)
+#define TSI_INTR_LOST BIT(1)
+#define TSI_INTR_LOCK BIT(0)
+#define TSI_SYNCSTATUS(i) (0x7118 + (i) * 0x70)
+#define TSI_STAT_PKTST_ERR BIT(21)
+#define TSI_STAT_LARGE_ERR BIT(20)
+#define TSI_STAT_SMALL_ERR BIT(19)
+#define TSI_STAT_LOCK BIT(18)
+#define TSI_STAT_SYNC BIT(17)
+#define TSI_STAT_SEARCH BIT(16)
+#define TSI_PCRPID(i) (0x711c + (i) * 0x70)
+#define TSI_PCRCTRL(i) (0x7120 + (i) * 0x70)
+#define TSI_STCBASE(i) (0x7124 + (i) * 0x70)
+#define TSI_STCEXT(i) (0x7128 + (i) * 0x70)
+#define TSI_CURSTC1(i) (0x712c + (i) * 0x70)
+#define TSI_CURSTCBASE(i) (0x712c + (i) * 0x70)
+#define TSI_CURSTC2(i) (0x7130 + (i) * 0x70)
+#define TSI_CURSTCEXT(i) (0x7130 + (i) * 0x70)
+#define TSI_STC2BASE(i) (0x7134 + (i) * 0x70)
+#define TSI_STC2EXT(i) (0x7138 + (i) * 0x70)
+#define TSI_PCRBASE(i) (0x713c + (i) * 0x70)
+#define TSI_PCREXT(i) (0x7140 + (i) * 0x70)
+#define TSI_TIMESTAMP(i) (0x7144 + (i) * 0x70)
+#define TSI_CNTCTRL0(i) (0x7148 + (i) * 0x70)
+#define TSI_CNTCTRL1(i) (0x714c + (i) * 0x70)
+#define TSI_DEBUG(i) (0x7150 + (i) * 0x70)
+
+#define TSI_STCCMPCTRL 0x7000
+#define VCXOSTCBASE(i) (0x7010 + (i) * 0x18)
+#define VCXOSTCEXT(i) (0x7014 + (i) * 0x18)
+#define VCXOCURSTC1(i) (0x7018 + (i) * 0x18)
+#define VCXOCURSTC2(i) (0x701c + (i) * 0x18)
+#define VCXOSTC2BASE(i) (0x7020 + (i) * 0x18)
+#define VCXOSTC2EXT(i) (0x7024 + (i) * 0x18)
+
+/* UCODE DL */
+#define UCODE_REVISION_AM 0x10fd0
+#define CIP_UCODEADDR_AM1 0x10fd4
+#define CIP_UCODEADDR_AM0 0x10fd8
+#define CORRECTATS_CTRL 0x10fdc
+#define UCODE_REVISION 0x10fe0
+#define AM_UCODE_IGPGCTRL 0x10fe4
+#define REPDPLLCTRLEN 0x10fe8
+#define UCODE_DLADDR1 0x10fec
+#define UCODE_DLADDR0 0x10ff0
+#define UCODE_ERRLOGCTRL 0x10ff4
+
+#endif /* DVB_UNIPHIER_HSC_REG_H__ */
diff --git a/drivers/media/platform/uniphier/hsc.h b/drivers/media/platform/uniphier/hsc.h
new file mode 100644
index 000000000000..ad57fea58675
--- /dev/null
+++ b/drivers/media/platform/uniphier/hsc.h
@@ -0,0 +1,480 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Socionext UniPhier DVB driver for High-speed Stream Controller (HSC).
+ *
+ * Copyright (c) 2018 Socionext Inc.
+ */
+
+#ifndef DVB_UNIPHIER_HSC_H__
+#define DVB_UNIPHIER_HSC_H__
+
+#include <linux/gpio/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include <media/dmxdev.h>
+#include <media/dvbdev.h>
+#include <media/dvb_demux.h>
+#include <media/dvb_frontend.h>
+
+enum HSC_CORE {
+ HSC_CORE_0,
+ HSC_CORE_1,
+ HSC_CORE_2,
+};
+
+enum HSC_UCODE {
+ HSC_UCODE_SPU_0,
+ HSC_UCODE_SPU_1,
+ HSC_UCODE_ACE,
+};
+
+enum HSC_INTR_IOB {
+ HSC_INTR_IOB_0,
+ HSC_INTR_IOB_0_1,
+ HSC_INTR_IOB_0_2,
+ HSC_INTR_IOB_1,
+ HSC_INTR_IOB_1_1,
+ HSC_INTR_IOB_2,
+ HSC_INTR_IOB_3,
+ HSC_INTR_IOB_4,
+ HSC_INTR_IOB_5,
+ HSC_INTR_IOB_5_1,
+ HSC_INTR_IOB_5_2,
+ HSC_INTR_IOB_6,
+ HSC_INTR_IOB_6_1,
+ HSC_INTR_IOB_7,
+ HSC_INTR_IOB_8,
+ HSC_INTR_IOB_9,
+
+ HSC_INTR_IOB_NUM,
+};
+
+enum HSC_DPLL {
+ HSC_DPLL0,
+ HSC_DPLL1,
+ HSC_DPLL2,
+ HSC_DPLL3,
+
+ HSC_DPLL_NUM,
+};
+
+enum HSC_DPLL_SRC {
+ HSC_DPLL_SRC_NONE = -1,
+ HSC_DPLL_SRC_TSI0 = 0x00,
+ HSC_DPLL_SRC_TSI1,
+ HSC_DPLL_SRC_TSI2,
+ HSC_DPLL_SRC_TSI3,
+ HSC_DPLL_SRC_TSI4,
+ HSC_DPLL_SRC_TSI5,
+ HSC_DPLL_SRC_TSI6,
+ HSC_DPLL_SRC_TSI7,
+ HSC_DPLL_SRC_TSI8,
+ HSC_DPLL_SRC_TSI9,
+ HSC_DPLL_SRC_REP0 = 0x0a,
+ HSC_DPLL_SRC_REP1,
+ HSC_DPLL_SRC_REP2,
+ HSC_DPLL_SRC_REP3,
+ HSC_DPLL_SRC_REP4,
+ HSC_DPLL_SRC_REP5,
+
+ HSC_DPLL_SRC_NUM,
+};
+
+/* Port to send to CSS */
+enum HSC_CSS_IN {
+ HSC_CSS_IN_1394_0 = 0x00,
+ HSC_CSS_IN_1394_1,
+ HSC_CSS_IN_1394_2,
+ HSC_CSS_IN_1394_3,
+ HSC_CSS_IN_DMD0 = 0x04,
+ HSC_CSS_IN_DMD1,
+ HSC_CSS_IN_SRLTS0 = 0x06,
+ HSC_CSS_IN_SRLTS1,
+ HSC_CSS_IN_SRLTS2,
+ HSC_CSS_IN_SRLTS3,
+ HSC_CSS_IN_SRLTS4,
+ HSC_CSS_IN_SRLTS5,
+ HSC_CSS_IN_SRLTS6,
+ HSC_CSS_IN_SRLTS7,
+ HSC_CSS_IN_PARTS0 = 0x10,
+ HSC_CSS_IN_PARTS1,
+ HSC_CSS_IN_PARTS2,
+ HSC_CSS_IN_PARTS3,
+ HSC_CSS_IN_TSO0 = 0x18,
+ HSC_CSS_IN_TSO1,
+ HSC_CSS_IN_TSO2,
+ HSC_CSS_IN_TSO3,
+ HSC_CSS_IN_ENCORDER0_IN = 0x1c,
+ HSC_CSS_IN_ENCORDER1_IN,
+
+ HSC_CSS_IN_NUM,
+};
+
+/* Port to receive from CSS */
+enum HSC_CSS_OUT {
+ HSC_CSS_OUT_SRLTS0 = 0x00,
+ HSC_CSS_OUT_SRLTS1,
+ HSC_CSS_OUT_SRLTS2,
+ HSC_CSS_OUT_SRLTS3,
+ HSC_CSS_OUT_TSI0 = 0x04,
+ HSC_CSS_OUT_TSI1,
+ HSC_CSS_OUT_TSI2,
+ HSC_CSS_OUT_TSI3,
+ HSC_CSS_OUT_TSI4,
+ HSC_CSS_OUT_TSI5,
+ HSC_CSS_OUT_TSI6,
+ HSC_CSS_OUT_TSI7,
+ HSC_CSS_OUT_TSI8,
+ HSC_CSS_OUT_TSI9,
+ HSC_CSS_OUT_PARTS0 = 0x10,
+ HSC_CSS_OUT_PARTS1,
+ HSC_CSS_OUT_PKTFF0 = 0x14,
+ HSC_CSS_OUT_PKTFF1,
+};
+
+/* TS input interface */
+enum HSC_TS_IN {
+ HSC_TSI0,
+ HSC_TSI1,
+ HSC_TSI2,
+ HSC_TSI3,
+ HSC_TSI4,
+ HSC_TSI5,
+ HSC_TSI6,
+ HSC_TSI7,
+ HSC_TSI8,
+ HSC_TSI9,
+
+ HSC_TS_IN_NUM,
+};
+
+/* TS output interface */
+enum HSC_TS_OUT {
+ HSC_TS_OUT0,
+ HSC_TS_OUT1,
+ HSC_TS_OUT2,
+ HSC_TS_OUT3,
+ HSC_TS_OUT4,
+ HSC_TS_OUT5,
+ HSC_TS_OUT6,
+ HSC_TS_OUT7,
+ HSC_TS_OUT8,
+ HSC_TS_OUT9,
+
+ HSC_TS_OUT_NUM,
+};
+
+/* DMA to read from memory (Replay DMA) */
+enum HSC_DMA_IN {
+ HSC_DMA_IN0,
+ HSC_DMA_IN1,
+ HSC_DMA_IN2,
+ HSC_DMA_IN3,
+ HSC_DMA_IN4,
+ HSC_DMA_IN5,
+ HSC_DMA_IN6,
+ HSC_DMA_IN7,
+ HSC_DMA_IN8,
+ HSC_DMA_IN9,
+
+ HSC_DMA_IN_NUM,
+};
+
+/* DMA to write to memory (Record DMA) */
+enum HSC_DMA_OUT {
+ HSC_DMA_OUT0,
+ HSC_DMA_OUT1,
+ HSC_DMA_OUT2,
+ HSC_DMA_OUT3,
+ HSC_DMA_OUT4,
+ HSC_DMA_OUT5,
+ HSC_DMA_OUT6,
+ HSC_DMA_OUT7,
+ HSC_DMA_OUT8,
+ HSC_DMA_OUT9,
+
+ HSC_DMA_OUT_NUM,
+};
+
+enum HSC_TSIF_FMT {
+ HSC_TSIF_MPEG2_TS,
+ HSC_TSIF_MPEG2_TS_ATS,
+};
+
+#define HSC_STREAM_IF_NUM 2
+
+#define HSC_DMAIF_TS_BUFSIZE (192 * 1024 * 5)
+
+#define HSC_MBC_DMCH_REC0 1
+#define HSC_MBC_DMCH_REC1 2
+#define HSC_MBC_DMCH_REC2 3
+#define HSC_MBC_DMCH_REP0 5
+#define HSC_MBC_DMCH_REP1 6
+#define HSC_MBC_DMCH_REP2 7
+#define HSC_MBC_DMCH_CIP0_R 8
+#define HSC_MBC_DMCH_CIP0_W 9
+#define HSC_MBC_DMCH_CIP1_R 10
+#define HSC_MBC_DMCH_CIP1_W 11
+#define HSC_MBC_DMCH_CIP2_R 12
+#define HSC_MBC_DMCH_CIP2_W 13
+#define HSC_MBC_DMCH_CIP3_R 14
+#define HSC_MBC_DMCH_CIP3_W 15
+#define HSC_MBC_DMCH_CIP4_R 16
+#define HSC_MBC_DMCH_CIP4_W 17
+#define HSC_MBC_DMCH_REC3 19
+#define HSC_MBC_DMCH_REC4 20
+#define HSC_MBC_DMCH_REC5 21
+#define HSC_MBC_DMCH_REP3 22
+#define HSC_MBC_DMCH_REP4 23
+#define HSC_MBC_DMCH_REP5 24
+
+struct hsc_ucode_buf {
+ void *buf_code;
+ dma_addr_t phys_code;
+ size_t size_code;
+ void *buf_data;
+ dma_addr_t phys_data;
+ size_t size_data;
+};
+
+struct hsc_spec_ucode {
+ const char *name_code;
+ const char *name_data;
+};
+
+struct hsc_spec_init_ram {
+ u32 addr;
+ size_t size;
+ u32 pattern;
+};
+
+struct hsc_css_pol {
+ int valid;
+ u32 reg;
+ int sft_sync;
+ int sft_val;
+ int sft_clk;
+};
+
+struct hsc_css_sel {
+ int valid;
+ u32 reg;
+ u32 mask;
+};
+
+struct hsc_spec_css_in {
+ struct hsc_css_pol pol;
+};
+
+struct hsc_spec_css_out {
+ struct hsc_css_pol pol;
+ struct hsc_css_sel sel;
+};
+
+struct hsc_cmn_intr {
+ int valid;
+ u32 reg;
+ int sft_intr;
+};
+
+struct hsc_spec_ts {
+ struct hsc_cmn_intr intr;
+};
+
+struct hsc_dma_en {
+ int valid;
+ u32 reg;
+ int sft_toggle;
+};
+
+struct hsc_spec_dma {
+ int dma_ch;
+ struct hsc_dma_en en;
+ struct hsc_cmn_intr intr;
+};
+
+struct hsc_spec {
+ const struct hsc_spec_ucode ucode_spu;
+ const struct hsc_spec_ucode ucode_ace;
+ const struct hsc_spec_init_ram *init_rams;
+ size_t num_init_rams;
+ const struct hsc_spec_css_in *css_in;
+ size_t num_css_in;
+ const struct hsc_spec_css_out *css_out;
+ size_t num_css_out;
+ const struct hsc_spec_ts *ts_in;
+ size_t num_ts_in;
+ const struct hsc_spec_dma *dma_in;
+ size_t num_dma_in;
+ const struct hsc_spec_dma *dma_out;
+ size_t num_dma_out;
+};
+
+struct hsc_tsif {
+ struct hsc_chip *chip;
+
+ struct dvb_adapter adapter;
+ struct dvb_demux demux;
+ struct dmxdev dmxdev;
+ struct dvb_frontend *fe;
+ int valid_adapter;
+ int valid_demux;
+ int valid_dmxdev;
+ int valid_fe;
+
+ enum HSC_CSS_IN css_in;
+ enum HSC_CSS_OUT css_out;
+ enum HSC_TS_IN tsi;
+ enum HSC_DPLL dpll;
+ enum HSC_DPLL_SRC dpll_src;
+ struct hsc_dmaif *dmaif;
+
+ int running;
+ struct delayed_work recover_work;
+ unsigned long recover_delay;
+};
+
+struct hsc_dma_in {
+ struct hsc_chip *chip;
+
+ enum HSC_DMA_IN id;
+ const struct hsc_spec_dma *spec;
+ struct hsc_dma_buf *buf;
+};
+
+struct hsc_dma_out {
+ struct hsc_chip *chip;
+
+ enum HSC_DMA_OUT id;
+ const struct hsc_spec_dma *spec;
+ struct hsc_dma_buf *buf;
+};
+
+struct hsc_dma_buf {
+ void *virt;
+ dma_addr_t phys;
+ u64 size;
+ u64 size_chk;
+ u64 rd_offs;
+ u64 wr_offs;
+ u64 chk_offs;
+};
+
+struct hsc_dmaif {
+ struct hsc_chip *chip;
+
+ struct hsc_dma_buf buf_out;
+ struct hsc_dma_out dma_out;
+
+ struct hsc_tsif *tsif;
+
+ /* guard read/write pointer of DMA buffer from interrupt handler */
+ spinlock_t lock;
+ int running;
+ struct work_struct feed_work;
+};
+
+struct hsc_chip {
+ const struct hsc_spec *spec;
+ short *adapter_nums;
+
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct clk *clk_stdmac;
+ struct clk *clk_hsc;
+ struct reset_control *rst_stdmac;
+ struct reset_control *rst_hsc;
+
+ struct hsc_dmaif dmaif[HSC_STREAM_IF_NUM];
+ struct hsc_tsif tsif[HSC_STREAM_IF_NUM];
+
+ struct hsc_ucode_buf ucode_spu;
+ struct hsc_ucode_buf ucode_am;
+};
+
+struct hsc_conf {
+ enum HSC_CSS_IN css_in;
+ enum HSC_CSS_OUT css_out;
+ enum HSC_DPLL dpll;
+ enum HSC_DMA_OUT dma_out;
+};
+
+static inline u32 field_prep(u32 mask, u32 v)
+{
+ int sft = ffs(mask) - 1;
+
+ return (v << sft) & mask;
+}
+
+static inline u32 field_get(u32 mask, u32 v)
+{
+ int sft = ffs(mask) - 1;
+
+ return (v & mask) >> sft;
+}
+
+/* CSS */
+enum HSC_TS_IN hsc_css_out_to_ts_in(enum HSC_CSS_OUT out);
+enum HSC_DPLL_SRC hsc_css_out_to_dpll_src(enum HSC_CSS_OUT out);
+
+int hsc_dpll_get_src(struct hsc_chip *chip, enum HSC_DPLL dpll,
+ enum HSC_DPLL_SRC *src);
+int hsc_dpll_set_src(struct hsc_chip *chip, enum HSC_DPLL dpll,
+ enum HSC_DPLL_SRC src);
+int hsc_css_in_get_polarity(struct hsc_chip *chip, enum HSC_CSS_IN in,
+ bool *sync_bit, bool *val_bit, bool *clk_fall);
+int hsc_css_in_set_polarity(struct hsc_chip *chip, enum HSC_CSS_IN in,
+ bool sync_bit, bool val_bit, bool clk_fall);
+int hsc_css_out_get_polarity(struct hsc_chip *chip, enum HSC_CSS_OUT out,
+ bool *sync_bit, bool *val_bit, bool *clk_fall);
+int hsc_css_out_set_polarity(struct hsc_chip *chip, enum HSC_CSS_OUT out,
+ bool sync_bit, bool val_bit, bool clk_fall);
+int hsc_css_out_get_src(struct hsc_chip *chip, enum HSC_CSS_IN *in,
+ enum HSC_CSS_OUT out, bool *en);
+int hsc_css_out_set_src(struct hsc_chip *chip, enum HSC_CSS_IN in,
+ enum HSC_CSS_OUT out, bool en);
+
+/* TSI */
+const struct hsc_spec_tsi *hsc_ts_in_get_spec(struct hsc_chip *chip,
+ enum HSC_TS_IN in);
+int hsc_ts_in_set_enable(struct hsc_chip *chip, enum HSC_TS_IN in, bool en);
+int hsc_ts_in_set_dmaparam(struct hsc_chip *chip, enum HSC_TS_IN in,
+ enum HSC_TSIF_FMT ifmt);
+
+/* DMA */
+u64 hsc_rb_cnt(struct hsc_dma_buf *buf);
+u64 hsc_rb_cnt_to_end(struct hsc_dma_buf *buf);
+u64 hsc_rb_space(struct hsc_dma_buf *buf);
+u64 hsc_rb_space_to_end(struct hsc_dma_buf *buf);
+int hsc_dma_in_init(struct hsc_dma_in *dma_in, struct hsc_chip *chip,
+ enum HSC_DMA_IN in, struct hsc_dma_buf *buf);
+void hsc_dma_in_start(struct hsc_dma_in *dma_in, bool en);
+void hsc_dma_in_sync(struct hsc_dma_in *dma_in);
+int hsc_dma_in_get_intr(struct hsc_dma_in *dma_in, u32 *stat);
+void hsc_dma_in_clear_intr(struct hsc_dma_in *dma_in, u32 clear);
+int hsc_dma_out_init(struct hsc_dma_out *dma_out, struct hsc_chip *chip,
+ enum HSC_DMA_OUT out, struct hsc_dma_buf *buf);
+void hsc_dma_out_set_src_ts_in(struct hsc_dma_out *dma_out,
+ enum HSC_TS_IN ts_in);
+void hsc_dma_out_start(struct hsc_dma_out *dma_out, bool en);
+void hsc_dma_out_sync(struct hsc_dma_out *dma_out);
+int hsc_dma_out_get_intr(struct hsc_dma_out *dma_out, u32 *stat);
+void hsc_dma_out_clear_intr(struct hsc_dma_out *dma_out, u32 clear);
+
+/* UCODE DL */
+int hsc_ucode_load_all(struct hsc_chip *chip);
+int hsc_ucode_unload_all(struct hsc_chip *chip);
+
+/* For Adapter */
+int hsc_register_dvb(struct hsc_tsif *tsif);
+void hsc_unregister_dvb(struct hsc_tsif *tsif);
+int hsc_tsif_init(struct hsc_tsif *tsif, const struct hsc_conf *conf);
+void hsc_tsif_release(struct hsc_tsif *tsif);
+int hsc_dmaif_init(struct hsc_dmaif *dmaif, const struct hsc_conf *conf);
+void hsc_dmaif_release(struct hsc_dmaif *dmaif);
+extern const struct hsc_spec uniphier_hsc_ld11_spec;
+extern const struct hsc_spec uniphier_hsc_ld20_spec;
+
+#endif /* DVB_UNIPHIER_HSC_H__ */
--
2.17.0
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