* [PATCH V2 2/2] ARM: dts: imx6ul: add GPIO clocks
From: Fabio Estevam @ 2018-06-03 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527990245-13619-2-git-send-email-Anson.Huang@nxp.com>
On Sat, Jun 2, 2018 at 10:44 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6UL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH V2 1/3] ARM: imx: add L2 page power control for GPC
From: Fabio Estevam @ 2018-06-03 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527993226-19587-1-git-send-email-Anson.Huang@nxp.com>
On Sat, Jun 2, 2018 at 11:33 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Some platforms like i.MX6UL/i.MX6SLL have L2
> page power control in GPC, it needs to be
> disabled if ARM is power gated and L2 is NOT
> flushed, add GPC interface to control it.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH] ARM: pxa: zylonite: use the new ac97 bus support
From: Robert Jarzmik @ 2018-06-03 20:17 UTC (permalink / raw)
To: linux-arm-kernel
Now the PXA is converted to new ac97 bus support, the wm9713 is
automatically detected and probed. Remove it from the platform bus.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
arch/arm/mach-pxa/zylonite.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index d69de312d8d9..52e70a5c1281 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -47,16 +47,6 @@ int wm9713_irq;
int lcd_id;
int lcd_orientation;
-struct platform_device pxa_device_wm9713_audio = {
- .name = "wm9713-codec",
- .id = -1,
-};
-
-static void __init zylonite_init_wm9713_audio(void)
-{
- platform_device_register(&pxa_device_wm9713_audio);
-}
-
static struct resource smc91x_resources[] = {
[0] = {
.start = ZYLONITE_ETH_PHYS + 0x300,
@@ -428,7 +418,6 @@ static void __init zylonite_init(void)
zylonite_init_nand();
zylonite_init_leds();
zylonite_init_ohci();
- zylonite_init_wm9713_audio();
}
MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
--
2.11.0
^ permalink raw reply related
* [PATCH] ARM: pxa: add the missing AC97 clocks
From: Robert Jarzmik @ 2018-06-03 20:15 UTC (permalink / raw)
To: linux-arm-kernel
The AC97 bit clock is added as the pxa internally generated 13MHz
clock. This is a consequence of the new ac97 framework.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
arch/arm/mach-pxa/devices.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 5a16ea74e28a..a24783a03827 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -3,6 +3,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/clkdev.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/spi/pxa2xx_spi.h>
@@ -477,6 +478,18 @@ struct platform_device pxa_device_ac97 = {
void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
{
+ int ret;
+
+ ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:0", "AC97CLK",
+ &pxa_device_ac97.dev);
+ if (ret)
+ pr_err("PXA AC97 clock1 alias error: %d\n", ret);
+
+ ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:1", "AC97CLK",
+ &pxa_device_ac97.dev);
+ if (ret)
+ pr_err("PXA AC97 clock2 alias error: %d\n", ret);
+
pxa_register_device(&pxa_device_ac97, ops);
}
--
2.11.0
^ permalink raw reply related
* [PATCH v9] ASoC: pxa: switch to new ac97 bus support
From: Robert Jarzmik @ 2018-06-03 20:12 UTC (permalink / raw)
To: linux-arm-kernel
Switch to the new ac97 bus support in sound/ac97 instead of the legacy
snd_ac97 one.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
---
Since v8: fixed the trivial compilation error
v7 was in https://patchwork.kernel.org/patch/9951919/
---
sound/arm/Kconfig | 1 -
sound/soc/pxa/Kconfig | 5 ++---
sound/soc/pxa/pxa2xx-ac97.c | 48 +++++++++++++++++++++++----------------------
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig
index 65171f6657a2..f1f25704fe52 100644
--- a/sound/arm/Kconfig
+++ b/sound/arm/Kconfig
@@ -36,7 +36,6 @@ endif # SND_ARM
config SND_PXA2XX_LIB
tristate
- select SND_AC97_CODEC if SND_PXA2XX_LIB_AC97
select SND_DMAENGINE_PCM
config SND_PXA2XX_LIB_AC97
diff --git a/sound/soc/pxa/Kconfig b/sound/soc/pxa/Kconfig
index 484ab3c2ad67..1a0b55beb282 100644
--- a/sound/soc/pxa/Kconfig
+++ b/sound/soc/pxa/Kconfig
@@ -20,13 +20,12 @@ config SND_MMP_SOC
config SND_PXA2XX_AC97
tristate
- select SND_AC97_CODEC
config SND_PXA2XX_SOC_AC97
tristate
- select AC97_BUS
+ select AC97_BUS_NEW
select SND_PXA2XX_LIB_AC97
- select SND_SOC_AC97_BUS
+ select SND_SOC_AC97_BUS_NEW
config SND_PXA2XX_SOC_I2S
tristate
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 1b41c0f2a8fb..80e4757176d8 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -17,6 +17,7 @@
#include <linux/dmaengine.h>
#include <linux/dma/pxa-dma.h>
+#include <sound/ac97/controller.h>
#include <sound/core.h>
#include <sound/ac97_codec.h>
#include <sound/soc.h>
@@ -27,43 +28,35 @@
#include <mach/regs-ac97.h>
#include <mach/audio.h>
-static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
+static void pxa2xx_ac97_warm_reset(struct ac97_controller *adrv)
{
pxa2xx_ac97_try_warm_reset();
pxa2xx_ac97_finish_reset();
}
-static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
+static void pxa2xx_ac97_cold_reset(struct ac97_controller *adrv)
{
pxa2xx_ac97_try_cold_reset();
pxa2xx_ac97_finish_reset();
}
-static unsigned short pxa2xx_ac97_legacy_read(struct snd_ac97 *ac97,
- unsigned short reg)
+static int pxa2xx_ac97_read_actrl(struct ac97_controller *adrv, int slot,
+ unsigned short reg)
{
- int ret;
-
- ret = pxa2xx_ac97_read(ac97->num, reg);
- if (ret < 0)
- return 0;
- else
- return (unsigned short)(ret & 0xffff);
+ return pxa2xx_ac97_read(slot, reg);
}
-static void pxa2xx_ac97_legacy_write(struct snd_ac97 *ac97,
- unsigned short reg, unsigned short val)
+static int pxa2xx_ac97_write_actrl(struct ac97_controller *adrv, int slot,
+ unsigned short reg, unsigned short val)
{
- int ret;
-
- ret = pxa2xx_ac97_write(ac97->num, reg, val);
+ return pxa2xx_ac97_write(slot, reg, val);
}
-static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
- .read = pxa2xx_ac97_legacy_read,
- .write = pxa2xx_ac97_legacy_write,
+static struct ac97_controller_ops pxa2xx_ac97_ops = {
+ .read = pxa2xx_ac97_read_actrl,
+ .write = pxa2xx_ac97_write_actrl,
.warm_reset = pxa2xx_ac97_warm_reset,
.reset = pxa2xx_ac97_cold_reset,
};
@@ -219,6 +212,9 @@ static const struct snd_soc_component_driver pxa_ac97_component = {
static int pxa2xx_ac97_dev_probe(struct platform_device *pdev)
{
int ret;
+ struct ac97_controller *ctrl;
+ pxa2xx_audio_ops_t *pdata = pdev->dev.platform_data;
+ void **codecs_pdata;
if (pdev->id != -1) {
dev_err(&pdev->dev, "PXA2xx has only one AC97 port.\n");
@@ -231,10 +227,14 @@ static int pxa2xx_ac97_dev_probe(struct platform_device *pdev)
return ret;
}
- ret = snd_soc_set_ac97_ops(&pxa2xx_ac97_ops);
- if (ret != 0)
- return ret;
+ codecs_pdata = pdata ? pdata->codec_pdata : NULL;
+ ctrl = snd_ac97_controller_register(&pxa2xx_ac97_ops, &pdev->dev,
+ AC97_SLOTS_AVAILABLE_ALL,
+ codecs_pdata);
+ if (IS_ERR(ctrl))
+ return PTR_ERR(ctrl);
+ platform_set_drvdata(pdev, ctrl);
/* Punt most of the init to the SoC probe; we may need the machine
* driver to do interesting things with the clocking to get us up
* and running.
@@ -245,8 +245,10 @@ static int pxa2xx_ac97_dev_probe(struct platform_device *pdev)
static int pxa2xx_ac97_dev_remove(struct platform_device *pdev)
{
+ struct ac97_controller *ctrl = platform_get_drvdata(pdev);
+
snd_soc_unregister_component(&pdev->dev);
- snd_soc_set_ac97_ops(NULL);
+ snd_ac97_controller_unregister(ctrl);
pxa2xx_ac97_hw_remove(pdev);
return 0;
}
--
2.11.0
^ permalink raw reply related
* [PATCH 3/3] pinctrl: actions: Add interrupt support for OWL S900 SoC
From: Manivannan Sadhasivam @ 2018-06-03 16:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHp75Ve8ZCbEqnYK0KqtCHQm-EOUWRSyMzi51P+3_7brtXq6dA@mail.gmail.com>
Hi Andy,
On Sun, Jun 03, 2018 at 11:37:53AM +0300, Andy Shevchenko wrote:
> On Sat, Jun 2, 2018 at 7:54 PM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > Add interrupt support for Actions Semi OWL S900 SoC.
>
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> At which circumstances the above possible?
>
Only possible when the requested GPIO exceeds chip->ngpio. I know it is
a kind of redundant check, but it is good to have this during development.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> Ditto.
>
Same as above.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return;
>
> Ditto.
>
Same as above.
> > + port = owl_gpio_get_port(pctrl, &gpio);
> > + if (WARN_ON(port == NULL))
> > + return -ENODEV;
>
> Ditto.
>
Same as above.
>
> > + for (i = 0; i < chip->ngpio; i++) {
> > + irqno = irq_create_mapping(pctrl->domain, i);
> > + irq_set_chip_and_handler(irqno, &owl_gpio_irq_chip,
> > + handle_edge_irq);
> > + irq_set_chip_data(irqno, pctrl);
> > + }
>
> I'm not sure the handle_edge_irq() is a correct handler here. It would
> be handle_bad_irq() until IRQ has been requested properly.
> No?
>
Hmmm, good question. Since the handler used in irq_set_chip_and_handler
is superseded by irq_set_chained_handler_and_data, this doesn't matter
anyway. But I would like to hear what Linus suggests here!
> > +/* GPIO TYPE Bit Definition */
> > +#define OWL_GPIO_INT_LEVEL_HIGH 0
> > +#define OWL_GPIO_INT_LEVEL_LOW 1
> > +#define OWL_GPIO_INT_EDGE_RISING 2
> > +#define OWL_GPIO_INT_EDGE_FALLING 3
>
> > +#define OWL_GPIO_INT_MASK 3
>
> GENMASK?
>
Ack.
Thanks,
Mani
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply
* Common config for N900 and D4
From: Pavel Machek @ 2018-06-03 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180603104839.GA21197@amd>
Hi!
> Aaro, I know I have asked before, but if you have common config for
> N900 and Droid4, please send me a copy. Yes, it should be somewhere in
> my inbox already, but I can't find it and version for v4.17 would be
> more useful.
>
> While trying to came up with common config, I hit:
>
> [ 0.000000] L2C-310 erratum 727915 enabled
> [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
> [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
I tried disabling outer cache to get rid of this. That got me further
in boot, but not to working system:
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq0_ck!
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq1_ck!
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq2_ck!
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq3_ck!
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq4_ck!
[ 0.000000] ti_clk_get_reg_addr: clk-provider not found for
auxclkreq5_ck!
[ 0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles:
0xfffffffs
[ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns,
wraps every 6s
[ 3.105895] OMAP clocksource: 32k_counter at 32768 Hz
[ 3.111541] Unable to handle kernel NULL pointer dereference at
virtual addr0
[ 3.111541] pgd = (ptrval)
[ 3.122650] [00000000] *pgd=00000000
[ 3.122650] Internal error: Oops: 80000005 [#1] SMP ARM
[ 3.131683] Modules linked in:
[ 3.134826] CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.17.0-rc7-75535-g2a545
[ 3.143310] Hardware name: Generic DT based system
[ 3.143310] PC is at (null)
[ 3.143310] LR is at __irq_svc+0x6c/0x90
[ 3.143310] pc : [<00000000>] lr : [<c0101a2c>] psr: 20000193
[ 3.155303] sp : c0d01f70 ip : 00000002 fp : 00000000
[ 3.155303] r10: 00000001 r9 : c0d00000 r8 : ef7d2a00
[ 3.172424] r7 : c0d01fa4 r6 : ffffffff r5 : 20000013 r4 :
c0c00b78
[ 3.172424] r3 : c01d2db8 r2 : c0d01fc0 r1 : c0d0f678 r0 :
c0d01f70
[ 3.172424] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment noe
[ 3.193206] Control: 10c5387d Table: 8000404a DAC: 00000051
[ 3.199096] Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
[ 3.205261] Stack: (0xc0d01f70 to 0xc0d02000)
[ 3.205261] 1f60: 00000000
00000000 00000
[ 3.205261] 1f80: 00000000 ffffffff c0d50040 c0c358d4 ef7d2a00
411fc093 00000
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* [PATCH 7/7] staging: mt7621-pci: fix coding style error
From: Abdun Nihaal @ 2018-06-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: that open brace { should be on the previous line
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 510aa633589a..96cae1e1838b 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -663,8 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if ((RALINK_PCI0_STATUS & 0x1) == 0)
- {
+ if ((RALINK_PCI0_STATUS & 0x1) == 0) {
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
@@ -675,8 +674,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if ((RALINK_PCI1_STATUS & 0x1) == 0)
- {
+ if ((RALINK_PCI1_STATUS & 0x1) == 0) {
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
--
2.17.0
^ permalink raw reply related
* [PATCH 6/7] staging: mt7621-pci: add space after '==' symbol
From: Abdun Nihaal @ 2018-06-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: spaces required around that '==' (ctx:WxV)
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 3bd715a4b139..510aa633589a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -417,13 +417,13 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x0)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x1)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
- } else if ((dev->bus->number ==3) && (slot == 0x2)) {
+ } else if ((dev->bus->number == 3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else {
--
2.17.0
^ permalink raw reply related
* [PATCH 5/7] staging: mt7621-pci: add spaces around equal symbol
From: Abdun Nihaal @ 2018-06-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: spaces required around that '=' (ctx:VxW)
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index f347eaf9063c..3bd715a4b139 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -308,7 +308,7 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
}
}
-struct pci_ops mt7621_pci_ops= {
+struct pci_ops mt7621_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};
@@ -584,8 +584,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
unsigned long val = 0;
iomem_resource.start = 0;
- iomem_resource.end= ~0;
- ioport_resource.start= 0;
+ iomem_resource.end = ~0;
+ ioport_resource.start = 0;
ioport_resource.end = ~0;
#if defined (CONFIG_PCIE_PORT0)
--
2.17.0
^ permalink raw reply related
* [PATCH 4/7] staging: mt7621-pci: add space after comma symbol
From: Abdun Nihaal @ 2018-06-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This patch fixes the following checkpatch error:
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 36 ++++++++++++-------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 28b9a11e9ecb..f347eaf9063c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -373,17 +373,17 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 0 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
} else if ((dev->bus->number == 1) && (slot == 0x0)) {
switch (pcie_link_status) {
case 2:
@@ -396,7 +396,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE0;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x0)) {
switch (pcie_link_status) {
case 5:
@@ -406,7 +406,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE1;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x1)) {
switch (pcie_link_status) {
case 5:
@@ -416,18 +416,18 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
default:
irq = RALINK_INT_PCIE1;
}
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
- printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
+ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n", dev->bus->number, slot, dev->irq);
} else {
- printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
+ printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
return 0;
}
@@ -501,10 +501,10 @@ set_phy_for_ssc(void)
if (reg >= 6) {
printk("***** Xtal 25MHz *****\n");
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
} else {
printk("***** Xtal 20MHz *****\n");
}
@@ -539,10 +539,10 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) { // 25MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
--
2.17.0
^ permalink raw reply related
* [PATCH 3/7] staging: mt7621-pci: add space before open parenthesis
From: Abdun Nihaal @ 2018-06-03 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: space required before the open parenthesis '('
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++++++++++++-------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index fbcee58445b3..28b9a11e9ecb 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -155,13 +155,13 @@ extern void chk_phy_pll(void);
RALINK_RSTCTRL |= val; \
else \
RALINK_RSTCTRL &= ~val; \
- } while(0)
+ } while (0)
#define DEASSERT_SYSRST_PCIE(val) do { \
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
RALINK_RSTCTRL &= ~val; \
else \
RALINK_RSTCTRL |= val; \
- } while(0)
+ } while (0)
#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
@@ -210,7 +210,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
MV_WRITE(address_reg, address);
- switch(access_type) {
+ switch (access_type) {
case PCI_ACCESS_WRITE_1:
MV_WRITE_8(data_reg+(where&0x3), *data);
break;
@@ -374,12 +374,12 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0@slot 0 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
- } else if((dev->bus->number == 0) && (slot == 0x1)) {
+ } else if ((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
- } else if((dev->bus->number == 0) && (slot == 0x2)) {
+ } else if ((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
@@ -493,7 +493,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal
@@ -516,7 +516,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
@@ -533,7 +533,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
} else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
@@ -552,7 +552,7 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if(reg <= 5 && reg >= 3) { // 40MHz Xtal
+ if (reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
@@ -663,7 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if((RALINK_PCI0_STATUS & 0x1) == 0)
+ if ((RALINK_PCI0_STATUS & 0x1) == 0)
{
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
@@ -675,7 +675,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if((RALINK_PCI1_STATUS & 0x1) == 0)
+ if ((RALINK_PCI1_STATUS & 0x1) == 0)
{
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
@@ -711,7 +711,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
3'b110 1 0 x
3'b111 2 1 0
*/
- switch(pcie_link_status) {
+ switch (pcie_link_status) {
case 2:
RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
@@ -749,7 +749,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
#if defined (CONFIG_PCIE_PORT0)
//PCIe0
- if((pcie_link_status & 0x1) != 0) {
+ if ((pcie_link_status & 0x1) != 0) {
RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
RALINK_PCI0_CLASS = 0x06040001;
@@ -776,7 +776,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
#endif
- switch(pcie_link_status) {
+ switch (pcie_link_status) {
case 7:
read_config(0, 2, 0, 0x4, &val);
write_config(0, 2, 0, 0x4, val|0x4);
--
2.17.0
^ permalink raw reply related
* [PATCH 2/7] staging: mt7621-pci: remove trailing whitespace
From: Abdun Nihaal @ 2018-06-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: trailing whitespace
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 32 ++++++++++++-------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 44f1a592a7a5..fbcee58445b3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -498,7 +498,7 @@ set_phy_for_ssc(void)
printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- if (reg >= 6) {
+ if (reg >= 6) {
printk("***** Xtal 25MHz *****\n");
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
@@ -510,15 +510,15 @@ set_phy_for_ssc(void)
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
@@ -546,15 +546,15 @@ set_phy_for_ssc(void)
}
}
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
@@ -650,7 +650,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCIE_CLK_GEN |= 0x80000000;
mdelay(50);
RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
-
+
#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
--
2.17.0
^ permalink raw reply related
* [PATCH 1/7] staging: mt7621-pci: Remove space after open parenthesis
From: Abdun Nihaal @ 2018-06-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1528040188.git.abdun.nihaal@gmail.com>
This fixes the following checkpatch error:
ERROR: space prohibited after that open parenthesis '('
Signed-off-by: Abdun Nihaal <abdun.nihaal@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1fa41eb8a87f..44f1a592a7a5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -221,7 +221,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
MV_WRITE(data_reg, *data);
break;
case PCI_ACCESS_READ_1:
- MV_READ_8( data_reg+(where&0x3), data);
+ MV_READ_8(data_reg+(where&0x3), data);
break;
case PCI_ACCESS_READ_2:
MV_READ_16(data_reg+(where&0x3), data);
@@ -663,7 +663,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(500);
#if defined (CONFIG_PCIE_PORT0)
- if(( RALINK_PCI0_STATUS & 0x1) == 0)
+ if((RALINK_PCI0_STATUS & 0x1) == 0)
{
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
@@ -675,7 +675,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT1)
- if(( RALINK_PCI1_STATUS & 0x1) == 0)
+ if((RALINK_PCI1_STATUS & 0x1) == 0)
{
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
@@ -687,7 +687,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
}
#endif
#if defined (CONFIG_PCIE_PORT2)
- if (( RALINK_PCI2_STATUS & 0x1) == 0) {
+ if ((RALINK_PCI2_STATUS & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
--
2.17.0
^ permalink raw reply related
* [PATCH 0/7] staging: mt7621-pci: Fix coding style issues
From: Abdun Nihaal @ 2018-06-03 15:59 UTC (permalink / raw)
To: linux-arm-kernel
This patchset fixes the following set of coding style
issues found using checkpatch.
ERROR: space prohibited after that open parenthesis '('
ERROR: trailing whitespace
ERROR: space required before the open parenthesis '('
ERROR: space required after that ',' (ctx:VxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '==' (ctx:WxV)
ERROR: that open brace { should be on the previous line
Abdun Nihaal (7):
staging: mt7621-pci: Remove space after open parenthesis
staging: mt7621-pci: remove trailing whitespace
staging: mt7621-pci: add space before open parenthesis
staging: mt7621-pci: add space after comma symbol
staging: mt7621-pci: add spaces around equal symbol
staging: mt7621-pci: add space after '==' symbol
staging: mt7621-pci: fix coding style error
drivers/staging/mt7621-pci/pci-mt7621.c | 114 ++++++++++++------------
1 file changed, 56 insertions(+), 58 deletions(-)
--
2.17.0
^ permalink raw reply
* [PATCH 1/4] clk: imx6q: remove clks_init_on array
From: Fabio Estevam @ 2018-06-03 12:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2D554312-36F2-4781-899C-8D9F5BD20B46@nxp.com>
Hi Anson,
On Sun, Jun 3, 2018 at 9:48 AM, Anson Huang <anson.huang@nxp.com> wrote:
> As I explain in previous mail, busy divider clk type already include the flag when registered.
Ok, then please add this information in the commit log to make the
review process easier.
^ permalink raw reply
* [PATCH 3/4] clk: imx6sx: remove clks_init_on array
From: Fabio Estevam @ 2018-06-03 12:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527994847-2363-3-git-send-email-Anson.Huang@nxp.com>
On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Clock framework will enable those clocks registered
> with CLK_IS_CRITICAL flag, so no need to have
> clks_init_on array during clock initialization now.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx6sx.c | 40 ++++++++++++++--------------------------
> 1 file changed, 14 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
> index 10c771b..aed4391 100644
> --- a/drivers/clk/imx/clk-imx6sx.c
> +++ b/drivers/clk/imx/clk-imx6sx.c
> @@ -92,14 +92,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
> static struct clk *clks[IMX6SX_CLK_CLK_END];
> static struct clk_onecell_data clk_data;
>
> -static int const clks_init_on[] __initconst = {
> - IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
> - IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
> - IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
> - IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
> - IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,
> -};
MX6SX_CLK_ARM and IMX6SX_CLK_IPG did not have the CLK_IS_CRITICAL flag.
Is this on purpose?
^ permalink raw reply
* [PATCH 1/4] clk: imx6q: remove clks_init_on array
From: Anson Huang @ 2018-06-03 12:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5CmgBsaaegVV9OjdyXv5_O0V9iTS2qYbtuH26qkG2_zrA@mail.gmail.com>
Hi, Fabio
>From Anson's iPhone 6
> ? 2018?6?3??20:44?Fabio Estevam <festevam@gmail.com> ???
>
>> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
>> Clock framework will enable those clocks registered
>> with CLK_IS_CRITICAL flag, so no need to have
>> clks_init_on array during clock initialization now.
>>
>> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
>> ---
>> drivers/clk/imx/clk-imx6q.c | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
>> index b9ea703..8754c61 100644
>> --- a/drivers/clk/imx/clk-imx6q.c
>> +++ b/drivers/clk/imx/clk-imx6q.c
>> @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
>> static struct clk *clk[IMX6QDL_CLK_END];
>> static struct clk_onecell_data clk_data;
>>
>> -static unsigned int const clks_init_on[] __initconst = {
>> - IMX6QDL_CLK_MMDC_CH0_AXI,
>> - IMX6QDL_CLK_ROM,
>> - IMX6QDL_CLK_ARM,
>
> IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag.
>
> Is this intended? If so, please mention in the commit log.
As I explain in previous mail, busy divider clk type already include the flag when registered.
Anson.
^ permalink raw reply
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array
From: Anson Huang @ 2018-06-03 12:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5Af_Wdp=MNR28v3ALiguxQSQv4x2Zf224FXSiEGtP68Bw@mail.gmail.com>
Hi, Fabio
>From Anson's iPhone 6
> ? 2018?6?3??20:17?Fabio Estevam <festevam@gmail.com> ???
>
> Hi Anson,
>
>> On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
>> Clock framework will enable those clocks registered
>> with CLK_IS_CRITICAL flag, so no need to have
>> clks_init_on array during clock initialization now.
>>
>> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
>> ---
>> drivers/clk/imx/clk-imx6sl.c | 12 ------------
>> 1 file changed, 12 deletions(-)
>>
>> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
>> index 66b1dd1..eb6bcbf 100644
>> --- a/drivers/clk/imx/clk-imx6sl.c
>> +++ b/drivers/clk/imx/clk-imx6sl.c
>> @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data;
>> static void __iomem *ccm_base;
>> static void __iomem *anatop_base;
>>
>> -static const u32 clks_init_on[] __initconst = {
>> - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
>> -};
>
> It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks.
The ARM and mmdc root are busy divider, the CLK_IS_CRITICAL flag is included by default when busy divider is registered. IPG?parent is AHB which is also a busy divider. And IPG itself has no gate, no need to add flag.
Anson.
^ permalink raw reply
* [PATCH 1/4] clk: imx6q: remove clks_init_on array
From: Fabio Estevam @ 2018-06-03 12:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527994847-2363-1-git-send-email-Anson.Huang@nxp.com>
On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Clock framework will enable those clocks registered
> with CLK_IS_CRITICAL flag, so no need to have
> clks_init_on array during clock initialization now.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx6q.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index b9ea703..8754c61 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -96,12 +96,6 @@ static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
> static struct clk *clk[IMX6QDL_CLK_END];
> static struct clk_onecell_data clk_data;
>
> -static unsigned int const clks_init_on[] __initconst = {
> - IMX6QDL_CLK_MMDC_CH0_AXI,
> - IMX6QDL_CLK_ROM,
> - IMX6QDL_CLK_ARM,
IMX6QDL_CLK_ARM does not have the CLK_IS_CRITICAL flag.
Is this intended? If so, please mention in the commit log.
^ permalink raw reply
* [PATCH 2/4] clk: imx6sl: remove clks_init_on array
From: Fabio Estevam @ 2018-06-03 12:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527994847-2363-2-git-send-email-Anson.Huang@nxp.com>
Hi Anson,
On Sun, Jun 3, 2018 at 12:00 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Clock framework will enable those clocks registered
> with CLK_IS_CRITICAL flag, so no need to have
> clks_init_on array during clock initialization now.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> drivers/clk/imx/clk-imx6sl.c | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
> index 66b1dd1..eb6bcbf 100644
> --- a/drivers/clk/imx/clk-imx6sl.c
> +++ b/drivers/clk/imx/clk-imx6sl.c
> @@ -104,10 +104,6 @@ static struct clk_onecell_data clk_data;
> static void __iomem *ccm_base;
> static void __iomem *anatop_base;
>
> -static const u32 clks_init_on[] __initconst = {
> - IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
> -};
It looks like you missed to pass the CLK_IS_CRITICAL flag to these clocks.
^ permalink raw reply
* Common config for N900 and D4
From: Pavel Machek @ 2018-06-03 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
Aaro, I know I have asked before, but if you have common config for
N900 and Droid4, please send me a copy. Yes, it should be somewhere in
my inbox already, but I can't find it and version for v4.17 would be
more useful.
While trying to came up with common config, I hit:
[ 0.000000] L2C-310 erratum 727915 enabled
[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
[ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[ 0.000000] Unhandled fault: imprecise external abort (0xc06) at
0x01f9d31c
[ 0.000000] pgd = (ptrval)
[ 0.000000] [01f9d31c] *pgd=00000000
[ 0.000000] Internal error: : c06 [#1] ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
4.17.0-rc7-75534-g9416de8-\
dirty #692
[ 0.000000] Hardware name: Generic DT based system
[ 0.000000] PC is at l2c310_configure+0x38/0x160
[ 0.000000] LR is at l2c310_configure+0x10/0x160
[ 0.000000] pc : [<c0116168>] lr : [<c0116140>] psr: 60000093
[ 0.000000] sp : c0d01ec0 ip : 00000001 fp : 00000000
[ 0.000000] r10: c0c0674c r9 : 00000000 r8 : 00000000
[ 0.000000] r7 : 00000008 r6 : c0b4a030 r5 : c0d50f4c r4 :
f0800000
[ 0.000000] r3 : 00000000 r2 : 00000000 r1 : 00000008 r0 :
00000000
[ 0.000000] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM
Segment none
[ 0.000000] Control: 10c5387d Table: 80004059 DAC: 00000051
[ 0.000000] Process swapper (pid: 0, stack limit = 0x(ptrval))
[ 0.000000] Stack: (0xc0d01ec0 to 0xc0d02000)
[ 0.000000] 1ec0: f0800000 c0d50f4c c0b4a030 c0115f54 c0d50f4c
f0800000 5e470001 00000004
Which sounds like kernel bug. I was running Droid 4 in !CONFIG_SMP
configuration by mistake, maybe that has something to do with it. I'll
try to investigate more.
Best regards
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [PATCH 3/3] pinctrl: actions: Add interrupt support for OWL S900 SoC
From: Andy Shevchenko @ 2018-06-03 8:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180602165415.30956-4-manivannan.sadhasivam@linaro.org>
On Sat, Jun 2, 2018 at 7:54 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add interrupt support for Actions Semi OWL S900 SoC.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
At which circumstances the above possible?
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
Ditto.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return;
Ditto.
> + port = owl_gpio_get_port(pctrl, &gpio);
> + if (WARN_ON(port == NULL))
> + return -ENODEV;
Ditto.
> + for (i = 0; i < chip->ngpio; i++) {
> + irqno = irq_create_mapping(pctrl->domain, i);
> + irq_set_chip_and_handler(irqno, &owl_gpio_irq_chip,
> + handle_edge_irq);
> + irq_set_chip_data(irqno, pctrl);
> + }
I'm not sure the handle_edge_irq() is a correct handler here. It would
be handle_bad_irq() until IRQ has been requested properly.
No?
> +/* GPIO TYPE Bit Definition */
> +#define OWL_GPIO_INT_LEVEL_HIGH 0
> +#define OWL_GPIO_INT_LEVEL_LOW 1
> +#define OWL_GPIO_INT_EDGE_RISING 2
> +#define OWL_GPIO_INT_EDGE_FALLING 3
> +#define OWL_GPIO_INT_MASK 3
GENMASK?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* 答复: [PATCH v10 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
From: liwei (CM) @ 2018-06-03 7:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180525091712.37227-1-liwei213@huawei.com>
Hi, all
Sorry to bother you. Anybody else have any comments?
Hi, Philippe
This patch has been submitted for a long time, can it be merged?
Reviews and tests for previous versions of the patch are as follows:
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Riku Voipio <riku.voipio@linaro.org>
Thank you all for your attention and look forward to your reply.
Thanks!
-----????-----
???: liwei (CM)
????: 2018?5?25? 17:17
???: robh+dt at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com; will.deacon at arm.com; vinholikatti at gmail.com; jejb at linux.vnet.ibm.com; martin.petersen at oracle.com; khilman at baylibre.com; arnd at arndb.de; gregory.clement at free-electrons.com; thomas.petazzoni at free-electrons.com; yamada.masahiro at socionext.com; riku.voipio at linaro.org; treding at nvidia.com; krzk at kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-scsi at vger.kernel.org
??: zangleigang; Gengjianfeng; guodong.xu at linaro.org; Chenfeng (puck); john.stultz at linaro.org; liwei (CM); Fengbaopeng (kevin, Kirin Solution Dept)
??: [PATCH v10 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board.
Li Wei (5):
scsi: ufs: add Hisilicon ufs driver code
dt-bindings: scsi: ufs: add document for hisi-ufs
arm64: dts: add ufs dts node
arm64: defconfig: enable configs for Hisilicon ufs
arm64: defconfig: enable f2fs and squashfs
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 41 ++
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 +-
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 18 +
arch/arm64/configs/defconfig | 11 +
drivers/scsi/ufs/Kconfig | 9 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-hisi.c | 619 +++++++++++++++++++++
drivers/scsi/ufs/ufs-hisi.h | 115 ++++
8 files changed, 821 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
create mode 100644 drivers/scsi/ufs/ufs-hisi.c
create mode 100644 drivers/scsi/ufs/ufs-hisi.h
Major changes in v10:
- solve review comments from Rob Herring.
*Modify the "reset-names" describe in ufs-hisi.txt binding file.
*List clocks in ufs-hisi.txt binding file.
*remove the "arst" and keep only "rst" in the binging files.
*remove the "arst" member from both dts and c code.
Major changes in v9:
- solve review comments from Rob Herring.
*remove freq-table-hz in ufs-hisi.txt binding file.
*Move the rst to the ufshcd_pltfm.txt common binding file.
*Modify the member "assert" of UFS host structure to "arst".
Major changes in v8:
- solve review comments from zhangfei.
*Add Version history.
- solve review comments from Rob Herring.
*remove freq-table-hz.
- solve review comments from Riku Voipio.
*Add MODULE_DEVICE_TABLE for ufs driver.
--
Major changes in v7:
- solve review comments from Philippe Ombredanne.
*use the new SPDX license ids instead of the GNU General Public License.
--
2.15.0
^ permalink raw reply
* [PATCH 4/4] clk: imx6ul: remove clks_init_on array
From: Anson Huang @ 2018-06-03 3:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527994847-2363-1-git-send-email-Anson.Huang@nxp.com>
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
This patch is based on "[V2,1/2] clk: imx6ul: add GPIO clock gates".
drivers/clk/imx/clk-imx6ul.c | 23 ++++++-----------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 3ea2d97..d3f7f4d 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", };
static struct clk *clks[IMX6UL_CLK_END];
static struct clk_onecell_data clk_data;
-static int const clks_init_on[] __initconst = {
- IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
- IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
- IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
-};
-
static const struct clk_div_table clk_enet_ref_table[] = {
{ .val = 0, .div = 20, },
{ .val = 1, .div = 10, },
@@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
- int i;
clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
/* CCGR0 */
- clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
- clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
+ clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
+ clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4);
clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
@@ -412,9 +405,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
- clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
- clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
- clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28);
+ clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
+ clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
+ clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", base + 0x74, 28, CLK_IS_CRITICAL);
/* CCGR4 */
clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12);
@@ -428,7 +421,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30);
/* CCGR5 */
- clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
+ clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", base + 0x7c, 8);
clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
@@ -502,10 +495,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
- /* keep all the clks on just for bringup */
- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
- clk_prepare_enable(clks[clks_init_on[i]]);
-
if (clk_on_imx6ull())
clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]);
--
2.7.4
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