* [PATCH v3 0/3] serial: xuartps: hardware race condition and cleanup
From: Helmut Grohne @ 2018-06-04 10:21 UTC (permalink / raw)
To: linux-arm-kernel
The character transmission in xuartps is racy. If the transmitter is disabled
early, the device is confused and produces a desync. Garbage on the remote end
can be a visible symptom. The second patch in this series tries to reduce that
race condition in accordance with the hardware documentation, but it cannot
remove it entirely. The first and third patches are code cleanup.
Changes since v2:
* Do not attempt to disable the transmitter after a transmission (original
behaviour around 3.14). These patches no longer touch with the transmitter
state at all as requested by S?ren Brinkmann.
* Add Acked-by/Reviewed-by tags from S?ren Brinkmann after addressing his
remarks.
Earlier patches/discussion at:
https://www.spinics.net/lists/linux-serial/msg23145.html
https://www.spinics.net/lists/linux-serial/msg23156.html
https://www.spinics.net/lists/linux-serial/msg23157.html
Helmut Grohne (3):
serial: xuartps: fix typo in cdns_uart_startup
serial: xuartps: reduce hardware TX race condition
serial: xuartps: remove unnecessary register write
drivers/tty/serial/xilinx_uartps.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH 0/2] Use SPDX-License-Identifier for rockchip devicetree files
From: Heiko Stuebner @ 2018-06-04 10:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215114427.32059-1-klaus.goger@theobroma-systems.com>
Am Freitag, 15. Dezember 2017, 12:44:25 CEST schrieb Klaus Goger:
> This patch series replaces all the license text in rockchip devicetree
> files text with a proper SPDX-License-Identifier.
> It follows the guidelines submitted[1] by Thomas Gleixner that are not
> yet merged.
>
> These series also fixes the issue with contradicting statements in most
> licenses. The introduction text claims to be GPL or X11[2] but the
> following verbatim copy of the license is actually a MIT[3] license.
> The X11 license includes a advertise clause and trademark information
> related to the X Consortium. As these X Consortium specfic points are
> irrelevant for us we stick with the actuall license text.
>
> [1] https://patchwork.kernel.org/patch/10091607/
> [2] https://spdx.org/licenses/X11.html
> [3] https://spdx.org/licenses/MIT.html
>
>
> Klaus Goger (2):
> arm64: dts: rockchip: use SPDX-License-Identifier
> ARM: dts: rockchip: use SPDX-License-Identifier
This had now 6 months for anybody concerned about this change to speak
up - with no NACKs received, so I've applied both patches for 4.19
Heiko
^ permalink raw reply
* [PATCH 0/2] Use SPDX-License-Identifier for rockchip devicetree files
From: Heiko Stuebner @ 2018-06-04 10:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD=FV=WA44n8MYtGZTQN3r0F86E=xDcdWhQDLDOkyqS=aaCXfQ@mail.gmail.com>
Am Freitag, 15. Dezember 2017, 18:29:02 CEST schrieb Doug Anderson:
> Hi,
>
> On Fri, Dec 15, 2017 at 3:44 AM, Klaus Goger
> <klaus.goger@theobroma-systems.com> wrote:
> > This patch series replaces all the license text in rockchip devicetree
> > files text with a proper SPDX-License-Identifier.
> > It follows the guidelines submitted[1] by Thomas Gleixner that are not
> > yet merged.
> >
> > These series also fixes the issue with contradicting statements in most
> > licenses. The introduction text claims to be GPL or X11[2] but the
> > following verbatim copy of the license is actually a MIT[3] license.
> > The X11 license includes a advertise clause and trademark information
> > related to the X Consortium. As these X Consortium specfic points are
> > irrelevant for us we stick with the actuall license text.
> >
> > [1] https://patchwork.kernel.org/patch/10091607/
> > [2] https://spdx.org/licenses/X11.html
> > [3] https://spdx.org/licenses/MIT.html
> >
> >
> > Klaus Goger (2):
> > arm64: dts: rockchip: use SPDX-License-Identifier
> > ARM: dts: rockchip: use SPDX-License-Identifier
> >
> > arch/arm/boot/dts/rk3036-evb.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3036-kylin.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3036.dtsi | 40 +---------------------
> > arch/arm/boot/dts/rk3066a-bqcurie2.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3066a-marsboard.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3066a-mk808.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3066a-rayeager.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3066a.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3188-px3-evb.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3188-radxarock.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3188.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3228-evb.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3229-evb.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3229.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk322x.dtsi | 40 +---------------------
> > arch/arm/boot/dts/rk3288-evb-act8846.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3288-evb-rk808.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3288-evb.dtsi | 40 +---------------------
> > arch/arm/boot/dts/rk3288-fennec.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3288-firefly-beta.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-firefly-reload.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-firefly.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-firefly.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-miqi.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-phycore-rdk.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-phycore-som.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-popmetal.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-r89.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-rock2-som.dtsi | 40 +---------------------
> > arch/arm/boot/dts/rk3288-rock2-square.dts | 40 +---------------------
> > arch/arm/boot/dts/rk3288-tinker.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi | 5 +--
> > arch/arm/boot/dts/rk3288-veyron-brain.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-jaq.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-jerry.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-mickey.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-minnie.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-pinky.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron-speedy.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288-veyron.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rk3288-vyasa.dts | 39 +--------------------
> > arch/arm/boot/dts/rk3288.dtsi | 40 +---------------------
> > arch/arm/boot/dts/rk3xxx.dtsi | 39 +--------------------
> > arch/arm/boot/dts/rv1108-evb.dts | 40 +---------------------
> > arch/arm/boot/dts/rv1108.dtsi | 40 +---------------------
> > arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 39 +--------------------
> > .../arm64/boot/dts/rockchip/rk3368-evb-act8846.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts | 39 +--------------------
> > .../boot/dts/rockchip/rk3368-orion-r68-meta.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 39 +--------------------
> > .../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 39 +--------------------
> > .../dts/rockchip/rk3399-sapphire-excavator.dts | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 39 +--------------------
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 39 +--------------------
> > 69 files changed, 69 insertions(+), 2603 deletions(-)
>
> This is just removing the verbatim license text and adding a link to
> another file with the text? ...and correcting the name of the
> alternate license to be the MIT license... I'm no lawyer, but if
> that's what everyone in the kernel agrees is the way they want it
> going forward then I have no objections to anything I was involved in.
correct.
Documentation/process/license-rules.rst Describes the process of
handling these license identifiers.
There was one criticism in the beginning, that an arbitary third-party
site would hold the binding license texts, but that got resolved by
including LICENSES/preferred/$identifier into the kernel sources itself.
Heiko
^ permalink raw reply
* [PATCH 0/6] ARM: shmobile: rcar: Drop lehacy SYSC fallbacks
From: Simon Horman @ 2018-06-04 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527693916-11215-1-git-send-email-geert+renesas@glider.be>
On Wed, May 30, 2018 at 05:25:10PM +0200, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> When DT SYSC support was introduced in v4.7, legacy fallbacks were kept
> to keep secondary CPUs working on R-Car H1, H2, and M2-W using old DTBs.
> However, the time has come to drop these fallbacks, and clean up the
> resulting code.
>
> Most of this was written when I worked on DT SYSC support, but postponed
> until the time was ripe. So basically I've been running this during the
> last +2 years.
>
> I avoided touching drivers/soc/renesas and arch/arm/mach-shmobile code
> in the same patch. If you prefer some patches to be squashed, please
> let me know.
>
> Tested on Marzen (R-Car H1), Lager (R-Car H2), and Koelsch (R-Car M2-W).
>
> Thanks!
>
> Geert Uytterhoeven (6):
> ARM: shmobile: rcar-gen2: Remove explicit SYSC config and init
> ARM: shmobile: r8a7779: Stop powering down secondary CPUs during early
> boot
> soc: renesas: rcar-sysc: Provide helpers to power up/down CPUs
> ARM: shmobile: r8a7779: Use rcar_sysc_power_{down,up}_cpu()
> ARM: shmobile: r8a7779: Remove explicit SYSC config and init
> soc: renesas: rcar-sysc: Drop legacy handling
>
> arch/arm/mach-shmobile/Makefile | 2 +-
> arch/arm/mach-shmobile/pm-r8a7779.c | 41 ----------------------
> arch/arm/mach-shmobile/pm-rcar-gen2.c | 25 --------------
> arch/arm/mach-shmobile/r8a7779.h | 2 --
> arch/arm/mach-shmobile/smp-r8a7779.c | 54 ++++-------------------------
> drivers/soc/renesas/rcar-sysc.c | 64 ++++++++++++++++++++++-------------
> include/linux/soc/renesas/rcar-sysc.h | 13 ++-----
> 7 files changed, 50 insertions(+), 151 deletions(-)
> delete mode 100644 arch/arm/mach-shmobile/pm-r8a7779.c
Thanks, I have applied this and intend to push shortly.
I had a conflict in the Makefile when applying patch 5/6.
Please check to make sure I applied that patch correctly.
^ permalink raw reply
* [PATCH] KVM: arm64: VHE: Migrate _elx sysreg accessors to msr_s/mrs_s
From: Dave Martin @ 2018-06-04 10:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180601094224.ctyvafybcnzys6f4@salmiak>
On Fri, Jun 01, 2018 at 10:42:24AM +0100, Mark Rutland wrote:
> Hi,
>
> On Tue, May 29, 2018 at 03:20:47PM +0100, Dave Martin wrote:
> > Currently, the {read,write}_sysreg_el*() accessors for accessing
> > particular ELs' sysregs in the presence of VHE rely on some local
> > hacks and define their system register encodings in a way that is
> > inconsistent with the core definitions in <asm/sysreg.h>.
> >
> > As a result, it is necessary to add duplicate definitions for any
> > system register that already needs a definition in sysreg.h for
> > other reasons.
> >
> > This is a bit of a maintenance headache, and the reasons for the
> > _el*() accessors working the way they do is a bit historical.
> >
> > This patch gets rid of the shadow sysreg definitions in
> > <asm/kvm_hyp.h>, converts the _el*() accessors to use the core
> > msr_s/mrs_s interface, and converts all call sites to use the
> > standard sysreg #define names (i.e., upper case, with SYS_ prefix).
>
> Nice!
>
> [...]
>
> > static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
> > {
> > if (vcpu->arch.sysregs_loaded_on_cpu)
> > - return read_sysreg_el1(elr);
> > + return read_sysreg_el1(SYS_ELR);
>
> Could we have the macro implicitly handle the SYS_ prefix?
>
> A further bit of cleanup that I'd like to do is make {read,write}_sysreg() use
> {mrs,msr}_s, implicitly handling the SYS_ prefix, so that we can kill off
> {read,write}_sysreg_s(), and always use a {read,write}_sysreg().
>
> A minor pain point is that we'd have to convert callers to pass the sysreg name
> in upper-case, but that conversion can be scripted fairly easily.
>
> e.g. for the above, read_sysreg() would take ELR_EL1, and read_sysreg_el1()
> would take ELR.
Ideally yes.
I will bear that in mind for the next iteration, but I hadn't figured
out how to solve the whole problem yet. I'll see if I can push a bit
further in that direction.
Cheers
---Dave
^ permalink raw reply
* [PATCH v7 0/9] Add support for SAMA5D2 touchscreen
From: Jonathan Cameron @ 2018-06-04 10:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <45ff713b-7811-22c6-2124-4fbcad59b7e8@microchip.com>
On 4 June 2018 07:15:57 BST, Eugen Hristev <eugen.hristev@microchip.com> wrote:
>
>
>On 22.05.2018 20:57, Jonathan Cameron wrote:
>> On Tue, 22 May 2018 10:52:30 +0300
>> Eugen Hristev <eugen.hristev@microchip.com> wrote:
>>
>>> Hello,
>>>
>>> This patch series is a rework of my previous series named:
>>> [PATCH 00/14] iio: triggers: add consumer support
>>>
>>> This is the version 7 of the series, and addresses the received
>feedback
>>> on the v2 series named:
>>> [PATCH v2 00/10] Add support for SAMA5D2 touchscreen
>>> and the v3 series named
>>> [PATCH v3 00/11] Add support for SAMA5D2 touchscreen
>>> and the v4 series named
>>> [PATCH v4 0/9] Add support for SAMA5D2 touchscreen
>>> and fixes one bug found in series named
>>> [PATCH v5 0/9] Add support for SAMA5D2 touchscreen
>>> and addresses comments in series named
>>> [PATCH v6 0/9] Add support for SAMA5D2 touchscreen
>>>
>>> This series applies on top of fixes-togreg branch of iio.git,
>>> specifically on top of commit:
>>> "f0c8d1f" : iio: adc: at91-sama5d2_adc:
>>> fix channel configuration for differential channels
>>>
>>> Jonathan, if you need me to rebase this on top of testing, let me
>know.
>>>
>>> Changes in previous versions are presented at the end of the cover
>letter below.
>>> Thanks everyone for the feedback. Below is the original v2 cover
>letter:
>>>
>>> In few words, this is the implementation of splitting the
>functionality
>>> of the IP block ADC device in SAMA5D2 SoC from ADC with touchscreen
>>> support. In order to avoid having a MFD device, two separate
>>> drivers that would work on same register base and split the IRQ,etc,
>>> as advised on the mailing list, I created a consumer driver for the
>>> channels, that will connect to the ADC as described in the device
>tree.
>>>
>>> I have collected feedback from everyone and here is the result:
>>> I have added a new generic resistive touchscreen driver, which acts
>>> as a iio consumer for the given channels and will create an input
>>> device and report the events. It uses a callback buffer to register
>>> to the IIO device and waits for data to be pushed.
>>> Inside the IIO device, I have kept a similar approach with the first
>version
>>> of the series, except that now the driver can take multiple buffers,
>and
>>> will configure the touchscreen part of the hardware device if the
>specific
>>> channels are requested.
>>>
>>> The SAMA5D2 ADC driver registers three new channels: two for the
>>> position on the X and Y axis, and one for the touch pressure.
>>> When channels are requested, it will check if the touchscreen
>channel mask
>>> includes the requested channels (it is possible that the consumer
>driver
>>> will not request pressure for example). If it's the case, it will
>work
>>> in touchscreen mode, and will refuse to do usual analog-digital
>conversion,
>>> because we have a single trigger and the touchscreen needs it.
>>> When the scan mask will include only old channels, the driver will
>function
>>> in the same way as before. If the scan mask somehow is a mix of the
>two (the
>>> masks intersect), the driver will refuse to work whatsoever (cannot
>have both
>>> in the same time).
>>> The driver allows reading raw data for the new channels, if claim
>direct
>>> mode works: no touchscreen driver requested anything. The new
>channels can
>>> act like the old ones. However, when requesting these channels, the
>usual
>>> trigger will not work and will not be enabled. The touchscreen
>channels
>>> require special trigger and irq configuration: pen detect, no pen
>detect
>>> and a periodic trigger to sample the touchscreen position and
>pressure.
>>> If the user attempts to use another trigger while there is a buffer
>>> that already requested the touchscreen channels (thus the trigger),
>the
>>> driver will refuse to comply.
>>>
>>> In order to have defines for the channel numbers, I added a bindings
>include
>>> file that goes on a separate commit :
>>> dt-bindings: iio: adc: at91-sama5d2_adc: add channel specific
>consumer info
>>> This should go in the same tree with the following commits :
>>> ARM: dts: at91: sama5d2: add channel cells for ADC device
>>> ARM: dts: at91: sama5d2: Add resistive touch device
>>>
>>> as build will break because these commits depend on the binding one
>>> which creates the included header file.
>>> V5 update: After discussing with Alexandre Belloni on Mailing list,
>the two
>>> DTS patches are to be taken in the next version after bindings reach
>mainline.
>>>
>>> Changes in v7:
>>> - Addressed some feedback from Dmitry, explained in input driver
>patch
>>> changelog.
>>> - Added Acked-by Dmitry.
>>>
>>> Changes in v6:
>>> - Fixed a crash in ADC driver , explained in driver patch
>changelog.
>>> - changed a dev_err to dev_dbg in input driver.
>>> - added Reviewed-by Rob Herring.
>>>
>>> Changes in v5:
>>> - renamed property touchscreen-threshold-pressure to
>touchscreen-min-pressure
>>> - added one return in touchscreen driver
>>>
>>> Changes in v4:
>>> - removed patch for inkern module get/set kref
>>> - addressed feedback on both the ADC and the touchscreen driver.
>each
>>> patch has a history inside the patch file for the specific changes.
>>> - patch that fixes the channel fix
>>> [PATCH v3 01/11] iio: adc: at91-sama5d2_adc:
>>> fix channel configuration for differential channels
>>> was accepted in fixes-togreg branch thus removed from this series.
>>> - added Reviewed-by for the bindings by Rob Herring
>>>
>>> Changes in v3:
>>> - changed input driver name according to feedback and reworked in
>commits
>>> to adapt to binding changes and new name.
>>> - moved channel index fix in at91-sama5d2_adc at the beginning of
>the series
>>> (PATCH 01/11)
>>> - created a new optional binding for the touchscreen as a separate
>commit
>>> and added it to the series :
>>> [PATCH v3 04/11] dt-bindings: input: touchscreen: add pressure
>>> threshold touchscreen property
>>> - changed at91-sama5d2_adc driver patch to address the comments.
>Exact changes
>>> are in the patch file for the driver source file.
>>>
>>> Eugen Hristev (9):
>>> MAINTAINERS: add generic resistive touchscreen adc
>>> iio: Add channel for Position Relative
>>> dt-bindings: input: touchscreen: add minimum pressure touchscreen
>>> property
>>> dt-bindings: input: touchscreen: resistive-adc-touch: create
>bindings
>>> iio: adc: at91-sama5d2_adc: add support for position and pressure
>>> channels
>>> input: touchscreen: resistive-adc-touch: add generic resistive
>ADC
>>> touchscreen
>>> dt-bindings: iio: adc: at91-sama5d2_adc: add channel specific
>consumer
>>> info
>>> ARM: dts: at91: sama5d2: add channel cells for ADC device
>>> ARM: dts: at91: sama5d2: Add resistive touch device
>>>
>>> Documentation/ABI/testing/sysfs-bus-iio | 12 +
>>> .../bindings/iio/adc/at91-sama5d2_adc.txt | 9 +
>>> .../input/touchscreen/resistive-adc-touch.txt | 30 +
>>> .../bindings/input/touchscreen/touchscreen.txt | 3 +
>>> MAINTAINERS | 6 +
>>> arch/arm/boot/dts/sama5d2.dtsi | 12 +
>>> drivers/iio/adc/at91-sama5d2_adc.c | 609
>+++++++++++++++++++--
>>> drivers/iio/industrialio-core.c | 1 +
>>> drivers/input/touchscreen/Kconfig | 13 +
>>> drivers/input/touchscreen/Makefile | 1 +
>>> drivers/input/touchscreen/resistive-adc-touch.c | 204 +++++++
>>> include/dt-bindings/iio/adc/at91-sama5d2_adc.h | 16 +
>>> include/uapi/linux/iio/types.h | 1 +
>>> tools/iio/iio_event_monitor.c | 2 +
>>> 14 files changed, 861 insertions(+), 58 deletions(-)
>>> create mode 100644
>Documentation/devicetree/bindings/input/touchscreen/resistive-adc-touch.txt
>>> create mode 100644 drivers/input/touchscreen/resistive-adc-touch.c
>>> create mode 100644 include/dt-bindings/iio/adc/at91-sama5d2_adc.h
>>>
>>
>> Hi All,
>>
>> I'm happy to take this, but there is a slight issue that we have a
>fix working
>> it's way in which this is dependent on.
>>
>> I'll see if we can get this sorted before the merge window, but we
>may be
>> cutting it fine.
>>
>> Jonathan
>>
>
>Hello Jonathan,
>
>I can see the dependency fix made it to 4.17. What is the plan for this
>
>series? Getting into this merge window ?
Sorry, no. We were to tight on time. Will get it into linux-next in a few weeks, ready for the next merge window.
Jonathan
>
>Thanks,
>Eugen
>--
>To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>the body of a message to majordomo at vger.kernel.org
>More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
^ permalink raw reply
* [PATCH v5 4/4] ARM: dts: imx: add missing compatible and clock properties for EPIT
From: Clément Péron @ 2018-06-04 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604100035.19558-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add missing compatible and clock properties for EPIT node.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
arch/arm/boot/dts/imx25.dtsi | 8 ++++++--
arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
arch/arm/boot/dts/imx6sl.dtsi | 14 ++++++++++----
arch/arm/boot/dts/imx6sx.dtsi | 10 ++++++++--
arch/arm/boot/dts/imx6ul.dtsi | 10 ++++++++--
5 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index cf70df20b19c..15fd4308dad8 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -396,15 +396,19 @@
};
epit1: timer at 53f94000 {
- compatible = "fsl,imx25-epit";
+ compatible = "fsl,imx25-epit", "fsl,imx31-epit";
reg = <0x53f94000 0x4000>;
interrupts = <28>;
+ clocks = <&clks 83>;
+ status = "disabled";
};
epit2: timer at 53f98000 {
- compatible = "fsl,imx25-epit";
+ compatible = "fsl,imx25-epit", "fsl,imx31-epit";
reg = <0x53f98000 0x4000>;
interrupts = <27>;
+ clocks = <&clks 84>;
+ status = "disabled";
};
gpio4: gpio at 53f9c000 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c003e62bf290..65c4ee07454c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -843,14 +843,20 @@
};
};
- epit1: epit at 20d0000 { /* EPIT1 */
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 { /* EPIT2 */
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ab6a7e2e7e8f..6229bbef7ccc 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -671,14 +671,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6sl-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6sl-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 49c7205b8db8..2b30559d3270 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -736,14 +736,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6sx-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6sx-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972b16ba..d5f765da1ee2 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -658,14 +658,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6ul-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6ul-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
--
2.17.0
^ permalink raw reply related
* [PATCH v5 3/4] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-06-04 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604100035.19558-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add driver for NXP's EPIT timer used in i.MX SoC.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 265 +++++++++++++++++++++++++++
3 files changed, 277 insertions(+)
create mode 100644 drivers/clocksource/timer-imx-epit.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10..790478afd02c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -576,6 +576,17 @@ config H8300_TPU
This enables the clocksource for the H8300 platform with the
H8S2678 cpu.
+config CLKSRC_IMX_EPIT
+ bool "Clocksource using i.MX EPIT"
+ depends on CLKDEV_LOOKUP && (ARCH_MXC || COMPILE_TEST)
+ select CLKSRC_MMIO
+ help
+ This enables EPIT support available on some i.MX platforms.
+ Normally you don't have a reason to do so as the EPIT has
+ the same features and uses the same clocks as the GPT.
+ Anyway, on some systems the GPT may be in use for other
+ purposes.
+
config CLKSRC_IMX_GPT
bool "Clocksource using i.MX GPT" if COMPILE_TEST
depends on ARM && CLKDEV_LOOKUP
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 00caf37e52f9..d9426f69ec69 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
+obj-$(CONFIG_CLKSRC_IMX_EPIT) += timer-imx-epit.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
diff --git a/drivers/clocksource/timer-imx-epit.c b/drivers/clocksource/timer-imx-epit.c
new file mode 100644
index 000000000000..15f70e210fad
--- /dev/null
+++ b/drivers/clocksource/timer-imx-epit.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
+ * Copyright (C) 2018 Cl?ment P?ron <clement.peron@devialet.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0c
+#define EPITCNR 0x10
+
+#define EPITCR_EN BIT(0)
+#define EPITCR_ENMOD BIT(1)
+#define EPITCR_OCIEN BIT(2)
+#define EPITCR_RLD BIT(3)
+#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
+#define EPITCR_SWR BIT(16)
+#define EPITCR_IOVW BIT(17)
+#define EPITCR_DBGEN BIT(18)
+#define EPITCR_WAITEN BIT(19)
+#define EPITCR_RES BIT(20)
+#define EPITCR_STOPEN BIT(21)
+#define EPITCR_OM_DISCON (0 << 22)
+#define EPITCR_OM_TOGGLE (1 << 22)
+#define EPITCR_OM_CLEAR (2 << 22)
+#define EPITCR_OM_SET (3 << 22)
+#define EPITCR_CLKSRC_OFF (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
+#define EPITCR_CLKSRC_REF_LOW (3 << 24)
+
+#define EPITSR_OCIF BIT(0)
+
+struct epit_timer {
+ void __iomem *base;
+ int irq;
+ struct clk *clk;
+ struct clock_event_device ced;
+ struct irqaction act;
+};
+
+static void __iomem *sched_clock_reg;
+
+static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
+{
+ return container_of(ced, struct epit_timer, ced);
+}
+
+static inline void epit_irq_disable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static inline void epit_irq_enable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static void epit_irq_acknowledge(struct epit_timer *epittm)
+{
+ writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
+}
+
+static u64 notrace epit_read_sched_clock(void)
+{
+ return ~readl_relaxed(sched_clock_reg);
+}
+
+static int epit_set_next_event(unsigned long cycles,
+ struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long tcmp;
+
+ tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
+ writel_relaxed(tcmp, epittm->base + EPITCMPR);
+
+ return 0;
+}
+
+/* Left event sources disabled, no more interrupts appear */
+static int epit_shutdown(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt */
+ epit_irq_acknowledge(epittm);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int epit_set_oneshot(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt, only while switching mode */
+ if (!clockevent_state_oneshot(ced))
+ epit_irq_acknowledge(epittm);
+
+ /*
+ * Do not put overhead of interrupt enable/disable into
+ * epit_set_next_event(), the core has about 4 minutes
+ * to call epit_set_next_event() or shutdown clock after
+ * mode switching
+ */
+ epit_irq_enable(epittm);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ced = dev_id;
+ struct epit_timer *epittm = to_epit_timer(ced);
+
+ epit_irq_acknowledge(epittm);
+
+ ced->event_handler(ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init epit_clocksource_init(struct epit_timer *epittm)
+{
+ unsigned int c = clk_get_rate(epittm->clk);
+
+ sched_clock_reg = epittm->base + EPITCNR;
+ sched_clock_register(epit_read_sched_clock, 32, c);
+
+ return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
+ clocksource_mmio_readl_down);
+}
+
+static int __init epit_clockevent_init(struct epit_timer *epittm)
+{
+ struct clock_event_device *ced = &epittm->ced;
+ struct irqaction *act = &epittm->act;
+
+ ced->name = "epit";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
+ ced->set_state_shutdown = epit_shutdown;
+ ced->tick_resume = epit_shutdown;
+ ced->set_state_oneshot = epit_set_oneshot;
+ ced->set_next_event = epit_set_next_event;
+ ced->rating = 200;
+ ced->cpumask = cpumask_of(0);
+ ced->irq = epittm->irq;
+ clockevents_config_and_register(ced, clk_get_rate(epittm->clk),
+ 0xff, 0xfffffffe);
+
+ act->name = "i.MX EPIT Timer Tick",
+ act->flags = IRQF_TIMER | IRQF_IRQPOLL;
+ act->handler = epit_timer_interrupt;
+ act->dev_id = ced;
+
+ /* Make irqs happen */
+ return setup_irq(epittm->irq, act);
+}
+
+static int __init epit_timer_init(struct device_node *np)
+{
+ struct epit_timer *epittm;
+ int ret;
+
+ epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
+ if (!epittm)
+ return -ENOMEM;
+
+ epittm->base = of_iomap(np, 0);
+ if (!epittm->base) {
+ ret = -ENXIO;
+ goto out_kfree;
+ }
+
+ epittm->irq = irq_of_parse_and_map(np, 0);
+ if (!epittm->irq) {
+ ret = -EINVAL;
+ goto out_iounmap;
+ }
+
+ /* Get EPIT clock */
+ epittm->clk = of_clk_get(np, 0);
+ if (IS_ERR(epittm->clk)) {
+ pr_err("i.MX EPIT: unable to get clk\n");
+ ret = PTR_ERR(epittm->clk);
+ goto out_iounmap;
+ }
+
+ ret = clk_prepare_enable(epittm->clk);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk\n");
+ goto out_iounmap;
+ }
+
+ /* Initialise to a known state (all timers off, and timing reset) */
+ writel_relaxed(0x0, epittm->base + EPITCR);
+ writel_relaxed(0xffffffff, epittm->base + EPITLR);
+ writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+ epittm->base + EPITCR);
+
+ ret = epit_clocksource_init(epittm);
+ if (ret) {
+ pr_err("i.MX EPIT: failed to init clocksource\n");
+ goto out_clk_disable;
+ }
+
+ ret = epit_clockevent_init(epittm);
+ if (ret) {
+ pr_err("i.MX EPIT: failed to init clockevent\n");
+ goto out_clk_disable;
+ }
+
+ return 0;
+
+out_clk_disable:
+ clk_disable_unprepare(epittm->clk);
+out_iounmap:
+ iounmap(epittm->base);
+out_kfree:
+ kfree(epittm);
+
+ return ret;
+}
+TIMER_OF_DECLARE(epit_timer, "fsl,imx31-epit", epit_timer_init);
--
2.17.0
^ permalink raw reply related
* [PATCH v5 2/4] dt-bindings: timer: add i.MX EPIT timer binding
From: Clément Péron @ 2018-06-04 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604100035.19558-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
Add devicetree binding document for NXP's i.MX SoC specific
EPIT timer driver.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
.../devicetree/bindings/timer/fsl,imxepit.txt | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxepit.txt
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxepit.txt b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt
new file mode 100644
index 000000000000..de2e6ef68d24
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt
@@ -0,0 +1,21 @@
+Binding for the i.MX Enhanced Periodic Interrupt Timer (EPIT)
+
+The Enhanced Periodic Interrupt Timer (EPIT) is a 32-bit set-and-forget timer
+that is capable of providing precise interrupts at regular intervals with
+minimal processor intervention.
+
+Required properties:
+- compatible: should be "fsl,<chip>-epit", "fsl,imx31-epit" where <chip> is
+ imx25, imx6qdl, imx6sl, imx6sul or imx6sx.
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Should contain EPIT controller interrupt
+- clocks : The clock provided by the SoC to drive the timer.
+
+Example for i.MX6QDL:
+ epit1: epit at 20d0000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
+ reg = <0x020d0000 0x4000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>;
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH v5 1/4] ARM: imx: remove inexistant EPIT timer init
From: Clément Péron @ 2018-06-04 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604100035.19558-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
i.MX EPIT timer has been removed but not the init function declaration.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c8d68e918b2f..18aae76fa2da 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -38,7 +38,6 @@ void imx21_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
-void epit_timer_init(void __iomem *base, int irq);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
--
2.17.0
^ permalink raw reply related
* [PATCH v5 0/4] Reintroduce i.MX EPIT Timer
From: Clément Péron @ 2018-06-04 10:00 UTC (permalink / raw)
To: linux-arm-kernel
From: Cl?ment Peron <clement.peron@devialet.com>
As suggested in the commit message we have added the device tree support,
proper bindings and we moved the driver into the correct folder.
Moreover we made some changes like use of relaxed IO accesor,
implement sched_clock, delay_timer and reduce the clockevents min_delta.
Changes since v4:
- removed ipg clk
- change in dt epit to timer
- add introduction in doc
- add all compatibles in doc
- update epit entry for other i.MX device-trees
Changes since v3:
- Clean Kconfig
- Rename imx6q-epit to imx31-epit
- Update doc and bindings
- Indent and fix
Changes since v2 (Thanks Fabio Estevam):
- Removed unused ckil clock
- Add out_iounmap
- Check and handle if clk_prepare_enable failed
- Fix comment typo
Changes since v1 (Thanks Vladimir Zapolskiy):
- Add OF dependency in Kconfig
- Sort header
- Use BIT macro
- Remove useless comments
- Fix incorrect indent
- Fix memory leak
- Add check and handle possible returned error
Cl?ment Peron (2):
ARM: imx: remove inexistant EPIT timer init
dt-bindings: timer: add i.MX EPIT timer binding
Colin Didier (2):
clocksource: add driver for i.MX EPIT timer
ARM: dts: imx: add missing compatible and clock properties for EPIT
.../devicetree/bindings/timer/fsl,imxepit.txt | 21 ++
arch/arm/boot/dts/imx25.dtsi | 8 +-
arch/arm/boot/dts/imx6qdl.dtsi | 10 +-
arch/arm/boot/dts/imx6sl.dtsi | 14 +-
arch/arm/boot/dts/imx6sx.dtsi | 10 +-
arch/arm/boot/dts/imx6ul.dtsi | 10 +-
arch/arm/mach-imx/common.h | 1 -
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 265 ++++++++++++++++++
10 files changed, 338 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxepit.txt
create mode 100644 drivers/clocksource/timer-imx-epit.c
--
2.17.0
^ permalink raw reply
* [PATCH 0/3] ARM: shmobile: apmu: Cleanups after legacy SMP fallback removal
From: Simon Horman @ 2018-06-04 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180531143947.j56rcjmscflmvf6a@verge.net.au>
On Thu, May 31, 2018 at 10:39:48AM -0400, Simon Horman wrote:
> On Wed, May 30, 2018 at 05:15:25PM +0200, Geert Uytterhoeven wrote:
> > Hi Simon, Magnus,
> >
> > Now the legacy SMP fallbacks for R-Car H2 and M2-W have been removed, a
> > few more code cleanups can be applied.
> >
> > The third patch is a bit larger than I had hoped, due to the need to
> > reshuffle a few functions in the absence of forward declarations.
> >
> > Tested on Lager (R-Car H2) and Koelsch (R-Car M2-W).
> >
> > Thanks!
> >
> > Geert Uytterhoeven (3):
> > ARM: shmobile: apmu: Move cpu_leave_lowpower() to SUSPEND section
> > ARM: shmobile: apmu: Remove obsolete shmobile_smp_apmu_prepare_cpus()
> > ARM: shmobile: apmu: Remove platsmp-apmu.h
>
> This looks fine but I will wait to see if there are other reviews before
> applying.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks, applied.
^ permalink raw reply
* [PATCH v1 2/2] arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS
From: gengdongjiu @ 2018-06-04 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAG7+5M08R5MDHbR-oYK+un1jgGta2UfuaLaVG5Hf9qT7usHKfg@mail.gmail.com>
On 2018/6/2 5:22, Eric Northup wrote:
> On Wed, May 30, 2018 at 10:04 PM Dongjiu Geng <gengdongjiu@huawei.com> wrote:
>>
>> For the migrating VMs, user space may need to know the exception
[...]
>> + __u8 pad[6];
>> + __u64 serror_esr;
>> + } exception;
>> + __u32 reserved[12];
>
> It will be easier to re-purpose this in the future if the field is
> reserved and is checked that it must be zero. SET_VCPU_EVENTS would
> return EINVAL if reserved fields get used until a later meaning is
> defined for them.
Ok, thanks. I will check the reserved fields when calling SET_VCPU_EVENTS.
>
>> +};
>> +
>> /* If you need to interpret the index values, here is the key: */
>> #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
>> #define KVM_REG_ARM_COPROC_SHIFT 16
>> diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
>> index 56a0260..71d3841 100644
>> --- a/arch/arm64/kvm/guest.c
>> +++ b/arch/arm64/kvm/guest.c
>> @@ -289,6 +289,42 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
>> return -EINVAL;
>> }
>>
[...]
>> --
>> 2.7.4
>>
>
> .
>
^ permalink raw reply
* [PATCH v2 0/2] Add R8A77980/Condor I2C support
From: Simon Horman @ 2018-06-04 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2a88f4e9-0a86-8e6f-0ef2-20913dc9431d@cogentembedded.com>
On Thu, May 31, 2018 at 11:18:57PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180529-v4.17-rc7' tag. We're adding the R8A77980 I2C nodes
> and then describing 2 PCA9654 I/O expanders connected to the I2C0 bus on
> the Condor board.
Thanks, applied.
^ permalink raw reply
* [PATCH v2] ARM: avoid Cortex-A9 livelock on tight dmb loops
From: Will Deacon @ 2018-06-04 9:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fOhn6-00008E-3b@rmk-PC.armlinux.org.uk>
Hi Russell,
On Fri, Jun 01, 2018 at 12:00:16PM +0100, Russell King wrote:
> Executing loops such as:
>
> while (1)
> cpu_relax();
>
> with interrupts disabled results in a livelock of the entire system,
> as other CPUs are prevented making progress. This is most noticable
> as a failure of crashdump kexec, which stops just after issuing:
>
> Loading crashdump kernel...
>
> to the system console. Two other locations of these loops within the
> ARM code have been identified and fixed up.
Can you confirm that this only happens if CONFIG_ARM_ERRATA_754327=y?
The only erratum I can find for A9 that matches this behaviour exists
when the body of the tight loop contains a DMB and some of the possible
workarounds are:
- Add ten NOPs after the DMB
- Use DSB instead of DMB in the tight loop
- Set bit 16 in the diagnostic control register (p15, c1, 5, 0, c0, 1)
WFE is probably fine (the write-up isn't clear), but if this only occurs
due to CONFIG_ARM_ERRATA_754327=y it would be nice to mitigate it in the
alternative cpu_relax() definition itself, which isn't generally possible
with WFE.
Will
^ permalink raw reply
* [PATCH V2] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Simon Horman @ 2018-06-04 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180525200508.22207-1-marek.vasut+renesas@gmail.com>
On Fri, May 25, 2018 at 10:05:08PM +0200, Marek Vasut wrote:
> Rather than hard-coding the quirk topology, which stopped scaling,
> parse the information from DT. The code looks for all compatible
> PMICs -- da9036 and da9210 -- and checks if their IRQ line is tied
> to the same pin. If so, the code sends a matching sequence to the
> PMIC to deassert the IRQ.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Simon Horman <horms+renesas@verge.net.au>
> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Cc: linux-renesas-soc at vger.kernel.org
> ---
> V2: - Replace the DT shared IRQ check loop with memcmp()
> - Send the I2C message to deassert the IRQ line to all PMICs
> in the list with shared IRQ line instead of just one
> - Add comment that this works only in case all the PMICs are
> on the same I2C bus
> ---
> arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 117 ++++++++++++++++-----
> 1 file changed, 93 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
> index 93f628acfd94..4db8d9ea5f97 100644
> --- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
> +++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
> @@ -31,8 +31,10 @@
> #include <linux/i2c.h>
> #include <linux/init.h>
> #include <linux/io.h>
> +#include <linux/list.h>
> #include <linux/notifier.h>
> #include <linux/of.h>
> +#include <linux/of_irq.h>
> #include <linux/mfd/da9063/registers.h>
>
>
> @@ -44,34 +46,47 @@
> /* start of DA9210 System Control and Event Registers */
> #define DA9210_REG_MASK_A 0x54
>
> +struct regulator_quirk {
> + struct list_head list;
> + const struct of_device_id *id;
> + struct of_phandle_args irq_args;
> + struct i2c_msg i2c_msg;
> + bool shared; /* IRQ line is shared */
> +};
> +
> +static LIST_HEAD(quirk_list);
> static void __iomem *irqc;
>
> /* first byte sets the memory pointer, following are consecutive reg values */
> static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
> static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
>
> -static struct i2c_msg da9xxx_msgs[3] = {
> - {
> - .addr = 0x58,
> - .len = ARRAY_SIZE(da9063_irq_clr),
> - .buf = da9063_irq_clr,
> - }, {
> - .addr = 0x68,
> - .len = ARRAY_SIZE(da9210_irq_clr),
> - .buf = da9210_irq_clr,
> - }, {
> - .addr = 0x70,
> - .len = ARRAY_SIZE(da9210_irq_clr),
> - .buf = da9210_irq_clr,
> - },
> +static struct i2c_msg da9063_msgs = {
> + .addr = 0x00,
I don't think you need to explicitly initialise the .addr fields to 0.
> + .len = ARRAY_SIZE(da9063_irq_clr),
> + .buf = da9063_irq_clr,
> +};
> +
> +static struct i2c_msg da9210_msgs = {
> + .addr = 0x00,
> + .len = ARRAY_SIZE(da9210_irq_clr),
> + .buf = da9210_irq_clr,
> +};
> +
> +static const struct of_device_id rcar_gen2_quirk_match[] = {
> + { .compatible = "dlg,da9063", .data = &da9063_msgs },
> + { .compatible = "dlg,da9210", .data = &da9210_msgs },
> + {},
> };
>
> static int regulator_quirk_notify(struct notifier_block *nb,
> unsigned long action, void *data)
> {
> + struct regulator_quirk *pos, *tmp;
> struct device *dev = data;
> struct i2c_client *client;
> static bool done;
> + int ret;
> u32 mon;
>
> if (done)
> @@ -88,17 +103,20 @@ static int regulator_quirk_notify(struct notifier_block *nb,
> client = to_i2c_client(dev);
> dev_dbg(dev, "Detected %s\n", client->name);
>
> - if ((client->addr == 0x58 && !strcmp(client->name, "da9063")) ||
> - (client->addr == 0x68 && !strcmp(client->name, "da9210")) ||
> - (client->addr == 0x70 && !strcmp(client->name, "da9210"))) {
> - int ret, len;
> + /*
> + * Send message to all PMICs that share an IRQ line to deassert it.
> + *
> + * WARNING: This works only if all the PMICs are on the same I2C bus.
> + */
> + list_for_each_entry(pos, &quirk_list, list) {
> + if (!pos->shared)
> + continue;
>
> - /* There are two DA9210 on Stout, one on the other boards. */
> - len = of_machine_is_compatible("renesas,stout") ? 3 : 2;
> + dev_info(&client->dev, "clearing %s at 0x%02x interrupts\n",
> + pos->id->compatible, pos->i2c_msg.addr);
>
> - dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
> - ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
> - if (ret != len)
> + ret = i2c_transfer(client->adapter, &pos->i2c_msg, 1);
> + if (ret != 1)
> dev_err(&client->dev, "i2c error %d\n", ret);
> }
>
> @@ -111,6 +129,11 @@ static int regulator_quirk_notify(struct notifier_block *nb,
> remove:
> dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
>
> + list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
> + list_del(&pos->list);
> + kfree(pos);
> + }
> +
> done = true;
> iounmap(irqc);
> return 0;
> @@ -122,7 +145,13 @@ static struct notifier_block regulator_quirk_nb = {
>
> static int __init rcar_gen2_regulator_quirk(void)
> {
> - u32 mon;
> + struct device_node *np;
> + const struct of_device_id *id;
> + struct regulator_quirk *quirk;
> + struct regulator_quirk *pos;
> + struct of_phandle_args *argsa, *argsb;
> + u32 mon, addr;
> + int ret;
>
> if (!of_machine_is_compatible("renesas,koelsch") &&
> !of_machine_is_compatible("renesas,lager") &&
> @@ -130,6 +159,46 @@ static int __init rcar_gen2_regulator_quirk(void)
> !of_machine_is_compatible("renesas,gose"))
> return -ENODEV;
>
> + for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
> + if (!np || !of_device_is_available(np))
> + break;
> +
> + quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
> +
> + argsa = &quirk->irq_args;
> + memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
> +
> + ret = of_property_read_u32(np, "reg", &addr);
> + if (ret)
> + return ret;
> +
> + quirk->id = id;
> + quirk->i2c_msg.addr = addr;
> + quirk->shared = false;
> +
> + ret = of_irq_parse_one(np, 0, &quirk->irq_args);
&quirk->irq_args is assigned to argsa above and used directly here.
> + if (ret)
> + return ret;
> +
> + list_for_each_entry(pos, &quirk_list, list) {
> + argsa = &quirk->irq_args;
argsa is initialised both here and further above.
> + argsb = &pos->irq_args;
> +
> + if (argsa->args_count != argsb->args_count)
> + continue;
> +
> + ret = memcmp(argsa->args, argsb->args,
> + argsa->args_count *
> + sizeof(argsa->args[0]));
> + if (!ret) {
> + pos->shared = true;
> + quirk->shared = true;
> + }
> + }
> +
> + list_add_tail(&quirk->list, &quirk_list);
> + }
> +
> irqc = ioremap(IRQC_BASE, PAGE_SIZE);
> if (!irqc)
> return -ENOMEM;
> --
> 2.16.2
>
^ permalink raw reply
* [PATCH v4 4/5] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-06-04 9:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <677be207-67be-ccbc-8bb3-ab90bf9d05a7@mentor.com>
Hi Vladimir,
On Thu, 31 May 2018 at 10:36, Vladimir Zapolskiy
<vladimir_zapolskiy@mentor.com> wrote:
>
> Hi Cl?ment,
>
> On 05/30/2018 03:03 PM, Cl?ment P?ron wrote:
> > From: Colin Didier <colin.didier@devialet.com>
> >
> > Add driver for NXP's EPIT timer used in i.MX 6 family of SoC.
> >
> > Signed-off-by: Colin Didier <colin.didier@devialet.com>
> > Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
> > ---
>
> [snip]
>
> > +++ b/drivers/clocksource/timer-imx-epit.c
> > @@ -0,0 +1,281 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * i.MX EPIT Timer
> > + *
> > + * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
> > + * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
> > + * Copyright (C) 2018 Cl?ment P?ron <clement.peron@devialet.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/err.h>
>
> The included header above still can be removed.
Ok.
>
> I have no more comments about the code, I will try to find time to
> test the driver, but please don't take it as a promise.
Regarding the clks, i think the management of the ipg clk in the
driver is useless
has it is already handled by the imx clk driver.
I remove the ipg clk and test it on i.MX6Q.
My test is limited to disabled the GPT and enabled the EPIT in the device-tree
&gpt {
status = "disabled";
};
&epit1 {
status = "okay";
};
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.17.0-rc6 (cperon at cperon-Latitude-7490)
(gcc version 6.4.1 20170707 (Linaro GCC 6.4-2017.08)) #1 SMP PREEMPT
Mon Jun 4 11:13:41 CEST 2018
[ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
instruction cache
[ 0.000000] OF: fdt: Machine model: Devialet Aerobase
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] On node 0 totalpages: 262144
[ 0.000000] Normal zone: 2048 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 262144 pages, LIFO batch:31
[ 0.000000] random: get_random_bytes called from
start_kernel+0x80/0x398 with crng_init=0
[ 0.000000] percpu: Embedded 16 pages/cpu @(ptrval) s35084 r8192
d22260 u65536
[ 0.000000] pcpu-alloc: s35084 r8192 d22260 u65536 alloc=16*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096
[ 0.000000] Kernel command line: console=ttymxc0,115200
root=/dev/nfs rw nfsroot=192.168.0.4:/opt/nfsroot,v3,tcp ip=dhcp
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 1029544K/1048576K available (6144K kernel code,
194K rwdata, 1312K rodata, 1024K init, 224K bss, 19032K reserved, 0K
cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Tasks RCU enabled.\x00
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] L2C-310 errata 752271 769419 enabled
[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
[ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[ 0.000000] L2C-310 ID prefetch enabled, offset 16 lines
[ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[ 0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[ 0.000000] L2C-310: CACHE_ID 0x410000c7, AUX_CTRL 0x76470001
[ 0.000012] sched_clock: 32 bits at 66MHz, resolution 15ns, wraps
every 32537631224ns
[ 0.000032] clocksource: epit: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 28958491609 ns
[ 0.001231] Calibrating delay loop... 1560.57 BogoMIPS (lpj=780288)
[ 0.008161] pid_max: default: 32768 minimum: 301
[ 0.008336] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.008360] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.009042] CPU: Testing write buffer coherency: ok
[ 0.009506] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.014238] Setting up static identity map for 0x10100000 - 0x10100060
[ 0.015207] Hierarchical SRCU implementation.
[ 0.017208] smp: Bringing up secondary CPUs ...
[ 0.029147] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.041146] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[ 0.053146] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[ 0.053321] smp: Brought up 1 node, 4 CPUs
[ 0.053340] SMP: Total of 4 processors activated (6303.74 BogoMIPS).
[ 0.053349] CPU: All CPU(s) started in SVC mode.
[ 0.054441] devtmpfs: initialized
[ 0.063770] VFP support v0.3: implementor 41 architecture 3 part 30
variant 9 rev 4
[ 0.064454] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 1911260446275000 ns
[ 0.064477] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.064742] pinctrl core: initialized pinctrl subsystem
[ 0.066693] NET: Registered protocol family 16
[ 0.068623] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.071654] cpuidle: using governor menu
[ 0.071802] CPU identified as i.MX6Q, silicon rev 1.2
>
> --
> With best wishes,
> Vladimir
^ permalink raw reply
* [PATCH] arm64: alternative:flush cache with unpatched code
From: Will Deacon @ 2018-06-04 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527788750049.85185@nvidia.com>
On Thu, May 31, 2018 at 05:45:11PM +0000, Rohit Khanna wrote:
> Will, thanks for the comments.
> I will push a new patch set.
> We want to avoid using __flush_icache_all as much as possible and hence
> trying to flush cache by range.
Why? We're going to do it once at boot and once on each module load, so I
can't see it being a performance concern.
Will
^ permalink raw reply
* [PATCH v4 5/5] ARM: dts: imx6qdl: add missing compatible and clock properties for EPIT
From: Clément Péron @ 2018-06-04 9:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f71fe02d-23a7-a475-52df-62c17089549b@mentor.com>
Hi Vladimir,
On Thu, 31 May 2018 at 10:54, Vladimir Zapolskiy
<vladimir_zapolskiy@mentor.com> wrote:
>
> Hi Cl?ment,
>
> On 05/31/2018 11:41 AM, Cl?ment P?ron wrote:
> > Hi Vladimir,
> >
> > On Thu, 31 May 2018 at 10:33, Vladimir Zapolskiy
> > <vladimir_zapolskiy@mentor.com> wrote:
> >>
> >> On 05/30/2018 03:03 PM, Cl?ment P?ron wrote:
> >>> From: Colin Didier <colin.didier@devialet.com>
> >>>
> >>> Add missing compatible and clock properties for EPIT node.
> >>>
> >>> Signed-off-by: Colin Didier <colin.didier@devialet.com>
> >>> Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
> >>> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
> >>> ---
> >>> arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++++
> >>> 1 file changed, 10 insertions(+)
> >>>
> >>> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> >>> index c003e62bf290..0feec516847a 100644
> >>> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> >>> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> >>> @@ -844,13 +844,23 @@
> >>> };
> >>>
> >>> epit1: epit at 20d0000 { /* EPIT1 */
> >>
> >> epit1: timer at 20d0000 { ...
> >>
> >> And /* EPIT1 */ comment can be removed, it is quite clear from the same
> >> line context.
> >>
> >> Formally it is a subject to another patch, but I think this can be
> >> accepted as a part of this one.
> >
> > Should I also update other boards ?
> > I only did it for imx6qdl.dtsi, but the EPIT is present in other boards
> > but i can't test it myself.
> >
>
> Sure, please do it, why not, it is quite a safe modification.
>
> One change per one dtsi file will suffice, and I see that imx25.dtsi
> already contains the requested change, however probably you may
> want to update its compatible = "fsl,imx25-epit" line.
>
> Regarding compatibles for other imx6* SoCs, I think all of them should
> be documented in fsl,imxepit.txt and then added to the correspondent
> dtsi files one per SoC.
Nvidia UART doc did this :
- For other Tegra, must contain '"nvidia,<chip>-uart",
"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
I will follow this.
>
> And I forgot the outcome of one former discussion with Uwe Kleine-K?nig,
> but if my bad memory serves me, we agreed that i.MX25 was released later
> than i.MX31, so the most generic (the last value in the list) compatible
> should be a compatible with i.MX31 like in
>
> imx25.dtsi:367: compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
>
> --
> With best wishes,
> Vladimir
Regards,
Clement
^ permalink raw reply
* [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.18
From: Simon Horman @ 2018-06-04 9:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180602083220.o6b7xqziugeqyd46@localhost>
On Sat, Jun 02, 2018 at 01:32:20AM -0700, Olof Johansson wrote:
> On Mon, May 28, 2018 at 09:44:41AM +0200, Simon Horman wrote:
> > Hi Olof,
> >
> > On Sat, May 26, 2018 at 02:14:20PM -0700, Olof Johansson wrote:
> > > Hi Simon,
> > >
> > > On Fri, May 18, 2018 at 01:16:00PM +0200, Simon Horman wrote:
> > > > Hi Olof, Hi Kevin, Hi Arnd,
> > > >
> > > > Please consider these Renesas ARM64 based SoC DT updates for v4.18.
> > > >
> > > >
> > > > The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
> > > >
> > > > Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
> > > >
> > > > are available in the git repository at:
> > > >
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt-for-v4.18
> > > >
> > > > for you to fetch changes up to 908001d778eba06ee1d832863d4e9a1e2cfd4746:
> > > >
> > > > arm64: dts: renesas: salvator-common: Add ADV7482 support (2018-05-18 11:52:03 +0200)
> > >
> > > This pull request is really, really hard for us to digest. The tag
> > > description is very large, and it repeats several SoCs several times,
> > > making it hard to get an overview of what is in it. The verbosity of "<x>
> > > says.." makes it harder on this size of a pull request as well.
> >
> > I appologise that this pull-request has turned out to be hard to digest.
> >
> > I think that one reason for this is that there are an unusally large number
> > of commits. It seems that the team has been a little more productive than
> > usual and I might have been better to send a smaller pull-request earlier
> > in the development cycle and then follow-up with a second batch. I'll try
> > to pay more attention to this aspect of things going forwards.
> >
> > Regarding your specific comments:
> >
> > * Repetition of SoCs. I do try to group things in a logical manner,
> > but clearly I failed in this case. I'll try to make that a bit clearer
> > in future.
>
> I don't think you're helped by the fact that Renesas product names seem
> to have little rhyme or reason to them, and mumbles families and product
> names and numbers seemingly random. :(
>
> > * Verbosity: There as a request a few development cycles for me
> > to include more information in the commit logs. It seems that
> > I may have gone a bit too far. I'll try to find a better balance next
> > time around.
>
> There's a balance to be found here. You chose to describe some very small
> changes with 3 lines of description, and as a result it's hard to get an
> overview of what's in the pull request.
>
> As a maintainer, you should strive to be the editor that makes sure that
> things are easy to understand, and arranged in a manner that makes sense
> for both your developers and the rest of the community (and the upstream
> maintainers).
Understood. I'll work on making things easier to digest for all concerned.
> > * Patches for the same change split up for different SoCs/boards.
> > Featurs broken out into incremental patches. And so on.
> >
> > This has been a long-standing practice for Renesas SoC development.
> > We find that in general it aids review. It also works well
> > with the way we develop patches. But I do see your point that
> > it may be a little excessive - f.e. multiple patches for the same
> > whitespace fixes. Again, we'll try to find a better balance.
>
> I can understand where the policy comes from, but it seems to me that at least
> in this case it's one that's no longer scaling to the number of SoCs you're
> supporting, and the number of (each small) additions that you're doing.
> Grouping in some of the simpler dtsi additions into one per SoC, or one per IP
> block across all SoCs, seems like something to attempt here.
I think your point about scaling is well made. We'll start tweaking our
processes to see if we can find a better way.
> > > For example:
> > >
> > > > * Condor board with R-Car V3H (r8a77980) SoC
> > > > - Enable eMMC
> > > >
> > > > Sergei Shtylyov says "We're adding the R8A77980 MMC (SDHI)
> > > > device nodes and then enable eMMC support on the Condor board."
> > >
> > > The "Enable eMMC" line is just fine here.
> > >
> > > > ----------------------------------------------------------------
> > > > Geert Uytterhoeven (11):
> > > > arm64: dts: renesas: draak: Rename EtherAVB "mdc" pin group to "mdio"
> > > > arm64: dts: renesas: salvator-common: Rename EtherAVB "mdc" pin group to "mdio"
> > > > arm64: dts: renesas: ulcb: Rename EtherAVB "mdc" pin group to "mdio"
> > >
> > > Why can't these be done in one commit?
> > >
> > > > arm64: dts: renesas: r8a7795: Correct whitespace
> > > > arm64: dts: renesas: r8a7796: Correct whitespace
> > > > arm64: dts: renesas: r8a77965: Correct whitespace
> > >
> > > Do these really need to be three commits to fix some whitespace?
> > >
> > > > arm64: dts: renesas: ulcb: Add BD9571 PMIC
> > > > arm64: dts: renesas: salvator-common: Add PMIC DDR Backup Power config
> > > > arm64: dts: renesas: ulcb: Add PMIC DDR Backup Power config
> > > > arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
> > > > arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
> > >
> > > Why can't these be done in the same commit?
> > >
> > > > Kieran Bingham (7):
> > > > arm64: dts: renesas: r8a77965: Add FCPF and FCPV instances
> > > > arm64: dts: renesas: r8a77965: Add VSP instances
> > > > arm64: dts: renesas: r8a77965: Populate the DU instance placeholder
> > > > arm64: dts: renesas: r8a77965: Add HDMI encoder instance
> > > > arm64: dts: renesas: r8a77965-salvator-x: Enable DU external clocks and HDMI
> > > > arm64: dts: renesas: r8a77965-salvator-xs: Enable DU external clocks and HDMI
> > >
> > > These two can probably be in one commit as well.
> > >
> > > > arm64: dts: renesas: salvator-common: Add ADV7482 support
> > > >
> > > > Kuninori Morimoto (8):
> > > > arm64: dts: renesas: r8a7795: add HDMI sound support
> > > > arm64: dts: renesas: r8a7796: add HDMI sound support
> > >
> > > ... starting to see a trend?
> > >
> > > > arm64: dts: renesas: salvator-common: use audio-graph-card for Sound
> > > > arm64: dts: renesas: r8a7795-es1-salvator-x: enable HDMI sound
> > > > arm64: dts: renesas: r8a7795-salvator-xs: enable HDMI sound
> > > > arm64: dts: renesas: r8a7796-salvator-xs: enable HDMI sound
> > > > arm64: dts: renesas: r8a7795-salvator-x: enable HDMI sound
> > > > arm64: dts: renesas: r8a7796-salvator-x: enable HDMI sound
> > >
> > > ... and more.
> > >
> > > >
> > > > Magnus Damm (5):
> > > > arm64: dts: renesas: r8a77970: Update IPMMU DS1 bit number
> > > > arm64: dts: renesas: r8a7795: Enable IPMMU devices
> > > > arm64: dts: renesas: r8a7796: Enable IPMMU devices
> > > > arm64: dts: renesas: r8a77970: Enable IPMMU devices
> > > > arm64: dts: renesas: r8a77995: Enable IPMMU devices
> > >
> > > I think these 4 could be in one commit too.
> > >
> > > >
> > > > Niklas S?derlund (11):
> > > > arm64: dts: renesas: r8a7795: decrease temperature hysteresis
> > > > arm64: dts: renesas: r8a7796: decrease temperature hysteresis
> > > > arm64: dts: renesas: r8a77965: use r8a77965-sysc binding definitions
> > > > arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support
> > > > arm64: dts: renesas: r8a77965: add I2C support
> > > > arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
> > > > arm64: dts: renesas: r8a7795-es1: add CSI-2 node
> > > > arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
> > > > arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
> > > > arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
> > >
> > >
> > > .... etc, etc. I'll stop here.
> > >
> > >
> > > I haven't merged this branch yet, will need to set aside more time to review
> > > the contents. I can't guarantee that it'll make v4.18 but I'll try.
> >
> > Please let me know if there is anything I can do to help make this happen.
> > This work is very important to Renesas.
>
> I've queued this and the SoC branch up in a next/late branch now. I'm planning
> on sending it in unless it's a messy or hard merge window for some reason.
Thanks, much appreciated.
^ permalink raw reply
* [PATCH v3 2/2] arm64: allwinner: a64-amarula-relic: Enable AP6330 WiFi support
From: Maxime Ripard @ 2018-06-04 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180601173527.18051-2-jagan@amarulasolutions.com>
On Fri, Jun 01, 2018 at 11:05:27PM +0530, Jagan Teki wrote:
> Enable AP6330 WiFi/BT combo chip on Amarula A64-Relic board:
> - WiFi SDIO interface is connected to MMC1
> - WiFi WL-PMU-EN pin connected to gpio PL2: attach to mmc-pwrseq
> - WiFi WL-WAKE-AP pin connected to gpio PL3
> - 32kHz external oscillator gate clock from RTC
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Applied both, thanks
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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* [PATCH v2 0/9] Rewrite asm-generic/bitops/{atomic,lock}.h and use on arm64
From: Will Deacon @ 2018-06-04 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604074029.GN12217@hirez.programming.kicks-ass.net>
On Mon, Jun 04, 2018 at 09:40:29AM +0200, Peter Zijlstra wrote:
> On Fri, Jun 01, 2018 at 05:06:20PM +0100, Will Deacon wrote:
> > Hi all,
> >
> > This patch series has previously been posted in RFC form here:
> >
> > RFCv1: https://www.spinics.net/lists/arm-kernel/msg634719.html
> > RFCv2: https://www.spinics.net/lists/arm-kernel/msg636875.html
> > v1: https://www.spinics.net/lists/arm-kernel/msg655262.html
> >
> > The only change since v1 is that some of the fetch ops are replaced
> > by non-value-returning ops for some of the atomic bitops.
> >
>
> Looks good,
>
> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Thanks, Peter!
> How do you want to route this, through tip or the arm64 tree?
I think -tip would make the most sense, if that's ok with Ingo.
Cheers,
Will
^ permalink raw reply
* [PATCH] arm64: alternative:flush cache with unpatched code
From: Mark Rutland @ 2018-06-04 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527882765869.38555@nvidia.com>
On Fri, Jun 01, 2018 at 07:52:05PM +0000, Rohit Khanna wrote:
> [RK] - Thanks for the comments Mark. Reply inlined.
>
> Thanks
> Rohit
> ________________________________________
> From: Mark Rutland <mark.rutland@arm.com>
> Sent: Friday, June 1, 2018 2:03 AM
> To: Rohit Khanna
> Cc: catalin.marinas at arm.com; robin.murphy at arm.com; Suzuki.Poulose at arm.com; linux-arm-kernel at lists.infradead.org; Alexander Van Brunt; Bo Yan; will.deacon at arm.com
> Subject: Re: [PATCH] arm64: alternative:flush cache with unpatched code
[...]
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -617,6 +617,9 @@
> > #define MVFR1_FPDNAN_SHIFT 4
> > #define MVFR1_FPFTZ_SHIFT 0
> >
> > +/* SYS_CTR_EL0 */
> > +#define SYS_CTR_ISIZE_SHIFT 0
> > +#define SYS_CTR_DSIZE_SHIFT 16
>
> We already have CTR_DMINLINE_SHIFT in <asm/cache.h>
>
> Can we please add CTR_IMINLIN_SHIFT there too?
>
> Maybe those should be moved into sysreg.h, but that can be a separate cleanup.
>
> [RK] - <asm/cache.h> doesnt contain CTR_DMINLINE_SHIFT.
It's on line 23 of arch/arm64/include/asm/cache.h, looking at v4.17.
[...]
> > + /* use sanitised value of ctr_el0 rather than raw value from CPU */
> > + ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
> > + /* size in bytes */
> > + d_size = cpuid_feature_extract_unsigned_field(ctr_el0,
> > + SYS_CTR_DSIZE_SHIFT);
> > + i_size = cpuid_feature_extract_unsigned_field(ctr_el0,
> > + SYS_CTR_ISIZE_SHIFT);
>
> This isn't the size in bytes. Each is log2 the number of (4-byte) words.
>
> i.e. the size in bytes is (xMinLine << 2).
> [RK] - This doesnt seem right. For eg if IMinLine = 4 or 0b100
> then with above formula ICacheSize in Bytes = 4 << 2 = 16
> The correct formula should be (4 << xMinLine).
> So in case IMinLine = 4 or 0b100,
> ICacheSizeBytes = 4 << 4 = 64B
Whoops. You are correct with 4 << xMinLine.
[...]
> > + d_start = (u64)start & ~(d_size - 1);
> > + while (d_start <= (u64)end) {
> > + /* Use civac instead of cvau. This is required
> > + * due to ARM errata 826319, 827319, 824069,
> > + * 819472 on A53
> > + */
> > + asm volatile("dc civac, %0" : : "r" (d_start));
>
> Either this needs a memory clobber, or we need barrier() first, to ensure that
> the compiler doesn't re-order this against some of the patching code, however
> unlikely that may be.
> [RK] - So add barrier() before calling clean_dcache_range_nopatch() ?
I'd put it before the loop here so that it's clearly associated with the DC CIVAC.
Thanks,
Mark.
^ permalink raw reply
* [PATCH 1/3] arm64: allwinner: a64: add R_I2C controller
From: Maxime Ripard @ 2018-06-04 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+E=qVfH3wWsSdzGn353q0Jf-PQ8cjU-i5osLOV1c4qWVGrR5A@mail.gmail.com>
On Fri, Jun 01, 2018 at 10:30:00AM -0700, Vasily Khoruzhick wrote:
> >> ---
> >> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++
> >> 1 file changed, 17 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> index 1b2ef28c42bd..b5e903ccf0ec 100644
> >> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> @@ -46,6 +46,7 @@
> >> #include <dt-bindings/clock/sun8i-r-ccu.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> #include <dt-bindings/reset/sun50i-a64-ccu.h>
> >> +#include <dt-bindings/reset/sun8i-r-ccu.h>
> >>
> >> / {
> >> interrupt-parent = <&gic>;
> >> @@ -655,6 +656,17 @@
> >> #reset-cells = <1>;
> >> };
> >>
> >> + r_i2c: i2c at 1f02400 {
> >> + compatible = "allwinner,sun6i-a31-i2c";
> >
> > You should add an a64 compatible here
>
> We don't have it for regular i2c, why should I add it here?
We miss some of them. Adding for i2c would make sense too.
> >> + reg = <0x01f02400 0x400>;
> >> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&r_ccu CLK_APB0_I2C>;
> >> + resets = <&r_ccu RST_APB0_I2C>;
> >> + status = "disabled";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + };
> >> +
> >> r_pio: pinctrl at 1f02c00 {
> >> compatible = "allwinner,sun50i-a64-r-pinctrl";
> >> reg = <0x01f02c00 0x400>;
> >> @@ -670,6 +682,11 @@
> >> pins = "PL0", "PL1";
> >> function = "s_rsb";
> >> };
> >> +
> >> + r_i2c_pins_a: i2c-a {
> >> + pins = "PL8", "PL9";
> >> + function = "s_i2c";
> >> + };
> >
> > This should be ordered by alphabetical order
>
> OK
>
> > If this is the only muxing option, you can also add it to the i2c DT
> > node.
>
> It's not the only option, but other option conflicts with rsb. Should
> I still add it to i2c DT node?
I guess you can put it there, the muxing will only be enforced if the
device is enabled, and there should be only one of RSB or I2C that
would be.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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* [PATCH 3/3] arm64: dts: allwinner: add support for Pinebook
From: Maxime Ripard @ 2018-06-04 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+E=qVffecgkCG2V_5ptS9oRxo4XwjpQQhWmf8ywpfF78Yy+7A@mail.gmail.com>
On Fri, Jun 01, 2018 at 10:37:29AM -0700, Vasily Khoruzhick wrote:
> On Fri, Jun 1, 2018 at 2:23 AM, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > On Thu, May 31, 2018 at 11:29:01PM -0700, Vasily Khoruzhick wrote:
> >> From: Icenowy Zheng <icenowy@aosc.xyz>
> >>
> >> Pinebook is a A64-based laptop produced by Pine64, with the following
> >> peripherals:
> >>
> >> USB:
> >> - Two external USB ports (one is directly connected to A64's OTG
> >> controller, the other is under a internal hub connected to the host-only
> >> controller.)
> >> - USB HID keyboard and touchpad connected to the internal hub.
> >> - USB UVC camera connected to the internal hub.
> >>
> >> Power-related:
> >> - A DC IN jack connected to AXP803's DCIN pin.
> >> - A Li-Polymer battery connected to AXP803's battery pins.
> >>
> >> Storage:
> >> - An eMMC by Foresee on the main board (in the product revision of the
> >> main board it's designed to be switchable).
> >> - An external MicroSD card slot.
> >>
> >> Display:
> >> - An eDP LCD panel (1366x768) connected via an ANX6345 RGB-eDP bridge.
> >> - A mini HDMI port.
> >>
> >> Misc:
> >> - A Hall sensor designed to detect the status of lid, connected to GPIO PL12.
> >> - A headphone jack connected to the SoC's internal codec.
> >> - A debug UART port muxed with headphone jack.
> >>
> >> This commit adds basical support for it.
> >>
> >> [vasily: squashed several commits into one, added simplefb node, added usbphy
> >> to ehci0 and ohci0 nodes]
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> >> ---
> >> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> >> .../dts/allwinner/sun50i-a64-pinebook.dts | 285 ++++++++++++++++++
> >> 2 files changed, 286 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> >>
> >> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> >> index 8bebe7da5ed9..a8c6d0c6f2c5 100644
> >> --- a/arch/arm64/boot/dts/allwinner/Makefile
> >> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> >> @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
> >> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
> >> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> >> new file mode 100644
> >> index 000000000000..d952db217702
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
> >> @@ -0,0 +1,285 @@
> >> +/*
> >> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
> >> + * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
> >> + *
> >> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >
> > The SPDX tag should be the first one.
>
> OK, but it's not in number of other dts files, e.g.
> sun50i-a64-teres-i.dts or sun50i-h5-orangepi-zero-plus.dts
I guess we'd have to fix it then
> >> +/* The ANX6345 eDP-bridge is on r_i2c. There is no linux (mainline)
> >> + * driver for this chip at the moment, the bootloader initializes it.
> >> + * However it can be accessed with the i2c-dev driver from user space.
> >> + */
> >
> > The comment format is wrong, and the part after r_i2c, about i2c-dev
> > and the mainline support is not really relevant. The DT describes the
> > hardware, and is used by several different projects that might or
> > might not have i2c-dev, an interface similar, or might have or not a
> > driver for the bridge.
>
> Comment is identical to sun50i-a64-teres-i.dts (which was merged few
> months ago).
> I'll remove everything but first sentence.
We don't notice everything unfortunately. Feel free to fix it in the
TERES-I DTS as well.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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