* [PATCH v2 1/1] ARM: dts: cygnus: enable iproc-hwrng
From: Florian Fainelli @ 2018-06-07 16:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528309291-25579-1-git-send-email-scott.branden@broadcom.com>
On Wed, 6 Jun 2018 11:21:31 -0700, Scott Branden <scott.branden@broadcom.com> wrote:
> From: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
>
> Enable the HW rng driver "iproc-rng200" for all cygnus platforms.
>
> Signed-off-by: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
> ---
Applied to devicetree/next, thanks!
--
Florian
^ permalink raw reply
* [PATCH v2 1/1] ARM: dts: cygnus: enable iproc-hwrng
From: Clément Péron @ 2018-06-07 16:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c0b4d69d-2826-320e-974e-c7cdbf341747@gmail.com>
Hi Florian,
On Thu, 7 Jun 2018 at 18:35, Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On 06/06/2018 11:21 AM, Scott Branden wrote:
> > From: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
> >
> > Enable the HW rng driver "iproc-rng200" for all cygnus platforms.
> >
> > Signed-off-by: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
> > Reviewed-by: Ray Jui <ray.jui@broadcom.com>
> > Signed-off-by: Scott Branden <scott.branden@broadcom.com>
>
> Clement, do you want to test this and reported back?
Tested v1 and works fine on bcm58305
Tested-by: Cl?ment P?ron <peron.clem@gmail.com>
>
> > ---
> > arch/arm/boot/dts/bcm-cygnus.dtsi | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
> > index 9fe4f5a..b0e38fa 100644
> > --- a/arch/arm/boot/dts/bcm-cygnus.dtsi
> > +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
> > @@ -417,6 +417,11 @@
> > status = "disabled";
> > };
> >
> > + rng: rng at 18032000 {
> > + compatible = "brcm,iproc-rng200";
> > + reg = <0x18032000 0x28>;
> > + };
> > +
> > sdhci0: sdhci at 18041000 {
> > compatible = "brcm,sdhci-iproc-cygnus";
> > reg = <0x18041000 0x100>;
> >
>
>
> --
> Florian
^ permalink raw reply
* [PATCH v2 1/1] ARM: dts: cygnus: enable iproc-hwrng
From: Florian Fainelli @ 2018-06-07 16:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528309291-25579-1-git-send-email-scott.branden@broadcom.com>
On 06/06/2018 11:21 AM, Scott Branden wrote:
> From: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
>
> Enable the HW rng driver "iproc-rng200" for all cygnus platforms.
>
> Signed-off-by: Mohamed Ismail Abdul Packir Mohamed <mohamed-ismail.abdul@broadcom.com>
> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Clement, do you want to test this and reported back?
> ---
> arch/arm/boot/dts/bcm-cygnus.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
> index 9fe4f5a..b0e38fa 100644
> --- a/arch/arm/boot/dts/bcm-cygnus.dtsi
> +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
> @@ -417,6 +417,11 @@
> status = "disabled";
> };
>
> + rng: rng at 18032000 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0x18032000 0x28>;
> + };
> +
> sdhci0: sdhci at 18041000 {
> compatible = "brcm,sdhci-iproc-cygnus";
> reg = <0x18041000 0x100>;
>
--
Florian
^ permalink raw reply
* [alsa-devel] [PATCH 0/3] ASoC: stm32: sai: add support of iec958 controls
From: Arnaud Pouliquen @ 2018-06-07 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <s5hpo14w8k6.wl-tiwai@suse.de>
On 06/06/2018 11:47 AM, Takashi Iwai wrote:
> On Wed, 06 Jun 2018 11:31:45 +0200,
> Arnaud Pouliquen wrote:
>>
>>
>>
>> On 06/05/2018 08:29 PM, Takashi Iwai wrote:
>> > On Tue, 05 Jun 2018 17:50:57 +0200,
>> > Arnaud Pouliquen wrote:
>> >>
>> >> Hi Takashi,
>> >>
>> >> On 04/17/2018 01:17 PM, Mark Brown wrote:
>> >> > On Tue, Apr 17, 2018 at 08:29:17AM +0000, Olivier MOYSAN wrote:
>> >> >
>> >> >> I guess the blocking patch in this patchset is the patch "add IEC958
>> >> >> channel status control helper". This patch has been reviewed several
>> >> >> times, but did not get a ack so far.
>> >> >> If you think these helpers will not be merged, I will reintegrate the
>> >> >> corresponding code in stm driver.
>> >> >> Please let me know, if I need to prepare a v2 without helpers, or if we
>> >> >> can go further in the review of iec helpers patch ?
>> >> >
>> >> > I don't mind either way but you're right here, I'm waiting for Takashi
>> >> > to review the first patch.? I'd probably be OK with it just integrated
>> >> > into the driver if we have to go that way though.
>> >>
>> >> Gentlemen reminder for this patch set. We would appreciate to have your
>> >> feedback on iec helper.
>> >> From our point of view it could be useful to have a generic management
>> >> of the iec controls based on helpers instead of redefining them in DAIs.
>> >> Having the same behavior for these controls could be useful to ensure
>> >> coherence of the control management used by application (for instance
>> >> Gstreamer uses it to determine iec raw mode capability for iec61937 streams)
>> >
>> > Oh sorry for the late reply, I've totally overlooked the thread.
>> >
>> > And, another sorry: the patchset doesn't look convincing enough to
>> > me.
>> >
>> > First off, the provided API definition appears somewhat
>> > unconventional, the mixture of the ops, the static data and the
>> > dynamic data.
>> Sorry i can't figure out your point. I suppose that you speak about the
>> snd_pcm_iec958_params.
>> what would be a more conventional API?
>
> Imagine you'd want to put a const to the data passed to the API for
> hardening.? The current struct is a mixture of static and dynamic
> data.
>
>
>> > Moreover, this is only for your driver, ATM.?
>> It is also compatible with the sound/sti driver, even if we does not
>> propose patch yet. We also plan to propose an implementation, for the
>> HDMI_codec that would need to export a control to allow none-audio mode.
>>
>> >If it were an API that
>> > does clean up the already existing usages, I'd happily apply it. There
>> > are lots of drivers creating and controlling the IEC958 ctls even
>> > now.
>> >
>> > Also, the patchset requires more fine-tuning, in anyways.? The changes
>> > in create_iec958_consumre() are basically irrelevant, should be split
>> > off as an individual fix.? it is linked to the control, as not possible in existing implementation
>> (rate and width are get from hwparam or runtime). But no problem we can
>> split it in a separate patch.
>>
>> Also, the new function doesn't create the
>> > "XXX Mask" controls.? And the byte comparison should be replaced with
>> > memcmp(), etc, etc.
>> Yes mask are missing, can be added. For the rest could you comment
>> directly in code? i suppose that you want to replace the for loops by
>> memcmp, memcpy...
>
> Right.
>
>> > So, please proceed rather with the open codes for now.? If you can
>> > provide a patch that cleans up the *multiple* driver codes, again,
>> > I'll happily take it.? But it can be done anytime later, too.
>> Not simple to clean up the other drivers as this control is a PCM
>> control, that is mainly implemented as a mixer or card control.
>> This means that it should be registered on the pcm_new in CPU DAI or in
>> the DAI codec, to be able to bind it to the PCM device.
>> Inpact is not straigthforward as this could generate regression on driver.
>
> Yes, and that's my point.? The application of API is relatively
> limited -- although the API itself has nothing to do with ASoC at
> all.
>
>> For now We can add the clean up on the sti driver based on this helper,
>> and we are working on the HDMI_codec, we could also use this helper to
>> export the control....
>>
>> So if you estimate that it is interesting to purchase on this helper we
>> can try to come back with a patch set that implements the helper for
>> the 3 drivers.
>
> Right.? Basically there are two cases we add a new API:
>
> 1. It's absolutely new and nothing else can do it
> 2. API simplifies the whole tree, not only one you're trying to add.
>
> And in this case, let's prove 2 at first, that the API *is* actually
> useful in multiple situations we already have.? Then I'll happily ack
> for that.? More drivers cleanup, better.? At best, think of more
> range above ASoC, as you're proposing ALSA core API, not the ASoC
> one.
>
>> The other option, is that we drop the helpers, and implement the control
>> directly in our drivers.
>
> This is of course another, maybe easier option.
>
>> Please just tell us if we should continue to propose the helpers or not.
>
> I have no preference over two ways, but am only interested in the
> resulting patches :)
My tentative here was to start to introduce helpers at ALSA level (not
only ASoC) to have a generic implementation of the this generic control.
Today the snd_pcm_create_iec958_consumer_hw_params just allow to fill
AES based on runtime parameters, but not to offer a generic management
of iec control.
Now you are right i'm developing under ASoC and i have not the whole
knowledge of the ALSA drivers, an probably too limited view of the iec
controls usage.
Based on your feedback i think (at least in a first step) we will choose
the easiest option for the STM driver...
Thanks
Arnaud
>
>
> thanks,
>
> Takashi
^ permalink raw reply
* [PATCH] perf: xgene: Fix IOB SLOW PMU parser error
From: Will Deacon @ 2018-06-07 16:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528319214-19726-1-git-send-email-hoan.tran@amperecomputing.com>
On Wed, Jun 06, 2018 at 02:06:54PM -0700, Hoan Tran wrote:
> This patch fixes the below parser error of the IOB SLOW PMU.
>
> # perf stat -a -e iob-slow0/cycle-count/ sleep 1
> evenf syntax error: 'iob-slow0/cycle-count/'
> \___ parser error
>
> It replaces the "-" character by "_" character inside the PMU name.
>
> Signed-off-by: Hoan Tran <hoan.tran@amperecomputing.com>
Hmm, why did you only notice this now? :(
Anyway, whilst this could in theory break something, we did this for the CPU
PMUs in the past without issues so I'll pick this up.
Cheers,
Will
^ permalink raw reply
* [PATCH v4 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver
From: Rob Herring @ 2018-06-07 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <OSBPR01MB205442B483C792125E6A6AF7D2640@OSBPR01MB2054.jpnprd01.prod.outlook.com>
On Thu, Jun 7, 2018 at 1:59 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> On 06 June 2018 22:53, Frank wrote:
>> On 06/06/18 14:48, Frank Rowand wrote:
>> > On 06/05/18 23:36, Michel Pollet wrote:
>> >> Hi Frank,
>> >>
>> >> On 05 June 2018 18:34, Frank wrote:
>> >>> On 06/05/18 04:28, Michel Pollet wrote:
>> >>>> The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot
>> >>>> time, it requires a special enable method to get it started.
[...]
>> >>>> + * The second CPU is parked in ROM at boot time. It requires
>> >>>> +waking it after
>> >>>> + * writing an address into the BOOTADDR register of sysctrl.
>> >>>> + *
>> >>>> + * So the default value of the "cpu-release-addr" corresponds to
>> >>> BOOTADDR...
>> >>>> + *
>> >>>> + * *However* the BOOTADDR register is not available when the
>> >>>> +kernel
>> >>>> + * starts in NONSEC mode.
>> >>>> + *
>> >>>> + * So for NONSEC mode, the bootloader re-parks the second CPU into
>> >>>> +a pen
>> >>>> + * in SRAM, and changes the "cpu-release-addr" of linux's DT to a
>> >>>> +SRAM address,
>> >>>> + * which is not restricted.
>> >>>
>> >>> The binding document for cpu-release-addr does not have a definition
>> >>> for 32 bit arm. The existing definition is only 64 bit arm. Please
>> >>> add the definition for 32 bit arm to patch 1.
>> >>
>> >> Hmmm I do find a definition in
>> >> Documentation/devicetree/bindings/arm/cpus.txt -- just under where I
>> >> added my 'enable-method' -- And it is already used as 32 bits in at
>> >> least arch/arm/boot/dts/stih407-family.dtsi.
>> >
>> > If the correct answer is for cpu-release-addr to be 64 bits in certain
>> > cases (that discussion is ongoing further downthread) then one
>> > approach to maintain compatibility _and_ to fix the devicetree source
>> > files is to change the source code that currently gets
>> > cpu-release-addr as a
>> > 32 bit object to check the size of the property and get it as either a
>> > 32 bit or 64 bit object, based on the actual size of the property in
>> > the device tree and then change the value in the devicetree source
>> > files to be two cells. BUT this does not consider the bootloader
>> > complication. arch/arm/boot/dts/axm5516-cpus.dtsi has a note "//
>> > Fixed by the boot loader", so the boot loader also has to be modified
>> > to be able to handle the possibility that the property could be either
>> > 32 bits or 64 bits. I don't know how to maintain compatibility with
>> > the boot loader since we can't force it to change synchronously with
>> > changes in the kernel.
>> >
>> > You can consider this comment to be a drive-by observation. I think
>> > Rob and Geert and people like that are likely to be more helpful with
>> > what to actually do, and you can treat my comment more as pointing out
>> > the issue than as providing the perfect solution.
>>
>> Darn it, hit <send> too quickly.
>>
>> I meant to mention that there are several devicetree source files that have a
>> single cell value for cpu-release-addr, and thus potentially face the same
>> situation, depending on what the final decision is on the proper size for cpu-
>> release-addr. As of v4.17, a git grep shows one cell values in:
>>
>> arch/arm/boot/dts/axm5516-cpus.dtsi
>> arch/arm/boot/dts/stih407-family.dtsi
>> arch/arm/boot/dts/stih418.dtsi
>
> Yes, I had grepped before I used 32 bits on mine...
>
> Now, what is the decision here? Our bootloader is already modified to set it to 32 bits, so I propose that
And too late to fix the bootloader?
>
> + I change the driver to handle 32 and 64 bits properties
That's fine if you can't fix the bootloader.
> + I add this to the cpu.txt, as a separate patch:
> # On other systems, the property can be either
> 32 bits or 64 bits, it is the driver's responsibility
> to deal with either sizes.
That is definitely not what we want to say. Use of 32-bit should be
considered out of spec. Yes, we have a few platforms in that category,
but they already handle that themselves. Would be nice to fix them,
but at least the STi platforms don't seem too active.
IMO, we should delete whatever text we can here and at most just refer
to the spec.
Rob
^ permalink raw reply
* "media: ov5640: Add horizontal and vertical totals" regression issue on i.MX6QDL
From: Maxime Ripard @ 2018-06-07 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMty3ZCjNHUeHAJCDjoTHh_w1nNkUFTLjbp1=sYuF2DRiz-E-g@mail.gmail.com>
On Thu, Jun 07, 2018 at 08:02:28PM +0530, Jagan Teki wrote:
> Hi,
>
> ov5640 camera is breaking with below commit on i.MXQDL platform.
>
> commit 476dec012f4c6545b0b7599cd9adba2ed819ad3b
> Author: Maxime Ripard <maxime.ripard@bootlin.com>
> Date: Mon Apr 16 08:36:55 2018 -0400
>
> media: ov5640: Add horizontal and vertical totals
>
> All the initialization arrays are changing the horizontal and vertical
> totals for some value.
>
> In order to clean up the driver, and since we're going to need that value
> later on, let's introduce in the ov5640_mode_info structure the horizontal
> and vertical total sizes, and move these out of the bytes array.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
>
> We have reproduced as below [1] and along with ipu1_csi0 pipeline. I
> haven't debug further please let us know how to move further.
>
> media-ctl --links "'ov5640 2-003c':0->'imx6-mipi-csi2':0[1]"
> media-ctl --links "'imx6-mipi-csi2':1->'ipu1_csi0_mux':0[1]"
> media-ctl --links "'ipu1_csi0_mux':2->'ipu1_csi0':0[1]"
> media-ctl --links "'ipu1_csi0':2->'ipu1_csi0 capture':0[1]"
>
> media-ctl --set-v4l2 "'ov5640 2-003c':0[fmt:UYVY2X8/640x480 field:none]"
> media-ctl --set-v4l2 "'imx6-mipi-csi2':1[fmt:UYVY2X8/640x480 field:none]"
> media-ctl --set-v4l2 "'ipu1_csi0_mux':2[fmt:UYVY2X8/640x480 field:none]"
> media-ctl --set-v4l2 "'ipu1_csi0':0[fmt:AYUV32/640x480 field:none]"
> media-ctl --set-v4l2 "'ipu1_csi0':2[fmt:AYUV32/640x480 field:none]"
>
> [1] https://lkml.org/lkml/2018/5/31/543
Yeah, this has already been reported as part as this serie:
https://www.mail-archive.com/linux-media at vger.kernel.org/msg131655.html
and some suggestions have been done here:
https://www.mail-archive.com/linux-media at vger.kernel.org/msg132570.html
Feel free to help debug this.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH 3/3] rtc: ftrtc010: let the core handle range
From: Hans Ulli Kroll @ 2018-06-07 14:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604141528.15635-3-alexandre.belloni@bootlin.com>
On Mon, 4 Jun 2018, Alexandre Belloni wrote:
> The current range handling is highly suspicious. Anyway, let the core
> handle it.
> The RTC has a 32 bit counter on top of days + hh:mm:ss registers.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/rtc/rtc-ftrtc010.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/rtc/rtc-ftrtc010.c b/drivers/rtc/rtc-ftrtc010.c
> index 2cdc78ffeb17..61f798c6101f 100644
> --- a/drivers/rtc/rtc-ftrtc010.c
> +++ b/drivers/rtc/rtc-ftrtc010.c
> @@ -95,9 +95,6 @@ static int ftrtc010_rtc_set_time(struct device *dev, struct rtc_time *tm)
> u32 sec, min, hour, day, offset;
> timeu64_t time;
>
> - if (tm->tm_year >= 2148) /* EPOCH Year + 179 */
> - return -EINVAL;
> -
> time = rtc_tm_to_time64(tm);
>
> sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND);
> @@ -120,6 +117,7 @@ static const struct rtc_class_ops ftrtc010_rtc_ops = {
>
> static int ftrtc010_rtc_probe(struct platform_device *pdev)
> {
> + u32 days, hour, min, sec;
> struct ftrtc010_rtc *rtc;
> struct device *dev = &pdev->dev;
> struct resource *res;
> @@ -172,6 +170,15 @@ static int ftrtc010_rtc_probe(struct platform_device *pdev)
>
> rtc->rtc_dev->ops = &ftrtc010_rtc_ops;
>
> + sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND);
> + min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE);
> + hour = readl(rtc->rtc_base + FTRTC010_RTC_HOUR);
> + days = readl(rtc->rtc_base + FTRTC010_RTC_DAYS);
> +
> + rtc->rtc_dev->range_min = (u64)days * 86400 + hour * 3600 +
> + min * 60 + sec;
> + rtc->rtc_dev->range_max = U32_MAX + rtc->rtc_dev->range_min;
> +
> ret = devm_request_irq(dev, rtc->rtc_irq, ftrtc010_rtc_interrupt,
> IRQF_SHARED, pdev->name, dev);
> if (unlikely(ret))
> --
> 2.17.1
>
>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
^ permalink raw reply
* [PATCH 2/3] rtc: ftrtc010: handle dates after 2106
From: Hans Ulli Kroll @ 2018-06-07 14:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604141528.15635-2-alexandre.belloni@bootlin.com>
On Mon, 4 Jun 2018, Alexandre Belloni wrote:
> Use correct types for offset and time and use
> rtc_time64_to_tm/rtc_tm_to_time64 to handle dates after 2106 properly.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/rtc/rtc-ftrtc010.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/rtc/rtc-ftrtc010.c b/drivers/rtc/rtc-ftrtc010.c
> index 165d0b62db00..2cdc78ffeb17 100644
> --- a/drivers/rtc/rtc-ftrtc010.c
> +++ b/drivers/rtc/rtc-ftrtc010.c
> @@ -73,8 +73,8 @@ static int ftrtc010_rtc_read_time(struct device *dev, struct rtc_time *tm)
> {
> struct ftrtc010_rtc *rtc = dev_get_drvdata(dev);
>
> - unsigned int days, hour, min, sec;
> - unsigned long offset, time;
> + u32 days, hour, min, sec, offset;
> + timeu64_t time;
>
> sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND);
> min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE);
> @@ -84,7 +84,7 @@ static int ftrtc010_rtc_read_time(struct device *dev, struct rtc_time *tm)
>
> time = offset + days * 86400 + hour * 3600 + min * 60 + sec;
>
> - rtc_time_to_tm(time, tm);
> + rtc_time64_to_tm(time, tm);
>
> return 0;
> }
> @@ -92,13 +92,13 @@ static int ftrtc010_rtc_read_time(struct device *dev, struct rtc_time *tm)
> static int ftrtc010_rtc_set_time(struct device *dev, struct rtc_time *tm)
> {
> struct ftrtc010_rtc *rtc = dev_get_drvdata(dev);
> - unsigned int sec, min, hour, day;
> - unsigned long offset, time;
> + u32 sec, min, hour, day, offset;
> + timeu64_t time;
>
> if (tm->tm_year >= 2148) /* EPOCH Year + 179 */
> return -EINVAL;
>
> - rtc_tm_to_time(tm, &time);
> + time = rtc_tm_to_time64(tm);
>
> sec = readl(rtc->rtc_base + FTRTC010_RTC_SECOND);
> min = readl(rtc->rtc_base + FTRTC010_RTC_MINUTE);
> --
> 2.17.1
>
>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
^ permalink raw reply
* [PATCH 1/3] rtc: ftrtc010: switch to devm_rtc_allocate_device
From: Hans Ulli Kroll @ 2018-06-07 14:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604141528.15635-1-alexandre.belloni@bootlin.com>
On Mon, 4 Jun 2018, Alexandre Belloni wrote:
> Switch to devm_rtc_allocate_device/rtc_register_device. This allow or
> further improvement and simplifies ftrtc010_rtc_remove().
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/rtc/rtc-ftrtc010.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/rtc/rtc-ftrtc010.c b/drivers/rtc/rtc-ftrtc010.c
> index af8d6beae20c..165d0b62db00 100644
> --- a/drivers/rtc/rtc-ftrtc010.c
> +++ b/drivers/rtc/rtc-ftrtc010.c
> @@ -166,14 +166,18 @@ static int ftrtc010_rtc_probe(struct platform_device *pdev)
> if (!rtc->rtc_base)
> return -ENOMEM;
>
> + rtc->rtc_dev = devm_rtc_allocate_device(dev);
> + if (IS_ERR(rtc->rtc_dev))
> + return PTR_ERR(rtc->rtc_dev);
> +
> + rtc->rtc_dev->ops = &ftrtc010_rtc_ops;
> +
> ret = devm_request_irq(dev, rtc->rtc_irq, ftrtc010_rtc_interrupt,
> IRQF_SHARED, pdev->name, dev);
> if (unlikely(ret))
> return ret;
>
> - rtc->rtc_dev = rtc_device_register(pdev->name, dev,
> - &ftrtc010_rtc_ops, THIS_MODULE);
> - return PTR_ERR_OR_ZERO(rtc->rtc_dev);
> + return rtc_register_device(rtc->rtc_dev);
> }
>
> static int ftrtc010_rtc_remove(struct platform_device *pdev)
> @@ -184,7 +188,6 @@ static int ftrtc010_rtc_remove(struct platform_device *pdev)
> clk_disable_unprepare(rtc->extclk);
> if (!IS_ERR(rtc->pclk))
> clk_disable_unprepare(rtc->pclk);
> - rtc_device_unregister(rtc->rtc_dev);
>
> return 0;
> }
> --
> 2.17.1
>
>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
^ permalink raw reply
* "media: ov5640: Add horizontal and vertical totals" regression issue on i.MX6QDL
From: Jagan Teki @ 2018-06-07 14:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
ov5640 camera is breaking with below commit on i.MXQDL platform.
commit 476dec012f4c6545b0b7599cd9adba2ed819ad3b
Author: Maxime Ripard <maxime.ripard@bootlin.com>
Date: Mon Apr 16 08:36:55 2018 -0400
media: ov5640: Add horizontal and vertical totals
All the initialization arrays are changing the horizontal and vertical
totals for some value.
In order to clean up the driver, and since we're going to need that value
later on, let's introduce in the ov5640_mode_info structure the horizontal
and vertical total sizes, and move these out of the bytes array.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
We have reproduced as below [1] and along with ipu1_csi0 pipeline. I
haven't debug further please let us know how to move further.
media-ctl --links "'ov5640 2-003c':0->'imx6-mipi-csi2':0[1]"
media-ctl --links "'imx6-mipi-csi2':1->'ipu1_csi0_mux':0[1]"
media-ctl --links "'ipu1_csi0_mux':2->'ipu1_csi0':0[1]"
media-ctl --links "'ipu1_csi0':2->'ipu1_csi0 capture':0[1]"
media-ctl --set-v4l2 "'ov5640 2-003c':0[fmt:UYVY2X8/640x480 field:none]"
media-ctl --set-v4l2 "'imx6-mipi-csi2':1[fmt:UYVY2X8/640x480 field:none]"
media-ctl --set-v4l2 "'ipu1_csi0_mux':2[fmt:UYVY2X8/640x480 field:none]"
media-ctl --set-v4l2 "'ipu1_csi0':0[fmt:AYUV32/640x480 field:none]"
media-ctl --set-v4l2 "'ipu1_csi0':2[fmt:AYUV32/640x480 field:none]"
[1] https://lkml.org/lkml/2018/5/31/543
Jagan.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
^ permalink raw reply
* [PATCH v2] arm64: topology: Avoid checking numa mask for scheduler MC selection
From: Geert Uytterhoeven @ 2018-06-07 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606163846.495725-1-jeremy.linton@arm.com>
Hi Jeremy,
On Wed, Jun 6, 2018 at 6:38 PM, Jeremy Linton <jeremy.linton@arm.com> wrote:
> The numa mask subset check can often lead to system hang or crash during
> CPU hotplug and system suspend operation if NUMA is disabled. This is
Also during boot, if CONFIG_ARM_PSCI_CHECKER=y.
> mostly observed on HMP systems where the CPU compute capacities are
> different and ends up in different scheduler domains. Since
> cpumask_of_node is returned instead core_sibling, the scheduler is
> confused with incorrect cpumasks(e.g. one CPU in two different sched
> domains at the same time) on CPU hotplug.
>
> Lets disable the NUMA siblings checks for the time being, as NUMA in
> socket machines have LLC's that will assure that the scheduler topology
> isn't "borken".
>
> The NUMA check exists to assure that if a LLC within a socket crosses
> NUMA nodes/chiplets the scheduler domains remain consistent. This code will
> likely have to be re-enabled in the near future once the NUMA mask story
> is sorted. At the moment its not necessary because the NUMA in socket
> machines LLC's are contained within the NUMA domains.
>
> Further, as a defensive mechanism during hot-plug, lets assure that the
> LLC siblings are also masked.
>
> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Thanks!
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm64/kernel/topology.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> index 7415c166281f..f845a8617812 100644
> --- a/arch/arm64/kernel/topology.c
> +++ b/arch/arm64/kernel/topology.c
> @@ -215,13 +215,8 @@ EXPORT_SYMBOL_GPL(cpu_topology);
>
> const struct cpumask *cpu_coregroup_mask(int cpu)
> {
> - const cpumask_t *core_mask = cpumask_of_node(cpu_to_node(cpu));
> + const cpumask_t *core_mask = &cpu_topology[cpu].core_sibling;
>
> - /* Find the smaller of NUMA, core or LLC siblings */
> - if (cpumask_subset(&cpu_topology[cpu].core_sibling, core_mask)) {
> - /* not numa in package, lets use the package siblings */
> - core_mask = &cpu_topology[cpu].core_sibling;
> - }
> if (cpu_topology[cpu].llc_id != -1) {
> if (cpumask_subset(&cpu_topology[cpu].llc_siblings, core_mask))
> core_mask = &cpu_topology[cpu].llc_siblings;
> @@ -239,8 +234,10 @@ static void update_siblings_masks(unsigned int cpuid)
> for_each_possible_cpu(cpu) {
> cpu_topo = &cpu_topology[cpu];
>
> - if (cpuid_topo->llc_id == cpu_topo->llc_id)
> + if (cpuid_topo->llc_id == cpu_topo->llc_id) {
> cpumask_set_cpu(cpu, &cpuid_topo->llc_siblings);
> + cpumask_set_cpu(cpuid, &cpu_topo->llc_siblings);
> + }
>
> if (cpuid_topo->package_id != cpu_topo->package_id)
> continue;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2] ARM: multi_v7_defconfig: Add Marvell NAND controller support
From: Gregory CLEMENT @ 2018-06-07 14:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180528151357.29203-1-gregory.clement@bootlin.com>
Hi,
On lun., mai 28 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:
> Add Marvell NAND controller support used by some Marvell Armada based
> boards.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Changelog v1 -> v2:
>
> - Rebased on v4.17-rc1 (Dropped "ARM: multi_v7_defconfig: Update with
> current configuration")
I would like to be sure that you don't miss it. I didn't sent a PR for
it but just a patch as you asked me however I still didn't see it in
arm-soc/for-next.
Thanks,
Gregory
>
> arch/arm/configs/multi_v7_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index e6b3c96d4c09..3fcb17b38f50 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -210,6 +210,7 @@ CONFIG_MTD_NAND_DENALI_DT=y
> CONFIG_MTD_NAND_OMAP2=y
> CONFIG_MTD_NAND_OMAP_BCH=y
> CONFIG_MTD_NAND_ATMEL=y
> +CONFIG_MTD_NAND_MARVELL=y
> CONFIG_MTD_NAND_GPMI_NAND=y
> CONFIG_MTD_NAND_BRCMNAND=y
> CONFIG_MTD_NAND_VF610_NFC=y
> --
> 2.17.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* [xlnx:master 1122/1659] drivers/mtd/spi-nor/spi-nor.c:3334:14: error: implicit declaration of function 'of_get_next_parent'; did you mean 'of_get_parent'?
From: kbuild test robot @ 2018-06-07 14:12 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx master
head: c2ba891326bb472da59b6a2da29aca218d337687
commit: 818f168696f561c127f161379eb5b8d1835218a2 [1122/1659] Merge tag 'v4.14' into master
config: x86_64-randconfig-i0-201822 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
git checkout 818f168696f561c127f161379eb5b8d1835218a2
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/mtd/spi-nor/spi-nor.c: In function 'spi_nor_scan':
>> drivers/mtd/spi-nor/spi-nor.c:3334:14: error: implicit declaration of function 'of_get_next_parent'; did you mean 'of_get_parent'? [-Werror=implicit-function-declaration]
np_spi = of_get_next_parent(np);
^~~~~~~~~~~~~~~~~~
of_get_parent
drivers/mtd/spi-nor/spi-nor.c:3334:12: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
np_spi = of_get_next_parent(np);
^
drivers/mtd/spi-nor/spi-nor.c:3080:6: warning: unused variable 'is_dual' [-Wunused-variable]
u32 is_dual;
^~~~~~~
At top level:
drivers/mtd/spi-nor/spi-nor.c:323:12: warning: 'read_ear' defined but not used [-Wunused-function]
static int read_ear(struct spi_nor *nor, struct flash_info *info)
^~~~~~~~
Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls64
Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u64
Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
Cyclomatic Complexity 1 include/linux/math64.h:div_u64_rem
Cyclomatic Complexity 1 include/linux/kobject.h:kobject_name
Cyclomatic Complexity 2 include/linux/device.h:dev_name
Cyclomatic Complexity 1 include/linux/device.h:dev_of_node
Cyclomatic Complexity 68 include/linux/slab.h:kmalloc_large
Cyclomatic Complexity 3 include/linux/slab.h:kmalloc
Cyclomatic Complexity 1 include/linux/of.h:of_find_property
Cyclomatic Complexity 1 include/linux/of.h:of_property_match_string
Cyclomatic Complexity 1 include/linux/of.h:of_property_read_bool
Cyclomatic Complexity 1 include/linux/mtd/mtd.h:mtd_get_of_node
Cyclomatic Complexity 1 include/linux/mtd/spi-nor.h:spi_nor_get_protocol_data_nbits
Cyclomatic Complexity 1 include/linux/mtd/spi-nor.h:spi_nor_get_protocol_width
Cyclomatic Complexity 1 include/linux/mtd/spi-nor.h:spi_nor_get_flash_node
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:write_sr
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:write_enable
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:write_disable
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:mtd_to_spi_nor
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_convert_opcode
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_convert_3to4_read
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_convert_3to4_program
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_convert_3to4_erase
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_set_4byte_opcodes
Cyclomatic Complexity 6 drivers/mtd/spi-nor/spi-nor.c:set_4byte
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_s3an_addr_convert
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:spi_nor_erase_sector
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:min_lockable_sectors
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:get_protected_area_start
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:min_protected_area_including_offset
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:bp_bits_from_sr
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:stm_get_locked_range
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:stm_check_lock_status_sr
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:stm_is_locked_sr
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:stm_is_unlocked_sr
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_set_read_settings
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_set_pp_settings
Cyclomatic Complexity 5 drivers/mtd/spi-nor/spi-nor.c:spi_nor_read_sfdp
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_set_read_settings_from_bfpt
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_hwcaps2cmd
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_hwcaps_read2cmd
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_hwcaps_pp2cmd
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_select_read
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_select_pp
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_select_erase
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:read_cr
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:s3an_sr_ready
Cyclomatic Complexity 10 drivers/mtd/spi-nor/spi-nor.c:spi_nor_setup
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:s3an_nor_scan
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_lock_and_prep
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_unlock_and_unprep
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_is_locked
Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:read_sr
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:stm_is_locked
Cyclomatic Complexity 5 drivers/mtd/spi-nor/spi-nor.c:spi_nor_sr_ready
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:read_fsr
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spi_nor_fsr_ready
Cyclomatic Complexity 5 drivers/mtd/spi-nor/spi-nor.c:spi_nor_ready
Cyclomatic Complexity 6 drivers/mtd/spi-nor/spi-nor.c:spi_nor_check
Cyclomatic Complexity 66 include/linux/log2.h:__order_base_2
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:spi_nor_wait_till_ready_with_timeout
Cyclomatic Complexity 1 drivers/mtd/spi-nor/spi-nor.c:spi_nor_wait_till_ready
Cyclomatic Complexity 10 drivers/mtd/spi-nor/spi-nor.c:write_ear
Cyclomatic Complexity 19 drivers/mtd/spi-nor/spi-nor.c:spi_nor_write
Cyclomatic Complexity 15 drivers/mtd/spi-nor/spi-nor.c:sst_write
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:write_sr_cr
Cyclomatic Complexity 6 drivers/mtd/spi-nor/spi-nor.c:write_sr_modify_protection
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:spi_nor_unlock
Cyclomatic Complexity 4 drivers/mtd/spi-nor/spi-nor.c:spansion_quad_enable
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:spansion_read_cr_quad_enable
Cyclomatic Complexity 2 drivers/mtd/spi-nor/spi-nor.c:spansion_no_read_cr_quad_enable
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:spi_nor_lock
Cyclomatic Complexity 144 drivers/mtd/spi-nor/spi-nor.c:stm_unlock
Cyclomatic Complexity 141 drivers/mtd/spi-nor/spi-nor.c:stm_lock
Cyclomatic Complexity 18 drivers/mtd/spi-nor/spi-nor.c:spi_nor_read
Cyclomatic Complexity 5 drivers/mtd/spi-nor/spi-nor.c:erase_chip
Cyclomatic Complexity 17 drivers/mtd/spi-nor/spi-nor.c:spi_nor_erase
Cyclomatic Complexity 6 drivers/mtd/spi-nor/spi-nor.c:macronix_quad_enable
Cyclomatic Complexity 7 drivers/mtd/spi-nor/spi-nor.c:sr2_bit7_quad_enable
Cyclomatic Complexity 3 drivers/mtd/spi-nor/spi-nor.c:spi_nor_match_id
vim +3334 drivers/mtd/spi-nor/spi-nor.c
b199489d3 Huang Shijie 2014-02-24 3270
b199489d3 Huang Shijie 2014-02-24 3271 if (info->flags & SPI_NOR_NO_ERASE)
b199489d3 Huang Shijie 2014-02-24 3272 mtd->flags |= MTD_NO_ERASE;
b199489d3 Huang Shijie 2014-02-24 3273
29e641775 Naga Sureshkumar Relli 2017-03-06 3274 nor->jedec_id = info->id[0];
b199489d3 Huang Shijie 2014-02-24 3275 mtd->dev.parent = dev;
cfc5604c4 Cyrille Pitchen 2017-04-25 3276 nor->page_size = params.page_size;
b199489d3 Huang Shijie 2014-02-24 3277 mtd->writebufsize = nor->page_size;
b199489d3 Huang Shijie 2014-02-24 3278
b199489d3 Huang Shijie 2014-02-24 3279 if (np) {
b199489d3 Huang Shijie 2014-02-24 3280 /* If we were instantiated by DT, use it */
b199489d3 Huang Shijie 2014-02-24 3281 if (of_property_read_bool(np, "m25p,fast-read"))
cfc5604c4 Cyrille Pitchen 2017-04-25 3282 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
b199489d3 Huang Shijie 2014-02-24 3283 else
cfc5604c4 Cyrille Pitchen 2017-04-25 3284 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
b199489d3 Huang Shijie 2014-02-24 3285 } else {
b199489d3 Huang Shijie 2014-02-24 3286 /* If we weren't instantiated by DT, default to fast-read */
cfc5604c4 Cyrille Pitchen 2017-04-25 3287 params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
b199489d3 Huang Shijie 2014-02-24 3288 }
b199489d3 Huang Shijie 2014-02-24 3289
b199489d3 Huang Shijie 2014-02-24 3290 /* Some devices cannot do fast-read, no matter what DT tells us */
b199489d3 Huang Shijie 2014-02-24 3291 if (info->flags & SPI_NOR_NO_FR)
cfc5604c4 Cyrille Pitchen 2017-04-25 3292 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
b199489d3 Huang Shijie 2014-02-24 3293
cfc5604c4 Cyrille Pitchen 2017-04-25 3294 /*
cfc5604c4 Cyrille Pitchen 2017-04-25 3295 * Configure the SPI memory:
cfc5604c4 Cyrille Pitchen 2017-04-25 3296 * - select op codes for (Fast) Read, Page Program and Sector Erase.
cfc5604c4 Cyrille Pitchen 2017-04-25 3297 * - set the number of dummy cycles (mode cycles + wait states).
cfc5604c4 Cyrille Pitchen 2017-04-25 3298 * - set the SPI protocols for register and memory accesses.
cfc5604c4 Cyrille Pitchen 2017-04-25 3299 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
cfc5604c4 Cyrille Pitchen 2017-04-25 3300 */
cfc5604c4 Cyrille Pitchen 2017-04-25 3301 ret = spi_nor_setup(nor, info, ¶ms, hwcaps);
cfc5604c4 Cyrille Pitchen 2017-04-25 3302 if (ret)
b199489d3 Huang Shijie 2014-02-24 3303 return ret;
b199489d3 Huang Shijie 2014-02-24 3304
f384b352c Cyrille Pitchen 2017-06-26 3305 if (nor->addr_width) {
f384b352c Cyrille Pitchen 2017-06-26 3306 /* already configured from SFDP */
f384b352c Cyrille Pitchen 2017-06-26 3307 } else if (info->addr_width) {
b199489d3 Huang Shijie 2014-02-24 3308 nor->addr_width = info->addr_width;
f384b352c Cyrille Pitchen 2017-06-26 3309 } else if (mtd->size > 0x1000000) {
1e7078305 Michal Simek 2017-01-24 3310 #ifdef CONFIG_OF
1e7078305 Michal Simek 2017-01-24 3311 np_spi = of_get_next_parent(np);
1e7078305 Michal Simek 2017-01-24 3312 if (of_property_match_string(np_spi, "compatible",
1e7078305 Michal Simek 2017-01-24 3313 "xlnx,zynq-qspi-1.0") >= 0) {
1e7078305 Michal Simek 2017-01-24 3314 int status;
1e7078305 Michal Simek 2017-01-24 3315
1e7078305 Michal Simek 2017-01-24 3316 nor->addr_width = 3;
1e7078305 Michal Simek 2017-01-24 3317 set_4byte(nor, info, 0);
1e7078305 Michal Simek 2017-01-24 3318 status = read_ear(nor, info);
1e7078305 Michal Simek 2017-01-24 3319 if (status < 0)
1e7078305 Michal Simek 2017-01-24 3320 dev_warn(dev, "failed to read ear reg\n");
1e7078305 Michal Simek 2017-01-24 3321 else
1e7078305 Michal Simek 2017-01-24 3322 nor->curbank = status & EAR_SEGMENT_MASK;
1e7078305 Michal Simek 2017-01-24 3323 } else {
1e7078305 Michal Simek 2017-01-24 3324 #endif
818f16869 Michal Simek 2018-01-11 3325 /*
818f16869 Michal Simek 2018-01-11 3326 * enable 4-byte addressing
818f16869 Michal Simek 2018-01-11 3327 * if the device exceeds 16MiB
818f16869 Michal Simek 2018-01-11 3328 */
b199489d3 Huang Shijie 2014-02-24 3329 nor->addr_width = 4;
ba3ae6a1d Cyrille Pitchen 2016-10-27 3330 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
ba3ae6a1d Cyrille Pitchen 2016-10-27 3331 info->flags & SPI_NOR_4B_OPCODES)
ba3ae6a1d Cyrille Pitchen 2016-10-27 3332 spi_nor_set_4byte_opcodes(nor, info);
818f16869 Michal Simek 2018-01-11 3333 else {
d80f6153e Naga Sureshkumar Relli 2017-04-18 @3334 np_spi = of_get_next_parent(np);
818f16869 Michal Simek 2018-01-11 3335 if (of_property_match_string(np_spi,
818f16869 Michal Simek 2018-01-11 3336 "compatible",
d80f6153e Naga Sureshkumar Relli 2017-04-18 3337 "xlnx,xps-spi-2.00.a") >= 0) {
d80f6153e Naga Sureshkumar Relli 2017-04-18 3338 nor->addr_width = 3;
d80f6153e Naga Sureshkumar Relli 2017-04-18 3339 set_4byte(nor, info, 0);
d80f6153e Naga Sureshkumar Relli 2017-04-18 3340 } else {
d928a2593 Huang Shijie 2014-11-06 3341 set_4byte(nor, info, 1);
d859d3457 Anurag Kumar Vulisha 2015-05-13 3342 if (nor->isstacked) {
d80f6153e Naga Sureshkumar Relli 2017-04-18 3343 nor->spi->master->flags |=
d80f6153e Naga Sureshkumar Relli 2017-04-18 3344 SPI_MASTER_U_PAGE;
d859d3457 Anurag Kumar Vulisha 2015-05-13 3345 set_4byte(nor, info, 1);
d80f6153e Naga Sureshkumar Relli 2017-04-18 3346 nor->spi->master->flags &=
d80f6153e Naga Sureshkumar Relli 2017-04-18 3347 ~SPI_MASTER_U_PAGE;
d80f6153e Naga Sureshkumar Relli 2017-04-18 3348 }
d80f6153e Naga Sureshkumar Relli 2017-04-18 3349 }
d859d3457 Anurag Kumar Vulisha 2015-05-13 3350 }
1e7078305 Michal Simek 2017-01-24 3351 #ifdef CONFIG_OF
1e7078305 Michal Simek 2017-01-24 3352 }
1e7078305 Michal Simek 2017-01-24 3353 #endif
b199489d3 Huang Shijie 2014-02-24 3354 } else {
b199489d3 Huang Shijie 2014-02-24 3355 nor->addr_width = 3;
b199489d3 Huang Shijie 2014-02-24 3356 }
b199489d3 Huang Shijie 2014-02-24 3357
c67cbb839 Brian Norris 2015-11-10 3358 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
c67cbb839 Brian Norris 2015-11-10 3359 dev_err(dev, "address width is too large: %u\n",
c67cbb839 Brian Norris 2015-11-10 3360 nor->addr_width);
c67cbb839 Brian Norris 2015-11-10 3361 return -EINVAL;
c67cbb839 Brian Norris 2015-11-10 3362 }
c67cbb839 Brian Norris 2015-11-10 3363
e99ca98f1 Ricardo Ribalda Delgado 2016-12-02 3364 if (info->flags & SPI_S3AN) {
e99ca98f1 Ricardo Ribalda Delgado 2016-12-02 3365 ret = s3an_nor_scan(info, nor);
e99ca98f1 Ricardo Ribalda Delgado 2016-12-02 3366 if (ret)
e99ca98f1 Ricardo Ribalda Delgado 2016-12-02 3367 return ret;
e99ca98f1 Ricardo Ribalda Delgado 2016-12-02 3368 }
b199489d3 Huang Shijie 2014-02-24 3369
7ae20097f Naga Sureshkumar Relli 2017-01-30 3370 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
b199489d3 Huang Shijie 2014-02-24 3371 (long long)mtd->size >> 10);
b199489d3 Huang Shijie 2014-02-24 3372
7ae20097f Naga Sureshkumar Relli 2017-01-30 3373 dev_dbg(dev,
7ae20097f Naga Sureshkumar Relli 2017-01-30 3374 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
b199489d3 Huang Shijie 2014-02-24 3375 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
b199489d3 Huang Shijie 2014-02-24 3376 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
b199489d3 Huang Shijie 2014-02-24 3377 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
b199489d3 Huang Shijie 2014-02-24 3378
b199489d3 Huang Shijie 2014-02-24 3379 if (mtd->numeraseregions)
b199489d3 Huang Shijie 2014-02-24 3380 for (i = 0; i < mtd->numeraseregions; i++)
7ae20097f Naga Sureshkumar Relli 2017-01-30 3381 dev_dbg(dev,
7ae20097f Naga Sureshkumar Relli 2017-01-30 3382 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
b199489d3 Huang Shijie 2014-02-24 3383 ".erasesize = 0x%.8x (%uKiB), "
b199489d3 Huang Shijie 2014-02-24 3384 ".numblocks = %d }\n",
b199489d3 Huang Shijie 2014-02-24 3385 i, (long long)mtd->eraseregions[i].offset,
b199489d3 Huang Shijie 2014-02-24 3386 mtd->eraseregions[i].erasesize,
b199489d3 Huang Shijie 2014-02-24 3387 mtd->eraseregions[i].erasesize / 1024,
b199489d3 Huang Shijie 2014-02-24 3388 mtd->eraseregions[i].numblocks);
b199489d3 Huang Shijie 2014-02-24 3389 return 0;
b199489d3 Huang Shijie 2014-02-24 3390 }
b61834b0d Brian Norris 2014-04-08 3391 EXPORT_SYMBOL_GPL(spi_nor_scan);
b199489d3 Huang Shijie 2014-02-24 3392
:::::: The code at line 3334 was first introduced by commit
:::::: d80f6153e7c446e0c7dc8400b06d199c50bfd509 mtd: spi-nor: Disable 4-Byte addressing for axi_quad_spi
:::::: TO: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
:::::: CC: Michal Simek <michal.simek@xilinx.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v6 5/5] ARM: dts: imx: add missing compatible and clock properties for EPIT
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add missing compatible and clock properties for EPIT node.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
arch/arm/boot/dts/imx25.dtsi | 8 ++++++--
arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
arch/arm/boot/dts/imx6sl.dtsi | 10 ++++++++--
arch/arm/boot/dts/imx6sx.dtsi | 10 ++++++++--
arch/arm/boot/dts/imx6ul.dtsi | 10 ++++++++--
5 files changed, 38 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index cf70df20b19c..15fd4308dad8 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -396,15 +396,19 @@
};
epit1: timer at 53f94000 {
- compatible = "fsl,imx25-epit";
+ compatible = "fsl,imx25-epit", "fsl,imx31-epit";
reg = <0x53f94000 0x4000>;
interrupts = <28>;
+ clocks = <&clks 83>;
+ status = "disabled";
};
epit2: timer at 53f98000 {
- compatible = "fsl,imx25-epit";
+ compatible = "fsl,imx25-epit", "fsl,imx31-epit";
reg = <0x53f98000 0x4000>;
interrupts = <27>;
+ clocks = <&clks 84>;
+ status = "disabled";
};
gpio4: gpio at 53f9c000 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index c003e62bf290..65c4ee07454c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -843,14 +843,20 @@
};
};
- epit1: epit at 20d0000 { /* EPIT1 */
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 { /* EPIT2 */
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ab6a7e2e7e8f..d63f8ebbc8a1 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -671,14 +671,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6sl-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6sl-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 49c7205b8db8..2b30559d3270 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -736,14 +736,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6sx-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6sx-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972b16ba..d5f765da1ee2 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -658,14 +658,20 @@
};
};
- epit1: epit at 20d0000 {
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6ul-epit", "fsl,imx31-epit";
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_EPIT1>;
+ status = "disabled";
};
- epit2: epit at 20d4000 {
+ epit2: timer at 20d4000 {
+ compatible = "fsl,imx6ul-epit", "fsl,imx31-epit";
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_EPIT2>;
+ status = "disabled";
};
src: src at 20d8000 {
--
2.17.1
^ permalink raw reply related
* [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Add driver for NXP's EPIT timer used in i.MX SoC.
Signed-off-by: Colin Didier <colin.didier@devialet.com>
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 265 +++++++++++++++++++++++++++
3 files changed, 277 insertions(+)
create mode 100644 drivers/clocksource/timer-imx-epit.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 8e8a09755d10..790478afd02c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -576,6 +576,17 @@ config H8300_TPU
This enables the clocksource for the H8300 platform with the
H8S2678 cpu.
+config CLKSRC_IMX_EPIT
+ bool "Clocksource using i.MX EPIT"
+ depends on CLKDEV_LOOKUP && (ARCH_MXC || COMPILE_TEST)
+ select CLKSRC_MMIO
+ help
+ This enables EPIT support available on some i.MX platforms.
+ Normally you don't have a reason to do so as the EPIT has
+ the same features and uses the same clocks as the GPT.
+ Anyway, on some systems the GPT may be in use for other
+ purposes.
+
config CLKSRC_IMX_GPT
bool "Clocksource using i.MX GPT" if COMPILE_TEST
depends on ARM && CLKDEV_LOOKUP
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 00caf37e52f9..d9426f69ec69 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
+obj-$(CONFIG_CLKSRC_IMX_EPIT) += timer-imx-epit.o
obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
diff --git a/drivers/clocksource/timer-imx-epit.c b/drivers/clocksource/timer-imx-epit.c
new file mode 100644
index 000000000000..15f70e210fad
--- /dev/null
+++ b/drivers/clocksource/timer-imx-epit.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
+ * Copyright (C) 2018 Cl?ment P?ron <clement.peron@devialet.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0c
+#define EPITCNR 0x10
+
+#define EPITCR_EN BIT(0)
+#define EPITCR_ENMOD BIT(1)
+#define EPITCR_OCIEN BIT(2)
+#define EPITCR_RLD BIT(3)
+#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
+#define EPITCR_SWR BIT(16)
+#define EPITCR_IOVW BIT(17)
+#define EPITCR_DBGEN BIT(18)
+#define EPITCR_WAITEN BIT(19)
+#define EPITCR_RES BIT(20)
+#define EPITCR_STOPEN BIT(21)
+#define EPITCR_OM_DISCON (0 << 22)
+#define EPITCR_OM_TOGGLE (1 << 22)
+#define EPITCR_OM_CLEAR (2 << 22)
+#define EPITCR_OM_SET (3 << 22)
+#define EPITCR_CLKSRC_OFF (0 << 24)
+#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
+#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
+#define EPITCR_CLKSRC_REF_LOW (3 << 24)
+
+#define EPITSR_OCIF BIT(0)
+
+struct epit_timer {
+ void __iomem *base;
+ int irq;
+ struct clk *clk;
+ struct clock_event_device ced;
+ struct irqaction act;
+};
+
+static void __iomem *sched_clock_reg;
+
+static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
+{
+ return container_of(ced, struct epit_timer, ced);
+}
+
+static inline void epit_irq_disable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static inline void epit_irq_enable(struct epit_timer *epittm)
+{
+ u32 val;
+
+ val = readl_relaxed(epittm->base + EPITCR);
+ writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
+}
+
+static void epit_irq_acknowledge(struct epit_timer *epittm)
+{
+ writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
+}
+
+static u64 notrace epit_read_sched_clock(void)
+{
+ return ~readl_relaxed(sched_clock_reg);
+}
+
+static int epit_set_next_event(unsigned long cycles,
+ struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long tcmp;
+
+ tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
+ writel_relaxed(tcmp, epittm->base + EPITCMPR);
+
+ return 0;
+}
+
+/* Left event sources disabled, no more interrupts appear */
+static int epit_shutdown(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt */
+ epit_irq_acknowledge(epittm);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int epit_set_oneshot(struct clock_event_device *ced)
+{
+ struct epit_timer *epittm = to_epit_timer(ced);
+ unsigned long flags;
+
+ /*
+ * The timer interrupt generation is disabled at least
+ * for enough time to call epit_set_next_event()
+ */
+ local_irq_save(flags);
+
+ /* Disable interrupt in EPIT module */
+ epit_irq_disable(epittm);
+
+ /* Clear pending interrupt, only while switching mode */
+ if (!clockevent_state_oneshot(ced))
+ epit_irq_acknowledge(epittm);
+
+ /*
+ * Do not put overhead of interrupt enable/disable into
+ * epit_set_next_event(), the core has about 4 minutes
+ * to call epit_set_next_event() or shutdown clock after
+ * mode switching
+ */
+ epit_irq_enable(epittm);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ced = dev_id;
+ struct epit_timer *epittm = to_epit_timer(ced);
+
+ epit_irq_acknowledge(epittm);
+
+ ced->event_handler(ced);
+
+ return IRQ_HANDLED;
+}
+
+static int __init epit_clocksource_init(struct epit_timer *epittm)
+{
+ unsigned int c = clk_get_rate(epittm->clk);
+
+ sched_clock_reg = epittm->base + EPITCNR;
+ sched_clock_register(epit_read_sched_clock, 32, c);
+
+ return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
+ clocksource_mmio_readl_down);
+}
+
+static int __init epit_clockevent_init(struct epit_timer *epittm)
+{
+ struct clock_event_device *ced = &epittm->ced;
+ struct irqaction *act = &epittm->act;
+
+ ced->name = "epit";
+ ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
+ ced->set_state_shutdown = epit_shutdown;
+ ced->tick_resume = epit_shutdown;
+ ced->set_state_oneshot = epit_set_oneshot;
+ ced->set_next_event = epit_set_next_event;
+ ced->rating = 200;
+ ced->cpumask = cpumask_of(0);
+ ced->irq = epittm->irq;
+ clockevents_config_and_register(ced, clk_get_rate(epittm->clk),
+ 0xff, 0xfffffffe);
+
+ act->name = "i.MX EPIT Timer Tick",
+ act->flags = IRQF_TIMER | IRQF_IRQPOLL;
+ act->handler = epit_timer_interrupt;
+ act->dev_id = ced;
+
+ /* Make irqs happen */
+ return setup_irq(epittm->irq, act);
+}
+
+static int __init epit_timer_init(struct device_node *np)
+{
+ struct epit_timer *epittm;
+ int ret;
+
+ epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
+ if (!epittm)
+ return -ENOMEM;
+
+ epittm->base = of_iomap(np, 0);
+ if (!epittm->base) {
+ ret = -ENXIO;
+ goto out_kfree;
+ }
+
+ epittm->irq = irq_of_parse_and_map(np, 0);
+ if (!epittm->irq) {
+ ret = -EINVAL;
+ goto out_iounmap;
+ }
+
+ /* Get EPIT clock */
+ epittm->clk = of_clk_get(np, 0);
+ if (IS_ERR(epittm->clk)) {
+ pr_err("i.MX EPIT: unable to get clk\n");
+ ret = PTR_ERR(epittm->clk);
+ goto out_iounmap;
+ }
+
+ ret = clk_prepare_enable(epittm->clk);
+ if (ret) {
+ pr_err("i.MX EPIT: unable to prepare+enable clk\n");
+ goto out_iounmap;
+ }
+
+ /* Initialise to a known state (all timers off, and timing reset) */
+ writel_relaxed(0x0, epittm->base + EPITCR);
+ writel_relaxed(0xffffffff, epittm->base + EPITLR);
+ writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
+ epittm->base + EPITCR);
+
+ ret = epit_clocksource_init(epittm);
+ if (ret) {
+ pr_err("i.MX EPIT: failed to init clocksource\n");
+ goto out_clk_disable;
+ }
+
+ ret = epit_clockevent_init(epittm);
+ if (ret) {
+ pr_err("i.MX EPIT: failed to init clockevent\n");
+ goto out_clk_disable;
+ }
+
+ return 0;
+
+out_clk_disable:
+ clk_disable_unprepare(epittm->clk);
+out_iounmap:
+ iounmap(epittm->base);
+out_kfree:
+ kfree(epittm);
+
+ return ret;
+}
+TIMER_OF_DECLARE(epit_timer, "fsl,imx31-epit", epit_timer_init);
--
2.17.1
^ permalink raw reply related
* [PATCH v6 3/5] dt-bindings: timer: add i.MX EPIT timer binding
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
Add devicetree binding document for NXP's i.MX SoC specific
EPIT timer driver.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
---
.../devicetree/bindings/timer/fsl,imxepit.txt | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxepit.txt
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxepit.txt b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt
new file mode 100644
index 000000000000..819d6458a860
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,imxepit.txt
@@ -0,0 +1,21 @@
+Binding for the i.MX Enhanced Periodic Interrupt Timer (EPIT)
+
+The Enhanced Periodic Interrupt Timer (EPIT) is a 32-bit set-and-forget timer
+that is capable of providing precise interrupts at regular intervals with
+minimal processor intervention.
+
+Required properties:
+- compatible: should be "fsl,<chip>-epit", "fsl,imx31-epit" where <chip> is
+ imx25, imx6qdl, imx6sl, imx6sul or imx6sx.
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Should contain EPIT controller interrupt
+- clocks : The clock provided by the SoC to drive the timer.
+
+Example for i.MX6QDL:
+ epit1: timer at 20d0000 {
+ compatible = "fsl,imx6qdl-epit", "fsl,imx31-epit";
+ reg = <0x020d0000 0x4000>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_EPIT1>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v6 2/5] ARM: imx: remove inexistant EPIT timer init
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-1-peron.clem@gmail.com>
From: Cl?ment Peron <clement.peron@devialet.com>
i.MX EPIT timer has been removed but not the init function declaration.
Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/common.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c8d68e918b2f..18aae76fa2da 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -38,7 +38,6 @@ void imx21_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
-void epit_timer_init(void __iomem *base, int irq);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
--
2.17.1
^ permalink raw reply related
* [PATCH v6 1/5] clk: imx6: add EPIT clock support
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-1-peron.clem@gmail.com>
From: Colin Didier <colin.didier@devialet.com>
Please ignore this commit.
It has already been merged in clk-next.
Leave it here to avoid error with automatic CI.
---
drivers/clk/imx/clk-imx6q.c | 2 ++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 8d518ad5dc13..b9ea7037e193 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -753,6 +753,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
else
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
+ clk[IMX6QDL_CLK_EPIT1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
+ clk[IMX6QDL_CLK_EPIT2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9cdb5e..7ad171b8f3bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
-#define IMX6QDL_CLK_END 261
+#define IMX6QDL_CLK_EPIT1 261
+#define IMX6QDL_CLK_EPIT2 262
+#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.17.1
^ permalink raw reply related
* [PATCH v6 0/5] Reintroduce i.MX EPIT Timer
From: Clément Péron @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Cl?ment Peron <clement.peron@devialet.com>
As suggested in the commit message we have added the device tree support,
proper bindings and we moved the driver into the correct folder.
Moreover we made some changes like use of relaxed IO accesor,
implement sched_clock, delay_timer and reduce the clockevents min_delta.
Changes since v5:
- change epit to timer in doc example
- fix typo in imx6sl.dtsi
Changes since v4:
- removed ipg clk
- change in dt epit to timer
- add introduction in doc
- add all compatibles in doc
- update epit entry for other i.MX device-trees
Changes since v3:
- Clean Kconfig
- Rename imx6q-epit to imx31-epit
- Update doc and bindings
- Indent and fix
Changes since v2 (Thanks Fabio Estevam):
- Removed unused ckil clock
- Add out_iounmap
- Check and handle if clk_prepare_enable failed
- Fix comment typo
Changes since v1 (Thanks Vladimir Zapolskiy):
- Add OF dependency in Kconfig
- Sort header
- Use BIT macro
- Remove useless comments
- Fix incorrect indent
- Fix memory leak
- Add check and handle possible returned error
Cl?ment Peron (2):
ARM: imx: remove inexistant EPIT timer init
dt-bindings: timer: add i.MX EPIT timer binding
Colin Didier (3):
clk: imx6: add EPIT clock support
clocksource: add driver for i.MX EPIT timer
ARM: dts: imx: add missing compatible and clock properties for EPIT
.../devicetree/bindings/timer/fsl,imxepit.txt | 21 ++
arch/arm/boot/dts/imx25.dtsi | 8 +-
arch/arm/boot/dts/imx6qdl.dtsi | 10 +-
arch/arm/boot/dts/imx6sl.dtsi | 10 +-
arch/arm/boot/dts/imx6sx.dtsi | 10 +-
arch/arm/boot/dts/imx6ul.dtsi | 10 +-
arch/arm/mach-imx/common.h | 1 -
drivers/clk/imx/clk-imx6q.c | 2 +
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-imx-epit.c | 265 ++++++++++++++++++
include/dt-bindings/clock/imx6qdl-clock.h | 4 +-
12 files changed, 341 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxepit.txt
create mode 100644 drivers/clocksource/timer-imx-epit.c
--
2.17.1
^ permalink raw reply
* [PATCH 3.16 267/410] arm64: do not use print_symbol()
From: Ben Hutchings @ 2018-06-07 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <lsq.1528380320.647747352@decadent.org.uk>
3.16.57-rc1 review patch. If anyone has any objections, please let me know.
------------------
From: Sergey Senozhatsky <sergey.senozhatsky.work@gmail.com>
commit 4ef7963843d3243260aa335dfb9cb2fede06aacf upstream.
print_symbol() is a very old API that has been obsoleted by %pS format
specifier in a normal printk() call.
Replace print_symbol() with a direct printk("%pS") call.
Link: http://lkml.kernel.org/r/20171211125025.2270-3-sergey.senozhatsky at gmail.com
To: Andrew Morton <akpm@linux-foundation.org>
To: Russell King <linux@armlinux.org.uk>
To: Catalin Marinas <catalin.marinas@arm.com>
To: Mark Salter <msalter@redhat.com>
To: Tony Luck <tony.luck@intel.com>
To: David Howells <dhowells@redhat.com>
To: Yoshinori Sato <ysato@users.sourceforge.jp>
To: Guan Xuetao <gxt@mprc.pku.edu.cn>
To: Borislav Petkov <bp@alien8.de>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Thomas Gleixner <tglx@linutronix.de>
To: Peter Zijlstra <peterz@infradead.org>
To: Vineet Gupta <vgupta@synopsys.com>
To: Fengguang Wu <fengguang.wu@intel.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Petr Mladek <pmladek@suse.com>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-c6x-dev at linux-c6x.org
Cc: linux-ia64 at vger.kernel.org
Cc: linux-am33-list at redhat.com
Cc: linux-sh at vger.kernel.org
Cc: linux-edac at vger.kernel.org
Cc: x86 at kernel.org
Cc: linux-snps-arc at lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sergey Senozhatsky <sergey.senozhatsky@gmail.com>
[pmladek at suse.com: updated commit message]
Signed-off-by: Petr Mladek <pmladek@suse.com>
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
arch/arm64/kernel/process.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -31,7 +31,6 @@
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
-#include <linux/kallsyms.h>
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/elfcore.h>
@@ -198,8 +197,8 @@ void __show_regs(struct pt_regs *regs)
}
show_regs_print_info(KERN_DEFAULT);
- print_symbol("pc : %s\n", regs->pc);
- print_symbol("lr : %s\n", lr);
+ printk("pc : %pS\n", (void *)regs->pc);
+ printk("lr : %pS\n", (void *)lr);
printk("sp : %016llx pstate : %08llx\n", sp, regs->pstate);
for (i = top_reg; i >= 0; i--) {
printk("x%-2d: %016llx ", i, regs->regs[i]);
^ permalink raw reply
* [PATCH 4/4] soc: imx: add SC firmware IPC and APIs
From: A.s. Dong @ 2018-06-07 13:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607070835.ebqsj7qurcdvcubz@pengutronix.de>
Hi Sascha,
> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: Thursday, June 7, 2018 3:09 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: dongas86 at gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> kernel at pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>;
> shawnguo at kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 4/4] soc: imx: add SC firmware IPC and APIs
>
> On Thu, Jun 07, 2018 at 04:18:54AM +0000, A.s. Dong wrote:
> > Hi Sascha,
> >
> > > > One problem of the way you suggested may be that:
> > > > If we doing like below, we may lose flexibility to change the MU
> > > > used for SCU firmware communication.
> > > > scu at 5d1b0000 {
> > > > compatible = "fsl,imx8qxp-scu";
> > > > reg = <0x0 0x5d1b0000 0x0 0x10000>;
> > > > };
> > > >
> > > > And current design is that the system supports multiple MU
> > > > channels used by various users at the same time, e.g. SCU, Power
> > > > Domain, Clock and
> > > others.
> > > > User can flexibly change it under their nodes: And each MU channel
> > > > is protected by their private lock and not affect each others.
> > > >
> > > > e.g.
> > > > scu {
> > > > compatible = "nxp,imx8qxp-scu", "simple-bus";
> > > > fsl,mu = <&lsio_mu0>;
> > > >
> > > > clk: clk {
> > > > compatible = "fsl,imx8qxp-clk";
> > > > #clock-cells = <1>;
> > > > };
> > > >
> > > > iomuxc: iomuxc {
> > > > compatible = "fsl,imx8qxp-iomuxc";
> > > > fsl,mu = <&lsio_mu3>;
> > > > };
> > > >
> > > > imx8qx-pm {
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > > fsl,mu = <&lsio_mu4>;
> > > > .............
> > > > }
> > > >
> > > > The default code only uses MU0 which is used by SCU.
> > > >
> > > > The change may affect this design. Any ideas?
> > >
> > > Sorry for the delay.
> > >
> > > You can add the child nodes to the mu nodes they should use:
> > >
> > > scu1 {
> > > compatible = "nxp,imx8qxp-scu";
> > > reg = <0x0 0x5d1b0000 0x0 0x10000>;
> > >
> > > clk: clk {
> > > compatible = "fsl,imx8qxp-clk";
> > > #clock-cells = <1>;
> > > };
> > >
> > > ...
> > > };
> > >
> > > scu2 {
> > > compatible = "nxp,imx8qxp-scu";
> > > reg = <0x0 someothermu 0x0 0x10000>;
> > >
> > > iomuxc: iomuxc {
> > > compatible = "fsl,imx8qxp-iomuxc";
> > > };
> > >
> > > ...
> > > };
> > >
> > > So instead of adding all possible children to a single mu and
> > > phandle to other mu's, just add the right children to each mu.
> > >
> >
> > I got your point now. But sorry i'm still a bit hestitate to it....
> >
> > This way increases complexity and looks more like a per-channel binding.
> > But we normally have only one (abstract) SCU firmware node in a system
> > which may use different channels to implement different functions like clk,
> pd and etc.
> > Multiple faked SCU nodes make people a bit confusing.
>
> They are not faked, indeed that's the MU units that physically exist.
>
> > Furthermore, it's still lose the flexibility for user to changing a MU to use.
> >
> > Looking at all exist users in kernel, seems no one to use like this.
> > See:
> > Documentation/devicetree/bindings/arm/arm,scpi.txt
> > Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
> >
> > All are similar like:
> > xxx: protocol-node {
> > compatible = "xxx-protocal";
> > channel = ...
> > ...
> >
> > clk_node: clk_node {
> > ...
> > };
> >
> > pd_node: pd_node {
> > ...
> > };
> > };
> > The protocol node work is selecting the correct channel, do necessary
> > initialization and populate the all child function device nodes.
> >
> > IMHO I'm still a bit like to this common way used in kernel if no stronger
> objection.
> > Do you think we can choose this way to go step forward?
>
> I'm not convinced, but go ahead if you think this is the better way to proceed.
>
> I think my original point that led to this discussion is the muddled way the
> MUs are handled in the code.
>
> To start with in the system controller code you ioremap the physical address
> of the MU and later on pass this address as a reference to the MU library
> code. There's no way for the MU code to ever create a private data. It would
> be much better if you would pass mu_init a pointer to the device node it shall
> initialize, let mu_init allocate a private data struct, ioremap the base and put
> it in the private data struct, and return the private data struct.
>
Actually I have tried that way initially, but ....
> Then there is this sc_ipc_get_handle() thing that your consumers shall use to
> get a handle to the SCU. Instead of returning a struct sc_ipc * there you
> return a ida which you first have to search for each time a consumer wants to
> do something on the SCU. Please just return a pointer there (which can be a
> cookie, i.e. the struct definition is unknown to the consumer but privately to
> the SCU code).
>
The problem is that sc_ipc_t is defined as uint32_t.
/*
* This type is used to declare a handle for an IPC communication
* channel. Its meaning is specific to the IPC implementation.
*/
typedef uint32_t sc_ipc_t;
which is referenced by the standard rpc call:
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
I can't return a pointer which is 64bit on ARMv8 platform and used it
for sc_call_rpc directly.
That why I need a way to convert struct sc_ipc_t to struct sc_ipc
(done by sc_ipc_get(ipc)).
But you're right, that means we have to search for each time a consumer
wants to do something on the SCU.
If we want to void it, one possible way may be changing the prototype of
both ipc handle sc_ipc_t and IPC channel ID sc_ipc_id_t to unsigned long,
then we can directly pass them the address pointer.
Although I initially don't want to changing SCU API prototype, but if we
have to, I will do it.
Sounds good to you?
Regards
Dong Aisheng
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions |
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^ permalink raw reply
* [GIT PULL] ARM: mvebu: fixes for v4.17 (#2)
From: Gregory CLEMENT @ 2018-06-07 13:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180602082431.lahocepns6vub6uq@localhost>
Hi Olof,
On sam., juin 02 2018, Olof Johansson <olof@lixom.net> wrote:
> On Mon, May 28, 2018 at 05:10:16PM +0200, Gregory CLEMENT wrote:
>> Hi,
>>
>> Here is the second pull request for fixes for mvebu for v4.17.
>> Nothing really critical but it needs to be fixed.
>>
>> Gregory
>>
>> The following changes since commit f43194c1447c9536efb0859c2f3f46f6bf2b9154:
>>
>> ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node (2018-04-27 17:47:24 +0200)
>>
>> are available in the Git repository at:
>>
>> git://git.infradead.org/linux-mvebu.git tags/mvebu-fixes-4.17-2
>>
>> for you to fetch changes up to ac62cc9d9cd6fa4c79e171c13dc8d58c3862b678:
>>
>> arm: dts: armada: Fix "#cooling-cells" property's name (2018-05-28 16:54:44 +0200)
>>
>> ----------------------------------------------------------------
>> mvebu fixes for 4.17 (part 2)
>>
>> - Use correct size for ICU nodes (irq controller) on Armada 7K/8K
>> - Fix "#cooling-cells" property's name on Synology DS116 (Armada 385)
>>
>> ----------------------------------------------------------------
>> Miquel Raynal (1):
>> arm64: dts: marvell: fix CP110 ICU node size
>>
>> Viresh Kumar (1):
>> arm: dts: armada: Fix "#cooling-cells" property's name
>
> Subject here should be 'ARM: dts: ...'
>
> The latter is definitely not 4.17 material by now. It's unclear on the ICU
> patch whether it's causing a real problem in reality, i.e. if it's an urgent
> regression fix or if it's just fixing up the register range to be correct per
> documentation. Let me know if it's a real issue and I can either cherry-pick
> it or send a separate pull request with just that fix.
Even the first patch did not fix a regression. But it is more just than
just fixing the documentation as the extension of the size of the
register set is needed to support more feature provided by ICU (it is
part of series already submitted).
It's not a problem for me that this PR was not merged in 4.17, but could
you add it for 4.18 in the current merge window?
Thanks,
Gregory
>
>
> -Olof
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* [RFC V2 3/3] perf: qcom: Add Falkor CPU PMU IMPLEMENTATION DEFINED event support
From: Agustin Vega-Frias @ 2018-06-07 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528379808-27970-1-git-send-email-agustinv@codeaurora.org>
Selection of these events can be envisioned as indexing them from
a 3D matrix:
- the first index selects a Region Event Selection Register (PMRESRx_EL0)
- the second index selects a group from which only one event at a time
can be selected
- the third index selects the event
The event is encoded into perf_event_attr.config as 0xPRCCG, where:
P [config:16 ] = prefix (flag that indicates a matrix-based event)
R [config:12-15] = register (specifies the PMRESRx_EL0 instance)
G [config:0-3 ] = group (specifies the event group)
CC [config:4-11 ] = code (specifies the event)
Events with the P flag set to zero are treated as common PMUv3 events
and are directly programmed into PMXEVTYPERx_EL0.
The first two indexes are set combining the RESR and group number with
a base number and writing it into the architected PMXEVTYPER_EL0 register.
The third index is set by writing the code into the bits corresponding
with the group into the appropriate IMPLEMENTATION DEFINED PMRESRx_EL0
register.
Support for this extension is signaled by the presence of the Falkor PMU
device node under each Falkor CPU device node in the DSDT ACPI table. E.g.:
Device (CPU0)
{
Name (_HID, "ACPI0007" /* Processor Device */)
...
Device (PMU0)
{
Name (_HID, "QCOM8150") /* Qualcomm Falkor PMU device */
...
}
}
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/perf/Makefile | 2 +-
drivers/perf/qcom_arm_pmu.c | 310 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 311 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/qcom_arm_pmu.c
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index b3902bd..a61afd9 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o
obj-$(CONFIG_ARM_CCN) += arm-ccn.o
obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o
obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
-obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
+obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o qcom_arm_pmu.o
obj-$(CONFIG_HISI_PMU) += hisilicon/
obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
diff --git a/drivers/perf/qcom_arm_pmu.c b/drivers/perf/qcom_arm_pmu.c
new file mode 100644
index 0000000..5cec756
--- /dev/null
+++ b/drivers/perf/qcom_arm_pmu.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm Technologies CPU PMU IMPLEMENTATION DEFINED extensions support
+ *
+ * Current extensions supported:
+ *
+ * - Matrix-based microarchitectural events support
+ *
+ * Selection of these events can be envisioned as indexing them from
+ * a 3D matrix:
+ * - the first index selects a Region Event Selection Register (PMRESRx_EL0)
+ * - the second index selects a group from which only one event at a time
+ * can be selected
+ * - the third index selects the event
+ *
+ * The event is encoded into perf_event_attr.config as 0xPRCCG, where:
+ * P [config:16 ] = prefix (flag that indicates a matrix-based event)
+ * R [config:12-15] = register (specifies the PMRESRx_EL0 instance)
+ * G [config:0-3 ] = group (specifies the event group)
+ * CC [config:4-11 ] = code (specifies the event)
+ *
+ * Events with the P flag set to zero are treated as common PMUv3 events
+ * and are directly programmed into PMXEVTYPERx_EL0.
+ *
+ * The first two indexes are set combining the RESR and group number with
+ * a base number and writing it into the architected PMXEVTYPER_EL0 register.
+ * The third index is set by writing the code into the bits corresponding
+ * with the group into the appropriate IMPLEMENTATION DEFINED PMRESRx_EL0
+ * register.
+ */
+
+#include <linux/acpi.h>
+#include <linux/perf/arm_pmu.h>
+
+#define pmresr0_el0 sys_reg(3, 5, 11, 3, 0)
+#define pmresr1_el0 sys_reg(3, 5, 11, 3, 2)
+#define pmresr2_el0 sys_reg(3, 5, 11, 3, 4)
+#define pmxevcntcr_el0 sys_reg(3, 5, 11, 0, 3)
+
+#define QC_EVT_PFX_SHIFT 16
+#define QC_EVT_REG_SHIFT 12
+#define QC_EVT_CODE_SHIFT 4
+#define QC_EVT_GRP_SHIFT 0
+#define QC_EVT_PFX_MASK GENMASK(QC_EVT_PFX_SHIFT, QC_EVT_PFX_SHIFT)
+#define QC_EVT_REG_MASK GENMASK(QC_EVT_REG_SHIFT + 3, QC_EVT_REG_SHIFT)
+#define QC_EVT_CODE_MASK GENMASK(QC_EVT_CODE_SHIFT + 7, QC_EVT_CODE_SHIFT)
+#define QC_EVT_GRP_MASK GENMASK(QC_EVT_GRP_SHIFT + 3, QC_EVT_GRP_SHIFT)
+#define QC_EVT_PRG_MASK (QC_EVT_PFX_MASK | QC_EVT_REG_MASK | QC_EVT_GRP_MASK)
+#define QC_EVT_PRG(event) ((event) & QC_EVT_PRG_MASK)
+#define QC_EVT_REG(event) (((event) & QC_EVT_REG_MASK) >> QC_EVT_REG_SHIFT)
+#define QC_EVT_CODE(event) (((event) & QC_EVT_CODE_MASK) >> QC_EVT_CODE_SHIFT)
+#define QC_EVT_GROUP(event) (((event) & QC_EVT_GRP_MASK) >> QC_EVT_GRP_SHIFT)
+
+#define QC_MAX_GROUP 7
+#define QC_MAX_RESR 2
+#define QC_BITS_PER_GROUP 8
+#define QC_RESR_ENABLE BIT_ULL(63)
+#define QC_RESR_EVT_BASE 0xd8
+
+static struct arm_pmu *def_ops;
+
+static inline void falkor_write_pmresr(u64 reg, u64 val)
+{
+ if (reg == 0)
+ write_sysreg_s(val, pmresr0_el0);
+ else if (reg == 1)
+ write_sysreg_s(val, pmresr1_el0);
+ else
+ write_sysreg_s(val, pmresr2_el0);
+}
+
+static inline u64 falkor_read_pmresr(u64 reg)
+{
+ return (reg == 0 ? read_sysreg_s(pmresr0_el0) :
+ reg == 1 ? read_sysreg_s(pmresr1_el0) :
+ read_sysreg_s(pmresr2_el0));
+}
+
+static void falkor_set_resr(u64 reg, u64 group, u64 code)
+{
+ u64 shift = group * QC_BITS_PER_GROUP;
+ u64 mask = GENMASK(shift + QC_BITS_PER_GROUP - 1, shift);
+ u64 val;
+
+ val = falkor_read_pmresr(reg) & ~mask;
+ val |= (code << shift);
+ val |= QC_RESR_ENABLE;
+ falkor_write_pmresr(reg, val);
+}
+
+static void falkor_clear_resr(u64 reg, u64 group)
+{
+ u32 shift = group * QC_BITS_PER_GROUP;
+ u64 mask = GENMASK(shift + QC_BITS_PER_GROUP - 1, shift);
+ u64 val = falkor_read_pmresr(reg) & ~mask;
+
+ falkor_write_pmresr(reg, val == QC_RESR_ENABLE ? 0 : val);
+}
+
+/*
+ * Check if e1 and e2 conflict with each other
+ *
+ * e1 is a matrix-based microarchitectural event we are checking against e2.
+ * A conflict exists if the events use the same reg, group, and a different
+ * code. Events with the same code are allowed because they could be using
+ * different filters (e.g. one to count user space and the other to count
+ * kernel space events).
+ */
+static inline int events_conflict(struct perf_event *e1, struct perf_event *e2)
+{
+ if ((e1 != e2) &&
+ (e1->pmu == e2->pmu) &&
+ (QC_EVT_PRG(e1->attr.config) == QC_EVT_PRG(e2->attr.config)) &&
+ (QC_EVT_CODE(e1->attr.config) != QC_EVT_CODE(e2->attr.config))) {
+ pr_debug_ratelimited(
+ "Group exclusion: conflicting events %llx %llx\n",
+ e1->attr.config,
+ e2->attr.config);
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Check if the given event is valid for the PMU and if so return the value
+ * that can be used in PMXEVTYPER_EL0 to select the event
+ */
+static int falkor_map_event(struct perf_event *event)
+{
+ u64 reg = QC_EVT_REG(event->attr.config);
+ u64 group = QC_EVT_GROUP(event->attr.config);
+ struct perf_event *leader;
+ struct perf_event *sibling;
+
+ if (!(event->attr.config & QC_EVT_PFX_MASK))
+ /* Common PMUv3 event, forward to the original op */
+ return def_ops->map_event(event);
+
+ /* Is it a valid matrix event? */
+ if ((group > QC_MAX_GROUP) || (reg > QC_MAX_RESR))
+ return -ENOENT;
+
+ /* If part of an event group, check if the event can be put in it */
+
+ leader = event->group_leader;
+ if (events_conflict(event, leader))
+ return -ENOENT;
+
+ for_each_sibling_event(sibling, leader)
+ if (events_conflict(event, sibling))
+ return -ENOENT;
+
+ return QC_RESR_EVT_BASE + reg*8 + group;
+}
+
+/*
+ * Find a slot for the event on the current CPU
+ */
+static int falkor_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event)
+{
+ int idx;
+
+ if (!!(event->attr.config & QC_EVT_PFX_MASK))
+ /* Matrix event, check for conflicts with existing events */
+ for_each_set_bit(idx, cpuc->used_mask, ARMPMU_MAX_HWEVENTS)
+ if (cpuc->events[idx] &&
+ events_conflict(event, cpuc->events[idx]))
+ return -ENOENT;
+
+ /* Let the original op handle the rest */
+ idx = def_ops->get_event_idx(cpuc, event);
+
+ /*
+ * This is called for actually allocating the events, but also with
+ * a dummy pmu_hw_events when validating groups, for that case we
+ * need to ensure that cpuc->events[idx] is NULL so we don't use
+ * an uninitialized pointer. Conflicts for matrix events in groups
+ * are checked during event mapping anyway (see falkor_event_map).
+ */
+ cpuc->events[idx] = NULL;
+
+ return idx;
+}
+
+/*
+ * Reset the PMU
+ */
+static void falkor_reset(void *info)
+{
+ struct arm_pmu *pmu = (struct arm_pmu *)info;
+ u32 i, ctrs = pmu->num_events;
+
+ /* PMRESRx_EL0 regs are unknown at reset, except for the EN field */
+ for (i = 0; i <= QC_MAX_RESR; i++)
+ falkor_write_pmresr(i, 0);
+
+ /* PMXEVCNTCRx_EL0 regs are unknown@reset */
+ for (i = 0; i <= ctrs; i++) {
+ write_sysreg(i, pmselr_el0);
+ isb();
+ write_sysreg_s(0, pmxevcntcr_el0);
+ }
+
+ /* Let the original op handle the rest */
+ def_ops->reset(info);
+}
+
+/*
+ * Enable the given event
+ */
+static void falkor_enable(struct perf_event *event)
+{
+ if (!!(event->attr.config & QC_EVT_PFX_MASK)) {
+ /* Matrix event, program the appropriate PMRESRx_EL0 */
+ struct arm_pmu *pmu = to_arm_pmu(event->pmu);
+ struct pmu_hw_events *events = this_cpu_ptr(pmu->hw_events);
+ u64 reg = QC_EVT_REG(event->attr.config);
+ u64 code = QC_EVT_CODE(event->attr.config);
+ u64 group = QC_EVT_GROUP(event->attr.config);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&events->pmu_lock, flags);
+ falkor_set_resr(reg, group, code);
+ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+ }
+
+ /* Let the original op handle the rest */
+ def_ops->enable(event);
+}
+
+/*
+ * Disable the given event
+ */
+static void falkor_disable(struct perf_event *event)
+{
+ /* Use the original op to disable the counter and interrupt */
+ def_ops->enable(event);
+
+ if (!!(event->attr.config & QC_EVT_PFX_MASK)) {
+ /* Matrix event, de-program the appropriate PMRESRx_EL0 */
+ struct arm_pmu *pmu = to_arm_pmu(event->pmu);
+ struct pmu_hw_events *events = this_cpu_ptr(pmu->hw_events);
+ u64 reg = QC_EVT_REG(event->attr.config);
+ u64 group = QC_EVT_GROUP(event->attr.config);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&events->pmu_lock, flags);
+ falkor_clear_resr(reg, group);
+ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+ }
+}
+
+PMU_FORMAT_ATTR(event, "config:0-15");
+PMU_FORMAT_ATTR(prefix, "config:16");
+PMU_FORMAT_ATTR(reg, "config:12-15");
+PMU_FORMAT_ATTR(code, "config:4-11");
+PMU_FORMAT_ATTR(group, "config:0-3");
+
+static struct attribute *falkor_pmu_formats[] = {
+ &format_attr_event.attr,
+ &format_attr_prefix.attr,
+ &format_attr_reg.attr,
+ &format_attr_code.attr,
+ &format_attr_group.attr,
+ NULL,
+};
+
+static struct attribute_group falkor_pmu_format_attr_group = {
+ .name = "format",
+ .attrs = falkor_pmu_formats,
+};
+
+static int qcom_falkor_pmu_init(struct arm_pmu *pmu, struct device *dev)
+{
+ /* Save base arm_pmu so we can invoke its ops when appropriate */
+ def_ops = devm_kmemdup(dev, pmu, sizeof(*def_ops), GFP_KERNEL);
+ if (!def_ops) {
+ pr_warn("Failed to allocate arm_pmu for QCOM extensions");
+ return -ENODEV;
+ }
+
+ pmu->name = "qcom_pmuv3";
+
+ /* Override the necessary ops */
+ pmu->map_event = falkor_map_event;
+ pmu->get_event_idx = falkor_get_event_idx;
+ pmu->reset = falkor_reset;
+ pmu->enable = falkor_enable;
+ pmu->disable = falkor_disable;
+
+ /* Override the necessary attributes */
+ pmu->pmu.attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
+ &falkor_pmu_format_attr_group;
+
+ return 1;
+}
+
+ACPI_DECLARE_PMU_VARIANT(qcom_falkor, "QCOM8150", qcom_falkor_pmu_init);
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [RFC V2 2/3] arm_pmu: acpi: add support for CPU PMU variant detection
From: Agustin Vega-Frias @ 2018-06-07 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528379808-27970-1-git-send-email-agustinv@codeaurora.org>
DT allows CPU PMU variant detection via the PMU device compatible
property. ACPI does not have an equivalent mechanism so we introduce
a probe table to allow this via a device nested inside the CPU device
in the DSDT:
Device (CPU0)
{
Name (_HID, "ACPI0007" /* Processor Device */)
...
Device (PMU0)
{
Name (_HID, "QCOM8150") /* Qualcomm Falkor PMU device */
/*
* The device might also contain _DSD properties to indicate other
* IMPLEMENTATION DEFINED PMU features.
*/
Name (_DSD, Package ()
{
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package ()
{
...
}
})
}
}
With this in place we can declare the variant:
ACPI_DECLARE_PMU_VARIANT(qcom_falkor, "QCOM8150", falkor_pmu_init);
The init function is called after the default PMU initialization and is
passed a pointer to the arm_pmu structure and a pointer to the PMU device.
The init function can then override arm_pmu callbacks and attributes and
query more properties from the PMU device.
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
---
drivers/perf/arm_pmu_acpi.c | 27 +++++++++++++++++++++++++++
include/asm-generic/vmlinux.lds.h | 1 +
include/linux/acpi.h | 11 +++++++++++
include/linux/perf/arm_pmu.h | 1 +
4 files changed, 40 insertions(+)
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
index 0f19751..6b0ca71 100644
--- a/drivers/perf/arm_pmu_acpi.c
+++ b/drivers/perf/arm_pmu_acpi.c
@@ -220,6 +220,26 @@ static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
return 0;
}
+/*
+ * Check if the given child device of the CPU device matches a PMU variant
+ * device declared with ACPI_DECLARE_PMU_VARIANT, if so, pass the arm_pmu
+ * structure and the matching device for further initialization.
+ */
+static int arm_pmu_variant_init(struct device *dev, void *data)
+{
+ extern struct acpi_device_id ACPI_PROBE_TABLE(pmu);
+ unsigned int cpu = *((unsigned int *)data);
+ const struct acpi_device_id *id;
+
+ id = acpi_match_device(&ACPI_PROBE_TABLE(pmu), dev);
+ if (id) {
+ armpmu_acpi_init_fn fn = (armpmu_acpi_init_fn)id->driver_data;
+
+ return fn(per_cpu(probed_pmus, cpu), dev);
+ }
+ return 0;
+}
+
int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
{
int pmu_idx = 0;
@@ -240,6 +260,7 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
*/
for_each_possible_cpu(cpu) {
struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
+ struct device *dev = get_cpu_device(cpu);
char *base_name;
if (!pmu || pmu->name)
@@ -254,6 +275,10 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
return ret;
}
+ ret = device_for_each_child(dev, &cpu, arm_pmu_variant_init);
+ if (ret == -ENODEV)
+ pr_warn("Failed PMU re-init, fallback to plain PMUv3");
+
base_name = pmu->name;
pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
if (!pmu->name) {
@@ -290,3 +315,5 @@ static int arm_pmu_acpi_init(void)
return ret;
}
subsys_initcall(arm_pmu_acpi_init)
+
+ACPI_DECLARE_PMU_SENTINEL();
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 5894049..f1be62a 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -600,6 +600,7 @@
IRQCHIP_OF_MATCH_TABLE() \
ACPI_PROBE_TABLE(irqchip) \
ACPI_PROBE_TABLE(timer) \
+ ACPI_PROBE_TABLE(pmu) \
EARLYCON_TABLE()
#define INIT_TEXT \
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 15bfb15..9c410cf 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -1153,6 +1153,17 @@ struct acpi_probe_entry {
(&ACPI_PROBE_TABLE_END(t) - \
&ACPI_PROBE_TABLE(t))); \
})
+
+#define ACPI_DECLARE_PMU_VARIANT(name, hid, init_fn) \
+ static const struct acpi_device_id __acpi_probe_##name \
+ __used __section(__pmu_acpi_probe_table) \
+ = { .id = hid, .driver_data = (kernel_ulong_t)init_fn }
+
+#define ACPI_DECLARE_PMU_SENTINEL() \
+ static const struct acpi_device_id __acpi_probe_sentinel \
+ __used __section(__pmu_acpi_probe_table_end) \
+ = { .id = "", .driver_data = 0 }
+
#else
static inline int acpi_dev_get_property(struct acpi_device *adev,
const char *name, acpi_object_type type,
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 40036a5..ff43d65 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -123,6 +123,7 @@ int armpmu_map_event(struct perf_event *event,
u32 raw_event_mask);
typedef int (*armpmu_init_fn)(struct arm_pmu *);
+typedef int (*armpmu_acpi_init_fn)(struct arm_pmu *, struct device *);
struct pmu_probe_info {
unsigned int cpuid;
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
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