* [PATCH] net: thunderx: prevent concurrent data re-writing by nicvf_set_rx_mode
From: Dean Nelson @ 2018-06-11 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180610.123551.885190586229525170.davem@davemloft.net>
On 06/10/2018 02:35 PM, David Miller wrote:
> From: Vadim Lomovtsev <Vadim.Lomovtsev@caviumnetworks.com>
> Date: Fri, 8 Jun 2018 02:27:59 -0700
>
>> + /* Save message data locally to prevent them from
>> + * being overwritten by next ndo_set_rx_mode call().
>> + */
>> + spin_lock(&nic->rx_mode_wq_lock);
>> + mode = vf_work->mode;
>> + mc = vf_work->mc;
>> + vf_work->mc = NULL;
If I'm reading this code correctly, I believe nic->rx_mode_work.mc will
have been set to NULL before the lock is dropped by
nicvf_set_rx_mode_task() and acquired by nicvf_set_rx_mode().
>> + spin_unlock(&nic->rx_mode_wq_lock);
>
> At the moment you drop this lock, the memory behind 'mc' can be
> freed up by:
>
>> + spin_lock(&nic->rx_mode_wq_lock);
>> + kfree(nic->rx_mode_work.mc);
So the kfree() will be called with a NULL pointer and quickly return.
>
> And you'll crash when you dereference it above via
> __nicvf_set_rx_mode_task().
>
I believe the call to kfree() in nicvf_set_rx_mode() is there to free
up a mc_list that has been allocated by nicvf_set_rx_mode() during a
previous callback to the function, one that has not yet been processed
by nicvf_set_rx_mode_task().
In this way only the last 'unprocessed' callback to nicvf_set_rx_mode()
gets processed should there be multiple callbacks occurring between the
times the nicvf_set_rx_mode_task() runs.
In my testing with this patch, this is what I see happening.
^ permalink raw reply
* [PATCH v2] irqchip/gic-v3-its: fix ITS queue timeout
From: Yang Yingliang @ 2018-06-11 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0ebd8eef-1a86-3c7e-cd3b-f9580c497b5c@arm.com>
Hi, Marc
On 2018/6/11 17:31, Marc Zyngier wrote:
> On 06/06/18 03:40, Yang Yingliang wrote:
>> When the kernel booted with maxcpus=x, 'x' is smaller
>> than actual cpu numbers, the TAs of offline cpus won't
>> be set to its->collection.
>>
>> If LPI is bind to offline cpu, sync cmd will use zero TA,
>> it leads to ITS queue timeout. Fix this by choosing a
>> online cpu, if there is no online cpu in cpu_mask.
>>
>> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>> index 5416f2b..d8b9539 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -2309,7 +2309,9 @@ static int its_irq_domain_activate(struct irq_domain *domain,
>> cpu_mask = cpumask_of_node(its_dev->its->numa_node);
>>
>> /* Bind the LPI to the first possible CPU */
>> - cpu = cpumask_first(cpu_mask);
>> + cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
>> + if (cpu >= nr_cpu_ids)
>> + cpu = cpumask_first(cpu_online_mask);
> I've thought about this one a bit more, and apart from breaking TX1
> in a very bad way, I think it is actually correct. It is just that
> the commit message doesn't make much sense.
>
> The way I understand it is:
> - this is a NUMA system, with at least one node not online
> - the SRAT table indicates that this ITS is local to an offline node
Yes, your comment is more proper and correct. Mine describes how the BUG
happens.
I will send a v3 later with proper comment.
Thanks,
Yang
>
> In that case, we need to pick an online CPU, and any will do (again,
> ignoring the silly Cavium erratum). Explained like this, the above
> hunk is sensible, and just needs to handle the TX1 quirk. Something like:
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 5416f2b2ac21..21b7b5151177 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -2309,7 +2309,13 @@ static int its_irq_domain_activate(struct irq_domain *domain,
> cpu_mask = cpumask_of_node(its_dev->its->numa_node);
>
> /* Bind the LPI to the first possible CPU */
> - cpu = cpumask_first(cpu_mask);
> + cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
> + if (cpu >= nr_cpu_idx) {
> + if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
> + return -EINVAL;
> +
> + cpu = cpumask_first(cpu_online_mask);
> + }
> its_dev->event_map.col_map[event] = cpu;
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>
>
>> its_dev->event_map.col_map[event] = cpu;
>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>>
>> @@ -2466,7 +2468,10 @@ static int its_vpe_set_affinity(struct irq_data *d,
>> bool force)
>> {
>> struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
>> - int cpu = cpumask_first(mask_val);
>> + int cpu = cpumask_first_and(mask_val, cpu_online_mask);
>> +
>> + if (cpu >= nr_cpu_ids)
>> + cpu = cpumask_first(cpu_online_mask);
>>
>> /*
>> * Changing affinity is mega expensive, so let's be as lazy as
>>
> This hunk, on the other hand, is completely useless. Look how this is
> called from vgic_v4_flush_hwstate():
>
> err = irq_set_affinity(irq, cpumask_of(smp_processor_id()));
>
> The mask is always that of the CPU we run on, and we're in a non-premptible
> section. So no way we can be targeting an offline CPU.
>
> If you quickly respin this patch with a decent commit log, I'll take it.
>
> Thanks,
>
> M.
^ permalink raw reply
* [PATCH 04/24] 32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option
From: Yury Norov @ 2018-06-11 11:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a16ByPtCwKbdLQRDRni3qV9DXLNYZ9QJUH6uHaZYHr34g@mail.gmail.com>
On Mon, Jun 11, 2018 at 09:48:02AM +0200, Arnd Bergmann wrote:
> On Sat, Jun 9, 2018 at 9:42 AM, Yury Norov <ynorov@caviumnetworks.com> wrote:
> > On Fri, Jun 08, 2018 at 06:32:07PM +0100, Catalin Marinas wrote:
> >> On Wed, May 16, 2018 at 11:18:49AM +0300, Yury Norov wrote:
> >> > diff --git a/arch/Kconfig b/arch/Kconfig
> >> > index 76c0b54443b1..ee079244dc3c 100644
> >> > --- a/arch/Kconfig
> >> > +++ b/arch/Kconfig
> >> > @@ -264,6 +264,21 @@ config ARCH_THREAD_STACK_ALLOCATOR
> >> > config ARCH_WANTS_DYNAMIC_TASK_STRUCT
> >> > bool
> >> >
> >> > +config ARCH_32BIT_OFF_T
> >> > + bool
> >> > + depends on !64BIT
> >> > + help
> >> > + All new 32-bit architectures should have 64-bit off_t type on
> >> > + userspace side which corresponds to the loff_t kernel type. This
> >> > + is the requirement for modern ABIs. Some existing architectures
> >> > + already have 32-bit off_t. This option is enabled for all such
> >> > + architectures explicitly. Namely: arc, arm, blackfin, cris, frv,
> >> > + h8300, hexagon, m32r, m68k, metag, microblaze, mips32, mn10300,
> >> > + nios2, openrisc, parisc32, powerpc32, score, sh, sparc, tile32,
> >> > + unicore32, x86_32 and xtensa. This is the complete list. Any
> >> > + new 32-bit architecture should declare 64-bit off_t type on user
> >> > + side and so should not enable this option.
> >>
> >> Do you know if this is the case for riscv and nds32, merged in the
> >> meantime? If not, I suggest you drop this patch altogether and just
> >> define force_o_largefile() for arm64/ilp32 as we don't seem to stick to
> >> "all new 32-bit architectures should have 64-bit off_t".
> >
> > I wrote this patch at request of Arnd Bergmann. This is actually his
> > words that all new 32-bit architectures should have 64-bit off_t. So
> > I was surprized when riscv was merged with 32-bit off_t (and I didn't
> > follow nds32).
> >
> > If this rule is still in force, we'd better add new exceptions to this
> > patch. Otherwise, we can drop it.
> >
> > Arnd, could you please comment it?
>
> I completely forgot about it and had assumed that it was merged long
> ago, sorry about that.
Hi Arnd,
There are 3 patches like this in ILP32 series that change ABI for new
targets. I've submitted them in separated series:
https://lkml.org/lkml/2017/9/25/574
They all seems to be acked by you. If you ready to upstream the
series, I can rebase it and add riscv32 and nds32 exceptions.
If Palmer and riscv people will decide to follow new rules, we can
easily drop the exception.
Yury
^ permalink raw reply
* [PATCH v1] ARM: imx: add imx7d-m4
From: Stefan Agner @ 2018-06-11 11:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528706126.2842.1.camel@pengutronix.de>
On 11.06.2018 10:35, Lucas Stach wrote:
> Hi Shawn,
>
> Am Montag, den 11.06.2018, 16:20 +0800 schrieb Shawn Guo:
>> On Mon, Jun 11, 2018 at 10:02:53AM +0200, Oleksij Rempel wrote:
>> > Hi all,
>> >
>> > this patch was send 05.04.2018. Any comments?
>> >
>> > @Shawn, can you please take it?
>>
>> Honestly I'm not sure how useful it will be.??If we can have some i.MX
>> developers ACK on it, I will be more comfortable to take it.
>
> This is all highly experimental and in PoC stage, but we see some value
> in running a second Linux system on the M4 coprocessor. There are lots
> of things that still need to be figured out, but we are working on this
> from time to time when there are some hours to spare.
>
> This patch seems like a good step in the right direction and IMHO the
> amount of code and changes is small enough to carry it upstream without
> impacting anything else. I would be happy if this could be pulled in.
I agree with Lucas here, this is rather minimal and not invasive.
Out of interest, on what memory region do you run Linux? Do you use
caches? In some experiments a while ago I noticed that only 2MiB/(or
4MiB) of DDR memory can use caches, which is somewhat tight to run Linux
on.
https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/
--
Stefan
>> >
>> > On 05.04.2018 13:51, Oleksij Rempel wrote:
>> > > Provide basic support for Cortex-M4 located on NXP iMX7D.
>> > > This code was tested in combination with imx-rproc driver
>> > > which will upload with specially formatted ELF image containing
>> > > kernel, device and CPIO rootfs.
>> > >
>> > > > > > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>> > > ---
>> > > ?arch/arm/boot/dts/Makefile?????????|??2 +-
>> > > ?arch/arm/mach-imx/Kconfig??????????| 33 +++++++++++++++++++++------------
>> > > ?arch/arm/mach-imx/Makefile?????????|??3 ++-
>> > > ?arch/arm/mach-imx/mach-imx7d-cm4.c | 21 +++++++++++++++++++++
>> > > ?4 files changed, 45 insertions(+), 14 deletions(-)
>> > > ?create mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
>> > >
>> > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> > > index 852452515bea..d49bb9a58aee 100644
>> > > --- a/arch/arm/boot/dts/Makefile
>> > > +++ b/arch/arm/boot/dts/Makefile
>> > > @@ -527,7 +527,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>> > > > > > ? imx6ul-tx6ul-0011.dtb \
>> > > > > > ? imx6ul-tx6ul-mainboard.dtb \
>> > > > > > ? imx6ull-14x14-evk.dtb
>> > > -dtb-$(CONFIG_SOC_IMX7D) += \
>> > > +dtb-$(CONFIG_SOC_IMX7D_CA7) += \
>> > > > > > ? imx7d-cl-som-imx7.dtb \
>> > > > > > ? imx7d-colibri-emmc-eval-v3.dtb \
>> > > > > > ? imx7d-colibri-eval-v3.dtb \
>> > > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>> > > index 782699e67600..101c8599d952 100644
>> > > --- a/arch/arm/mach-imx/Kconfig
>> > > +++ b/arch/arm/mach-imx/Kconfig
>> > > @@ -528,18 +528,6 @@ config SOC_IMX6UL
>> > > > > > ? help
>> > > > > > ? ??This enables support for Freescale i.MX6 UltraLite processor.
>> > > ?
>> > > -config SOC_IMX7D
>> > > > > > - bool "i.MX7 Dual support"
>> > > > > > - select PINCTRL_IMX7D
>> > > > > > - select ARM_GIC
>> > > > > > - select HAVE_ARM_ARCH_TIMER
>> > > > > > - select HAVE_IMX_ANATOP
>> > > > > > - select HAVE_IMX_MMDC
>> > > > > > - select HAVE_IMX_SRC
>> > > > > > - select IMX_GPCV2
>> > > > > > - help
>> > > > > > - This enables support for Freescale i.MX7 Dual processor.
>> > > -
>> > > ?config SOC_LS1021A
>> > > > > > ? bool "Freescale LS1021A support"
>> > > > > > ? select ARM_GIC
>> > > @@ -554,6 +542,27 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>> > > ?
>> > > ?if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
>> > > ?
>> > > +config SOC_IMX7D_CA7
>> > > > > > + bool
>> > > > > > + select ARM_GIC
>> > > > > > + select HAVE_ARM_ARCH_TIMER
>> > > > > > + select HAVE_IMX_ANATOP
>> > > > > > + select HAVE_IMX_MMDC
>> > > > > > + select HAVE_IMX_SRC
>> > > > > > + select IMX_GPCV2
>> > > +
>> > > +config SOC_IMX7D_CM4
>> > > > > > + bool
>> > > > > > + select ARMV7M_SYSTICK
>> > > +
>> > > +config SOC_IMX7D
>> > > > > > + bool "i.MX7 Dual support"
>> > > > > > + select PINCTRL_IMX7D
>> > > > > > + select SOC_IMX7D_CA7 if ARCH_MULTI_V7
>> > > > > > + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
>> > > > > > + help
>> > > > > > + This enables support for Freescale i.MX7 Dual processor.
>> > > +
>> > > ?config SOC_VF610
>> > > > > > ? bool "Vybrid Family VF610 support"
>> > > > > > ? select ARM_GIC if ARCH_MULTI_V7
>> > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>> > > index 8ff71058207d..68640f100ef3 100644
>> > > --- a/arch/arm/mach-imx/Makefile
>> > > +++ b/arch/arm/mach-imx/Makefile
>> > > @@ -80,7 +80,8 @@ obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
>> > > ?obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
>> > > ?obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
>> > > ?obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
>> > > -obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
>> > > +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
>> > > +obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
>> > > ?
>> > > ?ifeq ($(CONFIG_SUSPEND),y)
>> > > ?AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
>> > > diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
>> > > new file mode 100644
>> > > index 000000000000..c36dea79aeb8
>> > > --- /dev/null
>> > > +++ b/arch/arm/mach-imx/mach-imx7d-cm4.c
>> > > @@ -0,0 +1,21 @@
>> > > +/*
>> > > + * Copyright 2017 Pengutronix
>> > > + *
>> > > + * This program is free software; you can redistribute it and/or modify
>> > > + * it under the terms of the GNU General Public License version 2 as
>> > > + * published by the Free Software Foundation.
>> > > + */
>> > > +
>> > > +#include <linux/kernel.h>
>> > > +#include <asm/v7m.h>
>> > > +#include <asm/mach/arch.h>
>> > > +
>> > > +static const char * const imx7d_cm4_dt_compat[] __initconst = {
>> > > > > > + "fsl,imx7d-cm4",
>> > > > > > + NULL,
>> > > +};
>> > > +
>> > > +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
>> > > > > > + .dt_compat = imx7d_cm4_dt_compat,
>> > > > > > + .restart = armv7m_restart,
>> > > +MACHINE_END
>> > >
>>
>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* linux-next: manual merge of the regulator tree with the arm-soc tree
From: Linus Walleij @ 2018-06-11 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180604104642.GC7536@sirena.org.uk>
On Mon, Jun 4, 2018 at 12:46 PM, Mark Brown <broonie@kernel.org> wrote:
> On Fri, Jun 01, 2018 at 12:49:53AM +0200, Janusz Krzysztofik wrote:
>
>> I confirm the fix by Stephen works for me, however, the conflicting patch by
>> Linus breaks things a bit.
>
>> Lookup tables added to board files use function name "enable" while the
>> regulator uses NULL. As a result, GPIO descriptor is not matched and not
>> assigned to the regulator which ends up running with no control over GPIO pin.
>
>> Either the regulator driver should use the function name "enable" or that name
>> should be removed from lookup tables.
>
> I'll revert this one as well :(
I see this is a generic problem, no idea why I didn't pass these
unnamed as NULL in the first place, probably my ignorance as usual.
I fixed it up in my patch making them all anonymous and rebasing
the rest as well. Let's see how it looks after the merge window.
I will also need to rebase on top of Janusz changes and then it
will look even better.
Janusz: would be super if you could test my patches after that!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v1] ARM: imx: add imx7d-m4
From: Oleksij Rempel @ 2018-06-11 11:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3fa291a7da6978545cd21fdcf78c483e@agner.ch>
On 11.06.2018 13:48, Stefan Agner wrote:
> On 11.06.2018 10:35, Lucas Stach wrote:
>> Hi Shawn,
>>
>> Am Montag, den 11.06.2018, 16:20 +0800 schrieb Shawn Guo:
>>> On Mon, Jun 11, 2018 at 10:02:53AM +0200, Oleksij Rempel wrote:
>>>> Hi all,
>>>>
>>>> this patch was send 05.04.2018. Any comments?
>>>>
>>>> @Shawn, can you please take it?
>>>
>>> Honestly I'm not sure how useful it will be.??If we can have some i.MX
>>> developers ACK on it, I will be more comfortable to take it.
>>
>> This is all highly experimental and in PoC stage, but we see some value
>> in running a second Linux system on the M4 coprocessor. There are lots
>> of things that still need to be figured out, but we are working on this
>> from time to time when there are some hours to spare.
>>
>> This patch seems like a good step in the right direction and IMHO the
>> amount of code and changes is small enough to carry it upstream without
>> impacting anything else. I would be happy if this could be pulled in.
>
> I agree with Lucas here, this is rather minimal and not invasive.
>
>
> Out of interest, on what memory region do you run Linux? Do you use
> caches? In some experiments a while ago I noticed that only 2MiB/(or
> 4MiB) of DDR memory can use caches, which is somewhat tight to run Linux
> on.
>
> https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/
here is DT part for master system on Cortex A7 to run Linux on Cortex M4:
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
m4_reserved_sysmem1: rproc at 88000000 {
reg = <0x88000000 0x4000000>;
no-map;
};
/* not really needed node. used as example */
m4_reserved_sysmem2: rproc at 88080000 {
reg = <0x8c000000 0x80000>;
no-map;
};
};
mailbox_test {
compatible = "mailbox-test";
reg = <0x00900000 0x00020000>, <0x00920000
0x00020000>;
mboxes = <&mu0a 0>, <&mu0a 0>;
mbox-names = "tx", "rx";
};
};
/* node reserved for rproc */
&uart1 {
assigned-clock-rates = <240000000>;
status = "disabled";
};
&gpt2 {
assigned-clock-rates = <24000000>;
status = "disabled";
};
&mu0a {
status = "okay";
#mbox-cells = <1>;
};
&imx_rproc {
status = "okay";
memory-region = <&m4_reserved_sysmem1>,
<&m4_reserved_sysmem2>;
remote-nodes = <&gpt2>, <&uart1>;
};
> --
> Stefan
>
>
>>>>
>>>> On 05.04.2018 13:51, Oleksij Rempel wrote:
>>>>> Provide basic support for Cortex-M4 located on NXP iMX7D.
>>>>> This code was tested in combination with imx-rproc driver
>>>>> which will upload with specially formatted ELF image containing
>>>>> kernel, device and CPIO rootfs.
>>>>>
>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>> ---
>>>>> ?arch/arm/boot/dts/Makefile?????????|??2 +-
>>>>> ?arch/arm/mach-imx/Kconfig??????????| 33 +++++++++++++++++++++------------
>>>>> ?arch/arm/mach-imx/Makefile?????????|??3 ++-
>>>>> ?arch/arm/mach-imx/mach-imx7d-cm4.c | 21 +++++++++++++++++++++
>>>>> ?4 files changed, 45 insertions(+), 14 deletions(-)
>>>>> ?create mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>>>> index 852452515bea..d49bb9a58aee 100644
>>>>> --- a/arch/arm/boot/dts/Makefile
>>>>> +++ b/arch/arm/boot/dts/Makefile
>>>>> @@ -527,7 +527,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>>>>>>>> ? imx6ul-tx6ul-0011.dtb \
>>>>>>>> ? imx6ul-tx6ul-mainboard.dtb \
>>>>>>>> ? imx6ull-14x14-evk.dtb
>>>>> -dtb-$(CONFIG_SOC_IMX7D) += \
>>>>> +dtb-$(CONFIG_SOC_IMX7D_CA7) += \
>>>>>>>> ? imx7d-cl-som-imx7.dtb \
>>>>>>>> ? imx7d-colibri-emmc-eval-v3.dtb \
>>>>>>>> ? imx7d-colibri-eval-v3.dtb \
>>>>> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>>>>> index 782699e67600..101c8599d952 100644
>>>>> --- a/arch/arm/mach-imx/Kconfig
>>>>> +++ b/arch/arm/mach-imx/Kconfig
>>>>> @@ -528,18 +528,6 @@ config SOC_IMX6UL
>>>>>>>> ? help
>>>>>>>> ? ??This enables support for Freescale i.MX6 UltraLite processor.
>>>>> ?
>>>>> -config SOC_IMX7D
>>>>>>>> - bool "i.MX7 Dual support"
>>>>>>>> - select PINCTRL_IMX7D
>>>>>>>> - select ARM_GIC
>>>>>>>> - select HAVE_ARM_ARCH_TIMER
>>>>>>>> - select HAVE_IMX_ANATOP
>>>>>>>> - select HAVE_IMX_MMDC
>>>>>>>> - select HAVE_IMX_SRC
>>>>>>>> - select IMX_GPCV2
>>>>>>>> - help
>>>>>>>> - This enables support for Freescale i.MX7 Dual processor.
>>>>> -
>>>>> ?config SOC_LS1021A
>>>>>>>> ? bool "Freescale LS1021A support"
>>>>>>>> ? select ARM_GIC
>>>>> @@ -554,6 +542,27 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>>>>> ?
>>>>> ?if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
>>>>> ?
>>>>> +config SOC_IMX7D_CA7
>>>>>>>> + bool
>>>>>>>> + select ARM_GIC
>>>>>>>> + select HAVE_ARM_ARCH_TIMER
>>>>>>>> + select HAVE_IMX_ANATOP
>>>>>>>> + select HAVE_IMX_MMDC
>>>>>>>> + select HAVE_IMX_SRC
>>>>>>>> + select IMX_GPCV2
>>>>> +
>>>>> +config SOC_IMX7D_CM4
>>>>>>>> + bool
>>>>>>>> + select ARMV7M_SYSTICK
>>>>> +
>>>>> +config SOC_IMX7D
>>>>>>>> + bool "i.MX7 Dual support"
>>>>>>>> + select PINCTRL_IMX7D
>>>>>>>> + select SOC_IMX7D_CA7 if ARCH_MULTI_V7
>>>>>>>> + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
>>>>>>>> + help
>>>>>>>> + This enables support for Freescale i.MX7 Dual processor.
>>>>> +
>>>>> ?config SOC_VF610
>>>>>>>> ? bool "Vybrid Family VF610 support"
>>>>>>>> ? select ARM_GIC if ARCH_MULTI_V7
>>>>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>>>>> index 8ff71058207d..68640f100ef3 100644
>>>>> --- a/arch/arm/mach-imx/Makefile
>>>>> +++ b/arch/arm/mach-imx/Makefile
>>>>> @@ -80,7 +80,8 @@ obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
>>>>> ?obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
>>>>> ?obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
>>>>> ?obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
>>>>> -obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
>>>>> +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
>>>>> +obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
>>>>> ?
>>>>> ?ifeq ($(CONFIG_SUSPEND),y)
>>>>> ?AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
>>>>> diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>> new file mode 100644
>>>>> index 000000000000..c36dea79aeb8
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>> @@ -0,0 +1,21 @@
>>>>> +/*
>>>>> + * Copyright 2017 Pengutronix
>>>>> + *
>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>> + * it under the terms of the GNU General Public License version 2 as
>>>>> + * published by the Free Software Foundation.
>>>>> + */
>>>>> +
>>>>> +#include <linux/kernel.h>
>>>>> +#include <asm/v7m.h>
>>>>> +#include <asm/mach/arch.h>
>>>>> +
>>>>> +static const char * const imx7d_cm4_dt_compat[] __initconst = {
>>>>>>>> + "fsl,imx7d-cm4",
>>>>>>>> + NULL,
>>>>> +};
>>>>> +
>>>>> +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
>>>>>>>> + .dt_compat = imx7d_cm4_dt_compat,
>>>>>>>> + .restart = armv7m_restart,
>>>>> +MACHINE_END
>>>>>
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
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* [PATCH v1] ARM: imx: add imx7d-m4
From: Fabio Estevam @ 2018-06-11 12:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3fa291a7da6978545cd21fdcf78c483e@agner.ch>
On Mon, Jun 11, 2018 at 8:48 AM, Stefan Agner <stefan@agner.ch> wrote:
> On 11.06.2018 10:35, Lucas Stach wrote:
>> Hi Shawn,
>>
>> Am Montag, den 11.06.2018, 16:20 +0800 schrieb Shawn Guo:
>>> On Mon, Jun 11, 2018 at 10:02:53AM +0200, Oleksij Rempel wrote:
>>> > Hi all,
>>> >
>>> > this patch was send 05.04.2018. Any comments?
>>> >
>>> > @Shawn, can you please take it?
>>>
>>> Honestly I'm not sure how useful it will be. If we can have some i.MX
>>> developers ACK on it, I will be more comfortable to take it.
>>
>> This is all highly experimental and in PoC stage, but we see some value
>> in running a second Linux system on the M4 coprocessor. There are lots
>> of things that still need to be figured out, but we are working on this
>> from time to time when there are some hours to spare.
>>
>> This patch seems like a good step in the right direction and IMHO the
>> amount of code and changes is small enough to carry it upstream without
>> impacting anything else. I would be happy if this could be pulled in.
>
> I agree with Lucas here, this is rather minimal and not invasive.
Agreed here as well.
It would be nice if we could start improving the CortexM4 support in
general with mainline.
Thanks
^ permalink raw reply
* handling voice calls in ALSA soc (on Droid 4)
From: Pavel Machek @ 2018-06-11 12:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180611111011.GA11580@sirena.org.uk>
On Mon 2018-06-11 12:10:11, Mark Brown wrote:
> On Mon, Jun 11, 2018 at 12:25:30PM +0200, Pavel Machek wrote:
>
> > ...and also. What is right interface for this? Mixer component that
> > says if voice call is active or not?
>
> Your modem should be represented as a component in the system and have
> an input and an output representing the input and output on the cell
> network. See speyside for an example of how this can look in software
> though there's a bunch of different ways modems can appear so you might
> not have a fully digital link like that.
Thanks for the pointer.
With setup like that, how does userland tell kernel that the baseband
<-> microphone/speaker connection should be activated?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* [PATCH V3] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Marek Vasut @ 2018-06-11 12:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXG6mMfFTz+fdZQ53hLxYgVZPmsGpaRri8TesiruUNYUg@mail.gmail.com>
On 06/11/2018 11:56 AM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi,
> On Mon, Jun 4, 2018 at 7:59 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>> Rather than hard-coding the quirk topology, which stopped scaling,
>> parse the information from DT. The code looks for all compatible
>> PMICs -- da9036 and da9210 -- and checks if their IRQ line is tied
>
> da9063
>
>> to the same pin. If so, the code sends a matching sequence to the
>> PMIC to deassert the IRQ.
>
> Note that not all R-Car Gen2 boards have all regulators described in DT yet.
> E.g. gose lacks da9210. So that has to be fixed first.
[...]
> da9210_msg?
Fixed
>
>> + .len = ARRAY_SIZE(da9210_irq_clr),
>> + .buf = da9210_irq_clr,
>> +};
>
>> @@ -122,7 +143,13 @@ static struct notifier_block regulator_quirk_nb = {
>>
>> static int __init rcar_gen2_regulator_quirk(void)
>> {
>> - u32 mon;
>> + struct device_node *np;
>> + const struct of_device_id *id;
>> + struct regulator_quirk *quirk;
>> + struct regulator_quirk *pos;
>> + struct of_phandle_args *argsa, *argsb;
>> + u32 mon, addr;
>> + int ret;
>
> Some people prefer "Reverse Christmas Tree Ordering", i.e. longest line first.
>
>>
>> if (!of_machine_is_compatible("renesas,koelsch") &&
>> !of_machine_is_compatible("renesas,lager") &&
>> @@ -130,6 +157,45 @@ static int __init rcar_gen2_regulator_quirk(void)
>> !of_machine_is_compatible("renesas,gose"))
>> return -ENODEV;
>
> I think the board checks above can be removed. That will auto-enable the
> fix on e.g. Porter (once its regulators have ended up in DTS, of course).
Removing the check would also enable it on boards where we don't want
this enabled, so I'd prefer to keep the check to avoid strange surprises.
>>
>> + for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
>> + if (!np || !of_device_is_available(np))
>
> !np cannot happen
Right
>> + break;
>> +
>> + quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
>
> Missing NULL check
>
>> +
>> + argsa = &quirk->irq_args;
>> + memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
>> +
>> + ret = of_property_read_u32(np, "reg", &addr);
>> + if (ret)
>> + return ret;
>
> I think it's safer to skip this entry and continue, after calling
> kfree(quirk), of course.
>
>> +
>> + quirk->id = id;
>> + quirk->i2c_msg.addr = addr;
>> + quirk->shared = false;
>
> No need to clear shared, it was cleared by kzalloc().
>
>> +
>> + ret = of_irq_parse_one(np, 0, &quirk->irq_args);
>> + if (ret)
>> + return ret;
>
> kfree(quirk) and continue...
>
I wonder if it shouldn't rather free the entire list and abort ?
> Works fine on Koelsch, so
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
--
Best regards,
Marek Vasut
^ permalink raw reply
* [PATCH v3 0/6] add virt-dma support for imx-sdma
From: Robin Gong @ 2018-06-11 12:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528714877.2842.3.camel@pengutronix.de>
Hi Lucas,
Thank for your report, I tested it only on SPI, will update to you after try on uart tomorrow.
> ? 2018?6?11????7:01?Lucas Stach <l.stach@pengutronix.de> ???
>
> Hi Robin,
>
> this series breaks serial DMA for me. I wasn't able to dig in deeper
> yet. Please let me know if you can test/reproduce at your side, if not
> I'll try to find some time to collect some more debug info.
>
> Regards,
> Lucas
>
> Am Montag, den 11.06.2018, 22:59 +0800 schrieb Robin Gong:
>> The legacy sdma driver has below limitations or drawbacks:
>> 1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc
>> one page size for one channel regardless of only few BDs needed
>> most time. But in few cases, the max PAGE_SIZE maybe not enough.
>> 2. One SDMA channel can't stop immediatley once channel disabled which
>> means SDMA interrupt may come in after this channel terminated.There
>> are some patches for this corner case such as commit "2746e2c389f9",
>> but not cover non-cyclic.
>>
>> The common virt-dma overcomes the above limitations. It can alloc bd
>> dynamically and free bd once this tx transfer done. No memory wasted or
>> maximum limititation here, only depends on how many memory can be requested
>> from kernel. For No.2, such issue can be workaround by checking if there
>> is available descript("sdmac->desc") now once the unwanted interrupt
>> coming. At last the common virt-dma is easier for sdma driver maintain.
>>
>> Change from v2:
>> 1. include Sascha's patch to make the main patch easier to review.
>> Thanks Sacha.
>> 2. remove useless 'desc'/'chan' in struct sdma_channe.
>>
>> Change from v1:
>> 1. split v1 patch into 5 patches.
>> 2. remove some unnecessary condition check.
>> 3. remove unnecessary 'pending' list.
>>
>> Robin Gong (5):
>> dmaengine: imx-sdma: add virt-dma support
>> Revert "dmaengine: imx-sdma: fix pagefault when channel is disabled
>> during interrupt"
>> dmaengine: imx-sdma: remove usless lock
>> dmaengine: imx-sdma: remove the maximum limation for bd numbers
>> dmaengine: imx-sdma: add sdma_transfer_init to decrease code overlap
>>
>> drivers/dma/Kconfig | 1 +
>> drivers/dma/imx-sdma.c | 392 ++++++++++++++++++++++++++++---------------------
>> 2 files changed, 227 insertions(+), 166 deletions(-)
>>
>> --
>> 2.7.4
>>
>> Robin Gong (5):
>> dmaengine: imx-sdma: add virt-dma support
>> Revert "dmaengine: imx-sdma: fix pagefault when channel is disabled
>> during interrupt"
>> dmaengine: imx-sdma: remove usless lock
>> dmaengine: imx-sdma: remove the maximum limation for bd numbers
>> dmaengine: imx-sdma: add sdma_transfer_init to decrease code overlap
>>
>> Sascha Hauer (1):
>> dmaengine: imx-sdma: factor out a struct sdma_desc from struct
>> sdma_channel
>>
>> drivers/dma/Kconfig | 1 +
>> drivers/dma/imx-sdma.c | 391 ++++++++++++++++++++++++++++---------------------
>> 2 files changed, 226 insertions(+), 166 deletions(-)
>>
^ permalink raw reply
* [PATCH V5] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Marek Vasut @ 2018-06-11 12:15 UTC (permalink / raw)
To: linux-arm-kernel
Rather than hard-coding the quirk topology, which stopped scaling,
parse the information from DT. The code looks for all compatible
PMICs -- da9063 and da9210 -- and checks if their IRQ line is tied
to the same pin. If so, the code sends a matching sequence to the
PMIC to deassert the IRQ.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: linux-renesas-soc at vger.kernel.org
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> (on Koelsch)
---
V2: - Replace the DT shared IRQ check loop with memcmp()
- Send the I2C message to deassert the IRQ line to all PMICs
in the list with shared IRQ line instead of just one
- Add comment that this works only in case all the PMICs are
on the same I2C bus
V3: - Drop the addr = 0x00 init
- Drop reinit of argsa in rcar_gen2_regulator_quirk
V4: - Squash regulator_quirk on single line
- Drop !np check in for_each_matching_node_and_match()
- Use argsa in of_irq_parse_one
V5: - Check kzalloc failure
- Rename da...._msgs to da...._msg
- Don't reinit quirk->shared
---
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 137 ++++++++++++++++-----
1 file changed, 108 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index 93f628acfd94..cf4d260882cf 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -31,11 +31,12 @@
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/list.h>
#include <linux/notifier.h>
#include <linux/of.h>
+#include <linux/of_irq.h>
#include <linux/mfd/da9063/registers.h>
-
#define IRQC_BASE 0xe61c0000
#define IRQC_MONITOR 0x104 /* IRQn Signal Level Monitor Register */
@@ -44,34 +45,45 @@
/* start of DA9210 System Control and Event Registers */
#define DA9210_REG_MASK_A 0x54
+struct regulator_quirk {
+ struct list_head list;
+ const struct of_device_id *id;
+ struct of_phandle_args irq_args;
+ struct i2c_msg i2c_msg;
+ bool shared; /* IRQ line is shared */
+};
+
+static LIST_HEAD(quirk_list);
static void __iomem *irqc;
/* first byte sets the memory pointer, following are consecutive reg values */
static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
-static struct i2c_msg da9xxx_msgs[3] = {
- {
- .addr = 0x58,
- .len = ARRAY_SIZE(da9063_irq_clr),
- .buf = da9063_irq_clr,
- }, {
- .addr = 0x68,
- .len = ARRAY_SIZE(da9210_irq_clr),
- .buf = da9210_irq_clr,
- }, {
- .addr = 0x70,
- .len = ARRAY_SIZE(da9210_irq_clr),
- .buf = da9210_irq_clr,
- },
+static struct i2c_msg da9063_msg = {
+ .len = ARRAY_SIZE(da9063_irq_clr),
+ .buf = da9063_irq_clr,
+};
+
+static struct i2c_msg da9210_msg = {
+ .len = ARRAY_SIZE(da9210_irq_clr),
+ .buf = da9210_irq_clr,
+};
+
+static const struct of_device_id rcar_gen2_quirk_match[] = {
+ { .compatible = "dlg,da9063", .data = &da9063_msg },
+ { .compatible = "dlg,da9210", .data = &da9210_msg },
+ {},
};
static int regulator_quirk_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
+ struct regulator_quirk *pos, *tmp;
struct device *dev = data;
struct i2c_client *client;
static bool done;
+ int ret;
u32 mon;
if (done)
@@ -88,17 +100,20 @@ static int regulator_quirk_notify(struct notifier_block *nb,
client = to_i2c_client(dev);
dev_dbg(dev, "Detected %s\n", client->name);
- if ((client->addr == 0x58 && !strcmp(client->name, "da9063")) ||
- (client->addr == 0x68 && !strcmp(client->name, "da9210")) ||
- (client->addr == 0x70 && !strcmp(client->name, "da9210"))) {
- int ret, len;
+ /*
+ * Send message to all PMICs that share an IRQ line to deassert it.
+ *
+ * WARNING: This works only if all the PMICs are on the same I2C bus.
+ */
+ list_for_each_entry(pos, &quirk_list, list) {
+ if (!pos->shared)
+ continue;
- /* There are two DA9210 on Stout, one on the other boards. */
- len = of_machine_is_compatible("renesas,stout") ? 3 : 2;
+ dev_info(&client->dev, "clearing %s at 0x%02x interrupts\n",
+ pos->id->compatible, pos->i2c_msg.addr);
- dev_info(&client->dev, "clearing da9063/da9210 interrupts\n");
- ret = i2c_transfer(client->adapter, da9xxx_msgs, len);
- if (ret != len)
+ ret = i2c_transfer(client->adapter, &pos->i2c_msg, 1);
+ if (ret != 1)
dev_err(&client->dev, "i2c error %d\n", ret);
}
@@ -111,6 +126,11 @@ static int regulator_quirk_notify(struct notifier_block *nb,
remove:
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
+ list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
+ list_del(&pos->list);
+ kfree(pos);
+ }
+
done = true;
iounmap(irqc);
return 0;
@@ -122,7 +142,12 @@ static struct notifier_block regulator_quirk_nb = {
static int __init rcar_gen2_regulator_quirk(void)
{
- u32 mon;
+ struct regulator_quirk *quirk, *pos, *tmp;
+ struct of_phandle_args *argsa, *argsb;
+ const struct of_device_id *id;
+ struct device_node *np;
+ u32 mon, addr;
+ int ret;
if (!of_machine_is_compatible("renesas,koelsch") &&
!of_machine_is_compatible("renesas,lager") &&
@@ -130,22 +155,76 @@ static int __init rcar_gen2_regulator_quirk(void)
!of_machine_is_compatible("renesas,gose"))
return -ENODEV;
+ for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
+ if (!of_device_is_available(np))
+ break;
+
+ quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
+ if (!quirk) {
+ ret = -ENOMEM;
+ goto err_mem;
+ }
+
+ argsa = &quirk->irq_args;
+ memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
+
+ ret = of_property_read_u32(np, "reg", &addr);
+ if (ret)
+ return ret;
+
+ quirk->id = id;
+ quirk->i2c_msg.addr = addr;
+
+ ret = of_irq_parse_one(np, 0, argsa);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(pos, &quirk_list, list) {
+ argsb = &pos->irq_args;
+
+ if (argsa->args_count != argsb->args_count)
+ continue;
+
+ ret = memcmp(argsa->args, argsb->args,
+ argsa->args_count *
+ sizeof(argsa->args[0]));
+ if (!ret) {
+ pos->shared = true;
+ quirk->shared = true;
+ }
+ }
+
+ list_add_tail(&quirk->list, &quirk_list);
+ }
+
irqc = ioremap(IRQC_BASE, PAGE_SIZE);
- if (!irqc)
- return -ENOMEM;
+ if (!irqc) {
+ ret = -ENOMEM;
+ goto err_mem;
+ }
mon = ioread32(irqc + IRQC_MONITOR);
if (mon & REGULATOR_IRQ_MASK) {
pr_debug("%s: IRQ2 is not asserted, not installing quirk\n",
__func__);
- iounmap(irqc);
- return 0;
+ ret = 0;
+ goto err_free;
}
pr_info("IRQ2 is asserted, installing da9063/da9210 regulator quirk\n");
bus_register_notifier(&i2c_bus_type, ®ulator_quirk_nb);
return 0;
+
+err_free:
+ iounmap(irqc);
+err_mem:
+ list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
+ list_del(&pos->list);
+ kfree(pos);
+ }
+
+ return ret;
}
arch_initcall(rcar_gen2_regulator_quirk);
--
2.16.2
^ permalink raw reply related
* [PATCH v3] irqchip/gic-v3-its: fix ITS queue timeout
From: Yang Yingliang @ 2018-06-11 12:25 UTC (permalink / raw)
To: linux-arm-kernel
On a NUMA system, if an ITS is local to an offline
node, the ITS driver may pick an offline CPU to bind
the LPI. In this case, we need to pick an online CPU.
But on some systems, binding LPI to non-local node
CPU will cause deadlock. In this case, we don't
bind the LPI to any online CPU and return an error code.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5416f2b..137c433 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2309,7 +2309,13 @@ static int its_irq_domain_activate(struct irq_domain *domain,
cpu_mask = cpumask_of_node(its_dev->its->numa_node);
/* Bind the LPI to the first possible CPU */
- cpu = cpumask_first(cpu_mask);
+ cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
+ if (cpu >= nr_cpu_ids) {
+ if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
+ return -EINVAL;
+
+ cpu = cpumask_first(cpu_online_mask);
+ }
its_dev->event_map.col_map[event] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
--
1.8.3
^ permalink raw reply related
* [PATCH] arm64: dma-mapping: clear buffers allocated with FORCE_CONTIGUOUS flag
From: Will Deacon @ 2018-06-11 12:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdV8PTBArnaoXMXsuTqxLcizAZe4YO59TkZ6Wj-F4M6Sbg@mail.gmail.com>
On Mon, Jun 11, 2018 at 09:55:54AM +0200, Geert Uytterhoeven wrote:
> Hi Marek,
>
> Thanks for your patch!
>
> On Mon, Jun 11, 2018 at 7:14 AM Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
> > dma_alloc_*() buffers might be exposed to userspace via mmap() call, so
> > they should be cleared on allocation. In case of IOMMU-based dma-mapping
> > implementation such buffer clearing was missing in the code path for
> > DMA_ATTR_FORCE_CONTIGUOUS flag handling. This patch fixes this issue. For
>
> Is it? The memory is allocated using dma_alloc_from_contiguous(..., gfp),
> and __iommu_alloc_attrs() has
>
> /*
> * Some drivers rely on this, and we probably don't want the
> * possibility of stale kernel data being read by devices anyway.
> */
> gfp |= __GFP_ZERO;
>
> at the top, before the allocation.
>
> If cma_alloc() (called from dma_alloc_from_contiguous()) doesn't honor
> __GFP_ZERO, I think cma_alloc() should be fixed instead.
Agreed. We tried to fix this in 7132813c3845 ("arm64: Honor __GFP_ZERO in
dma allocations"). Has something broken that?
Will
^ permalink raw reply
* [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer
From: Stefan Agner @ 2018-06-11 12:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180607140544.22268-5-peron.clem@gmail.com>
On 07.06.2018 16:05, Cl?ment P?ron wrote:
> From: Colin Didier <colin.didier@devialet.com>
>
> Add driver for NXP's EPIT timer used in i.MX SoC.
>
> Signed-off-by: Colin Didier <colin.didier@devialet.com>
> Signed-off-by: Cl?ment Peron <clement.peron@devialet.com>
> ---
> drivers/clocksource/Kconfig | 11 ++
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-imx-epit.c | 265 +++++++++++++++++++++++++++
> 3 files changed, 277 insertions(+)
> create mode 100644 drivers/clocksource/timer-imx-epit.c
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 8e8a09755d10..790478afd02c 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -576,6 +576,17 @@ config H8300_TPU
> This enables the clocksource for the H8300 platform with the
> H8S2678 cpu.
>
> +config CLKSRC_IMX_EPIT
> + bool "Clocksource using i.MX EPIT"
> + depends on CLKDEV_LOOKUP && (ARCH_MXC || COMPILE_TEST)
> + select CLKSRC_MMIO
> + help
> + This enables EPIT support available on some i.MX platforms.
> + Normally you don't have a reason to do so as the EPIT has
> + the same features and uses the same clocks as the GPT.
> + Anyway, on some systems the GPT may be in use for other
> + purposes.
> +
> config CLKSRC_IMX_GPT
> bool "Clocksource using i.MX GPT" if COMPILE_TEST
> depends on ARM && CLKDEV_LOOKUP
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 00caf37e52f9..d9426f69ec69 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
> obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
> obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
> obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
> +obj-$(CONFIG_CLKSRC_IMX_EPIT) += timer-imx-epit.o
> obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
> obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
> obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
> diff --git a/drivers/clocksource/timer-imx-epit.c
> b/drivers/clocksource/timer-imx-epit.c
> new file mode 100644
> index 000000000000..15f70e210fad
> --- /dev/null
> +++ b/drivers/clocksource/timer-imx-epit.c
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * i.MX EPIT Timer
> + *
> + * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
> + * Copyright (C) 2018 Colin Didier <colin.didier@devialet.com>
> + * Copyright (C) 2018 Cl?ment P?ron <clement.peron@devialet.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/sched_clock.h>
> +#include <linux/slab.h>
> +
> +#define EPITCR 0x00
> +#define EPITSR 0x04
> +#define EPITLR 0x08
> +#define EPITCMPR 0x0c
> +#define EPITCNR 0x10
> +
> +#define EPITCR_EN BIT(0)
> +#define EPITCR_ENMOD BIT(1)
> +#define EPITCR_OCIEN BIT(2)
> +#define EPITCR_RLD BIT(3)
> +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
> +#define EPITCR_SWR BIT(16)
> +#define EPITCR_IOVW BIT(17)
> +#define EPITCR_DBGEN BIT(18)
> +#define EPITCR_WAITEN BIT(19)
> +#define EPITCR_RES BIT(20)
> +#define EPITCR_STOPEN BIT(21)
> +#define EPITCR_OM_DISCON (0 << 22)
> +#define EPITCR_OM_TOGGLE (1 << 22)
> +#define EPITCR_OM_CLEAR (2 << 22)
> +#define EPITCR_OM_SET (3 << 22)
> +#define EPITCR_CLKSRC_OFF (0 << 24)
> +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
> +#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
> +#define EPITCR_CLKSRC_REF_LOW (3 << 24)
> +
> +#define EPITSR_OCIF BIT(0)
> +
> +struct epit_timer {
> + void __iomem *base;
> + int irq;
> + struct clk *clk;
> + struct clock_event_device ced;
> + struct irqaction act;
> +};
> +
> +static void __iomem *sched_clock_reg;
> +
> +static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
> +{
> + return container_of(ced, struct epit_timer, ced);
> +}
> +
> +static inline void epit_irq_disable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static inline void epit_irq_enable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static void epit_irq_acknowledge(struct epit_timer *epittm)
> +{
> + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
> +}
> +
> +static u64 notrace epit_read_sched_clock(void)
> +{
> + return ~readl_relaxed(sched_clock_reg);
> +}
> +
> +static int epit_set_next_event(unsigned long cycles,
> + struct clock_event_device *ced)
> +{
> + struct epit_timer *epittm = to_epit_timer(ced);
> + unsigned long tcmp;
> +
> + tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
> + writel_relaxed(tcmp, epittm->base + EPITCMPR);
> +
> + return 0;
> +}
> +
> +/* Left event sources disabled, no more interrupts appear */
> +static int epit_shutdown(struct clock_event_device *ced)
> +{
> + struct epit_timer *epittm = to_epit_timer(ced);
> + unsigned long flags;
> +
> + /*
> + * The timer interrupt generation is disabled at least
> + * for enough time to call epit_set_next_event()
> + */
> + local_irq_save(flags);
> +
> + /* Disable interrupt in EPIT module */
> + epit_irq_disable(epittm);
> +
> + /* Clear pending interrupt */
> + epit_irq_acknowledge(epittm);
> +
> + local_irq_restore(flags);
> +
> + return 0;
> +}
> +
> +static int epit_set_oneshot(struct clock_event_device *ced)
> +{
> + struct epit_timer *epittm = to_epit_timer(ced);
> + unsigned long flags;
> +
> + /*
> + * The timer interrupt generation is disabled at least
> + * for enough time to call epit_set_next_event()
> + */
> + local_irq_save(flags);
> +
> + /* Disable interrupt in EPIT module */
> + epit_irq_disable(epittm);
> +
> + /* Clear pending interrupt, only while switching mode */
> + if (!clockevent_state_oneshot(ced))
> + epit_irq_acknowledge(epittm);
> +
> + /*
> + * Do not put overhead of interrupt enable/disable into
> + * epit_set_next_event(), the core has about 4 minutes
> + * to call epit_set_next_event() or shutdown clock after
> + * mode switching
> + */
> + epit_irq_enable(epittm);
> + local_irq_restore(flags);
> +
> + return 0;
> +}
> +
> +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
> +{
> + struct clock_event_device *ced = dev_id;
> + struct epit_timer *epittm = to_epit_timer(ced);
> +
> + epit_irq_acknowledge(epittm);
> +
> + ced->event_handler(ced);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int __init epit_clocksource_init(struct epit_timer *epittm)
> +{
> + unsigned int c = clk_get_rate(epittm->clk);
> +
> + sched_clock_reg = epittm->base + EPITCNR;
> + sched_clock_register(epit_read_sched_clock, 32, c);
> +
> + return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
> + clocksource_mmio_readl_down);
> +}
> +
> +static int __init epit_clockevent_init(struct epit_timer *epittm)
> +{
> + struct clock_event_device *ced = &epittm->ced;
> + struct irqaction *act = &epittm->act;
> +
> + ced->name = "epit";
> + ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
> + ced->set_state_shutdown = epit_shutdown;
> + ced->tick_resume = epit_shutdown;
> + ced->set_state_oneshot = epit_set_oneshot;
> + ced->set_next_event = epit_set_next_event;
> + ced->rating = 200;
> + ced->cpumask = cpumask_of(0);
> + ced->irq = epittm->irq;
> + clockevents_config_and_register(ced, clk_get_rate(epittm->clk),
> + 0xff, 0xfffffffe);
> +
> + act->name = "i.MX EPIT Timer Tick",
> + act->flags = IRQF_TIMER | IRQF_IRQPOLL;
> + act->handler = epit_timer_interrupt;
> + act->dev_id = ced;
> +
> + /* Make irqs happen */
> + return setup_irq(epittm->irq, act);
> +}
> +
> +static int __init epit_timer_init(struct device_node *np)
> +{
> + struct epit_timer *epittm;
> + int ret;
> +
> + epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
> + if (!epittm)
> + return -ENOMEM;
> +
> + epittm->base = of_iomap(np, 0);
> + if (!epittm->base) {
> + ret = -ENXIO;
> + goto out_kfree;
> + }
> +
> + epittm->irq = irq_of_parse_and_map(np, 0);
> + if (!epittm->irq) {
> + ret = -EINVAL;
> + goto out_iounmap;
> + }
> +
> + /* Get EPIT clock */
> + epittm->clk = of_clk_get(np, 0);
> + if (IS_ERR(epittm->clk)) {
> + pr_err("i.MX EPIT: unable to get clk\n");
> + ret = PTR_ERR(epittm->clk);
> + goto out_iounmap;
> + }
There is something off with indent here.
There is a helper library in drivers/clocksource/timer-of.c which might
be useful for this driver.
--
Stefan
> +
> + ret = clk_prepare_enable(epittm->clk);
> + if (ret) {
> + pr_err("i.MX EPIT: unable to prepare+enable clk\n");
> + goto out_iounmap;
> + }
> +
> + /* Initialise to a known state (all timers off, and timing reset) */
> + writel_relaxed(0x0, epittm->base + EPITCR);
> + writel_relaxed(0xffffffff, epittm->base + EPITLR);
> + writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
> + epittm->base + EPITCR);
> +
> + ret = epit_clocksource_init(epittm);
> + if (ret) {
> + pr_err("i.MX EPIT: failed to init clocksource\n");
> + goto out_clk_disable;
> + }
> +
> + ret = epit_clockevent_init(epittm);
> + if (ret) {
> + pr_err("i.MX EPIT: failed to init clockevent\n");
> + goto out_clk_disable;
> + }
> +
> + return 0;
> +
> +out_clk_disable:
> + clk_disable_unprepare(epittm->clk);
> +out_iounmap:
> + iounmap(epittm->base);
> +out_kfree:
> + kfree(epittm);
> +
> + return ret;
> +}
> +TIMER_OF_DECLARE(epit_timer, "fsl,imx31-epit", epit_timer_init);
^ permalink raw reply
* [PATCH 1/2] arm64: avoid alloc memory on offline node
From: Xie XiuQi @ 2018-06-11 12:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180611085237.GI13364@dhcp22.suse.cz>
Hi Michal,
On 2018/6/11 16:52, Michal Hocko wrote:
> On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> Hi Michal,
>>
>> On 2018/6/7 20:21, Michal Hocko wrote:
>>> On Thu 07-06-18 19:55:53, Hanjun Guo wrote:
>>>> On 2018/6/7 18:55, Michal Hocko wrote:
>>> [...]
>>>>> I am not sure I have the full context but pci_acpi_scan_root calls
>>>>> kzalloc_node(sizeof(*info), GFP_KERNEL, node)
>>>>> and that should fall back to whatever node that is online. Offline node
>>>>> shouldn't keep any pages behind. So there must be something else going
>>>>> on here and the patch is not the right way to handle it. What does
>>>>> faddr2line __alloc_pages_nodemask+0xf0 tells on this kernel?
>>>>
>>>> The whole context is:
>>>>
>>>> The system is booted with a NUMA node has no memory attaching to it
>>>> (memory-less NUMA node), also with NR_CPUS less than CPUs presented
>>>> in MADT, so CPUs on this memory-less node are not brought up, and
>>>> this NUMA node will not be online (but SRAT presents this NUMA node);
>>>>
>>>> Devices attaching to this NUMA node such as PCI host bridge still
>>>> return the valid NUMA node via _PXM, but actually that valid NUMA node
>>>> is not online which lead to this issue.
>>>
>>> But we should have other numa nodes on the zonelists so the allocator
>>> should fall back to other node. If the zonelist is not intiailized
>>> properly, though, then this can indeed show up as a problem. Knowing
>>> which exact place has blown up would help get a better picture...
>>>
>>
>> I specific a non-exist node to allocate memory using kzalloc_node,
>> and got this following error message.
>>
>> And I found out there is just a VM_WARN, but it does not prevent the memory
>> allocation continue.
>>
>> This nid would be use to access NODE_DADA(nid), so if nid is invalid,
>> it would cause oops here.
>>
>> 459 /*
>> 460 * Allocate pages, preferring the node given as nid. The node must be valid and
>> 461 * online. For more general interface, see alloc_pages_node().
>> 462 */
>> 463 static inline struct page *
>> 464 __alloc_pages_node(int nid, gfp_t gfp_mask, unsigned int order)
>> 465 {
>> 466 VM_BUG_ON(nid < 0 || nid >= MAX_NUMNODES);
>> 467 VM_WARN_ON(!node_online(nid));
>> 468
>> 469 return __alloc_pages(gfp_mask, order, nid);
>> 470 }
>> 471
>>
>> (I wrote a ko, to allocate memory on a non-exist node using kzalloc_node().)
>
> OK, so this is an artificialy broken code, right. You shouldn't get a
> non-existent node via standard APIs AFAICS. The original report was
> about an existing node which is offline AFAIU. That would be a different
> case. If I am missing something and there are legitimate users that try
> to allocate from non-existing nodes then we should handle that in
> node_zonelist.
I think hanjun's comments may help to understood this question:
- NUMA node will be built if CPUs and (or) memory are valid on this NUMA node;
- But if we boot the system with memory-less node and also with CONFIG_NR_CPUS
less than CPUs in SRAT, for example, 64 CPUs total with 4 NUMA nodes, 16 CPUs
on each NUMA node, if we boot with CONFIG_NR_CPUS=48, then we will not built
numa node for node 3, but with devices on that numa node, alloc memory will
be panic because NUMA node 3 is not a valid node.
I triggered this BUG on arm64 platform, and I found a similar bug has been fixed
on x86 platform. So I sent a similar patch for this bug.
Or, could we consider to fix it in the mm subsystem?
>From b755de8dfdfef97effaa91379ffafcb81f4d62a1 Mon Sep 17 00:00:00 2001
From: Yinghai Lu <Yinghai.Lu@Sun.COM>
Date: Wed, 20 Feb 2008 12:41:52 -0800
Subject: [PATCH] x86: make dev_to_node return online node
a numa system (with multi HT chains) may return node without ram. Aka it
is not online. Try to get an online node, otherwise return -1.
Signed-off-by: Yinghai Lu <yinghai.lu@sun.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/pci/acpi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index d95de2f..ea8685f 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -172,6 +172,9 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int do
set_mp_bus_to_node(busnum, node);
else
node = get_mp_bus_to_node(busnum);
+
+ if (node != -1 && !node_online(node))
+ node = -1;
#endif
/* Allocate per-root-bus (not per bus) arch-specific data.
--
1.8.3.1
>
> [...]
>
--
Thanks,
Xie XiuQi
^ permalink raw reply related
* [PATCH] media: stm32-dcmi: add power saving support
From: kbuild test robot @ 2018-06-11 12:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528709597-7734-1-git-send-email-hugues.fruchet@st.com>
Hi Hugues,
I love your patch! Yet something to improve:
[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.17 next-20180608]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Hugues-Fruchet/media-stm32-dcmi-add-power-saving-support/20180611-174016
base: git://linuxtv.org/media_tree.git master
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/media/platform/stm32/stm32-dcmi.c: In function 'dcmi_suspend':
>> drivers/media/platform/stm32/stm32-dcmi.c:1886:2: error: implicit declaration of function 'pinctrl_pm_select_sleep_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_sleep_state(dev);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media/platform/stm32/stm32-dcmi.c: In function 'dcmi_resume':
>> drivers/media/platform/stm32/stm32-dcmi.c:1894:2: error: implicit declaration of function 'pinctrl_pm_select_default_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_default_state(dev);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/pinctrl_pm_select_sleep_state +1886 drivers/media/platform/stm32/stm32-dcmi.c
1879
1880 static __maybe_unused int dcmi_suspend(struct device *dev)
1881 {
1882 /* disable clock */
1883 pm_runtime_force_suspend(dev);
1884
1885 /* change pinctrl state */
> 1886 pinctrl_pm_select_sleep_state(dev);
1887
1888 return 0;
1889 }
1890
1891 static __maybe_unused int dcmi_resume(struct device *dev)
1892 {
1893 /* restore pinctl default state */
> 1894 pinctrl_pm_select_default_state(dev);
1895
1896 /* clock enable */
1897 pm_runtime_force_resume(dev);
1898
1899 return 0;
1900 }
1901
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [RFC] Configure i.MX6 RGMII pad group control registers from device tree
From: Michal Vokáč @ 2018-06-11 12:36 UTC (permalink / raw)
To: linux-arm-kernel
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = <PIN_FUNC_ID CONFIG> property can be used. Is there any convenient
way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and ODT) in the individual RGMII pad
control registers are read-only. To tweak those parameters (signal voltage and
termination resistors) one need to write to the pad group control registers for
the whole RGMII pad group. Namely IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII and
IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM. The group registers in general are not
accessible from the list in arch/arm/boot/dts/imx6dl-pinfunc.h.
I could not find any other way to change the group registers than hacking-in
some lines into the imx6q_init_machine(void) function in
arch/arm/mach-imx/mach-imx6q.c source. As I work towards upstreaming my board
this should be done from my device tree or solved in some universal way.
Any hints will be much appreciated.
Michal
^ permalink raw reply
* [PATCH v1] ARM: imx: add imx7d-m4
From: Stefan Agner @ 2018-06-11 12:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a4657c84-a807-d194-950c-38f5f8e4a53c@pengutronix.de>
On 11.06.2018 13:53, Oleksij Rempel wrote:
> On 11.06.2018 13:48, Stefan Agner wrote:
>> On 11.06.2018 10:35, Lucas Stach wrote:
>>> Hi Shawn,
>>>
>>> Am Montag, den 11.06.2018, 16:20 +0800 schrieb Shawn Guo:
>>>> On Mon, Jun 11, 2018 at 10:02:53AM +0200, Oleksij Rempel wrote:
>>>>> Hi all,
>>>>>
>>>>> this patch was send 05.04.2018. Any comments?
>>>>>
>>>>> @Shawn, can you please take it?
>>>>
>>>> Honestly I'm not sure how useful it will be.??If we can have some i.MX
>>>> developers ACK on it, I will be more comfortable to take it.
>>>
>>> This is all highly experimental and in PoC stage, but we see some value
>>> in running a second Linux system on the M4 coprocessor. There are lots
>>> of things that still need to be figured out, but we are working on this
>>> from time to time when there are some hours to spare.
>>>
>>> This patch seems like a good step in the right direction and IMHO the
>>> amount of code and changes is small enough to carry it upstream without
>>> impacting anything else. I would be happy if this could be pulled in.
>>
>> I agree with Lucas here, this is rather minimal and not invasive.
>>
>>
>> Out of interest, on what memory region do you run Linux? Do you use
>> caches? In some experiments a while ago I noticed that only 2MiB/(or
>> 4MiB) of DDR memory can use caches, which is somewhat tight to run Linux
>> on.
>>
>> https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/
>
> here is DT part for master system on Cortex A7 to run Linux on Cortex M4:
>
> memory {
> device_type = "memory";
> reg = <0x80000000 0x40000000>;
> };
>
> reserved-memory {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> m4_reserved_sysmem1: rproc at 88000000 {
> reg = <0x88000000 0x4000000>;
> no-map;
> };
So I guess that is where Linux on the M4 goes? Afaik this is in the
uncacheable area, so it is rather slow?
--
Stefan
>
> /* not really needed node. used as example */
> m4_reserved_sysmem2: rproc at 88080000 {
> reg = <0x8c000000 0x80000>;
> no-map;
> };
> };
>
> mailbox_test {
> compatible = "mailbox-test";
> reg = <0x00900000 0x00020000>, <0x00920000
> 0x00020000>;
> mboxes = <&mu0a 0>, <&mu0a 0>;
> mbox-names = "tx", "rx";
> };
> };
>
> /* node reserved for rproc */
> &uart1 {
> assigned-clock-rates = <240000000>;
> status = "disabled";
> };
>
> &gpt2 {
> assigned-clock-rates = <24000000>;
> status = "disabled";
> };
>
> &mu0a {
> status = "okay";
> #mbox-cells = <1>;
> };
>
> &imx_rproc {
> status = "okay";
> memory-region = <&m4_reserved_sysmem1>,
> <&m4_reserved_sysmem2>;
>
> remote-nodes = <&gpt2>, <&uart1>;
> };
>
>
>
>> --
>> Stefan
>>
>>
>>>>>
>>>>> On 05.04.2018 13:51, Oleksij Rempel wrote:
>>>>>> Provide basic support for Cortex-M4 located on NXP iMX7D.
>>>>>> This code was tested in combination with imx-rproc driver
>>>>>> which will upload with specially formatted ELF image containing
>>>>>> kernel, device and CPIO rootfs.
>>>>>>
>>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>>> ---
>>>>>> ?arch/arm/boot/dts/Makefile?????????|??2 +-
>>>>>> ?arch/arm/mach-imx/Kconfig??????????| 33 +++++++++++++++++++++------------
>>>>>> ?arch/arm/mach-imx/Makefile?????????|??3 ++-
>>>>>> ?arch/arm/mach-imx/mach-imx7d-cm4.c | 21 +++++++++++++++++++++
>>>>>> ?4 files changed, 45 insertions(+), 14 deletions(-)
>>>>>> ?create mode 100644 arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>>>>> index 852452515bea..d49bb9a58aee 100644
>>>>>> --- a/arch/arm/boot/dts/Makefile
>>>>>> +++ b/arch/arm/boot/dts/Makefile
>>>>>> @@ -527,7 +527,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>>>>>>>>> ? imx6ul-tx6ul-0011.dtb \
>>>>>>>>> ? imx6ul-tx6ul-mainboard.dtb \
>>>>>>>>> ? imx6ull-14x14-evk.dtb
>>>>>> -dtb-$(CONFIG_SOC_IMX7D) += \
>>>>>> +dtb-$(CONFIG_SOC_IMX7D_CA7) += \
>>>>>>>>> ? imx7d-cl-som-imx7.dtb \
>>>>>>>>> ? imx7d-colibri-emmc-eval-v3.dtb \
>>>>>>>>> ? imx7d-colibri-eval-v3.dtb \
>>>>>> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
>>>>>> index 782699e67600..101c8599d952 100644
>>>>>> --- a/arch/arm/mach-imx/Kconfig
>>>>>> +++ b/arch/arm/mach-imx/Kconfig
>>>>>> @@ -528,18 +528,6 @@ config SOC_IMX6UL
>>>>>>>>> ? help
>>>>>>>>> ? ??This enables support for Freescale i.MX6 UltraLite processor.
>>>>>> ?
>>>>>> -config SOC_IMX7D
>>>>>>>>> - bool "i.MX7 Dual support"
>>>>>>>>> - select PINCTRL_IMX7D
>>>>>>>>> - select ARM_GIC
>>>>>>>>> - select HAVE_ARM_ARCH_TIMER
>>>>>>>>> - select HAVE_IMX_ANATOP
>>>>>>>>> - select HAVE_IMX_MMDC
>>>>>>>>> - select HAVE_IMX_SRC
>>>>>>>>> - select IMX_GPCV2
>>>>>>>>> - help
>>>>>>>>> - This enables support for Freescale i.MX7 Dual processor.
>>>>>> -
>>>>>> ?config SOC_LS1021A
>>>>>>>>> ? bool "Freescale LS1021A support"
>>>>>>>>> ? select ARM_GIC
>>>>>> @@ -554,6 +542,27 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
>>>>>> ?
>>>>>> ?if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
>>>>>> ?
>>>>>> +config SOC_IMX7D_CA7
>>>>>>>>> + bool
>>>>>>>>> + select ARM_GIC
>>>>>>>>> + select HAVE_ARM_ARCH_TIMER
>>>>>>>>> + select HAVE_IMX_ANATOP
>>>>>>>>> + select HAVE_IMX_MMDC
>>>>>>>>> + select HAVE_IMX_SRC
>>>>>>>>> + select IMX_GPCV2
>>>>>> +
>>>>>> +config SOC_IMX7D_CM4
>>>>>>>>> + bool
>>>>>>>>> + select ARMV7M_SYSTICK
>>>>>> +
>>>>>> +config SOC_IMX7D
>>>>>>>>> + bool "i.MX7 Dual support"
>>>>>>>>> + select PINCTRL_IMX7D
>>>>>>>>> + select SOC_IMX7D_CA7 if ARCH_MULTI_V7
>>>>>>>>> + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
>>>>>>>>> + help
>>>>>>>>> + This enables support for Freescale i.MX7 Dual processor.
>>>>>> +
>>>>>> ?config SOC_VF610
>>>>>>>>> ? bool "Vybrid Family VF610 support"
>>>>>>>>> ? select ARM_GIC if ARCH_MULTI_V7
>>>>>> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
>>>>>> index 8ff71058207d..68640f100ef3 100644
>>>>>> --- a/arch/arm/mach-imx/Makefile
>>>>>> +++ b/arch/arm/mach-imx/Makefile
>>>>>> @@ -80,7 +80,8 @@ obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
>>>>>> ?obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
>>>>>> ?obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
>>>>>> ?obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
>>>>>> -obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
>>>>>> +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
>>>>>> +obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
>>>>>> ?
>>>>>> ?ifeq ($(CONFIG_SUSPEND),y)
>>>>>> ?AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
>>>>>> diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>>> new file mode 100644
>>>>>> index 000000000000..c36dea79aeb8
>>>>>> --- /dev/null
>>>>>> +++ b/arch/arm/mach-imx/mach-imx7d-cm4.c
>>>>>> @@ -0,0 +1,21 @@
>>>>>> +/*
>>>>>> + * Copyright 2017 Pengutronix
>>>>>> + *
>>>>>> + * This program is free software; you can redistribute it and/or modify
>>>>>> + * it under the terms of the GNU General Public License version 2 as
>>>>>> + * published by the Free Software Foundation.
>>>>>> + */
>>>>>> +
>>>>>> +#include <linux/kernel.h>
>>>>>> +#include <asm/v7m.h>
>>>>>> +#include <asm/mach/arch.h>
>>>>>> +
>>>>>> +static const char * const imx7d_cm4_dt_compat[] __initconst = {
>>>>>>>>> + "fsl,imx7d-cm4",
>>>>>>>>> + NULL,
>>>>>> +};
>>>>>> +
>>>>>> +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
>>>>>>>>> + .dt_compat = imx7d_cm4_dt_compat,
>>>>>>>>> + .restart = armv7m_restart,
>>>>>> +MACHINE_END
>>>>>>
>>>>
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel at lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer
From: Clément Péron @ 2018-06-11 12:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5df13d8f6422d9099c1692dd2091d9ca@agner.ch>
Hi Stefan,
> > +
> > +#define EPITCR 0x00
> > +#define EPITSR 0x04
> > +#define EPITLR 0x08
> > +#define EPITCMPR 0x0c
> > +#define EPITCNR 0x10
> > +
> > +#define EPITCR_EN BIT(0)
> > +#define EPITCR_ENMOD BIT(1)
> > +#define EPITCR_OCIEN BIT(2)
> > +#define EPITCR_RLD BIT(3)
> > +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
> > +#define EPITCR_SWR BIT(16)
> > +#define EPITCR_IOVW BIT(17)
> > +#define EPITCR_DBGEN BIT(18)
> > +#define EPITCR_WAITEN BIT(19)
> > +#define EPITCR_RES BIT(20)
> > +#define EPITCR_STOPEN BIT(21)
> > +#define EPITCR_OM_DISCON (0 << 22)
> > +#define EPITCR_OM_TOGGLE (1 << 22)
> > +#define EPITCR_OM_CLEAR (2 << 22)
> > +#define EPITCR_OM_SET (3 << 22)
> > +#define EPITCR_CLKSRC_OFF (0 << 24)
> > +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
> > +#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
> > +#define EPITCR_CLKSRC_REF_LOW (3 << 24)
> > +
> > +#define EPITSR_OCIF BIT(0)
> > +
> > +struct epit_timer {
> > + void __iomem *base;
> > + int irq;
> > + struct clk *clk;
> > + struct clock_event_device ced;
> > + struct irqaction act;
> > +};
> > +
> > +static void __iomem *sched_clock_reg;
> > +
> > +static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
> > +{
> > + return container_of(ced, struct epit_timer, ced);
> > +}
> > +
> > +static inline void epit_irq_disable(struct epit_timer *epittm)
> > +{
> > + u32 val;
> > +
> > + val = readl_relaxed(epittm->base + EPITCR);
> > + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
> > +}
> > +
> > +static inline void epit_irq_enable(struct epit_timer *epittm)
> > +{
> > + u32 val;
> > +
> > + val = readl_relaxed(epittm->base + EPITCR);
> > + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
> > +}
> > +
> > +static void epit_irq_acknowledge(struct epit_timer *epittm)
> > +{
> > + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
> > +}
> > +
> > +static u64 notrace epit_read_sched_clock(void)
> > +{
> > + return ~readl_relaxed(sched_clock_reg);
> > +}
> > +
> > +static int epit_set_next_event(unsigned long cycles,
> > + struct clock_event_device *ced)
> > +{
> > + struct epit_timer *epittm = to_epit_timer(ced);
> > + unsigned long tcmp;
> > +
> > + tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
> > + writel_relaxed(tcmp, epittm->base + EPITCMPR);
> > +
> > + return 0;
> > +}
> > +
> > +/* Left event sources disabled, no more interrupts appear */
> > +static int epit_shutdown(struct clock_event_device *ced)
> > +{
> > + struct epit_timer *epittm = to_epit_timer(ced);
> > + unsigned long flags;
> > +
> > + /*
> > + * The timer interrupt generation is disabled at least
> > + * for enough time to call epit_set_next_event()
> > + */
> > + local_irq_save(flags);
> > +
> > + /* Disable interrupt in EPIT module */
> > + epit_irq_disable(epittm);
> > +
> > + /* Clear pending interrupt */
> > + epit_irq_acknowledge(epittm);
> > +
> > + local_irq_restore(flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int epit_set_oneshot(struct clock_event_device *ced)
> > +{
> > + struct epit_timer *epittm = to_epit_timer(ced);
> > + unsigned long flags;
> > +
> > + /*
> > + * The timer interrupt generation is disabled at least
> > + * for enough time to call epit_set_next_event()
> > + */
> > + local_irq_save(flags);
> > +
> > + /* Disable interrupt in EPIT module */
> > + epit_irq_disable(epittm);
> > +
> > + /* Clear pending interrupt, only while switching mode */
> > + if (!clockevent_state_oneshot(ced))
> > + epit_irq_acknowledge(epittm);
> > +
> > + /*
> > + * Do not put overhead of interrupt enable/disable into
> > + * epit_set_next_event(), the core has about 4 minutes
> > + * to call epit_set_next_event() or shutdown clock after
> > + * mode switching
> > + */
> > + epit_irq_enable(epittm);
> > + local_irq_restore(flags);
> > +
> > + return 0;
> > +}
> > +
> > +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
> > +{
> > + struct clock_event_device *ced = dev_id;
> > + struct epit_timer *epittm = to_epit_timer(ced);
> > +
> > + epit_irq_acknowledge(epittm);
> > +
> > + ced->event_handler(ced);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int __init epit_clocksource_init(struct epit_timer *epittm)
> > +{
> > + unsigned int c = clk_get_rate(epittm->clk);
> > +
> > + sched_clock_reg = epittm->base + EPITCNR;
> > + sched_clock_register(epit_read_sched_clock, 32, c);
> > +
> > + return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
> > + clocksource_mmio_readl_down);
> > +}
> > +
> > +static int __init epit_clockevent_init(struct epit_timer *epittm)
> > +{
> > + struct clock_event_device *ced = &epittm->ced;
> > + struct irqaction *act = &epittm->act;
> > +
> > + ced->name = "epit";
> > + ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
> > + ced->set_state_shutdown = epit_shutdown;
> > + ced->tick_resume = epit_shutdown;
> > + ced->set_state_oneshot = epit_set_oneshot;
> > + ced->set_next_event = epit_set_next_event;
> > + ced->rating = 200;
> > + ced->cpumask = cpumask_of(0);
> > + ced->irq = epittm->irq;
> > + clockevents_config_and_register(ced, clk_get_rate(epittm->clk),
> > + 0xff, 0xfffffffe);
> > +
> > + act->name = "i.MX EPIT Timer Tick",
> > + act->flags = IRQF_TIMER | IRQF_IRQPOLL;
> > + act->handler = epit_timer_interrupt;
> > + act->dev_id = ced;
> > +
> > + /* Make irqs happen */
> > + return setup_irq(epittm->irq, act);
> > +}
> > +
> > +static int __init epit_timer_init(struct device_node *np)
> > +{
> > + struct epit_timer *epittm;
> > + int ret;
> > +
> > + epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
> > + if (!epittm)
> > + return -ENOMEM;
> > +
> > + epittm->base = of_iomap(np, 0);
> > + if (!epittm->base) {
> > + ret = -ENXIO;
> > + goto out_kfree;
> > + }
> > +
> > + epittm->irq = irq_of_parse_and_map(np, 0);
> > + if (!epittm->irq) {
> > + ret = -EINVAL;
> > + goto out_iounmap;
> > + }
> > +
> > + /* Get EPIT clock */
> > + epittm->clk = of_clk_get(np, 0);
> > + if (IS_ERR(epittm->clk)) {
> > + pr_err("i.MX EPIT: unable to get clk\n");
> > + ret = PTR_ERR(epittm->clk);
> > + goto out_iounmap;
> > + }
>
> There is something off with indent here.
Thanks for pointing out that, I will fix it.
>
> There is a helper library in drivers/clocksource/timer-of.c which might
> be useful for this driver.
Indeed, but will require a bit of rewrite.
Clement
>
> --
> Stefan
>
> > +
> > + ret = clk_prepare_enable(epittm->clk);
> > + if (ret) {
> > + pr_err("i.MX EPIT: unable to prepare+enable clk\n");
> > + goto out_iounmap;
> > + }
> > +
> > + /* Initialise to a known state (all timers off, and timing reset) */
> > + writel_relaxed(0x0, epittm->base + EPITCR);
> > + writel_relaxed(0xffffffff, epittm->base + EPITLR);
> > + writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
> > + epittm->base + EPITCR);
> > +
> > + ret = epit_clocksource_init(epittm);
> > + if (ret) {
> > + pr_err("i.MX EPIT: failed to init clocksource\n");
> > + goto out_clk_disable;
> > + }
> > +
> > + ret = epit_clockevent_init(epittm);
> > + if (ret) {
> > + pr_err("i.MX EPIT: failed to init clockevent\n");
> > + goto out_clk_disable;
> > + }
> > +
> > + return 0;
> > +
> > +out_clk_disable:
> > + clk_disable_unprepare(epittm->clk);
> > +out_iounmap:
> > + iounmap(epittm->base);
> > +out_kfree:
> > + kfree(epittm);
> > +
> > + return ret;
> > +}
> > +TIMER_OF_DECLARE(epit_timer, "fsl,imx31-epit", epit_timer_init);
^ permalink raw reply
* [PATCH 1/1] ARM: dts: s5pv210: Add missing interrupt-controller property to gph2
From: Krzysztof Kozlowski @ 2018-06-11 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528640149-2195-1-git-send-email-pawel.mikolaj.chmiel@gmail.com>
On Sun, Jun 10, 2018 at 4:15 PM, Pawe? Chmiel
<pawel.mikolaj.chmiel@gmail.com> wrote:
> This commit adds missing interrupt-controller property to gph2 block,
Just "Add missing". See:
https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151
> to silence following warnings during build
> /soc/pinctrl at e0200000/gph2: Missing interrupt-controller or interrupt-map property
>
> Observed on not yet mainlined, an S5PV210 based
> Samsung Galaxy S (i9000) phone.
The warning is not reproduceable (as you mentioned board is not
present in mainline) thus please skip it. Instead, either describe
existing reason for this change (e.g. because bindings require it for
node of every bank of pins supporting GPIO interrupts) or include this
in series mainlining new board (where the reason will be - it will be
used by new board etc).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer
From: Stefan Agner @ 2018-06-11 12:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJiuCcdHKpfCkLhV=rZcLHx2k9BAh7bnDQMWDkquXJOYiQoTeA@mail.gmail.com>
On 11.06.2018 14:42, Cl?ment P?ron wrote:
> Hi Stefan,
>
>
>> > +
>> > +#define EPITCR 0x00
>> > +#define EPITSR 0x04
>> > +#define EPITLR 0x08
>> > +#define EPITCMPR 0x0c
>> > +#define EPITCNR 0x10
>> > +
>> > +#define EPITCR_EN BIT(0)
>> > +#define EPITCR_ENMOD BIT(1)
>> > +#define EPITCR_OCIEN BIT(2)
>> > +#define EPITCR_RLD BIT(3)
>> > +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
>> > +#define EPITCR_SWR BIT(16)
>> > +#define EPITCR_IOVW BIT(17)
>> > +#define EPITCR_DBGEN BIT(18)
>> > +#define EPITCR_WAITEN BIT(19)
>> > +#define EPITCR_RES BIT(20)
>> > +#define EPITCR_STOPEN BIT(21)
>> > +#define EPITCR_OM_DISCON (0 << 22)
>> > +#define EPITCR_OM_TOGGLE (1 << 22)
>> > +#define EPITCR_OM_CLEAR (2 << 22)
>> > +#define EPITCR_OM_SET (3 << 22)
>> > +#define EPITCR_CLKSRC_OFF (0 << 24)
>> > +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
>> > +#define EPITCR_CLKSRC_REF_HIGH (2 << 24)
>> > +#define EPITCR_CLKSRC_REF_LOW (3 << 24)
>> > +
>> > +#define EPITSR_OCIF BIT(0)
>> > +
>> > +struct epit_timer {
>> > + void __iomem *base;
>> > + int irq;
>> > + struct clk *clk;
>> > + struct clock_event_device ced;
>> > + struct irqaction act;
>> > +};
>> > +
>> > +static void __iomem *sched_clock_reg;
>> > +
>> > +static inline struct epit_timer *to_epit_timer(struct clock_event_device *ced)
>> > +{
>> > + return container_of(ced, struct epit_timer, ced);
>> > +}
>> > +
>> > +static inline void epit_irq_disable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static inline void epit_irq_enable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static void epit_irq_acknowledge(struct epit_timer *epittm)
>> > +{
>> > + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
>> > +}
>> > +
>> > +static u64 notrace epit_read_sched_clock(void)
>> > +{
>> > + return ~readl_relaxed(sched_clock_reg);
>> > +}
>> > +
>> > +static int epit_set_next_event(unsigned long cycles,
>> > + struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long tcmp;
>> > +
>> > + tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
>> > + writel_relaxed(tcmp, epittm->base + EPITCMPR);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +/* Left event sources disabled, no more interrupts appear */
>> > +static int epit_shutdown(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > + * The timer interrupt generation is disabled at least
>> > + * for enough time to call epit_set_next_event()
>> > + */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt */
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int epit_set_oneshot(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > + * The timer interrupt generation is disabled at least
>> > + * for enough time to call epit_set_next_event()
>> > + */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt, only while switching mode */
>> > + if (!clockevent_state_oneshot(ced))
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + /*
>> > + * Do not put overhead of interrupt enable/disable into
>> > + * epit_set_next_event(), the core has about 4 minutes
>> > + * to call epit_set_next_event() or shutdown clock after
>> > + * mode switching
>> > + */
>> > + epit_irq_enable(epittm);
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
>> > +{
>> > + struct clock_event_device *ced = dev_id;
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > +
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + ced->event_handler(ced);
>> > +
>> > + return IRQ_HANDLED;
>> > +}
>> > +
>> > +static int __init epit_clocksource_init(struct epit_timer *epittm)
>> > +{
>> > + unsigned int c = clk_get_rate(epittm->clk);
>> > +
>> > + sched_clock_reg = epittm->base + EPITCNR;
>> > + sched_clock_register(epit_read_sched_clock, 32, c);
>> > +
>> > + return clocksource_mmio_init(epittm->base + EPITCNR, "epit", c, 200, 32,
>> > + clocksource_mmio_readl_down);
>> > +}
>> > +
>> > +static int __init epit_clockevent_init(struct epit_timer *epittm)
>> > +{
>> > + struct clock_event_device *ced = &epittm->ced;
>> > + struct irqaction *act = &epittm->act;
>> > +
>> > + ced->name = "epit";
>> > + ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
>> > + ced->set_state_shutdown = epit_shutdown;
>> > + ced->tick_resume = epit_shutdown;
>> > + ced->set_state_oneshot = epit_set_oneshot;
>> > + ced->set_next_event = epit_set_next_event;
>> > + ced->rating = 200;
>> > + ced->cpumask = cpumask_of(0);
>> > + ced->irq = epittm->irq;
>> > + clockevents_config_and_register(ced, clk_get_rate(epittm->clk),
>> > + 0xff, 0xfffffffe);
>> > +
>> > + act->name = "i.MX EPIT Timer Tick",
>> > + act->flags = IRQF_TIMER | IRQF_IRQPOLL;
>> > + act->handler = epit_timer_interrupt;
>> > + act->dev_id = ced;
>> > +
>> > + /* Make irqs happen */
>> > + return setup_irq(epittm->irq, act);
>> > +}
>> > +
>> > +static int __init epit_timer_init(struct device_node *np)
>> > +{
>> > + struct epit_timer *epittm;
>> > + int ret;
>> > +
>> > + epittm = kzalloc(sizeof(*epittm), GFP_KERNEL);
>> > + if (!epittm)
>> > + return -ENOMEM;
>> > +
>> > + epittm->base = of_iomap(np, 0);
>> > + if (!epittm->base) {
>> > + ret = -ENXIO;
>> > + goto out_kfree;
>> > + }
>> > +
>> > + epittm->irq = irq_of_parse_and_map(np, 0);
>> > + if (!epittm->irq) {
>> > + ret = -EINVAL;
>> > + goto out_iounmap;
>> > + }
>> > +
>> > + /* Get EPIT clock */
>> > + epittm->clk = of_clk_get(np, 0);
>> > + if (IS_ERR(epittm->clk)) {
>> > + pr_err("i.MX EPIT: unable to get clk\n");
>> > + ret = PTR_ERR(epittm->clk);
>> > + goto out_iounmap;
>> > + }
>>
>> There is something off with indent here.
> Thanks for pointing out that, I will fix it.
>
>>
>> There is a helper library in drivers/clocksource/timer-of.c which might
>> be useful for this driver.
> Indeed, but will require a bit of rewrite.
That is fine for me ;-) Afaict, if should be simplify code a quite a
bit, and doable with reasonable amount of work.
It is typically the expectation for new drivers to make use of such
libraries. In the end it is up to the clocksource maintainer(s) to
decide whether they make it as an requirement for this driver.
--
Stefan
>
> Clement
>
>>
>> --
>> Stefan
>>
>> > +
>> > + ret = clk_prepare_enable(epittm->clk);
>> > + if (ret) {
>> > + pr_err("i.MX EPIT: unable to prepare+enable clk\n");
>> > + goto out_iounmap;
>> > + }
>> > +
>> > + /* Initialise to a known state (all timers off, and timing reset) */
>> > + writel_relaxed(0x0, epittm->base + EPITCR);
>> > + writel_relaxed(0xffffffff, epittm->base + EPITLR);
>> > + writel_relaxed(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
>> > + epittm->base + EPITCR);
>> > +
>> > + ret = epit_clocksource_init(epittm);
>> > + if (ret) {
>> > + pr_err("i.MX EPIT: failed to init clocksource\n");
>> > + goto out_clk_disable;
>> > + }
>> > +
>> > + ret = epit_clockevent_init(epittm);
>> > + if (ret) {
>> > + pr_err("i.MX EPIT: failed to init clockevent\n");
>> > + goto out_clk_disable;
>> > + }
>> > +
>> > + return 0;
>> > +
>> > +out_clk_disable:
>> > + clk_disable_unprepare(epittm->clk);
>> > +out_iounmap:
>> > + iounmap(epittm->base);
>> > +out_kfree:
>> > + kfree(epittm);
>> > +
>> > + return ret;
>> > +}
>> > +TIMER_OF_DECLARE(epit_timer, "fsl,imx31-epit", epit_timer_init);
^ permalink raw reply
* [PATCH V3] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Geert Uytterhoeven @ 2018-06-11 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fa4f843b-ae9d-fac2-77e2-b3ac1116f916@gmail.com>
Hi Marek,
On Mon, Jun 11, 2018 at 2:15 PM Marek Vasut <marek.vasut@gmail.com> wrote:
> On 06/11/2018 11:56 AM, Geert Uytterhoeven wrote:
> > On Mon, Jun 4, 2018 at 7:59 PM Marek Vasut <marek.vasut@gmail.com> wrote:
> >> Rather than hard-coding the quirk topology, which stopped scaling,
> >> parse the information from DT. The code looks for all compatible
> >> PMICs -- da9036 and da9210 -- and checks if their IRQ line is tied
> >
> > da9063
> >
> >> to the same pin. If so, the code sends a matching sequence to the
> >> PMIC to deassert the IRQ.
> >> @@ -122,7 +143,13 @@ static struct notifier_block regulator_quirk_nb = {
> >>
> >> static int __init rcar_gen2_regulator_quirk(void)
> >> {
> >> - u32 mon;
> >> + struct device_node *np;
> >> + const struct of_device_id *id;
> >> + struct regulator_quirk *quirk;
> >> + struct regulator_quirk *pos;
> >> + struct of_phandle_args *argsa, *argsb;
> >> + u32 mon, addr;
> >> + int ret;
> >
> > Some people prefer "Reverse Christmas Tree Ordering", i.e. longest line first.
> >
> >>
> >> if (!of_machine_is_compatible("renesas,koelsch") &&
> >> !of_machine_is_compatible("renesas,lager") &&
> >> @@ -130,6 +157,45 @@ static int __init rcar_gen2_regulator_quirk(void)
> >> !of_machine_is_compatible("renesas,gose"))
> >> return -ENODEV;
> >
> > I think the board checks above can be removed. That will auto-enable the
> > fix on e.g. Porter (once its regulators have ended up in DTS, of course).
>
> Removing the check would also enable it on boards where we don't want
> this enabled, so I'd prefer to keep the check to avoid strange surprises.
Like, Porter? ;-)
> >> + ret = of_property_read_u32(np, "reg", &addr);
> >> + if (ret)
> >> + return ret;
> >
> > I think it's safer to skip this entry and continue, after calling
> > kfree(quirk), of course.
> >
> >> +
> >> + quirk->id = id;
> >> + quirk->i2c_msg.addr = addr;
> >> + quirk->shared = false;
> >> +
> >> + ret = of_irq_parse_one(np, 0, &quirk->irq_args);
> >> + if (ret)
> >> + return ret;
> >
> > kfree(quirk) and continue...
>
> I wonder if it shouldn't rather free the entire list and abort ?
"Be strict when sending, be liberal when receiving."
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] media: stm32-dcmi: add power saving support
From: kbuild test robot @ 2018-06-11 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528709597-7734-1-git-send-email-hugues.fruchet@st.com>
Hi Hugues,
I love your patch! Yet something to improve:
[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.17 next-20180608]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Hugues-Fruchet/media-stm32-dcmi-add-power-saving-support/20180611-174016
base: git://linuxtv.org/media_tree.git master
config: sparc64-allyesconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=sparc64
All errors (new ones prefixed by >>):
drivers/media//platform/stm32/stm32-dcmi.c: In function 'dcmi_suspend':
drivers/media//platform/stm32/stm32-dcmi.c:1886:2: error: implicit declaration of function 'pinctrl_pm_select_sleep_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_sleep_state(dev);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media//platform/stm32/stm32-dcmi.c: In function 'dcmi_resume':
>> drivers/media//platform/stm32/stm32-dcmi.c:1894:2: error: implicit declaration of function 'pinctrl_pm_select_default_state'; did you mean 'irq_set_default_host'? [-Werror=implicit-function-declaration]
pinctrl_pm_select_default_state(dev);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
irq_set_default_host
cc1: some warnings being treated as errors
vim +1894 drivers/media//platform/stm32/stm32-dcmi.c
1879
1880 static __maybe_unused int dcmi_suspend(struct device *dev)
1881 {
1882 /* disable clock */
1883 pm_runtime_force_suspend(dev);
1884
1885 /* change pinctrl state */
> 1886 pinctrl_pm_select_sleep_state(dev);
1887
1888 return 0;
1889 }
1890
1891 static __maybe_unused int dcmi_resume(struct device *dev)
1892 {
1893 /* restore pinctl default state */
> 1894 pinctrl_pm_select_default_state(dev);
1895
1896 /* clock enable */
1897 pm_runtime_force_resume(dev);
1898
1899 return 0;
1900 }
1901
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v3] irqchip/gic-v3-its: fix ITS queue timeout
From: Marc Zyngier @ 2018-06-11 13:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528719909-16572-1-git-send-email-yangyingliang@huawei.com>
On 11/06/18 13:25, Yang Yingliang wrote:
> On a NUMA system, if an ITS is local to an offline
> node, the ITS driver may pick an offline CPU to bind
> the LPI. In this case, we need to pick an online CPU.
> But on some systems, binding LPI to non-local node
> CPU will cause deadlock. In this case, we don't
> bind the LPI to any online CPU and return an error code.
>
> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 5416f2b..137c433 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -2309,7 +2309,13 @@ static int its_irq_domain_activate(struct irq_domain *domain,
> cpu_mask = cpumask_of_node(its_dev->its->numa_node);
>
> /* Bind the LPI to the first possible CPU */
> - cpu = cpumask_first(cpu_mask);
> + cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
> + if (cpu >= nr_cpu_ids) {
> + if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
> + return -EINVAL;
> +
> + cpu = cpumask_first(cpu_online_mask);
> + }
> its_dev->event_map.col_map[event] = cpu;
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>
>
Queued as a fix for 4.18 with a slightly updated change-log and a cc to
stable.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH V3] ARM: shmobile: Rework the PMIC IRQ line quirk
From: Marek Vasut @ 2018-06-11 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXw146fwm0tHS7CBAofDAgRgDD2tNqgEJwzx0Jm1xKCyw@mail.gmail.com>
On 06/11/2018 03:03 PM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi,
> On Mon, Jun 11, 2018 at 2:15 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>> On 06/11/2018 11:56 AM, Geert Uytterhoeven wrote:
>>> On Mon, Jun 4, 2018 at 7:59 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>>>> Rather than hard-coding the quirk topology, which stopped scaling,
>>>> parse the information from DT. The code looks for all compatible
>>>> PMICs -- da9036 and da9210 -- and checks if their IRQ line is tied
>>>
>>> da9063
>>>
>>>> to the same pin. If so, the code sends a matching sequence to the
>>>> PMIC to deassert the IRQ.
>
>>>> @@ -122,7 +143,13 @@ static struct notifier_block regulator_quirk_nb = {
>>>>
>>>> static int __init rcar_gen2_regulator_quirk(void)
>>>> {
>>>> - u32 mon;
>>>> + struct device_node *np;
>>>> + const struct of_device_id *id;
>>>> + struct regulator_quirk *quirk;
>>>> + struct regulator_quirk *pos;
>>>> + struct of_phandle_args *argsa, *argsb;
>>>> + u32 mon, addr;
>>>> + int ret;
>>>
>>> Some people prefer "Reverse Christmas Tree Ordering", i.e. longest line first.
>>>
>>>>
>>>> if (!of_machine_is_compatible("renesas,koelsch") &&
>>>> !of_machine_is_compatible("renesas,lager") &&
>>>> @@ -130,6 +157,45 @@ static int __init rcar_gen2_regulator_quirk(void)
>>>> !of_machine_is_compatible("renesas,gose"))
>>>> return -ENODEV;
>>>
>>> I think the board checks above can be removed. That will auto-enable the
>>> fix on e.g. Porter (once its regulators have ended up in DTS, of course).
>>
>> Removing the check would also enable it on boards where we don't want
>> this enabled, so I'd prefer to keep the check to avoid strange surprises.
>
> Like, Porter? ;-)
I'm adding Porter in a separate patch.
>>>> + ret = of_property_read_u32(np, "reg", &addr);
>>>> + if (ret)
>>>> + return ret;
>>>
>>> I think it's safer to skip this entry and continue, after calling
>>> kfree(quirk), of course.
>>>
>>>> +
>>>> + quirk->id = id;
>>>> + quirk->i2c_msg.addr = addr;
>>>> + quirk->shared = false;
>>>> +
>>>> + ret = of_irq_parse_one(np, 0, &quirk->irq_args);
>>>> + if (ret)
>>>> + return ret;
>>>
>>> kfree(quirk) and continue...
>>
>> I wonder if it shouldn't rather free the entire list and abort ?
>
> "Be strict when sending, be liberal when receiving."
Meaning ? I think "the language barrier is protecting me" (TM)
--
Best regards,
Marek Vasut
^ permalink raw reply
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