* [PATCH 0/5] RFC: Mezzanine handling for 96boards
From: Arnd Bergmann @ 2018-06-18 14:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu-gAkfRsEUOc=iyxi6Twvg9cbvWNqNHRS2HzUDZg8xUhg@mail.gmail.com>
On Mon, Jun 18, 2018 at 3:22 PM, Ard Biesheuvel
<ard.biesheuvel@linaro.org> wrote:
> On 18 June 2018 at 14:21, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Mon, Jun 18, 2018 at 9:45 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> Also, given that we can (and do) already describe topologies involving
> mezzanines by ignoring the connector altogether (which is not entirely
> unreasonable given the fact that we [as Linaro/96boards] dropped the
> ball on this one and did not mandate discoverability for mezzanines).
> So ideally, DTs can be expressed such that older kernels can still use
> those peripherals.
Not sure. Modeling the connector as a device with its own driver does
seem like a significant advantage, which to me weighs more than backward
compatibility with old kernels. We can clearly always describe the devices
behind the connector individually and ignore the connector on old kernels
and we should still allow running DT files that work with the old kernels
on new kernels, but I don't see running new DT files on old kernels as
essential in this case. Many platforms don't actually care about that case
at all today (but some do of course).
Arnd
^ permalink raw reply
* [PATCH v5 5/5] ARM: dts: at91: sama5d2 Xplained: add pin muxing for I2S
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618141239.10892-1-codrin.ciubotariu@microchip.com>
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
This patch sets the pin muxing for the I2S controllers
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[codrin.ciubotariu at microchip.com: added pin muxing for the second
controller]
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
Changes in v5:
- Previous name was:
[PATCH v4 7/7] ARM: dts: at91: sama5d2 Xplained: add pin muxing for I2S
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 28 +++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index e4bbb7e0f793..03917312dec1 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -281,6 +281,11 @@
status = "okay";
};
+ i2s0: i2s at f8050000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s0_default>;
+ };
+
can0: can at f8054000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
@@ -424,6 +429,24 @@
bias-disable;
};
+ pinctrl_i2s0_default: i2s0_default {
+ pinmux = <PIN_PC1__I2SC0_CK>,
+ <PIN_PC2__I2SC0_MCK>,
+ <PIN_PC3__I2SC0_WS>,
+ <PIN_PC4__I2SC0_DI0>,
+ <PIN_PC5__I2SC0_DO0>;
+ bias-disable;
+ };
+
+ pinctrl_i2s1_default: i2s1_default {
+ pinmux = <PIN_PA15__I2SC1_CK>,
+ <PIN_PA14__I2SC1_MCK>,
+ <PIN_PA16__I2SC1_WS>,
+ <PIN_PA17__I2SC1_DI0>,
+ <PIN_PA18__I2SC1_DO0>;
+ bias-disable;
+ };
+
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PB9__GPIO>;
bias-pull-up;
@@ -546,6 +569,11 @@
status = "okay";
};
+ i2s1: i2s at fc04c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s1_default>;
+ };
+
can1: can at fc050000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
--
2.17.1
^ permalink raw reply related
* [PATCH v5 4/5] ARM: dts: at91: sama5d2: add nodes for I2S controllers
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618141239.10892-1-codrin.ciubotariu@microchip.com>
From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
This patch adds DT nodes for I2S0 and I2S1. It also adds an alias for
each I2S node.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[codrin.ciubotariu at microchip.com: added phandle to new mux clock]
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
The bindings for the I2S node are applied to broonie/sound.git .
Changes in v5:
- the previous name was:
[PATCH v4 6/7] ARM: dts: at91: sama5d2: add nodes for I2S controllers
arch/arm/boot/dts/sama5d2.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index eeb6afa1cda7..eca73ce40bc5 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -58,6 +58,8 @@
serial1 = &uart3;
tcb0 = &tcb0;
tcb1 = &tcb1;
+ i2s0 = &i2s0;
+ i2s1 = &i2s1;
};
cpus {
@@ -1313,6 +1315,22 @@
clocks = <&clk32k>;
};
+ i2s0: i2s at f8050000 {
+ compatible = "atmel,sama5d2-i2s";
+ reg = <0xf8050000 0x100>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(31))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>;
+ dma-names = "tx", "rx";
+ clocks = <&i2s0_clk>, <&i2s0_gclk>, <&audio_pll_pmc>, <&i2s0muxck>;
+ clock-names = "pclk", "gclk", "aclk", "muxclk";
+ status = "disabled";
+ };
+
can0: can at f8054000 {
compatible = "bosch,m_can";
reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
@@ -1506,6 +1524,22 @@
status = "disabled";
};
+ i2s1: i2s at fc04c000 {
+ compatible = "atmel,sama5d2-i2s";
+ reg = <0xfc04c000 0x100>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(33))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(34))>;
+ dma-names = "tx", "rx";
+ clocks = <&i2s1_clk>, <&i2s1_gclk>, <&audio_pll_pmc>, <&i2s1muxck>;
+ clock-names = "pclk", "gclk", "aclk", "muxclk";
+ status = "disabled";
+ };
+
can1: can at fc050000 {
compatible = "bosch,m_can";
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
--
2.17.1
^ permalink raw reply related
* [PATCH v5 3/5] ARM: dts: at91: sama5d2: add I2S clock muxing nodes
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618141239.10892-1-codrin.ciubotariu@microchip.com>
This patch adds two clock muxes for the two I2S
buses present on sama5d2 platforms.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 61f68e5c48e9..eeb6afa1cda7 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -992,6 +992,24 @@
atmel,clk-output-range = <0 100000000>;
};
};
+
+ i2s_clkmux {
+ compatible = "atmel,sama5d2-clk-i2s-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2s0muxck: i2s0_muxclk {
+ clocks = <&i2s0_clk>, <&i2s0_gclk>;
+ #clock-cells = <0>;
+ reg = <0>;
+ };
+
+ i2s1muxck: i2s1_muxclk {
+ clocks = <&i2s1_clk>, <&i2s1_gclk>;
+ #clock-cells = <0>;
+ reg = <1>;
+ };
+ };
};
qspi0: spi at f0020000 {
--
2.17.1
^ permalink raw reply related
* [PATCH v5 2/5] clk: at91: add I2S clock mux driver
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618141239.10892-1-codrin.ciubotariu@microchip.com>
This driver is a simple muxing driver that controls the
I2S's clock input by using syscon/regmap to change the parent.
The available inputs can be peripheral clock and generated clock.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
Changes in v5:
- removed CLK_IGNORE_UNUSED flag;
- fixed typo in patch description;
- fixed letter case in patch description;
- reduced size of 'bus_id' member of struct clk_i2s_mux from 32b to 8b,
and all the other changes that come with it;
- made 'clk_i2s_mux_ops' static;
arch/arm/mach-at91/Kconfig | 4 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-i2s-mux.c | 116 +++++++++++++++++++++++++++++++++
3 files changed, 121 insertions(+)
create mode 100644 drivers/clk/at91/clk-i2s-mux.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1254bf9d91b4..903f23c309df 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -27,6 +27,7 @@ config SOC_SAMA5D2
select HAVE_AT91_H32MX
select HAVE_AT91_GENERATED_CLK
select HAVE_AT91_AUDIO_PLL
+ select HAVE_AT91_I2S_MUX_CLK
select PINCTRL_AT91PIO4
help
Select this if ou are using one of Microchip's SAMA5D2 family SoC.
@@ -129,6 +130,9 @@ config HAVE_AT91_GENERATED_CLK
config HAVE_AT91_AUDIO_PLL
bool
+config HAVE_AT91_I2S_MUX_CLK
+ bool
+
config SOC_SAM_V4_V5
bool
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 082596f37c1d..facc169ebb68 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
+obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
new file mode 100644
index 000000000000..ab834c4a605b
--- /dev/null
+++ b/drivers/clk/at91/clk-i2s-mux.c
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Microchip Technology Inc,
+ * Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
+ *
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <soc/at91/atmel-sfr.h>
+
+#define I2S_BUS_NR 2
+
+struct clk_i2s_mux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ u8 bus_id;
+};
+
+#define to_clk_i2s_mux(hw) container_of(hw, struct clk_i2s_mux, hw)
+
+static u8 clk_i2s_mux_get_parent(struct clk_hw *hw)
+{
+ struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
+ u32 val;
+
+ regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val);
+
+ return (val & BIT(mux->bus_id)) >> mux->bus_id;
+}
+
+static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
+
+ return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL,
+ BIT(mux->bus_id), index << mux->bus_id);
+}
+
+static const struct clk_ops clk_i2s_mux_ops = {
+ .get_parent = clk_i2s_mux_get_parent,
+ .set_parent = clk_i2s_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+};
+
+static struct clk_hw * __init
+at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
+ const char * const *parent_names,
+ unsigned int num_parents, u8 bus_id)
+{
+ struct clk_init_data init = {};
+ struct clk_i2s_mux *i2s_ck;
+ int ret;
+
+ i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL);
+ if (!i2s_ck)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_i2s_mux_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ i2s_ck->hw.init = &init;
+ i2s_ck->bus_id = bus_id;
+ i2s_ck->regmap = regmap;
+
+ ret = clk_hw_register(NULL, &i2s_ck->hw);
+ if (ret) {
+ kfree(i2s_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &i2s_ck->hw;
+}
+
+static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
+{
+ struct regmap *regmap_sfr;
+ u8 bus_id;
+ const char *parent_names[2];
+ struct device_node *i2s_mux_np;
+ struct clk_hw *hw;
+ int ret;
+
+ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
+ if (IS_ERR(regmap_sfr))
+ return;
+
+ for_each_child_of_node(np, i2s_mux_np) {
+ if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
+ continue;
+
+ if (bus_id > I2S_BUS_NR)
+ continue;
+
+ ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
+ if (ret != 2)
+ continue;
+
+ hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
+ parent_names, 2, bus_id);
+ if (IS_ERR(hw))
+ continue;
+
+ of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
+ }
+}
+
+CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
+ of_sama5d2_clk_i2s_mux_setup);
--
2.17.1
^ permalink raw reply related
* [PATCH v5 1/5] dt-bindings: clk: at91: add an I2S mux clock
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618141239.10892-1-codrin.ciubotariu@microchip.com>
The I2S mux clock can be used to select the I2S input clock. The
available parents are the peripheral and the generated clocks.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
Changes in v5:
- specified clock's parent;
- added a newline before adding the clock's compatible string;
.../devicetree/bindings/clock/at91-clock.txt | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index 51c259a92d02..d0adbf5ae144 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -91,6 +91,9 @@ Required properties:
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
and can be used by peripheral clock or generic clock
+ "atmel,sama5d2-clk-i2s-mux" (under pmc node):
+ at91 I2S clock source selection
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -507,3 +510,35 @@ For example:
atmel,clk-output-range = <0 83000000>;
};
};
+
+Required properties for I2S mux clocks:
+- #size-cells : shall be 0 (reg is used to encode I2S bus id).
+- #address-cells : shall be 1 (reg is used to encode I2S bus id).
+- name: device tree node describing a specific mux clock.
+ * #clock-cells : from common clock binding; shall be set to 0.
+ * clocks : shall be the mux clock parent phandles; shall be 2 phandles:
+ peripheral and generated clock; the first phandle shall belong to the
+ peripheral clock and the second one shall belong to the generated
+ clock; "clock-indices" property can be user to specify
+ the correct order.
+ * reg: I2S bus id of the corresponding mux clock.
+ e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
+
+For example:
+ i2s_clkmux {
+ compatible = "atmel,sama5d2-clk-i2s-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2s0muxck: i2s0_muxclk {
+ clocks = <&i2s0_clk>, <&i2s0_gclk>;
+ #clock-cells = <0>;
+ reg = <0>;
+ };
+
+ i2s1muxck: i2s1_muxclk {
+ clocks = <&i2s1_clk>, <&i2s1_gclk>;
+ #clock-cells = <0>;
+ reg = <1>;
+ };
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v5 0/5] ASoC: add driver for Atmel I2S controller
From: Codrin Ciubotariu @ 2018-06-18 14:12 UTC (permalink / raw)
To: linux-arm-kernel
This is a rework of Cyrille's patches named:
[PATCH v3 0/2] ASoC: add driver for Atmel I2S controller
https://lkml.org/lkml/2015/9/29/454
This is the version 5 of the series, and addresses the received feedback
on the mailing lists.
This series applies on top of clk-next branch of clk/linux.git.
Based on received feedback, I created a mux clock driver to select the I2S
clock source, that also includes proper devicetree bindings and nodes.
Also, I added the I2S nodes in sama5d2's devicetree, with the missing
pin muxing for the second I2S controller.
Alexandre Belloni plans to change the at91 fine grained clock nodes and
he recommended to leave the bindings for this clock driver in the same
(wrong) manner, so he could fix them all at once.
This series of patches adds support to the new Atmel I2S controller
embedded on sama5d2 SoCs.
ChangeLog
v4 -> v5
- removed patches:
[PATCH v4 4/7] ASoC: atmel-i2s: dt-bindings: add DT bindings for I2S controller
[PATCH v4 5/7] ASoC: atmel-i2s: add driver for the new Atmel I2S controller
from this series since they were applied to the asoc tree at:
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
- addressed comments received on the mux clock;
v3 -> v4
- as suggested by Rob Herring:
- added a clock mux driver for I2S's clock control bit;
- more precise description of I2S's devicetree bindings;
- removed SoC and internal detalls from bindings;
- addressed comments from Mark Brown;
- added devicetree nodes and pin muxing for I2S;
v2 -> v3
- fix the coding style, add some more comments and add a section dedicated
to sama5d2 SoCs in the DT binding documentation as suggested by Mark
Brown.
v1 -> v2
- initialize dev->dev before calling dev->caps->mck_init()
Codrin Ciubotariu (3):
dt-bindings: clk: at91: add an I2S mux clock
clk: at91: add I2S clock mux driver
ARM: dts: at91: sama5d2: add I2S clock muxing nodes
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2: add nodes for I2S controllers
ARM: dts: at91: sama5d2 Xplained: add pin muxing for I2S
.../devicetree/bindings/clock/at91-clock.txt | 35 ++++++
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 28 +++++
arch/arm/boot/dts/sama5d2.dtsi | 52 ++++++++
arch/arm/mach-at91/Kconfig | 4 +
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-i2s-mux.c | 116 ++++++++++++++++++
6 files changed, 236 insertions(+)
create mode 100644 drivers/clk/at91/clk-i2s-mux.c
--
2.17.1
^ permalink raw reply
* [PATCH] regulator: core: Pass max_uV value to regulator_set_voltage_rdev
From: Maciej Purski @ 2018-06-18 14:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180615112916.GK112168@atomide.com>
If the regulator is not coupled, balance_voltage() should preserve
its desired max uV, instead of setting the exact value like in
coupled regulators case.
Remove debugs, which are not necessary for now.
Signed-off-by: Maciej Purski <m.purski@samsung.com>
---
drivers/regulator/core.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 266f4eb..9894f4e 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -2245,7 +2245,6 @@ static int _regulator_enable(struct regulator_dev *rdev)
{
int ret;
- rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
lockdep_assert_held_once(&rdev->mutex);
/* check voltage and requested load before enabling */
@@ -2294,7 +2293,6 @@ int regulator_enable(struct regulator *regulator)
struct regulator_dev *rdev = regulator->rdev;
int ret = 0;
- rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
if (rdev->coupling_desc.n_resolved != rdev->coupling_desc.n_coupled) {
rdev_err(rdev, "not all coupled regulators registered\n");
return -EPERM;
@@ -2319,7 +2317,6 @@ int regulator_enable(struct regulator *regulator)
if (ret != 0 && rdev->supply)
regulator_disable(rdev->supply);
- rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_enable);
@@ -2418,7 +2415,6 @@ int regulator_disable(struct regulator *regulator)
struct regulator_dev *rdev = regulator->rdev;
int ret = 0;
- rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
if (regulator->always_on)
return 0;
@@ -2431,7 +2427,6 @@ int regulator_disable(struct regulator *regulator)
if (ret == 0 && rdev->supply)
regulator_disable(rdev->supply);
- rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_disable);
@@ -3112,6 +3107,8 @@ static int regulator_set_voltage_rdev(struct regulator_dev *rdev, int min_uV,
int supply_change_uV = 0;
int ret;
+ rdev_err(rdev, "%s: %d\n", __func__, __LINE__);
+
if (rdev->supply &&
regulator_ops_is_valid(rdev->supply->rdev,
REGULATOR_CHANGE_VOLTAGE) &&
@@ -3175,7 +3172,8 @@ static int regulator_set_voltage_rdev(struct regulator_dev *rdev, int min_uV,
return ret;
}
-static int regulator_get_optimal_voltage(struct regulator_dev *rdev)
+static int
+regulator_get_optimal_voltage(struct regulator_dev *rdev, int *max_uV)
{
struct coupling_desc *c_desc = &rdev->coupling_desc;
struct regulator_dev **c_rdevs = c_desc->coupled_rdevs;
@@ -3200,6 +3198,7 @@ static int regulator_get_optimal_voltage(struct regulator_dev *rdev)
*/
if (n_coupled == 1) {
ret = desired_min_uV;
+ *max_uV = desired_max_uV;
goto out;
}
@@ -3274,6 +3273,7 @@ static int regulator_get_optimal_voltage(struct regulator_dev *rdev)
goto out;
}
ret = possible_uV;
+ *max_uV = ret;
out:
return ret;
@@ -3303,6 +3303,8 @@ static int regulator_balance_voltage(struct regulator_dev *rdev,
* if there isn't any possible change.
*/
while (1) {
+ int max_uV;
+
best_delta = 0;
best_uV = 0;
best_rdev = NULL;
@@ -3318,9 +3320,9 @@ static int regulator_balance_voltage(struct regulator_dev *rdev,
* max_spread constraint in order to balance
* the coupled voltages.
*/
- int optimal_uV, current_uV;
+ int optimal_uV, current_uV;;
- optimal_uV = regulator_get_optimal_voltage(c_rdevs[i]);
+ optimal_uV = regulator_get_optimal_voltage(c_rdevs[i], &max_uV);
if (optimal_uV < 0) {
ret = optimal_uV;
goto out;
@@ -3337,6 +3339,10 @@ static int regulator_balance_voltage(struct regulator_dev *rdev,
best_rdev = c_rdevs[i];
best_uV = optimal_uV;
}
+
+ rdev_err(rdev,
+ "optimal uV: %d current uV: %d, max uV: %d\n",
+ optimal_uV, current_uV, max_uV);
}
/* Nothing to change, return successfully */
@@ -3346,7 +3352,7 @@ static int regulator_balance_voltage(struct regulator_dev *rdev,
}
ret = regulator_set_voltage_rdev(best_rdev, best_uV,
- best_uV, state);
+ max_uV, state);
if (ret < 0)
goto out;
@@ -3378,7 +3384,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
{
int ret = 0;
- rdev_err(regulator->rdev, "%s: %d\n", __func__, __LINE__);
+ dev_err(regulator->dev, "%s: %d\n", __func__, __LINE__);
regulator_lock_dependent(regulator->rdev);
ret = regulator_set_voltage_unlocked(regulator, min_uV, max_uV,
--
2.7.4
^ permalink raw reply related
* [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
From: Miquel Raynal @ 2018-06-18 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180618103908.17a04679@bbrezillon>
Hi Boris,
On Mon, 18 Jun 2018 10:39:08 +0200, Boris Brezillon
<boris.brezillon@bootlin.com> wrote:
> On Thu, 29 Mar 2018 15:10:54 +0200
> Peter Rosin <peda@axentia.se> wrote:
>
> > On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
> > flash accesses have a tendency to cause display disturbances. Add a
> > module param to disable DMA from the NAND controller, since that fixes
> > the display problem for me.
> >
> > Signed-off-by: Peter Rosin <peda@axentia.se>
>
> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
>
> Miquel, can you queue this one to nand/next.
Yes of course.
I'll just change the subject to "mtd: rawnand: atmel:".
Thanks,
Miqu?l
^ permalink raw reply
* [PATCH 3/3] ARM: mx5: Set the DBGEN bit in ARM_GPC register
From: Fabio Estevam @ 2018-06-18 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529329939-14117-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
On i.MX51/i.MX53 it is necessery to set the DBGEN bit in
ARM_GPC register in order to turn on the debug clocks.
The DBGEN bit of ARM_GPC register has the following description
in the i.MX53 Reference Manual:
"This allows the user to manually activate clocks within the debug
system. This register bit directly controls the platform's dbgen_out
output signal which connects to the DAP_SYS to enable all debug clocks.
Once enabled, the clocks cannot be disabled except by asserting the
disable_trace input of the DAP_SYS."
Based on a previous patch from Sebastian Reichel.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpu-imx5.c | 38 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-imx/mach-imx53.c | 2 ++
3 files changed, 41 insertions(+)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c8d68e9..db78329 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -62,6 +62,7 @@ void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
void imx25_pm_init(void);
void imx27_pm_init(void);
+void imx5_pmu_init(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 4f2d1c7..6c5a055 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -117,3 +117,41 @@ int mx53_revision(void)
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx53_revision);
+
+#define ARM_GPC 0x4
+#define DBGEN BIT(16)
+
+/*
+ * This enables the DBGEN bit in ARM_GPC register, which is
+ * required for accessing some performance counter features.
+ * Technically it is only required while perf is used, but to
+ * keep the source code simple we just enable it all the time
+ * when the kernel configuration allows using the feature.
+ */
+void imx5_pmu_init(void)
+{
+ void __iomem *arm_plat_base;
+ struct device_node *np;
+ u32 gpc;
+
+ if (!IS_ENABLED(CONFIG_ARM_PMU))
+ return;
+
+ np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
+ if (!np)
+ return;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx51-arm-plat");
+ if (!np)
+ return;
+
+ arm_plat_base = of_iomap(np, 0);
+ if (!arm_plat_base) {
+ pr_warn("Unable to map ARM platform registers\n");
+ return;
+ }
+
+ gpc = readl_relaxed(arm_plat_base + ARM_GPC);
+ gpc |= DBGEN;
+ writel_relaxed(gpc, arm_plat_base + ARM_GPC);
+}
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 07c2e8d..15fba89 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -32,6 +32,8 @@ static void __init imx53_dt_init(void)
{
imx_src_init();
+ imx5_pmu_init();
+
imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
}
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: imx53: Add a label for the PMU node
From: Fabio Estevam @ 2018-06-18 13:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529329939-14117-1-git-send-email-festevam@gmail.com>
From: Fabio Estevam <fabio.estevam@nxp.com>
Add a label for the PMU node so that the board dts may be able to
pass the 'secure-reg-access' property like this:
&pmu {
secure-reg-access;
};
This also makes it consistent with the PMU node in imx6qdl.dtsi
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx53.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a70fbf4..263bd39f 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -113,7 +113,7 @@
};
};
- pmu {
+ pmu: pmu {
compatible = "arm,cortex-a8-pmu";
interrupt-parent = <&tzic>;
interrupts = <77>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] ARM: dts: imx53: Add 'ARM platform' node
From: Fabio Estevam @ 2018-06-18 13:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
As per the i.MX53 Reference Manual add an entry for the
'ARM platform' region in the device tree.
This is needed for accessing the ARM_GPC register to set the
DBGEN bit, so that the debug clocks can be turned on.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx53.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 1a7a7bb..a70fbf4 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -672,6 +672,11 @@
status = "disabled";
};
+ arm_platform: arm-platform at 63fa0000 {
+ compatible = "fsl,imx53-arm-plat", "fsl,imx51-arm-plat";
+ reg = <0x63fa0000 0x28>;
+ };
+
owire: owire at 63fa4000 {
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
reg = <0x63fa4000 0x4000>;
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM: NOMMU: Use instr_sync instead of plain isb in common code
From: Vladimir Murzin @ 2018-06-18 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d32342e7-9ff0-0e26-e9e5-17b6fa2933b5@kernel.org>
Hi Greg,
On 18/06/18 13:42, Greg Ungerer wrote:
> Hi Vladimir,
>
> On 18/06/18 19:48, Vladimir Murzin wrote:
>> Greg reported that commit 3c24121039c9d ("ARM: 8756/1: NOMMU: Postpone
>> MPU activation till __after_proc_init") is causing breakage for the
>> old Versatile platform in no-MMU mode (with out-of-tree patches):
>>
>> ?? AS????? arch/arm/kernel/head-nommu.o
>> arch/arm/kernel/head-nommu.S: Assembler messages:
>> arch/arm/kernel/head-nommu.S:180: Error: selected processor does not support `isb' in ARM mode
>> scripts/Makefile.build:417: recipe for target 'arch/arm/kernel/head-nommu.o' failed
>> make[2]: *** [arch/arm/kernel/head-nommu.o] Error 1
>> Makefile:1034: recipe for target 'arch/arm/kernel' failed
>> make[1]: *** [arch/arm/kernel] Error 2
>>
>> Since the code is common for all NOMMU builds usage of the isb was a
>> bad idea (please, note that isb also used in MPU related code which is
>> fine because MPU has dependency on CPU_V7/CPU_V7M), instead use more
>> robust instr_sync assembler macro.
>>
>> Fixes: 3c24121039c9 ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init")
>> Reported-by: Greg Ungerer <gerg@kernel.org>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>
> Tested and working for me.
>
> Tested-by: Greg Ungerer <gerg@kernel.org>
Great! It is in Russell's tracker now (patch 8775/1)
Cheers
Vladimir
>
> Thanks
> Greg
>
>
>> ---
>> ? arch/arm/kernel/head-nommu.S | 2 +-
>> ? 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
>> index dd546d6..7a9b869 100644
>> --- a/arch/arm/kernel/head-nommu.S
>> +++ b/arch/arm/kernel/head-nommu.S
>> @@ -177,7 +177,7 @@ M_CLASS(streq??? r3, [r12, #PMSAv8_MAIR1])
>> ????? bic??? r0, r0, #CR_I
>> ? #endif
>> ????? mcr??? p15, 0, r0, c1, c0, 0??????? @ write control reg
>> -??? isb
>> +??? instr_sync
>> ? #elif defined (CONFIG_CPU_V7M)
>> ? #ifdef CONFIG_ARM_MPU
>> ????? ldreq??? r3, [r12, MPU_CTRL]
>>
>
^ permalink raw reply
* [PATCH 0/5] RFC: Mezzanine handling for 96boards
From: Ard Biesheuvel @ 2018-06-18 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a2KqoX-squhGc8TBuJ==8xxELsuy-H+c1+C7Fu7Z4OjDA@mail.gmail.com>
On 18 June 2018 at 14:21, Arnd Bergmann <arnd@arndb.de> wrote:
> On Mon, Jun 18, 2018 at 9:45 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
>> This is a proposal for how to handle the non-discoverable
>> 96boards plug-in expansion boards called "mezzanines" in the
>> Linux kernel. It is a working RFC series meant for discussion
>> at the moment.
>>
>> The RFC was done on the brand new Ultra96 board from Xilinx
>> with a Secure96 mezzanine expansion board. The main part
>> is in patch 4, the rest is enabling and examples.
>>
>> The code can be obtained from here:
>> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator.git/log/?h=ultra96
>>
>> You can for example probably augment the DTS file for any
>> upstream-supported 96board and get the Secure96 going with
>> it with minor efforts.
>
> Hi Linus,
>
> Thanks for your work on solving this long-standing problem. I've just
> read through your patches briefly and have a few thoughts:
>
> - I really like the idea of having C code deal with the mezzanine
> connector itself, acting as an intermediate to tie a number of
> boards to a number of add-on cards, this seems much simpler than
> trying to do everything with overlays or one of the other more
> generic mechanisms.
>
> - I don't like the idea of having the bus driver contain a list of possible
> add-ons, this seems to go against our usual driver model. What
> I think we want instead is to make the connector itself a proper
> bus_type, to allow drivers to register against it as loadable modules,
> and devices (maybe limited to one device) being created as probed
> from DT or some other method as you describe.
>
> - You export symbols in the mezzanine_* namespace, which I think
> is a bit too generic and should perhaps contain something related
> to 96boards in its name to make it less ambiguous. I suspect we
> would add a number of further connectors for hats, capes, lures etc,
> which could all be described as mezzanines. One open question
> is how we structure the commonality between the various
> connectors, but we can defer that until we have more than one
> or two of them.
>
Hello all,
We should also consider firmware use of the mezzanines. For instance,
the Secure96 has a RNG which UEFI may want to use so the early boot
code can access is for KASLR. It also has a TPM, which should not be
reset/reinitialized/etc by the OS if we want to make meaningful use of
it.
Also, given that we can (and do) already describe topologies involving
mezzanines by ignoring the connector altogether (which is not entirely
unreasonable given the fact that we [as Linaro/96boards] dropped the
ball on this one and did not mandate discoverability for mezzanines).
So ideally, DTs can be expressed such that older kernels can still use
those peripherals.
^ permalink raw reply
* [PATCH v2 7/7] arm64: topology: re-introduce numa mask check for scheduler MC selection
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
Commit 37c3ec2d810f ("arm64: topology: divorce MC scheduling domain from
core_siblings") selected the smallest of LLC, socket siblings, and NUMA
node siblings to ensure that the sched domain we build for the MC layer
isn't larger than the DIE above it or it's shrunk to the socket or NUMA
node if LLC exist acrosis NUMA node/chiplets.
Commit acd32e52e4e0 ("arm64: topology: Avoid checking numa mask for
scheduler MC selection") reverted the NUMA siblings checks since the
CPU topology masks weren't updated on hotplug at that time.
This patch re-introduces numa mask check as the CPU and NUMA topology
is now updated in hotplug paths. Effectively, this patch does the
partial revert of commit acd32e52e4e0.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/kernel/topology.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index e0db80252cfb..01cdc83b1ec7 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -215,8 +215,13 @@ EXPORT_SYMBOL_GPL(cpu_topology);
const struct cpumask *cpu_coregroup_mask(int cpu)
{
- const cpumask_t *core_mask = &cpu_topology[cpu].core_sibling;
+ const cpumask_t *core_mask = cpumask_of_node(cpu_to_node(cpu));
+ /* Find the smaller of NUMA, core or LLC siblings */
+ if (cpumask_subset(&cpu_topology[cpu].core_sibling, core_mask)) {
+ /* not numa in package, lets use the package siblings */
+ core_mask = &cpu_topology[cpu].core_sibling;
+ }
if (cpu_topology[cpu].llc_id != -1) {
if (cpumask_subset(&cpu_topology[cpu].llc_sibling, core_mask))
core_mask = &cpu_topology[cpu].llc_sibling;
--
2.7.4
^ permalink raw reply related
* [PATCH v2 6/7] arm64: topology: rename llc_siblings to align with other struct members
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
Similar to core_sibling and thread_sibling, it's better to align and
rename llc_siblings to llc_sibling.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/include/asm/topology.h | 2 +-
arch/arm64/kernel/topology.c | 14 +++++++-------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index fb996f454305..dda4b6dba6b4 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -11,7 +11,7 @@ struct cpu_topology {
int llc_id;
cpumask_t thread_sibling;
cpumask_t core_sibling;
- cpumask_t llc_siblings;
+ cpumask_t llc_sibling;
};
extern struct cpu_topology cpu_topology[NR_CPUS];
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index b60d7018e9db..e0db80252cfb 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -218,8 +218,8 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
const cpumask_t *core_mask = &cpu_topology[cpu].core_sibling;
if (cpu_topology[cpu].llc_id != -1) {
- if (cpumask_subset(&cpu_topology[cpu].llc_siblings, core_mask))
- core_mask = &cpu_topology[cpu].llc_siblings;
+ if (cpumask_subset(&cpu_topology[cpu].llc_sibling, core_mask))
+ core_mask = &cpu_topology[cpu].llc_sibling;
}
return core_mask;
@@ -235,8 +235,8 @@ static void update_siblings_masks(unsigned int cpuid)
cpu_topo = &cpu_topology[cpu];
if (cpuid_topo->llc_id == cpu_topo->llc_id) {
- cpumask_set_cpu(cpu, &cpuid_topo->llc_siblings);
- cpumask_set_cpu(cpuid, &cpu_topo->llc_siblings);
+ cpumask_set_cpu(cpu, &cpuid_topo->llc_sibling);
+ cpumask_set_cpu(cpuid, &cpu_topo->llc_sibling);
}
if (cpuid_topo->package_id != cpu_topo->package_id)
@@ -303,8 +303,8 @@ static void clear_cpu_topology(int cpu, bool reset)
cpu_topo->llc_id = -1;
}
- cpumask_clear(&cpu_topo->llc_siblings);
- cpumask_set_cpu(cpu, &cpu_topo->llc_siblings);
+ cpumask_clear(&cpu_topo->llc_sibling);
+ cpumask_set_cpu(cpu, &cpu_topo->llc_sibling);
cpumask_clear(&cpu_topo->core_sibling);
cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
@@ -320,7 +320,7 @@ static void __init reset_cpu_topology(void)
clear_cpu_topology(cpu, true);
}
-#define cpu_llc_shared_mask(cpu) (&cpu_topology[cpu].llc_siblings)
+#define cpu_llc_shared_mask(cpu) (&cpu_topology[cpu].llc_sibling)
void remove_cpu_topology(unsigned int cpu)
{
int sibling;
--
2.7.4
^ permalink raw reply related
* [PATCH v2 5/7] arm64: smp: remove cpu and numa topology information when hotplugging out CPU
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
We already repopulate the information on CPU hotplug-in, so we can safely
remove the CPU topology and NUMA cpumap information during CPU hotplug
out operation. This will help to provide the correct cpumask for
scheduler domains.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/kernel/smp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 49a021e30dfb..63a40ba3cd37 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -279,6 +279,9 @@ int __cpu_disable(void)
if (ret)
return ret;
+ remove_cpu_topology(cpu);
+ numa_remove_cpu(cpu);
+
/*
* Take this CPU offline. Once we clear this, we can't return,
* and we must not schedule until we're ready to give up the cpu.
--
2.7.4
^ permalink raw reply related
* [PATCH v2 4/7] arm64: topology: restrict updating siblings_masks to online cpus only
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
It's incorrect to iterate over all the possible CPUs to update the
sibling masks when any CPU is hotplugged in. In case the topology
siblings masks of the CPU is removed when is it hotplugged out, we
end up updating those masks when one of it's sibling is powered up
again. This will provide inconsistent view.
Further, since the CPU calling update_sibling_masks is yet to be set
online, there's no need to compare itself with each online CPU when
updating the siblings masks.
This patch restricts updation of sibling masks only for CPUs that are
already online. It also the drops the unnecessary cpuid check.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/kernel/topology.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 38b102013708..b60d7018e9db 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -231,7 +231,7 @@ static void update_siblings_masks(unsigned int cpuid)
int cpu;
/* update core and thread sibling masks */
- for_each_possible_cpu(cpu) {
+ for_each_online_cpu(cpu) {
cpu_topo = &cpu_topology[cpu];
if (cpuid_topo->llc_id == cpu_topo->llc_id) {
@@ -243,15 +243,13 @@ static void update_siblings_masks(unsigned int cpuid)
continue;
cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
- if (cpu != cpuid)
- cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
if (cpuid_topo->core_id != cpu_topo->core_id)
continue;
cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
- if (cpu != cpuid)
- cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
}
}
--
2.7.4
^ permalink raw reply related
* [PATCH v2 3/7] arm64: topology: add support to remove cpu topology sibling masks
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
This patch adds support to remove all the CPU topology information using
clear_cpu_topology and also resetting the sibling information on other
sibling CPUs. This will be used in cpu_disable so that all the topology
sibling information is removed on CPU hotplug out.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/include/asm/topology.h | 1 +
arch/arm64/kernel/topology.c | 15 +++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index df48212f767b..fb996f454305 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -23,6 +23,7 @@ extern struct cpu_topology cpu_topology[NR_CPUS];
void init_cpu_topology(void);
void store_cpu_topology(unsigned int cpuid);
+void remove_cpu_topology(unsigned int cpuid);
const struct cpumask *cpu_coregroup_mask(int cpu);
#ifdef CONFIG_NUMA
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index 6ea3ec49d418..38b102013708 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -322,6 +322,21 @@ static void __init reset_cpu_topology(void)
clear_cpu_topology(cpu, true);
}
+#define cpu_llc_shared_mask(cpu) (&cpu_topology[cpu].llc_siblings)
+void remove_cpu_topology(unsigned int cpu)
+{
+ int sibling;
+
+ for_each_cpu(sibling, topology_core_cpumask(cpu))
+ cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
+ for_each_cpu(sibling, topology_sibling_cpumask(cpu))
+ cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
+ for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
+ cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
+
+ clear_cpu_topology(cpu, false);
+}
+
#ifdef CONFIG_ACPI
/*
* Propagate the topology information of the processor_topology_node tree to the
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/7] arm64: numa: separate out updates to percpu nodeid and NUMA node cpumap
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
Currently numa_clear_node removes both cpu information from the NUMA
node cpumap as well as the NUMA node id from the cpu. Similarly
numa_store_cpu_info updates both percpu nodeid and NUMA cpumap.
However we need to retain the numa node id for the cpu and only remove
the cpu information from the numa node cpumap during CPU hotplug out.
The same can be extended for hotplugging in the CPU.
This patch separates out numa_{add,remove}_cpu from numa_clear_node and
numa_store_cpu_info.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/include/asm/numa.h | 4 ++++
arch/arm64/kernel/smp.c | 2 ++
arch/arm64/mm/numa.c | 29 +++++++++++++++++++++--------
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/numa.h b/arch/arm64/include/asm/numa.h
index 01bc46d5b43a..626ad01e83bf 100644
--- a/arch/arm64/include/asm/numa.h
+++ b/arch/arm64/include/asm/numa.h
@@ -35,10 +35,14 @@ void __init numa_set_distance(int from, int to, int distance);
void __init numa_free_distance(void);
void __init early_map_cpu_to_node(unsigned int cpu, int nid);
void numa_store_cpu_info(unsigned int cpu);
+void numa_add_cpu(unsigned int cpu);
+void numa_remove_cpu(unsigned int cpu);
#else /* CONFIG_NUMA */
static inline void numa_store_cpu_info(unsigned int cpu) { }
+static inline void numa_add_cpu(unsigned int cpu) { }
+static inline void numa_remove_cpu(unsigned int cpu) { }
static inline void arm64_numa_init(void) { }
static inline void early_map_cpu_to_node(unsigned int cpu, int nid) { }
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index f3e2e3aec0b0..49a021e30dfb 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -225,6 +225,7 @@ asmlinkage void secondary_start_kernel(void)
notify_cpu_starting(cpu);
store_cpu_topology(cpu);
+ numa_add_cpu(cpu);
/*
* OK, now it's safe to let the boot CPU continue. Wait for
@@ -679,6 +680,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
this_cpu = smp_processor_id();
store_cpu_topology(this_cpu);
numa_store_cpu_info(this_cpu);
+ numa_add_cpu(this_cpu);
/*
* If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c
index dad128ba98bf..43cc669bc7bc 100644
--- a/arch/arm64/mm/numa.c
+++ b/arch/arm64/mm/numa.c
@@ -70,19 +70,32 @@ EXPORT_SYMBOL(cpumask_of_node);
#endif
-static void map_cpu_to_node(unsigned int cpu, int nid)
+static void numa_update_cpu(unsigned int cpu, bool remove)
{
- set_cpu_numa_node(cpu, nid);
- if (nid >= 0)
+ int nid = cpu_to_node(cpu);
+
+ if (nid < 0)
+ return;
+
+ if (remove)
+ cpumask_clear_cpu(cpu, node_to_cpumask_map[nid]);
+ else
cpumask_set_cpu(cpu, node_to_cpumask_map[nid]);
}
-void numa_clear_node(unsigned int cpu)
+void numa_add_cpu(unsigned int cpu)
{
- int nid = cpu_to_node(cpu);
+ numa_update_cpu(cpu, false);
+}
- if (nid >= 0)
- cpumask_clear_cpu(cpu, node_to_cpumask_map[nid]);
+void numa_remove_cpu(unsigned int cpu)
+{
+ numa_update_cpu(cpu, true);
+}
+
+void numa_clear_node(unsigned int cpu)
+{
+ numa_remove_cpu(cpu);
set_cpu_numa_node(cpu, NUMA_NO_NODE);
}
@@ -116,7 +129,7 @@ static void __init setup_node_to_cpumask_map(void)
*/
void numa_store_cpu_info(unsigned int cpu)
{
- map_cpu_to_node(cpu, cpu_to_node_map[cpu]);
+ set_cpu_numa_node(cpu, cpu_to_node_map[cpu]);
}
void __init early_map_cpu_to_node(unsigned int cpu, int nid)
--
2.7.4
^ permalink raw reply related
* [PATCH v2 1/7] arm64: topology: refactor reset_cpu_topology to add support for removing topology
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529327923-17911-1-git-send-email-sudeep.holla@arm.com>
Currently reset_cpu_topology clears all the CPU topology information
and resets to default values. However we may need to just clear the
information when we hotplug out the CPU. In preparation to add the
support the same, let's refactor reset_cpu_topology to clear out the
information and reset them only if explicitly requested.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm64/kernel/topology.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index f845a8617812..6ea3ec49d418 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -293,26 +293,33 @@ void store_cpu_topology(unsigned int cpuid)
update_siblings_masks(cpuid);
}
-static void __init reset_cpu_topology(void)
+static void clear_cpu_topology(int cpu, bool reset)
{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- struct cpu_topology *cpu_topo = &cpu_topology[cpu];
+ struct cpu_topology *cpu_topo = &cpu_topology[cpu];
+ if (reset) {
cpu_topo->thread_id = -1;
cpu_topo->core_id = 0;
cpu_topo->package_id = -1;
cpu_topo->llc_id = -1;
- cpumask_clear(&cpu_topo->llc_siblings);
- cpumask_set_cpu(cpu, &cpu_topo->llc_siblings);
-
- cpumask_clear(&cpu_topo->core_sibling);
- cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
- cpumask_clear(&cpu_topo->thread_sibling);
- cpumask_set_cpu(cpu, &cpu_topo->thread_sibling);
}
+
+ cpumask_clear(&cpu_topo->llc_siblings);
+ cpumask_set_cpu(cpu, &cpu_topo->llc_siblings);
+
+ cpumask_clear(&cpu_topo->core_sibling);
+ cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
+ cpumask_clear(&cpu_topo->thread_sibling);
+ cpumask_set_cpu(cpu, &cpu_topo->thread_sibling);
+}
+
+static void __init reset_cpu_topology(void)
+{
+ unsigned int cpu;
+
+ for_each_possible_cpu(cpu)
+ clear_cpu_topology(cpu, true);
}
#ifdef CONFIG_ACPI
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/7] arm64: numa/topology/smp: update the cpumasks for CPU hotplug
From: Sudeep Holla @ 2018-06-18 13:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Commit 37c3ec2d810f ("arm64: topology: divorce MC scheduling domain from core_siblings")
was reported to cause some hotplug and system suspend regressions when
it was merged. On investigation, it was found that unlike x86/PPC,
arm64 doesn't update the cpu and numa masks on CPU hotplug. That's
somewhat expected from the scheduler.
Since these changes were bit invasive as a solution to the above
mentioned regression, as small change was temporarily applied as a fix.
This series updates the cpu and numa masks on CPU hotplug and reverts
that temporary fix.
It would be good to get this tested(CPU hotplug - few and all CPUs in
a socket) on multi-socket/NUMA systems from Cavium and Huawei/Hisilicon.
Regards,
Sudeep
v1->v2:
- Rebased on v4.18-rc1 and hence do revert of the temporary fix
that was merged for v4.18
- Removed one of the wrong use of possible_mask
Sudeep Holla (7):
arm64: topology: refactor reset_cpu_topology to add support for removing topology
arm64: numa: separate out updates to percpu nodeid and NUMA node cpumap
arm64: topology: add support to remove cpu topology sibling masks
arm64: topology: restrict updating siblings_masks to online cpus only
arm64: smp: remove cpu and numa topology information when hotplugging out CPU
arm64: topology: rename llc_siblings to align with other struct members
arm64: topology: re-introduce numa mask check for scheduler MC selection
arch/arm64/include/asm/numa.h | 4 +++
arch/arm64/include/asm/topology.h | 3 +-
arch/arm64/kernel/smp.c | 5 +++
arch/arm64/kernel/topology.c | 69 ++++++++++++++++++++++++++-------------
arch/arm64/mm/numa.c | 29 +++++++++++-----
5 files changed, 79 insertions(+), 31 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2] regulator: core: Enable voltage balancing
From: Maciej Purski @ 2018-06-18 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180615112916.GK112168@atomide.com>
On 06/15/2018 01:29 PM, Tony Lindgren wrote:
> Hi,
>
> * Maciej Purski <m.purski@samsung.com> [180613 10:39]:
>> Call regulator_balance_voltage() instead of set_voltage_rdev()
>> in set_voltage_unlocked() and in enabling and disabling functions,
>> but only if the regulator is coupled.
>>
>> Signed-off-by: Maciej Purski <m.purski@samsung.com>
>>
>> ---
>> Changes in v2:
>> - fix compile errors
>> - make debug messages more informative
>
> Thanks for updating it. This series still hangs after loading
> modules on beagleboard-x15:
>
> [ 26.679749] smps12: regulator_set_voltage: 3381
> [ 26.684529] smps12: regulator_set_voltage_unlocked: 3045
> [ 26.695616] smps12: _regulator_do_set_voltage: 2912
> [ 26.701275] smps12: regulator_set_voltage: 3381
> [ 26.706002] smps12: regulator_set_voltage_unlocked: 3045
> [ 26.712349] smps12: _regulator_do_set_voltage: 2912
> [ 26.719329] abb_mpu: regulator_set_voltage: 3381
> [ 26.724105] abb_mpu: regulator_set_voltage_unlocked: 3045
>
> So it seems to be the abb_mpu where it hangs?
>
> Regards,
>
> Tony
>
Hi,
thanks for testing. Yes, it seems that it fails on abb_mpu. I don't know
yet, what is so special about that regulator.
We know at least, that it fails on voltage setting somewhere
between set_voltage_unlocked() and do_set_voltage()
and it does not look like any locking issue.
The most suspicious part in voltage balancing code is of course the
infinite loop. Soon I'll send a next patch on top of my latest compiling
path:
2ff49a6 regulator: core: Enable voltage balancing.
It should reveal, if it is indeed the loop.
As usual, I'd be grateful, if you gave it a try.
Best regards,
Maciej Purski
^ permalink raw reply
* [PATCH] ARM: dts: imx7d-sdb: Remove duplicate regulator-can2-3v3
From: Leonard Crestez @ 2018-06-18 13:11 UTC (permalink / raw)
To: linux-arm-kernel
Two different regulators are defined with the same name and label but
distinct properties.
The first definition was added with the first board dts and the second
was added when upstream added flexcan support.
Looking at schematics it is indeed gpio2 14 connected to the STB pin of
the CAN transceiver so remove the first definition.
The second definition entirely overrides the first so this already
worked and this patch results in no DTB change, just a cleanup.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
arch/arm/boot/dts/imx7d-sdb.dts | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 940849163104..9f9e6a1e3b72 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -69,18 +69,10 @@
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
- reg_can2_3v3: regulator-can2-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "can2-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
-
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
--
2.17.1
^ permalink raw reply related
* [linux-sunxi] [PATCH v2 00/27] Add support for R40 HDMI pipeline
From: Jagan Teki @ 2018-06-18 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5084905.C41JrL457O@jernej-laptop>
On Thu, Jun 14, 2018 at 10:59 PM, Jernej ?krabec
<jernej.skrabec@siol.net> wrote:
> Dne ?etrtek, 14. junij 2018 ob 19:16:46 CEST je Jagan Teki napisal(a):
>> On Thu, Jun 14, 2018 at 8:04 PM, Jernej ?krabec <jernej.skrabec@siol.net>
> wrote:
>> > Dne ?etrtek, 14. junij 2018 ob 09:12:41 CEST je Jagan Teki napisal(a):
>> >> On Wed, Jun 13, 2018 at 1:30 AM, Jernej Skrabec <jernej.skrabec@siol.net>
>> >
>> > wrote:
>> >> > This series adds support for R40 HDMI pipeline. It is a bit special
>> >> > than other already supported pipelines because it has additional unit
>> >> > called TCON TOP responsible for relationship configuration between
>> >> > mixers, TCONs and HDMI. Additionally, it has additional gates for DSI
>> >> > and TV TCONs, TV encoder clock settings and pin muxing between LCD
>> >> > and TV encoders.
>> >> >
>> >> > However, it seems that TCON TOP will become a norm, since newer
>> >> > Allwinner SoCs like H6 also have this unit.
>> >> >
>> >> > I tested different possible configurations:
>> >> > - mixer0 <> TCON-TV0 <> HDMI
>> >> > - mixer0 <> TCON-TV1 <> HDMI
>> >> > - mixer1 <> TCON-TV0 <> HDMI
>> >> > - mixer1 <> TCON-TV1 <> HDMI
>> >> >
>> >> > Please review.
>> >> >
>> >> > Best regards,
>> >> > Jernej
>> >> >
>> >> > Changes from v1:
>> >> > - Split DT bindings patch and updated description
>> >> > - Split HDMI PHY patch
>> >> > - Move header file from TCON TOP patch to dt bindings patch
>> >> > - Added Rob reviewed-by tag
>> >> > - Used clk_hw_register_gate() instead of custom gate registration code
>> >> > - Reworked TCON TOP to be part of of-graph. Because of that, a lot of
>> >> >
>> >> > new patches were added.
>> >> >
>> >> > - Droped mixer index quirk patch
>> >> > - Reworked TCON support for TCON TOP
>> >> > - Updated commit messages
>> >> >
>> >> > Jernej Skrabec (27):
>> >> > clk: sunxi-ng: r40: Add minimal rate for video PLLs
>> >> > clk: sunxi-ng: r40: Allow setting parent rate to display related
>> >> >
>> >> > clocks
>> >> >
>> >> > clk: sunxi-ng: r40: Export video PLLs
>> >> > dt-bindings: display: sunxi-drm: Add TCON TOP description
>> >> > drm/sun4i: Add TCON TOP driver
>> >> > drm/sun4i: Fix releasing node when enumerating enpoints
>> >> > drm/sun4i: Split out code for enumerating endpoints in output port
>> >> > drm/sun4i: Add support for traversing graph with TCON TOP
>> >> > drm/sun4i: Don't skip TCONs if they don't have channel 0
>> >> > dt-bindings: display: sun4i-drm: Add R40 TV TCON description
>> >> > drm/sun4i: tcon: Add support for tcon-top gate
>> >> > drm/sun4i: tcon: Generalize engine search algorithm
>> >> > drm/sun4i: Don't check for LVDS and RGB when TCON has only ch1
>> >> > drm/sun4i: Don't check for panel or bridge on TV TCONs
>> >> > drm/sun4i: Add support for R40 TV TCON
>> >> > dt-bindings: display: sun4i-drm: Add R40 mixer compatibles
>> >> > drm/sun4i: Add support for R40 mixers
>> >> > dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY
>> >> > drm/sun4i: Enable DW HDMI PHY clock
>> >> > drm/sun4i: Don't change clock bits in DW HDMI PHY driver
>> >> > drm/sun4i: DW HDMI PHY: Add support for second PLL
>> >> > drm/sun4i: Add support for second clock parent to DW HDMI PHY clk
>> >> >
>> >> > driver
>> >> >
>> >> > drm/sun4i: Add support for A64 HDMI PHY
>> >> > drm: of: Export drm_crtc_port_mask()
>> >> > drm/sun4i: DW HDMI: Expand algorithm for possible crtcs
>> >> > ARM: dts: sun8i: r40: Add HDMI pipeline
>> >> > ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
>> >>
>> >> Tested whole series on top of linux-next.
>> >>
>> >> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
>> >
>> > Thanks!
>>
>> I've V40 board, which is same as R40. I'm able to detect the HDMI but
>> seems edid not detecting properly.
>>
>> [ 0.983007] sun4i-drm display-engine: bound 1100000.mixer (ops
>> 0xc074a80c) [ 0.999043] sun4i-drm display-engine: bound 1200000.mixer
>> (ops 0xc074a80c) [ 1.006229] sun4i-drm display-engine: bound
>> 1c70000.tcon-top (ops 0xc074e2ac) [ 1.013609] sun4i-drm display-engine:
>> bound 1c73000.lcd-controller (ops 0xc0747a28)
>> [ 1.053988] sun8i-dw-hdmi 1ee0000.hdmi: Detected HDMI TX controller
>> v1.32a with HDCP (sun8i_dw_hdmi_phy)
>> [ 1.063913] sun8i-dw-hdmi 1ee0000.hdmi: registered DesignWare HDMI
>> I2C bus driver
>> [ 1.071683] sun4i-drm display-engine: bound 1ee0000.hdmi (ops 0xc074a298)
>> [ 1.078484] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>> [ 1.085098] [drm] No driver support for vblank timestamp query. [
>> 1.091055] [drm] Cannot find any crtc or sizes
>> [ 1.095995] [drm] Initialized sun4i-drm 1.0.0 20150629 for
>> display-engine on minor 0
>
> This seems like DT issue. Can you post somewhere your V40 DTSI (if it is
> different to R40) and board DTS?
same dtsi shared between r40 and v40, here is board dts support for HDMI[1]
[1] https://paste.ubuntu.com/p/wqVz38BHrM/
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