* [PATCH] driver core: add a debugfs entry to show deferred devices
From: Javier Martinez Canillas @ 2018-06-20 9:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ea628ded-3cb3-c426-da6d-bf7cb51f4ca8@redhat.com>
[adding Peter Robinson - Fedora IoT Architect to cc list]
On 06/20/2018 10:46 AM, Javier Martinez Canillas wrote:
> On 06/20/2018 12:51 AM, Greg Kroah-Hartman wrote:
>
> [snip]
>
>>> @@ -233,6 +252,9 @@ void device_unblock_probing(void)
>>> */
>>> static int deferred_probe_initcall(void)
>>> {
>>> + debugfs_create_file("deferred_devices", 0444, NULL, NULL,
>>> + &deferred_devs_fops);
>>
>> In the root of debugfs?
>>
>
> I added in the root for lack of a better place. Any suggestion is welcomed.
>
>> Anyway, what about "devices_deferred", to help keep things semi-sane if
>> we have other driver core debugfs entries?
>>
>
> I don't have a strong opinion on the name really, so I'll change it.
>
>> And you don't remove the file ever?
>>
>
> Yeah, I saw that it wasn't removed in other places for debugfs entries
> created by the core since unlike drivers they can't be built as a module
> or re-loaded. But you are right, I'll add an __exitcall to remove there.
>
>> And what is the use of this file? What can you do with this
>> information? Who is going to use it? Don't we have other deferred
>
> This patch is the result of a discussion with Tomeu and Mark (cc'ed) to
> allow https://kernelci.org to test if there was a regression that makes
> drivers to defer their probe.
>
> The problem with the probe deferral mechanism is that you don't have a
> way to distinguish between a valid deferral due a dependency not being
> available yet and a bug (i.e: wrong DTB, config symbol not enabled, etc)
> that prevents the device to eventually being probed.
>
This is not only useful for catching regressions though, Peter also told me
that having this information would save him a lot of time when doing hardware
bringup for ARM devices / IoT platforms.
As mentioned, debugging probe deferral issues caused by drivers not available
or wrong Device Trees is really a PITA. Not all architectures have the luxury
of ACPI / PnP / auto enumerable buses / etc, that hide all this complexity.
So the most information to troubleshoot we have, the better in my opinion.
>> probe debugging somewhere else?
>>
>
> There is some debug yes, but it isn't suitable for the use case I explained.
>
> For start, it only tells you if a given driver for a device was deferred or
> probed correctly while this patch attempts to tell what was left (if any)
> in the queue after the last driver was registered.
>
> Second, is only enabled until late_initcall so it will only print the probe
> deferral for built-in drivers and not for modules. This patch registers the
> debugfs entry after the probe debugging has been disabled.
>
>> thanks,
>>
>> greg k-h
>>
Best regards,
--
Javier Martinez Canillas
Software Engineer - Desktop Hardware Enablement
Red Hat
^ permalink raw reply
* [PATCH 00/20] coresight: Update device tree bindings
From: Suzuki K Poulose @ 2018-06-20 9:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528235011-30691-1-git-send-email-suzuki.poulose@arm.com>
On 05/06/18 22:43, Suzuki K Poulose wrote:
> Coresight uses DT graph bindings to describe the connections of the
> components. However we have some undocumented usage of the bindings
> to describe some of the properties of the connections.
>
> The coresight driver needs to know the hardware ports invovled
> in the connection and the direction of data flow to effectively
> manage the trace sessions. So far we have relied on the "port"
> address (as described by the generic graph bindings) to represent
> the hardware port of the component for a connection.
>
...
> There were three options considered for the hardware port number scheme:
>
...
> 3) Use explicit properties (implemented in the series) for the hardware
> port id and direction. We define a new property "coresight,hwid" for
> each endpoint in coresight devices to specify the hardware port number
> explicitly. Also use a separate property "direction" to specify the
> direction of the data flow.
>
> e.g,
>
> port at 0{
> reg = <0>;
> endpoint {
> direction = <1>; // Output
> coresight,hwid = <0>; // Port # 0
> }
> };
>
> port at 1{
> reg = <1>;
> endpoint {
> direction = <0>; // Input
> coresight,hwid = <0>; // Port # 0
> };
> };
>
> Pros:
> - The bindings are formal and reader friendly, and less prone to errors.
> Cons:
> - Backward compatibility is lost.
>
>
> This series implements Option (3) listed above and falls back to the old
> bindings if the new bindings are not available. This allows the systems
> with old bindings work with the new driver. The driver now issues a warning
> (once) when it encounters the old bindings.
....
> dts: juno: Update coresight bindings for hw port
> dts: hisilicon: Update coresight bindings for hw ports
> dts: spreadtrum: Update coresight bindings for hw ports
> dts: qcom: Update coresight bindings for hw ports
> dts: arm: hisilicon: Update coresight bindings for hardware port
> dts: arm: imx7{d,s}: Update coresight binding for hardware ports
> dts: arm: omap: Update coresight bindings for hardware ports
> dts: arm: qcom: Update coresight bindings for hardware ports
> dts: sama5d2: Update coresight bindings for hardware ports
> dts: ste-dbx5x0: Update coresight bindings for hardware port
> dts: tc2: Update coresight bindings for hardware ports
>
All,
Pleas hold on with applying the DTS changes listed above. There are
still some on going discussions on the bindings and we are yet to
come to a conclusion [0]. And there are high chances that these might
change. Sorry for the inconvenience.
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-June/582269.html
Kind regards
Suzuki
^ permalink raw reply
* [PATCH V2 0/3] add iwdg2 support for stm32mp157c
From: Alexandre Torgue @ 2018-06-20 10:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529481238-15277-1-git-send-email-ludovic.Barre@st.com>
Hi Ludovic
On 06/20/2018 09:53 AM, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch series updates stm32_iwdg driver to manage config
> by compatible. stm32mp1 config requires a pclk clock.
>
> Ludovic Barre (3):
> watchdog: stm32: add pclk feature for stm32mp1
> ARM: dts: stm32: add iwdg2 support for stm32mp157c
> ARM: dts: stm32: add iwdg2 support for stm32mp157c-ed1
>
> .../devicetree/bindings/watchdog/st,stm32-iwdg.txt | 21 +++-
> arch/arm/boot/dts/stm32mp157c-ed1.dts | 5 +
> arch/arm/boot/dts/stm32mp157c.dtsi | 8 ++
> drivers/watchdog/stm32_iwdg.c | 132 ++++++++++++++-------
> 4 files changed, 117 insertions(+), 49 deletions(-)
>
STM32 DT patches looks good to me. I will take them as soon as driver
part is acked.
Regards
Alex
^ permalink raw reply
* [PATCH] arm64/mm: Introduce a variable to hold base address of linear region
From: James Morse @ 2018-06-20 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACi5LpMXpSWUP97R2VWjf==LdxPBCKTcpKjQjCs4j3Kz9SzYGg@mail.gmail.com>
Hi guys,
On 20/06/18 08:26, Bhupesh Sharma wrote:
> On Wed, Jun 20, 2018 at 7:46 AM, Jin, Yanjiang
> <yanjiang.jin@hxt-semitech.com> wrote:
>> If /proc/kcore always exists in kexec/kdump, I think this issue can be fixed
>> easily. But it requires that Kexec/kdump have to rely on " CONFIG_PROC_KCORE=y".
>> I am not sure if we can persuade Kexec-tools community to accept this.
For the kernel this would be:
--------------%<--------------
diff --git a/arch/Kconfig b/arch/Kconfig
index 1aa59063f1fd..0ea2c7c0ac08 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -8,6 +8,7 @@ config CRASH_CORE
config KEXEC_CORE
select CRASH_CORE
+ select PROC_KCORE
bool
config HAVE_IMA_KEXEC
--------------%<--------------
With this kernel's that support kdump but don't have /proc/kcore wouldn't have
the new PT_NOTEs anyway. Whatever you do today is all you can do.
> Most distributions like Ubuntu and Fedora already enable
> CONFIG_PROC_KCORE by default, to support user-space tools like
> crash-utility and makedumpfile which can be used for 'live' debugging
> of a primary kernel (without the requirement of being in the secondary
> or crash kernel).
>
> For such cases. '/proc/kcore' and 'vmlinux' are the only available
> sources for PT_NOTE/PT_LOAD segments and kernel symbols respectively.
>
> Since we need to support all such existing user-space utilities (which
> work well with other archs like x86 and ppc64),
x86 has kaslr too, I couldn't work out how your user-space:phys_to_virt() works
there. Are we missing an alternative trick?
> we need to have a
> solution which works without modifying most of them - the rest (like
> kexec-tools) can be easily modified to follow the same approach.
(We're also trying to solve this in a way that lets user-space shed
arch-specific code.)
Thanks,
James
^ permalink raw reply related
* [PATCH v5 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks
From: Thomas Gleixner @ 2018-06-20 10:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620094649.GA2766@piout.net>
On Wed, 20 Jun 2018, Alexandre Belloni wrote:
> On 20/06/2018 11:03:40+0200, Thomas Gleixner wrote:
> > > +/*
> > > + * Clocksource and clockevent using the same channel(s)
> > > + */
> > > +static u64 tc_get_cycles(struct clocksource *cs)
> > > +{
> > > + u32 lower, upper;
> > > +
> > > + do {
> > > + upper = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1]));
> > > + lower = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > + } while (upper != readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1])));
> > > +
> > > + return (upper << 16) | lower;
> > > +}
> >
> > For timekeeping the win of this is dubious. With a 5Mhz clock the 32bit
> > part wraps around in ~859 seconds, which is plenty even for NOHZ.
> >
> > So I really would avoid the double read/compare/eventually repeat magic and
> > just use the lower 32bits for performance sake. I assume the same is true
> > for sched_clock(), but I might be wrong.
> >
>
> Agreed, this is why this is only used with the 16 bit counters (the
> register is 32 bit wide but the counter only have 16 bits. For the 32
> bit counters, tc_get_cycles32 is used and only use one counter.
Ah, sorry. I misread the code. Missed that it's the 16bit case.
> > > +static int tcb_clkevt_next_event(unsigned long delta,
> > > + struct clock_event_device *d)
> > > +{
> > > + u32 old, next, cur;
> > > +
> > > + old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > + next = old + delta;
> > > + writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
> > > + cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > +
> > > + /* check whether the delta elapsed while setting the register */
> > > + if ((next < old && cur < old && cur > next) ||
> > > + (next > old && (cur < old || cur > next))) {
> > > + /*
> > > + * Clear the CPCS bit in the status register to avoid
> > > + * generating a spurious interrupt next time a valid
> > > + * timer event is configured.
> > > + */
> > > + old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
> > > + return -ETIME;
> > > + }
> >
> > Aarg. Doesn;t that timer block have a simple count down and fire mode?
> > These compare equal timers suck.
>
> It only counts up...
Have you tried to play with that waveform stuff?
Thanks,
tglx
^ permalink raw reply
* [PATCH 1/1] arm64/mm: move {idmap_pg_dir, tramp_pg_dir, swapper_pg_dir} to .rodata section
From: Ard Biesheuvel @ 2018-06-20 10:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620085755.20045-2-yaojun8558363@gmail.com>
On 20 June 2018 at 10:57, Jun Yao <yaojun8558363@gmail.com> wrote:
> Move {idmap_pg_dir,tramp_pg_dir,swapper_pg_dir} to .rodata
> section. And update the swapper_pg_dir by fixmap.
>
I think we may be able to get away with not mapping idmap_pg_dir and
tramp_pg_dir at all.
As for swapper_pg_dir, it would indeed be nice if we could keep those
mappings read-only most of the time, but I'm not sure how useful this
is if we apply it to the root level only.
> Signed-off-by: Jun Yao <yaojun8558363@gmail.com>
> ---
> arch/arm64/include/asm/pgalloc.h | 19 +++++++++++++++++++
> arch/arm64/kernel/vmlinux.lds.S | 32 ++++++++++++++++++--------------
> arch/arm64/mm/mmu.c | 23 +++++++++++++++++++----
> 3 files changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
> index 2e05bcd944c8..cc96a7e6957d 100644
> --- a/arch/arm64/include/asm/pgalloc.h
> +++ b/arch/arm64/include/asm/pgalloc.h
> @@ -29,6 +29,10 @@
> #define PGALLOC_GFP (GFP_KERNEL | __GFP_ZERO)
> #define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
>
> +#if CONFIG_STRICT_KERNEL_RWX
> +extern spinlock_t pgdir_lock;
> +#endif
> +
> #if CONFIG_PGTABLE_LEVELS > 2
>
> static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
> @@ -78,6 +82,21 @@ static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pudp, pgdval_t prot)
>
> static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgdp, pud_t *pudp)
> {
> +#if CONFIG_STRICT_KERNEL_RWX
> + if (mm == &init_mm) {
> + pgd_t *pgd;
> +
> + spin_lock(&pgdir_lock);
> + pgd = pgd_set_fixmap(__pa_symbol(swapper_pg_dir));
> +
> + pgd = (pgd_t *)((unsigned long)pgd + pgdp - swapper_pg_dir);
> + __pgd_populate(pgdp, __pa(pudp), PUD_TYPE_TABLE);
> +
This only works for 4-level paging, but we support 2 and 3 level paging as well.
> + pgd_clear_fixmap();
> + spin_unlock(&pgdir_lock);
> + return;
> + }
> +#endif
> __pgd_populate(pgdp, __pa(pudp), PUD_TYPE_TABLE);
> }
> #else
> diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
> index 605d1b60469c..86532c57206a 100644
> --- a/arch/arm64/kernel/vmlinux.lds.S
> +++ b/arch/arm64/kernel/vmlinux.lds.S
> @@ -216,21 +216,25 @@ SECTIONS
> BSS_SECTION(0, 0, 0)
>
> . = ALIGN(PAGE_SIZE);
> - idmap_pg_dir = .;
> - . += IDMAP_DIR_SIZE;
>
> -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
> - tramp_pg_dir = .;
> - . += PAGE_SIZE;
> -#endif
> -
> -#ifdef CONFIG_ARM64_SW_TTBR0_PAN
> - reserved_ttbr0 = .;
> - . += RESERVED_TTBR0_SIZE;
> -#endif
> - swapper_pg_dir = .;
> - . += SWAPPER_DIR_SIZE;
> - swapper_pg_end = .;
> + .rodata : {
> + . = ALIGN(PAGE_SIZE);
> + idmap_pg_dir = .;
> + . += IDMAP_DIR_SIZE;
> +
> + #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
CPP directives should start in the first column
> + tramp_pg_dir = .;
> + . += PAGE_SIZE;
> + #endif
> +
> + #ifdef CONFIG_ARM64_SW_TTBR0_PAN
> + reserved_ttbr0 = .;
> + . += RESERVED_TTBR0_SIZE;
> + #endif
> + swapper_pg_dir = .;
> + . += SWAPPER_DIR_SIZE;
> + swapper_pg_end = .;
> + }
>
> __pecoff_data_size = ABSOLUTE(. - __initdata_begin);
> _end = .;
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 2dbb2c9f1ec1..c1aa85a6ada5 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -66,6 +66,10 @@ static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
> static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss __maybe_unused;
> static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss __maybe_unused;
>
> +#ifdef CONFIG_STRICT_KERNEL_RWX
> +DEFINE_SPINLOCK(pgdir_lock);
> +#endif
> +
> pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
> unsigned long size, pgprot_t vma_prot)
> {
> @@ -417,12 +421,22 @@ static void __init __map_memblock(pgd_t *pgdp, phys_addr_t start,
>
> void __init mark_linear_text_alias_ro(void)
> {
> + unsigned long size;
> +
> /*
> * Remove the write permissions from the linear alias of .text/.rodata
> + *
> + * We free some pages in .rodata at paging_init(), which generates a
> + * hole. And the hole splits .rodata into two pieces.
> */
> + size = (unsigned long)swapper_pg_dir + PAGE_SIZE - (unsigned long)_text;
> update_mapping_prot(__pa_symbol(_text), (unsigned long)lm_alias(_text),
> - (unsigned long)__init_begin - (unsigned long)_text,
> - PAGE_KERNEL_RO);
> + size, PAGE_KERNEL_RO);
> +
> + size = (unsigned long)__init_begin - (unsigned long)swapper_pg_end;
> + update_mapping_prot(__pa_symbol(swapper_pg_end),
> + (unsigned long)lm_alias(swapper_pg_end),
> + size, PAGE_KERNEL_RO);
I don't think this is necessary. Even if some pages are freed, it
doesn't harm to keep a read-only alias of them here since the new
owner won't access them via this mapping anyway. So we can keep
.rodata as a single region.
> }
>
> static void __init map_mem(pgd_t *pgdp)
> @@ -587,8 +601,9 @@ static void __init map_kernel(pgd_t *pgdp)
> */
> map_kernel_segment(pgdp, _text, _etext, text_prot, &vmlinux_text, 0,
> VM_NO_GUARD);
> - map_kernel_segment(pgdp, __start_rodata, __inittext_begin, PAGE_KERNEL,
> - &vmlinux_rodata, NO_CONT_MAPPINGS, VM_NO_GUARD);
> + map_kernel_segment(pgdp, __start_rodata, __inittext_begin,
> + PAGE_KERNEL, &vmlinux_rodata,
> + NO_CONT_MAPPINGS | NO_BLOCK_MAPPINGS, VM_NO_GUARD);
Given the above, you should be able to drop this as well.
> map_kernel_segment(pgdp, __inittext_begin, __inittext_end, text_prot,
> &vmlinux_inittext, 0, VM_NO_GUARD);
> map_kernel_segment(pgdp, __initdata_begin, __initdata_end, PAGE_KERNEL,
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH] ARM: dts: imx6sll: declare src module to be compatible to imx51's src
From: Fabio Estevam @ 2018-06-20 10:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529483917-18057-1-git-send-email-Anson.Huang@nxp.com>
On Wed, Jun 20, 2018 at 5:38 AM, Anson Huang <Anson.Huang@nxp.com> wrote:
> i.MX6SLL uses same SRC module as i.MX51, add "fsl,imx51-src"
> compatible string to enable SRC driver to support setting
> CPU resume address for cpu-idle and suspend/resume.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH v5 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks
From: Alexandre Belloni @ 2018-06-20 10:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.21.1806201156510.10546@nanos.tec.linutronix.de>
On 20/06/2018 12:07:00+0200, Thomas Gleixner wrote:
> > > > +static int tcb_clkevt_next_event(unsigned long delta,
> > > > + struct clock_event_device *d)
> > > > +{
> > > > + u32 old, next, cur;
> > > > +
> > > > + old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > > + next = old + delta;
> > > > + writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
> > > > + cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > > +
> > > > + /* check whether the delta elapsed while setting the register */
> > > > + if ((next < old && cur < old && cur > next) ||
> > > > + (next > old && (cur < old || cur > next))) {
> > > > + /*
> > > > + * Clear the CPCS bit in the status register to avoid
> > > > + * generating a spurious interrupt next time a valid
> > > > + * timer event is configured.
> > > > + */
> > > > + old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
> > > > + return -ETIME;
> > > > + }
> > >
> > > Aarg. Doesn;t that timer block have a simple count down and fire mode?
> > > These compare equal timers suck.
> >
> > It only counts up...
>
> Have you tried to play with that waveform stuff?
>
There are only a count up and count up then down modes. As the counter
value is in a read only register, the only configurable starting value
is 0 so it will always start by counting up. I'm pretty sure the up/down
mode will not help us.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH] ARM: dts: imx7d-sdb: Restore pwm backlight support
From: Leonard Crestez @ 2018-06-20 10:41 UTC (permalink / raw)
To: linux-arm-kernel
This was removed in commit 5eaeaccdaedb ("ARM: dts: imx7d-sdb: Pass
'enable-gpios' and 'power-supply' properties") with a note claiming that
GPIO1_IO01 is connected to a pin labeled as "PWREN" on the connector.
Despite that label this pin does actually work as a PWM controlling
brightness. So restore pwm functionality.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
arch/arm/boot/dts/imx7d-sdb.dts | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
This was tested with the suggested LCD8000-43T, maybe there are other
display options which don't have PWM and require that pin to be always
enabled?
This same LCD is also supported on imx6ul-14x14-evk with a similar
backlight.
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 940849163104..bf6f21b984ca 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -114,14 +114,21 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
panel {
compatible = "innolux,at043tn24";
- pinctrl-0 = <&pinctrl_backlight>;
- enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
power-supply = <®_lcd_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
@@ -710,18 +717,24 @@
>;
};
};
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
&iomuxc_lpsr {
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
- pinctrl_backlight: backlightgrp {
+ pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0
+ MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
>;
};
};
--
2.17.1
^ permalink raw reply related
* [PATCH] ARM: dts: imx7d-sdb: Restore pwm backlight support
From: Fabio Estevam @ 2018-06-20 10:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c328d3e13702fa624febe08d7cd68df5b82b8c30.1529490998.git.leonard.crestez@nxp.com>
On Wed, Jun 20, 2018 at 7:41 AM, Leonard Crestez
<leonard.crestez@nxp.com> wrote:
> This was removed in commit 5eaeaccdaedb ("ARM: dts: imx7d-sdb: Pass
> 'enable-gpios' and 'power-supply' properties") with a note claiming that
> GPIO1_IO01 is connected to a pin labeled as "PWREN" on the connector.
>
> Despite that label this pin does actually work as a PWM controlling
> brightness. So restore pwm functionality.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Yes, it seems to me that the PWM functionality has been removed by mistake:
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH 18/20] dts: sama5d2: Update coresight bindings for hardware ports
From: Alexandre Belloni @ 2018-06-20 10:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <abf65bac-0956-f1de-127e-38b0f41a6233@arm.com>
On 20/06/2018 10:44:29+0100, Suzuki K Poulose wrote:
> On 19/06/18 22:24, Alexandre Belloni wrote:
> > On 05/06/2018 22:43:29+0100, Suzuki K Poulose wrote:
> > > Switch to the new coresight bindings for hardware ports
> > >
> > > Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
> > > Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > ---
> > > arch/arm/boot/dts/sama5d2.dtsi | 5 ++++-
> > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > Applied, thanks.
> >
>
> Alexandre,
>
> Please hold off applying this change, as we are yet to come to an
> agreement on this. Sorry for the trouble. See [0]
>
I've removed it.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH] driver core: add a debugfs entry to show deferred devices
From: Mark Brown @ 2018-06-20 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180619225145.GA23389@kroah.com>
On Wed, Jun 20, 2018 at 07:51:45AM +0900, Greg Kroah-Hartman wrote:
> And what is the use of this file? What can you do with this
> information? Who is going to use it? Don't we have other deferred
> probe debugging somewhere else?
Pretty much all we have right now is kernel log messages, and people
keep trying to suppress those as they're quite noisy sometimes. Ideally
the device dependency stuff will reduce that problem but I'm not sure
how that's getting on.
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^ permalink raw reply
* [PATCH v5 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks
From: Thomas Gleixner @ 2018-06-20 10:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620103259.GA7737@piout.net>
On Wed, 20 Jun 2018, Alexandre Belloni wrote:
> On 20/06/2018 12:07:00+0200, Thomas Gleixner wrote:
> > > > > +static int tcb_clkevt_next_event(unsigned long delta,
> > > > > + struct clock_event_device *d)
> > > > > +{
> > > > > + u32 old, next, cur;
> > > > > +
> > > > > + old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > > > + next = old + delta;
> > > > > + writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
> > > > > + cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
> > > > > +
> > > > > + /* check whether the delta elapsed while setting the register */
> > > > > + if ((next < old && cur < old && cur > next) ||
> > > > > + (next > old && (cur < old || cur > next))) {
> > > > > + /*
> > > > > + * Clear the CPCS bit in the status register to avoid
> > > > > + * generating a spurious interrupt next time a valid
> > > > > + * timer event is configured.
> > > > > + */
> > > > > + old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
> > > > > + return -ETIME;
> > > > > + }
> > > >
> > > > Aarg. Doesn;t that timer block have a simple count down and fire mode?
> > > > These compare equal timers suck.
> > >
> > > It only counts up...
> >
> > Have you tried to play with that waveform stuff?
> >
>
> There are only a count up and count up then down modes. As the counter
> value is in a read only register, the only configurable starting value
> is 0 so it will always start by counting up. I'm pretty sure the up/down
> mode will not help us.
Hmm, fair enough.
Though the manual says:
A trigger resets the counter and starts the counter clock. Three types
of triggers are common to both modes, and a fourth external trigger is
available to each mode.
...
Software Trigger: Each channel has a software trigger, available by
setting SWTRG in TC_CCR.
So the question is whether you can't do the following:
stop_counter()
issue_sw_trigger() ---> resets the counter to zero
write_compare()
start_counter()
So that should avoid all te mess with comparing to the free running counter
as long as you have two blocks of counters, but then one of them will be
16bit only assumed that there are always 3 counter channels in the TC.
Just a thought, but the code you have should work as well.
Thanks,
tglx
^ permalink raw reply
* [PATCH v5 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks
From: Alexandre Belloni @ 2018-06-20 11:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.21.1806201244110.10546@nanos.tec.linutronix.de>
On 20/06/2018 12:58:01+0200, Thomas Gleixner wrote:
> > There are only a count up and count up then down modes. As the counter
> > value is in a read only register, the only configurable starting value
> > is 0 so it will always start by counting up. I'm pretty sure the up/down
> > mode will not help us.
>
> Hmm, fair enough.
>
> Though the manual says:
>
> A trigger resets the counter and starts the counter clock. Three types
> of triggers are common to both modes, and a fourth external trigger is
> available to each mode.
>
> ...
>
> Software Trigger: Each channel has a software trigger, available by
> setting SWTRG in TC_CCR.
>
> So the question is whether you can't do the following:
>
> stop_counter()
> issue_sw_trigger() ---> resets the counter to zero
> write_compare()
> start_counter()
>
> So that should avoid all te mess with comparing to the free running counter
> as long as you have two blocks of counters, but then one of them will be
> 16bit only assumed that there are always 3 counter channels in the TC.
>
> Just a thought, but the code you have should work as well.
>
Ah yes, sure, I misunderstood your first comment then. the driver will
register one or two clockevent devices, depending on the number of
available channels.
The first one is based on the clocksource counter and does the counter
comparison you don't like. the second one uses its own channel in the
way you describe (set RC, reset counter, start counter).
This was necessary because some people are running out of TCB channels
as they use the remaining ones as PWMs. But it is still better to use
one channel as clocksource and clockevent that use the PIT.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v3 0/2] mmc: sdhci-of-arasan: workaround for broken clocks
From: Helmut Grohne @ 2018-06-20 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180615081830.zrgx6arwn6ga27gu@laureti-dev>
This patch series works around the internal clock indicating stability too
quickly to operate. It manifests itself as:
mmc0: error -84 whilst initialising SD card
Changes since v2:
* Ulf Hansson requested splitting the patch in accordance with
Documentation/devicetree/bindings/submitting-patches.txt. Also update
recipient list accordingly.
* Added Acked-by from Adrian Hunter.
Helmut Grohne (2):
dt-bindings: mmc: broken clock stable indicator on arasan controllers
mmc: sdhci-of-arasan: Add quirk for unstable clocks
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 ++
drivers/mmc/host/sdhci-of-arasan.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
--
2.11.0
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: mmc: broken clock stable indicator on arasan controllers
From: Helmut Grohne @ 2018-06-20 11:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1529493667.git.h.grohne@intenta.de>
Some controllers immediately report that their internal clock is stable
after activating it even when the clock is not stable. When used in
conjunction with older/slower cards, this can result in:
mmc0: error -84 whilst initialising SD card
This flag allows documenting and thus working around such a hardware
defect.
Signed-off-by: Helmut Grohne <h.grohne@intenta.de>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 60481bfc3d31..28332b655d2e 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -39,6 +39,8 @@ Optional Properties:
- xlnx,fails-without-test-cd: when present, the controller doesn't work when
the CD line is not connected properly, and the line is not connected
properly. Test mode can be used to force the controller to function.
+ - xlnx,int-clock-stable-broken: when present, the controller always reports
+ that the internal clock is stable even when it is not.
Example:
sdhci at e0100000 {
--
2.11.0
^ permalink raw reply related
* [PATCH v3 2/2] mmc: sdhci-of-arasan: Add quirk for unstable clocks
From: Helmut Grohne @ 2018-06-20 11:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1529493667.git.h.grohne@intenta.de>
Some controllers immediately report SDHCI_CLOCK_INT_STABLE after
enabling the clock even when the clock is not stable. When used in
conjunction with older/slower cards, this can result in:
mmc0: error -84 whilst initialising SD card
When the stable reporting is known to be broken, we simply wait for the
maximum stabilization period.
Signed-off-by: Helmut Grohne <h.grohne@intenta.de>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-of-arasan.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index e3332a522a5d..a40bcc27f187 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -102,6 +102,9 @@ struct sdhci_arasan_data {
/* Controller does not have CD wired and will not function normally without */
#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
+/* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
+ * internal clock even when the clock isn't stable */
+#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
};
static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
@@ -207,6 +210,16 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
sdhci_set_clock(host, clock);
+ if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
+ /*
+ * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
+ * after enabling the clock even though the clock is not
+ * stable. Trying to use a clock without waiting here results
+ * in EILSEQ while detecting some older/slower cards. The
+ * chosen delay is the maximum delay from sdhci_set_clock.
+ */
+ msleep(20);
+
if (ctrl_phy) {
phy_power_on(sdhci_arasan->phy);
sdhci_arasan->is_phy_on = true;
@@ -758,6 +771,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
+ if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
+ sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
+
pltfm_host->clk = clk_xin;
if (of_device_is_compatible(pdev->dev.of_node,
--
2.11.0
^ permalink raw reply related
* [PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes misalignments
From: Radhey Shyam Pandey @ 2018-06-20 11:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620083653.17010-1-andrea.merello@gmail.com>
> -----Original Message-----
> From: dmaengine-owner at vger.kernel.org [mailto:dmaengine-
> owner at vger.kernel.org] On Behalf Of Andrea Merello
> Sent: Wednesday, June 20, 2018 2:07 PM
> To: vkoul at kernel.org; dan.j.williams at intel.com; Michal Simek
> <michals@xilinx.com>; Appana Durga Kedareswara Rao
> <appanad@xilinx.com>; dmaengine at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> Andrea Merello <andrea.merello@gmail.com>
> Subject: [PATCH 1/6] dmaengine: xilinx_dma: fix splitting transfer causes
> misalignments
We should rephrase commit message to something like "In axidma
slave_sg and dma_cylic mode align split descriptors"
>
> Whenever a single or cyclic transaction is prepared, the driver
> could eventually split it over several SG descriptors in order
> to deal with the HW maximum transfer length.
>
> This could end up in DMA operations starting from a misaligned
> address. This seems fatal for the HW.
This seems fatal for the HW if DRE is not enabled.
>
> This patch eventually adjusts the transfer size in order to make sure
> all operations start from an aligned address.
>
> Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
> ---
> drivers/dma/xilinx/xilinx_dma.c | 27 ++++++++++++++++++++-------
> 1 file changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 27b523530c4a..a516e7ffef21 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -376,6 +376,7 @@ struct xilinx_dma_chan {
> void (*start_transfer)(struct xilinx_dma_chan *chan);
> int (*stop_transfer)(struct xilinx_dma_chan *chan);
> u16 tdest;
> + u32 copy_mask;
We can reuse copy_align itself. See below.
> };
>
> /**
> @@ -1789,10 +1790,14 @@ static struct dma_async_tx_descriptor
> *xilinx_dma_prep_slave_sg(
>
> /*
> * Calculate the maximum number of bytes to transfer,
> - * making sure it is less than the hw limit
> + * making sure it is less than the hw limit and that
> + * the next chuck start address is aligned
/s/chuck/chunk
> */
> - copy = min_t(size_t, sg_dma_len(sg) - sg_used,
> - XILINX_DMA_MAX_TRANS_LEN);
> + copy = sg_dma_len(sg) - sg_used;
> + if (copy > XILINX_DMA_MAX_TRANS_LEN)
> + copy = XILINX_DMA_MAX_TRANS_LEN &
> + chan->copy_mask;
> +
In below implementation, we can reuse copy_align.
Same for dma_cyclic.
if ((copy + sg_used < sg_dma_len(sg)) &&
chan->xdev->common.copy_align) {
/* If this is not the last descriptor, make sure
* the next one will be properly aligned
*/
copy = rounddown(copy,
(1 << chan->xdev->common.copy_align));
}
> hw = &segment->hw;
>
> /* Fill in the descriptor */
> @@ -1894,10 +1899,14 @@ static struct dma_async_tx_descriptor
> *xilinx_dma_prep_dma_cyclic(
>
> /*
> * Calculate the maximum number of bytes to transfer,
> - * making sure it is less than the hw limit
> + * making sure it is less than the hw limit and that
> + * the next chuck start address is aligned
> */
> - copy = min_t(size_t, period_len - sg_used,
> - XILINX_DMA_MAX_TRANS_LEN);
> + copy = period_len - sg_used;
> + if (copy > XILINX_DMA_MAX_TRANS_LEN)
> + copy = XILINX_DMA_MAX_TRANS_LEN &
> + chan->copy_mask;
> +
> hw = &segment->hw;
> xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
> period_len * i);
> @@ -2402,8 +2411,12 @@ static int xilinx_dma_chan_probe(struct
> xilinx_dma_device *xdev,
> if (width > 8)
> has_dre = false;
>
> - if (!has_dre)
> + if (has_dre) {
> + chan->copy_mask = ~0;
> + } else {
> xdev->common.copy_align = fls(width - 1);
> + chan->copy_mask = ~(width - 1);
> + }
As mentioned above we don't need this additional field.
>
> if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
> of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
> --
> 2.17.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/2] arm64: avoid alloc memory on offline node
From: Punit Agrawal @ 2018-06-20 11:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <814205eb-ae86-a519-bed0-f09b8e2d3a02@huawei.com>
Xie XiuQi <xiexiuqi@huawei.com> writes:
> Hi Lorenzo, Punit,
>
>
> On 2018/6/20 0:32, Lorenzo Pieralisi wrote:
>> On Tue, Jun 19, 2018 at 04:35:40PM +0100, Punit Agrawal wrote:
>>> Michal Hocko <mhocko@kernel.org> writes:
>>>
>>>> On Tue 19-06-18 15:54:26, Punit Agrawal wrote:
>>>> [...]
>>>>> In terms of $SUBJECT, I wonder if it's worth taking the original patch
>>>>> as a temporary fix (it'll also be easier to backport) while we work on
>>>>> fixing these other issues and enabling memoryless nodes.
>>>>
>>>> Well, x86 already does that but copying this antipatern is not really
>>>> nice. So it is good as a quick fix but it would be definitely much
>>>> better to have a robust fix. Who knows how many other places might hit
>>>> this. You certainly do not want to add a hack like this all over...
>>>
>>> Completely agree! I was only suggesting it as a temporary measure,
>>> especially as it looked like a proper fix might be invasive.
>>>
>>> Another fix might be to change the node specific allocation to node
>>> agnostic allocations. It isn't clear why the allocation is being
>>> requested from a specific node. I think Lorenzo suggested this in one of
>>> the threads.
>>
>> I think that code was just copypasted but it is better to fix the
>> underlying issue.
>>
>>> I've started putting together a set fixing the issues identified in this
>>> thread. It should give a better idea on the best course of action.
>>
>> On ACPI ARM64, this diff should do if I read the code correctly, it
>> should be (famous last words) just a matter of mapping PXMs to nodes for
>> every SRAT GICC entry, feel free to pick it up if it works.
>>
>> Yes, we can take the original patch just because it is safer for an -rc
>> cycle even though if the patch below would do delaying the fix for a
>> couple of -rc (to get it tested across ACPI ARM64 NUMA platforms) is
>> not a disaster.
>
> I tested this patch on my arm board, it works.
I am assuming you tried the patch without enabling support for
memory-less nodes.
The patch de-couples the onlining of numa nodes (as parsed from SRAT)
from NR_CPUS restriction. When it comes to building zonelists, the node
referenced by the PCI controller also has zonelists initialised.
So it looks like a fallback node is setup even if we don't have
memory-less nodes enabled. I need to stare some more at the code to see
why we need memory-less nodes at all then ...
^ permalink raw reply
* [PATCH v5 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks
From: Thomas Gleixner @ 2018-06-20 11:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620111833.GE7737@piout.net>
On Wed, 20 Jun 2018, Alexandre Belloni wrote:
> On 20/06/2018 12:58:01+0200, Thomas Gleixner wrote:
> > > There are only a count up and count up then down modes. As the counter
> > > value is in a read only register, the only configurable starting value
> > > is 0 so it will always start by counting up. I'm pretty sure the up/down
> > > mode will not help us.
> >
> > Hmm, fair enough.
> >
> > Though the manual says:
> >
> > A trigger resets the counter and starts the counter clock. Three types
> > of triggers are common to both modes, and a fourth external trigger is
> > available to each mode.
> >
> > ...
> >
> > Software Trigger: Each channel has a software trigger, available by
> > setting SWTRG in TC_CCR.
> >
> > So the question is whether you can't do the following:
> >
> > stop_counter()
> > issue_sw_trigger() ---> resets the counter to zero
> > write_compare()
> > start_counter()
> >
> > So that should avoid all te mess with comparing to the free running counter
> > as long as you have two blocks of counters, but then one of them will be
> > 16bit only assumed that there are always 3 counter channels in the TC.
> >
> > Just a thought, but the code you have should work as well.
> >
>
> Ah yes, sure, I misunderstood your first comment then. the driver will
> register one or two clockevent devices, depending on the number of
> available channels.
>
> The first one is based on the clocksource counter and does the counter
> comparison you don't like. the second one uses its own channel in the
> way you describe (set RC, reset counter, start counter).
>
> This was necessary because some people are running out of TCB channels
> as they use the remaining ones as PWMs. But it is still better to use
> one channel as clocksource and clockevent that use the PIT.
Fair enough.
^ permalink raw reply
* [PATCH v5 0/8] Introduce on-chip interconnect API
From: Georgi Djakov @ 2018-06-20 12:11 UTC (permalink / raw)
To: linux-arm-kernel
Modern SoCs have multiple processors and various dedicated cores (video, gpu,
graphics, modem). These cores are talking to each other and can generate a
lot of data flowing through the on-chip interconnects. These interconnect
buses could form different topologies such as crossbar, point to point buses,
hierarchical buses or use the network-on-chip concept.
These buses have been sized usually to handle use cases with high data
throughput but it is not necessary all the time and consume a lot of power.
Furthermore, the priority between masters can vary depending on the running
use case like video playback or CPU intensive tasks.
Having an API to control the requirement of the system in terms of bandwidth
and QoS, so we can adapt the interconnect configuration to match those by
scaling the frequencies, setting link priority and tuning QoS parameters.
This configuration can be a static, one-time operation done at boot for some
platforms or a dynamic set of operations that happen at run-time.
This patchset introduce a new API to get the requirement and configure the
interconnect buses across the entire chipset to fit with the current demand.
The API is NOT for changing the performance of the endpoint devices, but only
the interconnect path in between them.
The API is using a consumer/provider-based model, where the providers are
the interconnect buses and the consumers could be various drivers.
The consumers request interconnect resources (path) to an endpoint and set
the desired constraints on this data flow path. The provider(s) receive
requests from consumers and aggregate these requests for all master-slave
pairs on that path. Then the providers configure each participating in the
topology node according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Below is a simplified diagram of a real-world SoC topology. The interconnect
providers are the NoCs.
+----------------+ +----------------+
| HW Accelerator |--->| M NoC |<---------------+
+----------------+ +----------------+ |
| | +------------+
+-----+ +-------------+ V +------+ | |
| DDR | | +--------+ | PCIe | | |
+-----+ | | Slaves | +------+ | |
^ ^ | +--------+ | | C NoC |
| | V V | |
+------------------+ +------------------------+ | | +-----+
| |-->| |-->| |-->| CPU |
| |-->| |<--| | +-----+
| Mem NoC | | S NoC | +------------+
| |<--| |---------+ |
| |<--| |<------+ | | +--------+
+------------------+ +------------------------+ | | +-->| Slaves |
^ ^ ^ ^ ^ | | +--------+
| | | | | | V
+------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
| CPUs | | | GPU | | DSP | | Masters |-->| P NoC |-->| Slaves |
+------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
|
+-------+
| Modem |
+-------+
TODO:
* Create icc_set_extended() to handle parameters such as latency and other
QoS values.
* Convert from using global node identifiers to local per provider ids.
* Cache the path between the nodes instead of walking the graph on each get().
* Sync interconnect requests with the idle state of the device.
Changes since patchset v4 (https://lkml.org/lkml/2018/3/9/856)
* Simplified locking by using a single global mutex. (Evan)
* Changed the aggregation function interface.
* Implemented functions for node, link, provider removal. (Evan)
* Naming changes on variables and functions, removed redundant code. (Evan)
* Fixes and clarifications in the docs. (Matthias, Evan, Amit, Alexandre)
* Removed mandatory reg DT property, made interconnect-names optional. (Bjorn)
* Made interconnect-cells property required to align with other bindings. (Neil)
* Moved msm8916 specific bindings into a separate file and patch. (Bjorn)
* Use the names, instead of the hardcoded ids for topology. (Matthias)
* Init the node before creating the links. (Evan)
* Added icc_units_to_bps macro. (Amit)
Changes since patchset v3 (https://lkml.org/lkml/2017/9/8/544)
* Refactored the constraints aggregation.
* Use the IDR API.
* Split the provider and consumer bindings into separate patches and propose
new bindings for consumers, which allows to specify the local source port.
* Adopted the icc_ prefix for API functions.
* Introduced separate API functions for creating interconnect nodes and links.
* Added DT lookup support in addition to platform data.
* Dropped the event tracing patch for now.
* Added a patch to provide summary via debugfs.
* Use macro for the list of topology definitions in the platform driver.
* Various minor changes.
Changes since patchset v2 (https://lkml.org/lkml/2017/7/20/825)
* Split the aggregation into per node and per provider. Cache the
aggregated values.
* Various small refactorings and cleanups in the framework.
* Added a patch introducing basic tracepoint support for monitoring
the time required to update the interconnect nodes.
Changes since patchset v1 (https://lkml.org/lkml/2017/6/27/890)
* Updates in the documentation.
* Changes in request aggregation, locking.
* Dropped the aggregate() callback and use the default as it currently
sufficient for the single vendor driver. Will add it later when needed.
* Dropped the dt-bindings draft patch for now.
Changes since RFC v2 (https://lkml.org/lkml/2017/6/12/316)
* Converted documentation to rst format.
* Fixed an incorrect call to mutex_lock. Renamed max_bw to peak_bw.
Changes since RFC v1 (https://lkml.org/lkml/2017/5/15/605)
* Refactored code into shorter functions.
* Added a new aggregate() API function.
* Rearranged some structs to reduce padding bytes.
Changes since RFC v0 (https://lkml.org/lkml/2017/3/1/599)
* Removed DT support and added optional Patch 3 with new bindings proposal.
* Converted the topology into internal driver data.
* Made the framework modular.
* interconnect_get() now takes (src and dst ports as arguments).
* Removed public declarations of some structs.
* Now passing prev/next nodes to the vendor driver.
* Properly remove requests on _put().
* Added refcounting.
* Updated documentation.
* Changed struct interconnect_path to use array instead of linked list.
Georgi Djakov (8):
interconnect: Add generic on-chip interconnect API
dt-bindings: Introduce interconnect provider bindings
interconnect: Add debugfs support
interconnect: qcom: Add RPM communication
dt-bindings: interconnect: Document qcom,msm8916 NoC bindings
interconnect: qcom: Add msm8916 interconnect provider driver
dt-bindings: Introduce interconnect consumers bindings
interconnect: Allow endpoints translation via DT
.../bindings/interconnect/interconnect.txt | 60 ++
.../bindings/interconnect/qcom-msm8916.txt | 39 +
.../bindings/interconnect/qcom-smd.txt | 32 +
Documentation/interconnect/interconnect.rst | 96 +++
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/interconnect/Kconfig | 15 +
drivers/interconnect/Makefile | 3 +
drivers/interconnect/core.c | 726 ++++++++++++++++++
drivers/interconnect/qcom/Kconfig | 11 +
drivers/interconnect/qcom/Makefile | 4 +
drivers/interconnect/qcom/msm8916.c | 495 ++++++++++++
drivers/interconnect/qcom/smd-rpm.c | 90 +++
drivers/interconnect/qcom/smd-rpm.h | 15 +
include/dt-bindings/interconnect/qcom.h | 350 +++++++++
include/linux/interconnect-provider.h | 127 +++
include/linux/interconnect.h | 49 ++
17 files changed, 2115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/interconnect.txt
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-smd.txt
create mode 100644 Documentation/interconnect/interconnect.rst
create mode 100644 drivers/interconnect/Kconfig
create mode 100644 drivers/interconnect/Makefile
create mode 100644 drivers/interconnect/core.c
create mode 100644 drivers/interconnect/qcom/Kconfig
create mode 100644 drivers/interconnect/qcom/Makefile
create mode 100644 drivers/interconnect/qcom/msm8916.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.h
create mode 100644 include/dt-bindings/interconnect/qcom.h
create mode 100644 include/linux/interconnect-provider.h
create mode 100644 include/linux/interconnect.h
^ permalink raw reply
* [PATCH v5 1/8] interconnect: Add generic on-chip interconnect API
From: Georgi Djakov @ 2018-06-20 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org>
This patch introduce a new API to get requirements and configure the
interconnect buses across the entire chipset to fit with the current
demand.
The API is using a consumer/provider-based model, where the providers are
the interconnect buses and the consumers could be various drivers.
The consumers request interconnect resources (path) between endpoints and
set the desired constraints on this data flow path. The providers receive
requests from consumers and aggregate these requests for all master-slave
pairs on that path. Then the providers configure each participating in the
topology node according to the requested data flow path, physical links and
constraints. The topology could be complicated and multi-tiered and is SoC
specific.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
Documentation/interconnect/interconnect.rst | 96 ++++
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/interconnect/Kconfig | 10 +
drivers/interconnect/Makefile | 2 +
drivers/interconnect/core.c | 586 ++++++++++++++++++++
include/linux/interconnect-provider.h | 127 +++++
include/linux/interconnect.h | 42 ++
8 files changed, 866 insertions(+)
create mode 100644 Documentation/interconnect/interconnect.rst
create mode 100644 drivers/interconnect/Kconfig
create mode 100644 drivers/interconnect/Makefile
create mode 100644 drivers/interconnect/core.c
create mode 100644 include/linux/interconnect-provider.h
create mode 100644 include/linux/interconnect.h
diff --git a/Documentation/interconnect/interconnect.rst b/Documentation/interconnect/interconnect.rst
new file mode 100644
index 000000000000..a1ebd83ad0a1
--- /dev/null
+++ b/Documentation/interconnect/interconnect.rst
@@ -0,0 +1,96 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================================
+GENERIC SYSTEM INTERCONNECT SUBSYSTEM
+=====================================
+
+Introduction
+------------
+
+This framework is designed to provide a standard kernel interface to control
+the settings of the interconnects on a SoC. These settings can be throughput,
+latency and priority between multiple interconnected devices or functional
+blocks. This can be controlled dynamically in order to save power or provide
+maximum performance.
+
+The interconnect bus is a hardware with configurable parameters, which can be
+set on a data path according to the requests received from various drivers.
+An example of interconnect buses are the interconnects between various
+components or functional blocks in chipsets. There can be multiple interconnects
+on a SoC that can be multi-tiered.
+
+Below is a simplified diagram of a real-world SoC interconnect bus topology.
+
+::
+
+ +----------------+ +----------------+
+ | HW Accelerator |--->| M NoC |<---------------+
+ +----------------+ +----------------+ |
+ | | +------------+
+ +-----+ +-------------+ V +------+ | |
+ | DDR | | +--------+ | PCIe | | |
+ +-----+ | | Slaves | +------+ | |
+ ^ ^ | +--------+ | | C NoC |
+ | | V V | |
+ +------------------+ +------------------------+ | | +-----+
+ | |-->| |-->| |-->| CPU |
+ | |-->| |<--| | +-----+
+ | Mem NoC | | S NoC | +------------+
+ | |<--| |---------+ |
+ | |<--| |<------+ | | +--------+
+ +------------------+ +------------------------+ | | +-->| Slaves |
+ ^ ^ ^ ^ ^ | | +--------+
+ | | | | | | V
+ +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
+ | CPUs | | | GPU | | DSP | | Masters |-->| P NoC |-->| Slaves |
+ +------+ | +-----+ +-----+ +---------+ +----------------+ +--------+
+ |
+ +-------+
+ | Modem |
+ +-------+
+
+Terminology
+-----------
+
+Interconnect provider is the software definition of the interconnect hardware.
+The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC
+and Mem NoC.
+
+Interconnect node is the software definition of the interconnect hardware
+port. Each interconnect provider consists of multiple interconnect nodes,
+which are connected to other SoC components including other interconnect
+providers. The point on the diagram where the CPUs connects to the memory is
+called an interconnect node, which belongs to the Mem NoC interconnect provider.
+
+Interconnect endpoints are the first or the last element of the path. Every
+endpoint is a node, but not every node is an endpoint.
+
+Interconnect path is everything between two endpoints including all the nodes
+that have to be traversed to reach from a source to destination node. It may
+include multiple master-slave pairs across several interconnect providers.
+
+Interconnect consumers are the entities which make use of the data paths exposed
+by the providers. The consumers send requests to providers requesting various
+throughput, latency and priority. Usually the consumers are device drivers, that
+send request based on their needs. An example for a consumer is a video decoder
+that supports various formats and image sizes.
+
+Interconnect providers
+----------------------
+
+Interconnect provider is an entity that implements methods to initialize and
+configure a interconnect bus hardware. The interconnect provider drivers should
+be registered with the interconnect provider core.
+
+The interconnect framework provider API functions are documented in
+.. kernel-doc:: include/linux/interconnect-provider.h
+
+Interconnect consumers
+----------------------
+
+Interconnect consumers are the clients which use the interconnect APIs to
+get paths between endpoints and set their bandwidth/latency/QoS requirements
+for these interconnect paths.
+
+The interconnect framework consumer API functions are documented in
+.. kernel-doc:: include/linux/interconnect.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9ccc08165..3ed6ede9d021 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -217,4 +217,6 @@ source "drivers/siox/Kconfig"
source "drivers/slimbus/Kconfig"
+source "drivers/interconnect/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 24cd47014657..0cca95740d9b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -185,3 +185,4 @@ obj-$(CONFIG_TEE) += tee/
obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
obj-$(CONFIG_SIOX) += siox/
+obj-$(CONFIG_INTERCONNECT) += interconnect/
diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
new file mode 100644
index 000000000000..a261c7d41deb
--- /dev/null
+++ b/drivers/interconnect/Kconfig
@@ -0,0 +1,10 @@
+menuconfig INTERCONNECT
+ tristate "On-Chip Interconnect management support"
+ help
+ Support for management of the on-chip interconnects.
+
+ This framework is designed to provide a generic interface for
+ managing the interconnects in a SoC.
+
+ If unsure, say no.
+
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
new file mode 100644
index 000000000000..97fca2e09d24
--- /dev/null
+++ b/drivers/interconnect/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_INTERCONNECT) += core.o
diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c
new file mode 100644
index 000000000000..e7f96fc6722e
--- /dev/null
+++ b/drivers/interconnect/core.c
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Interconnect framework core driver
+ *
+ * Copyright (c) 2018, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/device.h>
+#include <linux/idr.h>
+#include <linux/init.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+static DEFINE_IDR(icc_idr);
+static LIST_HEAD(icc_provider_list);
+static DEFINE_MUTEX(icc_lock);
+
+/**
+ * struct icc_req - constraints that are attached to each node
+ *
+ * @req_node: entry in list of requests for the particular @node
+ * @node: the interconnect node to which this constraint applies
+ * @dev: reference to the device that sets the constraints
+ * @avg_bw: an integer describing the average bandwidth in kbps
+ * @peak_bw: an integer describing the peak bandwidth in kbps
+ */
+struct icc_req {
+ struct hlist_node req_node;
+ struct icc_node *node;
+ struct device *dev;
+ u32 avg_bw;
+ u32 peak_bw;
+};
+
+/**
+ * struct icc_path - interconnect path structure
+ * @num_nodes: number of hops (nodes)
+ * @reqs: array of the requests applicable to this path of nodes
+ */
+struct icc_path {
+ size_t num_nodes;
+ struct icc_req reqs[0];
+};
+
+static struct icc_node *node_find(const int id)
+{
+ struct icc_node *node;
+
+ mutex_lock(&icc_lock);
+ node = idr_find(&icc_idr, id);
+ mutex_unlock(&icc_lock);
+
+ return node;
+}
+
+static struct icc_path *path_allocate(struct icc_node *dst, ssize_t num_nodes)
+{
+ struct icc_node *node = dst;
+ struct icc_path *path;
+ size_t i;
+
+ path = kzalloc(sizeof(*path) + num_nodes * sizeof(*path->reqs),
+ GFP_KERNEL);
+ if (!path)
+ return ERR_PTR(-ENOMEM);
+
+ path->num_nodes = num_nodes;
+
+ for (i = 0; i < num_nodes; i++) {
+ hlist_add_head(&path->reqs[i].req_node, &node->req_list);
+
+ path->reqs[i].node = node;
+ /* reference to previous node was saved during path traversal */
+ node = node->reverse;
+ }
+
+ return path;
+}
+
+static struct icc_path *path_find(struct device *dev, struct icc_node *src,
+ struct icc_node *dst)
+{
+ struct icc_node *n, *node = NULL;
+ struct icc_provider *provider;
+ struct list_head traverse_list;
+ struct list_head edge_list;
+ struct list_head visited_list;
+ size_t i, depth = 0;
+ bool found = false;
+ int ret = -EPROBE_DEFER;
+
+ INIT_LIST_HEAD(&traverse_list);
+ INIT_LIST_HEAD(&edge_list);
+ INIT_LIST_HEAD(&visited_list);
+
+ list_add_tail(&src->search_list, &traverse_list);
+ src->reverse = NULL;
+
+ do {
+ list_for_each_entry_safe(node, n, &traverse_list, search_list) {
+ if (node == dst) {
+ found = true;
+ list_add(&node->search_list, &visited_list);
+ break;
+ }
+ for (i = 0; i < node->num_links; i++) {
+ struct icc_node *tmp = node->links[i];
+
+ if (!tmp) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ if (tmp->is_traversed)
+ continue;
+
+ tmp->is_traversed = true;
+ tmp->reverse = node;
+ list_add(&tmp->search_list, &edge_list);
+ }
+ }
+ if (found)
+ break;
+
+ list_splice_init(&traverse_list, &visited_list);
+ list_splice_init(&edge_list, &traverse_list);
+
+ /* count the hops away from the source */
+ depth++;
+
+ } while (!list_empty(&traverse_list));
+
+out:
+ /* reset the traversed state */
+ list_for_each_entry(provider, &icc_provider_list, provider_list) {
+ list_for_each_entry(n, &provider->nodes, node_list)
+ if (n->is_traversed)
+ n->is_traversed = false;
+ }
+
+ if (found) {
+ struct icc_path *path = path_allocate(dst, depth);
+
+ if (IS_ERR(path))
+ return path;
+
+ /* initialize the path */
+ for (i = 0; i < path->num_nodes; i++) {
+ node = path->reqs[i].node;
+ path->reqs[i].dev = dev;
+ node->provider->users++;
+ }
+ return path;
+ }
+
+ return ERR_PTR(ret);
+}
+
+/*
+ * We want the path to honor all bandwidth requests, so the average
+ * bandwidth requirements from each consumer are aggregated at each node
+ * and provider level. By default the average bandwidth is the sum of all
+ * averages and the peak will be the highest of all peak bandwidth requests.
+ */
+
+static int aggregate_requests(struct icc_node *node)
+{
+ struct icc_provider *p = node->provider;
+ struct icc_req *r;
+
+ node->avg_bw = 0;
+ node->peak_bw = 0;
+
+ hlist_for_each_entry(r, &node->req_list, req_node)
+ p->aggregate(node, r->avg_bw, r->peak_bw,
+ &node->avg_bw, &node->peak_bw);
+
+ return 0;
+}
+
+static void aggregate_provider(struct icc_provider *p)
+{
+ struct icc_node *n;
+
+ p->avg_bw = 0;
+ p->peak_bw = 0;
+
+ list_for_each_entry(n, &p->nodes, node_list)
+ p->aggregate(n, n->avg_bw, n->peak_bw,
+ &p->avg_bw, &p->peak_bw);
+}
+
+static int apply_constraints(struct icc_path *path)
+{
+ struct icc_node *next, *prev = NULL;
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < path->num_nodes; i++, prev = next) {
+ struct icc_provider *p;
+
+ next = path->reqs[i].node;
+ /*
+ * Both endpoints should be valid master-slave pairs of the
+ * same interconnect provider that will be configured.
+ */
+ if (!prev || next->provider != prev->provider)
+ continue;
+
+ p = next->provider;
+
+ aggregate_provider(p);
+
+ if (p->set) {
+ /* set the constraints */
+ ret = p->set(prev, next, p->avg_bw, p->peak_bw);
+ }
+
+ if (ret)
+ goto out;
+ }
+out:
+ return ret;
+}
+
+/**
+ * icc_set() - set constraints on an interconnect path between two endpoints
+ * @path: reference to the path returned by icc_get()
+ * @avg_bw: average bandwidth in kbps
+ * @peak_bw: peak bandwidth in kbps
+ *
+ * This function is used by an interconnect consumer to express its own needs
+ * in terms of bandwidth for a previously requested path between two endpoints.
+ * The requests are aggregated and each node is updated accordingly. The entire
+ * path is locked by a mutex to ensure that the set() is completed.
+ * The @path can be NULL when the "interconnects" DT properties is missing,
+ * which will mean that no constraints will be set.
+ *
+ * Returns 0 on success, or an appropriate error code otherwise.
+ */
+int icc_set(struct icc_path *path, u32 avg_bw, u32 peak_bw)
+{
+ struct icc_node *node;
+ struct icc_provider *p;
+ size_t i;
+ int ret = 0;
+
+ if (!path)
+ return 0;
+
+ mutex_lock(&icc_lock);
+
+ for (i = 0; i < path->num_nodes; i++) {
+ node = path->reqs[i].node;
+ p = node->provider;
+
+ /* update the consumer request for this path */
+ path->reqs[i].avg_bw = avg_bw;
+ path->reqs[i].peak_bw = peak_bw;
+
+ /* aggregate requests for this node */
+ aggregate_requests(node);
+ }
+
+ ret = apply_constraints(path);
+ if (ret)
+ pr_err("interconnect: error applying constraints (%d)", ret);
+
+ mutex_unlock(&icc_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(icc_set);
+
+/**
+ * icc_get() - return a handle for path between two endpoints
+ * @dev: the device requesting the path
+ * @src_id: source device port id
+ * @dst_id: destination device port id
+ *
+ * This function will search for a path between two endpoints and return an
+ * icc_path handle on success. Use icc_put() to release
+ * constraints when the they are not needed anymore.
+ *
+ * Return: icc_path pointer on success, or ERR_PTR() on error
+ */
+struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id)
+{
+ struct icc_node *src, *dst;
+ struct icc_path *path = ERR_PTR(-EPROBE_DEFER);
+
+ src = node_find(src_id);
+ if (!src) {
+ dev_err(dev, "%s: invalid src=%d\n", __func__, src_id);
+ goto out;
+ }
+
+ dst = node_find(dst_id);
+ if (!dst) {
+ dev_err(dev, "%s: invalid dst=%d\n", __func__, dst_id);
+ goto out;
+ }
+
+ mutex_lock(&icc_lock);
+ path = path_find(dev, src, dst);
+ mutex_unlock(&icc_lock);
+ if (IS_ERR(path)) {
+ dev_err(dev, "%s: invalid path=%ld\n", __func__, PTR_ERR(path));
+ goto out;
+ }
+
+out:
+ return path;
+}
+EXPORT_SYMBOL_GPL(icc_get);
+
+/**
+ * icc_put() - release the reference to the icc_path
+ * @path: interconnect path
+ *
+ * Use this function to release the constraints on a path when the path is
+ * no longer needed. The constraints will be re-aggregated.
+ */
+void icc_put(struct icc_path *path)
+{
+ struct icc_node *node;
+ size_t i;
+ int ret;
+
+ if (!path || WARN_ON_ONCE(IS_ERR(path)))
+ return;
+
+ ret = icc_set(path, 0, 0);
+ if (ret)
+ pr_err("%s: error (%d)\n", __func__, ret);
+
+ mutex_lock(&icc_lock);
+ for (i = 0; i < path->num_nodes; i++) {
+ node = path->reqs[i].node;
+ hlist_del(&path->reqs[i].req_node);
+
+ node->provider->users--;
+ }
+ mutex_unlock(&icc_lock);
+
+ kfree(path);
+}
+EXPORT_SYMBOL_GPL(icc_put);
+
+/**
+ * icc_node_create() - create a node
+ * @id: node id
+ *
+ * Return: icc_node pointer on success, or ERR_PTR() on error
+ */
+struct icc_node *icc_node_create(int id)
+{
+ struct icc_node *node;
+
+ /* check if node already exists */
+ node = node_find(id);
+ if (node)
+ goto out;
+
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
+ if (!node) {
+ node = ERR_PTR(-ENOMEM);
+ goto out;
+ }
+
+ mutex_lock(&icc_lock);
+
+ id = idr_alloc(&icc_idr, node, id, id + 1, GFP_KERNEL);
+ if (WARN(id < 0, "couldn't get idr")) {
+ node = ERR_PTR(id);
+ goto out;
+ }
+
+ node->id = id;
+
+out:
+ mutex_unlock(&icc_lock);
+
+ return node;
+}
+EXPORT_SYMBOL_GPL(icc_node_create);
+
+/**
+ * icc_node_remove() - remove a node
+ * @id: node id
+ *
+ */
+void icc_node_remove(int id)
+{
+ struct icc_node *node;
+
+ node = node_find(id);
+ if (node) {
+ mutex_lock(&icc_lock);
+ idr_remove(&icc_idr, node->id);
+ mutex_unlock(&icc_lock);
+ }
+
+ kfree(node);
+}
+EXPORT_SYMBOL_GPL(icc_node_remove);
+
+/**
+ * icc_link_create() - create a link between two nodes
+ * @src_id: source node id
+ * @dst_id: destination node id
+ *
+ * Create a link between two nodes. The nodes might belong to different
+ * interconnect providers and the @dst_id node might not exist (if the
+ * provider driver has not probed yet). So just create the @dst_id node
+ * and when the actual provider driver is probed, the rest of the node
+ * data is filled.
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_link_create(struct icc_node *node, const int dst_id)
+{
+ struct icc_node *dst;
+ struct icc_node **new;
+ int ret = 0;
+
+ if (!node->provider)
+ return -EINVAL;
+
+ dst = node_find(dst_id);
+ if (!dst) {
+ dst = icc_node_create(dst_id);
+
+ if (IS_ERR(dst)) {
+ ret = PTR_ERR(dst);
+ goto out;
+ }
+ }
+
+ mutex_lock(&icc_lock);
+
+ new = krealloc(node->links,
+ (node->num_links + 1) * sizeof(*node->links),
+ GFP_KERNEL);
+ if (!new) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ node->links = new;
+ node->links[node->num_links++] = dst;
+
+out:
+ mutex_unlock(&icc_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(icc_link_create);
+
+/**
+ * icc_link_remove() - remove a link between two nodes
+ * @src: pointer to source node
+ * @dst: pointer to destination node
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_link_remove(struct icc_node *src, struct icc_node *dst)
+{
+ struct icc_node **new;
+ int ret = 0;
+ int i, j;
+
+ if (IS_ERR_OR_NULL(src))
+ return PTR_ERR(src);
+
+ if (IS_ERR_OR_NULL(dst))
+ return PTR_ERR(dst);
+
+ mutex_lock(&icc_lock);
+
+ new = krealloc(src->links,
+ (src->num_links - 1) * sizeof(*src->links),
+ GFP_KERNEL);
+ if (!new) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ for (i = 0, j = 0; j < src->num_links; j++) {
+ if (src->links[j] == dst)
+ continue;
+
+ new[i++] = src->links[j];
+ }
+
+ src->links = new;
+ src->num_links--;
+
+out:
+ mutex_unlock(&icc_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(icc_link_remove);
+
+/**
+ * icc_node_add() - add an interconnect node to interconnect provider
+ * @node: pointer to the interconnect node
+ * @provider: pointer to the interconnect provider
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_node_add(struct icc_node *node, struct icc_provider *provider)
+{
+ mutex_lock(&icc_lock);
+
+ node->provider = provider;
+ list_add(&node->node_list, &provider->nodes);
+
+ mutex_unlock(&icc_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(icc_node_add);
+
+/**
+ * icc_provider_add() - add a new interconnect provider
+ * @icc_provider: the interconnect provider that will be added into topology
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_provider_add(struct icc_provider *provider)
+{
+ if (WARN_ON(!provider->set))
+ return -EINVAL;
+
+ mutex_init(&icc_lock);
+
+ INIT_LIST_HEAD(&provider->nodes);
+ list_add(&provider->provider_list, &icc_provider_list);
+
+ mutex_unlock(&icc_lock);
+
+ dev_dbg(provider->dev, "interconnect provider added to topology\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(icc_provider_add);
+
+/**
+ * icc_provider_del() - delete previously added interconnect provider
+ * @icc_provider: the interconnect provider that will be removed from topology
+ *
+ * Return: 0 on success, or an error code otherwise
+ */
+int icc_provider_del(struct icc_provider *provider)
+{
+ mutex_lock(&icc_lock);
+ if (provider->users) {
+ pr_warn("interconnect provider still has %d users\n",
+ provider->users);
+ mutex_unlock(&icc_lock);
+ return -EBUSY;
+ }
+
+ if (!list_empty_careful(&provider->nodes)) {
+ pr_warn("interconnect provider still has nodes\n");
+ mutex_unlock(&icc_lock);
+ return -EEXIST;
+ }
+
+ list_del(&provider->provider_list);
+ mutex_unlock(&icc_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(icc_provider_del);
+
+MODULE_AUTHOR("Georgi Djakov <georgi.djakov at linaro.org");
+MODULE_DESCRIPTION("Interconnect Driver Core");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/interconnect-provider.h b/include/linux/interconnect-provider.h
new file mode 100644
index 000000000000..f4613c6dce4f
--- /dev/null
+++ b/include/linux/interconnect-provider.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef _LINUX_INTERCONNECT_PROVIDER_H
+#define _LINUX_INTERCONNECT_PROVIDER_H
+
+#include <linux/interconnect.h>
+
+#define icc_units_to_bps(bw) ((bw) * 1000ULL)
+
+struct icc_node;
+
+/**
+ * struct icc_provider - interconnect provider (controller) entity that might
+ * provide multiple interconnect controls
+ *
+ * @provider_list: list of the registered interconnect providers
+ * @nodes: internal list of the interconnect provider nodes
+ * @set: pointer to device specific set operation function
+ * @aggregate: pointer to device specific aggregate operation function
+ * @dev: the device this interconnect provider belongs to
+ * @users: count of active users
+ * @avg_bw: aggregated value of average bandwidth requests from all nodes
+ * @peak_bw: aggregated value of peak bandwidth requests from all nodes
+ * @data: pointer to private data
+ */
+struct icc_provider {
+ struct list_head provider_list;
+ struct list_head nodes;
+ int (*set)(struct icc_node *src, struct icc_node *dst,
+ u32 avg_bw, u32 peak_bw);
+ int (*aggregate)(struct icc_node *node, u32 avg_bw, u32 peak_bw,
+ u32 *agg_avg, u32 *agg_peak);
+ struct device *dev;
+ int users;
+ u32 avg_bw;
+ u32 peak_bw;
+ void *data;
+};
+
+/**
+ * struct icc_node - entity that is part of the interconnect topology
+ *
+ * @id: platform specific node id
+ * @name: node name used in debugfs
+ * @links: a list of targets pointing to where we can go next when traversing
+ * @num_links: number of links to other interconnect nodes
+ * @provider: points to the interconnect provider of this node
+ * @node_list: the list entry in the parent provider's "nodes" list
+ * @search_list: list used when walking the nodes graph
+ * @reverse: pointer to previous node when walking the nodes graph
+ * @is_traversed: flag that is used when walking the nodes graph
+ * @req_list: a list of QoS constraint requests associated with this node
+ * @avg_bw: aggregated value of average bandwidth requests from all consumers
+ * @peak_bw: aggregated value of peak bandwidth requests from all consumers
+ * @data: pointer to private data
+ */
+struct icc_node {
+ int id;
+ const char *name;
+ struct icc_node **links;
+ size_t num_links;
+
+ struct icc_provider *provider;
+ struct list_head node_list;
+ struct list_head orphan_list;
+ struct list_head search_list;
+ struct icc_node *reverse;
+ bool is_traversed;
+ struct hlist_head req_list;
+ u32 avg_bw;
+ u32 peak_bw;
+ void *data;
+};
+
+#if IS_ENABLED(CONFIG_INTERCONNECT)
+
+struct icc_node *icc_node_create(int id);
+void icc_node_remove(int id);
+int icc_link_create(struct icc_node *node, const int dst_id);
+int icc_link_remove(struct icc_node *src, struct icc_node *dst);
+int icc_node_add(struct icc_node *node, struct icc_provider *provider);
+int icc_provider_add(struct icc_provider *provider);
+int icc_provider_del(struct icc_provider *provider);
+
+#else
+
+static inline struct icc_node *icc_node_create(int id)
+{
+ return ERR_PTR(-ENOTSUPP);
+}
+
+void icc_node_remove(int id)
+{
+}
+
+static inline int icc_link_create(struct icc_node *node, const int dst_id)
+{
+ return -ENOTSUPP;
+}
+
+int icc_link_remove(struct icc_node *src, struct icc_node *dst)
+{
+ return -ENOTSUPP;
+}
+
+int icc_node_add(struct icc_node *node, struct icc_provider *provider)
+{
+ return -ENOTSUPP;
+}
+
+static inline int icc_provider_add(struct icc_provider *provider)
+{
+ return -ENOTSUPP;
+}
+
+static inline int icc_provider_del(struct icc_provider *provider)
+{
+ return -ENOTSUPP;
+}
+
+#endif /* CONFIG_INTERCONNECT */
+
+#endif /* _LINUX_INTERCONNECT_PROVIDER_H */
diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h
new file mode 100644
index 000000000000..593215371fd6
--- /dev/null
+++ b/include/linux/interconnect.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef _LINUX_INTERCONNECT_H
+#define _LINUX_INTERCONNECT_H
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+struct icc_path;
+struct device;
+
+#if IS_ENABLED(CONFIG_INTERCONNECT)
+
+struct icc_path *icc_get(struct device *dev, const int src_id,
+ const int dst_id);
+void icc_put(struct icc_path *path);
+int icc_set(struct icc_path *path, u32 avg_bw, u32 peak_bw);
+
+#else
+
+static inline struct icc_path *icc_get(struct device *dev, const int src_id,
+ const int dst_id)
+{
+ return NULL;
+}
+
+static inline void icc_put(struct icc_path *path)
+{
+}
+
+static inline int icc_set(struct icc_path *path, u32 avg_bw, u32 peak_bw)
+{
+ return 0;
+}
+
+#endif /* CONFIG_INTERCONNECT */
+
+#endif /* _LINUX_INTERCONNECT_H */
^ permalink raw reply related
* [PATCH v5 2/8] dt-bindings: Introduce interconnect provider bindings
From: Georgi Djakov @ 2018-06-20 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org>
This binding is intended to represent the interconnect hardware present
in some of the modern SoCs. Currently it consists only of a binding for
the interconnect hardware devices (provider).
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
.../bindings/interconnect/interconnect.txt | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/interconnect.txt
diff --git a/Documentation/devicetree/bindings/interconnect/interconnect.txt b/Documentation/devicetree/bindings/interconnect/interconnect.txt
new file mode 100644
index 000000000000..6e2b2971b094
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/interconnect.txt
@@ -0,0 +1,33 @@
+Interconnect Provider Device Tree Bindings
+=========================================
+
+The purpose of this document is to define a common set of generic interconnect
+providers/consumers properties.
+
+
+= interconnect providers =
+
+The interconnect provider binding is intended to represent the interconnect
+controllers in the system. Each provider registers a set of interconnect
+nodes, which expose the interconnect related capabilities of the interconnect
+to consumer drivers. These capabilities can be throughput, latency, priority
+etc. The consumer drivers set constraints on interconnect path (or endpoints)
+depending on the use case. Interconnect providers can also be interconnect
+consumers, such as in the case where two network-on-chip fabrics interface
+directly
+
+Required properties:
+- compatible : contains the interconnect provider compatible string
+- #interconnect-cells : number of cells in a interconnect specifier needed to
+ encode the interconnect node id
+
+Example:
+
+ snoc: snoc at 580000 {
+ compatible = "qcom,msm8916-snoc";
+ #interconnect-cells = <1>;
+ reg = <0x580000 0x14000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
^ permalink raw reply related
* [PATCH v5 3/8] interconnect: Add debugfs support
From: Georgi Djakov @ 2018-06-20 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org>
Add a functionality to provide information about the current constraints
per each node and provider.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/interconnect/core.c | 78 +++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c
index e7f96fc6722e..dafc001ce758 100644
--- a/drivers/interconnect/core.c
+++ b/drivers/interconnect/core.c
@@ -6,6 +6,7 @@
* Author: Georgi Djakov <georgi.djakov@linaro.org>
*/
+#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/idr.h>
#include <linux/init.h>
@@ -15,10 +16,12 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/slab.h>
+#include <linux/uaccess.h>
static DEFINE_IDR(icc_idr);
static LIST_HEAD(icc_provider_list);
static DEFINE_MUTEX(icc_lock);
+static struct dentry *icc_debugfs_dir;
/**
* struct icc_req - constraints that are attached to each node
@@ -47,6 +50,81 @@ struct icc_path {
struct icc_req reqs[0];
};
+#ifdef CONFIG_DEBUG_FS
+
+static void icc_summary_show_one(struct seq_file *s, struct icc_node *n)
+{
+ if (!n)
+ return;
+
+ seq_printf(s, "%-30s %12d %12d\n",
+ n->name, n->avg_bw, n->peak_bw);
+}
+
+static int icc_summary_show(struct seq_file *s, void *data)
+{
+ struct icc_provider *provider;
+
+ seq_puts(s, " node avg peak\n");
+ seq_puts(s, "--------------------------------------------------------\n");
+
+ mutex_lock(&icc_lock);
+
+ list_for_each_entry(provider, &icc_provider_list, provider_list) {
+ struct icc_node *n;
+
+ list_for_each_entry(n, &provider->nodes, node_list) {
+ struct icc_req *r;
+
+ icc_summary_show_one(s, n);
+ hlist_for_each_entry(r, &n->req_list, req_node) {
+ if (!r->dev)
+ continue;
+
+ seq_printf(s, " %-26s %12d %12d\n",
+ dev_name(r->dev), r->avg_bw,
+ r->peak_bw);
+ }
+ }
+ }
+
+ mutex_unlock(&icc_lock);
+
+ return 0;
+}
+
+static int icc_summary_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, icc_summary_show, inode->i_private);
+}
+
+static const struct file_operations icc_summary_fops = {
+ .open = icc_summary_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int __init icc_debugfs_init(void)
+{
+ struct dentry *file;
+
+ icc_debugfs_dir = debugfs_create_dir("interconnect", NULL);
+ if (!icc_debugfs_dir) {
+ pr_err("interconnect: error creating debugfs directory\n");
+ return -ENODEV;
+ }
+
+ file = debugfs_create_file("interconnect_summary", 0444,
+ icc_debugfs_dir, NULL, &icc_summary_fops);
+ if (!file)
+ return -ENODEV;
+
+ return 0;
+}
+late_initcall(icc_debugfs_init);
+#endif
+
static struct icc_node *node_find(const int id)
{
struct icc_node *node;
^ permalink raw reply related
* [PATCH v5 4/8] interconnect: qcom: Add RPM communication
From: Georgi Djakov @ 2018-06-20 12:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org>
On some Qualcomm SoCs, there is a remote processor, which controls some of
the Network-On-Chip interconnect resources. Other CPUs express their needs
by communicating with this processor. Add a driver to handle comminication
with this remote processor.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
.../bindings/interconnect/qcom-smd.txt | 32 +++++++
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/smd-rpm.c | 90 +++++++++++++++++++
drivers/interconnect/qcom/smd-rpm.h | 15 ++++
4 files changed, 139 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-smd.txt
create mode 100644 drivers/interconnect/qcom/Makefile
create mode 100644 drivers/interconnect/qcom/smd-rpm.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom-smd.txt b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt
new file mode 100644
index 000000000000..88a5aeb50935
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt
@@ -0,0 +1,32 @@
+Qualcomm SMD-RPM interconnect driver binding
+------------------------------------------------
+The RPM (Resource Power Manager) is a dedicated hardware engine
+for managing the shared SoC resources in order to keep the lowest
+power profile. It communicates with other hardware subsystems via
+the shared memory driver (SMD) back-end and accepts requests for
+various resources.
+
+Required properties :
+- compatible : shall contain only one of the following:
+ "qcom,interconnect-smd-rpm"
+
+Example:
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <0 168 1>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8916";
+ qcom,smd-channels = "rpm_requests";
+
+ interconnect-smd-rpm {
+ compatible = "qcom,interconnect-smd-rpm";
+ };
+
+ };
+ };
+ };
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
new file mode 100644
index 000000000000..2a0c41db91c4
--- /dev/null
+++ b/drivers/interconnect/qcom/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += smd-rpm.o
diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
new file mode 100644
index 000000000000..0cf772f51642
--- /dev/null
+++ b/drivers/interconnect/qcom/smd-rpm.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RPM over SMD communication wrapper for interconects
+ *
+ * Copyright (C) 2018 Linaro Ltd
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/soc/qcom/smd-rpm.h>
+#include "smd-rpm.h"
+
+#define RPM_KEY_BW 0x00007762
+
+static struct qcom_icc_rpm {
+ struct qcom_smd_rpm *rpm;
+} icc_rpm_smd;
+
+struct icc_rpm_smd_req {
+ __le32 key;
+ __le32 nbytes;
+ __le32 value;
+};
+
+bool qcom_icc_rpm_smd_available(void)
+{
+ if (!icc_rpm_smd.rpm)
+ return false;
+
+ return true;
+}
+
+int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
+{
+ struct icc_rpm_smd_req req = {
+ .key = cpu_to_le32(RPM_KEY_BW),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(val),
+ };
+
+ return qcom_rpm_smd_write(icc_rpm_smd.rpm, ctx, rsc_type, id, &req,
+ sizeof(req));
+}
+EXPORT_SYMBOL(qcom_icc_rpm_smd_send);
+
+static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
+{
+ icc_rpm_smd.rpm = dev_get_drvdata(pdev->dev.parent);
+ if (!icc_rpm_smd.rpm) {
+ dev_err(&pdev->dev, "unable to retrieve handle to RPM\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id qcom_icc_rpm_smd_dt_match[] = {
+ { .compatible = "qcom,interconnect-smd-rpm", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, qcom_interconnect_rpm_smd_dt_match);
+
+static struct platform_driver qcom_interconnect_rpm_smd_driver = {
+ .driver = {
+ .name = "qcom-interconnect-smd-rpm",
+ .of_match_table = qcom_icc_rpm_smd_dt_match,
+ },
+ .probe = qcom_icc_rpm_smd_probe,
+};
+
+static int __init rpm_smd_interconnect_init(void)
+{
+ return platform_driver_register(&qcom_interconnect_rpm_smd_driver);
+}
+subsys_initcall(rpm_smd_interconnect_init);
+
+static void __exit rpm_smd_interconnect_exit(void)
+{
+ platform_driver_unregister(&qcom_interconnect_rpm_smd_driver);
+}
+module_exit(rpm_smd_interconnect_exit)
+
+MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
+MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h
new file mode 100644
index 000000000000..0f4a3da31cf6
--- /dev/null
+++ b/drivers/interconnect/qcom/smd-rpm.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __LINUX_INTERCONNECT_QCOM_RPM_H
+#define __LINUX_INTERCONNECT_QCOM_RPM_H
+
+#include <linux/soc/qcom/smd-rpm.h>
+
+bool qcom_icc_rpm_smd_available(void);
+int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
+
+#endif
^ permalink raw reply related
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