* [PATCH v3 2/2] drm/rockchip: Support 10 bits yuv format in vop
From: Randy Li @ 2018-06-21 16:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180621164737.23611-1-ayaka@soulik.info>
The rockchip use fully packed pixel format variants
for YUV 10bits.
This patch only make the VOP accept this pixel format,
but it doesn't add the converting data path for
the color gamuts that the target display are supported.
Signed-off-by: Randy Li <ayaka@soulik.info>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 27 +++++++++++++++++++++++++--
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 2121345a61af..6a54b20501ac 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -232,6 +232,7 @@ static enum vop_data_format vop_convert_format(uint32_t format)
case DRM_FORMAT_BGR565:
return VOP_FMT_RGB565;
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV12_10LE40:
return VOP_FMT_YUV420SP;
case DRM_FORMAT_NV16:
return VOP_FMT_YUV422SP;
@@ -249,6 +250,17 @@ static bool is_yuv_support(uint32_t format)
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV12_10LE40:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_yuv_10bit(uint32_t format)
+{
+ switch (format) {
+ case DRM_FORMAT_NV12_10LE40:
return true;
default:
return false;
@@ -711,6 +723,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
dma_addr_t dma_addr;
uint32_t val;
bool rb_swap;
+ bool is_10_bits = false;
int win_index = VOP_WIN_TO_INDEX(vop_win);
int format;
@@ -728,6 +741,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
return;
}
+ is_10_bits = is_yuv_10bit(fb->format->format);
+
obj = rockchip_fb_get_gem_obj(fb, 0);
rk_obj = to_rockchip_obj(obj);
@@ -742,7 +757,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
- offset = (src->x1 >> 16) * fb->format->cpp[0];
+ if (is_10_bits)
+ offset = (src->x1 >> 16) * (fb->format->cpp[0] * 5 / 4);
+ else
+ offset = (src->x1 >> 16) * fb->format->cpp[0];
+
offset += (src->y1 >> 16) * fb->pitches[0];
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
@@ -753,6 +772,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
VOP_WIN_SET(vop, win, format, format);
VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
+ VOP_WIN_SET(vop, win, fmt_10, is_10_bits);
if (is_yuv_support(fb->format->format)) {
int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
@@ -761,7 +781,10 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
uv_obj = rockchip_fb_get_gem_obj(fb, 1);
rk_uv_obj = to_rockchip_obj(uv_obj);
- offset = (src->x1 >> 16) * bpp / hsub;
+ if (is_10_bits)
+ offset = (src->x1 >> 16) * (bpp * 5 / 4) / hsub;
+ else
+ offset = (src->x1 >> 16) * bpp / hsub;
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 084acdd0019a..d9ec993f420a 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -131,6 +131,7 @@ struct vop_win_phy {
struct vop_reg enable;
struct vop_reg gate;
struct vop_reg format;
+ struct vop_reg fmt_10;
struct vop_reg rb_swap;
struct vop_reg act_info;
struct vop_reg dsp_info;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 08023d3ecb76..5393886ddd95 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -50,6 +50,7 @@ static const uint32_t formats_win_full[] = {
DRM_FORMAT_NV12,
DRM_FORMAT_NV16,
DRM_FORMAT_NV24,
+ DRM_FORMAT_NV12_10LE40,
};
static const uint32_t formats_win_lite[] = {
@@ -215,6 +216,7 @@ static const struct vop_win_phy rk3288_win01_data = {
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
--
2.14.4
^ permalink raw reply related
* [PATCH] ARM: ftrace: Only set kernel memory back to read-only after boot
From: Steven Rostedt @ 2018-06-21 16:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180621124710.453ee0ae@gandalf.local.home>
On Thu, 21 Jun 2018 12:47:10 -0400
Steven Rostedt <rostedt@goodmis.org> wrote:
> From: Steven Rostedt (VMware) <rostedt@goodmis.org>
>
> Dynamic ftrace requires modifying the code segments that are usually
> set to read-only. To do this, a per arch function is called both before
> and after the ftrace modifications are performed. The "before" function
> will set kernel code text to read-write to allow for ftrace to make the
> modifications, and the "after" function will set the kernel code text
> back to "read-only" to keep the kernel code text protected.
>
> The issue happens when dynamic ftrace is tested at boot up. The test is
> done before the kernel code text has been set to read-only. But the
> "before" and "after" calls are still performed. The "after" call will
> change the kernel code text to read-only prematurely, and other boot
> code that expects this code to be read-write will fail.
>
> The solution is to add a variable that is set when the kernel code text
> is expected to be converted to read-only, and make the ftrace "before"
> and "after" calls do nothing if that variable is not yet set. This is
> similar to the x86 solution from commit 162396309745 ("ftrace, x86:
> make kernel text writable only for conversions").
>
> Reported-by: Stefan Agner <stefan@agner.ch>
> Tested-by: Stefan Agner <stefan@agner.ch>
> Link: http://lkml.kernel.org/r/20180620212906.24b7b66e at vmware.local.home
> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
> ---
Perhaps I should have Cc'd stable too?
-- Steve
^ permalink raw reply
* [PATCH V4 2/4] watchdog: stm32: add pclk feature for stm32mp1
From: Guenter Roeck @ 2018-06-21 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529571737-3552-3-git-send-email-ludovic.Barre@st.com>
On Thu, Jun 21, 2018 at 11:02:15AM +0200, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch adds compatible data to manage pclk clock by
> compatible. Adds stm32mp1 support which requires pclk clock.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
> drivers/watchdog/stm32_iwdg.c | 116 +++++++++++++++++++++++++++---------------
> 1 file changed, 74 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
> index c97ad56..e00e3b3 100644
> --- a/drivers/watchdog/stm32_iwdg.c
> +++ b/drivers/watchdog/stm32_iwdg.c
> @@ -11,12 +11,13 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/kernel.h>
> -#include <linux/module.h>
> #include <linux/interrupt.h>
> #include <linux/io.h>
> #include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/watchdog.h>
>
> @@ -54,11 +55,15 @@
> #define TIMEOUT_US 100000
> #define SLEEP_US 1000
>
> +#define HAS_PCLK true
> +
> struct stm32_iwdg {
> struct watchdog_device wdd;
> void __iomem *regs;
> - struct clk *clk;
> + struct clk *clk_lsi;
> + struct clk *clk_pclk;
> unsigned int rate;
> + bool has_pclk;
> };
>
> static inline u32 reg_read(void __iomem *base, u32 reg)
> @@ -133,6 +138,44 @@ static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
> return 0;
> }
>
> +static int stm32_iwdg_clk_init(struct platform_device *pdev,
> + struct stm32_iwdg *wdt)
> +{
> + u32 ret;
> +
> + wdt->clk_lsi = devm_clk_get(&pdev->dev, "lsi");
I just noticed a subtle difference: This used to be
devm_clk_get(&pdev->dev, NULL);
which would always get the first clock, no matter how it is named.
Can that cause problems with backward compatibility ?
Thanks,
Guenter
> + if (IS_ERR(wdt->clk_lsi)) {
> + dev_err(&pdev->dev, "Unable to get lsi clock\n");
> + return PTR_ERR(wdt->clk_lsi);
> + }
> +
> + /* optional peripheral clock */
> + if (wdt->has_pclk) {
> + wdt->clk_pclk = devm_clk_get(&pdev->dev, "pclk");
> + if (IS_ERR(wdt->clk_pclk)) {
> + dev_err(&pdev->dev, "Unable to get pclk clock\n");
> + return PTR_ERR(wdt->clk_pclk);
> + }
> +
> + ret = clk_prepare_enable(wdt->clk_pclk);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to prepare pclk clock\n");
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(wdt->clk_lsi);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to prepare lsi clock\n");
> + clk_disable_unprepare(wdt->clk_pclk);
> + return ret;
> + }
> +
> + wdt->rate = clk_get_rate(wdt->clk_lsi);
> +
> + return 0;
> +}
> +
> static const struct watchdog_info stm32_iwdg_info = {
> .options = WDIOF_SETTIMEOUT |
> WDIOF_MAGICCLOSE |
> @@ -147,49 +190,42 @@ static const struct watchdog_ops stm32_iwdg_ops = {
> .set_timeout = stm32_iwdg_set_timeout,
> };
>
> +static const struct of_device_id stm32_iwdg_of_match[] = {
> + { .compatible = "st,stm32-iwdg", .data = (void *)!HAS_PCLK },
> + { .compatible = "st,stm32mp1-iwdg", .data = (void *)HAS_PCLK },
> + { /* end node */ }
> +};
> +MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
> +
> static int stm32_iwdg_probe(struct platform_device *pdev)
> {
> struct watchdog_device *wdd;
> + const struct of_device_id *match;
> struct stm32_iwdg *wdt;
> struct resource *res;
> - void __iomem *regs;
> - struct clk *clk;
> int ret;
>
> + match = of_match_device(stm32_iwdg_of_match, &pdev->dev);
> + if (!match)
> + return -ENODEV;
> +
> + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
> + if (!wdt)
> + return -ENOMEM;
> +
> + wdt->has_pclk = match->data;
> +
> /* This is the timer base. */
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - regs = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(regs)) {
> + wdt->regs = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(wdt->regs)) {
> dev_err(&pdev->dev, "Could not get resource\n");
> - return PTR_ERR(regs);
> + return PTR_ERR(wdt->regs);
> }
>
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk)) {
> - dev_err(&pdev->dev, "Unable to get clock\n");
> - return PTR_ERR(clk);
> - }
> -
> - ret = clk_prepare_enable(clk);
> - if (ret) {
> - dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
> + ret = stm32_iwdg_clk_init(pdev, wdt);
> + if (ret)
> return ret;
> - }
> -
> - /*
> - * Allocate our watchdog driver data, which has the
> - * struct watchdog_device nested within it.
> - */
> - wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
> - if (!wdt) {
> - ret = -ENOMEM;
> - goto err;
> - }
> -
> - /* Initialize struct stm32_iwdg. */
> - wdt->regs = regs;
> - wdt->clk = clk;
> - wdt->rate = clk_get_rate(clk);
>
> /* Initialize struct watchdog_device. */
> wdd = &wdt->wdd;
> @@ -217,7 +253,8 @@ static int stm32_iwdg_probe(struct platform_device *pdev)
>
> return 0;
> err:
> - clk_disable_unprepare(clk);
> + clk_disable_unprepare(wdt->clk_lsi);
> + clk_disable_unprepare(wdt->clk_pclk);
>
> return ret;
> }
> @@ -227,23 +264,18 @@ static int stm32_iwdg_remove(struct platform_device *pdev)
> struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
>
> watchdog_unregister_device(&wdt->wdd);
> - clk_disable_unprepare(wdt->clk);
> + clk_disable_unprepare(wdt->clk_lsi);
> + clk_disable_unprepare(wdt->clk_pclk);
>
> return 0;
> }
>
> -static const struct of_device_id stm32_iwdg_of_match[] = {
> - { .compatible = "st,stm32-iwdg" },
> - { /* end node */ }
> -};
> -MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
> -
> static struct platform_driver stm32_iwdg_driver = {
> .probe = stm32_iwdg_probe,
> .remove = stm32_iwdg_remove,
> .driver = {
> .name = "iwdg",
> - .of_match_table = stm32_iwdg_of_match,
> + .of_match_table = of_match_ptr(stm32_iwdg_of_match),
> },
> };
> module_platform_driver(stm32_iwdg_driver);
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/1] arm64/mm: move {idmap_pg_dir,tramp_pg_dir,swapper_pg_dir} to .rodata section
From: James Morse @ 2018-06-21 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu-t5ErL89J=sxeVRYzDNrB1Ejdj+XOggAMWk-gY7ewsOg@mail.gmail.com>
Hi Ard,
On 21/06/18 10:29, Ard Biesheuvel wrote:
> On 21 June 2018 at 10:59, James Morse <james.morse@arm.com> wrote:
>> On 21/06/18 07:39, Ard Biesheuvel wrote:
>>> On 21 June 2018 at 04:51, Jun Yao <yaojun8558363@gmail.com> wrote:
>>>> On Wed, Jun 20, 2018 at 12:09:49PM +0200, Ard Biesheuvel wrote:
>>>>> On 20 June 2018 at 10:57, Jun Yao <yaojun8558363@gmail.com> wrote:
>>>>>> Move {idmap_pg_dir,tramp_pg_dir,swapper_pg_dir} to .rodata
>>>>>> section. And update the swapper_pg_dir by fixmap.
>>>>>
>>>>> I think we may be able to get away with not mapping idmap_pg_dir and
>>>>> tramp_pg_dir at all.
>>>>
>>>> I think we need to move tramp_pg_dir to .rodata. The attacker can write
>>>> a block-mapping(AP=01) to tramp_pg_dir and then he can access kernel
>>>> memory.
>>
>>> Why does it need to be mapped at all? When do we ever access it from the code?
>>
>> (We would want to make its fixmap entry read-only too)
>
> It already is.
Sorry, I missed that,
>>>>> As for swapper_pg_dir, it would indeed be nice if we could keep those
>>>>> mappings read-only most of the time, but I'm not sure how useful this
>>>>> is if we apply it to the root level only.
>>>>
>>>> The purpose of it is to make 'KSMA' harder, where an single arbitrary
>>>> write is used to add a block mapping to the page-tables, giving the
>>>> attacker full access to kernel memory. That's why we just apply it to
>>>> the root level only. If the attacker can arbitrary write multiple times,
>>>> I think it's hard to defend.
>>>
>>> So the assumption is that the root level is more easy to find?
>>> Otherwise, I'm not sure I understand why being able to write a level 0
>>> entry is so harmful, given that we don't have block mappings at that
>>> level.
>>
>> I think this thing assumes 3-level page tables with 39bit VA.
> The attack, you mean? Because this code is unlikely to build with that
> configuration, given that __pgd_populate() BUILD_BUG()s in that case.
Yes, the attack. (I struggle to think of it as an 'attack' because you already
have arbitrary write...)
>>>>> @@ -417,12 +421,22 @@ static void __init __map_memblock(pgd_t *pgdp, phys_addr_t start,
>>>>>>
>>>>>> void __init mark_linear_text_alias_ro(void)
>>>>>> {
>>
>>>>>> + size = (unsigned long)__init_begin - (unsigned long)swapper_pg_end;
>>>>>> + update_mapping_prot(__pa_symbol(swapper_pg_end),
>>>>>> + (unsigned long)lm_alias(swapper_pg_end),
>>>>>> + size, PAGE_KERNEL_RO);
>>>>>
>>>>> I don't think this is necessary. Even if some pages are freed, it
>>>>> doesn't harm to keep a read-only alias of them here since the new
>>>>> owner won't access them via this mapping anyway. So we can keep
>>>>> .rodata as a single region.
>>>>
>>>> To be honest, I didn't think of this issue at first. I later found a
>>>> problem when testing the code on qemu:
>>>
>>> OK, you're right. I missed the fact that this operates on the linear
>>> alias, not the kernel mapping itself.
>>>
>>> What I don't like is that we lose the ability to use block mappings
>>> for the entire .rodata section this way. Isn't it possible to move
>>> these pgdirs to the end of the .rodata segment, perhaps by using a
>>> separate input section name and placing that explicitly? We could even
>>> simply forget about freeing those pages, given that [on 4k pages] the
>>> benefit of freeing 12 KB of space is likely to get lost in the
>>> rounding noise anyway [segments are rounded up to 64 KB in size]
>>
>> I assumed that to move swapper_pg_dir into the .rodata section we would need to
>> break it up. Today its ~3 levels, which we setup in head.S, then do a dance in
>> paging_init() so that swapper_pg_dir is always the top level.
>>
>> We could generate all leves of the 'init_pg_dir' in the __initdata section, then
>> copy only the top level into swapper_pg_dir into the rodata section during
>> paging_init().
> Is that complexity truly justified for a security sensitive piece of
> code?
Wouldn't this be less complex? (I've probably explained it badly.)
Today head.S builds the initial page tables in ~3 levels of swapper_pg_dir, then
during paging_init() build new tables with a temporary top level.
We switch to the temporary top level, then copy over the first level of
swapper_pg_dir, then switch back to swapper_pg_dir. Finally we free the
no-longer-used levels of swapper_pg_dir.
This looks like re-inventing __initdata for the bits of page table we eventually
free.
What I tried to describe is building the head.S/initial-page-tables in a
reserved area of the the __initdata section. We no longer need a temporary
top-level, we can build the final page tables directly in swapper_pg_dir, which
means one fewer rounds of cpu_replace_ttbr1().
> Can't we just drop the memblock_free() and be done with it?
That works, I assumed it would be at least frowned on!
Thanks,
James
^ permalink raw reply
* [PATCH V2 2/4] dt-bindings: arm: fsl: add mu binding doc
From: A.s. Dong @ 2018-06-21 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180621074641.sqqvudxebt3hd43m@pengutronix.de>
Hi Sascha,
> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: Thursday, June 21, 2018 3:47 PM
> To: Rob Herring <robh@kernel.org>
> Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-arm-
> kernel at lists.infradead.org; dongas86 at gmail.com; kernel at pengutronix.de;
> shawnguo at kernel.org; Fabio Estevam <fabio.estevam@nxp.com>; dl-linux-
> imx <linux-imx@nxp.com>; Mark Rutland <mark.rutland@arm.com>;
> devicetree at vger.kernel.org
> Subject: Re: [PATCH V2 2/4] dt-bindings: arm: fsl: add mu binding doc
>
> On Wed, Jun 20, 2018 at 01:43:10PM -0600, Rob Herring wrote:
> > On Sun, Jun 17, 2018 at 08:49:47PM +0800, Dong Aisheng wrote:
> > > The Messaging Unit module enables two processors within the SoC to
> > > communicate and coordinate by passing messages (e.g. data, status
> > > and control) through the MU interface.
> > >
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: devicetree at vger.kernel.org
> > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > > ---
> > > v1->v2:
> > > * typo fixes
> > > * remove status property
> > > * remove imx6&7 compatible string which may be added later for
> > > the generic mailbox binding
> > >
> > > Note: Because MU used by SCU is not implemented as a mailbox driver,
> > > Instead, they're provided in library calls to gain higher performance.
> >
> > Using a binding doesn't mean you have to use an OS's subsystem.
> >
> > What needs higher performance? What's the performance difference?
> Why
> > can't the mailbox framework be improved?
>
> From what I see the performance is improved by polling the interrupt
> registers rather than using interrupts.
> I see no reason though why this can't be implemented with the mailbox
> framework as is.
>
I thought you've agreed to not write generic MU(mailbox) driver for SCU.
https://www.spinics.net/lists/arm-kernel/msg650217.html
But seems it's still not quite certain...
I'd like to explain some more.
1) the interrupt mechanism is not quite suitable for SCU firmware protocol
as the transfer size would be more than 4 words and the response data size
is also undetermined (it's set by SCU firmware side during a response).
So polling mode may be the best way to handle this as MU message
handling usually is quite fast in a few microseconds.
2) It's true that Mailbox framework is well designed and powerful.
But it's not quite suitable for SCU MU as we don't need to use the most
bits of it. Mailbox seems like to be more suitable for a generic MU
mailbox driver used by various clients/servers. But SCU MU are
quite specific to SCU protocol and can't be used by other clients
(MU 0~4 is fixed for SCU communication in MX8 HW design).
Even we write a MU Mailbox driver for SCU MU, it's still not a general
one and can't be used by others (e.g. communication with M4).
So I'd believe the current library way is still the best approach for SCU MU
Using. But I'm also okay for another generic MU drivers for other common
communications between A core and M4 side.
3) We actually have tried the MU(Mailbox) internally, it increased a lot
complexity comparing to the current library way and got a booting time
regression issue due to extra delays introduced in handling SCU protocol
in mailbox way.
And finally a nature question to us is:
What the benefit we can get for SCU MU using a mailbox way?
If we can't find benefits but introduce more complexities then why
we would do that way?
Regards
Dong Aisheng
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions |
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fww
> w.pengutronix.de%2F&data=02%7C01%7Caisheng.dong%40nxp.com%7C8ec
> 827973f6e40d1fe1508d5d74b2471%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> 7C0%7C0%7C636651640089438560&sdata=oRARdjilF4Ve2%2FnsXVhG7fmjXip
> H0HslgDMldbIGgY0%3D&reserved=0 |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 5/6] coresight: catu: Add support for scatter gather tables
From: Mathieu Poirier @ 2018-06-21 17:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529319379-17895-6-git-send-email-suzuki.poulose@arm.com>
Suzuki,
On Mon, Jun 18, 2018 at 11:56:18AM +0100, Suzuki K Poulose wrote:
> This patch adds the support for setting up a SG table for use
> by the CATU. We reuse the tmc_sg_table to represent the table/data
> pages, even though the table format is different.
>
> Similar to ETR SG table, CATU uses a 4KB page size for data buffers
> as well as page tables. All table entries are 64bit wide and have
> the following format:
>
> 63 12 1 0
> x-----------------------------------x
> | Address [63-12] | SBZ | V |
> x-----------------------------------x
>
> Where [V] -> 0 - Pointer is invalid
> 1 - Pointer is Valid
>
> CATU uses only first half of the page for data page pointers.
> i.e, single table page will only have 256 page pointers, addressing
> upto 1MB of data. The second half of a table page contains only two
> pointers at the end of the page (i.e, pointers at index 510 and 511),
> which are used as links to the "Previous" and "Next" page tables
> respectively.
>
> The first table page has an "Invalid" previous pointer and the
> next pointer entry points to the second page table if there is one.
> Similarly the last table page has an "Invalid" next pointer to
> indicate the end of the table chain.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-catu.c | 249 +++++++++++++++++++++++++++
> 1 file changed, 249 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
> index 11c84cb..95064c3 100644
> --- a/drivers/hwtracing/coresight/coresight-catu.c
> +++ b/drivers/hwtracing/coresight/coresight-catu.c
> @@ -16,10 +16,259 @@
>
> #include "coresight-catu.h"
> #include "coresight-priv.h"
> +#include "coresight-tmc.h"
>
> #define csdev_to_catu_drvdata(csdev) \
> dev_get_drvdata(csdev->dev.parent)
>
> +/* Verbose output for CATU table contents */
> +#ifdef CATU_DEBUG
> +#define catu_dbg(x, ...) dev_dbg(x, __VA_ARGS__)
> +#else
> +#define catu_dbg(x, ...) do {} while (0)
> +#endif
> +
> +/*
> + * CATU uses a page size of 4KB for page tables as well as data pages.
> + * Each 64bit entry in the table has the following format.
> + *
> + * 63 12 1 0
> + * ------------------------------------
> + * | Address [63-12] | SBZ | V|
> + * ------------------------------------
> + *
> + * Where bit[0] V indicates if the address is valid or not.
> + * Each 4K table pages have upto 256 data page pointers, taking upto 2K
> + * size. There are two Link pointers, pointing to the previous and next
> + * table pages respectively at the end of the 4K page. (i.e, entry 510
> + * and 511).
> + * E.g, a table of two pages could look like :
> + *
> + * Table Page 0 Table Page 1
> + * SLADDR ===> x------------------x x--> x-----------------x
> + * INADDR ->| Page 0 | V | | | Page 256 | V | <- INADDR+1M
> + * |------------------| | |-----------------|
> + * INADDR+4K ->| Page 1 | V | | | |
> + * |------------------| | |-----------------|
> + * | Page 2 | V | | | |
> + * |------------------| | |-----------------|
> + * | ... | V | | | ... |
> + * |------------------| | |-----------------|
> + * INADDR+1020K| Page 255 | V | | | Page 511 | V |
> + * SLADDR+2K==>|------------------| | |-----------------|
> + * | UNUSED | | | | |
> + * |------------------| | | |
> + * | UNUSED | | | | |
> + * |------------------| | | |
> + * | ... | | | | |
> + * |------------------| | |-----------------|
> + * | IGNORED | 0 | | | Table Page 0| 1 |
> + * |------------------| | |-----------------|
> + * | Table Page 1| 1 |--x | IGNORED | 0 |
> + * x------------------x x-----------------x
> + * SLADDR+4K==>
> + *
> + * The base input address (used by the ETR, programmed in INADDR_{LO,HI})
> + * must be aligned to 1MB (the size addressable by a single page table).
> + * The CATU maps INADDR{LO:HI} to the first page in the table pointed
> + * to by SLADDR{LO:HI} and so on.
> + *
> + */
> +typedef u64 cate_t;
> +
> +#define CATU_PAGE_SHIFT 12
> +#define CATU_PAGE_SIZE (1UL << CATU_PAGE_SHIFT)
> +#define CATU_PAGES_PER_SYSPAGE (PAGE_SIZE / CATU_PAGE_SIZE)
> +
> +/* Page pointers are only allocated in the first 2K half */
> +#define CATU_PTRS_PER_PAGE ((CATU_PAGE_SIZE >> 1) / sizeof(cate_t))
> +#define CATU_PTRS_PER_SYSPAGE (CATU_PAGES_PER_SYSPAGE * CATU_PTRS_PER_PAGE)
> +#define CATU_LINK_PREV ((CATU_PAGE_SIZE / sizeof(cate_t)) - 2)
> +#define CATU_LINK_NEXT ((CATU_PAGE_SIZE / sizeof(cate_t)) - 1)
> +
> +#define CATU_ADDR_SHIFT 12
> +#define CATU_ADDR_MASK ~(((cate_t)1 << CATU_ADDR_SHIFT) - 1)
> +#define CATU_ENTRY_VALID ((cate_t)0x1)
> +#define CATU_VALID_ENTRY(addr) \
> + (((cate_t)(addr) & CATU_ADDR_MASK) | CATU_ENTRY_VALID)
> +#define CATU_ENTRY_ADDR(entry) ((cate_t)(entry) & ~((cate_t)CATU_ENTRY_VALID))
> +
> +/*
> + * catu_get_table : Retrieve the table pointers for the given @offset
> + * within the buffer. The buffer is wrapped around to a valid offset.
> + *
> + * Returns : The CPU virtual address for the beginning of the table
> + * containing the data page pointer for @offset. If @daddrp is not NULL,
> + * @daddrp points the DMA address of the beginning of the table.
> + */
> +static inline cate_t *catu_get_table(struct tmc_sg_table *catu_table,
> + unsigned long offset,
> + dma_addr_t *daddrp)
> +{
> + unsigned long buf_size = tmc_sg_table_buf_size(catu_table);
> + unsigned int table_nr, pg_idx, pg_offset;
> + struct tmc_pages *table_pages = &catu_table->table_pages;
> + void *ptr;
> +
> + /* Make sure offset is within the range */
> + offset %= buf_size;
> +
> + /*
> + * Each table can address 1MB and a single kernel page can
> + * contain "CATU_PAGES_PER_SYSPAGE" CATU tables.
> + */
> + table_nr = offset >> 20;
> + /* Find the table page where the table_nr lies in */
> + pg_idx = table_nr / CATU_PAGES_PER_SYSPAGE;
> + pg_offset = (table_nr % CATU_PAGES_PER_SYSPAGE) * CATU_PAGE_SIZE;
> + if (daddrp)
> + *daddrp = table_pages->daddrs[pg_idx] + pg_offset;
> + ptr = page_address(table_pages->pages[pg_idx]);
> + return (cate_t *)((unsigned long)ptr + pg_offset);
> +}
> +
> +#ifdef CATU_DEBUG
> +static void catu_dump_table(struct tmc_sg_table *catu_table)
> +{
> + int i;
> + cate_t *table;
> + unsigned long table_end, buf_size, offset = 0;
> +
> + buf_size = tmc_sg_table_buf_size(catu_table);
> + dev_dbg(catu_table->dev,
> + "Dump table %p, tdaddr: %llx\n",
> + catu_table, catu_table->table_daddr);
> +
> + while (offset < buf_size) {
> + table_end = offset + SZ_1M < buf_size ?
> + offset + SZ_1M : buf_size;
> + table = catu_get_table(catu_table, offset, NULL);
> + for (i = 0; offset < table_end; i++, offset += CATU_PAGE_SIZE)
> + dev_dbg(catu_table->dev, "%d: %llx\n", i, table[i]);
> + dev_dbg(catu_table->dev, "Prev : %llx, Next: %llx\n",
> + table[CATU_LINK_PREV], table[CATU_LINK_NEXT]);
> + dev_dbg(catu_table->dev, "== End of sub-table ===");
> + }
> + dev_dbg(catu_table->dev, "== End of Table ===");
> +}
> +
> +#else
> +static inline void catu_dump_table(struct tmc_sg_table *catu_table)
> +{
> +}
> +#endif
> +
> +static inline cate_t catu_make_entry(dma_addr_t addr)
> +{
> + return addr ? CATU_VALID_ENTRY(addr) : 0;
> +}
> +
> +/*
> + * catu_populate_table : Populate the given CATU table.
> + * The table is always populated as a circular table.
> + * i.e, the "prev" link of the "first" table points to the "last"
> + * table and the "next" link of the "last" table points to the
> + * "first" table. The buffer should be made linear by calling
> + * catu_set_table().
> + */
> +static void
> +catu_populate_table(struct tmc_sg_table *catu_table)
> +{
> + int i, dpidx, s_dpidx;
> + unsigned long offset, buf_size, last_offset;
> + dma_addr_t data_daddr;
> + dma_addr_t prev_taddr, next_taddr, cur_taddr;
> + cate_t *table_ptr, *next_table;
> +
> + buf_size = tmc_sg_table_buf_size(catu_table);
> + dpidx = s_dpidx = 0;
>From the reading the code below variable s_dpidx stands for "small" data page
index, which isn't obvious from the get go and could easily be mistaken for
"system" data page index. Please add a comment to make your intentions clear.
> + offset = 0;
> +
> + table_ptr = catu_get_table(catu_table, 0, &cur_taddr);
> + prev_taddr = 0; /* Prev link for the first table */
> +
> + while (offset < buf_size) {
> + /*
> + * The @offset is always 1M aligned here and we have an
> + * empty table @table_ptr to fill. Each table can address
> + * upto 1MB data buffer. The last table may have fewer
> + * entries if the buffer size is not aligned.
> + */
> + last_offset = (offset + SZ_1M) < buf_size ?
> + (offset + SZ_1M) : buf_size;
> + for (i = 0; offset < last_offset;
> + i++, offset += CATU_PAGE_SIZE) {
I really like the choice of "table_end" in function catu_dump_table(). I think
using the same denomination here would make it easier to understand the code.
I wouldn't bother with such details if you weren't respinning this set. But now
that you are and these are extremely simple I think it's worth it, and it will
help slowing the prolifiration of gray hair around my head when I look back at
this a year or two down the road.
Thanks,
Mathieu
> +
> + data_daddr = catu_table->data_pages.daddrs[dpidx] +
> + s_dpidx * CATU_PAGE_SIZE;
> + catu_dbg(catu_table->dev,
> + "[table %5ld:%03d] 0x%llx\n",
> + (offset >> 20), i, data_daddr);
> + table_ptr[i] = catu_make_entry(data_daddr);
> + /* Move the pointers for data pages */
> + s_dpidx = (s_dpidx + 1) % CATU_PAGES_PER_SYSPAGE;
> + if (s_dpidx == 0)
> + dpidx++;
> + }
> +
> + /*
> + * If we have finished all the valid entries, fill the rest of
> + * the table (i.e, last table page) with invalid entries,
> + * to fail the lookups.
> + */
> + if (offset == buf_size) {
> + memset(&table_ptr[i], 0,
> + sizeof(cate_t) * (CATU_PTRS_PER_PAGE - i));
> + next_taddr = 0;
> + } else {
> + next_table = catu_get_table(catu_table,
> + offset, &next_taddr);
> + }
> +
> + table_ptr[CATU_LINK_PREV] = catu_make_entry(prev_taddr);
> + table_ptr[CATU_LINK_NEXT] = catu_make_entry(next_taddr);
> +
> + catu_dbg(catu_table->dev,
> + "[table%5ld]: Cur: 0x%llx Prev: 0x%llx, Next: 0x%llx\n",
> + (offset >> 20) - 1, cur_taddr, prev_taddr, next_taddr);
> +
> + /* Update the prev/next addresses */
> + if (next_taddr) {
> + prev_taddr = cur_taddr;
> + cur_taddr = next_taddr;
> + table_ptr = next_table;
> + }
> + }
> +
> + /* Sync the table for device */
> + tmc_sg_table_sync_table(catu_table);
> +}
> +
> +static struct tmc_sg_table __maybe_unused *
> +catu_init_sg_table(struct device *catu_dev, int node,
> + ssize_t size, void **pages)
> +{
> + int nr_tpages;
> + struct tmc_sg_table *catu_table;
> +
> + /*
> + * Each table can address upto 1MB and we can have
> + * CATU_PAGES_PER_SYSPAGE tables in a system page.
> + */
> + nr_tpages = DIV_ROUND_UP(size, SZ_1M) / CATU_PAGES_PER_SYSPAGE;
> + catu_table = tmc_alloc_sg_table(catu_dev, node, nr_tpages,
> + size >> PAGE_SHIFT, pages);
> + if (IS_ERR(catu_table))
> + return catu_table;
> +
> + catu_populate_table(catu_table);
> + dev_dbg(catu_dev,
> + "Setup table %p, size %ldKB, %d table pages\n",
> + catu_table, (unsigned long)size >> 10, nr_tpages);
> + catu_dump_table(catu_table);
> + return catu_table;
> +}
> +
> coresight_simple_reg32(struct catu_drvdata, devid, CORESIGHT_DEVID);
> coresight_simple_reg32(struct catu_drvdata, control, CATU_CONTROL);
> coresight_simple_reg32(struct catu_drvdata, status, CATU_STATUS);
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 1/1] arm64/mm: move {idmap_pg_dir, tramp_pg_dir, swapper_pg_dir} to .rodata section
From: Ard Biesheuvel @ 2018-06-21 17:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <67a238a8-e4db-6bf1-6da5-62ca9536191f@arm.com>
On 21 June 2018 at 19:04, James Morse <james.morse@arm.com> wrote:
> Hi Ard,
>
> On 21/06/18 10:29, Ard Biesheuvel wrote:
>> On 21 June 2018 at 10:59, James Morse <james.morse@arm.com> wrote:
>>> On 21/06/18 07:39, Ard Biesheuvel wrote:
>>>> On 21 June 2018 at 04:51, Jun Yao <yaojun8558363@gmail.com> wrote:
>>>>> On Wed, Jun 20, 2018 at 12:09:49PM +0200, Ard Biesheuvel wrote:
>>>>>> On 20 June 2018 at 10:57, Jun Yao <yaojun8558363@gmail.com> wrote:
>>>>>>> Move {idmap_pg_dir,tramp_pg_dir,swapper_pg_dir} to .rodata
>>>>>>> section. And update the swapper_pg_dir by fixmap.
>>>>>>
>>>>>> I think we may be able to get away with not mapping idmap_pg_dir and
>>>>>> tramp_pg_dir at all.
>>>>>
>>>>> I think we need to move tramp_pg_dir to .rodata. The attacker can write
>>>>> a block-mapping(AP=01) to tramp_pg_dir and then he can access kernel
>>>>> memory.
>>>
>>>> Why does it need to be mapped at all? When do we ever access it from the code?
>>>
>>> (We would want to make its fixmap entry read-only too)
>>
>> It already is.
>
> Sorry, I missed that,
>
>
>>>>>> As for swapper_pg_dir, it would indeed be nice if we could keep those
>>>>>> mappings read-only most of the time, but I'm not sure how useful this
>>>>>> is if we apply it to the root level only.
>>>>>
>>>>> The purpose of it is to make 'KSMA' harder, where an single arbitrary
>>>>> write is used to add a block mapping to the page-tables, giving the
>>>>> attacker full access to kernel memory. That's why we just apply it to
>>>>> the root level only. If the attacker can arbitrary write multiple times,
>>>>> I think it's hard to defend.
>>>>
>>>> So the assumption is that the root level is more easy to find?
>>>> Otherwise, I'm not sure I understand why being able to write a level 0
>>>> entry is so harmful, given that we don't have block mappings at that
>>>> level.
>>>
>>> I think this thing assumes 3-level page tables with 39bit VA.
>
>> The attack, you mean? Because this code is unlikely to build with that
>> configuration, given that __pgd_populate() BUILD_BUG()s in that case.
>
> Yes, the attack. (I struggle to think of it as an 'attack' because you already
> have arbitrary write...)
>
OK, so in that case, you can abuse your single arbitrary write to map
an entire 1 GB block of memory with arbitrary permissions, allowing
userland to take control of the contents, right? And if you know the
virtual and physical addresses of swapper_pg_dir, you can make sure
this block covers the entire kernel, allowing the attacker to
manipulate all core kernel code and statically allocated data
structures.
What I don't understand about this patch is how it is sufficient to
only remap swapper_pg_dir r/w for updates on kernels that use 4 level
paging.
>
>>>>>> @@ -417,12 +421,22 @@ static void __init __map_memblock(pgd_t *pgdp, phys_addr_t start,
>>>>>>>
>>>>>>> void __init mark_linear_text_alias_ro(void)
>>>>>>> {
>>>
>>>>>>> + size = (unsigned long)__init_begin - (unsigned long)swapper_pg_end;
>>>>>>> + update_mapping_prot(__pa_symbol(swapper_pg_end),
>>>>>>> + (unsigned long)lm_alias(swapper_pg_end),
>>>>>>> + size, PAGE_KERNEL_RO);
>>>>>>
>>>>>> I don't think this is necessary. Even if some pages are freed, it
>>>>>> doesn't harm to keep a read-only alias of them here since the new
>>>>>> owner won't access them via this mapping anyway. So we can keep
>>>>>> .rodata as a single region.
>>>>>
>>>>> To be honest, I didn't think of this issue at first. I later found a
>>>>> problem when testing the code on qemu:
>>>>
>>>> OK, you're right. I missed the fact that this operates on the linear
>>>> alias, not the kernel mapping itself.
>>>>
>>>> What I don't like is that we lose the ability to use block mappings
>>>> for the entire .rodata section this way. Isn't it possible to move
>>>> these pgdirs to the end of the .rodata segment, perhaps by using a
>>>> separate input section name and placing that explicitly? We could even
>>>> simply forget about freeing those pages, given that [on 4k pages] the
>>>> benefit of freeing 12 KB of space is likely to get lost in the
>>>> rounding noise anyway [segments are rounded up to 64 KB in size]
>>>
>>> I assumed that to move swapper_pg_dir into the .rodata section we would need to
>>> break it up. Today its ~3 levels, which we setup in head.S, then do a dance in
>>> paging_init() so that swapper_pg_dir is always the top level.
>>>
>>> We could generate all leves of the 'init_pg_dir' in the __initdata section, then
>>> copy only the top level into swapper_pg_dir into the rodata section during
>>> paging_init().
>
>> Is that complexity truly justified for a security sensitive piece of
>> code?
>
> Wouldn't this be less complex? (I've probably explained it badly.)
>
> Today head.S builds the initial page tables in ~3 levels of swapper_pg_dir, then
> during paging_init() build new tables with a temporary top level.
> We switch to the temporary top level, then copy over the first level of
> swapper_pg_dir, then switch back to swapper_pg_dir. Finally we free the
> no-longer-used levels of swapper_pg_dir.
>
> This looks like re-inventing __initdata for the bits of page table we eventually
> free.
>
> What I tried to describe is building the head.S/initial-page-tables in a
> reserved area of the the __initdata section. We no longer need a temporary
> top-level, we can build the final page tables directly in swapper_pg_dir, which
> means one fewer rounds of cpu_replace_ttbr1().
>
Ah fair enough. So either the initial page tables are never referred
to via swapper_pg_dir in the first place, or we copy the first level
over from __initdata after setting it up (which is probably easier
than teaching the asm code about non-consecutive page ranges).
So indeed, that would be an improvement in its own right.
>
>> Can't we just drop the memblock_free() and be done with it?
>
> That works, I assumed it would be at least frowned on!
>
I think I prefer your suggestion above.
But we do need to teach this code to deal with folded page table levels.
^ permalink raw reply
* [PATCH 0/3] ARM: dts: imx: add two ZII boards
From: Andrey Gusakov @ 2018-06-21 17:44 UTC (permalink / raw)
To: linux-arm-kernel
Common part of dts was moved to imx51-zii-common.dtsi
for future reuse.
Andrey Gusakov (3):
ARM: dts: imx51-zii-common: create common include dtsi
ARM: dts: imx: add ZII SCU2 ESB board
ARM: dts: imx: add ZII SCU2 Mezz board
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/imx51-zii-common.dtsi | 317 ++++++++++++++++++++++++++++
arch/arm/boot/dts/imx51-zii-rdu1.dts | 330 +++---------------------------
arch/arm/boot/dts/imx51-zii-scu2-esb.dts | 178 ++++++++++++++++
arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 190 +++++++++++++++++
5 files changed, 718 insertions(+), 301 deletions(-)
create mode 100644 arch/arm/boot/dts/imx51-zii-common.dtsi
create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-esb.dts
create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
--
1.9.1
^ permalink raw reply
* [PATCH 1/3] ARM: dts: imx51-zii-common: create common include dtsi
From: Andrey Gusakov @ 2018-06-21 17:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529603100-31958-1-git-send-email-andrey.gusakov@cogentembedded.com>
Make shared include file. Move common stuff from rdu1 dts file to
dtsi for future reuse by other imx51 based boards from ZII.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
arch/arm/boot/dts/imx51-zii-common.dtsi | 317 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx51-zii-rdu1.dts | 330 +++-----------------------------
2 files changed, 347 insertions(+), 300 deletions(-)
create mode 100644 arch/arm/boot/dts/imx51-zii-common.dtsi
diff --git a/arch/arm/boot/dts/imx51-zii-common.dtsi b/arch/arm/boot/dts/imx51-zii-common.dtsi
new file mode 100644
index 0000000..b0f0643
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-zii-common.dtsi
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2018 Zodiac Inflight Innovations
+
+#include "imx51.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ /* Will be filled by the bootloader */
+ memory at 90000000 {
+ reg = <0x90000000 0>;
+ };
+
+ i2c_gpio: i2c-gpio {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_swi2c>;
+ i2c-gpio,delay-us = <50>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_vbus: regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu {
+ cpu-supply = <&sw1_reg>;
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+ <&gpio4 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ pmic at 0 {
+ compatible = "fsl,mc13892";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ spi-max-frequency = <6000000>;
+ spi-cs-high;
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,mc13xxx-uses-adc;
+
+ regulators {
+ sw1_reg: sw1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1375000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3_reg: sw3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vpll_reg: vpll {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdig_reg: vdig {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ };
+
+ vsd_reg: vsd {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3150000>;
+ };
+
+ vusb_reg: vusb {
+ regulator-always-on;
+ };
+
+ vusb2_reg: vusb2 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2775000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vvideo_reg: vvideo {
+ regulator-min-microvolt = <2775000>;
+ regulator-max-microvolt = <2775000>;
+ };
+
+ vaudio_reg: vaudio {
+ regulator-min-microvolt = <2300000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vcam_reg: vcam {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ };
+ };
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ led-control = <0x0 0x0 0x3f83f8 0x0>;
+
+ sysled3: led3 at 3 {
+ reg = <3>;
+ label = "system:red:power";
+ linux,default-trigger = "default-on";
+ };
+
+ sysled4: led4 at 4 {
+ reg = <4>;
+ label = "system:green:act";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+ };
+
+ flash at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <25000000>;
+ reg = <1>;
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
+ <&gpio3 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&esdhc1 {
+ non-removable;
+ no-1-8-v;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&esdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc4>;
+ bus-width = <4>;
+ no-1-8-v;
+ no-sdio;
+ cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom at 50 {
+ compatible = "atmel,24c04";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "host";
+ disable-over-current;
+ phy_type = "utmi_wide";
+ vbus-supply = <&usb_vbus>;
+ status = "okay";
+};
+
+&usbphy0 {
+ vcc-supply = <&vusb2_reg>;
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+ MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
+ MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
+ MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
+ MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
+ MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x85
+ MX51_PAD_NANDF_D12__GPIO3_28 0x85
+ >;
+ };
+
+ pinctrl_esdhc1_4bit: esdhc1grp_4bit {
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ >;
+ };
+
+ pinctrl_esdhc1_8bit: esdhc1grp_8bit {
+ fsl,pins = <
+ MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5
+ MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5
+ MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5
+ MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5
+ >;
+ };
+
+ pinctrl_esdhc4: esdhc4grp {
+ fsl,pins = <
+ MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5
+ MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5
+ MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5
+ MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5
+ MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5
+ MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5
+ MX51_PAD_NANDF_D0__GPIO4_8 0x100
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+ MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX51_PAD_GPIO1_4__GPIO1_4 0x85
+ MX51_PAD_GPIO1_8__GPIO1_8 0xe5
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index df9eca9..59a80da 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -1,61 +1,14 @@
-/*
- * Copyright (C) 2017 Zodiac Inflight Innovations
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2018 Zodiac Inflight Innovations
/dts-v1/;
-#include "imx51.dtsi"
+#include "imx51-zii-common.dtsi"
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
model = "ZII RDU1 Board";
compatible = "zii,imx51-rdu1", "fsl,imx51";
- chosen {
- stdout-path = &uart1;
- };
-
- /* Will be filled by the bootloader */
- memory at 90000000 {
- reg = <0x90000000 0>;
- };
-
aliases {
mdio-gpio0 = &mdio_gpio;
rtc0 = &ds1341;
@@ -94,14 +47,6 @@
enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
- reg_5p0v_main: regulator-5p0v-main {
- compatible = "regulator-fixed";
- regulator-name = "5V_MAIN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -150,28 +95,6 @@
};
};
- i2c_gpio: i2c-gpio {
- compatible = "i2c-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_swi2c>;
- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
- <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
- i2c-gpio,delay-us = <50>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- sgtl5000: codec at a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- clocks = <&clk_26M_snd>;
- VDDA-supply = <&vdig_reg>;
- VDDIO-supply = <&vvideo_reg>;
- #sound-dai-cells = <0>;
- };
- };
-
spi_gpio: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
@@ -315,178 +238,30 @@
};
};
-&cpu {
- cpu-supply = <&sw1_reg>;
+&usb_vbus {
+ regulator-always-on;
};
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
- <&gpio4 25 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- pmic at 0 {
- compatible = "fsl,mc13892";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- spi-max-frequency = <6000000>;
- spi-cs-high;
- reg = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
- fsl,mc13xxx-uses-adc;
-
- regulators {
- sw1_reg: sw1 {
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1375000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3_reg: sw3 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1850000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vpll_reg: vpll {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vdig_reg: vdig {
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1650000>;
- regulator-boot-on;
- };
-
- vsd_reg: vsd {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3150000>;
- };
-
- vusb_reg: vusb {
- regulator-always-on;
- };
-
- vusb2_reg: vusb2 {
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <2775000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vvideo_reg: vvideo {
- regulator-min-microvolt = <2775000>;
- regulator-max-microvolt = <2775000>;
- };
-
- vaudio_reg: vaudio {
- regulator-min-microvolt = <2300000>;
- regulator-max-microvolt = <3000000>;
- };
-
- vcam_reg: vcam {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3000000>;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-always-on;
- };
- };
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
- led-control = <0x0 0x0 0x3f83f8 0x0>;
-
- sysled0 at 3 {
- reg = <3>;
- label = "system:green:status";
- linux,default-trigger = "default-on";
- };
-
- sysled1 at 4 {
- reg = <4>;
- label = "system:green:act";
- linux,default-trigger = "heartbeat";
- };
- };
- };
-
- flash at 1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
- spi-max-frequency = <25000000>;
- reg = <1>;
- };
+&ecspi2 {
+ status = "disabled";
};
&esdhc1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc1>;
+ pinctrl-0 = <&pinctrl_esdhc1_4bit>;
bus-width = <4>;
- no-1-8-v;
- non-removable;
- no-sdio;
- no-sd;
- status = "okay";
+};
+
+&esdhc4 {
+ status = "disabled";
};
&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen3_reg>;
- status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom at 50 {
- compatible = "atmel,24c04";
- pagesize = <16>;
- reg = <0x50>;
- };
-
hpa1: amp at 60 {
compatible = "ti,tpa6130a2";
reg = <0x60>;
@@ -550,31 +325,29 @@
};
-&ipu_di0_disp1 {
- remote-endpoint = <&display_in>;
-};
+&i2c_gpio {
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
+ <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
-&ssi2 {
- status = "okay";
+ sgtl5000: codec at a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clk_26M_snd>;
+ VDDA-supply = <&vdig_reg>;
+ VDDIO-supply = <&vvideo_reg>;
+ #sound-dai-cells = <0>;
+ };
};
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
+&ipu_di0_disp1 {
+ remote-endpoint = <&display_in>;
};
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
+&ssi2 {
status = "okay";
};
&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-
rave-sp {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
@@ -593,7 +366,7 @@
fsl,usbphy = <&usbh1phy>;
disable-over-current;
maximum-speed = "full-speed";
- vbus-supply = <®_5p0v_main>;
+ vbus-supply = <&usb_vbus>;
status = "okay";
};
@@ -604,20 +377,12 @@
phy_type = "ulpi";
fsl,usbphy = <&usbh2phy>;
disable-over-current;
- vbus-supply = <®_5p0v_main>;
+ vbus-supply = <&usb_vbus>;
status = "okay";
};
-&usbphy0 {
- vcc-supply = <&vusb_reg>;
-};
-
-&usbotg {
- dr_mode = "host";
- disable-over-current;
- phy_type = "utmi_wide";
- vbus-supply = <®_5p0v_main>;
- status = "okay";
+&sysled3 {
+ label = "system:green:status";
};
&iomuxc {
@@ -642,27 +407,6 @@
>;
};
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
- MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
- MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
- >;
- };
-
- pinctrl_esdhc1: esdhc1grp {
- fsl,pins = <
- MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
- MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
- MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
- MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
- MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
- MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
- >;
- };
-
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
@@ -696,13 +440,6 @@
>;
};
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
- MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
- >;
- };
-
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
@@ -741,13 +478,6 @@
>;
};
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
- MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
- >;
- };
-
pinctrl_sndgate26mhz: sndgate26mhzgrp {
fsl,pins = <
MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: imx: add ZII SCU2 ESB board
From: Andrey Gusakov @ 2018-06-21 17:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529603100-31958-1-git-send-email-andrey.gusakov@cogentembedded.com>
This adds support for the Zodiac Inflight Innovations SCU2 Ethernet
Switch Board, which is based on the i.MX51.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx51-zii-scu2-esb.dts | 178 +++++++++++++++++++++++++++++++
2 files changed, 180 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-esb.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 37a3de7..d8900f4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -358,7 +358,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx51-ts4800.dtb \
- imx51-zii-rdu1.dtb
+ imx51-zii-rdu1.dtb \
+ imx51-zii-scu2-esb.dtb
dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \
imx53-cx9020.dtb \
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-esb.dts b/arch/arm/boot/dts/imx51-zii-scu2-esb.dts
new file mode 100644
index 0000000..e052133
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-zii-scu2-esb.dts
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2018 Zodiac Inflight Innovations
+
+/dts-v1/;
+#include "imx51-zii-common.dtsi"
+
+/ {
+ model = "ZII SCU2 ESB board";
+ compatible = "zii,imx51-scu2-esb", "fsl,imx51";
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_4bit &pinctrl_esdhc1_8bit>;
+ bus-width = <8>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+
+ fec_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ switch at 0 {
+ compatible = "marvell,mv88e6085";
+ reg = <0>;
+ dsa,member = <0 0>;
+ eeprom-length = <512>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "port1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "port2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "port3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "scu2scu";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "esb2host";
+ };
+ port at 5 {
+ reg = <5>;
+ label = "esb2mezz";
+ phy-mode = "sgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port at 6 {
+ reg = <6>;
+ label = "cpu";
+ phy-mode = "mii";
+ ethernet = <&fec>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ lm75 at 48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+};
+
+&i2c_gpio {
+ gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>, /* sda */
+ <&gpio3 0 GPIO_ACTIVE_HIGH>; /* scl */
+};
+
+&ipu {
+ status = "disabled";
+};
+
+&usb_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_mmc_reset>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <150000>;
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004
+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004
+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004
+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
+ MX51_PAD_DISP2_DAT10__FEC_COL 0x0180
+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180
+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085
+ MX51_PAD_DI_GP4__FEC_RDATA2 0x0085
+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085
+ MX51_PAD_DI2_PIN2__FEC_MDC 0x2004
+ MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5
+ MX51_PAD_DI2_PIN4__FEC_CRS 0x0180
+ MX51_PAD_AUD3_BB_FS__GPIO4_21 0x0000
+ >;
+ };
+
+ pinctrl_swi2c: swi2cgrp {
+ fsl,pins = <
+ MX51_PAD_DI1_PIN11__GPIO3_0 0x100
+ MX51_PAD_DI1_PIN12__GPIO3_1 0x100
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+ MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+ MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
+ MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5
+ MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+ MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_usb_mmc_reset: usbmmcgrp {
+ fsl,pins = <
+ MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100
+ >;
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: imx: add ZII SCU2 Mezz board
From: Andrey Gusakov @ 2018-06-21 17:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529603100-31958-1-git-send-email-andrey.gusakov@cogentembedded.com>
This adds support for the Zodiac Inflight Innovations SCU2 Mezz
board, which is based on the i.MX51.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 190 ++++++++++++++++++++++++++++++
2 files changed, 192 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d8900f4..e0dc187 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -359,7 +359,8 @@ dtb-$(CONFIG_SOC_IMX51) += \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx51-ts4800.dtb \
imx51-zii-rdu1.dtb \
- imx51-zii-scu2-esb.dtb
+ imx51-zii-scu2-esb.dtb \
+ imx51-zii-scu2-mezz.dtb
dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \
imx53-cx9020.dtb \
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
new file mode 100644
index 0000000..f58572a
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2018 Zodiac Inflight Innovations
+
+/dts-v1/;
+#include "imx51-zii-common.dtsi"
+
+/ {
+ model = "ZII SCU2 Mezz Board";
+ compatible = "zii,imx51-scu2-mezz", "fsl,imx51";
+
+ aliases {
+ mdio-gpio0 = &mdio_gpio;
+ };
+
+ mdio_gpio: mdio-gpio {
+ compatible = "virtual,mdio-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_swmdio>;
+ gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */
+ <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch at 0 {
+ compatible = "marvell,mv88e6085";
+ reg = <0>;
+ dsa,member = <0 0>;
+ eeprom-length = <512>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "port4";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "port5";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "port6";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "port7";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "cpu";
+ ethernet = <&fec>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "mezz2esb";
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+};
+
+&usb_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_mmc_reset>;
+ gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <150000>;
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1_4bit &pinctrl_esdhc1_8bit>;
+ bus-width = <8>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-supply = <&vgen3_reg>;
+ phy-handle = <ðphy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy at 0 {
+ reg = <0>;
+ max-speed = <100>;
+ };
+ };
+};
+
+
+&i2c_gpio {
+ gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>, /* sda */
+ <&gpio3 1 GPIO_ACTIVE_HIGH>; /* scl */
+};
+
+&uart2 {
+ status = "disabled";
+};
+
+&vsd_reg {
+ regulator-always-on;
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004
+ MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004
+ MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004
+ MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004
+ MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
+ MX51_PAD_DISP2_DAT10__FEC_COL 0x0180
+ MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180
+ MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4
+ MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4
+ MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
+ MX51_PAD_DI_GP3__FEC_TX_ER 0x2004
+ MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180
+ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085
+ MX51_PAD_DI_GP4__FEC_RDATA2 0x0085
+ MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085
+ MX51_PAD_DI2_PIN2__FEC_MDC 0x2004
+ MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5
+ MX51_PAD_DI2_PIN4__FEC_CRS 0x0180
+ MX51_PAD_EIM_A20__GPIO2_14 0x0085
+ MX51_PAD_EIM_A21__GPIO2_15 0x00e5
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+ MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_usb_mmc_reset: usbmmcgrp {
+ fsl,pins = <
+ MX51_PAD_CSI1_D9__GPIO3_13 0x85
+ >;
+ };
+
+ pinctrl_swmdio: swmdiogrp {
+ fsl,pins = <
+ MX51_PAD_EIM_D22__GPIO2_6 0x100
+ MX51_PAD_EIM_D23__GPIO2_7 0x100
+ >;
+ };
+
+ pinctrl_swi2c: swi2cgrp {
+ fsl,pins = <
+ MX51_PAD_DI1_PIN12__GPIO3_1 0x100
+ MX51_PAD_DI1_PIN13__GPIO3_2 0x100
+ >;
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM: ftrace: Only set kernel memory back to read-only after boot
From: Stefan Agner @ 2018-06-21 17:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180621125025.25b70bb9@gandalf.local.home>
On 21.06.2018 18:50, Steven Rostedt wrote:
> On Thu, 21 Jun 2018 12:47:10 -0400
> Steven Rostedt <rostedt@goodmis.org> wrote:
>
>> From: Steven Rostedt (VMware) <rostedt@goodmis.org>
>>
>> Dynamic ftrace requires modifying the code segments that are usually
>> set to read-only. To do this, a per arch function is called both before
>> and after the ftrace modifications are performed. The "before" function
>> will set kernel code text to read-write to allow for ftrace to make the
>> modifications, and the "after" function will set the kernel code text
>> back to "read-only" to keep the kernel code text protected.
>>
>> The issue happens when dynamic ftrace is tested at boot up. The test is
>> done before the kernel code text has been set to read-only. But the
>> "before" and "after" calls are still performed. The "after" call will
>> change the kernel code text to read-only prematurely, and other boot
>> code that expects this code to be read-write will fail.
>>
>> The solution is to add a variable that is set when the kernel code text
>> is expected to be converted to read-only, and make the ftrace "before"
>> and "after" calls do nothing if that variable is not yet set. This is
>> similar to the x86 solution from commit 162396309745 ("ftrace, x86:
>> make kernel text writable only for conversions").
>>
>> Reported-by: Stefan Agner <stefan@agner.ch>
>> Tested-by: Stefan Agner <stefan@agner.ch>
>> Link: http://lkml.kernel.org/r/20180620212906.24b7b66e at vmware.local.home
>> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
>> ---
>
> Perhaps I should have Cc'd stable too?
>
As it is self tests only which are broken probably not super important.
But then, the fix is also rather clean and safe IMHO, so why not.
--
Stefan
^ permalink raw reply
* [PATCH 1/2] rtc: armada38x: drop redundant initialization
From: Alexandre Belloni @ 2018-06-21 17:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <00ffe926e6878724d8289dd0e289a1f16df55ef7.1529602823.git.baruch@tkos.co.il>
On 21/06/2018 20:40:22+0300, Baruch Siach wrote:
> The 'ret' variable in these functions is set unconditionally below.
>
Hum, what is the actual benefit of this patch?
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> drivers/rtc/rtc-armada38x.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/rtc/rtc-armada38x.c b/drivers/rtc/rtc-armada38x.c
> index 1e4978c96ffd..4d62a54fd5d6 100644
> --- a/drivers/rtc/rtc-armada38x.c
> +++ b/drivers/rtc/rtc-armada38x.c
> @@ -229,7 +229,7 @@ static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
> static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
> {
> struct armada38x_rtc *rtc = dev_get_drvdata(dev);
> - int ret = 0;
> + int ret;
> unsigned long time, flags;
>
> ret = rtc_tm_to_time(tm, &time);
> @@ -272,7 +272,7 @@ static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
> u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
> u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
> unsigned long time, flags;
> - int ret = 0;
> + int ret;
>
> ret = rtc_tm_to_time(&alrm->time, &time);
>
> --
> 2.17.1
>
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH V2 2/4] dt-bindings: arm: fsl: add mu binding doc
From: Oleksij Rempel @ 2018-06-21 18:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM0PR04MB4211B39D5AFAB95FC2A91F9980760@AM0PR04MB4211.eurprd04.prod.outlook.com>
Hi,
On Thu, Jun 21, 2018 at 05:11:33PM +0000, A.s. Dong wrote:
> Hi Sascha,
> > On Wed, Jun 20, 2018 at 01:43:10PM -0600, Rob Herring wrote:
> > > On Sun, Jun 17, 2018 at 08:49:47PM +0800, Dong Aisheng wrote:
> > > > The Messaging Unit module enables two processors within the SoC to
> > > > communicate and coordinate by passing messages (e.g. data, status
> > > > and control) through the MU interface.
> > > >
> > > > ---
> > > > v1->v2:
> > > > * typo fixes
> > > > * remove status property
> > > > * remove imx6&7 compatible string which may be added later for
> > > > the generic mailbox binding
> > > >
> > > > Note: Because MU used by SCU is not implemented as a mailbox driver,
> > > > Instead, they're provided in library calls to gain higher performance.
> > >
> > > Using a binding doesn't mean you have to use an OS's subsystem.
> > >
> > > What needs higher performance? What's the performance difference?
> > Why
> > > can't the mailbox framework be improved?
> >
> > From what I see the performance is improved by polling the interrupt
> > registers rather than using interrupts.
> > I see no reason though why this can't be implemented with the mailbox
> > framework as is.
> >
>
> I thought you've agreed to not write generic MU(mailbox) driver for SCU.
> https://www.spinics.net/lists/arm-kernel/msg650217.html
> But seems it's still not quite certain...
>
> I'd like to explain some more.
>
> 1) the interrupt mechanism is not quite suitable for SCU firmware protocol
> as the transfer size would be more than 4 words and the response data size
> is also undetermined (it's set by SCU firmware side during a response).
> So polling mode may be the best way to handle this as MU message
> handling usually is quite fast in a few microseconds.
>
> 2) It's true that Mailbox framework is well designed and powerful.
> But it's not quite suitable for SCU MU as we don't need to use the most
> bits of it. Mailbox seems like to be more suitable for a generic MU
> mailbox driver used by various clients/servers. But SCU MU are
> quite specific to SCU protocol and can't be used by other clients
> (MU 0~4 is fixed for SCU communication in MX8 HW design).
> Even we write a MU Mailbox driver for SCU MU, it's still not a general
> one and can't be used by others (e.g. communication with M4).
> So I'd believe the current library way is still the best approach for SCU MU
> Using. But I'm also okay for another generic MU drivers for other common
> communications between A core and M4 side.
>
> 3) We actually have tried the MU(Mailbox) internally, it increased a lot
> complexity comparing to the current library way and got a booting time
> regression issue due to extra delays introduced in handling SCU protocol
> in mailbox way.
>
> And finally a nature question to us is:
> What the benefit we can get for SCU MU using a mailbox way?
>
> If we can't find benefits but introduce more complexities then why
> we would do that way?
Looks like my response to same topic within my patch set is lost, so I
repost it here:
ok.. let's take some of IMX8 SCU driver code to see if there any difference:
..this part of the code is blocking write procedure for one
channeler (register or what ever name you prefer) per write.. correct?
+void mu_send_msg(struct mu_priv *priv, uint32_t index, uint32_t msg)
+{
+ uint32_t mask = MU_SR_TE0_MASK >> index;
+
+ /* Wait TX register to be empty. */
+ while (!(readl_relaxed(priv->base + MU_ASR) & mask))
+ ;
+ writel_relaxed(msg, priv->base + MU_ATR0 + (index * 4));
+}
+EXPORT_SYMBOL_GPL(mu_send_msg);
According to documentation it is recommended to use only one status bit
for the last register to use MU as one big 4words sized pipe.
But, there is no way you can write to all 4 registers without checking status
for each of this register, because your protocol has dynamic message
size. So you are forced to use your one channel as 4 separate channels.
Write it part of the message separately and allow your firmware read 1
word to understand how to behave on the rest of the message.
+static void sc_ipc_write(struct sc_ipc *sc_ipc, void *data)
+{
+ sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
+ uint8_t count = 0;
+
+ /* Check size */
+ if (msg->size > SC_RPC_MAX_MSG)
+ return;
+
+ /* Write first word */
+ mu_send_msg(sc_ipc->mu_base, 0, *((uint32_t *) msg));
+ count++;
.. in this loop you are writing to one channel/register per loop. If
the communicate will stall for some reason, the linux system will just
freeze here without any timeout or error message.. no idea how about the
opposite site.
+ /* Write remaining words */
+ while (count < msg->size) {
+ mu_send_msg(sc_ipc->mu_base, count % MU_TR_COUNT,
+ msg->DATA.u32[count - 1]);
+ count++;
+ }
+}
... and here is a proof that sc_ipc_write will do in some cases 5 rounds
(5 * 4 bytes = 20 bytes single message) with probable busy waiting for
each channel
+sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, uint32_t addr_src,
+ uint32_t addr_dst, uint32_t len, bool fw)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_IMAGE_LOAD;
+ RPC_U32(&msg, 0) = addr_src;
+ RPC_U32(&msg, 4) = addr_dst;
+ RPC_U32(&msg, 8) = len;
+ RPC_U8(&msg, 12) = (uint8_t)fw;
+ RPC_SIZE(&msg) = 5;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
+}
+
So, the same code with mailbox framework will be some thing like this:
1. request all 4 channels in the probe. ignore completion callback and
set proper timeout.
2. keep your old code by replacing this part.
/* Write remaining words */
while (count < msg->size) {
mbox_send_message(sc_ipc->mbox_chan[count % MU_TR_COUNT],
msg->DATA.u32[count - 1]);
count++;
}
The advantage of this variant. If SCU firmware will stall, the linux
will be able to notify about it without blocking complete system.
Can you please provide (if possible) your old mailbox based
implementation. I'm curious to see why it is slow.
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* [PATCH v5] ARM: dts: imx51-zii-rdu1: fix touchscreen pinctrl
From: Nick Dyer @ 2018-06-21 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFXsbZr-HJE54c0BC5=d1tStByA5ytGhSSZMirNKE03JzGCDXQ@mail.gmail.com>
The pinctrl settings were incorrect for the touchscreen interrupt line, causing
an interrupt storm. This change has been tested with both the atmel_mxt_ts and
RMI4 drivers on the RDU1 units.
The value 0x4 comes from the value of register IOMUXC_SW_PAD_CTL_PAD_CSI1_D8
from the old vendor kernel.
Signed-off-by: Nick Dyer <nick@shmanahar.org>
Fixes: ceef0396f367 ("ARM: dts: imx: add ZII RDU1 board")
Cc: <stable@vger.kernel.org> # 4.15+
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Chris Healy <cphealy@gmail.com>
---
Changes in v5:
- Add tested by Chris Healy
Changes in v4:
- Add reviewed by Fabio
Changes in v3:
- Update commit message to add source of 0x4 value, fixes tag and CC stable
Changes in v2:
- Use hex, only alter IRQ line config
arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index df9eca94d812..8a878687197b 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -770,7 +770,7 @@
pinctrl_ts: tsgrp {
fsl,pins = <
- MX51_PAD_CSI1_D8__GPIO3_12 0x85
+ MX51_PAD_CSI1_D8__GPIO3_12 0x04
MX51_PAD_CSI1_D9__GPIO3_13 0x85
>;
};
--
2.17.1
^ permalink raw reply related
* Finish the GENERIC_IRQ_MULTI_HANDLER conversion
From: Palmer Dabbelt @ 2018-06-21 18:17 UTC (permalink / raw)
To: linux-arm-kernel
A while ago I sent a patch set that adds a GENERIC_IRQ_MULTI_HANDLER,
which is an exact copy of the existing IRQ_MULTI_HANDLER support in the
arm port, which is being used unconditionally by arm64 and openrisc.
GENERIC_IRQ_MULTI_HANDLER is currently being used by the RISC-V port. I
managed to make a few mistakes in my original patch set and as a result
my conversion of the other architectures of GENERIC_IRQ_MULTI_HANDLER
was dropped.
This patch set finishes up my original patch set by converting arm,
arm64, and openrisc over to the new GENERIC_IRQ_MULTI_HANDLER support
and then removing MULTI_IRQ_HANDLER as it's obselete.
At the time I wrote this I gave it fairly extensive build testing, but
went I recently rebased it I just tested the full patch set on arm,
arm64, and openrisc defconfigs.
Various flavors of this patch set have bounced around a few times
before, but I'm calling this a whole new patch set as it builds on top
of what was merged.
^ permalink raw reply
* [PATCH 2/2] arm64: dts: stratix10: Add SPI clocks for Stratix10
From: Thor Thayer @ 2018-06-21 18:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527617612-2205-2-git-send-email-thor.thayer@linux.intel.com>
Hi Dinh,
On 05/29/2018 01:13 PM, thor.thayer at linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Add the SPI clocks to the Stratix10 device tree.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 47fa4b450324..34658f135daf 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -316,6 +316,8 @@
> resets = <&rst SPIM0_RESET>;
> reg-io-width = <4>;
> num-cs = <4>;
> + clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>,
> + <&clkmgr STRATIX10_SPI_M_CLK>;
> status = "disabled";
> };
>
> @@ -328,6 +330,8 @@
> resets = <&rst SPIM1_RESET>;
> reg-io-width = <4>;
> num-cs = <4>;
> + clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>,
> + <&clkmgr STRATIX10_SPI_M_CLK>;
> status = "disabled";
> };
>
>
Any comments on this patch?
^ permalink raw reply
* [PATCH 1/2] arm64: dts: stratix10: Fix SPI nodes for Stratix10
From: Thor Thayer @ 2018-06-21 18:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527617612-2205-1-git-send-email-thor.thayer@linux.intel.com>
Hi Dinh,
On 05/29/2018 01:13 PM, thor.thayer at linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Remove the unused bus-num node and change num-chipselect
> to num-cs to match SPI bindings.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> Fixes: 78cd6a9d8e154 ("arm64: dts: Add base stratix 10 dtsi")
> Cc: stable at vger.kernel.org
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index d8c94d5ff4b4..47fa4b450324 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -315,8 +315,7 @@
> interrupts = <0 99 4>;
> resets = <&rst SPIM0_RESET>;
> reg-io-width = <4>;
> - num-chipselect = <4>;
> - bus-num = <0>;
> + num-cs = <4>;
> status = "disabled";
> };
>
> @@ -328,8 +327,7 @@
> interrupts = <0 100 4>;
> resets = <&rst SPIM1_RESET>;
> reg-io-width = <4>;
> - num-chipselect = <4>;
> - bus-num = <0>;
> + num-cs = <4>;
> status = "disabled";
> };
>
>
Any update on this patch?
^ permalink raw reply
* [PATCH] arm64: dts: rockchip: add 96boards RK3399 Ficus board
From: Ezequiel Garcia @ 2018-06-21 18:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1621532.NjQG3041Bx@phil>
On Thu, 2018-06-21 at 15:27 +0200, Heiko Stuebner wrote:
> Hi Ezequiel,
>
> Am Dienstag, 19. Juni 2018, 00:08:04 CEST schrieb Ezequiel Garcia:
> > The RK3399 Ficus board is an Enterprise Edition board
> > manufactured by Vamrs Ltd., based on the Rockchip RK3399 SoC.
> >
> > The board exposes a bunch of nice peripherals, including
> > SATA, HDMI, MIPI CSI, Ethernet, WiFi, USB 2.0, USB 3.0
> > and PCIe.
> >
> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
> > ---
> > I am not including USB support because I cannot seem
> > to make it work.
> >
> > [ 1.677293] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
> > [ 1.677937] dwc3 fe800000.dwc3: Configuration mismatch. dr_mode
> > forced to host
> > [ 1.678602] dwc3 fe800000.dwc3: failed to initialize core
> > [ 1.679409] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
> > [ 1.679988] dwc3 fe900000.dwc3: failed to initialize core
> >
> > I am under the impression it is related to:
> >
> > commit fe8abf332b8f66868013cfcd6bfe727136a2ab5f
> > Author: Masahiro Yamada <yamada.masahiro@socionext.com>
> > Date: Wed May 16 11:41:07 2018 +0900
> >
> > usb: dwc3: support clocks and resets for DWC3 core
> >
> > Any ideas? Would like to sort out the USB issue before
> > merging.
>
> From what I remember, we had an issue with usb ports not providing
> an extcon to the typc-c phys, making the dwc3 fail to probe.
> Enric did a nice patch adding support for extcon-less type-c phys in
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/co
> mmit/?id=ec1fcd7b7e6f50dd6e259ca76c6e41e2346b3afe
>
> So maybe the kernel you were working on was just to old?
>
I was working on top of next-20180618, quite new :).
However, at least that is a nice hint for me to chase.
>
> > Also, I should probably split the rk3399.dtsi change.
>
> correct :-D
>
>
> > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 564
> > ++++++++++++++++++
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 9 +
> > 3 files changed, 574 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
>
> Please also add an entry to
> Documentation/devicetree/bindings/arm/rockchip.txt
>
Got it.
>
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > new file mode 100644
> > index 000000000000..17471b4b7a14
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > @@ -0,0 +1,564 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2018 Collabora Ltd.
> > + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +#include "rk3399.dtsi"
> > +#include "rk3399-opp.dtsi"
> > +
> > +/ {
> > + model = "96boards RK3399 Ficus";
> > + compatible = "vamrs,ficus", "rockchip,rk3399";
> > +
> > + chosen {
> > + stdout-path = "serial2:1500000n8";
> > + };
> > +
> > + clkin_gmac: external-gmac-clock {
> > + compatible = "fixed-clock";
> > + clock-frequency = <125000000>;
> > + clock-output-names = "clkin_gmac";
> > + #clock-cells = <0>;
> > + };
> > +
> > + usb_typec_vbus: usb-typec-vbus {
> > + compatible = "regulator-fixed";
> > + regulator-name = "typec-vbus";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> > + };
> > +
> > + vcc1v8_s0: vcc1v8-s0 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc1v8_s0";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-always-on;
> > + };
> > +
> > + vcc_sys: vcc-sys {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc_sys";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + };
> > +
> > + vcc_phy: vcc-phy-regulator {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc_phy";
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
>
> please try to double-check the regulator setup with the schematics.
>
> Like this completely unconnected vcc_phy regulator is normally copy-
> pasted
> from Rockchip's default board-dt and never matches the actual power-
> tree.
>
Yeah, regulators need another look.
> Schematics seem to a at
> https://www.96boards.org/documentation/consumer/rock960/hardwar
> e-docs/
> and there doesn't even seem to be network interface on the board?
>
You are looking at a consumer edition board, and this is
the enterprise edition (aka ficus). It has network :)
Here's a nice video where Tom talks about it:
https://youtu.be/2UYcmhbKyP4
FWIW, I have tested mainline U-Boot and Linux. Gigabit network
and mmc tested on both. Also, this board is where I found the
iommu/vpu stall you fixed recently.
Haven't test SATA, but I will soon.
> Also please use regulator names as defined in the schematics.
>
>
> This applies to all regulators defined here. I'd really like to see a
> real
> supply-tree with regulators connected to their supplies.
>
> See for example the rk3399-gru boards for an example :-)
> And you can also check $DEBUGFS/regulator/regulator_summary
> which should form a nice tree structure if everything is correct.
>
>
> > +&gmac {
> > + assigned-clocks = <&cru SCLK_RMII_SRC>;
> > + assigned-clock-parents = <&clkin_gmac>;
> > + clock_in_out = "input";
> > + phy-supply = <&vcc_phy>;
> > + phy-mode = "rgmii";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&rgmii_pins>;
> > + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> > + snps,reset-active-low;
> > + snps,reset-delays-us = <0 10000 50000>;
> > + tx_delay = <0x28>;
> > + rx_delay = <0x11>;
> > + status = "okay";
> > +};
>
> Looking at the 96boards page, there is no gmac on the board at all?
>
>
> > + fusb0: fusb30x at 22 {
>
> node name should be generic ... typec at 22 or something like that
>
OK.
>
>
> > + vbus-supply = <&usb_typec_vbus>;
> > + compatible = "fairchild,fusb302";
> > + reg = <0x22>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&fusb0_int>;
> > + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
> > + status = "okay";
>
> Please do
> - compatible
> - reg
> - interrupts
> [alphabetical]
> - status
> for properties.
>
> Again applies to everything.
>
OK, thanks for the review.
Regards,
Eze
^ permalink raw reply
* [PATCH] drm/pl111: Support Nomadik LCDC variant
From: Linus Walleij @ 2018-06-21 18:44 UTC (permalink / raw)
To: linux-arm-kernel
The Nomadik has a variant of the PL110 known as "Color LCD
Controller" LCDC. This variant has the same bit ordering as
the DRM subsystem (in difference from the other variants)
and adds a few bits for the control of 5551, 565 etc in the
control register. Notably it also adds a packed RGB888
24BPP mode.
We add support by detecting this variant and also adding a
small plug-in that will mux the LCDC out if the ASIC happens
to be muxed to the other graphics controller (they are
mutually exclusive).
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpu/drm/pl111/Makefile | 1 +
drivers/gpu/drm/pl111/pl111_display.c | 54 ++++++++++++++++++++++-----
drivers/gpu/drm/pl111/pl111_drm.h | 5 +++
drivers/gpu/drm/pl111/pl111_drv.c | 41 +++++++++++++++++++-
drivers/gpu/drm/pl111/pl111_nomadik.c | 36 ++++++++++++++++++
drivers/gpu/drm/pl111/pl111_nomadik.h | 18 +++++++++
6 files changed, 144 insertions(+), 11 deletions(-)
create mode 100644 drivers/gpu/drm/pl111/pl111_nomadik.c
create mode 100644 drivers/gpu/drm/pl111/pl111_nomadik.h
diff --git a/drivers/gpu/drm/pl111/Makefile b/drivers/gpu/drm/pl111/Makefile
index 19a8189dc54f..0c70f0e91d21 100644
--- a/drivers/gpu/drm/pl111/Makefile
+++ b/drivers/gpu/drm/pl111/Makefile
@@ -4,6 +4,7 @@ pl111_drm-y += pl111_display.o \
pl111_drv.o
pl111_drm-$(CONFIG_ARCH_VEXPRESS) += pl111_vexpress.o
+pl111_drm-$(CONFIG_ARCH_NOMADIK) += pl111_nomadik.o
pl111_drm-$(CONFIG_DEBUG_FS) += pl111_debugfs.o
obj-$(CONFIG_DRM_PL111) += pl111_drm.o
diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 19b0d006a54a..a432eb7ad445 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -223,48 +223,84 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
/* Hard-code TFT panel */
cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
+ /* On the ST Micro variant, assume all 24 bits are connected */
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_CDWID_24;
- /* Note that the the hardware's format reader takes 'r' from
+ /*
+ * Note that the the ARM hardware's format reader takes 'r' from
* the low bit, while DRM formats list channels from high bit
- * to low bit as you read left to right.
+ * to low bit as you read left to right. The ST Micro version of
+ * the PL110 (LCDC) however uses the standard DRM format.
*/
switch (fb->format->format) {
+ case DRM_FORMAT_BGR888:
+ /* Only supported on the ST Micro variant */
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
+ break;
+ case DRM_FORMAT_RGB888:
+ /* Only supported on the ST Micro variant */
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_LCDBPP24_PACKED;
+ break;
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_XBGR8888:
- cntl |= CNTL_LCDBPP24;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_LCDBPP24 | CNTL_BGR;
+ else
+ cntl |= CNTL_LCDBPP24;
break;
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XRGB8888:
- cntl |= CNTL_LCDBPP24 | CNTL_BGR;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_LCDBPP24;
+ else
+ cntl |= CNTL_LCDBPP24 | CNTL_BGR;
break;
case DRM_FORMAT_BGR565:
if (priv->variant->is_pl110)
cntl |= CNTL_LCDBPP16;
+ else if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
else
cntl |= CNTL_LCDBPP16_565;
break;
case DRM_FORMAT_RGB565:
if (priv->variant->is_pl110)
- cntl |= CNTL_LCDBPP16;
+ cntl |= CNTL_LCDBPP16 | CNTL_BGR;
+ else if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
else
- cntl |= CNTL_LCDBPP16_565;
- cntl |= CNTL_BGR;
+ cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
break;
case DRM_FORMAT_ABGR1555:
case DRM_FORMAT_XBGR1555:
cntl |= CNTL_LCDBPP16;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
break;
case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_XRGB1555:
- cntl |= CNTL_LCDBPP16 | CNTL_BGR;
+ cntl |= CNTL_LCDBPP16;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_1XBPP_5551;
+ else
+ cntl |= CNTL_BGR;
break;
case DRM_FORMAT_ABGR4444:
case DRM_FORMAT_XBGR4444:
cntl |= CNTL_LCDBPP16_444;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
break;
case DRM_FORMAT_ARGB4444:
case DRM_FORMAT_XRGB4444:
- cntl |= CNTL_LCDBPP16_444 | CNTL_BGR;
+ cntl |= CNTL_LCDBPP16_444;
+ if (priv->variant->st_bitmux_control)
+ cntl |= CNTL_ST_1XBPP_444;
+ else
+ cntl |= CNTL_BGR;
break;
default:
WARN_ONCE(true, "Unknown FB format 0x%08x\n",
diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h
index ce4501d0ab48..1aa015ccacef 100644
--- a/drivers/gpu/drm/pl111/pl111_drm.h
+++ b/drivers/gpu/drm/pl111/pl111_drm.h
@@ -36,11 +36,14 @@ struct drm_minor;
* struct pl111_variant_data - encodes IP differences
* @name: the name of this variant
* @is_pl110: this is the early PL110 variant
+ * @is_lcdc: this is the ST Microelectronics Nomadik LCDC variant
* @external_bgr: this is the Versatile Pl110 variant with external
* BGR/RGB routing
* @broken_clockdivider: the clock divider is broken and we need to
* use the supplied clock directly
* @broken_vblank: the vblank IRQ is broken on this variant
+ * @st_bitmux_control: this variant is using the ST Micro bitmux
+ * extensions to the control register
* @formats: array of supported pixel formats on this variant
* @nformats: the length of the array of supported pixel formats
* @fb_bpp: desired bits per pixel on the default framebuffer
@@ -48,9 +51,11 @@ struct drm_minor;
struct pl111_variant_data {
const char *name;
bool is_pl110;
+ bool is_lcdc;
bool external_bgr;
bool broken_clockdivider;
bool broken_vblank;
+ bool st_bitmux_control;
const u32 *formats;
unsigned int nformats;
unsigned int fb_bpp;
diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c
index 454ff0804642..46559b686abd 100644
--- a/drivers/gpu/drm/pl111/pl111_drv.c
+++ b/drivers/gpu/drm/pl111/pl111_drv.c
@@ -75,6 +75,7 @@
#include "pl111_drm.h"
#include "pl111_versatile.h"
+#include "pl111_nomadik.h"
#define DRIVER_DESC "DRM module for PL111"
@@ -288,8 +289,8 @@ static int pl111_amba_probe(struct amba_device *amba_dev,
priv->memory_bw = 0;
}
- /* The two variants swap this register */
- if (variant->is_pl110) {
+ /* The two main variants swap this register */
+ if (variant->is_pl110 || variant->is_lcdc) {
priv->ienb = CLCD_PL110_IENB;
priv->ctrl = CLCD_PL110_CNTL;
} else {
@@ -308,6 +309,7 @@ static int pl111_amba_probe(struct amba_device *amba_dev,
ret = pl111_versatile_init(dev, priv);
if (ret)
goto dev_unref;
+ pl111_nomadik_init(dev);
/* turn off interrupts before requesting the irq */
writel(0, priv->regs + priv->ienb);
@@ -400,12 +402,47 @@ static const struct pl111_variant_data pl111_variant = {
.fb_bpp = 32,
};
+static const u32 pl110_nomadik_pixel_formats[] = {
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_BGR565,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ABGR4444,
+ DRM_FORMAT_XBGR4444,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB4444,
+};
+
+static const struct pl111_variant_data pl110_nomadik_variant = {
+ .name = "LCDC (PL110 Nomadik)",
+ .formats = pl110_nomadik_pixel_formats,
+ .nformats = ARRAY_SIZE(pl110_nomadik_pixel_formats),
+ .is_lcdc = true,
+ .st_bitmux_control = true,
+ .broken_vblank = true,
+ .fb_bpp = 16,
+};
+
+
static const struct amba_id pl111_id_table[] = {
{
.id = 0x00041110,
.mask = 0x000fffff,
.data = (void*)&pl110_variant,
},
+ {
+ .id = 0x00180110,
+ .mask = 0x00fffffe,
+ .data = (void*)&pl110_nomadik_variant,
+ },
{
.id = 0x00041111,
.mask = 0x000fffff,
diff --git a/drivers/gpu/drm/pl111/pl111_nomadik.c b/drivers/gpu/drm/pl111/pl111_nomadik.c
new file mode 100644
index 000000000000..6ade7ca9d367
--- /dev/null
+++ b/drivers/gpu/drm/pl111/pl111_nomadik.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include "pl111_nomadik.h"
+
+#define PMU_CTRL_OFFSET 0x0000
+#define PMU_CTRL_LCDNDIF BIT(26)
+
+void pl111_nomadik_init(struct device *dev)
+{
+ struct regmap *pmu_regmap;
+
+ /*
+ * Just bail out of this is not found, we could be running
+ * multiplatform on something else than Nomadik.
+ */
+ pmu_regmap =
+ syscon_regmap_lookup_by_compatible("stericsson,nomadik-pmu");
+ if (IS_ERR(pmu_regmap))
+ return;
+
+ /*
+ * This bit in the PMU controller multiplexes the two graphics
+ * blocks found in the Nomadik STn8815. The other one is called
+ * MDIF (Master Display Interface) and gets muxed out here.
+ */
+ regmap_update_bits(pmu_regmap,
+ PMU_CTRL_OFFSET,
+ PMU_CTRL_LCDNDIF,
+ 0);
+ dev_info(dev, "set Nomadik PMU mux to CLCD mode\n");
+}
+EXPORT_SYMBOL_GPL(pl111_nomadik_init);
diff --git a/drivers/gpu/drm/pl111/pl111_nomadik.h b/drivers/gpu/drm/pl111/pl111_nomadik.h
new file mode 100644
index 000000000000..c408842a1c73
--- /dev/null
+++ b/drivers/gpu/drm/pl111/pl111_nomadik.h
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/device.h>
+
+#ifndef PL111_NOMADIK_H
+#define PL111_NOMADIK_H
+#endif
+
+#ifdef CONFIG_ARCH_NOMADIK
+
+void pl111_nomadik_init(struct device *dev);
+
+#else
+
+static inline void pl111_nomadik_init(struct device *dev)
+{
+}
+
+#endif
--
2.17.1
^ permalink raw reply related
* [PATCH 0/7] Initial support for Samsung Galaxy S and Galaxy S 4G
From: Paweł Chmiel @ 2018-06-21 19:09 UTC (permalink / raw)
To: linux-arm-kernel
Jonathan Bakker (2):
ARM: dts: s5pv210: Add initial DTS config for SGH-T959P phone
dt-bindings: samsung: Document binding for SGH-T959P board
Pawe? Chmiel (5):
ARM: dts: s5pv210: Add missing interrupt-controller property to gph2
ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones.
ARM: dts: s5pv210: Add initial DTS for Samsung Galaxy S phone.
ARM: s5pv210_defconfig: Enable drivers for Samsung Aries based phones
dt-bindings: samsung: Document bindings for Samsung aries boards
.../bindings/arm/samsung/samsung-boards.txt | 3 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/s5pv210-aries.dtsi | 397 +++++++++++++++++++++
arch/arm/boot/dts/s5pv210-fascinate4g.dts | 40 +++
arch/arm/boot/dts/s5pv210-galaxys.dts | 72 ++++
arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 2 +
arch/arm/configs/s5pv210_defconfig | 49 ++-
7 files changed, 562 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/s5pv210-aries.dtsi
create mode 100644 arch/arm/boot/dts/s5pv210-fascinate4g.dts
create mode 100644 arch/arm/boot/dts/s5pv210-galaxys.dts
--
2.7.4
^ permalink raw reply
* [PATCH 1/7] ARM: dts: s5pv210: Add missing interrupt-controller property to gph2
From: Paweł Chmiel @ 2018-06-21 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529608199-5583-1-git-send-email-pawel.mikolaj.chmiel@gmail.com>
Adds missing interrupt-controller property to gph2 block,
to silence following warnings during build
/soc/pinctrl at e0200000/gph2: Missing interrupt-controller or interrupt-map property
It's reguired by Samsung aries boards, an S5PV210 based
Samsung Galaxy S (i9000) and Galaxy S 4G phones, which are added in next patches.
Signed-off-by: Pawe? Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
index 3a79feab11c3..7f0c9d447871 100644
--- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -258,6 +258,8 @@
gph2: gph2 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
#interrupt-cells = <2>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/7] ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones.
From: Paweł Chmiel @ 2018-06-21 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529608199-5583-1-git-send-email-pawel.mikolaj.chmiel@gmail.com>
This DTS file have initial support Samsung Aries based phones.
Initial version have support for:
- sdcard
- internal memory (present only on non 4g variant)
- max8998 pmic and rtc
- max17040 fuel gauge
- gpio keys
- fimd (no panel driver yet)
- usb (peripherial mode)
- wifi
Signed-off-by: Pawe? Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
arch/arm/boot/dts/s5pv210-aries.dtsi | 397 +++++++++++++++++++++++++++++++++++
1 file changed, 397 insertions(+)
create mode 100644 arch/arm/boot/dts/s5pv210-aries.dtsi
diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi
new file mode 100644
index 000000000000..6e8ac3615765
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-aries.dtsi
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's S5PV210 based Galaxy Aries board device tree source
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "s5pv210.dtsi"
+
+/ {
+ compatible = "samsung,aries", "samsung,s5pv210";
+
+ aliases {
+ i2c6 = &i2c_pmic;
+ i2c9 = &i2c_fuel;
+ };
+
+ memory at 30000000 {
+ device_type = "memory";
+ reg = <0x30000000 0x05000000
+ 0x40000000 0x10000000
+ 0x50000000 0x08000000>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_gpio_rst>;
+ post-power-on-delay-ms = <500>;
+ power-off-delay-us = <500>;
+ };
+
+ i2c_pmic: i2c-pmic {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic at 66 {
+ compatible = "maxim,max8998";
+ reg = <0x66>;
+ interrupt-parent = <&gph0>;
+ interrupts = <7 0>;
+
+ max8998,pmic-buck1-default-dvs-idx = <1>;
+ max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>,
+ <&gph0 4 GPIO_ACTIVE_HIGH>;
+ max8998,pmic-buck1-dvs-voltage = <1275000>, <1200000>,
+ <1050000>, <950000>;
+
+ max8998,pmic-buck2-default-dvs-idx = <0>;
+ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
+ max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>;
+
+ regulators {
+ ldo2_reg: LDO2 {
+ regulator-name = "VALIVE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "VUSB_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "VADC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "VLCD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ /* Till we get panel driver */
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-name = "VUSB_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "VCC_2.8V_PDA";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-name = "CAM_AF_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-name = "CAM_SENSOR_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VGA_VDDIO_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VGA_DVDD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "CAM_ISP_HOST_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VGA_AVDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VCC_3.0V_LCD";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ /* Till we get panel driver */
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vddarm";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1250000>;
+ };
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "vddint";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1500000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "VCC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ safe1_sreg: ESAFEOUT1 {
+ regulator-name = "SAFEOUT1";
+ };
+ };
+ };
+ };
+
+ i2c_fuel: i2c-fuel {
+ compatible = "i2c-gpio";
+ sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fuel at 36 {
+ compatible = "maxim,max17040";
+ interrupt-parent = <&vic0>;
+ interrupts = <7>;
+ reg = <0x36>;
+ };
+ };
+};
+
+&xusbxti {
+ clock-frequency = <24000000>;
+};
+
+&pinctrl0 {
+ wlan_bt_en: wlan-bt-en {
+ samsung,pins = "gpb-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-val = <1>;
+ };
+
+ wlan_gpio_rst: wlan-gpio-rst {
+ samsung,pins = "gpg1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ wifi_host_wake: wifi-host-wake {
+ samsung,pins = "gph2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ tf_detect: tf-detect {
+ samsung,pins = "gph3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ wifi_wake: wifi-wake {
+ samsung,pins = "gph3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ massmemory_en: massmemory-en {
+ samsung,pins = "gpj2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&sdhci1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ max-frequency = <38400000>;
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4 &wifi_wake &wifi_host_wake &wlan_bt_en>;
+ pinctrl-names = "default";
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf at 1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gph2>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&sdhci2 {
+ bus-width = <4>;
+ cd-gpios = <&gph3 4 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&ldo5_reg>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&hsotg {
+ vusb_a-supply = <&ldo8_reg>;
+ vusb_d-supply = <&ldo3_reg>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+ vbus-supply = <&safe1_sreg>;
+};
+
+&fimd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_clk &lcd_data24>;
+ status = "okay";
+
+ samsung,invert-vden;
+ samsung,invert-vclk;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display-timings {
+ native-mode = <&timing0>;
+
+ timing0: timing at 0 {
+ /* 480x800 at 60Hz */
+ clock-frequency = <25628040>;
+ hactive = <480>;
+ vactive = <800>;
+ hfront-porch = <16>;
+ hback-porch = <16>;
+ hsync-len = <2>;
+ vfront-porch = <28>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 3/7] ARM: dts: s5pv210: Add initial DTS for Samsung Galaxy S phone.
From: Paweł Chmiel @ 2018-06-21 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529608199-5583-1-git-send-email-pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: Pawe? Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/s5pv210-galaxys.dts | 72 +++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
create mode 100644 arch/arm/boot/dts/s5pv210-galaxys.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e2424957809..522ebdca1d3d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -846,6 +846,7 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-aquila.dtb \
+ s5pv210-galaxys.dtb \
s5pv210-goni.dtb \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \
diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts
new file mode 100644
index 000000000000..d435032541a9
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-galaxys.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "s5pv210-aries.dtsi"
+
+/ {
+ model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210";
+ compatible = "samsung,galaxys", "samsung,aries", "samsung,s5pv210";
+
+ chosen {
+ bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk2p1 rw rootwait ignore_loglevel earlyprintk";
+ };
+
+ nand_pwrseq: nand-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpj2 7 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&massmemory_en>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "power";
+ gpios = <&gph2 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ vol-down {
+ label = "volume_down";
+ gpios = <&gph3 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ vol-up {
+ label = "volume_up";
+ gpios = <&gph3 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ home {
+ label = "home";
+ gpios = <&gph3 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ wakeup-source;
+ };
+ };
+};
+
+&pinctrl0 {
+ massmemory_en: massmemory-en {
+ samsung,pins = "gpj2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&sdhci0 {
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&nand_pwrseq>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] ARM: s5pv210_defconfig: Enable drivers for Samsung Aries based phones
From: Paweł Chmiel @ 2018-06-21 19:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1529608199-5583-1-git-send-email-pawel.mikolaj.chmiel@gmail.com>
Enable config options required for Samsung Aries based phones..
While we're here, also enable other useful options like:
- SYSVIPC
- CGROUPS
- DEVTMPFS
- networking support
- ext4 and autofs
Signed-off-by: Pawe? Chmiel <pawel.mikolaj.chmiel@gmail.com>
---
arch/arm/configs/s5pv210_defconfig | 49 +++++++++++++++++++++++++++++++++++---
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index 09b5a7386414..a077597369f1 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -1,5 +1,7 @@
+CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CGROUPS=y
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
@@ -13,28 +15,68 @@ CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_ARCH_S5PV210=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT=y
-CONFIG_AEABI=y
+CONFIG_ARM_APPENDED_DTB=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
CONFIG_VFP=y
CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
+CONFIG_NETDEVICES=y
+CONFIG_BRCMFMAC=m
CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
+CONFIG_I2C_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_BATTERY_MAX17040=y
# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_MFD_MAX8998=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_MAX8998=y
+CONFIG_DRM=y
+CONFIG_DRM_EXYNOS=y
+CONFIG_DRM_EXYNOS_FIMD=y
+CONFIG_DRM_EXYNOS_DPI=y
+CONFIG_USB=y
+CONFIG_USB_OTG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_DWC2=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+CONFIG_MMC_SDHCI_S3C_DMA=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MAX8998=m
+CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHY_S5PV210_USB2=y
CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
@@ -44,6 +86,7 @@ CONFIG_ROMFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
--
2.7.4
^ permalink raw reply related
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