* [PATCH 7/7] arm64: tegra: Enable HDA controller on Jetson TX1
From: Thierry Reding @ 2018-12-06 16:50 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Sameer Pujar, linux-arm-kernel, Jon Hunter
In-Reply-To: <20181206165022.23845-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The HDA controller can be used for audio playback over HDMI.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index 365726ddd418..a96e6ee70c21 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1330,6 +1330,10 @@
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
};
+ hda@70030000 {
+ status = "okay";
+ };
+
padctl@7009f000 {
status = "okay";
--
2.19.1
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* Re: [PATCH] arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB
From: Baruch Siach @ 2018-12-06 17:02 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Russell King, Andrew Lunn, Jason Cooper, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <87tvjqveee.fsf@bootlin.com>
Hi Gregory,
Gregory CLEMENT writes:
> On jeu., déc. 06 2018, Baruch Siach <baruch@tkos.co.il> wrote:
>
>> Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K
>> board.
>>
>> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
>> ---
>> arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> index dfb26661a88e..5b4a9609e31f 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> @@ -282,6 +282,10 @@
>> vqmmc-supply = <&v_3_3>;
>> };
>>
>> +&cp0_usb3_1 {
>
> Don't you have any phy for this USB3 port?
Not as far as I can see. Why would I need one? The serdes signals are
connected directly to the mini-PCIe, just like the USB Type-A connector
on the same board. I haven't tested the USB3 signals on the mini-PCIe,
though, as I have no USB3 mini-PCIe device.
baruch
>> + status = "okay";
>> +};
>> +
>> &cp1_pinctrl {
>> /*
>> * MPP Bus:
>> --
>> 2.19.2
>>
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
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* Re: Moving ARM dts files
From: Rob Herring @ 2018-12-06 16:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Lunn, Alexandre Belloni, Tony Lindgren, Liviu Dudau,
Masahiro Yamada, Thierry Reding, Florian Fainelli, Kevin Hilman,
Gregory CLEMENT, Michal Simek, Krzysztof Kozlowski,
ARM-SoC Maintainers, Joel Stanley, Uwe Kleine-König,
Andy Gross, devicetree, Jason Cooper, Simon Horman,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Jisheng Zhang, Maxime Coquelin, Shawn Guo, Andreas Färber,
Daniel Mack
In-Reply-To: <CACRpkdbzyZD23JapAxEKc24jSwmZws5LqWS8O2Y4-VA3smgYyQ@mail.gmail.com>
On Thu, Dec 6, 2018 at 8:30 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Thu, Dec 6, 2018 at 3:05 PM Alexandre Belloni
> <alexandre.belloni@bootlin.com> wrote:
> > On 06/12/2018 07:58:24-0600, Rob Herring wrote:
> > > On Thu, Dec 6, 2018 at 7:39 AM Uwe Kleine-König
> > > <u.kleine-koenig@pengutronix.de> wrote:
> > > >
> > > > Hello,
> > > >
> > > > On Wed, Dec 05, 2018 at 09:01:59AM -0600, Rob Herring wrote:
> > > > > i.MX23 is a Sigmatel chip STMP??
> > > >
> > > > I think the Freescale i.MX23 didn't exist at Sigmatel back then. AFAIK
> > > > this is a new design using IP from Sigmatel after the aquisition.
> > >
> > > It is not. I was in the i.MX group which Sigmatel was merged into at
> > > the time. Purely marketing rebranding.
> > >
> >
> > Wouldn't it be easier to name the directory to the corresponding mach-*
> > entry?
> >
> > So, imx23 and imx28 would go to mxs/, other imx in imx/. And this also
> > solves the Marvell mess with the Synaptics Socs going in berlin/ and the
> > other ones in mvebu/.
>
> I like this idea.
Fine by me though I think marvell gets more complicated than that.
I'll try a pass at that at least for the cases with a mixture of
families.
> We discussed merging all ARM reference design mach-* to one dir
> if I just name that mach-arm then we get a convergence to the
> vendor name in some organic way.
TBC, you want .../boot/dts/arm/* for all the ARM, Ltd boards? Just
making sure as you were arguing against vendor names. :)
Rob
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* [PATCH 6/7] arm64: tegra: Add CEC controller on Tegra194
From: Thierry Reding @ 2018-12-06 16:50 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Sameer Pujar, linux-arm-kernel, Jon Hunter
In-Reply-To: <20181206165022.23845-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 59baa631b422..31add2e2ac1b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -357,6 +357,15 @@
interrupt-parent = <&gic>;
};
+ cec@3960000 {
+ compatible = "nvidia,tegra194-cec";
+ reg = <0x03960000 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA194_CLK_CEC>;
+ clock-names = "cec";
+ status = "disabled";
+ };
+
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x03c00000 0xa0000>;
--
2.19.1
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* [PATCH 5/7] arm64: tegra: Enable HDA on Jetson Xavier
From: Thierry Reding @ 2018-12-06 16:50 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Sameer Pujar, linux-arm-kernel, Jon Hunter
In-Reply-To: <20181206165022.23845-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Enable the HDA controller on Jetson Xavier so that it can be used for
audio playback over HDMI.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 274937042c4a..adf351010ff5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -24,6 +24,10 @@
status = "okay";
};
+ hda@3510000 {
+ status = "okay";
+ };
+
host1x@13e00000 {
display-hub@15200000 {
status = "okay";
--
2.19.1
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* [PATCH 1/7] arm64: tegra: Add HDA controller on Tegra186
From: Thierry Reding @ 2018-12-06 16:50 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Sameer Pujar, linux-arm-kernel, Jon Hunter
From: Thierry Reding <treding@nvidia.com>
The HDA controller found on Tegra186 can be used for audio playback over
HDMI.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 4c79778d80db..6cea54dc9d35 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -318,6 +318,22 @@
status = "disabled";
};
+ hda@3510000 {
+ compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
+ reg = <0x0 0x03510000 0x0 0x10000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_HDA>,
+ <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
+ <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
+ resets = <&bpmp TEGRA186_RESET_HDA>,
+ <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
+ <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
+ status = "disabled";
+ };
+
fuse@3820000 {
compatible = "nvidia,tegra186-efuse";
reg = <0x0 0x03820000 0x0 0x10000>;
--
2.19.1
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* [PATCH 3/7] arm64: tegra: Add CEC controller on Tegra186
From: Thierry Reding @ 2018-12-06 16:50 UTC (permalink / raw)
To: Thierry Reding; +Cc: linux-tegra, Sameer Pujar, linux-arm-kernel, Jon Hunter
In-Reply-To: <20181206165022.23845-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The CEC controller found on Tegra186 can be used to control consumer
devices using the HDMI CEC pin.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6cea54dc9d35..19fb266c0895 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -352,6 +352,15 @@
interrupt-parent = <&gic>;
};
+ cec@3960000 {
+ compatible = "nvidia,tegra186-cec";
+ reg = <0x0 0x03960000 0x0 0x10000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_CEC>;
+ clock-names = "cec";
+ status = "disabled";
+ };
+
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x0 0x03c00000 0x0 0xa0000>;
--
2.19.1
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* [PATCH v3 10/12] x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For drivers that do not support context exclusion let's advertise the
PERF_PMU_CAP_NOEXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/x86/events/amd/ibs.c | 13 +------------
arch/x86/events/amd/power.c | 10 ++--------
arch/x86/events/intel/cstate.c | 12 +++---------
arch/x86/events/intel/rapl.c | 9 ++-------
arch/x86/events/intel/uncore_snb.c | 9 ++-------
arch/x86/events/msr.c | 10 ++--------
6 files changed, 12 insertions(+), 51 deletions(-)
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index d50bb4d..62f317c 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -253,15 +253,6 @@ static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
return -EOPNOTSUPP;
}
-static const struct perf_event_attr ibs_notsupp = {
- .exclude_user = 1,
- .exclude_kernel = 1,
- .exclude_hv = 1,
- .exclude_idle = 1,
- .exclude_host = 1,
- .exclude_guest = 1,
-};
-
static int perf_ibs_init(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
@@ -282,9 +273,6 @@ static int perf_ibs_init(struct perf_event *event)
if (event->pmu != &perf_ibs->pmu)
return -ENOENT;
- if (perf_flags(&event->attr) & perf_flags(&ibs_notsupp))
- return -EINVAL;
-
if (config & ~perf_ibs->config_mask)
return -EINVAL;
@@ -537,6 +525,7 @@ static struct perf_ibs perf_ibs_fetch = {
.start = perf_ibs_start,
.stop = perf_ibs_stop,
.read = perf_ibs_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
},
.msr = MSR_AMD64_IBSFETCHCTL,
.config_mask = IBS_FETCH_CONFIG_MASK,
diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c
index 2aefacf..c5ff084 100644
--- a/arch/x86/events/amd/power.c
+++ b/arch/x86/events/amd/power.c
@@ -136,14 +136,7 @@ static int pmu_event_init(struct perf_event *event)
return -ENOENT;
/* Unsupported modes and filters. */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- /* no sampling */
- event->attr.sample_period)
+ if (event->attr.sample_period)
return -EINVAL;
if (cfg != AMD_POWER_EVENTSEL_PKG)
@@ -226,6 +219,7 @@ static struct pmu pmu_class = {
.start = pmu_event_start,
.stop = pmu_event_stop,
.read = pmu_event_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static int power_cpu_exit(unsigned int cpu)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 9f8084f..15a1981 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -280,13 +280,7 @@ static int cstate_pmu_event_init(struct perf_event *event)
return -ENOENT;
/* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.sample_period) /* no sampling */
+ if (event->attr.sample_period) /* no sampling */
return -EINVAL;
if (event->cpu < 0)
@@ -437,7 +431,7 @@ static struct pmu cstate_core_pmu = {
.start = cstate_pmu_event_start,
.stop = cstate_pmu_event_stop,
.read = cstate_pmu_event_update,
- .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
+ .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
.module = THIS_MODULE,
};
@@ -451,7 +445,7 @@ static struct pmu cstate_pkg_pmu = {
.start = cstate_pmu_event_start,
.stop = cstate_pmu_event_stop,
.read = cstate_pmu_event_update,
- .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
+ .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
.module = THIS_MODULE,
};
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index 32f3e94..18a5628 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -397,13 +397,7 @@ static int rapl_pmu_event_init(struct perf_event *event)
return -EINVAL;
/* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.sample_period) /* no sampling */
+ if (event->attr.sample_period) /* no sampling */
return -EINVAL;
/* must be done before validate_group */
@@ -699,6 +693,7 @@ static int __init init_rapl_pmus(void)
rapl_pmus->pmu.stop = rapl_pmu_event_stop;
rapl_pmus->pmu.read = rapl_pmu_event_read;
rapl_pmus->pmu.module = THIS_MODULE;
+ rapl_pmus->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
return 0;
}
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index 8527c3e..63a343b 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -374,13 +374,7 @@ static int snb_uncore_imc_event_init(struct perf_event *event)
return -EINVAL;
/* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.sample_period) /* no sampling */
+ if (event->attr.sample_period) /* no sampling */
return -EINVAL;
/*
@@ -474,6 +468,7 @@ static struct pmu snb_uncore_imc_pmu = {
.start = uncore_pmu_event_start,
.stop = uncore_pmu_event_stop,
.read = uncore_pmu_event_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static struct intel_uncore_ops snb_uncore_imc_ops = {
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index b4771a6..f7f64b0 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -160,13 +160,7 @@ static int msr_event_init(struct perf_event *event)
return -ENOENT;
/* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.sample_period) /* no sampling */
+ if (event->attr.sample_period) /* no sampling */
return -EINVAL;
if (cfg >= PERF_MSR_EVENT_MAX)
@@ -256,7 +250,7 @@ static struct pmu pmu_msr = {
.start = msr_event_start,
.stop = msr_event_stop,
.read = msr_event_update,
- .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
+ .capabilities = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
};
static int __init msr_init(void)
--
2.7.4
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* [PATCH v3 11/12] x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For x86 PMUs that do not support context exclusion let's advertise the
PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
This change means that amd/iommu and amd/uncore will now also
indicate that they do not support exclude_{hv|idle} and intel/uncore
that it does not support exclude_{guest|host}.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/x86/events/amd/iommu.c | 6 +-----
arch/x86/events/amd/uncore.c | 7 ++-----
arch/x86/events/intel/uncore.c | 9 +--------
3 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index 3210fee..7635c23 100644
--- a/arch/x86/events/amd/iommu.c
+++ b/arch/x86/events/amd/iommu.c
@@ -223,11 +223,6 @@ static int perf_iommu_event_init(struct perf_event *event)
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EINVAL;
- /* IOMMU counters do not have usr/os/guest/host bits */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_host || event->attr.exclude_guest)
- return -EINVAL;
-
if (event->cpu < 0)
return -EINVAL;
@@ -414,6 +409,7 @@ static const struct pmu iommu_pmu __initconst = {
.read = perf_iommu_read,
.task_ctx_nr = perf_invalid_context,
.attr_groups = amd_iommu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static __init int init_one_iommu(unsigned int idx)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 8671de1..988cb9c 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -201,11 +201,6 @@ static int amd_uncore_event_init(struct perf_event *event)
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EINVAL;
- /* NB and Last level cache counters do not have usr/os/guest/host bits */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_host || event->attr.exclude_guest)
- return -EINVAL;
-
/* and we do not enable counter overflow interrupts */
hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
hwc->idx = -1;
@@ -307,6 +302,7 @@ static struct pmu amd_nb_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static struct pmu amd_llc_pmu = {
@@ -317,6 +313,7 @@ static struct pmu amd_llc_pmu = {
.start = amd_uncore_start,
.stop = amd_uncore_stop,
.read = amd_uncore_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static struct amd_uncore *amd_uncore_alloc(unsigned int cpu)
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 27a4614..d516161 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -695,14 +695,6 @@ static int uncore_pmu_event_init(struct perf_event *event)
if (pmu->func_id < 0)
return -ENOENT;
- /*
- * Uncore PMU does measure at all privilege level all the time.
- * So it doesn't make sense to specify any exclude bits.
- */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_hv || event->attr.exclude_idle)
- return -EINVAL;
-
/* Sampling not supported yet */
if (hwc->sample_period)
return -EINVAL;
@@ -800,6 +792,7 @@ static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
.stop = uncore_pmu_event_stop,
.read = uncore_pmu_event_read,
.module = THIS_MODULE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
} else {
pmu->pmu = *pmu->type->pmu;
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 09/12] powerpc: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For PowerPC PMUs that do not support context exclusion let's
advertise the PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that
perf will prevent us from handling events where any exclusion flags
are set. Let's also remove the now unnecessary check for exclusion
flags.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/powerpc/perf/hv-24x7.c | 10 +---------
arch/powerpc/perf/hv-gpci.c | 10 +---------
arch/powerpc/perf/imc-pmu.c | 19 +------------------
3 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 72238ee..d2b8e60 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -1306,15 +1306,6 @@ static int h_24x7_event_init(struct perf_event *event)
return -EINVAL;
}
- /* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
/* no branch sampling */
if (has_branch_stack(event))
return -EOPNOTSUPP;
@@ -1577,6 +1568,7 @@ static struct pmu h_24x7_pmu = {
.start_txn = h_24x7_event_start_txn,
.commit_txn = h_24x7_event_commit_txn,
.cancel_txn = h_24x7_event_cancel_txn,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static int hv_24x7_init(void)
diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c
index 43fabb3..735e77b 100644
--- a/arch/powerpc/perf/hv-gpci.c
+++ b/arch/powerpc/perf/hv-gpci.c
@@ -232,15 +232,6 @@ static int h_gpci_event_init(struct perf_event *event)
return -EINVAL;
}
- /* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
/* no branch sampling */
if (has_branch_stack(event))
return -EOPNOTSUPP;
@@ -285,6 +276,7 @@ static struct pmu h_gpci_pmu = {
.start = h_gpci_event_start,
.stop = h_gpci_event_stop,
.read = h_gpci_event_update,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
static int hv_gpci_init(void)
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index 1fafc32b..1dbb0ee 100644
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -473,15 +473,6 @@ static int nest_imc_event_init(struct perf_event *event)
if (event->hw.sample_period)
return -EINVAL;
- /* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
if (event->cpu < 0)
return -EINVAL;
@@ -748,15 +739,6 @@ static int core_imc_event_init(struct perf_event *event)
if (event->hw.sample_period)
return -EINVAL;
- /* unsupported modes and filters */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
if (event->cpu < 0)
return -EINVAL;
@@ -1069,6 +1051,7 @@ static int update_pmu_ops(struct imc_pmu *pmu)
pmu->pmu.stop = imc_event_stop;
pmu->pmu.read = imc_event_update;
pmu->pmu.attr_groups = pmu->attr_groups;
+ pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
switch (pmu->domain) {
--
2.7.4
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v3 07/12] drivers/perf: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For drivers that do not support context exclusion let's advertise the
PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
drivers/perf/arm-cci.c | 10 +---------
drivers/perf/arm-ccn.c | 6 ++----
drivers/perf/arm_dsu_pmu.c | 9 ++-------
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_pmu.c | 9 ---------
7 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c
index 1bfeb16..bfd03e0 100644
--- a/drivers/perf/arm-cci.c
+++ b/drivers/perf/arm-cci.c
@@ -1327,15 +1327,6 @@ static int cci_pmu_event_init(struct perf_event *event)
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EOPNOTSUPP;
- /* We have no filtering of any kind */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
/*
* Following the example set by other "uncore" PMUs, we accept any CPU
* and rewrite its affinity dynamically rather than having perf core
@@ -1433,6 +1424,7 @@ static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev)
.stop = cci_pmu_stop,
.read = pmu_read,
.attr_groups = pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
cci_pmu->plat_device = pdev;
diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c
index 7dd850e..2ae7602 100644
--- a/drivers/perf/arm-ccn.c
+++ b/drivers/perf/arm-ccn.c
@@ -741,10 +741,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
return -EOPNOTSUPP;
}
- if (has_branch_stack(event) || event->attr.exclude_user ||
- event->attr.exclude_kernel || event->attr.exclude_hv ||
- event->attr.exclude_idle || event->attr.exclude_host ||
- event->attr.exclude_guest) {
+ if (has_branch_stack(event)) {
dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
return -EINVAL;
}
@@ -1290,6 +1287,7 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn)
.read = arm_ccn_pmu_event_read,
.pmu_enable = arm_ccn_pmu_enable,
.pmu_disable = arm_ccn_pmu_disable,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
/* No overflow interrupt? Have to use a timer instead. */
diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c
index 660cb8a..5851de5 100644
--- a/drivers/perf/arm_dsu_pmu.c
+++ b/drivers/perf/arm_dsu_pmu.c
@@ -562,13 +562,7 @@ static int dsu_pmu_event_init(struct perf_event *event)
return -EINVAL;
}
- if (has_branch_stack(event) ||
- event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest) {
+ if (has_branch_stack(event)) {
dev_dbg(dsu_pmu->pmu.dev, "Can't support filtering\n");
return -EINVAL;
}
@@ -735,6 +729,7 @@ static int dsu_pmu_device_probe(struct platform_device *pdev)
.read = dsu_pmu_read,
.attr_groups = dsu_pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
rc = perf_pmu_register(&dsu_pmu->pmu, name, -1);
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
index 1b10ea0..296fef8 100644
--- a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
@@ -396,6 +396,7 @@ static int hisi_ddrc_pmu_probe(struct platform_device *pdev)
.stop = hisi_uncore_pmu_stop,
.read = hisi_uncore_pmu_read,
.attr_groups = hisi_ddrc_pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
index 443906e..2553a84 100644
--- a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
@@ -407,6 +407,7 @@ static int hisi_hha_pmu_probe(struct platform_device *pdev)
.stop = hisi_uncore_pmu_stop,
.read = hisi_uncore_pmu_read,
.attr_groups = hisi_hha_pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
ret = perf_pmu_register(&hha_pmu->pmu, name, -1);
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
index 0bde5d9..cf1cc34 100644
--- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
@@ -397,6 +397,7 @@ static int hisi_l3c_pmu_probe(struct platform_device *pdev)
.stop = hisi_uncore_pmu_stop,
.read = hisi_uncore_pmu_read,
.attr_groups = hisi_l3c_pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
ret = perf_pmu_register(&l3c_pmu->pmu, name, -1);
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index 9efd241..f028cbc 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -142,15 +142,6 @@ int hisi_uncore_pmu_event_init(struct perf_event *event)
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EOPNOTSUPP;
- /* counters do not have these bits */
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle)
- return -EINVAL;
-
/*
* The uncore counters not specific to any CPU, so cannot
* support per-task
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 06/12] arm: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For drivers that do not support context exclusion let's advertise the
PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/arm/mach-imx/mmdc.c | 9 ++-------
arch/arm/mm/cache-l2x0-pmu.c | 9 +--------
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index 04b3bf7..3453838 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -293,13 +293,7 @@ static int mmdc_pmu_event_init(struct perf_event *event)
return -EOPNOTSUPP;
}
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest ||
- event->attr.sample_period)
+ if (event->attr.sample_period)
return -EINVAL;
if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS)
@@ -455,6 +449,7 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
.start = mmdc_pmu_event_start,
.stop = mmdc_pmu_event_stop,
.read = mmdc_pmu_event_update,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
},
.mmdc_base = mmdc_base,
.dev = dev,
diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c
index afe5b4c..99bcd07 100644
--- a/arch/arm/mm/cache-l2x0-pmu.c
+++ b/arch/arm/mm/cache-l2x0-pmu.c
@@ -314,14 +314,6 @@ static int l2x0_pmu_event_init(struct perf_event *event)
event->attach_state & PERF_ATTACH_TASK)
return -EINVAL;
- if (event->attr.exclude_user ||
- event->attr.exclude_kernel ||
- event->attr.exclude_hv ||
- event->attr.exclude_idle ||
- event->attr.exclude_host ||
- event->attr.exclude_guest)
- return -EINVAL;
-
if (event->cpu < 0)
return -EINVAL;
@@ -544,6 +536,7 @@ static __init int l2x0_pmu_init(void)
.del = l2x0_pmu_event_del,
.event_init = l2x0_pmu_event_init,
.attr_groups = l2x0_pmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
l2x0_pmu_reset();
--
2.7.4
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v3 08/12] drivers/perf: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
For drivers that do not support context exclusion let's advertise the
PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
This change means that qcom_{l2|l3}_pmu will now also indicate that
they do not support exclude_{host|guest} and that xgene_pmu does
not also support exclude_idle and exclude_hv.
Note that for qcom_l2_pmu we now implictly return -EINVAL instead
of -EOPNOTSUPP. This change will result in the perf userspace
utility retrying the perf_event_open system call with fallback
event attributes that do not fail.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
drivers/perf/qcom_l2_pmu.c | 9 +--------
drivers/perf/qcom_l3_pmu.c | 8 +-------
drivers/perf/xgene_pmu.c | 6 +-----
3 files changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c
index 842135c..091b4d7 100644
--- a/drivers/perf/qcom_l2_pmu.c
+++ b/drivers/perf/qcom_l2_pmu.c
@@ -509,14 +509,6 @@ static int l2_cache_event_init(struct perf_event *event)
return -EOPNOTSUPP;
}
- /* We cannot filter accurately so we just don't allow it. */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_hv || event->attr.exclude_idle) {
- dev_dbg_ratelimited(&l2cache_pmu->pdev->dev,
- "Can't exclude execution levels\n");
- return -EOPNOTSUPP;
- }
-
if (((L2_EVT_GROUP(event->attr.config) > L2_EVT_GROUP_MAX) ||
((event->attr.config & ~L2_EVT_MASK) != 0)) &&
(event->attr.config != L2CYCLE_CTR_RAW_CODE)) {
@@ -982,6 +974,7 @@ static int l2_cache_pmu_probe(struct platform_device *pdev)
.stop = l2_cache_event_stop,
.read = l2_cache_event_read,
.attr_groups = l2_cache_pmu_attr_grps,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
l2cache_pmu->num_counters = get_num_counters();
diff --git a/drivers/perf/qcom_l3_pmu.c b/drivers/perf/qcom_l3_pmu.c
index 2dc63d6..5d70646 100644
--- a/drivers/perf/qcom_l3_pmu.c
+++ b/drivers/perf/qcom_l3_pmu.c
@@ -495,13 +495,6 @@ static int qcom_l3_cache__event_init(struct perf_event *event)
return -ENOENT;
/*
- * There are no per-counter mode filters in the PMU.
- */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_hv || event->attr.exclude_idle)
- return -EINVAL;
-
- /*
* Sampling not supported since these events are not core-attributable.
*/
if (hwc->sample_period)
@@ -777,6 +770,7 @@ static int qcom_l3_cache_pmu_probe(struct platform_device *pdev)
.read = qcom_l3_cache__event_read,
.attr_groups = qcom_l3_cache_pmu_attr_grps,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
memrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c
index 0e31f13..dad6169 100644
--- a/drivers/perf/xgene_pmu.c
+++ b/drivers/perf/xgene_pmu.c
@@ -914,11 +914,6 @@ static int xgene_perf_event_init(struct perf_event *event)
if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
return -EINVAL;
- /* SOC counters do not have usr/os/guest/host bits */
- if (event->attr.exclude_user || event->attr.exclude_kernel ||
- event->attr.exclude_host || event->attr.exclude_guest)
- return -EINVAL;
-
if (event->cpu < 0)
return -EINVAL;
/*
@@ -1133,6 +1128,7 @@ static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
.start = xgene_perf_start,
.stop = xgene_perf_stop,
.read = xgene_perf_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
/* Hardware counter init */
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 03/12] perf/core: add PERF_PMU_CAP_NO_EXCLUDE for exclusion incapable PMUs
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
Many PMU drivers do not have the capability to exclude counting events
that occur in specific contexts such as idle, kernel, guest, etc. These
drivers indicate this by returning an error in their event_init upon
testing the events attribute flags. This approach is error prone and
often inconsistent.
Let's instead allow PMU drivers to advertise their inability to exclude
based on context via a new capability: PERF_PMU_CAP_NO_EXCLUDE. This
allows the perf core to reject requests for exclusion events where
there is no support in the PMU.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
include/linux/perf_event.h | 1 +
kernel/events/core.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index b2e806f..fe92b89 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -244,6 +244,7 @@ struct perf_event;
#define PERF_PMU_CAP_EXCLUSIVE 0x10
#define PERF_PMU_CAP_ITRACE 0x20
#define PERF_PMU_CAP_HETEROGENEOUS_CPUS 0x40
+#define PERF_PMU_CAP_NO_EXCLUDE 0x80
/**
* struct pmu - generic performance monitoring unit
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 5a97f34..5113cfc 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -9743,6 +9743,15 @@ static int perf_try_init_event(struct pmu *pmu, struct perf_event *event)
if (ctx)
perf_event_ctx_unlock(event->group_leader, ctx);
+ if (!ret) {
+ if (pmu->capabilities & PERF_PMU_CAP_NO_EXCLUDE &&
+ event_has_any_exclude_flag(event)) {
+ if (event->destroy)
+ event->destroy(event);
+ ret = -EINVAL;
+ }
+ }
+
if (ret)
module_put(pmu->module);
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 04/12] alpha: perf/core: use PERF_PMU_CAP_NO_EXCLUDE
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
As the Alpha PMU doesn't support context exclusion let's advertise
the PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
This change means that __hw_perf_event_init will now also
indicate that it doesn't support exclude_host and exclude_guest and
will now implicitly return -EINVAL instead of -EPERM. This is likely
more desirable as -EPERM will result in a kernel.perf_event_paranoid
related warning from the perf userspace utility.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
arch/alpha/kernel/perf_event.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 5613aa37..4341ccf 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -630,12 +630,6 @@ static int __hw_perf_event_init(struct perf_event *event)
return ev;
}
- /* The EV67 does not support mode exclusion */
- if (attr->exclude_kernel || attr->exclude_user
- || attr->exclude_hv || attr->exclude_idle) {
- return -EPERM;
- }
-
/*
* We place the event type in event_base here and leave calculation
* of the codes to programme the PMU for alpha_pmu_enable() because
@@ -771,6 +765,7 @@ static struct pmu pmu = {
.start = alpha_pmu_start,
.stop = alpha_pmu_stop,
.read = alpha_pmu_read,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
};
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 05/12] arm: perf: conditionally use PERF_PMU_CAP_NO_EXCLUDE
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
The ARM PMU driver can be used to represent a variety of ARM based
PMUs. Some of these PMUs do not provide support for context
exclusion, where this is the case we advertise the
PERF_PMU_CAP_NO_EXCLUDE capability to ensure that perf prevents us
from handling events where any exclusion flags are set.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
drivers/perf/arm_pmu.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 7f01f6f..ea69067 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -357,13 +357,6 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
}
static int
-event_requires_mode_exclusion(struct perf_event_attr *attr)
-{
- return attr->exclude_idle || attr->exclude_user ||
- attr->exclude_kernel || attr->exclude_hv;
-}
-
-static int
__hw_perf_event_init(struct perf_event *event)
{
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
@@ -393,9 +386,8 @@ __hw_perf_event_init(struct perf_event *event)
/*
* Check whether we need to exclude the counter from certain modes.
*/
- if ((!armpmu->set_event_filter ||
- armpmu->set_event_filter(hwc, &event->attr)) &&
- event_requires_mode_exclusion(&event->attr)) {
+ if (armpmu->set_event_filter &&
+ armpmu->set_event_filter(hwc, &event->attr)) {
pr_debug("ARM performance counters do not support "
"mode exclusion\n");
return -EOPNOTSUPP;
@@ -861,6 +853,9 @@ int armpmu_register(struct arm_pmu *pmu)
if (ret)
return ret;
+ if (!pmu->set_event_filter)
+ pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
+
ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
if (ret)
goto out_destroy;
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 02/12] perf/core: add function to test for event exclusion flags
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
Add a function that tests if any of the perf event exclusion flags
are set on a given event.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
include/linux/perf_event.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 53c500f..b2e806f 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -1004,6 +1004,15 @@ perf_event__output_id_sample(struct perf_event *event,
extern void
perf_log_lost_samples(struct perf_event *event, u64 lost);
+static inline bool event_has_any_exclude_flag(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+
+ return attr->exclude_idle || attr->exclude_user ||
+ attr->exclude_kernel || attr->exclude_hv ||
+ attr->exclude_guest || attr->exclude_host;
+}
+
static inline bool is_sampling_event(struct perf_event *event)
{
return event->attr.sample_period != 0;
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 01/12] perf/doc: update design.txt for exclude_{host|guest} flags
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
In-Reply-To: <1544114849-47266-1-git-send-email-andrew.murray@arm.com>
Update design.txt to reflect the presence of the exclude_host
and exclude_guest perf flags.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
---
tools/perf/design.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tools/perf/design.txt b/tools/perf/design.txt
index a28dca2..0453ba2 100644
--- a/tools/perf/design.txt
+++ b/tools/perf/design.txt
@@ -222,6 +222,10 @@ The 'exclude_user', 'exclude_kernel' and 'exclude_hv' bits provide a
way to request that counting of events be restricted to times when the
CPU is in user, kernel and/or hypervisor mode.
+Furthermore the 'exclude_host' and 'exclude_guest' bits provide a way
+to request counting of events restricted to guest and host contexts when
+using Linux as the hypervisor.
+
The 'mmap' and 'munmap' bits allow recording of PROT_EXEC mmap/munmap
operations, these can be used to relate userspace IP addresses to actual
code, even after the mapping (or even the whole process) is gone,
--
2.7.4
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^ permalink raw reply related
* [PATCH v3 00/12] perf/core: Generalise event exclusion checking
From: Andrew Murray @ 2018-12-06 16:47 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Richard Henderson, Ivan Kokshaysky, Matt Turner, Will Deacon,
Mark Rutland, Shawn Guo, Sascha Hauer, Benjamin Herrenschmidt,
Paul Mackerras, Thomas Gleixner, Borislav Petkov, Russell King,
suzuki.poulose, robin.murphy, Michael Ellerman
Cc: x86, linuxppc-dev, linux-kernel, linux-arm-kernel, linux-alpha
Many PMU drivers do not have the capability to exclude counting events
that occur in specific contexts such as idle, kernel, guest, etc. These
drivers indicate this by returning an error in their event_init upon
testing the events attribute flags.
However this approach requires that each time a new event modifier is
added to perf, all the perf drivers need to be modified to indicate that
they don't support the attribute. This results in additional boiler-plate
code common to many drivers that needs to be maintained. Furthermore the
drivers are not consistent with regards to the error value they return
when reporting unsupported attributes.
This patchset allow PMU drivers to advertise their inability to exclude
based on context via a new capability: PERF_PMU_CAP_NO_EXCLUDE. This
allows the perf core to reject requests for exclusion events where there
is no support in the PMU.
This is a functional change, in particular:
- Some drivers will now additionally (but correctly) report unsupported
exclusion flags. It's typical for existing userspace tools such as
perf to handle such errors by retrying the system call without the
unsupported flags.
- Drivers that do not support any exclusion that previously reported
-EPERM or -EOPNOTSUPP will now report -EINVAL - this is consistent
with the majority and results in userspace perf retrying without
exclusion.
All drivers touched by this patchset have been compile tested.
Changes from v2:
- Invert logic from CAP_EXCLUDE to CAP_NO_EXCLUDE
Changes from v1:
- Changed approach from explicitly rejecting events in unsupporting PMU
drivers to explicitly advertising a capability in PMU drivers that
do support exclusion events
- Added additional information to tools/perf/design.txt
- Rename event_has_exclude_flags to event_has_any_exclude_flag and
update commit log to reflect it's a function
Andrew Murray (12):
perf/doc: update design.txt for exclude_{host|guest} flags
perf/core: add function to test for event exclusion flags
perf/core: add PERF_PMU_CAP_NO_EXCLUDE for exclusion incapable PMUs
alpha: perf/core: use PERF_PMU_CAP_NO_EXCLUDE
arm: perf: conditionally use PERF_PMU_CAP_NO_EXCLUDE
arm: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
drivers/perf: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude
incapable PMUs
drivers/perf: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude
incapable PMUs
powerpc: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable
PMUs
x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs
perf/core: remove unused perf_flags
arch/alpha/kernel/perf_event.c | 7 +------
arch/arm/mach-imx/mmdc.c | 9 ++-------
arch/arm/mm/cache-l2x0-pmu.c | 9 +--------
arch/powerpc/perf/hv-24x7.c | 10 +---------
arch/powerpc/perf/hv-gpci.c | 10 +---------
arch/powerpc/perf/imc-pmu.c | 19 +------------------
arch/x86/events/amd/ibs.c | 13 +------------
arch/x86/events/amd/iommu.c | 6 +-----
arch/x86/events/amd/power.c | 10 ++--------
arch/x86/events/amd/uncore.c | 7 ++-----
arch/x86/events/intel/cstate.c | 12 +++---------
arch/x86/events/intel/rapl.c | 9 ++-------
arch/x86/events/intel/uncore.c | 9 +--------
arch/x86/events/intel/uncore_snb.c | 9 ++-------
arch/x86/events/msr.c | 10 ++--------
drivers/perf/arm-cci.c | 10 +---------
drivers/perf/arm-ccn.c | 6 ++----
drivers/perf/arm_dsu_pmu.c | 9 ++-------
drivers/perf/arm_pmu.c | 15 +++++----------
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 1 +
drivers/perf/hisilicon/hisi_uncore_pmu.c | 9 ---------
drivers/perf/qcom_l2_pmu.c | 9 +--------
drivers/perf/qcom_l3_pmu.c | 8 +-------
drivers/perf/xgene_pmu.c | 6 +-----
include/linux/perf_event.h | 10 ++++++++++
include/uapi/linux/perf_event.h | 2 --
kernel/events/core.c | 9 +++++++++
tools/include/uapi/linux/perf_event.h | 2 --
tools/perf/design.txt | 4 ++++
31 files changed, 62 insertions(+), 189 deletions(-)
--
2.7.4
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^ permalink raw reply
* Re: WIP: UFS on apq8098
From: Evan Green @ 2018-12-06 16:45 UTC (permalink / raw)
To: marc.w.gonzalez
Cc: jhugo, linux-arm-msm, sboyd, Bjorn Andersson, Andy Gross,
nicolas.dechesne, linux-arm-kernel
In-Reply-To: <6b8898b9-a9cb-8a72-0c73-f8a956cf629e@free.fr>
On Thu, Dec 6, 2018 at 8:18 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote:
>
> On 04/12/2018 18:31, Jeffrey Hugo wrote:
>
I'll throw my random thought into the hopper here. With one particular
brand of UFS part on SDM845 we needed to make sure we banged on the
ufs_reset pin before the device would re-initialize fully. My hunch
says this is not your issue, but it can't hurt to make sure this is
happening.
-Evan
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^ permalink raw reply
* Re: [PATCH] arm64: hugetlb: Register hugepages during arch init
From: Steve Capper @ 2018-12-06 16:38 UTC (permalink / raw)
To: Allen Pais
Cc: Anshuman Khandual, Catalin Marinas, Will Deacon,
linux-kernel@vger.kernel.org, nd,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1540256817-3327-1-git-send-email-allen.pais@oracle.com>
On Tue, Oct 23, 2018 at 06:36:57AM +0530, Allen Pais wrote:
> Add hstate for each supported hugepage size using arch initcall.
>
> * no hugepage parameters
>
> Without hugepage parameters, only a default hugepage size is
> available for dynamic allocation. It's different, for example, from
> x86_64 and sparc64 where all supported hugepage sizes are available.
>
> * only default_hugepagesz= is specified and set not to HPAGE_SIZE
>
> In spite of the fact that default_hugepagesz= is set to a valid
> hugepage size, it's treated as unsupported and reverted to
> HPAGE_SIZE. Such behaviour is also different from x86_64 and
> sparc64.
>
> Reviewed-by: Tom Saeger <tom.saeger@oracle.com>
> Signed-off-by: Dmitry Klochkov <dmitry.klochkov@oracle.com>
> Signed-off-by: Allen Pais <allen.pais@oracle.com>
> ---
> arch/arm64/mm/hugetlbpage.c | 33 ++++++++++++++++++++++-----------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> index f58ea50..28cbc22 100644
> --- a/arch/arm64/mm/hugetlbpage.c
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -429,6 +429,27 @@ void huge_ptep_clear_flush(struct vm_area_struct *vma,
> clear_flush(vma->vm_mm, addr, ptep, pgsize, ncontig);
> }
>
> +static void __init add_huge_page_size(unsigned long size)
> +{
> + if (size_to_hstate(size))
> + return;
> +
> + hugetlb_add_hstate(ilog2(size) - PAGE_SHIFT);
> +}
> +
> +static int __init hugetlbpage_init(void)
> +{
> +#ifdef CONFIG_ARM64_4K_PAGES
> + add_huge_page_size(PUD_SIZE);
> +#endif
> + add_huge_page_size(PMD_SIZE * CONT_PMDS);
> + add_huge_page_size(PMD_SIZE);
> + add_huge_page_size(PAGE_SIZE * CONT_PTES);
> +
> + return 0;
> +}
> +arch_initcall(hugetlbpage_init);
> +
> static __init int setup_hugepagesz(char *opt)
> {
> unsigned long ps = memparse(opt, &opt);
> @@ -440,7 +461,7 @@ static __init int setup_hugepagesz(char *opt)
> case PMD_SIZE * CONT_PMDS:
> case PMD_SIZE:
> case PAGE_SIZE * CONT_PTES:
> - hugetlb_add_hstate(ilog2(ps) - PAGE_SHIFT);
> + add_huge_page_size(ps);
> return 1;
> }
>
> @@ -449,13 +470,3 @@ static __init int setup_hugepagesz(char *opt)
> return 0;
> }
> __setup("hugepagesz=", setup_hugepagesz);
> -
> -#ifdef CONFIG_ARM64_64K_PAGES
> -static __init int add_default_hugepagesz(void)
> -{
> - if (size_to_hstate(CONT_PTES * PAGE_SIZE) == NULL)
> - hugetlb_add_hstate(CONT_PTE_SHIFT);
> - return 0;
> -}
> -arch_initcall(add_default_hugepagesz);
> -#endif
> --
> 1.8.3.1
>
Apologies for missing this, I like the idea of having all the hugetlb
sizes accessible right away.
FWIW:
Acked-by: Steve Capper <steve.capper@arm.com>
Cheers,
--
Steve
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^ permalink raw reply
* Re: dmapool regression in next
From: Tony Lindgren @ 2018-12-06 16:33 UTC (permalink / raw)
To: Tony Battersby
Cc: Stephen Rothwell, john.garry, linux, Krzysztof Kozlowski,
linux-kernel, andy.shevchenko, Matthew Wilcox, akpm, linux-omap,
Robin Murphy, hch, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <9187bbd9-3aaf-c1b3-16a3-4e1b3356c52e@cybernetics.com>
* Tony Battersby <tonyb@cybernetics.com> [181206 16:13]:
> On 12/6/18 10:51 AM, Robin Murphy wrote:
> >> Here is the prototype:
> >>
> >> void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t dma);
> >>
> >> With the old code, the 'dma' value had to be correct for use with
> >> pool_find_page(), or else you would get an error. If the 'vaddr' value
> >> was incorrect, it would corrupt the dmapool freelist, but you wouldn't
> >> get an error unless DMAPOOL_DEBUG was enabled.
> >>
> >> With my patch applied, 'vaddr' has to be correct for virt_to_page(). My
> >> code also checks that 'dma' is consistent with 'vaddr' even if
> >> DMAPOOL_DEBUG is disabled, since the check is fast and it will prevent
> >> problems like this in the future.
> > Unfortunately that logic has a fatal flaw - DMA pools are backed by
> > dma_alloc_coherent(), and there is absolutely no guarantee that the
> > memory dma_alloc_coherent() returns is backed by a struct page at all.
> > Even if it is, there is still absolutely no guarantee that the vaddr
> > value it returns is valid for virt_to_page() - on many systems it will
> > be in vmalloc or some architecture-specific region of address space.
> >
> > The problem is not that these drivers are buggy (they're not - the arch
> > code is returning a vmalloc()ed non-cacheable remap in the first place),
> > it's that 26abe88e830d is fundamentally unworkable and needs reverting.
> > Apparently the original patches managed not to catch my eye as something
> > I needed to review, sorry about that :(
> >
> > Robin.
> >
> Thanks for the info; the inner workings of the vm system are a bit out
> of my area of expertise. My first version of the patch series used a
> different method that didn't rely on virt_to_page(); I will go back to
> that version, clean it up, and resubmit when I have time.
>
> Andrew, please revert all 9 patches. I will resubmit the set when I
> have a workable solution.
OK sounds good to me. I can test the new set easily when available
if you Cc me on them.
Thanks,
Tony
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* Re: OMAP4430 SDP with KS8851: very slow networking
From: Tony Lindgren @ 2018-12-06 16:31 UTC (permalink / raw)
To: Russell King - ARM Linux; +Cc: netdev, linux-omap, linux-arm-kernel
In-Reply-To: <20181206132256.GT30658@n2100.armlinux.org.uk>
Hi,
* Russell King - ARM Linux <linux@armlinux.org.uk> [181206 13:23]:
> It looks very much like a receive problem - in that the board is not
> always aware of a packet having been received until it attempts to
> transmit (eg, in the case of TFTP, when it re-sends the ACK after a
> receive timeout, it _then_ notices that there's a packet waiting.)
>
> I'm not quite sure when this cropped up as I no longer regularly
> update and run my nightly boot tests, but I think 4.18 was fine.
Sounds like it's some gpio or PM related issue. If it's not caused
by commit b764a5863fd8 ("gpio: omap: Remove custom PM calls and
use cpu_pm instead"), then maybe the changes to probe devices
with ti-sysc interconnect target module driver caused it. Below
is a revert for mcspi that would help in that case.
Also I guess it could be caused by drivers/spi/spi-omap2-mcspi.c
changes since v4.18.
Care to post output of /sys/kernel/debug/pm_debug/count for
a working and non-working kernels?
Regards,
Tony
8< -------------------
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -2050,25 +2050,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x98000 0x1000>;
-
- mcspi1: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
+ status = "disabled";
};
target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
@@ -2089,20 +2071,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x9a000 0x1000>;
-
- mcspi2: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
+ status = "disabled";
};
target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
@@ -2290,17 +2259,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xb8000 0x1000>;
-
- mcspi3: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
- dma-names = "tx0", "rx0";
- };
+ status = "disabled";
};
target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
@@ -2321,17 +2280,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xba000 0x1000>;
-
- mcspi4: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
- dma-names = "tx0", "rx0";
- };
+ status = "disabled";
};
target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -193,6 +193,66 @@
#gpio-cells = <2>;
};
+ mcspi1: spi@48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ };
+
+ mcspi2: spi@4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ mcspi3: spi@480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ };
+
+ mcspi4: spi@480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ };
+
+
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
--
2.19.2
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* Re: [PATCH 0/2] meson: Fix IRQ trigger type
From: Emiliano Ingrassia @ 2018-12-06 16:24 UTC (permalink / raw)
To: Jerome Brunet, Martin Blumenstingl, Carlo Caione
Cc: mark.rutland, devicetree, khilman, robh+dt, linux-amlogic,
linux-arm-kernel
In-Reply-To: <8dd5d9da52d799f5b87272d276754e21a5e93464.camel@baylibre.com>
Hi Jerome,
On Thu, Dec 06, 2018 at 02:26:34PM +0100, Jerome Brunet wrote:
> On Thu, 2018-12-06 at 13:43 +0100, Emiliano Ingrassia wrote:
> > Hi all,
> >
> > thank you for involving me.
> >
> > I applied Carlo's patches[0] on a kernel vanilla 4.19.6
> > and tested it with kernel packet generator, monitoring
> > bandwidth usage with "nload".
> >
> > All tests were conducted on an Odroid-C1+ Rev. 0.4-20150930 board
> > with a short ethernet cable directly attached to a laptop with
> > 1G ethernet interface, with "nload" running on the board.
> >
> > The tests I performed are composed by the following steps:
> >
> > 1) Start packet generator with "rate 1000M" on laptop;
> >
> > 2) Keep packet generator active on the laptop and
> > start the packet generator on the board with "rate 1000M";
> >
> > 3) Stop both packet generators;
> >
> > 4) Start packet generator on the board;
> >
> > 5) Keep packet generator active on the board and
> > start the packet generator on the laptop.
> >
> >
> > Test results without Carlo's patches applied:
> >
> > 1) "nload" shows an incoming traffic of ~950Mbps;
> >
> > 2) "nload" shows an incoming traffic of ~400Mbps
> > and an outgoing traffic of ~250Mbps;
> >
> > 3) "nload" shows 0Mbps both for incoming and outgoing traffic;
> >
> > 4) "nload" shows an outgoing traffic of ~950Mbps from the board;
> >
> > 5) "nload" shows incoming traffic of 0Mbps
> > and an outgoing traffic of ~950Mbps.
> >
> > Applying only the first patch (change mac IRQ type) I got the same results.
> >
> > Applying only the second patch (drop eee-broken-1000t) I got the same
> > results!
> >
> > With both patches applied I got the same results but with an incoming
> > traffic
> > of ~3Mbps on the board.
>
> Are you sure you did not mix up the result ?
> I would expect this kind of drop when only the eee patch is applied.
Yes, I'm sure.
>
> >
> > Consider that the described tests were performed for a few minutes.
> >
> >
> > The tests I performed clearly show that currently the MAC does not
> > perform as 1G full-duplex.
>
> Do you really get 1G full duplex w/o any of these patch ?
> I would be surprised if they had any meaningful impact on throughput
As I wrote in the previous mail, without the two patches applied
I see an incoming traffic on the board of about 460 Mbps and an outgoing
of 256 Mbps.
On the laptop side I see an outgoing of about 940 Mbps and an incoming
of about 256 Mbps.
So it seems that the board (without the Carlo's patches) is losing traffic.
I'll keep investigating to see if they can solve this problem.
>
> > I can't say if this depends on the hardware, the driver or
> > the IP description in the board's device tree.
> >
> > From the results shown above I think that the patches regarding 32 bit
> > Meson SoCs should NOT be applied together, but you can consider to apply
> > only the second one which remove the "eee-broken-1000t" flag
> > from the board MAC IP description.
>
> I would defenitely advise against that.
>
> > In particular, I think that more tests are needed to better understand
> > what's happening in the case of Meson8b SoC.
> >
> > To better investigate the MAC behaviour on Odroid-C1+, should I use
> > the Amlogic development kernel[1]? If yes, what branch should I use?
>
> And bit of background:
> The MAC found in all Amlogic SoC we have seen so far comes from Synopsys
> (dwmac).
Yes, I know. I was referring to the patches regarding Meson8b SoCs
currently not in mainline that possibly can impact this problem.
>
> The kernel provided by the vendor use the IRQ type 'EDGE_RISING' for this IP
> This means that the HW block is supposed to generate a rising edge on the irq
> line every time there is an event. This is opposed to the Type "LEVEL_HIGH"
> with keep the irq line high as long as their pending IRQs
>
> Of course, when adding mainline support, we did the same as the vendor without
> thinking about it
>
> We started to investigate the network because, after a while, we noticed
> severe performance drops on the AXG family: the throughput would drop from
> 900MBps to 30MBps after somethings 12+ hours of iperf tests.
>
> We noticed that irqs were not triggered anymore. Manually acking the IRQ in
> the register would revive the interface. Since the IRQ is supposed to be acked
> in the ISR, we were clearly missing IRQs and as a consequence, never acking
> them.
>
> All HW using the dwmac out there are using "LEVEL_HIGH", except amlogic.
> Changing this fixes the problem.
>
> Now regarding EEE: about 2 years ago, the network would break on the OC-2. We
> noticed the EEE was generating a *LOT* of IRQs. Deactivating EEE solved the
> problem ... or so we thought. Fact is, it was an un-acked IRQ as well, and we
> just made it harder to trigger by disabling EEE.
>
> So applying the EEE patch without the IRQ_LEVEL would clearly be a mistake,
> you would be back in the situation we investigated 2 years, with a very
> unstable ethernet connection.
>
> Anyways, I have been able to test it on S905 and A113 and I think this series
> should applied, at least for the arm64 family ... most likely of all.
>
> If issues persist on meson8, maybe there is something else ? soemthing hidden
> before ?
>
> >
> >
> > On Tue, Dec 04, 2018 at 08:59:20PM +0100, Martin Blumenstingl wrote:
> > > adding Emiliano because he experienced high packet loss on Odroid-C1
> > > without "eee-broken-1000t"
> > >
> > > On Tue, Dec 4, 2018 at 5:05 PM Carlo Caione <ccaione@baylibre.com> wrote:
> > > > The wrong IRQ trigger type for the macirq was causing the connection
> > > > speed to drop after a few hours when stress testing the DUT. The fix
> > > > seems also to fix another long standing issue with EEE.
> >
> > Carlo, can you describe precisely the tests you conducted
> > on your board and the tools used?
> >
> >
> > > the other two DesignWare controllers (2x dwc2) are also using
> > > IRQ_TYPE_LEVEL_HIGH
> > > so this is not unlikely - good job detective!
> > >
> >
> > Consider that currently the USB ports do not work correctly.
> > In particular, USB pendrive insertion is not recognized at runtime.
> >
> >
> > > > The fixes are tested on a AXG board but we think that the same fix is
> > > > valid also for all the others Amlogic SoC families.
> > > I checked Amlogic's 3.10 kernel for the 32-bit SoCs and it seems they
> > > are setting all IRQs to be edge triggered: [0]
> > > however, Emiliano reported an issue with IRQ_TYPE_EDGE_RISING for the
> > > dwc2 controllers as well. 291f45dd6da5fa6 "ARM: dts: meson: fixing USB
> > > support on Meson6, Meson8 and Meson8b" fixed it for him whereas it
> > > worked for me with IRQ_TYPE_EDGE_RISING
> > >
> > > I find it strange though that Amlogic's buildroot kernel (even the
> > > latest buildroot_openlinux_kernel_4.9_fbdev_20180706) uses:
> > > interrupts = <0 8 1>
> > > which translates to:
> > > interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>
> > >
> > > does the datasheet give a hint that this IRQ should be level triggered
> > > or did you find out by trial and error?
> > >
> > > > Carlo Caione (2):
> > > > arm64: dts: meson: Fix IRQ trigger type for macirq
> > > > arm64: dts: meson: Remove eee-broken-1000t quirk
> > > >
> > > > arch/arm/boot/dts/meson.dtsi | 2 +-
> > > > arch/arm/boot/dts/meson8b-odroidc1.dts | 1 -
> > > these two should be in separate patches with "ARM: dts: " as prefix
> > >
> > > > arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 1 -
> > > > arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +-
> > > > arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
> > > > arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 1 -
> > > > arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 1 -
> > > > 7 files changed, 3 insertions(+), 7 deletions(-)
> > > >
> > > > --
> > > > 2.19.1
> > > >
> > >
> > > Regards
> > > Martin
> > >
> > > [0]
> > > https://github.com/endlessm/linux-meson/blob/cd4096c3ff4eb5b8a8a5581bb46508601c5470dc/drivers/irqchip/irq-gic.c#L400
> > >
> > > _______________________________________________
> > > linux-amlogic mailing list
> > > linux-amlogic@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-amlogic
> >
> > Best regards,
> >
> > Emiliano
> >
> > [0]
> > http://lists.infradead.org/pipermail/linux-amlogic/2018-December/009325.html
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git/
> >
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
>
Emiliano
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* Re: [PATCH v2 3/3] arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1
From: Jagan Teki @ 2018-12-06 16:18 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai, Rob Herring,
Michael Trimarchi, linux-amarula, linux-arm-kernel
In-Reply-To: <20181206153532.6c756gccmpuj4wdw@flea>
On Thu, Dec 6, 2018 at 9:05 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Thu, Dec 06, 2018 at 06:53:06PM +0530, Jagan Teki wrote:
> > Some camera modules have the SoC feeding a master clock to the sensor
> > instead of having a standalone crystal. This clock signal is generated
> > from the clock control unit and output from the CSI MCLK function of
> > pin PE1.
> >
> > Add a pinmux setting for it for camera sensors to reference.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> > Changes for v2:
> > - new patch
> >
> > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > index d7ab0006ebce..902b5238f1dd 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -538,6 +538,11 @@
> > function = "csi0";
> > };
> >
> > + csi_mclk_pin: csi-mclk {
> > + pins = "PE1";
> > + function = "csi0";
> > + };
> > +
>
> We're not merging nodes that have no users.
Yes, v1 [1] has a consumer for this. Since it's under discussion about
PE group supply, opendrain I hold it. will send once the discussion
done, I even tested on top-of your ov5640 changes.
[1] https://patchwork.kernel.org/patch/10709077/
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