* Re: [PATCH] PCI: controller: dwc: Make PCI_IMX6 depend on PCIEPORTBUS
From: Andrey Smirnov @ 2018-12-07 4:55 UTC (permalink / raw)
To: Lucas Stach
Cc: Dong Aisheng, Richard Zhu, linux-pci, linux-kernel, linux-imx,
Bjorn Helgaas, Leonard Crestez, Chris Healy, linux-arm-kernel
In-Reply-To: <1544092136.3709.57.camel@pengutronix.de>
On Thu, Dec 6, 2018 at 2:28 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Mittwoch, den 05.12.2018, 23:45 -0800 schrieb Andrey Smirnov:
> > Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n
> > produces a system where built-in PCIE bridge (16c3:abcd) isn't bound
> > to pcieport driver. This, in turn, results in a PCIE bus that is
> > capable of enumerating attached PCIE device, but lacks functional
> > interrupt support.
>
> This is odd. AFAIK PCI port services are a totally optional thing and
> them being absent should not lead to a non-functional PCI bus. So I
> would really like to see some deeper analysis what is going on here.
>
AFAICT, this is due to pcieport driver enabling MSI of the bridge
device (16c3:abcd) via pcie_port_device_register() ->
pcie_init_service_irqs() -> pcie_port_enable_irq_vec() -> etc.
I did an experiment on a i.MX8MQ/PCIE -> i210 setup I have: I disabled
CONFIG_PCIEPORTBUS and hacked igb_main.c enough to make the i210
driver believe it should fall back onto legacy interrupts. Even
without pcieport present in the system, i210 worked as expected via
legacy interrupts, which seems to collaborate my conjecture above.
Thanks,
Andrey Smirnov
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* Re: [PATCH 0/2] meson: Fix IRQ trigger type
From: Kevin Hilman @ 2018-12-07 4:17 UTC (permalink / raw)
To: Carlo Caione, robh+dt, mark.rutland, devicetree, linux-arm-kernel,
linux-amlogic, martin.blumenstingl
Cc: Carlo Caione
In-Reply-To: <20181204160447.27869-1-ccaione@baylibre.com>
Carlo Caione <ccaione@baylibre.com> writes:
> The wrong IRQ trigger type for the macirq was causing the connection
> speed to drop after a few hours when stress testing the DUT. The fix
> seems also to fix another long standing issue with EEE.
>
> The fixes are tested on a AXG board but we think that the same fix is
> valid also for all the others Amlogic SoC families.
For broader testing, I've created a v4.21/dt64-testing branch (on top of
the current v4.21/dt64 branch) which I've merged into the integ branch
so it gets a spin through kernelCI.org, and others can easily test the
integ branch which has all the other stuff currently queued for v4.21.
I´ll wait for the discussions to settle down and testing results before
deciding whether to officially queue this for v4.21.
Kevin
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* Re: [RFC PATCH 4/6] dt-bindings: update mvneta binding document
From: Kishon Vijay Abraham I @ 2018-12-07 4:07 UTC (permalink / raw)
To: Rob Herring, Russell King
Cc: Mark Rutland, devicetree, Jason Cooper, Andrew Lunn, netdev,
Gregory CLEMENT, Maxime Chevallier, Thomas Petazzoni,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Sebastian Hesselbarth
In-Reply-To: <CAL_JsqJXMDqQVQJoq0sXn0VEA1iFpcsK+Hjsxwt-7aWNreAkPw@mail.gmail.com>
Hi Russell,
On 05/12/18 9:00 PM, Rob Herring wrote:
> On Wed, Dec 5, 2018 at 5:00 AM Russell King - ARM Linux
> <linux@armlinux.org.uk> wrote:
>>
>> On Mon, Dec 03, 2018 at 05:54:55PM -0600, Rob Herring wrote:
>>> On Mon, Nov 12, 2018 at 12:31:02PM +0000, Russell King wrote:
>>>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>>>
>>> Needs a better subject and a commit msg.
>>
>> Hmm, not sure why it didn't contain:
>>
>> "dt-bindings: net: mvneta: add phys property
>>
>> Add an optional phys property to the mvneta binding documentation for
>> the common phy.
>>
>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>"
>>
>> as the commit message. With the correct commit message, are you happy
>> with it?
>
> Yes.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Are you planning to resend this series?
Thanks
Kishon
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* [PATCH -next] usb: mtu3: fix dbginfo in qmu_tx_zlp_error_handler
From: YueHaibing @ 2018-12-07 3:52 UTC (permalink / raw)
To: Chunfeng Yun, Greg Kroah-Hartman, Matthias Brugger
Cc: linux-mediatek, kernel-janitors, linux-usb, YueHaibing,
linux-arm-kernel
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/usb/mtu3/mtu3_qmu.c: In function 'qmu_tx_zlp_error_handler':
drivers/usb/mtu3/mtu3_qmu.c:385:22: warning:
variable 'req' set but not used [-Wunused-but-set-variable]
It seems dbginfo original intention is print 'req' other than 'mreq'
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
drivers/usb/mtu3/mtu3_qmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/mtu3/mtu3_qmu.c b/drivers/usb/mtu3/mtu3_qmu.c
index 73ac042..09f19f7 100644
--- a/drivers/usb/mtu3/mtu3_qmu.c
+++ b/drivers/usb/mtu3/mtu3_qmu.c
@@ -402,7 +402,7 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
return;
}
- dev_dbg(mtu->dev, "%s send ZLP for req=%p\n", __func__, mreq);
+ dev_dbg(mtu->dev, "%s send ZLP for req=%p\n", __func__, req);
mtu3_clrbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
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* Re: [PATCH] ARM: dts: imx51-zii-rdu1: Do not specify "power-gpio" for hpa1
From: Chris Healy @ 2018-12-07 3:32 UTC (permalink / raw)
To: Fabio Estevam; +Cc: Andrey Smirnov, Shawn Guo, linux ARM, Lucas Stach
In-Reply-To: <1544139677-16904-1-git-send-email-festevam@gmail.com>
> From: Andrey Smirnov <andrew.smirnov@gmail.com>
>
> TPA6130A2 SD pin on RDU1 is not really controlled by SoC and instead
> is only meant to notify the system that audio was "muted" by external
> actors. To accommodate that, drop "power-gpio" property of hpa1 node as
> well as specify a name for that GPIO so that userspace can access it.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
> arch/arm/boot/dts/imx51-zii-rdu1.dts | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
> index 28e9dca..a8220f0 100644
> --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
> +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
> @@ -478,6 +478,15 @@
> };
>
> &gpio1 {
> + gpio-line-names = "", "", "", "",
> + "", "", "", "",
Tested-by: Chris Healy <cphealy@gmail.com>
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* Re: [PATCH v2 0/3] PCIE support for i.MX8MQ
From: Andrey Smirnov @ 2018-12-07 2:44 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: Dong Aisheng, Mark Rutland, Richard Zhu, linux-arm-kernel,
Rob Herring, linux-pci, linux-kernel, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-imx, Bjorn Helgaas, Leonard Crestez, Chris Healy,
Lucas Stach
In-Reply-To: <20181206121550.GA2725@e107981-ln.cambridge.arm.com>
On Thu, Dec 6, 2018 at 4:15 AM Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
>
> On Wed, Dec 05, 2018 at 11:35:42PM -0800, Andrey Smirnov wrote:
> > Everyone:
> >
> > This series contains changes I made in order to enable support of PCIE
> > IP block on i.MX8MQ SoCs (full tree can be found at [github-v2]).
> >
> > NOTE: The last patch have a Kconfig symbol depenency on [imx8mq-kconfig].
> >
> > Changes since [v1]:
> >
> > - Driver changed to use single "fsl,controller-id" property to
> > distinguish between two intances of PCIE IP block
> >
> > - All code pertaining to L1SS was dropped to simplify the patch
> >
> > - Documented additions to DT bindings
> >
> > Feedback is welcome!
> >
> > Thanks,
> > Andrey Smirnov
>
> Andrey,
>
> I have applied the patches, I would like to make the CC list in standard
> format so I kindly ask you firstname/surname for cphealy@gmail.com, I
> could not find it in the maintainers list but I want to keep the CC
> list as per patches (I removed the lists, though).
Oh, sorry about that! That would be Chris Healy <cphealy@gmail.com>.
Let me know if anything else is needed.
Thanks,
Andrey Smirnov
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* Re: [PATCH v2 00/14] rtc: sun6i: clock rework and pre-H6 SoC support
From: Chen-Yu Tsai @ 2018-12-07 2:25 UTC (permalink / raw)
To: alexandre.belloni
Cc: linux-rtc, Alessandro Zummo, devicetree, Maxime Ripard,
Mike Turquette, linux-kernel, Stephen Boyd, linux-sunxi,
Rob Herring, Mark Rutland, linux-clk, linux-arm-kernel
In-Reply-To: <20181206203419.GD8952@piout.net>
On Fri, Dec 7, 2018 at 4:34 AM Alexandre Belloni
<alexandre.belloni@bootlin.com> wrote:
>
> On 06/12/2018 13:49:10+0800, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Mon, Dec 3, 2018 at 10:58 PM Chen-Yu Tsai <wens@csie.org> wrote:
> > >
> > > Hi everyone,
> > >
> > > This is v2 of my rtc-sun6i clean-up series.
> > >
> > > Changes since v1:
> > >
> > > - Collected tags
> > > - Dropped patch "clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC
> > > output"; already merged
> > > - Removed H6 compatible CLK_OF_DECLARE_DRIVER entry that wasn't
> > > overlooked
> > > - Only export IOSC clock for A64/H3/H5
> > >
> > > Original cover letter, with patch numbers corrected, follows:
> > >
> > > This series was started as part of enabling Bluetooth on various
> > > Allwinner SBCs. The bluetooth controller requires a precise 32.768 kHz
> > > clock fed to it to correctly detect the frequency of its main oscillator.
> > > This clock signal is provided by the RTC, either directly from a special
> > > pin on the SoC, or some clock output function from the clock controllers.
> > > I found that the clock-related properties of the RTC on later SoCs were
> > > incorrect or missing.
> > >
> > > This series reworks the compatible strings and clock parts of the device
> > > tree bindings for sun6i-rtc. Currently we assume most Allwinner SoCs use
> > > the same sun6i-rtc variant, when in fact they do not. The differences
> > > that matter with regards to clocks are a) the A31 does not have an extra
> > > external output for the RTC 32K clock, while most of the others do;
> > > b) the clock frequency of the internal RC oscillator is different on
> > > some SoCs; c) on the H6 the RTC also handles the 24 MHz DCXO, which
> > > feeds the system HOSC. The last difference, and by extension the H6, are
> > > not covered in this series.
> > >
> > > Patch 1 cleans up the clock-related section of the RTC device tree
> > > binding. This would make it easier to read and easier to add additional
> > > clocks.
> > >
> > > Patch 2 adds compatible strings for all identified variants introduced
> > > prior to the H6.
> > >
> > > Patch 3 deprecates the external clock output for the A31. The A31 does
> > > not have this output, so it's introduction and usage was an error.
> > >
> > > Patch 4 adds a clock output for the RTC's internal oscillator to the
> > > device tree binding. This feeds the PRCM in some SoCs.
> > >
> > > Patch 5 adds a default clock name for the LOSC to the RTC driver.
> > >
> > > Patch 6 adds support for different hardware variants to the RTC driver.
> > >
> > > Patch 7 adds support for all known pre-H6 variants.
> > >
> > > Patch 8 exposes the RTC's internal oscillator through the device tree.
> > >
> > > Patch 9 through 14 adds an RTC node or fixes up the RTC device node
> > > address ranges, clock properties, names of existing clocks, and adds
> > > accuracy properties for the external fixed oscillators.
> > >
> > > The clock names require fixing because the sunxi clock driver implicitly
> > > depends on the HOSC and LOSC being named "osc24M" and "osc32k". The
> > > "fixes" to the clock hierarchy introduced in this series means the names
> > > must also be shuffled around or the in kernel representation would be
> > > incorrect. This has been the case since the sunxi-ng drivers were
> > > introduced. There are plans to address this, but the code is still in its
> > > early stages.
> > >
> > > Please have a look.
> > >
> > > Thanks
> > > ChenYu
> > >
> > > Chen-Yu Tsai (14):
> > > dt-bindings: rtc: sun6i-rtc: Rewrite clock outputs as a list
> > > dt-bindings: rtc: sun6i-rtc: Add compatible strings for pre-H6
> > > variants
> > > dt-bindings: rtc: sun6i-rtc: Deprecate external clock output for A31
> > > dt-bindings: rtc: sun6i-rtc: Export internal RC oscillator
> > > rtc: sun6i: Add default clock name for LOSC
> > > rtc: sun6i: Add support for different variants
> > > rtc: sun6i: Add support for all known pre-H6 variants
> > > rtc: sun6i: Expose internal oscillator through device tree
>
> I've applied the above patches. However, for whatever reason, patch 3
> didn't apply without some fuzz, please check.
Sorry about that. The fuzz was due to a patch that I forgot to send out.
The fixup looks good.
I applied the remaining device tree patches. I'll send out the missing
patch, which fixes the register range in the binding example, later.
Thanks!
ChenYu
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* arm64: WARN_ON_ONCE issue when resuming from hibernation
From: Kunihiko Hayashi @ 2018-12-07 1:40 UTC (permalink / raw)
To: arm, linux-arm-kernel
Hello all,
I found that a WARN_ON_ONCE dump occured in the resuming sequence from
hibernation on arm64 SoC (I use UniPhier LD20 environment).
...
Disabling non-boot CPUs ...
CPU1: shutdown
psci: CPU1 killed.
CPU2: shutdown
psci: CPU2 killed.
CPU3: shutdown
psci: CPU3 killed.
WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1
...
I show the result of reading the code, however,
I'm not sure that this issue occurs in other arm64 SoC.
In the resuming sequence, once all CPUs are stopped and local IRQs
are disabled [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/power/hibernate.c?h=v4.20-rc4#n450
In case of arm64, flush_icache_range() will be called after that.
This calls kick_all_cpus_sync() to sync all CPUs with IPI, and
since local IRQs are disabled, WARN_ON_ONCE() will be called in
smp_call_function_many() [2].
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/smp.c?h=v4.20-rc4#n415
The following tree shows a part of the callgraph.
resume_target_kernel()
+- local_irq_disable()
+- swsusp_arch_resume() /* for arm64 */
+- create_safe_exec_page() /* for arm64 */
+- flush_icache_range() /* for arm64 */
+- kick_all_cpus_sync()
+- smp_call_function()
+- smp_call_function_many()
+- WARN_ON_ONCE(irq_disabled())
What is the possible way to solve this issue?
Thank you,
---
Best Regards,
Kunihiko Hayashi
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* Re: [PATCH 2/3] dt-bindings: drm/panel: simple: add support for PDA 91-00156-A0
From: Rob Herring @ 2018-12-06 23:45 UTC (permalink / raw)
To: Eugen.Hristev
Cc: mark.rutland, devicetree, airlied, linux-kernel, dri-devel,
thierry.reding, Cristian.Birsan, linux-arm-kernel
In-Reply-To: <1542789804-4584-3-git-send-email-eugen.hristev@microchip.com>
On Wed, Nov 21, 2018 at 08:48:00AM +0000, Eugen.Hristev@microchip.com wrote:
> From: Cristian Birsan <cristian.birsan@microchip.com>
>
> PDA 91-00156-A0 5.0 is a 5.0" WVGA TFT LCD panel.
> This panel with backlight is found in PDA 5" LCD screen (TM5000 series or
> AC320005-5).
> Adding Device Tree bindings for this panel.
>
> Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
> ---
> .../devicetree/bindings/display/panel/pda,91-00156-a0.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt
>
> diff --git a/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt b/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt
> new file mode 100644
> index 0000000..52f0da9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt
> @@ -0,0 +1,7 @@
> +PDA 91-00156-A0 5.0" WVGA TFT LCD panel
> +
> +Required properties:
> +- compatible: should be "pda,91-00156-a0"
> +
> +This binding is compatible with the simple-panel binding, which is specified
> +in simple-panel.txt in this directory.
You need to explicitly list what properties from this are used. Does
this have a single supply or did you just forget to add supplies for
example? I don't know.
Rob
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* [PATCH] thermal: uniphier: Convert to SPDX identifier
From: Kunihiko Hayashi @ 2018-12-07 1:06 UTC (permalink / raw)
To: Zhang Rui, Eduardo Valentin, Daniel Lezcano, Masahiro Yamada
Cc: Kunihiko Hayashi, linux-kernel, linux-arm-kernel, linux-pm
This converts license boilerplate to SPDX identifier, and removes
unnecessary lines.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/thermal/uniphier_thermal.c | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/thermal/uniphier_thermal.c b/drivers/thermal/uniphier_thermal.c
index 55477d7..bba2284 100644
--- a/drivers/thermal/uniphier_thermal.c
+++ b/drivers/thermal/uniphier_thermal.c
@@ -1,21 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/**
* uniphier_thermal.c - Socionext UniPhier thermal driver
- *
* Copyright 2014 Panasonic Corporation
* Copyright 2016-2017 Socionext Inc.
- * All rights reserved.
- *
* Author:
* Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 of
- * the License as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bitops.h>
--
2.7.4
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* Re: [PATCH v3 2/2] ARM: dts: aspeed: Add Facebook Backpack-CMM BMC
From: Tao Ren @ 2018-12-07 0:55 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, OpenBMC Maillist, linux-aspeed@lists.ozlabs.org,
Linux ARM
In-Reply-To: <CACPK8XfVHDwso=kMXjk_6Q0eEJTQxUC5B=onqLfw6QzAYZU7vQ@mail.gmail.com>
On 12/2/18, 2:59 PM, "Joel Stanley" <joel@jms.id.au> wrote:
> On Fri, 9 Nov 2018 at 11:20, Tao Ren <taoren@fb.com> wrote:
>>
>> Add initial version of device tree file for Facebook Backpack CMM
>> (Chasis Management Module) ast2500 BMC.
>>
>> Signed-off-by: Tao Ren <taoren@fb.com>
>
> Thanks. I've merged v3 for inclusion in 4.21.
Thank you Joel!
Cheers,
Tao
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* [PATCH v5 2/2] PCI: uniphier: Add UniPhier PCIe host controller support
From: Kunihiko Hayashi @ 2018-12-07 0:53 UTC (permalink / raw)
To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Mark Rutland,
Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-pci,
linux-kernel, Jassi Brar, Gustavo Pimentel, linux-arm-kernel
In-Reply-To: <1544143992-16385-1-git-send-email-hayashi.kunihiko@socionext.com>
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
MAINTAINERS | 7 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-uniphier.c | 471 +++++++++++++++++++++++++++++
4 files changed, 489 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-uniphier.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 48a65c3..f735af2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11332,6 +11332,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
F: drivers/pci/controller/pci-v3-semi.c
+PCIE DRIVER FOR SOCIONEXT UNIPHIER
+M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+L: linux-pci@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/uniphier-pcie.txt
+F: drivers/pci/controller/dwc/pcie-uniphier.c
+
PCIE DRIVER FOR ST SPEAR13XX
M: Pratyush Anand <pratyush.anand@gmail.com>
L: linux-pci@vger.kernel.org
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 91b0194..9550688 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,14 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCIE_UNIPHIER
+ bool "Socionext UniPhier PCIe controllers"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF && HAS_IOMEM
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support on UniPhier SoCs.
+ This driver supports LD20 and PXs3 SoCs.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cbde733 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
new file mode 100644
index 0000000..d5dc402
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for UniPhier SoCs
+ * Copyright 2018 Socionext Inc.
+ * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "pcie-designware.h"
+
+#define PCL_PINCTRL0 0x002c
+#define PCL_PERST_PLDN_REGEN BIT(12)
+#define PCL_PERST_NOE_REGEN BIT(11)
+#define PCL_PERST_OUT_REGEN BIT(8)
+#define PCL_PERST_PLDN_REGVAL BIT(4)
+#define PCL_PERST_NOE_REGVAL BIT(3)
+#define PCL_PERST_OUT_REGVAL BIT(0)
+
+#define PCL_PIPEMON 0x0044
+#define PCL_PCLK_ALIVE BIT(15)
+
+#define PCL_APP_READY_CTRL 0x8008
+#define PCL_APP_LTSSM_ENABLE BIT(0)
+
+#define PCL_APP_PM0 0x8078
+#define PCL_SYS_AUX_PWR_DET BIT(8)
+
+#define PCL_RCV_INT 0x8108
+#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
+#define PCL_CFG_BW_MGT_STATUS BIT(4)
+#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
+#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
+#define PCL_CFG_PME_MSI_STATUS BIT(1)
+
+#define PCL_RCV_INTX 0x810c
+#define PCL_RCV_INTX_ALL_ENABLE GENMASK(19, 16)
+#define PCL_RCV_INTX_ALL_MASK GENMASK(11, 8)
+#define PCL_RCV_INTX_MASK_SHIFT 8
+#define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
+#define PCL_RCV_INTX_STATUS_SHIFT 0
+
+#define PCL_STATUS_LINK 0x8140
+#define PCL_RDLH_LINK_UP BIT(1)
+#define PCL_XMLH_LINK_UP BIT(0)
+
+struct uniphier_pcie_priv {
+ void __iomem *base;
+ struct dw_pcie pci;
+ struct clk *clk;
+ struct reset_control *rst;
+ struct phy *phy;
+ struct irq_domain *legacy_irq_domain;
+};
+
+#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
+
+static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
+ bool enable)
+{
+ u32 val;
+
+ val = readl(priv->base + PCL_APP_READY_CTRL);
+ if (enable)
+ val |= PCL_APP_LTSSM_ENABLE;
+ else
+ val &= ~PCL_APP_LTSSM_ENABLE;
+ writel(val, priv->base + PCL_APP_READY_CTRL);
+}
+
+static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
+{
+ u32 val;
+
+ /* use auxiliary power detection */
+ val = readl(priv->base + PCL_APP_PM0);
+ val |= PCL_SYS_AUX_PWR_DET;
+ writel(val, priv->base + PCL_APP_PM0);
+
+ /* assert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
+ | PCL_PERST_PLDN_REGVAL);
+ val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
+ | PCL_PERST_PLDN_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+
+ uniphier_pcie_ltssm_enable(priv, false);
+
+ usleep_range(100000, 200000);
+
+ /* deassert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+}
+
+static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
+{
+ u32 status;
+ int ret;
+
+ /* wait PIPE clock */
+ ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
+ status & PCL_PCLK_ALIVE, 100000, 1000000);
+ if (ret) {
+ dev_err(priv->pci.dev,
+ "Failed to initialize controller in RC mode\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int uniphier_pcie_link_up(struct dw_pcie *pci)
+{
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ u32 val, mask;
+
+ val = readl(priv->base + PCL_STATUS_LINK);
+ mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
+
+ return (val & mask) == mask;
+}
+
+static int uniphier_pcie_establish_link(struct dw_pcie *pci)
+{
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+
+ if (dw_pcie_link_up(pci))
+ return 0;
+
+ uniphier_pcie_ltssm_enable(priv, true);
+
+ return dw_pcie_wait_for_link(pci);
+}
+
+static void uniphier_pcie_stop_link(struct dw_pcie *pci)
+{
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+
+ uniphier_pcie_ltssm_enable(priv, false);
+}
+
+static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
+{
+ writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
+ writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
+}
+
+static void uniphier_pcie_irq_disable(struct uniphier_pcie_priv *priv)
+{
+ writel(0, priv->base + PCL_RCV_INT);
+ writel(0, priv->base + PCL_RCV_INTX);
+}
+
+static void uniphier_pcie_irq_ack(struct irq_data *d)
+{
+ struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ u32 val;
+
+ val = readl(priv->base + PCL_RCV_INTX);
+ val &= ~PCL_RCV_INTX_ALL_STATUS;
+ val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
+ writel(val, priv->base + PCL_RCV_INTX);
+}
+
+static void uniphier_pcie_irq_mask(struct irq_data *d)
+{
+ struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ u32 val;
+
+ val = readl(priv->base + PCL_RCV_INTX);
+ val &= ~PCL_RCV_INTX_ALL_MASK;
+ val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
+ writel(val, priv->base + PCL_RCV_INTX);
+}
+
+static void uniphier_pcie_irq_unmask(struct irq_data *d)
+{
+ struct pcie_port *pp = irq_data_get_irq_chip_data(d);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ u32 val;
+
+ val = readl(priv->base + PCL_RCV_INTX);
+ val &= ~PCL_RCV_INTX_ALL_MASK;
+ val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
+ writel(val, priv->base + PCL_RCV_INTX);
+}
+
+static struct irq_chip uniphier_pcie_irq_chip = {
+ .name = "PCI",
+ .irq_ack = uniphier_pcie_irq_ack,
+ .irq_mask = uniphier_pcie_irq_mask,
+ .irq_unmask = uniphier_pcie_irq_unmask,
+};
+
+static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(irq, domain->host_data);
+
+ return 0;
+}
+
+static const struct irq_domain_ops uniphier_intx_domain_ops = {
+ .map = uniphier_pcie_intx_map,
+};
+
+static void uniphier_pcie_irq_handler(struct irq_desc *desc)
+{
+ struct pcie_port *pp = irq_desc_get_handler_data(desc);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long reg;
+ u32 val, bit, virq;
+
+ /* INT for debug */
+ val = readl(priv->base + PCL_RCV_INT);
+
+ if (val & PCL_CFG_BW_MGT_STATUS)
+ dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
+ if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
+ dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
+ if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
+ dev_dbg(pci->dev, "Root Error\n");
+ if (val & PCL_CFG_PME_MSI_STATUS)
+ dev_dbg(pci->dev, "PME Interrupt\n");
+
+ writel(val, priv->base + PCL_RCV_INT);
+
+ /* INTx */
+ chained_irq_enter(chip, desc);
+
+ val = readl(priv->base + PCL_RCV_INTX);
+ reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
+
+ for_each_set_bit(bit, ®, PCI_NUM_INTX) {
+ virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
+ generic_handle_irq(virq);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ struct device_node *np = pci->dev->of_node;
+ struct device_node *np_intc;
+
+ np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
+ if (!np_intc) {
+ dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
+ return -EINVAL;
+ }
+
+ pp->irq = irq_of_parse_and_map(np_intc, 0);
+ if (!pp->irq) {
+ dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
+ return -EINVAL;
+ }
+
+ priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
+ &uniphier_intx_domain_ops, pp);
+ if (!priv->legacy_irq_domain) {
+ dev_err(pci->dev, "Failed to get INTx domain\n");
+ return -ENODEV;
+ }
+
+ irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
+ pp);
+
+ return 0;
+}
+
+static int uniphier_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ int ret;
+
+ ret = uniphier_pcie_config_legacy_irq(pp);
+ if (ret)
+ return ret;
+
+ uniphier_pcie_irq_enable(priv);
+
+ dw_pcie_setup_rc(pp);
+ ret = uniphier_pcie_establish_link(pci);
+ if (ret)
+ return ret;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ dw_pcie_msi_init(pp);
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
+ .host_init = uniphier_pcie_host_init,
+};
+
+static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *pci = &priv->pci;
+ struct pcie_port *pp = &pci->pp;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->ops = &uniphier_pcie_host_ops;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
+ if (pp->msi_irq < 0)
+ return pp->msi_irq;
+ }
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "Failed to initialize host (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
+{
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(priv->rst);
+ if (ret)
+ goto out_clk_disable;
+
+ uniphier_pcie_init_rc(priv);
+
+ ret = phy_init(priv->phy);
+ if (ret)
+ goto out_rst_assert;
+
+ ret = uniphier_pcie_wait_rc(priv);
+ if (ret)
+ goto out_phy_exit;
+
+ return 0;
+
+out_phy_exit:
+ phy_exit(priv->phy);
+out_rst_assert:
+ reset_control_assert(priv->rst);
+out_clk_disable:
+ clk_disable_unprepare(priv->clk);
+
+ return ret;
+}
+
+static void uniphier_pcie_host_disable(struct uniphier_pcie_priv *priv)
+{
+ uniphier_pcie_irq_disable(priv);
+ phy_exit(priv->phy);
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = uniphier_pcie_establish_link,
+ .stop_link = uniphier_pcie_stop_link,
+ .link_up = uniphier_pcie_link_up,
+};
+
+static int uniphier_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct uniphier_pcie_priv *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->pci.dev = dev;
+ priv->pci.ops = &dw_pcie_ops;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
+ if (IS_ERR(priv->pci.dbi_base))
+ return PTR_ERR(priv->pci.dbi_base);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link");
+ priv->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ priv->rst = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(priv->rst))
+ return PTR_ERR(priv->rst);
+
+ priv->phy = devm_phy_optional_get(dev, "pcie-phy");
+ if (IS_ERR(priv->phy))
+ return PTR_ERR(priv->phy);
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = uniphier_pcie_host_enable(priv);
+ if (ret)
+ return ret;
+
+ return uniphier_add_pcie_port(priv, pdev);
+}
+
+static int uniphier_pcie_remove(struct platform_device *pdev)
+{
+ struct uniphier_pcie_priv *priv = platform_get_drvdata(pdev);
+
+ uniphier_pcie_host_disable(priv);
+
+ return 0;
+}
+
+static const struct of_device_id uniphier_pcie_match[] = {
+ { .compatible = "socionext,uniphier-pcie", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, uniphier_pcie_match);
+
+static struct platform_driver uniphier_pcie_driver = {
+ .probe = uniphier_pcie_probe,
+ .remove = uniphier_pcie_remove,
+ .driver = {
+ .name = "uniphier-pcie",
+ .of_match_table = uniphier_pcie_match,
+ },
+};
+builtin_platform_driver(uniphier_pcie_driver);
+
+MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PCIe host controller driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
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^ permalink raw reply related
* [PATCH v5 1/2] dt-bindings: PCI: Add UniPhier PCIe host controller description
From: Kunihiko Hayashi @ 2018-12-07 0:53 UTC (permalink / raw)
To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Mark Rutland,
Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-pci,
linux-kernel, Jassi Brar, Gustavo Pimentel, linux-arm-kernel
In-Reply-To: <1544143992-16385-1-git-send-email-hayashi.kunihiko@socionext.com>
Add DT bindings for PCIe controller implemented in UniPhier SoCs when
configured in Root Complex (host) mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt
new file mode 100644
index 0000000..1fa2c59
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt
@@ -0,0 +1,81 @@
+Socionext UniPhier PCIe host controller bindings
+
+This describes the devicetree bindings for PCIe host controller implemented
+on Socionext UniPhier SoCs.
+
+UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
+
+Required properties:
+- compatible: Should be "socionext,uniphier-pcie".
+- reg: Specifies offset and length of the register set for the device.
+ According to the reg-names, appropriate register sets are required.
+- reg-names: Must include the following entries:
+ "dbi" - controller configuration registers
+ "link" - SoC-specific glue layer registers
+ "config" - PCIe configuration space
+- clocks: A phandle to the clock gate for PCIe glue layer including
+ the host controller.
+- resets: A phandle to the reset line for PCIe glue layer including
+ the host controller.
+- interrupts: A list of interrupt specifiers. According to the
+ interrupt-names, appropriate interrupts are required.
+- interrupt-names: Must include the following entries:
+ "dma" - DMA interrupt
+ "msi" - MSI interrupt
+
+Optional properties:
+- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
+ phys are required.
+- phy-names: Must be "pcie-phy".
+
+Required sub-node:
+- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
+ interrupts.
+
+Required properties for legacy-interrupt-controller:
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. The value must be 1.
+- interrupt-parent: Phandle to the parent interrupt controller.
+- interrupts: An interrupt specifier for legacy interrupt.
+
+Example:
+
+ pcie: pcie@66000000 {
+ compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ status = "disabled";
+ reg-names = "dbi", "link", "config";
+ reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
+ <0x2fff0000 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&sys_clk 24>;
+ resets = <&sys_rst 24>;
+ num-lanes = <1>;
+ num-viewport = <1>;
+ bus-range = <0x0 0xff>;
+ device_type = "pci";
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
+ /* non-prefetchable memory */
+ 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
+ #interrupt-cells = <1>;
+ interrupt-names = "dma", "msi";
+ interrupts = <0 224 4>, <0 225 4>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
+ <0 0 0 2 &pcie_intc 1>, /* INTB */
+ <0 0 0 3 &pcie_intc 2>, /* INTC */
+ <0 0 0 4 &pcie_intc 3>; /* INTD */
+
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 226 4>;
+ };
+ };
--
2.7.4
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^ permalink raw reply related
* [PATCH v5 0/2] Add new UniPhier PCIe host driver
From: Kunihiko Hayashi @ 2018-12-07 0:53 UTC (permalink / raw)
To: Lorenzo Pieralisi, Bjorn Helgaas, Rob Herring, Mark Rutland,
Masahiro Yamada
Cc: devicetree, Kunihiko Hayashi, Masami Hiramatsu, linux-pci,
linux-kernel, Jassi Brar, Gustavo Pimentel, linux-arm-kernel
This series adds PCIe host controller driver for Socionext UniPhier SoCs.
This controller is based on the DesignWare PCIe core. This driver
supports LD20 and PXs3 SoCs.
v4: https://www.spinics.net/lists/linux-pci/msg78278.html
About legacy IRQ, it might be necessary to share common view from
keystone driver that have been cleaned up[1].
[1] https://lore.kernel.org/patchwork/patch/989541/
Changes since v4:
- fix an issue of using the wrong value to mask IRQ mask register
Changes since v3:
- dt-bindings: fix INTX numbering of legacy interrupt map
- change interrupts to level ones
- remove .xlate function
- merge uniphier_pcie_ltssm_disable() into uniphier_pcie_ltssm_enable()
- remove an error message on uniphier_pcie_establish_link()
- change the order between irq_domain_add_liniear() and
irq_set_chained_handler_and_data()
- replace dummy_irq_chip with uniphier_pcie_irq_chip and its functions
- add dependency on CONFIG_HAS_IOMEM
- MAINTAINERS: add pcie-uniphier entry
Changes since v2:
- dt-bindings: remove a comment that the node name isn't important
- dt-bindings: remove "intx" interrupt
- dt-bindings: define 'legacy-interrupt-controller' node and its properties
- return an error value when link up fails
- remove devm_request_irq() and a handler for MSI IRQ
- use chained interrupt instead of devm_request_irq() for legacy IRQ
- add unipher_pcie_config_legacy_irq() to get legacy IRQ from
'legacy-interrupt controller' node
- replace 4 statments to handle INTX with for_each_set_bit()
- remove initialization of pp->root_bus_nr
- remove indivisual interrupt enable bit definitions
- rename 'irq_domain' member to 'legacy_irq_domain' in private structure
- use pci_irqd_intx_xlate() for irq_domain_ops.xlate function
Changes since v1:
- follow capitalization conventions in the descriptions
- use C style comments except for the SPDX line
Kunihiko Hayashi (2):
dt-bindings: PCI: Add UniPhier PCIe host controller description
PCI: uniphier: Add UniPhier PCIe host controller support
.../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++
MAINTAINERS | 7 +
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-uniphier.c | 471 +++++++++++++++++++++
5 files changed, 570 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt
create mode 100644 drivers/pci/controller/dwc/pcie-uniphier.c
--
2.7.4
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* Re: [PATCH 1/5] dt-bindings: nvmem: add binding for Raspberry Pi OTP
From: Rob Herring @ 2018-12-06 23:49 UTC (permalink / raw)
To: Stefan Wahren
Cc: Mark Rutland, devicetree, Florian Fainelli, Arnd Bergmann,
Scott Branden, Ray Jui, Eric Anholt, Srinivas Kandagatla,
linux-rpi-kernel, gregkh, bcm-kernel-feedback-list,
linux-arm-kernel
In-Reply-To: <1542805904-6446-2-git-send-email-stefan.wahren@i2se.com>
On Wed, Nov 21, 2018 at 02:11:40PM +0100, Stefan Wahren wrote:
> This patch adds the devicetree binding for Raspberry Pi customer OTP
> driver.
>
> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
> ---
> .../nvmem/raspberrypi,bcm2835-customer-otp.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/raspberrypi,bcm2835-customer-otp.txt
>
> diff --git a/Documentation/devicetree/bindings/nvmem/raspberrypi,bcm2835-customer-otp.txt b/Documentation/devicetree/bindings/nvmem/raspberrypi,bcm2835-customer-otp.txt
> new file mode 100644
> index 0000000..041ff17
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/raspberrypi,bcm2835-customer-otp.txt
> @@ -0,0 +1,22 @@
> +Customer OTP Memory for Raspberry Pi
> +
> +The VC4 firmware exposes a mailbox interface that allows the ARM core
> +to access the customer part of the OTP memory.
> +
> +The OTP node must be a child node of the Raspberry Pi firmware node.
> +
> +Required properties :
> +- compatible : Should be "raspberrypi,bcm2835-customer-otp"
Why do we need this child node? Can't the parent instantiate this?
Are there OTP fields you want to expose in DT?
> +
> +See nvmem.txt for more information.
> +
> +Example:
> +
> +firmware: firmware-rpi {
> + compatible = "raspberrypi,bcm2835-firmware";
> + mboxes = <&mailbox>;
> +
> + customer_otp: otp {
> + compatible = "raspberrypi,bcm2835-customer-otp";
> + };
> +};
> --
> 2.7.4
>
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* [PATCH 5/6] arm64: add sysfs vulnerability show for speculative store bypass
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
From: Mian Yousaf Kaukab <ykaukab@suse.de>
Return status based no ssbd_state and the arm64 SSBS feature.
Return string "Unknown" in case CONFIG_ARM64_SSBD is
disabled or arch workaround2 is not available
in the firmware.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
[Added SSBS logic]
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/kernel/cpu_errata.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6505c93d507e..8aeb5ca38db8 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -423,6 +423,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
ssbd_state = ARM64_SSBD_UNKNOWN;
return false;
+ /* machines with mixed mitigation requirements must not return this */
case SMCCC_RET_NOT_REQUIRED:
pr_info_once("%s mitigation not required\n", entry->desc);
ssbd_state = ARM64_SSBD_MITIGATED;
@@ -828,4 +829,31 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
}
}
+ssize_t cpu_show_spec_store_bypass(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ /*
+ * Two assumptions: First, get_ssbd_state() reflects the worse case
+ * for hetrogenous machines, and that if SSBS is supported its
+ * supported by all cores.
+ */
+ switch (arm64_get_ssbd_state()) {
+ case ARM64_SSBD_MITIGATED:
+ return sprintf(buf, "Not affected\n");
+
+ case ARM64_SSBD_KERNEL:
+ case ARM64_SSBD_FORCE_ENABLE:
+ if (cpus_have_cap(ARM64_SSBS))
+ return sprintf(buf, "Not affected\n");
+ return sprintf(buf,
+ "Mitigation: Speculative Store Bypass disabled\n");
+
+ case ARM64_SSBD_FORCE_DISABLE:
+ return sprintf(buf, "Vulnerable\n");
+
+ default: /* ARM64_SSBD_UNKNOWN*/
+ return sprintf(buf, "Unknown\n");
+ }
+}
+
#endif
--
2.17.2
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* [PATCH 6/6] arm64: enable generic CPU vulnerabilites support
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
From: Mian Yousaf Kaukab <ykaukab@suse.de>
Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2,
meltdown and store-bypass.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ea2ab0330e3a..4b20d46c959b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -89,6 +89,7 @@ config ARM64
select GENERIC_CLOCKEVENTS
select GENERIC_CLOCKEVENTS_BROADCAST
select GENERIC_CPU_AUTOPROBE
+ select GENERIC_CPU_VULNERABILITIES
select GENERIC_EARLY_IOREMAP
select GENERIC_IDLE_POLL_SETUP
select GENERIC_IRQ_MULTI_HANDLER
--
2.17.2
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* [PATCH 4/6] arm64: add sysfs vulnerability show for spectre v2
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
Add code to track whether all the cores in the machine are
vulnerable, and whether all the vulnerable cores have been
mitigated.
Once we have that information we can add the sysfs stub and
provide an accurate view of what is known about the machine.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/kernel/cpu_errata.c | 72 +++++++++++++++++++++++++++++++---
1 file changed, 67 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 559ecdee6fd2..6505c93d507e 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -109,6 +109,11 @@ cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
+#if defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || defined(CONFIG_GENERIC_CPU_VULNERABILITIES)
+/* Track overall mitigation state. We are only mitigated if all cores are ok */
+static enum { A64_HBP_UNSET, A64_HBP_MIT, A64_HBP_NOTMIT } __hardenbp_enab = A64_HBP_UNSET;
+#endif
+
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
@@ -231,15 +236,19 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
if (!entry->matches(entry, SCOPE_LOCAL_CPU))
return;
- if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
+ if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
+ __hardenbp_enab = A64_HBP_NOTMIT;
return;
+ }
switch (psci_ops.conduit) {
case PSCI_CONDUIT_HVC:
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if ((int)res.a0 < 0)
+ if ((int)res.a0 < 0) {
+ __hardenbp_enab = A64_HBP_NOTMIT;
return;
+ }
cb = call_hvc_arch_workaround_1;
/* This is a guest, no need to patch KVM vectors */
smccc_start = NULL;
@@ -249,14 +258,17 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
case PSCI_CONDUIT_SMC:
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if ((int)res.a0 < 0)
+ if ((int)res.a0 < 0) {
+ __hardenbp_enab = A64_HBP_NOTMIT;
return;
+ }
cb = call_smc_arch_workaround_1;
smccc_start = __smccc_workaround_1_smc_start;
smccc_end = __smccc_workaround_1_smc_end;
break;
default:
+ __hardenbp_enab = A64_HBP_NOTMIT;
return;
}
@@ -266,6 +278,9 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
+ if (__hardenbp_enab == A64_HBP_UNSET)
+ __hardenbp_enab = A64_HBP_MIT;
+
return;
}
#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
@@ -539,7 +554,36 @@ multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
caps->cpu_enable(caps);
}
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+#if defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || \
+ defined(CONFIG_GENERIC_CPU_VULNERABILITIES)
+
+static enum { A64_SV2_UNSET, A64_SV2_SAFE, A64_SV2_UNSAFE } __spectrev2_safe = A64_SV2_UNSET;
+
+/*
+ * Track overall bp hardening for all heterogeneous cores in the machine.
+ * We are only considered "safe" if all booted cores are known safe.
+ */
+static bool __maybe_unused
+check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
+{
+ bool is_vul;
+ bool has_csv2;
+ u64 pfr0;
+
+ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
+
+ is_vul = is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
+
+ pfr0 = read_cpuid(ID_AA64PFR0_EL1);
+ has_csv2 = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT);
+
+ if (is_vul)
+ __spectrev2_safe = A64_SV2_UNSAFE;
+ else if (__spectrev2_safe == A64_SV2_UNSET && has_csv2)
+ __spectrev2_safe = A64_SV2_SAFE;
+
+ return is_vul;
+}
/*
* List of CPUs where we need to issue a psci call to
@@ -728,7 +772,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
{
.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
.cpu_enable = enable_smccc_arch_workaround_1,
- ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+ .matches = check_branch_predictor,
+ .midr_range_list = arm64_bp_harden_smccc_cpus,
},
#endif
#ifdef CONFIG_HARDEN_EL2_VECTORS
@@ -766,4 +812,20 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
}
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ switch (__spectrev2_safe) {
+ case A64_SV2_SAFE:
+ return sprintf(buf, "Not affected\n");
+ case A64_SV2_UNSAFE:
+ if (__hardenbp_enab == A64_HBP_MIT)
+ return sprintf(buf,
+ "Mitigation: Branch predictor hardening\n");
+ return sprintf(buf, "Vulnerable\n");
+ default:
+ return sprintf(buf, "Unknown\n");
+ }
+}
+
#endif
--
2.17.2
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* Re: [PATCH 1/3] dt-bindings: add vendor prefix for PDA Precision Design Associates, Inc.
From: Rob Herring @ 2018-12-06 23:44 UTC (permalink / raw)
To: Eugen.Hristev
Cc: mark.rutland, devicetree, airlied, linux-kernel, dri-devel,
robh+dt, thierry.reding, Cristian.Birsan, Eugen.Hristev,
linux-arm-kernel
In-Reply-To: <1542789804-4584-2-git-send-email-eugen.hristev@microchip.com>
On Wed, 21 Nov 2018 08:47:57 +0000, <Eugen.Hristev@microchip.com> wrote:
> Precision Design Associates, Inc. (PDA) manufactures standard and custom
> capacitive touch screens, LCD's embedded controllers and custom embedded
> software. They specialize in industrial, rugged and outdoor applications.
> Website: http://www.pdaatl.com/
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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* [PATCH 1/6] arm64: kpti: move check for non-vulnerable CPUs to a function
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
From: Mian Yousaf Kaukab <ykaukab@suse.de>
Add is_meltdown_safe() which is a whitelist of known safe cores.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
[Moved location of function]
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/kernel/cpufeature.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index aec5ecb85737..242898395f68 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -908,8 +908,7 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
-static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
- int scope)
+static bool is_cpu_meltdown_safe(void)
{
/* List of CPUs that are not vulnerable and don't need KPTI */
static const struct midr_range kpti_safe_list[] = {
@@ -917,6 +916,16 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
{ /* sentinel */ }
};
+ /* Don't force KPTI for CPUs that are not vulnerable */
+ if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
+ return true;
+
+ return false;
+}
+
+static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
+ int scope)
+{
char const *str = "command line option";
/*
@@ -940,8 +949,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
return true;
- /* Don't force KPTI for CPUs that are not vulnerable */
- if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
+ if (is_cpu_meltdown_safe())
return false;
/* Defer to CPU feature registers */
--
2.17.2
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* [PATCH 3/6] arm64: add sysfs vulnerability show for spectre v1
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
From: Mian Yousaf Kaukab <ykaukab@suse.de>
spectre v1, has been mitigated, and the mitigation is
always active.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/kernel/cpu_errata.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6ad715d67df8..559ecdee6fd2 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -757,3 +757,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
{
}
};
+
+#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
+
+ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "Mitigation: __user pointer sanitization\n");
+}
+
+#endif
--
2.17.2
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* [PATCH 2/6] arm64: add sysfs vulnerability show for meltdown
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
In-Reply-To: <20181206234408.1287689-1-jeremy.linton@arm.com>
Add a simple state machine which will track whether
all the online cores in a machine are vulnerable.
Once that is done we have a fairly authoritative view
of the machine vulnerability, which allows us to make a
judgment about machine safety if it hasn't been mitigated.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
arch/arm64/kernel/cpufeature.c | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 242898395f68..bea9adfef7fa 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -905,6 +905,8 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
return has_cpuid_feature(entry, scope);
}
+static enum { A64_MELT_UNSET, A64_MELT_SAFE, A64_MELT_UNKN } __meltdown_safe = A64_MELT_UNSET;
+
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
@@ -928,6 +930,15 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
{
char const *str = "command line option";
+ bool meltdown_safe = is_cpu_meltdown_safe() ||
+ has_cpuid_feature(entry, scope);
+
+ /* Only safe if all booted cores are known safe */
+ if (meltdown_safe && __meltdown_safe == A64_MELT_UNSET)
+ __meltdown_safe = A64_MELT_SAFE;
+ else if (!meltdown_safe)
+ __meltdown_safe = A64_MELT_UNKN;
+
/*
* For reasons that aren't entirely clear, enabling KPTI on Cavium
* ThunderX leads to apparent I-cache corruption of kernel text, which
@@ -949,11 +960,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
return true;
- if (is_cpu_meltdown_safe())
- return false;
-
- /* Defer to CPU feature registers */
- return !has_cpuid_feature(entry, scope);
+ return !meltdown_safe;
}
static void
@@ -1920,3 +1927,17 @@ static int __init enable_mrs_emulation(void)
}
core_initcall(enable_mrs_emulation);
+
+#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
+ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ if (arm64_kernel_unmapped_at_el0())
+ return sprintf(buf, "Mitigation: KPTI\n");
+
+ if (__meltdown_safe == A64_MELT_SAFE)
+ return sprintf(buf, "Not affected\n");
+
+ return sprintf(buf, "Unknown\n");
+}
+#endif
--
2.17.2
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* [PATCH 0/6] add system vulnerability sysfs entries
From: Jeremy Linton @ 2018-12-06 23:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, suzuki.poulose, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, Jeremy Linton, ykaukab, dave.martin,
shankerd
Part of this series was originally by Mian Yousaf Kaukab.
Arm64 machines should be displaying a human readable
vulnerability status to speculative execution attacks in
/sys/devices/system/cpu/vulnerabilities
This series enables that behavior by providing the expected
functions. Those functions expose the cpu errata and feature
states, as well as whether firmware is responding appropriately
to display the overall machine status. This means that in a
heterogeneous machine we will only claim the machine is mitigated
or safe if we are confident all booted cores are safe or
mitigated. Otherwise, we will display unknown or unsafe
depending on how much of the machine configuration can
be assured.
Jeremy Linton (2):
arm64: add sysfs vulnerability show for meltdown
arm64: add sysfs vulnerability show for spectre v2
Mian Yousaf Kaukab (4):
arm64: kpti: move check for non-vulnerable CPUs to a function
arm64: add sysfs vulnerability show for spectre v1
arm64: add sysfs vulnerability show for speculative store bypass
arm64: enable generic CPU vulnerabilites support
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/cpu_errata.c | 110 +++++++++++++++++++++++++++++++--
arch/arm64/kernel/cpufeature.c | 45 +++++++++++---
3 files changed, 143 insertions(+), 13 deletions(-)
--
2.17.2
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* Re: [PATCH v8 3/7] ASoC: dt-bindings: make enable-gpio optional for simple amplifier
From: Rob Herring @ 2018-12-06 23:43 UTC (permalink / raw)
To: Vasily Khoruzhick
Cc: Mark Rutland, devicetree, alsa-devel, Maxime Ripard, Takashi Iwai,
Liam Girdwood, Jaroslav Kysela, Vasily Khoruzhick, Chen-Yu Tsai,
Mark Brown, linux-arm-kernel, Jerome Brunet
In-Reply-To: <20181121051752.18387-4-anarsoul@gmail.com>
On Tue, 20 Nov 2018 21:17:48 -0800, Vasily Khoruzhick wrote:
> Amplifier may have no enable GPIO, so make this property optional
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> Documentation/devicetree/bindings/sound/simple-amplifier.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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* [PATCH] ARM: dts: imx51-zii-rdu1: Do not specify "power-gpio" for hpa1
From: Fabio Estevam @ 2018-12-06 23:41 UTC (permalink / raw)
To: shawnguo
Cc: andrew.smirnov, Fabio Estevam, linux-arm-kernel, cphealy, l.stach
From: Andrey Smirnov <andrew.smirnov@gmail.com>
TPA6130A2 SD pin on RDU1 is not really controlled by SoC and instead
is only meant to notify the system that audio was "muted" by external
actors. To accommodate that, drop "power-gpio" property of hpa1 node as
well as specify a name for that GPIO so that userspace can access it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
arch/arm/boot/dts/imx51-zii-rdu1.dts | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 28e9dca..a8220f0 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -478,6 +478,15 @@
};
&gpio1 {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "hp-amp-shutdown-b", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+
unused-sd3-wp-gpio {
/*
* See pinctrl_esdhc1 below for more details on this
@@ -496,9 +505,6 @@
hpa1: amp@60 {
compatible = "ti,tpa6130a2";
reg = <0x60>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ampgpio>;
- power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
Vdd-supply = <®_3p3v>;
};
@@ -672,7 +678,10 @@
};
&iomuxc {
- pinctrl_ampgpio: ampgpiogrp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
fsl,pins = <
MX51_PAD_GPIO1_9__GPIO1_9 0x5e
>;
--
2.7.4
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