* Re: [PATCH v7 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Miquel Raynal @ 2018-12-07 9:42 UTC (permalink / raw)
To: Jianxin Pan
Cc: Rob Herring, Hanjie Lin, Victor Wan, Marek Vasut,
Martin Blumenstingl, Richard Weinberger, Neil Armstrong,
Yixun Lan, linux-kernel, Boris Brezillon, Jian Hu, Liang Yang,
linux-mtd, Kevin Hilman, Carlo Caione, linux-amlogic,
Brian Norris, David Woodhouse, linux-arm-kernel, Jerome Brunet
In-Reply-To: <20181207102456.1dc67e07@xps13>
Hi Jianxin,
Miquel Raynal <miquel.raynal@bootlin.com> wrote on Fri, 7 Dec 2018
10:24:56 +0100:
> Hi Jianxin,
>
> Looks good to me overall, a few comments inline.
>
> Jianxin Pan <jianxin.pan@amlogic.com> wrote on Sat, 17 Nov 2018
> 00:40:38 +0800:
>
> > From: Liang Yang <liang.yang@amlogic.com>
> >
> > Add initial support for the Amlogic NAND flash controller which found
> > in the Meson-GXBB/GXL/AXG SoCs.
> >
> > Signed-off-by: Liang Yang <liang.yang@amlogic.com>
> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> > Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> > ---
> > drivers/mtd/nand/raw/Kconfig | 10 +
> > drivers/mtd/nand/raw/Makefile | 1 +
> > drivers/mtd/nand/raw/meson_nand.c | 1417 +++++++++++++++++++++++++++++++++++++
> > 3 files changed, 1428 insertions(+)
> > create mode 100644 drivers/mtd/nand/raw/meson_nand.c
> >
I forgot to mention, Boris has done more cleanup which breaks your
patches, please have a look at the following commits in the nand/next
branch, they will force you to do some light rework to get the driver
building (especially, you should not export the ->select_chip hook anymore):
7a08dbaedd36 mtd: rawnand: Move ->setup_data_interface() to nand_controller_ops
f2abfeb2078b mtd: rawnand: Move the ->exec_op() method to nand_controller_ops
7d6c37e90cf9 mtd: rawnand: Deprecate the ->select_chip() hook
1770022ffa85 mtd: rawnand: ams-delta: Stop implementing ->select_chip()
653c57c7da08 mtd: rawnand: vf610: Stop implementing ->select_chip()
2ace451cae22 mtd: rawnand: tegra: Stop implementing ->select_chip()
b25251414f6e mtd: rawnand: marvell: Stop implementing ->select_chip()
550b9fc4e3af mtd: rawnand: fsmc: Stop implementing ->select_chip()
02b4a52604a4 mtd: rawnand: Make ->select_chip() optional when ->exec_op() is implemented
ae2294b10b0f mtd: rawnand: Pass the CS line to be selected in struct nand_operation
1d0178593d14 mtd: rawnand: Add nand_[de]select_target() helpers
Thanks,
Miquèl
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* Re: [PATCH 1/2] gpio: mt7621: report failure of devm_kasprintf()
From: Linus Walleij @ 2018-12-07 9:46 UTC (permalink / raw)
To: Nicholas Mc Guire
Cc: Sergio Paracuellos, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Bartosz Golaszewski,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
In-Reply-To: <1542823573-20228-1-git-send-email-hofrat@osadl.org>
On Wed, Nov 21, 2018 at 7:12 PM Nicholas Mc Guire <hofrat@osadl.org> wrote:
> kasprintf() may return NULL on failure of internal allocation thus the
> assigned label is not safe if not explicitly checked. On error
> mediatek_gpio_bank_probe() returns negative values so -ENOMEM in the
> (unlikely) failure case should be fine here.
>
> Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
> Fixes: 4ba9c3afda41 ("gpio: mt7621: Add a driver for MT7621")
Patch applied with Bartosz and Sean's tags.
Yours,
Linus Walleij
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* Re: [PATCH V2] gpio: mt7621: pass mediatek_gpio_bank_probe() failure up the stack
From: Linus Walleij @ 2018-12-07 9:48 UTC (permalink / raw)
To: Nicholas Mc Guire
Cc: Sergio Paracuellos, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Bartosz Golaszewski,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
In-Reply-To: <1543338018-708-1-git-send-email-hofrat@osadl.org>
On Tue, Nov 27, 2018 at 6:06 PM Nicholas Mc Guire <hofrat@osadl.org> wrote:
> The error cases of mediatek_gpio_bank_probe() would go unnoticed (except
> for the dev_err() messages). The probe function should return an error
> if one of the banks failed to initialize properly indicated by
> not returning non-0.
>
> Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
> Fixes: 4ba9c3afda41 ("gpio: mt7621: Add a driver for MT7621")
Patch applied with Sean's ACK.
Yours,
Linus Walleij
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* Re: [PATCH 1/2] dt-bindings: gpio: lpc18xx: describe interrupt controllers of GPIO controller
From: Linus Walleij @ 2018-12-07 9:56 UTC (permalink / raw)
To: Vladimir Zapolskiy
Cc: Marc Zyngier,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring, Linux ARM, open list:GPIO SUBSYSTEM
In-Reply-To: <20181128224841.3646-2-vz@mleia.com>
On Wed, Nov 28, 2018 at 11:48 PM Vladimir Zapolskiy <vz@mleia.com> wrote:
> From LPC18xx and LPC43xx User Manuals the GPIO controller consists of
> the following weakly connected blocks:
> * GPIO pin interrupt block at 0x40087000,
> * GPIO GROUP0 interrupt block at 0x40088000,
> * GPIO GROUP1 interrupt block at 0x40089000,
> * GPIO port block at 0x400F4000.
>
> While all 4 sub-controller blocks have their own I/O addresses, moreover
> all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is
> an AHB slave, according to the hardware manual interrupt controllers and
> GPIO controller block are seen as a single device, all 4 sub-controllers
> have the shared reset signal RGU #28 and the same shared clock to access
> registers CLK_Mx_GPIO on CCU1.
>
> The change adds descriptions of the currently missing interrupt controller
> blocks found on GPIO controller, new added properties are 'reg-names',
> 'resets', 'interrupt-controller' and '#interrupt-cells', also the example
> is updated to reflect the changes in device tree binding description.
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
That is some seriously Frankenstein hardware.
But I see no problem with the way you are dealing with it,
it seems pretty much to the point.
So: patch applied.
Yours,
Linus Walleij
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* Re: [PATCH 2/2] gpio: lpc18xx: add GPIO pin interrupt controller support
From: Linus Walleij @ 2018-12-07 10:00 UTC (permalink / raw)
To: Vladimir Zapolskiy
Cc: Marc Zyngier,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring, Linux ARM, open list:GPIO SUBSYSTEM
In-Reply-To: <20181128224841.3646-3-vz@mleia.com>
On Wed, Nov 28, 2018 at 11:48 PM Vladimir Zapolskiy <vz@mleia.com> wrote:
> The change adds support of LPC18xx/LPC43xx GPIO pin interrupt controller
> block within SoC GPIO controller. The new interrupt controller driver
> allows to configure and capture edge or level interrupts on 8 arbitrary
> selectedinput GPIO pins, and lift the signals to be reported as NVIC rising
> edge interrupts. Configuration of a particular GPIO pin to serve as
> interrupt and its mapping to an interrupt on NVIC is done by SCU pin
> controller, for more details see description of 'nxp,gpio-pin-interrupt'
> device tree property of a GPIO pin [1].
>
> From LPC18xx and LPC43xx User Manuals the GPIO controller consists of
> the following blocks:
> * GPIO pin interrupt block at 0x40087000, this change adds its support,
> * GPIO GROUP0 interrupt block at 0x40088000,
> * GPIO GROUP1 interrupt block at 0x40089000,
> * GPIO port block at 0x400F4000, it is supported by the original driver.
>
> While all 4 sub-controller blocks have their own I/O addresses, moreover
> all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is
> an AHB slave, according to the hardware manual the GPIO controller is
> seen as a single block, and 4 sub-controllers have the shared reset signal
> RGU #28 and clock to register interface CLK_CPU_GPIO on CCU1.
>
> Likely support of two GPIO group interrupt blocks won't be added in short
> term, because the mechanism to mask several interrupt sources is not well
> defined.
>
> [1] Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
It's quite complex, but your implementation is so crisp and clean
that there is nothing to complain about really.
We are discussing putting some hierarchy handling into the
gpiolib core, so you might want to simplify the code later to
make use of this, but for now it's perfectly fine.
Patch applied.
Yours,
Linus Walleij
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* Re: [PATCH v2] media: Use of_node_name_eq for node name comparisons
From: Sylwester Nawrocki @ 2018-12-07 10:02 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-samsung-soc, Hyun Kwon, linux-kernel,
Krzysztof Kozlowski, Michal Simek, Benoit Parrot, Kyungmin Park,
Kukjin Kim, Laurent Pinchart, Mauro Carvalho Chehab,
linux-arm-kernel, linux-media
In-Reply-To: <20181206193519.13367-1-robh@kernel.org>
On 12/6/18 20:35, Rob Herring wrote:
> Convert string compares of DT node names to use of_node_name_eq helper
> instead. This removes direct access to the node name pointer.
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Reviewed-by: Benoit Parrot <bparrot@ti.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> - Also convert tabs to spaces between the 'if' and '('
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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* [PATCH 1/3] dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
From: Anson Huang @ 2018-12-07 10:03 UTC (permalink / raw)
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, Fabio Estevam, robh+dt@kernel.org,
mark.rutland@arm.com, mturquette@baylibre.com, sboyd@kernel.org,
Aisheng Dong, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Cc: dl-linux-imx
There are HSRUN mode clock mux and divider in SCG1 module,
and SMC1 can control i.MX7ULP CPU to run in RUN mode or
HSRUN mode, the mode switch bits are actually a clock mux,
add these clocks for clock driver and dtb to use.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
include/dt-bindings/clock/imx7ulp-clock.h | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 008c5ee..21d872e 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -54,8 +54,10 @@
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
#define IMX7ULP_CLK_SPLL_BUS_CLK 43
+#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
+#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
-#define IMX7ULP_CLK_SCG1_END 44
+#define IMX7ULP_CLK_SCG1_END 46
/* PCC2 */
#define IMX7ULP_CLK_DMA1 0
@@ -106,4 +108,9 @@
#define IMX7ULP_CLK_PCC3_END 16
+/* SMC1 */
+#define IMX7ULP_CLK_ARM 0
+
+#define IMX7ULP_CLK_SMC1_END 1
+
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
--
2.7.4
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* [PATCH 2/3] clk: imx: imx7ulp: add arm hsrun mode clocks support
From: Anson Huang @ 2018-12-07 10:03 UTC (permalink / raw)
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, Fabio Estevam, robh+dt@kernel.org,
mark.rutland@arm.com, mturquette@baylibre.com, sboyd@kernel.org,
Aisheng Dong, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <1544176659-32022-1-git-send-email-Anson.Huang@nxp.com>
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.
Latest clock tree in RUN mode as below:
firc 0 0 0 48000000 0 0 50000
firc_bus_clk 0 0 0 48000000 0 0 50000
hsrun_scs_sel 0 0 0 48000000 0 0 50000
hsrun_divcore 0 0 0 48000000 0 0 50000
sosc 3 3 3 24000000 0 0 50000
spll_pre_sel 1 1 1 24000000 0 0 50000
spll_pre_div 1 1 2 24000000 0 0 50000
spll 1 1 2 528000000 0 0 50000
spll_pfd0 1 1 1 500210526 0 0 50000
spll_pfd_sel 1 1 0 500210526 0 0 50000
spll_sel 1 1 0 500210526 0 0 50000
scs_sel 1 1 0 500210526 0 0 50000
divcore 1 1 0 500210526 0 0 50000
arm 1 1 0 500210526 0 0 50000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
drivers/clk/imx/clk-imx7ulp.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 3b7507f..4e18f62 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -29,6 +29,7 @@ static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
static const struct clk_div_table ulp_div_table[] = {
@@ -102,10 +103,12 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
/* scs/ddr/nic select different clock source requires that clock to be enabled first */
clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
+ clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
- clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+ clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
+ clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);
clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
0, ulp_div_table, &imx_ccm_lock);
@@ -218,3 +221,29 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
}
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
+
+static void __init imx7ulp_clk_smc1_init(struct device_node *np)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **clks;
+ void __iomem *base;
+
+ clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
+ IMX7ULP_CLK_SMC1_END, GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->num = IMX7ULP_CLK_SMC1_END;
+ clks = clk_data->hws;
+
+ /* SMC1 */
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ clks[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL);
+
+ imx_check_clk_hws(clks, clk_data->num);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+}
+CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init);
--
2.7.4
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* [PATCH 3/3] ARM: dts: imx7ulp: add HSRUN mode clocks
From: Anson Huang @ 2018-12-07 10:03 UTC (permalink / raw)
To: shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, Fabio Estevam, robh+dt@kernel.org,
mark.rutland@arm.com, mturquette@baylibre.com, sboyd@kernel.org,
Aisheng Dong, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <1544176659-32022-1-git-send-email-Anson.Huang@nxp.com>
i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
This patch is based on top of path series: [V5,1/6] dt-bindings: fsl: add compatible for imx7ulp evk,
https://patchwork.kernel.org/patch/10677263/
---
arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b275..b86daf7 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
};
- smc1: smc1@40410000 {
+ smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+ <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+ clock-names = "divcore", "hsrun_divcore";
};
pcc3: clock-controller@40b30000 {
--
2.7.4
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* Re: [PATCH v10 0/8] Introduce on-chip interconnect API
From: Georgi Djakov @ 2018-12-07 10:06 UTC (permalink / raw)
To: Greg KH, Evan Green
Cc: mark.rutland, Doug Anderson, sanjayc, maxime.ripard,
Michael Turquette, daidavid1, Bjorn Andersson, Saravana Kannan,
Alexandre Bailon, lorenzo.pieralisi, Vincent Guittot, seansw,
khilman, ksitaraman, devicetree, Arnd Bergmann, linux-pm,
linux-arm-msm, robh+dt, linux-tegra, linux-arm-kernel, rjw,
linux-kernel, amit.kucheria, Thierry Reding
In-Reply-To: <20181206145547.GA7884@kroah.com>
Hi Greg and Evan,
On 12/6/18 16:55, Greg KH wrote:
> On Wed, Dec 05, 2018 at 12:41:35PM -0800, Evan Green wrote:
>> On Tue, Nov 27, 2018 at 10:03 AM Georgi Djakov <georgi.djakov@linaro.org> wrote:
>>>
>>> Modern SoCs have multiple processors and various dedicated cores (video, gpu,
>>> graphics, modem). These cores are talking to each other and can generate a
>>> lot of data flowing through the on-chip interconnects. These interconnect
>>> buses could form different topologies such as crossbar, point to point buses,
>>> hierarchical buses or use the network-on-chip concept.
>>>
>>> These buses have been sized usually to handle use cases with high data
>>> throughput but it is not necessary all the time and consume a lot of power.
>>> Furthermore, the priority between masters can vary depending on the running
>>> use case like video playback or CPU intensive tasks.
>>>
>>> Having an API to control the requirement of the system in terms of bandwidth
>>> and QoS, so we can adapt the interconnect configuration to match those by
>>> scaling the frequencies, setting link priority and tuning QoS parameters.
>>> This configuration can be a static, one-time operation done at boot for some
>>> platforms or a dynamic set of operations that happen at run-time.
>>>
>>> This patchset introduce a new API to get the requirement and configure the
>>> interconnect buses across the entire chipset to fit with the current demand.
>>> The API is NOT for changing the performance of the endpoint devices, but only
>>> the interconnect path in between them.
>>
>> For what it's worth, we are ready to land this in Chrome OS. I think
>> this series has been very well discussed and reviewed, hasn't changed
>> much in the last few spins, and is in good enough shape to use as a
>> base for future patches. Georgi's also done a great job reaching out
>> to other SoC vendors, and there appears to be enough consensus that
>> this framework will be usable by more than just Qualcomm. There are
>> also several drivers out on the list trying to add patches to use this
>> framework, with more to come, so it made sense (to us) to get this
>> base framework nailed down. In my experiments this is an important
>> piece of the overall power management story, especially on systems
>> that are mostly idle.
>>
>> I'll continue to track changes to this series and we will ultimately
>> reconcile with whatever happens upstream, but I thought it was worth
>> sending this note to express our "thumbs up" towards this framework.
>
> Looks like a v11 will be forthcoming, so I'll wait for that one to apply
> it to the tree if all looks good.
>
Yes, it's coming. I will also include an additional fixup patch, as the
sdm845 provider driver will fail to build in linux-next, due to a recent
change in the cmd_db API.
Thanks,
Georgi
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^ permalink raw reply
* Re: [PATCH v16 06/16] lib: fdt: add a helper function for handling memory range property
From: James Morse @ 2018-12-07 10:12 UTC (permalink / raw)
To: Will Deacon, AKASHI, Takahiro
Cc: prudo, Herbert Xu, Baoquan He, Ard Biesheuvel, Catalin Marinas,
bhsharma, Frank Rowand, Heiko Carstens,
linux-kernel@vger.kernel.org, David Howells, devicetree,
Rob Herring, Arnd Bergmann,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, kexec,
Martin Schwidefsky, dyoung, David Miller, Vivek Goyal
In-Reply-To: <20181206155424.GA4422@arm.com>
Hi Akashi, Will,
On 06/12/2018 15:54, Will Deacon wrote:
> On Thu, Dec 06, 2018 at 08:47:04AM -0600, Rob Herring wrote:
>> On Wed, Nov 14, 2018 at 11:52 PM AKASHI Takahiro
>> <takahiro.akashi@linaro.org> wrote:
>>>
>>> Added function, fdt_setprop_reg(), will be used later to handle
>>> kexec-specific property in arm64's kexec_file implementation.
>>> It will possibly be merged into libfdt in the future.
>>
>> You generally can't modify libfdt files. Any changes will be blown
>> away with the next dtc sync (there's one in -next now). Though here
>> you are creating a new location with fdt code. lib/ is just a shim to
>> the actual libfdt code. Don't put any implementation there. You can
>> add this to drivers/of/fdt_address.c for the short term, but it still
>> needs to go upstream.
>>
>> Otherwise, the implementation looks fine to me.
>
> I agree, but I don't think there's a real need for us to hack
> drivers/of/fdt_address.c in the meantime -- let's just target upstream
> and not carry this in the kernel.
>
> Akashi -- for now, I'll drop the kdump parts of this series which rely
> on this helper. The majority of the series is actually independent and
> can go in as-is.
>
> I've pushed out a kexec branch to the arm64 tree for you to take a look
> at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=kexec
I gave this a quick spin. Without the elfcorehdr/usable-memory-range arm64 needs
to explicitly forbid kdump via kexec_file_load. (like powerpc does already).
Without this kdump works, but the second kernel overwrites the first as those DT
properties are missing.
I'll post a patch momentarily,
Thanks,
James
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* [PATCH arm64/kexec] arm64: kexec_file: forbid kdump via kexec_file_load()
From: James Morse @ 2018-12-07 10:14 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Herbert Xu, Baoquan He, Ard Biesheuvel, Will Deacon,
bhsharma, Frank Rowand, kexec, linux-kernel, Heiko Carstens,
David Howells, AKASHI Takahiro, Rob Herring, Arnd Bergmann,
James Morse, Catalin Marinas, Martin Schwidefsky, prudo, dyoung,
David Miller, Vivek Goyal
Now that kexec_walk_memblock() can do the crash-kernel placement itself
architectures that don't support kdump via kexe_file_load() need to
explicitly forbid it.
We don't support this on arm64 until the kernel can add the elfcorehdr
and usable-memory-range fields to the DT. Without these the crash-kernel
overwrites the previous kernel's memory during startup.
Add a check to refuse crash image loading.
Signed-off-by: James Morse <james.morse@arm.com>
---
Context: http://lore.kernel.org/r/20181206155424.GA4422@arm.com
arch/arm64/kernel/kexec_image.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/kernel/kexec_image.c b/arch/arm64/kernel/kexec_image.c
index 1ad1d5f8f024..07bf740bea91 100644
--- a/arch/arm64/kernel/kexec_image.c
+++ b/arch/arm64/kernel/kexec_image.c
@@ -47,6 +47,10 @@ static void *image_load(struct kimage *image,
struct kexec_segment *kernel_segment;
int ret;
+ /* We don't support crash kernels yet. */
+ if (image->type == KEXEC_TYPE_CRASH)
+ return ERR_PTR(-EOPNOTSUPP);
+
/*
* We require a kernel with an unambiguous Image header. Per
* Documentation/booting.txt, this is the case when image_size
--
2.19.2
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^ permalink raw reply related
* Re: [RFC PATCH] gpio: pl061: handle failed allocations
From: Linus Walleij @ 2018-12-07 10:14 UTC (permalink / raw)
To: Nicholas Mc Guire; +Cc: Russell King, Linux ARM, linux-kernel@vger.kernel.org
In-Reply-To: <1543665438-26756-1-git-send-email-hofrat@osadl.org>
On Sat, Dec 1, 2018 at 1:03 PM Nicholas Mc Guire <hofrat@osadl.org> wrote:
> devm_kzalloc(), devm_kstrdup() and devm_kasprintf() all can
> fail internal allocation and return NULL. Using any of the assigned
> objects without checking is not safe. As this is early in the boot
> phase and these allocations really should not fail, any failure here
> is probably an indication of a more serious issue so it makes little
> sense to try and rollback the previous allocated resources or try to
> continue; but rather the probe function is simply exited with -ENOMEM.
>
> Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
> Fixes: 684284b64aae ("ARM: integrator: add MMCI device to IM-PD1")
Looks good to me so patch applied to my Integrator tree
for fixes.
Yours,
Liinus Walleij
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^ permalink raw reply
* Re: [PATCH] iio: adc: Replace license text w/ SPDX identifier
From: Linus Walleij @ 2018-12-07 10:16 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Kim, Milo, Alexandre Belloni, Heiko Stübner, linux-aspeed,
Maxime Ripard, Michal Simek, Peter Meerwald, kernel-usp,
Lars-Peter Clausen, open list:ARM/Rockchip SoC..., Kevin Hilman,
Chen-Yu Tsai, Krzysztof Kozlowski, linux-iio, Ludovic Desroches,
Kukjin Kim, bcm-kernel-feedback-list, Joel Stanley,
Sylvain Lemieux, Michael Hennerich, Jon Mason, Ray Jui,
William Breathitt Gray, Vladimir Zapolskiy, Hans de Goede,
linux-samsung-soc, Andreas Klinger,
open list:ARM/Amlogic Meson..., ilucas.ms, matheus.bernardino,
Linux ARM, Support Opensource, Scott Branden, Andrew Jeffery,
linux-kernel@vger.kernel.org, Hartmut Knaack, Carlo Caione,
eugen.hristev
In-Reply-To: <20181201165550.51a78366@archlinux>
On Sat, Dec 1, 2018 at 5:56 PM Jonathan Cameron <jic23@kernel.org> wrote:
> +CC Linus Walleij as one of his files doesn't have a license...
Sorry about that. I am fine with GPL-2.0 or GPL-2.0+ on
any of "my" files. Feel free to add it with my Acked-by.
Yours,
Linus Walleij
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^ permalink raw reply
* [PATCH 0/3 REPOST] arm: covert a few spinlock_t locks to raw_spinlock_t
From: Sebastian Andrzej Siewior @ 2018-12-07 10:27 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann; +Cc: tglx, Russell King
Hi,
this small series converts a few spinlock_t locks to raw_spinlock_t.
This change makes no difference for !RT but is required for RT.
I added a few acks to first patch since the last repost [0]. Arnd
suggested that it might be best to route patch 1 via the arm-soc tree.
I hope that we can route patch 2 and 3 the same way.
[0] https://lkml.kernel.org/r/20180711110037.12928-1-bigeasy@linutronix.de
Sebastian
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^ permalink raw reply
* [PATCH 2/3] arm: kprobe: make patch_lock a raw_spinlock_t
From: Sebastian Andrzej Siewior @ 2018-12-07 10:27 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann
Cc: Yang Shi, tglx, Russell King, Sebastian Andrzej Siewior
In-Reply-To: <20181207102749.15205-1-bigeasy@linutronix.de>
From: Yang Shi <yang.shi@linaro.org>
When running kprobe on -rt kernel, the below bug is caught:
|BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
|in_atomic(): 1, irqs_disabled(): 128, pid: 14, name: migration/0
|Preemption disabled at:[<802f2b98>] cpu_stopper_thread+0xc0/0x140
|CPU: 0 PID: 14 Comm: migration/0 Tainted: G O 4.8.3-rt2 #1
|Hardware name: Freescale LS1021A
|[<8025a43c>] (___might_sleep)
|[<80b5b324>] (rt_spin_lock)
|[<80b5c31c>] (__patch_text_real)
|[<80b5c3ac>] (patch_text_stop_machine)
|[<802f2920>] (multi_cpu_stop)
Since patch_text_stop_machine() is called in stop_machine() which
disables IRQ, sleepable lock should be not used in this atomic context,
so replace patch_lock to raw lock.
Signed-off-by: Yang Shi <yang.shi@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/kernel/patch.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
index a50dc00d79a27..d0a05a3bdb965 100644
--- a/arch/arm/kernel/patch.c
+++ b/arch/arm/kernel/patch.c
@@ -16,7 +16,7 @@ struct patch {
unsigned int insn;
};
-static DEFINE_SPINLOCK(patch_lock);
+static DEFINE_RAW_SPINLOCK(patch_lock);
static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
__acquires(&patch_lock)
@@ -33,7 +33,7 @@ static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
return addr;
if (flags)
- spin_lock_irqsave(&patch_lock, *flags);
+ raw_spin_lock_irqsave(&patch_lock, *flags);
else
__acquire(&patch_lock);
@@ -48,7 +48,7 @@ static void __kprobes patch_unmap(int fixmap, unsigned long *flags)
clear_fixmap(fixmap);
if (flags)
- spin_unlock_irqrestore(&patch_lock, *flags);
+ raw_spin_unlock_irqrestore(&patch_lock, *flags);
else
__release(&patch_lock);
}
--
2.20.0.rc2
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* [PATCH 3/3] arm: use a raw_spinlock_t in unwind
From: Sebastian Andrzej Siewior @ 2018-12-07 10:27 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann
Cc: tglx, Russell King, Sebastian Andrzej Siewior
In-Reply-To: <20181207102749.15205-1-bigeasy@linutronix.de>
Mostly unwind is done with irqs enabled however SLUB may call it with
irqs disabled while creating a new SLUB cache.
I had system freeze while loading a module which called
kmem_cache_create() on init. That means SLUB's __slab_alloc() disabled
interrupts and then
->new_slab_objects()
->new_slab()
->setup_object()
->setup_object_debug()
->init_tracking()
->set_track()
->save_stack_trace()
->save_stack_trace_tsk()
->walk_stackframe()
->unwind_frame()
->unwind_find_idx()
=>spin_lock_irqsave(&unwind_lock);
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/kernel/unwind.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 0bee233fef9a3..314cfb232a635 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -93,7 +93,7 @@ extern const struct unwind_idx __start_unwind_idx[];
static const struct unwind_idx *__origin_unwind_idx;
extern const struct unwind_idx __stop_unwind_idx[];
-static DEFINE_SPINLOCK(unwind_lock);
+static DEFINE_RAW_SPINLOCK(unwind_lock);
static LIST_HEAD(unwind_tables);
/* Convert a prel31 symbol to an absolute address */
@@ -201,7 +201,7 @@ static const struct unwind_idx *unwind_find_idx(unsigned long addr)
/* module unwind tables */
struct unwind_table *table;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_for_each_entry(table, &unwind_tables, list) {
if (addr >= table->begin_addr &&
addr < table->end_addr) {
@@ -213,7 +213,7 @@ static const struct unwind_idx *unwind_find_idx(unsigned long addr)
break;
}
}
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
}
pr_debug("%s: idx = %p\n", __func__, idx);
@@ -529,9 +529,9 @@ struct unwind_table *unwind_table_add(unsigned long start, unsigned long size,
tab->begin_addr = text_addr;
tab->end_addr = text_addr + text_size;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_add_tail(&tab->list, &unwind_tables);
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
return tab;
}
@@ -543,9 +543,9 @@ void unwind_table_del(struct unwind_table *tab)
if (!tab)
return;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_del(&tab->list);
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
kfree(tab);
}
--
2.20.0.rc2
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* [PATCH] ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1
From: David HERNANDEZ SANCHEZ @ 2018-12-07 10:28 UTC (permalink / raw)
To: Maxime Coquelin, Alexandre TORGUE, Rob Herring, Mark Rutland
Cc: devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Enable STM32 Digital Thermal Sensor (dts) driver for
STM32MP157c-ed1 board.
Signed-off-by: David Hernandez Sanchez <david.hernandezsanchez@st.com>
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index c3ecb1e..98ef7a0 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -49,6 +49,10 @@
};
};
+&dts {
+ status = "okay";
+};
+
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
--
2.7.4
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* [PATCH 1/3] arm: Convert arm boot_lock to raw
From: Sebastian Andrzej Siewior @ 2018-12-07 10:27 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann
Cc: Tony Lindgren, Viresh Kumar, Linus Walleij, David Brown, Wei Xu,
Manivannan Sadhasivam, linux-samsung-soc, Viresh Kumar,
Russell King, Krzysztof Kozlowski, Maxime Ripard, Chen-Yu Tsai,
Kukjin Kim, Andy Gross, Sebastian Andrzej Siewior, linux-arm-msm,
tglx, linux-omap, Barry Song, Frank Rowand, Patrice Chotard,
Shiraz Hashim, Andreas Färber
In-Reply-To: <20181207102749.15205-1-bigeasy@linutronix.de>
From: Frank Rowand <frank.rowand@am.sony.com>
The arm boot_lock is used by the secondary processor startup code. The locking
task is the idle thread, which has idle->sched_class == &idle_sched_class.
idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
lock, the attempt to wake it when the lock becomes available will fail:
try_to_wake_up()
...
activate_task()
enqueue_task()
p->sched_class->enqueue_task(rq, p, flags)
Fix by converting boot_lock to a raw spin lock.
Cc: Andreas Färber <afaerber@suse.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Barry Song <baohua@kernel.org>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Viresh Kumar <vireshk@kernel.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org
Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tony Lindgren <tony@atomide.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Krzysztof Kozlowski <krzk@kernel.org> (Exynos5422 Linaro PM-QA)
Acked-by: Andreas Färber <afaerber@suse.de> (for mach-actions)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com> (for mach-sti)
Acked-by: Wei Xu <xuwei5@hisilicon.com> (for mach-hisi)
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/mach-actions/platsmp.c | 6 +++---
arch/arm/mach-exynos/platsmp.c | 12 ++++++------
arch/arm/mach-hisi/platmcpm.c | 22 +++++++++++-----------
arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
arch/arm/mach-prima2/platsmp.c | 10 +++++-----
arch/arm/mach-qcom/platsmp.c | 10 +++++-----
arch/arm/mach-spear/platsmp.c | 10 +++++-----
arch/arm/mach-sti/platsmp.c | 10 +++++-----
arch/arm/mach-sunxi/mc_smp.c | 20 ++++++++++----------
arch/arm/plat-versatile/platsmp.c | 10 +++++-----
10 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c
index 3efaa10efc439..770079245d273 100644
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -39,7 +39,7 @@ static void __iomem *sps_base_addr;
static void __iomem *timer_base_addr;
static int ncores;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void owl_secondary_startup(void);
@@ -93,7 +93,7 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
udelay(10);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
smp_send_reschedule(cpu);
@@ -106,7 +106,7 @@ static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return 0;
}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 6a1e682371b32..17dca0ff336e0 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -239,7 +239,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void exynos_secondary_init(unsigned int cpu)
{
@@ -252,8 +252,8 @@ static void exynos_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
@@ -317,7 +317,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -344,7 +344,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
if (timeout == 0) {
printk(KERN_ERR "cpu1 power enable failed");
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
}
@@ -390,7 +390,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
* calibrations, then wait for it to finish
*/
fail:
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? ret : 0;
}
diff --git a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c
index f66815c3dd07e..00524abd963f7 100644
--- a/arch/arm/mach-hisi/platmcpm.c
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -61,7 +61,7 @@
static void __iomem *sysctrl, *fabric;
static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static u32 fabric_phys_addr;
/*
* [0]: bootwrapper physical address
@@ -113,7 +113,7 @@ static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
return -EINVAL;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
if (hip04_cpu_table[cluster][cpu])
goto out;
@@ -147,7 +147,7 @@ static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
out:
hip04_cpu_table[cluster][cpu]++;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
@@ -162,11 +162,11 @@ static void hip04_cpu_die(unsigned int l_cpu)
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
hip04_cpu_table[cluster][cpu]--;
if (hip04_cpu_table[cluster][cpu] == 1) {
/* A power_up request went ahead of us. */
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return;
} else if (hip04_cpu_table[cluster][cpu] > 1) {
pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
@@ -174,7 +174,7 @@ static void hip04_cpu_die(unsigned int l_cpu)
}
last_man = hip04_cluster_is_down(cluster);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
if (last_man) {
/* Since it's Cortex A15, disable L2 prefetching. */
asm volatile(
@@ -203,7 +203,7 @@ static int hip04_cpu_kill(unsigned int l_cpu)
cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
count = TIMEOUT_MSEC / POLL_MSEC;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
for (tries = 0; tries < count; tries++) {
if (hip04_cpu_table[cluster][cpu])
goto err;
@@ -211,10 +211,10 @@ static int hip04_cpu_kill(unsigned int l_cpu)
data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
if (data & CORE_WFI_STATUS(cpu))
break;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
/* Wait for clean L2 when the whole cluster is down. */
msleep(POLL_MSEC);
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
}
if (tries >= count)
goto err;
@@ -231,10 +231,10 @@ static int hip04_cpu_kill(unsigned int l_cpu)
goto err;
if (hip04_cluster_is_down(cluster))
hip04_set_snoop_filter(cluster, 0);
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 1;
err:
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
#endif
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 1c73694c871ad..ac4d2f030b874 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -69,7 +69,7 @@ static const struct omap_smp_config omap5_cfg __initconst = {
.startup_addr = omap5_secondary_startup,
};
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void __iomem *omap4_get_scu_base(void)
{
@@ -177,8 +177,8 @@ static void omap4_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -191,7 +191,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* Update the AuxCoreBoot0 with boot state for secondary core.
@@ -270,7 +270,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return 0;
}
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 75ef5d4be554c..c17c86e5d860a 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -22,7 +22,7 @@
static void __iomem *clk_base;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void sirfsoc_secondary_init(unsigned int cpu)
{
@@ -36,8 +36,8 @@ static void sirfsoc_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static const struct of_device_id clk_ids[] = {
@@ -75,7 +75,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
/* make sure write buffer is drained */
mb();
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -107,7 +107,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 5494c9e0c909b..e8ce157d3548a 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -46,7 +46,7 @@
extern void secondary_startup_arm(void);
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
#ifdef CONFIG_HOTPLUG_CPU
static void qcom_cpu_die(unsigned int cpu)
@@ -60,8 +60,8 @@ static void qcom_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int scss_release_secondary(unsigned int cpu)
@@ -284,7 +284,7 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* Send the secondary CPU a soft interrupt, thereby causing
@@ -297,7 +297,7 @@ static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return ret;
}
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index 39038a03836ac..6da5c93872bf8 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -32,7 +32,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
@@ -47,8 +47,8 @@ static void spear13xx_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -59,7 +59,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -84,7 +84,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
index 231f19e174365..a3419b7003e6f 100644
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -35,7 +35,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void sti_secondary_init(unsigned int cpu)
{
@@ -48,8 +48,8 @@ static void sti_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -60,7 +60,7 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -91,7 +91,7 @@ static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index b4037b603897d..8a6c872f52b59 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -367,7 +367,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
int sunxi_mc_smp_first_comer;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
{
@@ -399,7 +399,7 @@ static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *i
if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
return -EINVAL;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
if (sunxi_mc_smp_cpu_table[cluster][cpu])
goto out;
@@ -417,7 +417,7 @@ static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *i
out:
sunxi_mc_smp_cpu_table[cluster][cpu]++;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
@@ -448,13 +448,13 @@ static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
sunxi_mc_smp_cpu_table[cluster][cpu]--;
if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
/* A power_up request went ahead of us. */
pr_debug("%s: aborting due to a power up request\n",
__func__);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return;
} else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
pr_err("Cluster %d CPU%d boots multiple times\n",
@@ -463,7 +463,7 @@ static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
}
last_man = sunxi_mc_smp_cluster_is_down(cluster);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
gic_cpu_if_down(0);
if (last_man)
@@ -542,11 +542,11 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
/* wait for CPU core to die and enter WFI */
count = TIMEOUT_USEC / POLL_USEC;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
for (tries = 0; tries < count; tries++) {
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
usleep_range(POLL_USEC / 2, POLL_USEC);
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
/*
* If the user turns off a bunch of cores at the same
@@ -593,7 +593,7 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
sunxi_cluster_powerdown(cluster);
out:
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
__func__, cluster, cpu, ret);
return !ret;
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index c2366510187a8..6b60f582b738c 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -32,7 +32,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void versatile_secondary_init(unsigned int cpu)
{
@@ -45,8 +45,8 @@ void versatile_secondary_init(unsigned int cpu)
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -57,7 +57,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* This is really belt and braces; we hold unintended secondary
@@ -87,7 +87,7 @@ int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
--
2.20.0.rc2
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^ permalink raw reply related
* [PATCH 0/2] AM654: Add ECAP PWM support
From: Vignesh R @ 2018-12-07 9:35 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon
Cc: devicetree, Rob Herring, linux-kernel, linux-arm-kernel,
Vignesh R
Couple of patches to add ECAP PWM support for AM654 SoC. Based on top of
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux.git 4.20-rc1-am65x-queue
Vignesh R (2):
arm64: dts: ti: k3-am65-main: Add ECAP PWM node
arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 +++++++++
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 11 +++++++++++
2 files changed, 20 insertions(+)
--
2.19.2
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^ permalink raw reply
* Re: [PATCH v2 5/5] ARM: spectre-v2: per-CPU vtables to work around big.Little systems
From: Russell King - ARM Linux @ 2018-12-07 10:37 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Mark Rutland, Julien Thierry, Marc Zyngier, Will Deacon,
Krzysztof Kozlowski, Qais.Yousef, linux-arm-kernel,
Morten.Rasmussen, dietmar.eggemann, Marek Szyprowski
In-Reply-To: <CAKv+Gu9hMQXunSmq56nz+Ndmu_mRAeump4VefY5yaa-_798QTg@mail.gmail.com>
On Fri, Dec 07, 2018 at 10:11:42AM +0100, Ard Biesheuvel wrote:
> Russell,
>
> I noticed that the patch merged by Linus has
>
> #if 1 // defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
>
> Was that what you intended?
Of course not - but it'll be harmless. That's what happens when you
end up hacking the patch to test it, have a cold and get distracted
with OMAP4 bug. Since it's harmless, I won't be intending to fix it
with any urgency, but thanks for pointing it out.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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^ permalink raw reply
* Re: [PATCH v7 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller
From: Liang Yang @ 2018-12-07 10:41 UTC (permalink / raw)
To: Miquel Raynal, Jianxin Pan
Cc: Rob Herring, Hanjie Lin, Victor Wan, Marek Vasut,
Martin Blumenstingl, Richard Weinberger, Neil Armstrong,
Yixun Lan, linux-kernel, Boris Brezillon, Jian Hu, linux-mtd,
Kevin Hilman, Carlo Caione, linux-amlogic, Brian Norris,
David Woodhouse, linux-arm-kernel, Jerome Brunet
In-Reply-To: <20181207104254.0ecfc1e5@xps13>
Hi Miquel,
Appreciate your time.
I will follow the nand/next and rework some next week as soon as possible.
On 2018/12/7 17:42, Miquel Raynal wrote:
> Hi Jianxin,
>
> Miquel Raynal <miquel.raynal@bootlin.com> wrote on Fri, 7 Dec 2018
> 10:24:56 +0100:
>
>> Hi Jianxin,
>>
>> Looks good to me overall, a few comments inline.
>>
>> Jianxin Pan <jianxin.pan@amlogic.com> wrote on Sat, 17 Nov 2018
>> 00:40:38 +0800:
>>
>>> From: Liang Yang <liang.yang@amlogic.com>
>>>
>>> Add initial support for the Amlogic NAND flash controller which found
>>> in the Meson-GXBB/GXL/AXG SoCs.
>>>
>>> Signed-off-by: Liang Yang <liang.yang@amlogic.com>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>> ---
>>> drivers/mtd/nand/raw/Kconfig | 10 +
>>> drivers/mtd/nand/raw/Makefile | 1 +
>>> drivers/mtd/nand/raw/meson_nand.c | 1417 +++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 1428 insertions(+)
>>> create mode 100644 drivers/mtd/nand/raw/meson_nand.c
>>>
>
> I forgot to mention, Boris has done more cleanup which breaks your
> patches, please have a look at the following commits in the nand/next
> branch, they will force you to do some light rework to get the driver
> building (especially, you should not export the ->select_chip hook anymore):
>
> 7a08dbaedd36 mtd: rawnand: Move ->setup_data_interface() to nand_controller_ops
> f2abfeb2078b mtd: rawnand: Move the ->exec_op() method to nand_controller_ops
> 7d6c37e90cf9 mtd: rawnand: Deprecate the ->select_chip() hook
> 1770022ffa85 mtd: rawnand: ams-delta: Stop implementing ->select_chip()
> 653c57c7da08 mtd: rawnand: vf610: Stop implementing ->select_chip()
> 2ace451cae22 mtd: rawnand: tegra: Stop implementing ->select_chip()
> b25251414f6e mtd: rawnand: marvell: Stop implementing ->select_chip()
> 550b9fc4e3af mtd: rawnand: fsmc: Stop implementing ->select_chip()
> 02b4a52604a4 mtd: rawnand: Make ->select_chip() optional when ->exec_op() is implemented
> ae2294b10b0f mtd: rawnand: Pass the CS line to be selected in struct nand_operation
> 1d0178593d14 mtd: rawnand: Add nand_[de]select_target() helpers
>
> Thanks,
> Miquèl
>
> .
>
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^ permalink raw reply
* Re: [RFC PATCH 4/6] dt-bindings: update mvneta binding document
From: Russell King - ARM Linux @ 2018-12-07 10:41 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mark Rutland, Rob Herring, Jason Cooper, Andrew Lunn, netdev,
Gregory CLEMENT, Maxime Chevallier, devicetree, Thomas Petazzoni,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Sebastian Hesselbarth
In-Reply-To: <2b832258-0b8f-a8f9-2907-878d0e4d6ee7@ti.com>
On Fri, Dec 07, 2018 at 09:37:54AM +0530, Kishon Vijay Abraham I wrote:
> Hi Russell,
>
> On 05/12/18 9:00 PM, Rob Herring wrote:
> > On Wed, Dec 5, 2018 at 5:00 AM Russell King - ARM Linux
> > <linux@armlinux.org.uk> wrote:
> >>
> >> On Mon, Dec 03, 2018 at 05:54:55PM -0600, Rob Herring wrote:
> >>> On Mon, Nov 12, 2018 at 12:31:02PM +0000, Russell King wrote:
> >>>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> >>>
> >>> Needs a better subject and a commit msg.
> >>
> >> Hmm, not sure why it didn't contain:
> >>
> >> "dt-bindings: net: mvneta: add phys property
> >>
> >> Add an optional phys property to the mvneta binding documentation for
> >> the common phy.
> >>
> >> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>"
> >>
> >> as the commit message. With the correct commit message, are you happy
> >> with it?
> >
> > Yes.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
>
> Are you planning to resend this series?
I'm not - you said previously that you had merged the first three
patches into the phy tree, which are fine. The next two could be
merged via netdev. However, we must avoid merging the last patch
with patch 5 if the patches are going via different trees or
mvneta will break.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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^ permalink raw reply
* Re: [PATCH V5 5/7] arm64: mm: Prevent mismatched 52-bit VA support
From: Suzuki K Poulose @ 2018-12-07 10:47 UTC (permalink / raw)
To: Steve Capper, linux-mm, linux-arm-kernel
Cc: catalin.marinas, will.deacon, jcm, ard.biesheuvel
In-Reply-To: <20181206225042.11548-6-steve.capper@arm.com>
Hi Steve,
On 12/06/2018 10:50 PM, Steve Capper wrote:
> For cases where there is a mismatch in ARMv8.2-LVA support between CPUs
> we have to be careful in allowing secondary CPUs to boot if 52-bit
> virtual addresses have already been enabled on the boot CPU.
>
> This patch adds code to the secondary startup path. If the boot CPU has
> enabled 52-bit VAs then ID_AA64MMFR2_EL1 is checked to see if the
> secondary can also enable 52-bit support. If not, the secondary is
> prevented from booting and an error message is displayed indicating why.
>
> Technically this patch could be implemented using the cpufeature code
> when considering 52-bit userspace support. However, we employ low level
> checks here as the cpufeature code won't be able to run if we have
> mismatched 52-bit kernel va support.
>
> Signed-off-by: Steve Capper <steve.capper@arm.com>
>
The patch looks good to me, except for one comment below.
> ---
>
> Patch is new in V5 of the series
> ---
> arch/arm64/kernel/head.S | 26 ++++++++++++++++++++++++++
> arch/arm64/kernel/smp.c | 5 +++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index f60081be9a1b..58fcc1edd852 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -707,6 +707,7 @@ secondary_startup:
> /*
> * Common entry point for secondary CPUs.
> */
> + bl __cpu_secondary_check52bitva
> bl __cpu_setup // initialise processor
> adrp x1, swapper_pg_dir
> bl __enable_mmu
> @@ -785,6 +786,31 @@ ENTRY(__enable_mmu)
> ret
> ENDPROC(__enable_mmu)
>
> +ENTRY(__cpu_secondary_check52bitva)
> +#ifdef CONFIG_ARM64_52BIT_VA
> + ldr_l x0, vabits_user
> + cmp x0, #52
> + b.ne 2f > +
> + mrs_s x0, SYS_ID_AA64MMFR2_EL1
> + and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
> + cbnz x0, 2f
> +
> + adr_l x0, va52mismatch
> + mov w1, #1
> + strb w1, [x0]
> + dmb sy
> + dc ivac, x0 // Invalidate potentially stale cache line
You may have to clear this variable before a CPU is brought up to avoid
raising a false error message when another secondary CPU doesn't boot
for some other reason (say granule support) after a CPU failed with lack
of 52bitva. It is really a crazy corner case.
Otherwise looks good to me.
Cheers
Suzuki
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* Re: arm64: WARN_ON_ONCE issue when resuming from hibernation
From: Will Deacon @ 2018-12-07 10:47 UTC (permalink / raw)
To: Kunihiko Hayashi; +Cc: arm, james.morse, linux-arm-kernel
In-Reply-To: <20181207104049.5F64.4A936039@socionext.com>
[+ James]
On Fri, Dec 07, 2018 at 10:40:50AM +0900, Kunihiko Hayashi wrote:
> I found that a WARN_ON_ONCE dump occured in the resuming sequence from
> hibernation on arm64 SoC (I use UniPhier LD20 environment).
>
> ...
> Disabling non-boot CPUs ...
> CPU1: shutdown
> psci: CPU1 killed.
> CPU2: shutdown
> psci: CPU2 killed.
> CPU3: shutdown
> psci: CPU3 killed.
> WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
> Modules linked in:
> CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1
> ...
>
> I show the result of reading the code, however,
> I'm not sure that this issue occurs in other arm64 SoC.
>
> In the resuming sequence, once all CPUs are stopped and local IRQs
> are disabled [1].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/power/hibernate.c?h=v4.20-rc4#n450
>
> In case of arm64, flush_icache_range() will be called after that.
> This calls kick_all_cpus_sync() to sync all CPUs with IPI, and
> since local IRQs are disabled, WARN_ON_ONCE() will be called in
> smp_call_function_many() [2].
>
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/smp.c?h=v4.20-rc4#n415
>
> The following tree shows a part of the callgraph.
>
> resume_target_kernel()
> +- local_irq_disable()
> +- swsusp_arch_resume() /* for arm64 */
> +- create_safe_exec_page() /* for arm64 */
> +- flush_icache_range() /* for arm64 */
> +- kick_all_cpus_sync()
> +- smp_call_function()
> +- smp_call_function_many()
> +- WARN_ON_ONCE(irq_disabled())
>
> What is the possible way to solve this issue?
Given that all secondary CPUs are hotplugged out at this point, we can
just use the non-IPI version of flush_icache_range(). Completely untested
diff below.
Will
--->8
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index 6b2686d54411..29cdc99688f3 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -214,7 +214,7 @@ static int create_safe_exec_page(void *src_start, size_t length,
}
memcpy((void *)dst, src_start, length);
- flush_icache_range(dst, dst + length);
+ __flush_icache_range(dst, dst + length);
pgdp = pgd_offset_raw(allocator(mask), dst_addr);
if (pgd_none(READ_ONCE(*pgdp))) {
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