* Re: WARNING in __mmdrop
From: Jason Gunthorpe @ 2019-07-31 23:00 UTC (permalink / raw)
To: Jason Wang
Cc: mhocko, Michael S. Tsirkin, peterz, ldv, james.bottomley,
linux-mm, namit, mingo, elena.reshetova, keescook, aarcange,
davem, hch, christian, syzbot, syzkaller-bugs, jglisse, viro,
linux-arm-kernel, wad, linux-parisc, linux-kernel, luto, ebiederm,
akpm, guro
In-Reply-To: <421a1af6-df06-e4a6-b34f-526ac123bc4a@redhat.com>
On Wed, Jul 31, 2019 at 04:49:32PM +0800, Jason Wang wrote:
> Yes, looking at the synchronization implemented by other MMU notifiers.
> Vhost is even the simplest.
I think that is only because it calls gup under a spinlock, which is,
IMHO, not great.
Jason
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 00/14] ARM: move lpc32xx and dove to multiplatform
From: Russell King - ARM Linux admin @ 2019-07-31 22:53 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Andrew Lunn, linux-watchdog, Jason Cooper, David S. Miller,
Greg Kroah-Hartman, Linus Walleij, linux-usb, Vladimir Zapolskiy,
linux-gpio, soc, netdev, Alan Stern, Guenter Roeck, linux-serial,
Sylvain Lemieux, Gregory Clement, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20190731195713.3150463-1-arnd@arndb.de>
On Wed, Jul 31, 2019 at 09:56:42PM +0200, Arnd Bergmann wrote:
> For dove, the patches are basically what I had proposed back in
> 2015 when all other ARMv6/ARMv7 machines became part of a single
> kernel build. I don't know what the state is mach-dove support is,
> compared to the DT based support in mach-mvebu for the same
> hardware. If they are functionally the same, we could also just
> remove mach-dove rather than applying my patches.
Well, the good news is that I'm down to a small board support file
for the Dove Cubox now - but the bad news is, that there's still a
board support file necessary to support everything the Dove SoC has
to offer.
Even for a DT based Dove Cubox, I'm still using mach-dove, but it
may be possible to drop most of mach-dove now. Without spending a
lot of time digging through it, it's impossible to really know.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
From: "Andrew F. Davis" <afd@ti.com>
The Programmable Real-Time Unit Subsystem (PRUSS) contains a local
interrupt controller (INTC) that can handle various system input events
and post interrupts back to the device-level initiators. The INTC can
support upto 64 input events with individual control configuration and
hardware prioritization. These events are mapped onto 10 output interrupt
lines through two levels of many-to-one mapping support. Different
interrupt lines are routed to the individual PRU cores or to the host
CPU, or to other devices on the SoC. Some of these events are sourced
from peripherals or other sub-modules within that PRUSS, while a few
others are sourced from SoC-level peripherals/devices.
The PRUSS INTC platform driver manages this PRUSS interrupt controller
and implements an irqchip driver to provide a Linux standard way for
the PRU client users to enable/disable/ack/re-trigger a PRUSS system
event. The system events to interrupt channels and output interrupts
relies on the mapping configuration provided either through the PRU
firmware blob or via the PRU application's device tree node. The
mappings will be programmed during the boot/shutdown of a PRU core.
The PRUSS INTC module is reference counted during the interrupt
setup phase through the irqchip's irq_request_resources() and
irq_release_resources() ops. This restricts the module from being
removed as long as there are active interrupt users.
The driver currently supports and can be built for OMAP architecture
based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based
66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs.
All of these SoCs support 64 system events, 10 interrupt channels and
10 output interrupt lines per PRUSS INTC with a few SoC integration
differences.
NOTE:
Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that
enables multiple external events to be routed to a specific number
of input interrupt events. Any non-default external interrupt event
directed towards PRUSS needs this crossbar to be setup properly.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
v2:
- Addressed all of David Lechner's comments
- Dropped irq_retrigger callback
- Updated interrupt names from "hostX" to "host_intrX"
- Moved host_mask variable to patch 4
v1: https://patchwork.kernel.org/patch/11034545/
v0: https://patchwork.kernel.org/patch/10795761/
drivers/irqchip/Kconfig | 10 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++
3 files changed, 349 insertions(+)
create mode 100644 drivers/irqchip/irq-pruss-intc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 80e10f4e213a..dc6b5aa77a5d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP
If you wish to use interrupt aggregator irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
+config TI_PRUSS_INTC
+ tristate "TI PRU-ICSS Interrupt Controller"
+ depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
+ select IRQ_DOMAIN
+ help
+ This enables support for the PRU-ICSS Local Interrupt Controller
+ present within a PRU-ICSS subsystem present on various TI SoCs.
+ The PRUSS INTC enables various interrupts to be routed to multiple
+ different processors within the SoC.
+
endmenu
config SIFIVE_PLIC
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 8d0fcec6ab23..a02e652ca805 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o
+obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
new file mode 100644
index 000000000000..4a9456544fd0
--- /dev/null
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-ICSS INTC IRQChip driver for various TI SoCs
+ *
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Andrew F. Davis <afd@ti.com>
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+/*
+ * Number of host interrupts reaching the main MPU sub-system. Note that this
+ * is not the same as the total number of host interrupts supported by the PRUSS
+ * INTC instance
+ */
+#define MAX_NUM_HOST_IRQS 8
+
+/* minimum starting host interrupt number for MPU */
+#define MIN_PRU_HOST_INT 2
+
+/* maximum number of system events */
+#define MAX_PRU_SYS_EVENTS 64
+
+/* PRU_ICSS_INTC registers */
+#define PRU_INTC_REVID 0x0000
+#define PRU_INTC_CR 0x0004
+#define PRU_INTC_GER 0x0010
+#define PRU_INTC_GNLR 0x001c
+#define PRU_INTC_SISR 0x0020
+#define PRU_INTC_SICR 0x0024
+#define PRU_INTC_EISR 0x0028
+#define PRU_INTC_EICR 0x002c
+#define PRU_INTC_HIEISR 0x0034
+#define PRU_INTC_HIDISR 0x0038
+#define PRU_INTC_GPIR 0x0080
+#define PRU_INTC_SRSR0 0x0200
+#define PRU_INTC_SRSR1 0x0204
+#define PRU_INTC_SECR0 0x0280
+#define PRU_INTC_SECR1 0x0284
+#define PRU_INTC_ESR0 0x0300
+#define PRU_INTC_ESR1 0x0304
+#define PRU_INTC_ECR0 0x0380
+#define PRU_INTC_ECR1 0x0384
+#define PRU_INTC_CMR(x) (0x0400 + (x) * 4)
+#define PRU_INTC_HMR(x) (0x0800 + (x) * 4)
+#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4)
+#define PRU_INTC_SIPR0 0x0d00
+#define PRU_INTC_SIPR1 0x0d04
+#define PRU_INTC_SITR0 0x0d80
+#define PRU_INTC_SITR1 0x0d84
+#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
+#define PRU_INTC_HIER 0x1500
+
+/* HIPIR register bit-fields */
+#define INTC_HIPIR_NONE_HINT 0x80000000
+
+/**
+ * struct pruss_intc - PRUSS interrupt controller structure
+ * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
+ * @base: base virtual address of INTC register space
+ * @irqchip: irq chip for this interrupt controller
+ * @domain: irq domain for this interrupt controller
+ * @lock: mutex to serialize access to INTC
+ */
+struct pruss_intc {
+ unsigned int irqs[MAX_NUM_HOST_IRQS];
+ void __iomem *base;
+ struct irq_chip *irqchip;
+ struct irq_domain *domain;
+ struct mutex lock; /* PRUSS INTC lock */
+};
+
+static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
+{
+ return readl_relaxed(intc->base + reg);
+}
+
+static inline void pruss_intc_write_reg(struct pruss_intc *intc,
+ unsigned int reg, u32 val)
+{
+ writel_relaxed(val, intc->base + reg);
+}
+
+static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
+ unsigned int sysevent)
+{
+ if (!intc)
+ return -EINVAL;
+
+ if (sysevent >= MAX_PRU_SYS_EVENTS)
+ return -EINVAL;
+
+ pruss_intc_write_reg(intc, reg, sysevent);
+
+ return 0;
+}
+
+static void pruss_intc_init(struct pruss_intc *intc)
+{
+ int i;
+
+ /* configure polarity to active high for all system interrupts */
+ pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
+ pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
+
+ /* configure type to pulse interrupt for all system interrupts */
+ pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
+ pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
+
+ /* clear all 16 interrupt channel map registers */
+ for (i = 0; i < 16; i++)
+ pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
+
+ /* clear all 3 host interrupt map registers */
+ for (i = 0; i < 3; i++)
+ pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
+}
+
+static void pruss_intc_irq_ack(struct irq_data *data)
+{
+ struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+ unsigned int hwirq = data->hwirq;
+
+ pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
+}
+
+static void pruss_intc_irq_mask(struct irq_data *data)
+{
+ struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+ unsigned int hwirq = data->hwirq;
+
+ pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq);
+}
+
+static void pruss_intc_irq_unmask(struct irq_data *data)
+{
+ struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+ unsigned int hwirq = data->hwirq;
+
+ pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq);
+}
+
+static int pruss_intc_irq_reqres(struct irq_data *data)
+{
+ if (!try_module_get(THIS_MODULE))
+ return -ENODEV;
+
+ return 0;
+}
+
+static void pruss_intc_irq_relres(struct irq_data *data)
+{
+ module_put(THIS_MODULE);
+}
+
+static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct pruss_intc *intc = d->host_data;
+
+ irq_set_chip_data(virq, intc);
+ irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
+
+ return 0;
+}
+
+static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
+{
+ irq_set_chip_and_handler(virq, NULL, NULL);
+ irq_set_chip_data(virq, NULL);
+}
+
+static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = pruss_intc_irq_domain_map,
+ .unmap = pruss_intc_irq_domain_unmap,
+};
+
+static void pruss_intc_irq_handler(struct irq_desc *desc)
+{
+ unsigned int irq = irq_desc_get_irq(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct pruss_intc *intc = irq_get_handler_data(irq);
+ u32 hipir;
+ unsigned int virq;
+ int i, hwirq;
+
+ chained_irq_enter(chip, desc);
+
+ /* find our host irq number */
+ for (i = 0; i < MAX_NUM_HOST_IRQS; i++)
+ if (intc->irqs[i] == irq)
+ break;
+ if (i == MAX_NUM_HOST_IRQS)
+ goto err;
+
+ i += MIN_PRU_HOST_INT;
+
+ /* get highest priority pending PRUSS system event */
+ hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
+ while (!(hipir & INTC_HIPIR_NONE_HINT)) {
+ hwirq = hipir & GENMASK(9, 0);
+ virq = irq_linear_revmap(intc->domain, hwirq);
+
+ /*
+ * NOTE: manually ACK any system events that do not have a
+ * handler mapped yet
+ */
+ if (unlikely(!virq))
+ pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq);
+ else
+ generic_handle_irq(virq);
+
+ /* get next system event */
+ hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
+ }
+err:
+ chained_irq_exit(chip, desc);
+}
+
+static int pruss_intc_probe(struct platform_device *pdev)
+{
+ static const char * const irq_names[] = {
+ "host_intr0", "host_intr1", "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5", "host_intr6", "host_intr7", };
+ struct device *dev = &pdev->dev;
+ struct pruss_intc *intc;
+ struct resource *res;
+ struct irq_chip *irqchip;
+ int i, irq;
+
+ intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
+ if (!intc)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, intc);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ intc->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(intc->base)) {
+ dev_err(dev, "failed to parse and map intc memory resource\n");
+ return PTR_ERR(intc->base);
+ }
+
+ dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
+ (size_t)resource_size(res), intc->base);
+
+ mutex_init(&intc->lock);
+
+ pruss_intc_init(intc);
+
+ irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
+ if (!irqchip)
+ return -ENOMEM;
+
+ irqchip->irq_ack = pruss_intc_irq_ack;
+ irqchip->irq_mask = pruss_intc_irq_mask;
+ irqchip->irq_unmask = pruss_intc_irq_unmask;
+ irqchip->irq_request_resources = pruss_intc_irq_reqres;
+ irqchip->irq_release_resources = pruss_intc_irq_relres;
+ irqchip->name = dev_name(dev);
+ intc->irqchip = irqchip;
+
+ /* always 64 events */
+ intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
+ &pruss_intc_irq_domain_ops, intc);
+ if (!intc->domain)
+ return -ENOMEM;
+
+ for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
+ irq = platform_get_irq_byname(pdev, irq_names[i]);
+ if (irq < 0) {
+ dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
+ irq_names[i], irq);
+ goto fail_irq;
+ }
+
+ intc->irqs[i] = irq;
+ irq_set_handler_data(irq, intc);
+ irq_set_chained_handler(irq, pruss_intc_irq_handler);
+ }
+
+ return 0;
+
+fail_irq:
+ while (--i >= 0) {
+ if (intc->irqs[i])
+ irq_set_chained_handler_and_data(intc->irqs[i], NULL,
+ NULL);
+ }
+ irq_domain_remove(intc->domain);
+ return irq;
+}
+
+static int pruss_intc_remove(struct platform_device *pdev)
+{
+ struct pruss_intc *intc = platform_get_drvdata(pdev);
+ unsigned int hwirq;
+ int i;
+
+ for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
+ if (intc->irqs[i])
+ irq_set_chained_handler_and_data(intc->irqs[i], NULL,
+ NULL);
+ }
+
+ for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
+ irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
+ irq_domain_remove(intc->domain);
+
+ return 0;
+}
+
+static const struct of_device_id pruss_intc_of_match[] = {
+ { .compatible = "ti,pruss-intc", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
+
+static struct platform_driver pruss_intc_driver = {
+ .driver = {
+ .name = "pruss-intc",
+ .of_match_table = pruss_intc_of_match,
+ },
+ .probe = pruss_intc_probe,
+ .remove = pruss_intc_remove,
+};
+module_platform_driver(pruss_intc_driver);
+
+MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
+MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
+MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
+MODULE_LICENSE("GPL v2");
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 6/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP,
commonly called ICSSG. The PRUSS INTC present within the ICSSG supports
more System Events (160 vs 64), more Interrupt Channels and Host Interrupts
(20 vs 10) compared to the previous generation PRUSS INTC instances. The
first 2 and the last 10 of these host interrupt lines are used by the
PRU and other auxiliary cores and sub-modules within the ICSSG, with 8
host interrupts connected to MPU. The host interrupts 5, 6, 7 are also
connected to the other ICSSG instances within the SoC and can be
partitioned as per system integration through the board dts files.
Enhance the PRUSS INTC driver to add support for this ICSSG INTC
instance. This support is added using specific compatible and match
data and updating the code to use this data instead of the current
hard-coded macros. The INTC config structure is updated to use the
higher events and channels on all SoCs, while limiting the actual
processing to only the relevant number of events/channels/interrupts.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
- Rebased patch with indexed macros like ESRx, ECRx where x = 0,1 dropped
v1: https://patchwork.kernel.org/patch/11034543/
drivers/irqchip/Kconfig | 2 +-
drivers/irqchip/irq-pruss-intc.c | 181 +++++++++++++++++--------
include/linux/irqchip/irq-pruss-intc.h | 4 +-
3 files changed, 126 insertions(+), 61 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index dc6b5aa77a5d..a98bfec6b364 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -473,7 +473,7 @@ config TI_SCI_INTA_IRQCHIP
config TI_PRUSS_INTC
tristate "TI PRU-ICSS Interrupt Controller"
- depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE
+ depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3
select IRQ_DOMAIN
help
This enables support for the PRU-ICSS Local Interrupt Controller
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 59e26dfbb179..891a14b6c399 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -7,6 +7,7 @@
* Suman Anna <s-anna@ti.com>
*/
+#include <linux/bitmap.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
@@ -26,9 +27,6 @@
/* minimum starting host interrupt number for MPU */
#define MIN_PRU_HOST_INT 2
-/* maximum number of host interrupts */
-#define MAX_PRU_HOST_INT 10
-
/* PRU_ICSS_INTC registers */
#define PRU_INTC_REVID 0x0000
#define PRU_INTC_CR 0x0004
@@ -42,19 +40,14 @@
#define PRU_INTC_HIDISR 0x0038
#define PRU_INTC_GPIR 0x0080
#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4)
-#define PRU_INTC_SECR0 0x0280
-#define PRU_INTC_SECR1 0x0284
-#define PRU_INTC_ESR0 0x0300
-#define PRU_INTC_ESR1 0x0304
-#define PRU_INTC_ECR0 0x0380
-#define PRU_INTC_ECR1 0x0384
+#define PRU_INTC_SECR(x) (0x0280 + (x) * 4)
+#define PRU_INTC_ESR(x) (0x0300 + (x) * 4)
+#define PRU_INTC_ECR(x) (0x0380 + (x) * 4)
#define PRU_INTC_CMR(x) (0x0400 + (x) * 4)
#define PRU_INTC_HMR(x) (0x0800 + (x) * 4)
#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4)
-#define PRU_INTC_SIPR0 0x0d00
-#define PRU_INTC_SIPR1 0x0d04
-#define PRU_INTC_SITR0 0x0d80
-#define PRU_INTC_SITR1 0x0d84
+#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4)
+#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4)
#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
#define PRU_INTC_HIER 0x1500
@@ -71,12 +64,23 @@
/* HIPIR register bit-fields */
#define INTC_HIPIR_NONE_HINT 0x80000000
+/**
+ * struct pruss_intc_match_data - match data to handle SoC variations
+ * @num_system_events: number of input system events handled by the PRUSS INTC
+ * @num_host_intrs: number of host interrupts supported by the PRUSS INTC
+ */
+struct pruss_intc_match_data {
+ u8 num_system_events;
+ u8 num_host_intrs;
+};
+
/**
* struct pruss_intc - PRUSS interrupt controller structure
* @irqs: kernel irq numbers corresponding to PRUSS host interrupts
* @base: base virtual address of INTC register space
* @irqchip: irq chip for this interrupt controller
* @domain: irq domain for this interrupt controller
+ * @data: cached PRUSS INTC IP configuration data
* @config_map: stored INTC configuration mapping data
* @lock: mutex to serialize access to INTC
* @host_mask: indicate which HOST IRQs are enabled
@@ -88,6 +92,7 @@ struct pruss_intc {
void __iomem *base;
struct irq_chip *irqchip;
struct irq_domain *domain;
+ const struct pruss_intc_match_data *data;
struct pruss_intc_config config_map;
struct mutex lock; /* PRUSS INTC lock */
u32 host_mask;
@@ -112,7 +117,7 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
if (!intc)
return -EINVAL;
- if (sysevent >= MAX_PRU_SYS_EVENTS)
+ if (sysevent >= intc->data->num_system_events)
return -EINVAL;
pruss_intc_write_reg(intc, reg, sysevent);
@@ -191,16 +196,28 @@ int pruss_intc_configure(struct device *dev,
struct pruss_intc_config *intc_config)
{
struct pruss_intc *intc;
- int i, idx, ret;
+ int i, idx;
s8 ch, host;
- u64 sysevt_mask = 0;
+ u32 num_events, num_intrs, num_regs;
+ unsigned long *sysevt_bitmap;
+ u32 *sysevts;
u32 ch_mask = 0;
u32 host_mask = 0;
+ int ret = 0;
intc = to_pruss_intc(dev);
if (IS_ERR(intc))
return PTR_ERR(intc);
+ num_events = intc->data->num_system_events;
+ num_intrs = intc->data->num_host_intrs;
+ num_regs = DIV_ROUND_UP(num_events, 32);
+
+ sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL);
+ if (!sysevt_bitmap)
+ return -ENOMEM;
+ sysevts = (u32 *)sysevt_bitmap;
+
mutex_lock(&intc->lock);
/*
@@ -208,7 +225,7 @@ int pruss_intc_configure(struct device *dev,
* for 4 events, with each event occupying the lower nibble in
* a register byte address in little-endian fashion
*/
- for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+ for (i = 0; i < num_events; i++) {
ch = intc_config->sysev_to_ch[i];
if (ch < 0)
continue;
@@ -223,7 +240,7 @@ int pruss_intc_configure(struct device *dev,
intc->config_map.sysev_to_ch[i] = ch;
pruss_intc_update_cmr(intc, i, ch);
- sysevt_mask |= BIT_ULL(i);
+ bitmap_set(sysevt_bitmap, i, 1);
ch_mask |= BIT(ch);
idx = i / CMR_EVT_PER_REG;
@@ -236,7 +253,7 @@ int pruss_intc_configure(struct device *dev,
* 4 channels, with each channel occupying the lower nibble in
* a register byte address in little-endian fashion
*/
- for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+ for (i = 0; i < num_intrs; i++) {
host = intc_config->ch_to_host[i];
if (host < 0)
continue;
@@ -267,17 +284,19 @@ int pruss_intc_configure(struct device *dev,
pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
}
- dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n",
- sysevt_mask, ch_mask, host_mask);
+ dev_info(dev, "configured system_events[%d-0] = %*pb\n",
+ num_events - 1, num_events, sysevt_bitmap);
+ dev_info(dev, "configured intr_channels = 0x%08x host_intr = 0x%08x\n",
+ ch_mask, host_mask);
/* enable system events, writing 0 has no-effect */
- pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask));
- pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
- pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask));
- pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+ for (i = 0; i < num_regs; i++) {
+ pruss_intc_write_reg(intc, PRU_INTC_ESR(i), sysevts[i]);
+ pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]);
+ }
/* enable host interrupts */
- for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+ for (i = 0; i < num_intrs; i++) {
if (host_mask & BIT(i))
pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i);
}
@@ -286,9 +305,7 @@ int pruss_intc_configure(struct device *dev,
pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
intc->host_mask |= host_mask;
-
- mutex_unlock(&intc->lock);
- return 0;
+ goto out;
fail_ch:
while (--i >= 0) {
@@ -297,7 +314,7 @@ int pruss_intc_configure(struct device *dev,
pruss_intc_update_hmr(intc, i, 0);
}
}
- i = ARRAY_SIZE(intc_config->sysev_to_ch);
+ i = num_events;
fail_evt:
while (--i >= 0) {
if (intc_config->sysev_to_ch[i] >= 0) {
@@ -305,7 +322,9 @@ int pruss_intc_configure(struct device *dev,
pruss_intc_update_cmr(intc, i, 0);
}
}
+out:
mutex_unlock(&intc->lock);
+ bitmap_free(sysevt_bitmap);
return ret;
}
EXPORT_SYMBOL_GPL(pruss_intc_configure);
@@ -325,28 +344,39 @@ int pruss_intc_unconfigure(struct device *dev,
struct pruss_intc *intc;
int i;
s8 ch, host;
- u64 sysevt_mask = 0;
+ u32 num_events, num_intrs, num_regs;
+ unsigned long *sysevt_bitmap;
+ u32 *sysevts;
u32 host_mask = 0;
intc = to_pruss_intc(dev);
if (IS_ERR(intc))
return PTR_ERR(intc);
+ num_events = intc->data->num_system_events;
+ num_intrs = intc->data->num_host_intrs;
+ num_regs = DIV_ROUND_UP(num_events, 32);
+
+ sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL);
+ if (!sysevt_bitmap)
+ return -ENOMEM;
+ sysevts = (u32 *)sysevt_bitmap;
+
mutex_lock(&intc->lock);
- for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+ for (i = 0; i < num_events; i++) {
ch = intc_config->sysev_to_ch[i];
if (ch < 0)
continue;
/* mark sysevent free in global map */
intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
- sysevt_mask |= BIT_ULL(i);
+ bitmap_set(sysevt_bitmap, i, 1);
/* clear the map using reset value 0 */
pruss_intc_update_cmr(intc, i, 0);
}
- for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+ for (i = 0; i < num_intrs; i++) {
host = intc_config->ch_to_host[i];
if (host < 0)
continue;
@@ -358,24 +388,26 @@ int pruss_intc_unconfigure(struct device *dev,
pruss_intc_update_hmr(intc, i, 0);
}
- dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n",
- sysevt_mask, host_mask);
+ dev_info(dev, "unconfigured system_events[%d-0] = %*pb\n",
+ num_events - 1, num_events, sysevt_bitmap);
+ dev_info(dev, "unconfigured host_intr = 0x%08x\n", host_mask);
- /* disable system events, writing 0 has no-effect */
- pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask));
- pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask));
- /* clear any pending status */
- pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
- pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+ for (i = 0; i < num_regs; i++) {
+ /* disable system events, writing 0 has no-effect */
+ pruss_intc_write_reg(intc, PRU_INTC_ECR(i), sysevts[i]);
+ /* clear any pending status */
+ pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]);
+ }
/* disable host interrupts */
- for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+ for (i = 0; i < num_intrs; i++) {
if (host_mask & BIT(i))
pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i);
}
intc->host_mask &= ~host_mask;
mutex_unlock(&intc->lock);
+ bitmap_free(sysevt_bitmap);
return 0;
}
@@ -384,21 +416,28 @@ EXPORT_SYMBOL_GPL(pruss_intc_unconfigure);
static void pruss_intc_init(struct pruss_intc *intc)
{
int i;
+ int num_chnl_map_regs = DIV_ROUND_UP(intc->data->num_system_events,
+ CMR_EVT_PER_REG);
+ int num_host_intr_regs = DIV_ROUND_UP(intc->data->num_host_intrs,
+ HMR_CH_PER_REG);
+ int num_event_type_regs =
+ DIV_ROUND_UP(intc->data->num_system_events, 32);
- /* configure polarity to active high for all system interrupts */
- pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff);
- pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff);
-
- /* configure type to pulse interrupt for all system interrupts */
- pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0);
- pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0);
+ /*
+ * configure polarity (SIPR register) to active high and
+ * type (SITR register) to pulse interrupt for all system events
+ */
+ for (i = 0; i < num_event_type_regs; i++) {
+ pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
+ pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
+ }
- /* clear all 16 interrupt channel map registers */
- for (i = 0; i < 16; i++)
+ /* clear all interrupt channel map registers, 4 events per register */
+ for (i = 0; i < num_chnl_map_regs; i++)
pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
- /* clear all 3 host interrupt map registers */
- for (i = 0; i < 3; i++)
+ /* clear all host interrupt map registers, 4 channels per register */
+ for (i = 0; i < num_host_intr_regs; i++)
pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
}
@@ -549,11 +588,20 @@ static int pruss_intc_probe(struct platform_device *pdev)
struct resource *res;
struct irq_chip *irqchip;
int i, irq, count;
+ const struct pruss_intc_match_data *data;
u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
+ u8 max_system_events;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -ENODEV;
+
+ max_system_events = data->num_system_events;
intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
if (!intc)
return -ENOMEM;
+ intc->data = data;
platform_set_drvdata(pdev, intc);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -623,8 +671,7 @@ static int pruss_intc_probe(struct platform_device *pdev)
irqchip->name = dev_name(dev);
intc->irqchip = irqchip;
- /* always 64 events */
- intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
+ intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
&pruss_intc_irq_domain_ops, intc);
if (!intc->domain)
return -ENOMEM;
@@ -661,6 +708,7 @@ static int pruss_intc_probe(struct platform_device *pdev)
static int pruss_intc_remove(struct platform_device *pdev)
{
struct pruss_intc *intc = platform_get_drvdata(pdev);
+ u8 max_system_events = intc->data->num_system_events;
unsigned int hwirq;
int i;
@@ -670,15 +718,32 @@ static int pruss_intc_remove(struct platform_device *pdev)
NULL);
}
- for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
+ for (hwirq = 0; hwirq < max_system_events; hwirq++)
irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
irq_domain_remove(intc->domain);
return 0;
}
+static const struct pruss_intc_match_data pruss_intc_data = {
+ .num_system_events = 64,
+ .num_host_intrs = 10,
+};
+
+static const struct pruss_intc_match_data icssg_intc_data = {
+ .num_system_events = 160,
+ .num_host_intrs = 20,
+};
+
static const struct of_device_id pruss_intc_of_match[] = {
- { .compatible = "ti,pruss-intc", },
+ {
+ .compatible = "ti,pruss-intc",
+ .data = &pruss_intc_data,
+ },
+ {
+ .compatible = "ti,icssg-intc",
+ .data = &icssg_intc_data,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h
index daffc048b303..cc6f9190b04f 100644
--- a/include/linux/irqchip/irq-pruss-intc.h
+++ b/include/linux/irqchip/irq-pruss-intc.h
@@ -10,10 +10,10 @@
#define __LINUX_IRQ_PRUSS_INTC_H
/* maximum number of system events */
-#define MAX_PRU_SYS_EVENTS 64
+#define MAX_PRU_SYS_EVENTS 160
/* maximum number of interrupt channels */
-#define MAX_PRU_CHANNELS 10
+#define MAX_PRU_CHANNELS 20
/* use -1 to mark unassigned events and channels */
#define PRU_INTC_FREE -1
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 5/6] irqchip/irq-pruss-intc: Implement irq_{get, set}_irqchip_state ops
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
From: David Lechner <david@lechnology.com>
This implements the irq_get_irqchip_state and irq_set_irqchip_state
callbacks for the TI PRUSS INTC driver. The set callback can be used
by drivers to "kick" a PRU by enabling a PRU system event.
Example:
irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, true);
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2: New patch from David replacing an exported API from v1,
https://patchwork.kernel.org/patch/11034565/
drivers/irqchip/irq-pruss-intc.c | 41 ++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 63cfc665be1e..59e26dfbb179 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -7,6 +7,7 @@
* Suman Anna <s-anna@ti.com>
*/
+#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/irq-pruss-intc.h>
@@ -40,8 +41,7 @@
#define PRU_INTC_HIEISR 0x0034
#define PRU_INTC_HIDISR 0x0038
#define PRU_INTC_GPIR 0x0080
-#define PRU_INTC_SRSR0 0x0200
-#define PRU_INTC_SRSR1 0x0204
+#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4)
#define PRU_INTC_SECR0 0x0280
#define PRU_INTC_SECR1 0x0284
#define PRU_INTC_ESR0 0x0300
@@ -439,6 +439,41 @@ static void pruss_intc_irq_relres(struct irq_data *data)
module_put(THIS_MODULE);
}
+static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
+ enum irqchip_irq_state which,
+ bool *state)
+{
+ struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+ u32 reg, mask, srsr;
+
+ if (which != IRQCHIP_STATE_PENDING)
+ return -EINVAL;
+
+ reg = PRU_INTC_SRSR(data->hwirq / 32);
+ mask = BIT(data->hwirq % 32);
+
+ srsr = pruss_intc_read_reg(intc, reg);
+
+ *state = !!(srsr & mask);
+
+ return 0;
+}
+
+static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
+ enum irqchip_irq_state which,
+ bool state)
+{
+ struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
+
+ if (which != IRQCHIP_STATE_PENDING)
+ return -EINVAL;
+
+ if (state)
+ return pruss_intc_check_write(intc, PRU_INTC_SISR, data->hwirq);
+
+ return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq);
+}
+
static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
@@ -583,6 +618,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
irqchip->irq_unmask = pruss_intc_irq_unmask;
irqchip->irq_request_resources = pruss_intc_irq_reqres;
irqchip->irq_release_resources = pruss_intc_irq_relres;
+ irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state;
+ irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state;
irqchip->name = dev_name(dev);
intc->irqchip = irqchip;
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 1/6] dt-bindings: irqchip: Add PRUSS interrupt controller bindings
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Rob Herring,
Tony Lindgren, Sekhar Nori, linux-kernel, Andrew F. Davis,
Lokesh Vutla, Rob Herring, Murali Karicheri, linux-omap,
linux-arm-kernel, Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt
controller (INTC) that can handle various system input events and post
interrupts back to the device-level initiators. The INTC can support
upto 64 input events on most SoCs with individual control configuration
and hardware prioritization. These events are mapped onto 10 output
interrupt lines through two levels of many-to-one mapping support.
Different interrupt lines are routed to the individual PRU cores or
to the host CPU or to other PRUSS instances.
The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP,
commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide
a higher number of host interrupts (20 vs 10) and can handle an increased
number of input events (160 vs 64) from various SoC interrupt sources.
Add the bindings document for these interrupt controllers on all the
applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x
and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci
architecture based OMAPL138 SoCs, and the K3 architecture based AM65x
and J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v2:
- Updated the interrupt-names from "hostX" to "host_intrX" and updated
example accordingly
- Updated the description for interrupts property
- Used generic interrupt controller in descriptions rather than GIC
- Added some clarifications about interrupt names to PRUSS INTC output
interrupts
- Picked up Rob's reviewed-by
v1: https://patchwork.kernel.org/patch/11034567/
.../interrupt-controller/ti,pruss-intc.txt | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
new file mode 100644
index 000000000000..17c7b49a7f2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
@@ -0,0 +1,98 @@
+PRU ICSS INTC on TI SoCs
+========================
+
+Each PRUSS has a single interrupt controller instance that is common to both
+the PRU cores. Most interrupt controllers can route 64 input events which are
+then mapped to 10 possible output interrupts through two levels of mapping.
+The input events can be triggered by either the PRUs and/or various other PRUSS
+internal and external peripherals. The first 2 output interrupts (0 & 1) are
+fed exclusively to the internal PRU cores, with the remaining 8 (2 through 9)
+connected to external interrupt controllers including the MPU and/or other
+PRUSS instances, DSPs or devices.
+
+The K3 family of SoCs can handle 160 input events that can be mapped to 20
+different possible output interrupts. The additional output interrupts (10
+through 19) are connected to new sub-modules within the ICSSG instances.
+
+This interrupt-controller node should be defined as a child node of the
+corresponding PRUSS node. The node should be named "interrupt-controller".
+Please see the overall PRUSS bindings document for additional details
+including a complete example,
+ Documentation/devicetree/bindings/soc/ti/ti,pruss.txt
+
+Required Properties:
+--------------------
+- compatible : should be one of the following,
+ "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
+ AM335x family of SoCs,
+ AM437x family of SoCs,
+ AM57xx family of SoCs
+ 66AK2G family of SoCs
+ "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
+- reg : base address and size for the PRUSS INTC sub-module
+- interrupts : all the interrupts generated towards the main host
+ processor in the SoC. The format depends on the
+ interrupt specifier for the particular SoC's Arm
+ parent interrupt controller. A shared interrupt can
+ be skipped if the desired destination and usage is by
+ a different processor/device.
+- interrupt-names : should use one of the following names for each valid
+ host event interrupt connected to Arm interrupt
+ controller, the name should match the corresponding
+ host event interrupt number,
+ "host_intr0", "host_intr1", "host_intr2",
+ "host_intr3", "host_intr4", "host_intr5",
+ "host_intr6" or "host_intr7"
+- interrupt-controller : mark this node as an interrupt controller
+- #interrupt-cells : should be 1. Client users shall use the PRU System
+ event number (the interrupt source that the client
+ is interested in) as the value of the interrupts
+ property in their node
+
+Optional Properties:
+--------------------
+The following properties are _required_ only for some SoCs. If none of the below
+properties are defined, it implies that all the PRUSS INTC output interrupts 2
+through 9 (host_intr0 through host_intr7) are connected exclusively to the
+Arm interrupt controller.
+
+- ti,irqs-reserved : an array of 8-bit elements of host interrupts between
+ 0 and 7 (corresponding to PRUSS INTC output interrupts
+ 2 through 9) that are not connected to the Arm
+ interrupt controller.
+ Eg: AM437x and 66AK2G SoCs do not have "host_intr5"
+ interrupt connected to MPU
+- ti,irqs-shared : an array of 8-bit elements of host interrupts between
+ 0 and 7 (corresponding to PRUSS INTC output interrupts
+ 2 through 9) that are also connected to other devices
+ or processors in the SoC.
+ Eg: AM65x and J721E SoCs have "host_intr5",
+ "host_intr6" and "host_intr7" interrupts
+ connected to MPU, and other ICSSG instances
+
+
+Example:
+--------
+
+1. /* AM33xx PRU-ICSS */
+ pruss: pruss@0 {
+ compatible = "ti,am3356-pruss";
+ reg = <0x0 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ...
+
+ pruss_intc: interrupt-controller@20000 {
+ compatible = "ti,pruss-intc";
+ reg = <0x20000 0x2000>;
+ interrupts = <20 21 22 23 24 25 26 27>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4", "host_intr5",
+ "host_intr6", "host_intr7";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,irqs-shared = /bits/ 8 <0 6 7>;
+ };
+ };
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 3/6] irqchip/irq-pruss-intc: Add support for shared and invalid interrupts
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
The PRUSS INTC has a fixed number of output interrupt lines that are
connected to a number of processors or other PRUSS instances or other
devices (like DMA) on the SoC. The output interrupt lines 2 through 9
are usually connected to the main Arm host processor and are referred
to as host interrupts 0 through 7 from ARM/MPU perspective.
All of these 8 host interrupts are not always exclusively connected
to the Arm interrupt controller. Some SoCs have some interrupt lines
not connected to the Arm interrupt controller at all, while a few others
have the interrupt lines connected to multiple processors in which they
need to be partitioned as per SoC integration needs. For example, AM437x
and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5
connected to the other PRUSS, while AM335x has host interrupt 0 shared
between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and
a DMA controller.
Add support to the PRUSS INTC driver to allow both these shared and
invalid interrupts by not returning a failure if any of these interrupts
are skipped from the corresponding INTC DT node.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
- Fixed a typo in error message trace for ti,irqs-shared
- Updated patch description to use generic "interrupt controller" instead
of GIC
- Revised the kerneldoc comment for invalid_intr
v1: https://patchwork.kernel.org/patch/11034559/
drivers/irqchip/irq-pruss-intc.c | 44 +++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 4a9456544fd0..3a1b8a93cfad 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -67,6 +67,8 @@
* @irqchip: irq chip for this interrupt controller
* @domain: irq domain for this interrupt controller
* @lock: mutex to serialize access to INTC
+ * @shared_intr: bit-map denoting if the MPU host interrupt is shared
+ * @invalid_intr: bit-map denoting if host interrupt is not connected to MPU
*/
struct pruss_intc {
unsigned int irqs[MAX_NUM_HOST_IRQS];
@@ -74,6 +76,8 @@ struct pruss_intc {
struct irq_chip *irqchip;
struct irq_domain *domain;
struct mutex lock; /* PRUSS INTC lock */
+ u16 shared_intr;
+ u16 invalid_intr;
};
static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
@@ -233,7 +237,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
struct pruss_intc *intc;
struct resource *res;
struct irq_chip *irqchip;
- int i, irq;
+ int i, irq, count;
+ u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
if (!intc)
@@ -250,6 +255,39 @@ static int pruss_intc_probe(struct platform_device *pdev)
dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
(size_t)resource_size(res), intc->base);
+ count = of_property_read_variable_u8_array(dev->of_node,
+ "ti,irqs-reserved",
+ temp_intr, 0,
+ MAX_NUM_HOST_IRQS);
+ if (count < 0 && count != -EINVAL)
+ return count;
+ count = (count == -EINVAL ? 0 : count);
+ for (i = 0; i < count; i++) {
+ if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+ intc->invalid_intr |= BIT(temp_intr[i]);
+ } else {
+ dev_warn(dev, "ignoring invalid reserved irq %d\n",
+ temp_intr[i]);
+ }
+ temp_intr[i] = 0;
+ }
+
+ count = of_property_read_variable_u8_array(dev->of_node,
+ "ti,irqs-shared",
+ temp_intr, 0,
+ MAX_NUM_HOST_IRQS);
+ if (count < 0 && count != -EINVAL)
+ return count;
+ count = (count == -EINVAL ? 0 : count);
+ for (i = 0; i < count; i++) {
+ if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+ intc->shared_intr |= BIT(temp_intr[i]);
+ } else {
+ dev_warn(dev, "ignoring invalid shared irq %d\n",
+ temp_intr[i]);
+ }
+ }
+
mutex_init(&intc->lock);
pruss_intc_init(intc);
@@ -275,6 +313,10 @@ static int pruss_intc_probe(struct platform_device *pdev)
for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
irq = platform_get_irq_byname(pdev, irq_names[i]);
if (irq < 0) {
+ if (intc->shared_intr & BIT(i) ||
+ intc->invalid_intr & BIT(i))
+ continue;
+
dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
irq_names[i], irq);
goto fail_irq;
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
In-Reply-To: <20190731224149.11153-1-s-anna@ti.com>
The PRUSS INTC receives a number of system input interrupt source events
and supports individual control configuration and hardware prioritization.
These input events can be mapped to some output interrupt lines through 2
levels of many-to-one mapping i.e. events to channel mapping and channels
to output interrupts.
This mapping information is provided through the PRU firmware that is
loaded onto a PRU core/s or through the device tree node of the PRU
application. The mapping is configured by the PRU remoteproc driver, and
is setup before the PRU core is started and cleaned up after the PRU core
is stopped. This event mapping configuration logic programs the Channel
Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) only when a
new program is being loaded/started and the same events and interrupt
channels are reset to zero when stopping a PRU.
Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure()
that the PRU remoteproc driver can use to configure the PRUSS INTC.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
v2:
- Added new internal helper functions pruss_intc_update_cmr/hmr for
programming CMR and HMR registers
- Added unroll logic on failures in pruss_intc_configure() using the
refactored functions
- Updated unconfigure logic to reset the map registers and updated
patch description accordingly
- Renamed the FREE macro to PRU_INTC_FREE and moved it to header file
v1: https://patchwork.kernel.org/patch/11034563/
drivers/irqchip/irq-pruss-intc.c | 286 ++++++++++++++++++++++++-
include/linux/irqchip/irq-pruss-intc.h | 36 ++++
2 files changed, 320 insertions(+), 2 deletions(-)
create mode 100644 include/linux/irqchip/irq-pruss-intc.h
diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c
index 3a1b8a93cfad..63cfc665be1e 100644
--- a/drivers/irqchip/irq-pruss-intc.c
+++ b/drivers/irqchip/irq-pruss-intc.c
@@ -9,6 +9,7 @@
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
+#include <linux/irqchip/irq-pruss-intc.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of_device.h>
@@ -24,8 +25,8 @@
/* minimum starting host interrupt number for MPU */
#define MIN_PRU_HOST_INT 2
-/* maximum number of system events */
-#define MAX_PRU_SYS_EVENTS 64
+/* maximum number of host interrupts */
+#define MAX_PRU_HOST_INT 10
/* PRU_ICSS_INTC registers */
#define PRU_INTC_REVID 0x0000
@@ -57,6 +58,16 @@
#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
#define PRU_INTC_HIER 0x1500
+/* CMR register bit-field macros */
+#define CMR_EVT_MAP_MASK 0xf
+#define CMR_EVT_MAP_BITS 8
+#define CMR_EVT_PER_REG 4
+
+/* HMR register bit-field macros */
+#define HMR_CH_MAP_MASK 0xf
+#define HMR_CH_MAP_BITS 8
+#define HMR_CH_PER_REG 4
+
/* HIPIR register bit-fields */
#define INTC_HIPIR_NONE_HINT 0x80000000
@@ -66,7 +77,9 @@
* @base: base virtual address of INTC register space
* @irqchip: irq chip for this interrupt controller
* @domain: irq domain for this interrupt controller
+ * @config_map: stored INTC configuration mapping data
* @lock: mutex to serialize access to INTC
+ * @host_mask: indicate which HOST IRQs are enabled
* @shared_intr: bit-map denoting if the MPU host interrupt is shared
* @invalid_intr: bit-map denoting if host interrupt is not connected to MPU
*/
@@ -75,7 +88,9 @@ struct pruss_intc {
void __iomem *base;
struct irq_chip *irqchip;
struct irq_domain *domain;
+ struct pruss_intc_config config_map;
struct mutex lock; /* PRUSS INTC lock */
+ u32 host_mask;
u16 shared_intr;
u16 invalid_intr;
};
@@ -105,6 +120,267 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg,
return 0;
}
+static void pruss_intc_update_cmr(struct pruss_intc *intc, int evt, s8 ch)
+{
+ u32 idx, val;
+
+ idx = evt / CMR_EVT_PER_REG;
+ val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
+ val &= ~(CMR_EVT_MAP_MASK <<
+ ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS));
+ val |= ch << ((evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
+ pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
+}
+
+static void pruss_intc_update_hmr(struct pruss_intc *intc, int ch, s8 host)
+{
+ u32 idx, val;
+
+ idx = ch / HMR_CH_PER_REG;
+ val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
+ val &= ~(HMR_CH_MAP_MASK <<
+ ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS));
+ val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
+ pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
+}
+
+static struct pruss_intc *to_pruss_intc(struct device *pru_dev)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+ struct device *pruss_dev = pru_dev->parent;
+ struct pruss_intc *intc = ERR_PTR(-ENODEV);
+
+ np = of_get_child_by_name(pruss_dev->of_node, "interrupt-controller");
+ if (!np) {
+ dev_err(pruss_dev, "pruss does not have an interrupt-controller node\n");
+ return intc;
+ }
+
+ pdev = of_find_device_by_node(np);
+ if (!pdev) {
+ dev_err(pruss_dev, "no associated platform device\n");
+ goto out;
+ }
+
+ intc = platform_get_drvdata(pdev);
+ if (!intc) {
+ dev_err(pruss_dev, "pruss intc device probe failed?\n");
+ intc = ERR_PTR(-EINVAL);
+ }
+
+out:
+ of_node_put(np);
+ return intc;
+}
+
+/**
+ * pruss_intc_configure() - configure the PRUSS INTC
+ * @dev: pru device pointer
+ * @intc_config: PRU core-specific INTC configuration
+ *
+ * Configures the PRUSS INTC with the provided configuration from
+ * a PRU core. Any existing event to channel mappings or channel to
+ * host interrupt mappings are checked to make sure there are no
+ * conflicting configuration between both the PRU cores. The function
+ * is intended to be used only by the PRU remoteproc driver.
+ *
+ * Returns 0 on success, or a suitable error code otherwise
+ */
+int pruss_intc_configure(struct device *dev,
+ struct pruss_intc_config *intc_config)
+{
+ struct pruss_intc *intc;
+ int i, idx, ret;
+ s8 ch, host;
+ u64 sysevt_mask = 0;
+ u32 ch_mask = 0;
+ u32 host_mask = 0;
+
+ intc = to_pruss_intc(dev);
+ if (IS_ERR(intc))
+ return PTR_ERR(intc);
+
+ mutex_lock(&intc->lock);
+
+ /*
+ * configure channel map registers - each register holds map info
+ * for 4 events, with each event occupying the lower nibble in
+ * a register byte address in little-endian fashion
+ */
+ for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+ ch = intc_config->sysev_to_ch[i];
+ if (ch < 0)
+ continue;
+
+ /* check if sysevent already assigned */
+ if (intc->config_map.sysev_to_ch[i] != PRU_INTC_FREE) {
+ dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n",
+ i, ch, intc->config_map.sysev_to_ch[i]);
+ ret = -EEXIST;
+ goto fail_evt;
+ }
+
+ intc->config_map.sysev_to_ch[i] = ch;
+ pruss_intc_update_cmr(intc, i, ch);
+ sysevt_mask |= BIT_ULL(i);
+ ch_mask |= BIT(ch);
+ idx = i / CMR_EVT_PER_REG;
+
+ dev_dbg(dev, "SYSEVT%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx,
+ pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
+ }
+
+ /*
+ * set host map registers - each register holds map info for
+ * 4 channels, with each channel occupying the lower nibble in
+ * a register byte address in little-endian fashion
+ */
+ for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+ host = intc_config->ch_to_host[i];
+ if (host < 0)
+ continue;
+
+ /* check if channel already assigned */
+ if (intc->config_map.ch_to_host[i] != PRU_INTC_FREE) {
+ dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n",
+ i, host, intc->config_map.ch_to_host[i]);
+ ret = -EEXIST;
+ goto fail_ch;
+ }
+
+ /* check if host intr is already in use by other PRU */
+ if (intc->host_mask & (1U << host)) {
+ dev_err(dev, "%s: host intr %d already in use\n",
+ __func__, host);
+ ret = -EEXIST;
+ goto fail_ch;
+ }
+
+ intc->config_map.ch_to_host[i] = host;
+ pruss_intc_update_hmr(intc, i, host);
+ ch_mask |= BIT(i);
+ host_mask |= BIT(host);
+ idx = i / HMR_CH_PER_REG;
+
+ dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", i, host, idx,
+ pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
+ }
+
+ dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n",
+ sysevt_mask, ch_mask, host_mask);
+
+ /* enable system events, writing 0 has no-effect */
+ pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask));
+ pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
+ pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask));
+ pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+
+ /* enable host interrupts */
+ for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+ if (host_mask & BIT(i))
+ pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i);
+ }
+
+ /* global interrupt enable */
+ pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
+
+ intc->host_mask |= host_mask;
+
+ mutex_unlock(&intc->lock);
+ return 0;
+
+fail_ch:
+ while (--i >= 0) {
+ if (intc_config->ch_to_host[i] >= 0) {
+ intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+ pruss_intc_update_hmr(intc, i, 0);
+ }
+ }
+ i = ARRAY_SIZE(intc_config->sysev_to_ch);
+fail_evt:
+ while (--i >= 0) {
+ if (intc_config->sysev_to_ch[i] >= 0) {
+ intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+ pruss_intc_update_cmr(intc, i, 0);
+ }
+ }
+ mutex_unlock(&intc->lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pruss_intc_configure);
+
+/**
+ * pruss_intc_unconfigure() - unconfigure the PRUSS INTC
+ * @dev: pru device pointer
+ * @intc_config: PRU core specific INTC configuration
+ *
+ * Undo whatever was done in pruss_intc_configure() for a PRU core.
+ * It should be sufficient to just mark the resources free in the
+ * global map and disable the host interrupts and sysevents.
+ */
+int pruss_intc_unconfigure(struct device *dev,
+ struct pruss_intc_config *intc_config)
+{
+ struct pruss_intc *intc;
+ int i;
+ s8 ch, host;
+ u64 sysevt_mask = 0;
+ u32 host_mask = 0;
+
+ intc = to_pruss_intc(dev);
+ if (IS_ERR(intc))
+ return PTR_ERR(intc);
+
+ mutex_lock(&intc->lock);
+
+ for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) {
+ ch = intc_config->sysev_to_ch[i];
+ if (ch < 0)
+ continue;
+
+ /* mark sysevent free in global map */
+ intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+ sysevt_mask |= BIT_ULL(i);
+ /* clear the map using reset value 0 */
+ pruss_intc_update_cmr(intc, i, 0);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) {
+ host = intc_config->ch_to_host[i];
+ if (host < 0)
+ continue;
+
+ /* mark channel free in global map */
+ intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+ host_mask |= BIT(host);
+ /* clear the map using reset value 0 */
+ pruss_intc_update_hmr(intc, i, 0);
+ }
+
+ dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n",
+ sysevt_mask, host_mask);
+
+ /* disable system events, writing 0 has no-effect */
+ pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask));
+ pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask));
+ /* clear any pending status */
+ pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask));
+ pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask));
+
+ /* disable host interrupts */
+ for (i = 0; i < MAX_PRU_HOST_INT; i++) {
+ if (host_mask & BIT(i))
+ pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i);
+ }
+
+ intc->host_mask &= ~host_mask;
+ mutex_unlock(&intc->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pruss_intc_unconfigure);
+
static void pruss_intc_init(struct pruss_intc *intc)
{
int i;
@@ -290,6 +566,12 @@ static int pruss_intc_probe(struct platform_device *pdev)
mutex_init(&intc->lock);
+ for (i = 0; i < ARRAY_SIZE(intc->config_map.sysev_to_ch); i++)
+ intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE;
+
+ for (i = 0; i < ARRAY_SIZE(intc->config_map.ch_to_host); i++)
+ intc->config_map.ch_to_host[i] = PRU_INTC_FREE;
+
pruss_intc_init(intc);
irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h
new file mode 100644
index 000000000000..daffc048b303
--- /dev/null
+++ b/include/linux/irqchip/irq-pruss-intc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PRU-ICSS sub-system private interfaces
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Suman Anna <s-anna@ti.com>
+ */
+
+#ifndef __LINUX_IRQ_PRUSS_INTC_H
+#define __LINUX_IRQ_PRUSS_INTC_H
+
+/* maximum number of system events */
+#define MAX_PRU_SYS_EVENTS 64
+
+/* maximum number of interrupt channels */
+#define MAX_PRU_CHANNELS 10
+
+/* use -1 to mark unassigned events and channels */
+#define PRU_INTC_FREE -1
+
+/**
+ * struct pruss_intc_config - INTC configuration info
+ * @sysev_to_ch: system events to channel mapping information
+ * @ch_to_host: interrupt channel to host interrupt information
+ */
+struct pruss_intc_config {
+ s8 sysev_to_ch[MAX_PRU_SYS_EVENTS];
+ s8 ch_to_host[MAX_PRU_CHANNELS];
+};
+
+int pruss_intc_configure(struct device *dev,
+ struct pruss_intc_config *intc_config);
+int pruss_intc_unconfigure(struct device *dev,
+ struct pruss_intc_config *intc_config);
+
+#endif /* __LINUX_IRQ_PRUSS_INTC_H */
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 0/6] Add TI PRUSS Local Interrupt Controller IRQChip driver
From: Suman Anna @ 2019-07-31 22:41 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, David Lechner, Tony Lindgren,
Sekhar Nori, linux-kernel, Andrew F. Davis, Lokesh Vutla,
Rob Herring, Murali Karicheri, linux-omap, linux-arm-kernel,
Roger Quadros
Hi All,
The following is a v2 version of the series [1] that adds an IRQChip driver for
the local interrupt controller present within a Programmable Real-Time Unit and
Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs
including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2
architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs
and the latest K3 architecture based AM65x and J721E SoCs. Please see the
v1 cover-letter [1] for details about the features of this interrupt controller.
More details can be found in any of the supported SoC TRMs.
Eg: Chapter 30.1.6 of AM5728 TRM [2]
Please see the individual patches for exact changes in each patch, following are
the main changes from v1:
- Dropped the pruss_intc_trigger() API and patch and replaced it with a new
patch achieving the same through irq_set_irqchip_state() callback (patch 5)
- Added cleanup logic on INTC mapping fails and reset the mapping registers
during unmap (patch 4)
- Minor revisions to the bindings, no new properties introduced (patch 1)
regards
Suman
[1] https://patchwork.kernel.org/cover/11034561/
[2] http://www.ti.com/lit/pdf/spruhz6
Andrew F. Davis (1):
irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS
interrupts
David Lechner (1):
irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops
Suman Anna (4):
dt-bindings: irqchip: Add PRUSS interrupt controller bindings
irqchip/irq-pruss-intc: Add support for shared and invalid interrupts
irqchip/irq-pruss-intc: Add helper functions to configure internal
mapping
irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs
.../interrupt-controller/ti,pruss-intc.txt | 98 +++
drivers/irqchip/Kconfig | 10 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-pruss-intc.c | 764 ++++++++++++++++++
include/linux/irqchip/irq-pruss-intc.h | 36 +
5 files changed, 909 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt
create mode 100644 drivers/irqchip/irq-pruss-intc.c
create mode 100644 include/linux/irqchip/irq-pruss-intc.h
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v5 14/14] riscv: Make mmap allocation top-down by default
From: Paul Walmsley @ 2019-07-31 22:40 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Albert Ou, Kees Cook, Catalin Marinas, Palmer Dabbelt,
Will Deacon, Russell King, Ralf Baechle, linux-kernel, linux-mm,
Luis Chamberlain, Paul Burton, James Hogan, linux-fsdevel,
Andrew Morton, linux-mips, Christoph Hellwig, linux-riscv,
linux-arm-kernel, Alexander Viro
In-Reply-To: <20190730055113.23635-15-alex@ghiti.fr>
On Tue, 30 Jul 2019, Alexandre Ghiti wrote:
> In order to avoid wasting user address space by using bottom-up mmap
> allocation scheme, prefer top-down scheme when possible.
>
> Before:
> root@qemuriscv64:~# cat /proc/self/maps
> 00010000-00016000 r-xp 00000000 fe:00 6389 /bin/cat.coreutils
> 00016000-00017000 r--p 00005000 fe:00 6389 /bin/cat.coreutils
> 00017000-00018000 rw-p 00006000 fe:00 6389 /bin/cat.coreutils
> 00018000-00039000 rw-p 00000000 00:00 0 [heap]
> 1555556000-155556d000 r-xp 00000000 fe:00 7193 /lib/ld-2.28.so
> 155556d000-155556e000 r--p 00016000 fe:00 7193 /lib/ld-2.28.so
> 155556e000-155556f000 rw-p 00017000 fe:00 7193 /lib/ld-2.28.so
> 155556f000-1555570000 rw-p 00000000 00:00 0
> 1555570000-1555572000 r-xp 00000000 00:00 0 [vdso]
> 1555574000-1555576000 rw-p 00000000 00:00 0
> 1555576000-1555674000 r-xp 00000000 fe:00 7187 /lib/libc-2.28.so
> 1555674000-1555678000 r--p 000fd000 fe:00 7187 /lib/libc-2.28.so
> 1555678000-155567a000 rw-p 00101000 fe:00 7187 /lib/libc-2.28.so
> 155567a000-15556a0000 rw-p 00000000 00:00 0
> 3fffb90000-3fffbb1000 rw-p 00000000 00:00 0 [stack]
>
> After:
> root@qemuriscv64:~# cat /proc/self/maps
> 00010000-00016000 r-xp 00000000 fe:00 6389 /bin/cat.coreutils
> 00016000-00017000 r--p 00005000 fe:00 6389 /bin/cat.coreutils
> 00017000-00018000 rw-p 00006000 fe:00 6389 /bin/cat.coreutils
> 2de81000-2dea2000 rw-p 00000000 00:00 0 [heap]
> 3ff7eb6000-3ff7ed8000 rw-p 00000000 00:00 0
> 3ff7ed8000-3ff7fd6000 r-xp 00000000 fe:00 7187 /lib/libc-2.28.so
> 3ff7fd6000-3ff7fda000 r--p 000fd000 fe:00 7187 /lib/libc-2.28.so
> 3ff7fda000-3ff7fdc000 rw-p 00101000 fe:00 7187 /lib/libc-2.28.so
> 3ff7fdc000-3ff7fe2000 rw-p 00000000 00:00 0
> 3ff7fe4000-3ff7fe6000 r-xp 00000000 00:00 0 [vdso]
> 3ff7fe6000-3ff7ffd000 r-xp 00000000 fe:00 7193 /lib/ld-2.28.so
> 3ff7ffd000-3ff7ffe000 r--p 00016000 fe:00 7193 /lib/ld-2.28.so
> 3ff7ffe000-3ff7fff000 rw-p 00017000 fe:00 7193 /lib/ld-2.28.so
> 3ff7fff000-3ff8000000 rw-p 00000000 00:00 0
> 3fff888000-3fff8a9000 rw-p 00000000 00:00 0 [stack]
>
> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
> Reviewed-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Kees Cook <keescook@chromium.org>
> Reviewed-by: Luis Chamberlain <mcgrof@kernel.org>
Acked-by: Paul Walmsley <paul.walmsley@sifive.com> # for arch/riscv
As Alex notes, this patch depends on "[PATCH] riscv: kbuild: add virtual
memory system selection":
https://lore.kernel.org/linux-riscv/alpine.DEB.2.21.9999.1907301218560.3486@viisi.sifive.com/T/#t
which will likely go up during v5.3-rc.
- Paul
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: next/master boot: 265 boots: 17 failed, 184 passed with 64 offline (next-20190730)
From: Linus Walleij @ 2019-07-31 22:40 UTC (permalink / raw)
To: Stephen Boyd
Cc: Kernel Build Reports Mailman List, Timur Tabi, Lina Iyer,
Bjorn Andersson, Mark Brown, Lee Jones, Linux ARM
In-Reply-To: <5d41b01a.1c69fb81.84578.a0bc@mx.google.com>
On Wed, Jul 31, 2019 at 5:13 PM Stephen Boyd <swboyd@chromium.org> wrote:
> - if (IS_ENABLED(CONFIG_OF_GPIO))
> - gc->need_valid_mask = of_gpio_need_valid_mask(gc);
> + if (of_gpio_need_valid_mask(gc))
> + gc->need_valid_mask = true;
This looks like the silver bullet, thanks for your sharp eyes for this!
I'll send this out with your authorship and apply to next so Mark can see
if it fixes the issue.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ASoC: zx-tdm: remove redundant assignment to ts_width on error return path
From: Colin King @ 2019-07-31 22:32 UTC (permalink / raw)
To: Jun Nie, Shawn Guo, Liam Girdwood, Mark Brown, Jaroslav Kysela,
Takashi Iwai, linux-arm-kernel, alsa-devel
Cc: kernel-janitors, linux-kernel
From: Colin Ian King <colin.king@canonical.com>
The value assigned to ts_width is never read on the error return path
so the assignment is redundant and can be removed. Remove it.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
sound/soc/zte/zx-tdm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/zte/zx-tdm.c b/sound/soc/zte/zx-tdm.c
index 5e877fe9ba7b..0e5a05b25a77 100644
--- a/sound/soc/zte/zx-tdm.c
+++ b/sound/soc/zte/zx-tdm.c
@@ -211,7 +211,6 @@ static int zx_tdm_hw_params(struct snd_pcm_substream *substream,
ts_width = 1;
break;
default:
- ts_width = 0;
dev_err(socdai->dev, "Unknown data format\n");
return -EINVAL;
}
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2] ARM: kirkwood: ts219: disable the SoC's RTC
From: Uwe Kleine-König @ 2019-07-31 22:32 UTC (permalink / raw)
To: Jason Cooper, Gregory Clement, Sebastian Hesselbarth
Cc: Andrew Lunn, Alexandre Belloni, tbm, linux-arm-kernel,
Oliver Hartkopp
[-- Attachment #1.1: Type: text/plain, Size: 1103 bytes --]
The internal RTC doesn't work, loading the driver only yields
rtc-mv f1010300.rtc: internal RTC not ticking
. So disable it.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
---
Hello,
This patch is (one) result of a discussion on the rtc list. v1 was sent
there only. This v2 is just a resend to the mvebu maintainers.
Alexandre Belloni said to v1: Seems good to me then.
This sounds a bit like an ack, but I didn't add it as it was not
explicit.
Best regards
Uwe
arch/arm/boot/dts/kirkwood-ts219.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index a88eb22070a1..994cabcf4b51 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -104,3 +104,11 @@
&pcie0 {
status = "okay";
};
+
+&rtc {
+ /*
+ * There is a s35390a available on the i2c bus, the internal rtc isn't
+ * working (probably no crystal assembled).
+ */
+ status = "disabled";
+};
--
2.20.1
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH] ARM: at91/dt: pinctrl: add helper define for MULTI_DRIVE + PULL_UP
From: Uwe Kleine-König @ 2019-07-31 22:24 UTC (permalink / raw)
To: Nicolas Ferre, Alexandre Belloni, Ludovic Desroches; +Cc: linux-arm-kernel
In-Reply-To: <20190731221448.tnxrrwny2jpe7iop@pengutronix.de>
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
---
On Thu, Aug 01, 2019 at 12:14:48AM +0200, Uwe Kleine-König wrote:
> The define I added in include/dt-bindings/pinctrl/at91.h would be nice
> to have though to simplify overriding the SoC's default pinctrl. Would
> it be OK to add this?
something like this ...
The name is a bit inconsistent compared to
AT91_PINCTRL_PULL_UP_DEGLITCH, but on the pro side it is shorter.
Assuming you like this, what is your naming preference?
Best regards
Uwe
include/dt-bindings/pinctrl/at91.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index 3831f91fb3ba..b8bb55a935f6 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -21,6 +21,7 @@
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+#define AT91_PINCTRL_MULTI_DRIVE_PU (AT91_PINCTRL_MULTI_DRIVE | AT91_PINCTRL_PULL_UP)
#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH] ARM: at91sam9x5/dt: enable internal pull-up for i2c-gpio lines
From: Uwe Kleine-König @ 2019-07-31 22:14 UTC (permalink / raw)
To: Nicolas Ferre, Alexandre Belloni, linux-arm-kernel
In-Reply-To: <20190731111828.oc7ysaq3pznnshds@M43218.corp.atmel.com>
hello Ludovic,
On Wed, Jul 31, 2019 at 01:18:28PM +0200, Ludovic Desroches wrote:
> On Mon, Jul 29, 2019 at 06:00:22PM +0200, Uwe Kleine-König wrote:
> > External E-Mail
> >
> >
> > This is what I need on my Arietta G25 to be able to just connect an i2c
> > device to the pin headers.
> > Also remove the comment that doesn't tell more than the pin declaration.
> >
> > Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
> > ---
> > Hello,
> >
> > not sure this is change suitable for the SoC dtsi. I'll leave it to the
> > at91 maintainers to decide.
>
> Usually we have pull-ups for those signals on our board. In this case,
> it's useless to activate the internal pull-up. Even if I am not sure we
> were consistent in our policy about what goes in the SoC dtsi and what
> goes in the dts board, I would prefer to have this at the board level.
OK.
The define I added in include/dt-bindings/pinctrl/at91.h would be nice
to have though to simplify overriding the SoC's default pinctrl. Would
it be OK to add this? (I kept the diff below.) Obviously there isn't a
mainline user (yet) because it's a custom modification of my Arietta
board that it has an i2c device (and it depends on the modification that
I need the internal pull up).
Best regards
Uwe
> > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
> > index 3831f91fb3ba..c72d40f50acd 100644
> > --- a/include/dt-bindings/pinctrl/at91.h
> > +++ b/include/dt-bindings/pinctrl/at91.h
> > @@ -20,6 +20,8 @@
> > #define AT91_PINCTRL_DEBOUNCE (1 << 16)
> > #define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
> >
> > +#define AT91_PINCTRL_MULTI_DRIVE_PU (AT91_PINCTRL_MULTI_DRIVE | AT91_PINCTRL_PULL_UP)
> > +
> > #define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
> >
> > #define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] at91/dt: ariettag25: style cleanup
From: Uwe Kleine-König @ 2019-07-31 22:00 UTC (permalink / raw)
To: Nicolas Ferre, Alexandre Belloni, Ludovic Desroches
Cc: Mark Rutland, devicetree, Rob Herring, linux-arm-kernel
- newline between properties and sub-nodes
- use tags from included dtsi instead of duplicating the hierarchy
- status should be the last property
- drop duplicated alias
There are no differences in the generated .dtb
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
---
Hello,
these are the style rules I was teached when modifying imx dts files.
Do they apply to at91, too?
Best regards
Uwe
arch/arm/boot/dts/at91-ariettag25.dts | 87 +++++++++++++--------------
1 file changed, 43 insertions(+), 44 deletions(-)
diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts
index 7a34c4dc05d2..8f9f5a22cbf6 100644
--- a/arch/arm/boot/dts/at91-ariettag25.dts
+++ b/arch/arm/boot/dts/at91-ariettag25.dts
@@ -6,14 +6,11 @@
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
+
/ {
model = "Acme Systems Arietta G25";
compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9";
- aliases {
- serial0 = &dbgu;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
@@ -34,55 +31,16 @@
ahb {
apb {
- mmc0: mmc@f0008000 {
- pinctrl-0 = <
- &pinctrl_mmc0_slot0_clk_cmd_dat0
- &pinctrl_mmc0_slot0_dat1_3>;
- status = "okay";
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- };
- };
-
- tcb0: timer@f8008000 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>;
- };
-
- timer@1 {
- compatible = "atmel,tcb-timer";
- reg = <1>;
- };
- };
-
- usb2: gadget@f803c000 {
- status = "okay";
- };
-
- dbgu: serial@fffff200 {
- status = "okay";
- };
-
rtc@fffffeb0 {
status = "okay";
};
};
- usb0: ohci@600000 {
- status = "okay";
- num-ports = <3>;
- };
-
- usb1: ehci@700000 {
- status = "okay";
- };
};
leds {
compatible = "gpio-leds";
+
arietta_led {
label = "arietta_led";
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
@@ -90,3 +48,44 @@
};
};
};
+
+&dbgu {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-0 = <
+ &pinctrl_mmc0_slot0_clk_cmd_dat0
+ &pinctrl_mmc0_slot0_dat1_3>;
+ status = "okay";
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ };
+};
+
+&tcb0 {
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&usb0 {
+ num-ports = <3>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 0/6] ReST conversion patches not applied yet
From: Mark Brown @ 2019-07-31 21:55 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Mark Rutland, Dave Kleikamp, alsa-devel, Linux Doc Mailing List,
Maxime Ripard, jfs-discussion, linux-kernel,
Peter Meerwald-Stadler, Evgeniy Polyakov, linux-cifs,
Lars-Peter Clausen, Jonathan Corbet, Alexander Shishkin,
Chen-Yu Tsai, devicetree, Evgeniy Dushistov, Suzuki K Poulose,
Mauro Carvalho Chehab, Rob Herring, linux-arm-kernel,
Mathieu Poirier, samba-technical, Liam Girdwood, linux-iio,
linux-spi, Steve French, Hartmut Knaack, Jonathan Cameron
In-Reply-To: <20190731182729.01c98cd3@coco.lan>
[-- Attachment #1.1: Type: text/plain, Size: 725 bytes --]
On Wed, Jul 31, 2019 at 06:27:29PM -0300, Mauro Carvalho Chehab wrote:
> Meanwhile, if someone needs something that it is at the wrong book, he
> can just use some search tool to seek what he needs, no matter on
> what book the relevant information is stored.
OTOH it might be weird for the intended audience of the book.
> Mark Brown <broonie@kernel.org> escreveu:
> > I don't know if it makes sense to have an embedded developer's
> > manual as well?
> Yeah, that's a good question.
> Jon is planning todo a documentation track at LPC. One of the things
> that should be discussed, IMO, is how we'll organize the books.
I'll be at Plumbers, not sure what the schedule's looking like yet
though.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 1/2] dts: add vendor prefix "acme" for "Acme Systems srl"
From: Uwe Kleine-König @ 2019-07-31 21:48 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Nicolas Ferre, Alexandre Belloni,
linux-arm-kernel, devicetree, info
In-Reply-To: <20190731113419.bz4qygnmnlf57yeo@M43218.corp.atmel.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 475 bytes --]
On 7/31/19 1:34 PM, Ludovic Desroches wrote:
> On Sun, Jul 28, 2019 at 11:04:02PM +0200, Uwe Kleine-König wrote:
>>
>> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
>
> As I can confirm it's not an April fool!
> Reviwed-by: Ludovic Desroches <ludovic.desroches@microchip.com>
s/Reviwed/Reviewed/
Not sure who will pick this up and which automatisms are used. This
might need manual fixup or attention to be picked up at all.
Best regards
Uwe
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 0/6] ReST conversion patches not applied yet
From: Mauro Carvalho Chehab @ 2019-07-31 21:27 UTC (permalink / raw)
To: Mark Brown
Cc: Mark Rutland, Dave Kleikamp, alsa-devel, Linux Doc Mailing List,
Maxime Ripard, jfs-discussion, linux-kernel,
Peter Meerwald-Stadler, Evgeniy Polyakov, linux-cifs,
Lars-Peter Clausen, Jonathan Corbet, Alexander Shishkin,
Chen-Yu Tsai, devicetree, Evgeniy Dushistov, Suzuki K Poulose,
Mauro Carvalho Chehab, Rob Herring, linux-arm-kernel,
Mathieu Poirier, samba-technical, Liam Girdwood, linux-iio,
linux-spi, Steve French, Hartmut Knaack, Jonathan Cameron
In-Reply-To: <20190731203712.GJ4369@sirena.org.uk>
Em Wed, 31 Jul 2019 21:37:12 +0100
Mark Brown <broonie@kernel.org> escreveu:
> On Wed, Jul 31, 2019 at 05:26:13PM -0300, Mauro Carvalho Chehab wrote:
> > Mark Brown <broonie@kernel.org> escreveu:
>
> > > There were outstanding questions about where it was going to get moved
> > > to but if I read the diff correctly it looks like it didn't actually get
> > > moved in the end?
>
> > Yeah, it doesn't have the move. My understanding from our discussions
> > is that we didn't reach a conclusion.
>
> Yes, that was my understanding too which was why I was surprised to see
> this going in. This is OK then, I'd have acked it.
>
> > In any case, I can send a separate patch with the move part once
> > we reach an agreement about what's the best way to proceed (or you
> > can do it directly, if you prefer so).
>
> I'm not likely to do anything without someone sending patches, I'm not
> clear on the utility of the move with the current division of the
> manuals.
Same here: I do see value on having docs focused on their audience.
Yet, I'm not so sure how worth is to break some subsystem documentation
into books, as, on some cases, this would mean huge efforts.
I'd prefer to see the big picture first, finishing the conversion and
then looking at the resulting docs.
Meanwhile, if someone needs something that it is at the wrong book, he
can just use some search tool to seek what he needs, no matter on
what book the relevant information is stored.
> I don't know if it makes sense to have an embedded developer's
> manual as well?
Yeah, that's a good question.
Jon is planning todo a documentation track at LPC. One of the things
that should be discussed, IMO, is how we'll organize the books.
I suspect that, once we finish the conversion of the remaining ~300
files to ReST, the next logical step is to check what are the gaps
and have a list of pending tasks.
Thanks,
Mauro
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] mailbox: imx: Fix Tx doorbell shutdown path
From: Daniel Baluta @ 2019-07-31 20:55 UTC (permalink / raw)
To: shawnguo, jassisinghbrar
Cc: Daniel Baluta, s.hauer, linux-kernel, o.rempel, linux-imx, kernel,
festevam, linux-arm-kernel
Tx doorbell is handled by txdb_tasklet and doesn't
have an associated IRQ.
Anyhow, imx_mu_shutdown ignores this and tries to
free an IRQ that wasn't requested for Tx DB resulting
in the following warning:
[ 1.967644] Trying to free already-free IRQ 26
[ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358
[ 1.980024] Modules linked in:
[ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G
[ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT)
[ 1.998668] Workqueue: events deferred_probe_work_func
[ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO)
[ 2.008607] pc : __free_irq+0xc0/0x358
[ 2.012364] lr : __free_irq+0xc0/0x358
[ 2.016111] sp : ffff00001179b7e0
[ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018
[ 2.024736] x27: ffff000011233000 x26: 0000000000000004
[ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4
[ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588
[ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400
[ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff
[ 2.051320] x17: 0000000000000000 x16: 0000000000000000
[ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517
[ 2.061953] x13: ffff00001179b525 x12: ffff000011142000
[ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970
[ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194
[ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09
[ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000
[ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff
[ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000
[ 2.099173] Call trace:
[ 2.101618] __free_irq+0xc0/0x358
[ 2.105021] free_irq+0x38/0x98
[ 2.108170] imx_mu_shutdown+0x90/0xb0
[ 2.111921] mbox_free_channel.part.2+0x24/0xb8
[ 2.116453] mbox_free_channel+0x18/0x28
This bug is present from the beginning of times.
Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Fixes: 2bb7005696e2246 ("mailbox: Add support for i.MX messaging unit")
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
drivers/mailbox/imx-mailbox.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 9f74dee1a58c..957c10c4e674 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -214,8 +214,10 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
- if (cp->type == IMX_MU_TYPE_TXDB)
+ if (cp->type == IMX_MU_TYPE_TXDB) {
tasklet_kill(&cp->txdb_tasklet);
+ return;
+ }
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH] arm64/mm: fix variable 'tag' set but not used
From: Qian Cai @ 2019-07-31 20:38 UTC (permalink / raw)
To: catalin.marinas, will
Cc: andreyknvl, Qian Cai, linux-kernel, linux-arm-kernel
When CONFIG_KASAN_SW_TAGS=n, set_tag() is compiled away. GCC throws a
warning,
mm/kasan/common.c: In function '__kasan_kmalloc':
mm/kasan/common.c:464:5: warning: variable 'tag' set but not used
[-Wunused-but-set-variable]
u8 tag = 0xff;
^~~
Fix it by making __tag_set() a static inline function.
Signed-off-by: Qian Cai <cai@lca.pw>
---
arch/arm64/include/asm/memory.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index b7ba75809751..9645b1340afe 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -210,7 +210,11 @@ static inline unsigned long kaslr_offset(void)
#define __tag_reset(addr) untagged_addr(addr)
#define __tag_get(addr) (__u8)((u64)(addr) >> 56)
#else
-#define __tag_set(addr, tag) (addr)
+static inline const void *__tag_set(const void *addr, u8 tag)
+{
+ return addr;
+}
+
#define __tag_reset(addr) (addr)
#define __tag_get(addr) 0
#endif
--
1.8.3.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 1/6] docs: fix a couple of new broken references
From: Dave Kleikamp @ 2019-07-31 20:36 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Linux Doc Mailing List
Cc: Mark Rutland, Dave Kleikamp, alsa-devel, Evgeniy Dushistov,
Mathieu Poirier, Jonathan Corbet, Maxime Ripard, Suzuki K Poulose,
Liam Girdwood, Rob Herring, linux-kernel, Alexander Shishkin,
Chen-Yu Tsai, Mark Brown, linux-arm-kernel, jfs-discussion,
Mauro Carvalho Chehab, devicetree
In-Reply-To: <5b4fae5978d309641fa8ba233a9efe2b48201cd6.1564603513.git.mchehab+samsung@kernel.org>
On 7/31/19 3:08 PM, Mauro Carvalho Chehab wrote:
> Those are due to recent changes. Most of the issues
> can be automatically fixed with:
>
> $ ./scripts/documentation-file-ref-check --fix
>
> The only exception was the sound binding with required
> manual work.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: > Dave Kleikamp <dave.kleikamp@oracle.com>
> ---
> Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt | 2 +-
> MAINTAINERS | 4 ++--
> drivers/hwtracing/coresight/Kconfig | 2 +-
> fs/jfs/Kconfig | 2 +-
> fs/ufs/Kconfig | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt
> index 2ca3d138528e..7ecf6bd60d27 100644
> --- a/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt
> +++ b/Documentation/devicetree/bindings/sound/sun8i-a33-codec.txt
> @@ -4,7 +4,7 @@ Allwinner SUN8I audio codec
> On Sun8i-A33 SoCs, the audio is separated in different parts:
> - A DAI driver. It uses the "sun4i-i2s" driver which is
> documented here:
> - Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> + Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
> - An analog part of the codec which is handled as PRCM registers.
> See Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
> - An digital part of the codec which is documented in this current
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6de82f019a52..f109a8bcffda 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8659,7 +8659,7 @@ L: jfs-discussion@lists.sourceforge.net
> W: http://jfs.sourceforge.net/
> T: git git://github.com/kleikamp/linux-shaggy.git
> S: Maintained
> -F: Documentation/filesystems/jfs.txt
> +F: Documentation/admin-guide/jfs.rst
> F: fs/jfs/
>
> JME NETWORK DRIVER
> @@ -16439,7 +16439,7 @@ F: drivers/hid/hid-udraw-ps3.c
> UFS FILESYSTEM
> M: Evgeniy Dushistov <dushistov@mail.ru>
> S: Maintained
> -F: Documentation/filesystems/ufs.txt
> +F: Documentation/admin-guide/ufs.rst
> F: fs/ufs/
>
> UHID USERSPACE HID IO DRIVER:
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 14638db4991d..7a9f5fb08330 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -106,7 +106,7 @@ config CORESIGHT_CPU_DEBUG
> can quickly get to know program counter (PC), secure state,
> exception level, etc. Before use debugging functionality, platform
> needs to ensure the clock domain and power domain are enabled
> - properly, please refer Documentation/trace/coresight-cpu-debug.txt
> + properly, please refer Documentation/trace/coresight-cpu-debug.rst
> for detailed description and the example for usage.
>
> endif
> diff --git a/fs/jfs/Kconfig b/fs/jfs/Kconfig
> index 22a273bd4648..05cb0e8e4382 100644
> --- a/fs/jfs/Kconfig
> +++ b/fs/jfs/Kconfig
> @@ -5,7 +5,7 @@ config JFS_FS
> select CRC32
> help
> This is a port of IBM's Journaled Filesystem . More information is
> - available in the file <file:Documentation/filesystems/jfs.txt>.
> + available in the file <file:Documentation/admin-guide/jfs.rst>.
>
> If you do not intend to use the JFS filesystem, say N.
>
> diff --git a/fs/ufs/Kconfig b/fs/ufs/Kconfig
> index fcb41516ea59..6d30adb6b890 100644
> --- a/fs/ufs/Kconfig
> +++ b/fs/ufs/Kconfig
> @@ -9,7 +9,7 @@ config UFS_FS
> this file system as well. Saying Y here will allow you to read from
> these partitions; if you also want to write to them, say Y to the
> experimental "UFS file system write support", below. Please read the
> - file <file:Documentation/filesystems/ufs.txt> for more information.
> + file <file:Documentation/admin-guide/ufs.rst> for more information.
>
> The recently released UFS2 variant (used in FreeBSD 5.x) is
> READ-ONLY supported.
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 0/6] ReST conversion patches not applied yet
From: Mark Brown @ 2019-07-31 20:37 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Mark Rutland, Dave Kleikamp, alsa-devel, Linux Doc Mailing List,
Maxime Ripard, jfs-discussion, linux-kernel,
Peter Meerwald-Stadler, Evgeniy Polyakov, linux-cifs,
Lars-Peter Clausen, Jonathan Corbet, Alexander Shishkin,
Chen-Yu Tsai, devicetree, Evgeniy Dushistov, Suzuki K Poulose,
Mauro Carvalho Chehab, Rob Herring, linux-arm-kernel,
Mathieu Poirier, samba-technical, Liam Girdwood, linux-iio,
linux-spi, Steve French, Hartmut Knaack, Jonathan Cameron
In-Reply-To: <20190731172613.32d65ad8@coco.lan>
[-- Attachment #1.1: Type: text/plain, Size: 933 bytes --]
On Wed, Jul 31, 2019 at 05:26:13PM -0300, Mauro Carvalho Chehab wrote:
> Mark Brown <broonie@kernel.org> escreveu:
> > There were outstanding questions about where it was going to get moved
> > to but if I read the diff correctly it looks like it didn't actually get
> > moved in the end?
> Yeah, it doesn't have the move. My understanding from our discussions
> is that we didn't reach a conclusion.
Yes, that was my understanding too which was why I was surprised to see
this going in. This is OK then, I'd have acked it.
> In any case, I can send a separate patch with the move part once
> we reach an agreement about what's the best way to proceed (or you
> can do it directly, if you prefer so).
I'm not likely to do anything without someone sending patches, I'm not
clear on the utility of the move with the current division of the
manuals. I don't know if it makes sense to have an embedded developer's
manual as well?
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 484 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 03/14] watchdog: pnx4008_wdt: allow compile-testing
From: Guenter Roeck @ 2019-07-31 20:36 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Andrew Lunn, LINUXWATCHDOG, Linux Kernel Mailing List,
Jason Cooper, David S. Miller, Greg Kroah-Hartman,
Gregory Clement, USB list, Russell King, Vladimir Zapolskiy,
open list:GPIO SUBSYSTEM, soc, Networking, Alan Stern,
linux-serial, Sylvain Lemieux, Wim Van Sebroeck, Linus Walleij,
Linux ARM, Sebastian Hesselbarth
In-Reply-To: <CAK8P3a2=gqeCMtdzdqg4d1n6v1-cdaHObeUoVXeB+=Okwd1rqA@mail.gmail.com>
On Wed, Jul 31, 2019 at 10:26:35PM +0200, Arnd Bergmann wrote:
> On Wed, Jul 31, 2019 at 10:23 PM Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > On Wed, Jul 31, 2019 at 09:56:45PM +0200, Arnd Bergmann wrote:
> > > The only thing that prevents building this driver on other
> > > platforms is the mach/hardware.h include, which is not actually
> > > used here at all, so remove the line and allow CONFIG_COMPILE_TEST.
> > >
> > > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> >
> > Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> >
> > What is the plan for this patch ? Push through watchdog
> > or through your branch ?
>
> I would prefer my branch so I can apply the final patch without waiting
> for another release. Not in a hurry though, so if some other maintainer
Ok with me.
Guenter
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 13/13] arm64: defconfig: Enable HFPLL
From: Jorge Ramirez-Ortiz @ 2019-07-31 20:29 UTC (permalink / raw)
To: jorge.ramirez-ortiz, bjorn.andersson, sboyd, david.brown,
jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
Cc: devicetree, linux-arm-msm, khasim.mohammed, linux-kernel,
amit.kucheria, linux-clk, vkoul, niklas.cassel, georgi.djakov,
linux-arm-kernel
In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org>
The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 34c3ac4e4b79..04b7fb26a942 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -698,6 +698,7 @@ CONFIG_MSM_MMCC_8996=y
CONFIG_MSM_GCC_8998=y
CONFIG_QCS_GCC_404=y
CONFIG_SDM_GCC_845=y
+CONFIG_QCOM_HFPLL=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_ARM_MHU=y
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox