* Re: [PATCH v8 05/14] media: rkisp1: add Rockchip ISP1 subdev driver
From: Hans Verkuil @ 2019-08-07 10:39 UTC (permalink / raw)
To: Helen Koike, hans.verkuil
Cc: devicetree, eddie.cai.linux, kernel, heiko, jacob2.chen,
jeffy.chen, zyc, linux-kernel, tfiga, linux-rockchip, Allon Huang,
Jacob Chen, laurent.pinchart, sakari.ailus, zhengsq, mchehab,
ezequiel, linux-arm-kernel, linux-media
In-Reply-To: <86e17716-193f-ca49-1104-9c599a667eeb@collabora.com>
On 8/6/19 8:51 PM, Helen Koike wrote:
> Hi Hans,
>
> On 7/30/19 3:42 PM, Helen Koike wrote:
>> From: Jacob Chen <jacob2.chen@rock-chips.com>
>>
>> Add the subdev driver for rockchip isp1.
>>
>> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
>> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
>> Signed-off-by: Yichong Zhong <zyc@rock-chips.com>
>> Signed-off-by: Jacob Chen <cc@rock-chips.com>
>> Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
>> Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
>> Signed-off-by: Tomasz Figa <tfiga@chromium.org>
>> [fixed unknown entity type / switched to PIXEL_RATE]
>> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
>> [update for upstream]
>> Signed-off-by: Helen Koike <helen.koike@collabora.com>
>>
>> ---
>>
>> Changes in v8: None
>> Changes in v7:
>> - fixed warning because of unknown entity type
>> - fixed v4l2-compliance errors regarding rkisp1 formats, try formats
>> and default values
>> - fix typo riksp1/rkisp1
>> - redesign: remove mipi/csi subdevice, sensors connect directly to the
>> isp subdevice in the media topology now. As a consequence, remove the
>> hack in mipidphy_g_mbus_config() where information from the sensor was
>> being propagated through the topology.
>> - From the old dphy:
>> * cache get_remote_sensor() in s_stream
>> * use V4L2_CID_PIXEL_RATE instead of V4L2_CID_LINK_FREQ
>> - Replace stream state with a boolean
>> - code styling and checkpatch fixes
>> - fix stop_stream (return after calling stop, do not reenable the stream)
>> - fix rkisp1_isp_sd_get_selection when V4L2_SUBDEV_FORMAT_TRY is set
>> - fix get format in output (isp_sd->out_fmt.mbus_code was being ignored)
>> - s/intput/input
>> - remove #define sd_to_isp_sd(_sd), add a static inline as it will be
>> reused by the capture
>>
>> drivers/media/platform/rockchip/isp1/rkisp1.c | 1286 +++++++++++++++++
>> drivers/media/platform/rockchip/isp1/rkisp1.h | 111 ++
>> 2 files changed, 1397 insertions(+)
>> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.c
>> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.h
>>
>> diff --git a/drivers/media/platform/rockchip/isp1/rkisp1.c b/drivers/media/platform/rockchip/isp1/rkisp1.c
>> new file mode 100644
>> index 000000000000..6d0c0ffb5e03
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip/isp1/rkisp1.c
>> @@ -0,0 +1,1286 @@
<snip>
>> +static int rkisp1_isp_sd_get_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *fmt)
>> +{
>> + struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
>> + struct v4l2_mbus_framefmt *mf = &fmt->format;
>> +
>> + if ((fmt->pad != RKISP1_ISP_PAD_SINK) &&
>> + (fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH)) {
>> + fmt->format.code = MEDIA_BUS_FMT_FIXED;
>> + /*
>> + * NOTE: setting a format here doesn't make much sense
>> + * but v4l2-compliance complains
>> + */
>> + fmt->format.width = RKISP1_DEFAULT_WIDTH;
>> + fmt->format.height = RKISP1_DEFAULT_HEIGHT;
>
> As I had mentioned to you, this is called for the isp pads connected to the
> DMA engines for statistics and parameters (meta data).
>
> If I remove those, I get the following errors:
>
> Sub-Device ioctls (Sink Pad 1):
> test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
> fail: v4l2-test-subdevs.cpp(311): fmt.width == 0 || fmt.width > 65536
> fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
> test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
> test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK
> test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
> fail: v4l2-test-subdevs.cpp(311): fmt.width == 0 || fmt.width > 65536
> fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
> test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
> test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK
> test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
>
> Here is the full log: http://ix.io/1QNt
>
> Is this a bug in v4l2-compliance?
Yes and no :-)
Currently v4l2-compliance assumes that only video is transferred over a media bus.
But that's not the case here, and testing the code field doesn't help v4l2-compliance
since MEDIA_BUS_FMT_FIXED is also still used by some older subdev drivers for video.
I think we need a new bus format: MEDIA_BUS_FMT_FIXED_METADATA. Then v4l2-compliance
can tell it apart from the regular fixed video bus format.
If I do a 'git grep MEDIA_BUS_FMT_FIXED' then I see that it is also in use by vsp1
for histogram information, so that should also be converted to use the new FIXED_METADATA
format, although that might be too late (there might be userspace complications).
Regards,
Hans
>
> Thanks
> Helen
>
>> + fmt->format.field = V4L2_FIELD_NONE;
>> + return 0;
>> + }
>> +
>> + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
>> + mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
>> + fmt->format = *mf;
>> + return 0;
>> + }
>> +
>> + if (fmt->pad == RKISP1_ISP_PAD_SINK) {
>> + *mf = isp_sd->in_frm;
>> + } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
>> + /* format of source pad */
>> + *mf = isp_sd->in_frm;
>> + mf->code = isp_sd->out_fmt.mbus_code;
>> + /* window size of source pad */
>> + mf->width = isp_sd->out_crop.width;
>> + mf->height = isp_sd->out_crop.height;
>> + mf->quantization = isp_sd->quantization;
>> + }
>> + mf->field = V4L2_FIELD_NONE;
>> +
>> + return 0;
>> +}
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^ permalink raw reply
* Re: [PATCH] arm64/ptrace: Fix typoes in sve_set() comment
From: Dave Martin @ 2019-08-07 10:38 UTC (permalink / raw)
To: Julien Grall; +Cc: catalin.marinas, will, linux-kernel, linux-arm-kernel, oleg
In-Reply-To: <20190807103445.32257-1-julien.grall@arm.com>
On Wed, Aug 07, 2019 at 11:34:45AM +0100, Julien Grall wrote:
> The ptrace trace SVE flags are prefixed with SVE_PT_*. Update the
> comment accordingly.
>
> Signed-off-by: Julien Grall <julien.grall@arm.com>
> ---
> arch/arm64/kernel/ptrace.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
> index 17525da8d5c8..0de3eae09d36 100644
> --- a/arch/arm64/kernel/ptrace.c
> +++ b/arch/arm64/kernel/ptrace.c
> @@ -870,7 +870,7 @@ static int sve_set(struct task_struct *target,
> goto out;
>
> /*
> - * Apart from PT_SVE_REGS_MASK, all PT_SVE_* flags are consumed by
> + * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by
> * sve_set_vector_length(), which will also validate them for us:
> */
Thanks for spotting that.
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Cheers
---Dave
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^ permalink raw reply
* Re: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI v2.0
From: Sudeep Holla @ 2019-08-07 10:35 UTC (permalink / raw)
To: Philipp Zabel
Cc: Peng Fan, Etienne Carriere, Souvik Chakravarty, wesleys, aidapala,
linux-kernel, Saeed Nowshadi, Bo Zhang, Felix Burton, Jim Quinlan,
pajay, Gaku Inami, Volodymyr Babchuk, linux-arm-kernel
In-Reply-To: <1565165870.5048.4.camel@pengutronix.de>
On Wed, Aug 07, 2019 at 10:17:50AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> > states a given device or domain can enter. Device(s) that can be
> > collectively reset through a common reset signal constitute a reset
> > domain for the firmware.
> >
> > A reset domain can be reset autonomously or explicitly through assertion
> > and de-assertion of the signal. When autonomous reset is chosen, the
> > firmware is responsible for taking the necessary steps to reset the
> > domain and to subsequently bring it out of reset. When explicit reset is
> > chosen, the caller has to specifically assert and then de-assert the
> > reset signal by issuing two separate RESET commands.
> >
> > Add the basic SCMI reset infrastructure that can be used by Linux
> > reset controller driver.
> >
> > Cc: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> > ---
> > drivers/firmware/arm_scmi/Makefile | 2 +-
> > drivers/firmware/arm_scmi/reset.c | 231 +++++++++++++++++++++++++++++
> > include/linux/scmi_protocol.h | 26 ++++
> > 3 files changed, 258 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/firmware/arm_scmi/reset.c
> >
> > diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile
> > index c47d28d556b6..5f298f00a82e 100644
> > --- a/drivers/firmware/arm_scmi/Makefile
> > +++ b/drivers/firmware/arm_scmi/Makefile
> > @@ -2,5 +2,5 @@
> > obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o
> > scmi-bus-y = bus.o
> > scmi-driver-y = driver.o
> > -scmi-protocols-y = base.o clock.o perf.o power.o sensors.o
> > +scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
> > obj-$(CONFIG_ARM_SCMI_POWER_DOMAIN) += scmi_pm_domain.o
> > diff --git a/drivers/firmware/arm_scmi/reset.c b/drivers/firmware/arm_scmi/reset.c
> > new file mode 100644
> > index 000000000000..11cb8b5ccf34
> > --- /dev/null
> > +++ b/drivers/firmware/arm_scmi/reset.c
> > @@ -0,0 +1,231 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * System Control and Management Interface (SCMI) Reset Protocol
> > + *
> > + * Copyright (C) 2019 ARM Ltd.
> > + */
> > +
> > +#include "common.h"
> > +
> > +enum scmi_reset_protocol_cmd {
> > + RESET_DOMAIN_ATTRIBUTES = 0x3,
> > + RESET = 0x4,
> > + RESET_NOTIFY = 0x5,
> > +};
> > +
> > +enum scmi_reset_protocol_notify {
> > + RESET_ISSUED = 0x0,
> > +};
> > +
> > +#define NUM_RESET_DOMAIN_MASK 0xffff
> > +#define RESET_NOTIFY_ENABLE BIT(0)
> > +
> > +struct scmi_msg_resp_reset_domain_attributes {
> > + __le32 attributes;
> > +#define SUPPORTS_ASYNC_RESET(x) ((x) & BIT(31))
> > +#define SUPPORTS_NOTIFY_RESET(x) ((x) & BIT(30))
> > + __le32 latency;
> > + u8 name[SCMI_MAX_STR_SIZE];
> > +};
> > +
> > +struct scmi_msg_reset_domain_reset {
> > + __le32 domain_id;
> > + __le32 flags;
> > +#define AUTONOMOUS_RESET BIT(0)
> > +#define EXPLICIT_RESET_ASSERT BIT(1)
> > +#define ASYNCHRONOUS_RESET BIT(2)
> > + __le32 reset_state;
> > +#define ARCH_RESET_TYPE BIT(31)
> > +#define COLD_RESET_STATE BIT(0)
> > +#define ARCH_COLD_RESET (ARCH_RESET_TYPE | COLD_RESET_STATE)
> > +};
> > +
> > +struct reset_dom_info {
> > + bool async_reset;
> > + bool reset_notify;
> > + u32 latency_us;
> > + char name[SCMI_MAX_STR_SIZE];
> > +};
> > +
> > +struct scmi_reset_info {
> > + int num_domains;
> > + struct reset_dom_info *dom_info;
> > +};
> > +
> > +static int scmi_reset_attributes_get(const struct scmi_handle *handle,
> > + struct scmi_reset_info *pi)
> > +{
> > + int ret;
> > + struct scmi_xfer *t;
> > + u32 *attr;
> > +
> > + ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES,
> > + SCMI_PROTOCOL_RESET, 0, sizeof(*attr), &t);
> > + if (ret)
> > + return ret;
> > +
> > + attr = t->rx.buf;
> > +
> > + ret = scmi_do_xfer(handle, t);
> > + if (!ret)
> > + pi->num_domains = le32_to_cpu(*attr) & NUM_RESET_DOMAIN_MASK;
> > +
> > + scmi_xfer_put(handle, t);
> > + return ret;
> > +}
> > +
> > +static int
> > +scmi_reset_domain_attributes_get(const struct scmi_handle *handle, u32 domain,
> > + struct reset_dom_info *dom_info)
> > +{
> > + int ret;
> > + struct scmi_xfer *t;
> > + struct scmi_msg_resp_reset_domain_attributes *attr;
> > +
> > + ret = scmi_xfer_get_init(handle, RESET_DOMAIN_ATTRIBUTES,
> > + SCMI_PROTOCOL_RESET, sizeof(domain),
> > + sizeof(*attr), &t);
> > + if (ret)
> > + return ret;
> > +
> > + *(__le32 *)t->tx.buf = cpu_to_le32(domain);
>
> Should this use
> put_unaligned_le32(domain, t->tx.buf);
> ? Either way,
>
Ah, new function to me. I will take a look, may need more place to fix.
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
>
Thanks,
Sudeep
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^ permalink raw reply
* [PATCH] arm64/ptrace: Fix typoes in sve_set() comment
From: Julien Grall @ 2019-08-07 10:34 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: catalin.marinas, Julien Grall, will, oleg, Dave.Martin
The ptrace trace SVE flags are prefixed with SVE_PT_*. Update the
comment accordingly.
Signed-off-by: Julien Grall <julien.grall@arm.com>
---
arch/arm64/kernel/ptrace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 17525da8d5c8..0de3eae09d36 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -870,7 +870,7 @@ static int sve_set(struct task_struct *target,
goto out;
/*
- * Apart from PT_SVE_REGS_MASK, all PT_SVE_* flags are consumed by
+ * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by
* sve_set_vector_length(), which will also validate them for us:
*/
ret = sve_set_vector_length(target, header.vl,
--
2.11.0
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* Re: [PATCH v2 5/5] reset: Add support for resets provided by SCMI
From: Sudeep Holla @ 2019-08-07 10:31 UTC (permalink / raw)
To: Philipp Zabel
Cc: Peng Fan, Etienne Carriere, Souvik Chakravarty, wesleys, aidapala,
linux-kernel, Saeed Nowshadi, Bo Zhang, Felix Burton, Jim Quinlan,
pajay, Gaku Inami, Volodymyr Babchuk, linux-arm-kernel
In-Reply-To: <1565165066.5048.2.camel@pengutronix.de>
On Wed, Aug 07, 2019 at 10:04:26AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > On some ARM based systems, a separate Cortex-M based System Control
> > Processor(SCP) provides the overall power, clock, reset and system
> > control. System Control and Management Interface(SCMI) Message Protocol
> > is defined for the communication between the Application Cores(AP)
> > and the SCP.
> >
> > Adds support for the resets provided using SCMI protocol for performing
> > reset management of various devices present on the SoC. Various reset
> > functionalities are achieved by the means of different ARM SCMI device
> > operations provided by the ARM SCMI framework.
> >
> > Cc: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/reset/Kconfig | 11 ++++
> > drivers/reset/Makefile | 1 +
> > drivers/reset/reset-scmi.c | 126 +++++++++++++++++++++++++++++++++++++
> > 4 files changed, 139 insertions(+)
> > create mode 100644 drivers/reset/reset-scmi.c
> >
> > v1->v2:
> > - Renamed RESET_ARM_SCMI to RESET_SCMI and reworded Kconfig text
> > - Dropped unused struct device pointer from scmi_reset_data
> > - Added to_scmi_handle which helped to remove some repetitive code
> > - Fixed some doxygen comments
> > - Initialised rcdev.nr_resets
> > - Fixed MODULE_DESCRIPTION
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 6426db5198f0..f4af5c59c116 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -15545,6 +15545,7 @@ F: drivers/clk/clk-sc[mp]i.c
> > F: drivers/cpufreq/sc[mp]i-cpufreq.c
> > F: drivers/firmware/arm_scpi.c
> > F: drivers/firmware/arm_scmi/
> > +F: drivers/reset/reset-scmi.c
> > F: include/linux/sc[mp]i_protocol.h
> >
> > SYSTEM RESET/SHUTDOWN DRIVERS
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index 21efb7d39d62..4178ac11ba85 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -116,6 +116,17 @@ config RESET_QCOM_PDC
> > to control reset signals provided by PDC for Modem, Compute,
> > Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
> >
> > +config RESET_SCMI
> > + tristate "Reset driver controlled via ARM SCMI interface"
> > + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
> > + default ARM_SCMI_PROTOCOL
> > + help
> > + This driver provides support for reset signal/domains that are
> > + controlled by firmware that implements the SCMI interface.
> > +
> > + This driver uses SCMI Message Protocol to interact with the
> > + firmware controlling all the reset signals.
> > +
> > config RESET_SIMPLE
> > bool "Simple Reset Controller Driver" if COMPILE_TEST
> > default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED || ARCH_BITMAIN
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index 61456b8f659c..cf60ce526064 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> > obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> > obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> > obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> > +obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
> > obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> > obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
> > obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> > diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
> > new file mode 100644
> > index 000000000000..5e976a02a6cc
> > --- /dev/null
> > +++ b/drivers/reset/reset-scmi.c
> > @@ -0,0 +1,126 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * ARM System Control and Management Interface (ARM SCMI) reset driver
> > + *
> > + * Copyright (C) 2019 ARM Ltd.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/mutex.h>
>
> You can drop mutex.h, it is unused.
>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
>
> This is not a platform device driver. Better replace this with
>
> #include <linux/device.h>
>
> > +#include <linux/reset-controller.h>
> > +#include <linux/scmi_protocol.h>
> > +
> > +/**
> > + * struct scmi_reset_data - reset controller information structure
> > + * @rcdev: reset controller entity
> > + * @handle: ARM SCMI handle used for communication with system controller
> > + * @dev: reset controller device pointer
>
> Drop this line, dev has been removed from struct scmi_reset_data.
>
All the above 3 are now fixed.
> > + */
> > +struct scmi_reset_data {
> > + struct reset_controller_dev rcdev;
> > + const struct scmi_handle *handle;
> > +};
> > +
> > +#define to_scmi_reset_data(p) container_of((p), struct scmi_reset_data, rcdev)
> > +#define to_scmi_handle(p) (to_scmi_reset_data(p)->handle)
> [...]
>
> Apart from these,
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
>
Thanks
--
Regards,
Sudeep
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^ permalink raw reply
* Re: [RFC PATCH] ARM: UNWINDER_FRAME_POINTER implementation for Clang
From: Dave Martin @ 2019-08-07 10:29 UTC (permalink / raw)
To: Nathan Huckleberry
Cc: Tri Vo, linux, linux-kernel, clang-built-linux, Robin Murphy,
linux-arm-kernel
In-Reply-To: <CAJkfWY5EL+MyRzSfcfJF2H8WoX73FEO0bOrwcoR4c4ekvaWvOQ@mail.gmail.com>
On Tue, Aug 06, 2019 at 02:29:16PM -0700, Nathan Huckleberry wrote:
> I'm not sure that we should disable a broken feature instead of
> attempting a fix.
>
> CONFIG_FUNCTION_GRAPH_TRACER is dependent on CONFIG_FRAME_POINTER and
> there have been reports by MediaTek that the frame pointer unwinder is
> faster in some cases.
Fair enough, just wanted to be sure we weren't doing something pointless.
[...]
Cheers
---Dave
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* Re: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
From: Sudeep Holla @ 2019-08-07 10:28 UTC (permalink / raw)
To: Peng Fan
Cc: aidapala@qti.qualcomm.com, Etienne Carriere, Souvik Chakravarty,
wesleys@xilinx.com, Ionela Voinescu, linux-kernel@vger.kernel.org,
Saeed Nowshadi, Quentin Perret, Bo Zhang, Felix Burton,
Jim Quinlan, Chris Redpath, pajay@qti.qualcomm.com, Gaku Inami,
Volodymyr Babchuk, linux-arm-kernel@lists.infradead.org
In-Reply-To: <AM0PR04MB4481BA101A13A0E45DA50E9088D40@AM0PR04MB4481.eurprd04.prod.outlook.com>
On Wed, Aug 07, 2019 at 09:23:41AM +0000, Peng Fan wrote:
> > Subject: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0
> > performance fastchannels
> >
> > SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional
> > channel that is dedicated to a single SCMI message type for controlling a
> > specific platform resource. They do not use a message header as they are
> > specialized for a single message.
> >
> > Only PERFORMANCE_LIMITS_{SET,GET} and
> > PERFORMANCE_LEVEL_{SET,GET} commands are supported over
> > fastchannels. As they are optional, they need to be discovered by
> > PERFORMANCE_DESCRIBE_FASTCHANNEL command.
> > Further {LIMIT,LEVEL}_SET commands can have optional doorbell support.
> >
> > Add support for discovery of these fastchannels.
> >
> > Cc: Ionela Voinescu <Ionela.Voinescu@arm.com>
> > Cc: Chris Redpath <Chris.Redpath@arm.com>
> > Cc: Quentin Perret <Quentin.Perret@arm.com>
> > Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> > ---
> > drivers/firmware/arm_scmi/perf.c | 153
> > ++++++++++++++++++++++++++++++-
> > 1 file changed, 149 insertions(+), 4 deletions(-)
> >
[...]
>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
>
Thanks for the review.
--
Regards,
Sudeep
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* Re: [PATCH v2 3/5] dt-bindings: arm: Extend SCMI to support new reset protocol
From: Sudeep Holla @ 2019-08-07 10:18 UTC (permalink / raw)
To: Philipp Zabel
Cc: Mark Rutland, devicetree, Peng Fan, Etienne Carriere,
Souvik Chakravarty, wesleys, aidapala, linux-kernel, Rob Herring,
Saeed Nowshadi, Bo Zhang, Felix Burton, Jim Quinlan, pajay,
Gaku Inami, Volodymyr Babchuk, linux-arm-kernel
In-Reply-To: <1565166410.5048.5.camel@pengutronix.de>
On Wed, Aug 07, 2019 at 10:26:50AM +0200, Philipp Zabel wrote:
> On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> > SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> > states a given device or domain can enter. Extend the existing SCMI
> > bindings to add reset protocol support by re-using the reset bindings
> > for bothe reset providers and consumers.
> ^
> typo
>
Thanks, fixed now.
--
Regards,
Sudeep
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* Re: [PATCH v4 0/3] DCMI bridge support
From: Hans Verkuil @ 2019-08-07 10:15 UTC (permalink / raw)
To: Hugues Fruchet, Alexandre Torgue, Mauro Carvalho Chehab,
Sakari Ailus
Cc: Mickael GUENE, linux-kernel, Philippe CORNU, Yannick Fertre,
Benjamin Gaignard, linux-stm32, linux-arm-kernel, linux-media
In-Reply-To: <1564577783-18627-1-git-send-email-hugues.fruchet@st.com>
Hi Hugues,
Can you provide the output of the most recent v4l2-compliance?
Use 'v4l2-compliance -s'.
Also, just to confirm, with this v4 there are no /dev/mediaX or
/dev/v4l-subdevX devices created anymore, right?
This v4 looks good to me, I just want to have these final checks
done.
Regards,
Hans
On 7/31/19 2:56 PM, Hugues Fruchet wrote:
> This patch serie allows to connect non-parallel camera sensor to
> DCMI thanks to a bridge connected in between such as STMIPID02 [1].
>
> Media controller support is introduced first, then support of
> several sub-devices within pipeline with dynamic linking
> between them.
> In order to keep backward compatibility with applications
> relying on V4L2 interface only, format set on video node
> is propagated to all sub-devices connected to camera interface.
>
> [1] https://www.spinics.net/lists/devicetree/msg278002.html
>
> ===========
> = history =
> ===========
> version 4:
> - Also drop subdev nodes registry as suggested by Hans:
> https://www.spinics.net/lists/arm-kernel/msg743375.html
>
> version 3:
> - Drop media device registry to not expose media controller
> interface to userspace as per Laurent' suggestion:
> https://www.spinics.net/lists/linux-media/msg153417.html
> - Prefer "source" instead of "sensor" and keep it in
> dcmi_graph_entity struct, move asd as first member
> of struct as per Sakari' suggestion:
> https://www.spinics.net/lists/linux-media/msg153119.html
> - Drop dcmi_graph_deinit() as per Sakari' suggestion:
> https://www.spinics.net/lists/linux-media/msg153417.html
>
> version 2:
> - Fix bus_info not consistent between media and V4L:
> https://www.spinics.net/lists/arm-kernel/msg717676.html
> - Propagation of format set on video node to the sub-devices
> chain connected on camera interface
>
> version 1:
> - Initial submission
>
> Hugues Fruchet (3):
> media: stm32-dcmi: improve sensor subdev naming
> media: stm32-dcmi: add media controller support
> media: stm32-dcmi: add support of several sub-devices
>
> drivers/media/platform/Kconfig | 2 +-
> drivers/media/platform/stm32/stm32-dcmi.c | 283 +++++++++++++++++++++++++-----
> 2 files changed, 236 insertions(+), 49 deletions(-)
>
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* Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
From: Suzuki K Poulose @ 2019-08-07 10:12 UTC (permalink / raw)
To: saiprakash.ranjan, mathieu.poirier, bjorn.andersson, leo.yan,
alexander.shishkin, agross, david.brown, mark.rutland
Cc: rnayak, marc.w.gonzalez, linux-arm-msm, linux-kernel, sibis,
vivek.gautam, linux-arm-kernel
In-Reply-To: <b5cb08ef-ca2f-e852-f234-d0f693b58596@codeaurora.org>
Sai,
On 07/08/2019 11:08, Sai Prakash Ranjan wrote:
> Hi Suzuki,
>
> On 7/31/2019 11:35 AM, Sai Prakash Ranjan wrote:
>> Hi Suzuki,
>>
>> On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
>>> Add coresight components found on Qualcomm SDM845 SoC.
>>>
>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
>>> 1 file changed, 451 insertions(+)
>>
>> I have tested coresight with scatter gather on SDM845 MTP and MSM8996
>> based DB820c board and posted the results in
>>
>> - https://github.com/saiprakash-ranjan/coresight-test-results
>>
>> Please let me know if you need some additional testing done.
>>
>> I could not perform coresight tests on MSM8998 MTP with latest build
>> as it was resulting in crash due to some AHB timeouts. This was not
>> due to scatter-gather and mostly likely the problem with the build.
>> Maybe we can keep msm8998-coresight on hold?
>>
>> BTW, patches are based on linux-next.
>>
>
> Any more tests you would want me to run?
Apologies for the late response. I had seen the results and they look fine.
I was hitting some issues, which I have now root caused to firmware issues.
So we are good to go.
Suzuki
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* Re: [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support
From: Sai Prakash Ranjan @ 2019-08-07 10:08 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Bjorn Andersson, Leo Yan,
Alexander Shishkin, Andy Gross, David Brown, Mark Rutland
Cc: Rajendra Nayak, Marc Gonzalez, linux-arm-msm, linux-kernel,
Sibi Sankar, Vivek Gautam, linux-arm-kernel
In-Reply-To: <b50c06d4-8298-7abe-4442-2aff336509f5@codeaurora.org>
Hi Suzuki,
On 7/31/2019 11:35 AM, Sai Prakash Ranjan wrote:
> Hi Suzuki,
>
> On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
>> 1 file changed, 451 insertions(+)
>
> I have tested coresight with scatter gather on SDM845 MTP and MSM8996
> based DB820c board and posted the results in
>
> - https://github.com/saiprakash-ranjan/coresight-test-results
>
> Please let me know if you need some additional testing done.
>
> I could not perform coresight tests on MSM8998 MTP with latest build
> as it was resulting in crash due to some AHB timeouts. This was not
> due to scatter-gather and mostly likely the problem with the build.
> Maybe we can keep msm8998-coresight on hold?
>
> BTW, patches are based on linux-next.
>
Any more tests you would want me to run?
-Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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* RE: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI v2.0
From: Peng Fan @ 2019-08-07 10:07 UTC (permalink / raw)
To: Sudeep Holla, linux-arm-kernel@lists.infradead.org
Cc: aidapala@qti.qualcomm.com, Etienne Carriere, Souvik Chakravarty,
Philipp Zabel, wesleys@xilinx.com, linux-kernel@vger.kernel.org,
Saeed Nowshadi, Bo Zhang, Felix Burton, Jim Quinlan,
pajay@qti.qualcomm.com, Gaku Inami, Volodymyr Babchuk
In-Reply-To: <20190806170208.6787-5-sudeep.holla@arm.com>
> Subject: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI
> v2.0
>
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Device(s) that can be collectively
> reset through a common reset signal constitute a reset domain for the
> firmware.
>
> A reset domain can be reset autonomously or explicitly through assertion and
> de-assertion of the signal. When autonomous reset is chosen, the firmware is
> responsible for taking the necessary steps to reset the domain and to
> subsequently bring it out of reset. When explicit reset is chosen, the caller has
> to specifically assert and then de-assert the reset signal by issuing two
> separate RESET commands.
>
> Add the basic SCMI reset infrastructure that can be used by Linux reset
> controller driver.
>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> drivers/firmware/arm_scmi/Makefile | 2 +-
> drivers/firmware/arm_scmi/reset.c | 231
> +++++++++++++++++++++++++++++
> include/linux/scmi_protocol.h | 26 ++++
> 3 files changed, 258 insertions(+), 1 deletion(-) create mode 100644
> drivers/firmware/arm_scmi/reset.c
>
> diff --git a/drivers/firmware/arm_scmi/Makefile
> b/drivers/firmware/arm_scmi/Makefile
> index c47d28d556b6..5f298f00a82e 100644
> --- a/drivers/firmware/arm_scmi/Makefile
> +++ b/drivers/firmware/arm_scmi/Makefile
> @@ -2,5 +2,5 @@
> obj-y = scmi-bus.o scmi-driver.o scmi-protocols.o
> scmi-bus-y = bus.o
> scmi-driver-y = driver.o
> -scmi-protocols-y = base.o clock.o perf.o power.o sensors.o
> +scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
> obj-$(CONFIG_ARM_SCMI_POWER_DOMAIN) += scmi_pm_domain.o diff
> --git a/drivers/firmware/arm_scmi/reset.c
> b/drivers/firmware/arm_scmi/reset.c
> new file mode 100644
> index 000000000000..11cb8b5ccf34
> --- /dev/null
> +++ b/drivers/firmware/arm_scmi/reset.c
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * System Control and Management Interface (SCMI) Reset Protocol
> + *
> + * Copyright (C) 2019 ARM Ltd.
> + */
> +
> +#include "common.h"
> +
> +enum scmi_reset_protocol_cmd {
> + RESET_DOMAIN_ATTRIBUTES = 0x3,
> + RESET = 0x4,
> + RESET_NOTIFY = 0x5,
> +};
> +
> +enum scmi_reset_protocol_notify {
> + RESET_ISSUED = 0x0,
> +};
> +
> +#define NUM_RESET_DOMAIN_MASK 0xffff
> +#define RESET_NOTIFY_ENABLE BIT(0)
> +
> +struct scmi_msg_resp_reset_domain_attributes {
> + __le32 attributes;
> +#define SUPPORTS_ASYNC_RESET(x) ((x) & BIT(31))
> +#define SUPPORTS_NOTIFY_RESET(x) ((x) & BIT(30))
> + __le32 latency;
> + u8 name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_msg_reset_domain_reset {
> + __le32 domain_id;
> + __le32 flags;
> +#define AUTONOMOUS_RESET BIT(0)
> +#define EXPLICIT_RESET_ASSERT BIT(1)
> +#define ASYNCHRONOUS_RESET BIT(2)
> + __le32 reset_state;
> +#define ARCH_RESET_TYPE BIT(31)
> +#define COLD_RESET_STATE BIT(0)
> +#define ARCH_COLD_RESET (ARCH_RESET_TYPE |
> COLD_RESET_STATE)
> +};
> +
> +struct reset_dom_info {
> + bool async_reset;
> + bool reset_notify;
> + u32 latency_us;
> + char name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_reset_info {
> + int num_domains;
> + struct reset_dom_info *dom_info;
> +};
> +
> +static int scmi_reset_attributes_get(const struct scmi_handle *handle,
> + struct scmi_reset_info *pi)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + u32 *attr;
> +
> + ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES,
> + SCMI_PROTOCOL_RESET, 0, sizeof(*attr), &t);
> + if (ret)
> + return ret;
> +
> + attr = t->rx.buf;
> +
> + ret = scmi_do_xfer(handle, t);
> + if (!ret)
> + pi->num_domains = le32_to_cpu(*attr) &
> NUM_RESET_DOMAIN_MASK;
> +
> + scmi_xfer_put(handle, t);
> + return ret;
> +}
> +
> +static int
> +scmi_reset_domain_attributes_get(const struct scmi_handle *handle, u32
> domain,
> + struct reset_dom_info *dom_info)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + struct scmi_msg_resp_reset_domain_attributes *attr;
> +
> + ret = scmi_xfer_get_init(handle, RESET_DOMAIN_ATTRIBUTES,
> + SCMI_PROTOCOL_RESET, sizeof(domain),
> + sizeof(*attr), &t);
> + if (ret)
> + return ret;
> +
> + *(__le32 *)t->tx.buf = cpu_to_le32(domain);
> + attr = t->rx.buf;
> +
> + ret = scmi_do_xfer(handle, t);
> + if (!ret) {
> + u32 attributes = le32_to_cpu(attr->attributes);
> +
> + dom_info->async_reset = SUPPORTS_ASYNC_RESET(attributes);
> + dom_info->reset_notify = SUPPORTS_NOTIFY_RESET(attributes);
> + dom_info->latency_us = le32_to_cpu(attr->latency);
> + if (dom_info->latency_us == U32_MAX)
> + dom_info->latency_us = 0;
> + strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE);
> + }
> +
> + scmi_xfer_put(handle, t);
> + return ret;
> +}
> +
> +static int scmi_reset_num_domains_get(const struct scmi_handle *handle)
> +{
> + struct scmi_reset_info *pi = handle->reset_priv;
> +
> + return pi->num_domains;
> +}
> +
> +static char *scmi_reset_name_get(const struct scmi_handle *handle, u32
> +domain) {
> + struct scmi_reset_info *pi = handle->reset_priv;
> + struct reset_dom_info *dom = pi->dom_info + domain;
> +
> + return dom->name;
> +}
> +
> +static int scmi_reset_latency_get(const struct scmi_handle *handle, u32
> +domain) {
> + struct scmi_reset_info *pi = handle->reset_priv;
> + struct reset_dom_info *dom = pi->dom_info + domain;
> +
> + return dom->latency_us;
> +}
> +
> +static int scmi_domain_reset(const struct scmi_handle *handle, u32 domain,
> + u32 flags, u32 state)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + struct scmi_msg_reset_domain_reset *dom;
> + struct scmi_reset_info *pi = handle->reset_priv;
> + struct reset_dom_info *rdom = pi->dom_info + domain;
> +
> + if (rdom->async_reset)
> + flags |= ASYNCHRONOUS_RESET;
> +
> + ret = scmi_xfer_get_init(handle, RESET, SCMI_PROTOCOL_RESET,
> + sizeof(*dom), 0, &t);
> + if (ret)
> + return ret;
> +
> + dom = t->tx.buf;
> + dom->domain_id = cpu_to_le32(domain);
> + dom->flags = cpu_to_le32(flags);
> + dom->domain_id = cpu_to_le32(state);
> +
> + if (rdom->async_reset)
> + ret = scmi_do_xfer_with_response(handle, t);
> + else
> + ret = scmi_do_xfer(handle, t);
> +
> + scmi_xfer_put(handle, t);
> + return ret;
> +}
> +
> +static int scmi_reset_domain_reset(const struct scmi_handle *handle,
> +u32 domain) {
> + return scmi_domain_reset(handle, domain, AUTONOMOUS_RESET,
> + ARCH_COLD_RESET);
> +}
> +
> +static int
> +scmi_reset_domain_assert(const struct scmi_handle *handle, u32 domain)
> +{
> + return scmi_domain_reset(handle, domain, EXPLICIT_RESET_ASSERT,
> + ARCH_COLD_RESET);
> +}
> +
> +static int
> +scmi_reset_domain_deassert(const struct scmi_handle *handle, u32
> +domain) {
> + return scmi_domain_reset(handle, domain, 0, ARCH_COLD_RESET); }
> +
> +static struct scmi_reset_ops reset_ops = {
> + .num_domains_get = scmi_reset_num_domains_get,
> + .name_get = scmi_reset_name_get,
> + .latency_get = scmi_reset_latency_get,
> + .reset = scmi_reset_domain_reset,
> + .assert = scmi_reset_domain_assert,
> + .deassert = scmi_reset_domain_deassert, };
> +
> +static int scmi_reset_protocol_init(struct scmi_handle *handle) {
> + int domain;
> + u32 version;
> + struct scmi_reset_info *pinfo;
> +
> + scmi_version_get(handle, SCMI_PROTOCOL_RESET, &version);
> +
> + dev_dbg(handle->dev, "Reset Version %d.%d\n",
> + PROTOCOL_REV_MAJOR(version),
> PROTOCOL_REV_MINOR(version));
> +
> + pinfo = devm_kzalloc(handle->dev, sizeof(*pinfo), GFP_KERNEL);
> + if (!pinfo)
> + return -ENOMEM;
> +
> + scmi_reset_attributes_get(handle, pinfo);
> +
> + pinfo->dom_info = devm_kcalloc(handle->dev, pinfo->num_domains,
> + sizeof(*pinfo->dom_info), GFP_KERNEL);
> + if (!pinfo->dom_info)
> + return -ENOMEM;
> +
> + for (domain = 0; domain < pinfo->num_domains; domain++) {
> + struct reset_dom_info *dom = pinfo->dom_info + domain;
> +
> + scmi_reset_domain_attributes_get(handle, domain, dom);
> + }
> +
> + handle->reset_ops = &reset_ops;
> + handle->reset_priv = pinfo;
> +
> + return 0;
> +}
> +
> +static int __init scmi_reset_init(void) {
> + return scmi_protocol_register(SCMI_PROTOCOL_RESET,
> + &scmi_reset_protocol_init);
> +}
> +subsys_initcall(scmi_reset_init);
> diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
> index f0f2b53a1dac..881fea47c83d 100644
> --- a/include/linux/scmi_protocol.h
> +++ b/include/linux/scmi_protocol.h
> @@ -187,6 +187,26 @@ struct scmi_sensor_ops {
> u64 *value);
> };
>
> +/**
> + * struct scmi_reset_ops - represents the various operations provided
> + * by SCMI Reset Protocol
> + *
> + * @num_domains_get: get the count of reset domains provided by SCMI
> + * @name_get: gets the name of a reset domain
> + * @latency_get: gets the reset latency for the specified reset domain
> + * @reset: resets the specified reset domain
> + * @assert: explicitly assert reset signal of the specified reset
> +domain
> + * @deassert: explicitly deassert reset signal of the specified reset
> +domain */ struct scmi_reset_ops {
> + int (*num_domains_get)(const struct scmi_handle *handle);
> + char *(*name_get)(const struct scmi_handle *handle, u32 domain);
> + int (*latency_get)(const struct scmi_handle *handle, u32 domain);
> + int (*reset)(const struct scmi_handle *handle, u32 domain);
> + int (*assert)(const struct scmi_handle *handle, u32 domain);
> + int (*deassert)(const struct scmi_handle *handle, u32 domain); };
> +
> /**
> * struct scmi_handle - Handle returned to ARM SCMI clients for usage.
> *
> @@ -196,6 +216,7 @@ struct scmi_sensor_ops {
> * @perf_ops: pointer to set of performance protocol operations
> * @clk_ops: pointer to set of clock protocol operations
> * @sensor_ops: pointer to set of sensor protocol operations
> + * @reset_ops: pointer to set of reset protocol operations
> * @perf_priv: pointer to private data structure specific to performance
> * protocol(for internal use only)
> * @clk_priv: pointer to private data structure specific to clock @@ -204,6
> +225,8 @@ struct scmi_sensor_ops {
> * protocol(for internal use only)
> * @sensor_priv: pointer to private data structure specific to sensors
> * protocol(for internal use only)
> + * @reset_priv: pointer to private data structure specific to reset
> + * protocol(for internal use only)
> */
> struct scmi_handle {
> struct device *dev;
> @@ -212,11 +235,13 @@ struct scmi_handle {
> struct scmi_clk_ops *clk_ops;
> struct scmi_power_ops *power_ops;
> struct scmi_sensor_ops *sensor_ops;
> + struct scmi_reset_ops *reset_ops;
> /* for protocol internal use */
> void *perf_priv;
> void *clk_priv;
> void *power_priv;
> void *sensor_priv;
> + void *reset_priv;
> };
>
> enum scmi_std_protocol {
> @@ -226,6 +251,7 @@ enum scmi_std_protocol {
> SCMI_PROTOCOL_PERF = 0x13,
> SCMI_PROTOCOL_CLOCK = 0x14,
> SCMI_PROTOCOL_SENSOR = 0x15,
> + SCMI_PROTOCOL_RESET = 0x16,
> };
Reviewed-by: Peng Fan <peng.fan@nxp.com>
>
> struct scmi_device {
> --
> 2.17.1
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^ permalink raw reply
* RE: [PATCH v2 2/5] firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
From: Peng Fan @ 2019-08-07 10:01 UTC (permalink / raw)
To: Sudeep Holla, linux-arm-kernel@lists.infradead.org
Cc: aidapala@qti.qualcomm.com, Etienne Carriere, Souvik Chakravarty,
wesleys@xilinx.com, Ionela Voinescu, linux-kernel@vger.kernel.org,
Saeed Nowshadi, Quentin Perret, Bo Zhang, Felix Burton,
Jim Quinlan, Chris Redpath, pajay@qti.qualcomm.com, Gaku Inami,
Volodymyr Babchuk, dl-linux-imx
In-Reply-To: <20190806170208.6787-3-sudeep.holla@arm.com>
> Subject: [PATCH v2 2/5] firmware: arm_scmi: Make use SCMI v2.0
> fastchannel for performance protocol
>
> SCMI v2.0 adds support for "FastChannel" which do not use a message
> header as they are specialized for a single message.
>
> Only PERFORMANCE_LIMITS_{SET,GET} and
> PERFORMANCE_LEVEL_{SET,GET} commands are supported over
> fastchannels. As they are optional, they need to be discovered by
> PERFORMANCE_DESCRIBE_FASTCHANNEL command.
> Further {LIMIT,LEVEL}_SET commands can have optional doorbell support.
>
> Add support for making use of these fastchannels.
>
> Cc: Ionela Voinescu <Ionela.Voinescu@arm.com>
> Cc: Chris Redpath <Chris.Redpath@arm.com>
> Cc: Quentin Perret <Quentin.Perret@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> drivers/firmware/arm_scmi/perf.c | 104
> +++++++++++++++++++++++++++++--
> 1 file changed, 100 insertions(+), 4 deletions(-)
>
> v1->v2:
> - Changed the macro SCMI_PERF_FC_RING_DB to use do {} while(0)
>
> diff --git a/drivers/firmware/arm_scmi/perf.c
> b/drivers/firmware/arm_scmi/perf.c
> index 6cce3e82e81e..fb7f6cab2c11 100644
> --- a/drivers/firmware/arm_scmi/perf.c
> +++ b/drivers/firmware/arm_scmi/perf.c
> @@ -8,6 +8,7 @@
> #include <linux/bits.h>
> #include <linux/of.h>
> #include <linux/io.h>
> +#include <linux/io-64-nonatomic-hi-lo.h>
> #include <linux/platform_device.h>
> #include <linux/pm_opp.h>
> #include <linux/sort.h>
> @@ -293,7 +294,42 @@ scmi_perf_describe_levels_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> -static int scmi_perf_limits_set(const struct scmi_handle *handle, u32
> domain,
> +#define SCMI_PERF_FC_RING_DB(doorbell, w) \
> +do { \
> + u##w val = 0; \
> + struct scmi_fc_db_info *db = doorbell; \
> + \
> + if (db->mask) \
> + val = ioread##w(db->addr) & db->mask; \
> + iowrite##w((u##w)db->set | val, db->addr); \
> +} while(0)
> +
> +static void scmi_perf_fc_ring_db(struct scmi_fc_db_info *db) {
> + if (!db || !db->addr)
> + return;
> +
> + if (db->width == 1)
> + SCMI_PERF_FC_RING_DB(db, 8);
> + else if (db->width == 2)
> + SCMI_PERF_FC_RING_DB(db, 16);
> + else if (db->width == 4)
> + SCMI_PERF_FC_RING_DB(db, 32);
> + else /* db->width == 8 */
> +#ifdef CONFIG_64BIT
> + SCMI_PERF_FC_RING_DB(db, 64);
> +#else
> + {
> + u64 val = 0;
> +
> + if (db->mask)
> + val = ioread64_hi_lo(db->addr) & db->mask;
> + iowrite64_hi_lo(db->set, db->addr);
> + }
> +#endif
> +}
> +
> +static int scmi_perf_mb_limits_set(const struct scmi_handle *handle,
> +u32 domain,
> u32 max_perf, u32 min_perf)
> {
> int ret;
> @@ -316,7 +352,23 @@ static int scmi_perf_limits_set(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> -static int scmi_perf_limits_get(const struct scmi_handle *handle, u32
> domain,
> +static int scmi_perf_limits_set(const struct scmi_handle *handle, u32
> domain,
> + u32 max_perf, u32 min_perf)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->limit_set_addr) {
> + iowrite32(max_perf, dom->fc_info->limit_set_addr);
> + iowrite32(min_perf, dom->fc_info->limit_set_addr + 4);
> + scmi_perf_fc_ring_db(dom->fc_info->limit_set_db);
> + return 0;
> + }
> +
> + return scmi_perf_mb_limits_set(handle, domain, max_perf, min_perf); }
> +
> +static int scmi_perf_mb_limits_get(const struct scmi_handle *handle,
> +u32 domain,
> u32 *max_perf, u32 *min_perf)
> {
> int ret;
> @@ -342,7 +394,22 @@ static int scmi_perf_limits_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> -static int scmi_perf_level_set(const struct scmi_handle *handle, u32 domain,
> +static int scmi_perf_limits_get(const struct scmi_handle *handle, u32
> domain,
> + u32 *max_perf, u32 *min_perf)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->limit_get_addr) {
> + *max_perf = ioread32(dom->fc_info->limit_get_addr);
> + *min_perf = ioread32(dom->fc_info->limit_get_addr + 4);
> + return 0;
> + }
> +
> + return scmi_perf_mb_limits_get(handle, domain, max_perf, min_perf); }
> +
> +static int scmi_perf_mb_level_set(const struct scmi_handle *handle, u32
> +domain,
> u32 level, bool poll)
> {
> int ret;
> @@ -365,7 +432,22 @@ static int scmi_perf_level_set(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> -static int scmi_perf_level_get(const struct scmi_handle *handle, u32 domain,
> +static int scmi_perf_level_set(const struct scmi_handle *handle, u32
> domain,
> + u32 level, bool poll)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->level_set_addr) {
> + iowrite32(level, dom->fc_info->level_set_addr);
> + scmi_perf_fc_ring_db(dom->fc_info->level_set_db);
> + return 0;
> + }
> +
> + return scmi_perf_mb_level_set(handle, domain, level, poll); }
> +
> +static int scmi_perf_mb_level_get(const struct scmi_handle *handle, u32
> +domain,
> u32 *level, bool poll)
> {
> int ret;
> @@ -387,6 +469,20 @@ static int scmi_perf_level_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> +static int scmi_perf_level_get(const struct scmi_handle *handle, u32
> domain,
> + u32 *level, bool poll)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->level_get_addr) {
> + *level = ioread32(dom->fc_info->level_get_addr);
> + return 0;
> + }
> +
> + return scmi_perf_mb_level_get(handle, domain, level, poll); }
> +
> static bool scmi_perf_fc_size_is_valid(u32 msg, u32 size) {
> if ((msg == PERF_LEVEL_GET || msg == PERF_LEVEL_SET) && size == 4)
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> --
> 2.17.1
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^ permalink raw reply
* [PATCH] KVM: arm/arm64: vgic: Reevaluate level sensitive interrupts on enable
From: Alexandru Elisei @ 2019-08-07 9:53 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, kvm
Cc: maz, andre.przywara, christoffer.dall, eric.auger
A HW mapped level sensitive interrupt asserted by a device will not be put
into the ap_list if it is disabled at the VGIC level. When it is enabled
again, it will be inserted into the ap_list and written to a list register
on guest entry regardless of the state of the device.
We could argue that this can also happen on real hardware, when the command
to enable the interrupt reached the GIC before the device had the chance to
de-assert the interrupt signal; however, we emulate the distributor and
redistributors in software and we can do better than that.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
virt/kvm/arm/vgic/vgic-mmio.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
index 3ba7278fb533..44efc2ff863f 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.c
+++ b/virt/kvm/arm/vgic/vgic-mmio.c
@@ -113,6 +113,22 @@ void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
raw_spin_lock_irqsave(&irq->irq_lock, flags);
+ if (vgic_irq_is_mapped_level(irq)) {
+ bool was_high = irq->line_level;
+
+ /*
+ * We need to update the state of the interrupt because
+ * the guest might have changed the state of the device
+ * while the interrupt was disabled at the VGIC level.
+ */
+ irq->line_level = vgic_get_phys_line_level(irq);
+ /*
+ * Deactivate the physical interrupt so the GIC will let
+ * us know when it is asserted again.
+ */
+ if (!irq->active && was_high && !irq->line_level)
+ vgic_irq_set_phys_active(irq, false);
+ }
irq->enabled = true;
vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
--
2.7.4
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^ permalink raw reply related
* [PATCH 3/3] ARM: OMAP2+: omap-iommu.c conversion to ti-sysc
From: Tero Kristo @ 2019-08-07 9:44 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <1565171081-7899-1-git-send-email-t-kristo@ti.com>
Convert omap2 iommu platform code to use ti-sysc instead of legacy
omap-device / hwmod interfaces.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/omap-iommu.c | 99 ++++++++++++++++++++++++++++++++--------
1 file changed, 80 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 8f6b6b8..f8cbf6b 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -16,19 +16,27 @@
#include <linux/platform_device.h>
#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/list.h>
-#include "omap_hwmod.h"
-#include "omap_device.h"
#include "clockdomain.h"
#include "powerdomain.h"
+struct pwrdm_link {
+ struct device *dev;
+ struct powerdomain *pwrdm;
+ struct list_head node;
+};
+
+static DEFINE_SPINLOCK(iommu_lock);
+static struct clockdomain *emu_clkdm;
+static atomic_t emu_count;
+
static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
bool enable)
{
- static struct clockdomain *emu_clkdm;
- static DEFINE_SPINLOCK(emu_lock);
- static atomic_t count;
struct device_node *np = pdev->dev.of_node;
+ unsigned long flags;
if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
return;
@@ -39,34 +47,87 @@ static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
return;
}
- spin_lock(&emu_lock);
+ spin_lock_irqsave(&iommu_lock, flags);
- if (enable && (atomic_inc_return(&count) == 1))
+ if (enable && (atomic_inc_return(&emu_count) == 1))
clkdm_deny_idle(emu_clkdm);
- else if (!enable && (atomic_dec_return(&count) == 0))
+ else if (!enable && (atomic_dec_return(&emu_count) == 0))
clkdm_allow_idle(emu_clkdm);
- spin_unlock(&emu_lock);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+}
+
+static struct powerdomain *_get_pwrdm(struct device *dev)
+{
+ struct clk *clk;
+ struct clk_hw_omap *hwclk;
+ struct clockdomain *clkdm;
+ struct powerdomain *pwrdm = NULL;
+ struct pwrdm_link *entry;
+ unsigned long flags;
+ static LIST_HEAD(cache);
+
+ spin_lock_irqsave(&iommu_lock, flags);
+
+ list_for_each_entry(entry, &cache, node) {
+ if (entry->dev == dev) {
+ pwrdm = entry->pwrdm;
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&iommu_lock, flags);
+
+ if (pwrdm)
+ return pwrdm;
+
+ clk = of_clk_get(dev->of_node->parent, 0);
+ if (!clk) {
+ dev_err(dev, "no fck found\n");
+ return NULL;
+ }
+
+ hwclk = to_clk_hw_omap(__clk_get_hw(clk));
+ clk_put(clk);
+ if (!hwclk || !hwclk->clkdm_name) {
+ dev_err(dev, "no hwclk data\n");
+ return NULL;
+ }
+
+ clkdm = clkdm_lookup(hwclk->clkdm_name);
+ if (!clkdm) {
+ dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name);
+ return NULL;
+ }
+
+ pwrdm = clkdm_get_pwrdm(clkdm);
+ if (!pwrdm) {
+ dev_err(dev, "pwrdm not found: %s\n", clkdm->name);
+ return NULL;
+ }
+
+ entry = kmalloc(sizeof(*entry), GFP_KERNEL);
+ if (entry) {
+ entry->dev = dev;
+ entry->pwrdm = pwrdm;
+ spin_lock_irqsave(&iommu_lock, flags);
+ list_add(&entry->node, &cache);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+ }
+
+ return pwrdm;
}
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst)
{
struct powerdomain *pwrdm;
- struct omap_device *od;
u8 next_pwrst;
int ret = 0;
- od = to_omap_device(pdev);
- if (!od)
- return -ENODEV;
-
- if (od->hwmods_cnt != 1)
- return -EINVAL;
-
- pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]);
+ pwrdm = _get_pwrdm(&pdev->dev);
if (!pwrdm)
- return -EINVAL;
+ return -ENODEV;
if (request) {
*pwrst = pwrdm_read_next_pwrst(pwrdm);
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 2/3] ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879
From: Tero Kristo @ 2019-08-07 9:44 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <1565171081-7899-1-git-send-email-t-kristo@ti.com>
From: Suman Anna <s-anna@ti.com>
Errata Title:
i879: DSP MStandby requires CD_EMU in SW_WKUP
Description:
The DSP requires the internal emulation clock to be actively toggling
in order to successfully enter a low power mode via execution of the
IDLE instruction and PRCM MStandby/Idle handshake. This assumes that
other prerequisites and software sequence are followed.
Workaround:
The emulation clock to the DSP is free-running anytime CCS is connected
via JTAG debugger to the DSP subsystem or when the CD_EMU clock domain
is set in SW_WKUP mode. The CD_EMU domain can be set in SW_WKUP mode
via the CM_EMU_CLKSTCTRL [1:0]CLKTRCTRL field.
Implementation:
This patch implements this workaround by denying the HW_AUTO mode
for the EMU clockdomain during the power-up of any DSP processor
and re-enabling the HW_AUTO mode during the shutdown of the last
DSP processor (actually done during the enabling and disabling of
the respective DSP MDMA MMUs). Reference counting has to be used to
manage the independent sequencing between the multiple DSP processors.
This switching is done at runtime rather than a static clockdomain
flags value to meet the target power domain state for the EMU power
domain during suspend.
Note that the DSP MStandby behavior is not consistent across all
boards prior to this fix. Please see commit 45f871eec6c0 ("ARM:
OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs") for
details.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm/mach-omap2/omap-iommu.c | 43 +++++++++++++++++++++++++++++++++++++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 1392a5b..8f6b6b8 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -19,14 +19,43 @@
#include "omap_hwmod.h"
#include "omap_device.h"
+#include "clockdomain.h"
#include "powerdomain.h"
+static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
+ bool enable)
+{
+ static struct clockdomain *emu_clkdm;
+ static DEFINE_SPINLOCK(emu_lock);
+ static atomic_t count;
+ struct device_node *np = pdev->dev.of_node;
+
+ if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
+ return;
+
+ if (!emu_clkdm) {
+ emu_clkdm = clkdm_lookup("emu_clkdm");
+ if (WARN_ON_ONCE(!emu_clkdm))
+ return;
+ }
+
+ spin_lock(&emu_lock);
+
+ if (enable && (atomic_inc_return(&count) == 1))
+ clkdm_deny_idle(emu_clkdm);
+ else if (!enable && (atomic_dec_return(&count) == 0))
+ clkdm_allow_idle(emu_clkdm);
+
+ spin_unlock(&emu_lock);
+}
+
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst)
{
struct powerdomain *pwrdm;
struct omap_device *od;
u8 next_pwrst;
+ int ret = 0;
od = to_omap_device(pdev);
if (!od)
@@ -39,13 +68,21 @@ int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
if (!pwrdm)
return -EINVAL;
- if (request)
+ if (request) {
*pwrst = pwrdm_read_next_pwrst(pwrdm);
+ omap_iommu_dra7_emu_swsup_config(pdev, true);
+ }
if (*pwrst > PWRDM_POWER_RET)
- return 0;
+ goto out;
next_pwrst = request ? PWRDM_POWER_ON : *pwrst;
- return pwrdm_set_next_pwrst(pwrdm, next_pwrst);
+ ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst);
+
+out:
+ if (!request)
+ omap_iommu_dra7_emu_swsup_config(pdev, false);
+
+ return ret;
}
--
1.9.1
--
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_______________________________________________
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^ permalink raw reply related
* [PATCH 1/3] ARM: OMAP4+: remove pdata quirks for omap4+ iommus
From: Tero Kristo @ 2019-08-07 9:44 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <1565171081-7899-1-git-send-email-t-kristo@ti.com>
IOMMU driver will be using ti-sysc bus driver for power management control
going forward, and the pdata quirks are not needed for anything anymore.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/mach-omap2/pdata-quirks.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6c6f8fc..58fb0de 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -419,14 +419,6 @@ static void __init omap3_pandora_legacy_init(void)
}
#endif /* CONFIG_ARCH_OMAP3 */
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-static struct iommu_platform_data omap4_iommu_pdata = {
- .reset_name = "mmu_cache",
- .assert_reset = omap_device_assert_hardreset,
- .deassert_reset = omap_device_deassert_hardreset,
-};
-#endif
-
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static struct wkup_m3_platform_data wkup_m3_data = {
.reset_name = "wkup_m3",
@@ -642,10 +634,6 @@ static void __init omap3_mcbsp_init(void) {}
&wkup_m3_data),
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
- OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
- &omap4_iommu_pdata),
- OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
- &omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000,
"4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]),
OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000,
--
1.9.1
--
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* [PATCH 0/3] ARM: OMAP2+: pdata quirk fixes for OMAP IOMMUs
From: Tero Kristo @ 2019-08-07 9:44 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
Hi,
A few quick fixes for OMAP IOMMU pdata quirks. These basically apply
one errata for remoteprocs, and also convert the support of iommus
to ti-sysc from hwmod for omap4+ devices.
-Tero
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* Re: [PATCH] arm64: mm: add missing PTE_SPECIAL in pte_mkdevmap on arm64
From: Catalin Marinas @ 2019-08-07 9:24 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Jia He, Anshuman Khandual, Christoffer Dall,
linux-kernel, Jun Yao, James Morse, Punit Agrawal, Qian Cai,
Thomas Gleixner, Robin Murphy, Alex Van Brunt, linux-arm-kernel
In-Reply-To: <20190807090929.zsiupxyqop75uzkn@willie-the-truck>
On Wed, Aug 07, 2019 at 10:09:29AM +0100, Will Deacon wrote:
> On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> > index 5fdcfe237338..e09760ece844 100644
> > --- a/arch/arm64/include/asm/pgtable.h
> > +++ b/arch/arm64/include/asm/pgtable.h
> > @@ -209,7 +209,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd)
> >
> > static inline pte_t pte_mkdevmap(pte_t pte)
> > {
> > - return set_pte_bit(pte, __pgprot(PTE_DEVMAP));
> > + return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
> > }
> >
> > static inline void set_pte(pte_t *ptep, pte_t pte)
> > @@ -396,7 +396,10 @@ static inline int pmd_protnone(pmd_t pmd)
> > #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> > #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
> > #endif
> > -#define pmd_mkdevmap(pmd) pte_pmd(pte_mkdevmap(pmd_pte(pmd)))
> > +static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > +{
> > + return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
> > +}
> >
> > #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
> > #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
>
> Acked-by: Will Deacon <will@kernel.org>
>
> I think Catalin can take this as a fix, although the commit message should
> probably be trimmed down a bit to remove the two call traces etc.
I'll queue this for -rc4 and sort out the commit message. Thanks.
--
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* RE: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
From: Peng Fan @ 2019-08-07 9:23 UTC (permalink / raw)
To: Sudeep Holla, linux-arm-kernel@lists.infradead.org
Cc: aidapala@qti.qualcomm.com, Etienne Carriere, Souvik Chakravarty,
wesleys@xilinx.com, Ionela Voinescu, linux-kernel@vger.kernel.org,
Saeed Nowshadi, Quentin Perret, Bo Zhang, Felix Burton,
Jim Quinlan, Chris Redpath, pajay@qti.qualcomm.com, Gaku Inami,
Volodymyr Babchuk
In-Reply-To: <20190806170208.6787-2-sudeep.holla@arm.com>
> Subject: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0
> performance fastchannels
>
> SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional
> channel that is dedicated to a single SCMI message type for controlling a
> specific platform resource. They do not use a message header as they are
> specialized for a single message.
>
> Only PERFORMANCE_LIMITS_{SET,GET} and
> PERFORMANCE_LEVEL_{SET,GET} commands are supported over
> fastchannels. As they are optional, they need to be discovered by
> PERFORMANCE_DESCRIBE_FASTCHANNEL command.
> Further {LIMIT,LEVEL}_SET commands can have optional doorbell support.
>
> Add support for discovery of these fastchannels.
>
> Cc: Ionela Voinescu <Ionela.Voinescu@arm.com>
> Cc: Chris Redpath <Chris.Redpath@arm.com>
> Cc: Quentin Perret <Quentin.Perret@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> drivers/firmware/arm_scmi/perf.c | 153
> ++++++++++++++++++++++++++++++-
> 1 file changed, 149 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/firmware/arm_scmi/perf.c
> b/drivers/firmware/arm_scmi/perf.c
> index 3c8ae7cc35de..6cce3e82e81e 100644
> --- a/drivers/firmware/arm_scmi/perf.c
> +++ b/drivers/firmware/arm_scmi/perf.c
> @@ -5,7 +5,9 @@
> * Copyright (C) 2018 ARM Ltd.
> */
>
> +#include <linux/bits.h>
> #include <linux/of.h>
> +#include <linux/io.h>
> #include <linux/platform_device.h>
> #include <linux/pm_opp.h>
> #include <linux/sort.h>
> @@ -21,6 +23,7 @@ enum scmi_performance_protocol_cmd {
> PERF_LEVEL_GET = 0x8,
> PERF_NOTIFY_LIMITS = 0x9,
> PERF_NOTIFY_LEVEL = 0xa,
> + PERF_DESCRIBE_FASTCHANNEL = 0xb,
> };
>
> struct scmi_opp {
> @@ -44,6 +47,7 @@ struct scmi_msg_resp_perf_domain_attributes {
> #define SUPPORTS_SET_PERF_LVL(x) ((x) & BIT(30))
> #define SUPPORTS_PERF_LIMIT_NOTIFY(x) ((x) & BIT(29))
> #define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28))
> +#define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27))
> __le32 rate_limit_us;
> __le32 sustained_freq_khz;
> __le32 sustained_perf_level;
> @@ -87,17 +91,56 @@ struct scmi_msg_resp_perf_describe_levels {
> } opp[0];
> };
>
> +struct scmi_perf_get_fc_info {
> + __le32 domain;
> + __le32 message_id;
> +};
> +
> +struct scmi_msg_resp_perf_desc_fc {
> + __le32 attr;
> +#define SUPPORTS_DOORBELL(x) ((x) & BIT(0))
> +#define DOORBELL_REG_WIDTH(x) FIELD_GET(GENMASK(2, 1), (x))
> + __le32 rate_limit;
> + __le32 chan_addr_low;
> + __le32 chan_addr_high;
> + __le32 chan_size;
> + __le32 db_addr_low;
> + __le32 db_addr_high;
> + __le32 db_set_lmask;
> + __le32 db_set_hmask;
> + __le32 db_preserve_lmask;
> + __le32 db_preserve_hmask;
> +};
> +
> +struct scmi_fc_db_info {
> + int width;
> + u64 set;
> + u64 mask;
> + void __iomem *addr;
> +};
> +
> +struct scmi_fc_info {
> + void __iomem *level_set_addr;
> + void __iomem *limit_set_addr;
> + void __iomem *level_get_addr;
> + void __iomem *limit_get_addr;
> + struct scmi_fc_db_info *level_set_db;
> + struct scmi_fc_db_info *limit_set_db;
> +};
> +
> struct perf_dom_info {
> bool set_limits;
> bool set_perf;
> bool perf_limit_notify;
> bool perf_level_notify;
> + bool perf_fastchannels;
> u32 opp_count;
> u32 sustained_freq_khz;
> u32 sustained_perf_level;
> u32 mult_factor;
> char name[SCMI_MAX_STR_SIZE];
> struct scmi_opp opp[MAX_OPPS];
> + struct scmi_fc_info *fc_info;
> };
>
> struct scmi_perf_info {
> @@ -162,6 +205,7 @@ scmi_perf_domain_attributes_get(const struct
> scmi_handle *handle, u32 domain,
> dom_info->set_perf = SUPPORTS_SET_PERF_LVL(flags);
> dom_info->perf_limit_notify =
> SUPPORTS_PERF_LIMIT_NOTIFY(flags);
> dom_info->perf_level_notify =
> SUPPORTS_PERF_LEVEL_NOTIFY(flags);
> + dom_info->perf_fastchannels =
> SUPPORTS_PERF_FASTCHANNELS(flags);
> dom_info->sustained_freq_khz =
> le32_to_cpu(attr->sustained_freq_khz);
> dom_info->sustained_perf_level =
> @@ -250,7 +294,7 @@ scmi_perf_describe_levels_get(const struct
> scmi_handle *handle, u32 domain, }
>
> static int scmi_perf_limits_set(const struct scmi_handle *handle, u32
> domain,
> - u32 max_perf, u32 min_perf)
> + u32 max_perf, u32 min_perf)
> {
> int ret;
> struct scmi_xfer *t;
> @@ -273,7 +317,7 @@ static int scmi_perf_limits_set(const struct
> scmi_handle *handle, u32 domain, }
>
> static int scmi_perf_limits_get(const struct scmi_handle *handle, u32
> domain,
> - u32 *max_perf, u32 *min_perf)
> + u32 *max_perf, u32 *min_perf)
> {
> int ret;
> struct scmi_xfer *t;
> @@ -299,7 +343,7 @@ static int scmi_perf_limits_get(const struct
> scmi_handle *handle, u32 domain, }
>
> static int scmi_perf_level_set(const struct scmi_handle *handle, u32
> domain,
> - u32 level, bool poll)
> + u32 level, bool poll)
> {
> int ret;
> struct scmi_xfer *t;
> @@ -322,7 +366,7 @@ static int scmi_perf_level_set(const struct
> scmi_handle *handle, u32 domain, }
>
> static int scmi_perf_level_get(const struct scmi_handle *handle, u32
> domain,
> - u32 *level, bool poll)
> + u32 *level, bool poll)
> {
> int ret;
> struct scmi_xfer *t;
> @@ -343,6 +387,104 @@ static int scmi_perf_level_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> +static bool scmi_perf_fc_size_is_valid(u32 msg, u32 size) {
> + if ((msg == PERF_LEVEL_GET || msg == PERF_LEVEL_SET) && size == 4)
> + return true;
> + if ((msg == PERF_LIMITS_GET || msg == PERF_LIMITS_SET) && size == 8)
> + return true;
> + return false;
> +}
> +
> +static void
> +scmi_perf_domain_desc_fc(const struct scmi_handle *handle, u32 domain,
> + u32 message_id, void __iomem **p_addr,
> + struct scmi_fc_db_info **p_db)
> +{
> + int ret;
> + u32 flags;
> + u64 phys_addr;
> + u8 size;
> + void __iomem *addr;
> + struct scmi_xfer *t;
> + struct scmi_fc_db_info *db;
> + struct scmi_perf_get_fc_info *info;
> + struct scmi_msg_resp_perf_desc_fc *resp;
> +
> + if (!p_addr)
> + return;
> +
> + ret = scmi_xfer_get_init(handle, PERF_DESCRIBE_FASTCHANNEL,
> + SCMI_PROTOCOL_PERF,
> + sizeof(*info), sizeof(*resp), &t);
> + if (ret)
> + return;
> +
> + info = t->tx.buf;
> + info->domain = cpu_to_le32(domain);
> + info->message_id = cpu_to_le32(message_id);
> +
> + ret = scmi_do_xfer(handle, t);
> + if (ret)
> + goto err_xfer;
> +
> + resp = t->rx.buf;
> + flags = le32_to_cpu(resp->attr);
> + size = le32_to_cpu(resp->chan_size);
> + if (!scmi_perf_fc_size_is_valid(message_id, size))
> + goto err_xfer;
> +
> + phys_addr = le32_to_cpu(resp->chan_addr_low);
> + phys_addr |= (u64)le32_to_cpu(resp->chan_addr_high) << 32;
> + addr = devm_ioremap(handle->dev, phys_addr, size);
> + if (!addr)
> + goto err_xfer;
> + *p_addr = addr;
> +
> + if (p_db && SUPPORTS_DOORBELL(flags)) {
> + db = devm_kzalloc(handle->dev, sizeof(*db), GFP_KERNEL);
> + if (!db)
> + goto err_xfer;
> +
> + size = 1 << DOORBELL_REG_WIDTH(flags);
> + phys_addr = le32_to_cpu(resp->db_addr_low);
> + phys_addr |= (u64)le32_to_cpu(resp->db_addr_high) << 32;
> + addr = devm_ioremap(handle->dev, phys_addr, size);
> + if (!addr)
> + goto err_xfer;
> +
> + db->addr = addr;
> + db->width = size;
> + db->set = le32_to_cpu(resp->db_set_lmask);
> + db->set |= (u64)le32_to_cpu(resp->db_set_hmask) << 32;
> + db->mask = le32_to_cpu(resp->db_preserve_lmask);
> + db->mask |= (u64)le32_to_cpu(resp->db_preserve_hmask) << 32;
> + *p_db = db;
> + }
> +err_xfer:
> + scmi_xfer_put(handle, t);
> +}
> +
> +static void scmi_perf_domain_init_fc(const struct scmi_handle *handle,
> + u32 domain, struct scmi_fc_info **p_fc) {
> + struct scmi_fc_info *fc;
> +
> + fc = devm_kzalloc(handle->dev, sizeof(*fc), GFP_KERNEL);
> + if (!fc)
> + return;
> +
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_SET,
> + &fc->level_set_addr, &fc->level_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_GET,
> + &fc->level_get_addr, NULL);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_SET,
> + &fc->limit_set_addr, &fc->limit_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_GET,
> + &fc->limit_get_addr, NULL);
> + *p_fc = fc;
> +}
> +
> /* Device specific ops */
> static int scmi_dev_domain_id(struct device *dev) { @@ -494,6 +636,9
> @@ static int scmi_perf_protocol_init(struct scmi_handle *handle)
>
> scmi_perf_domain_attributes_get(handle, domain, dom);
> scmi_perf_describe_levels_get(handle, domain, dom);
> +
> + if (dom->perf_fastchannels)
> + scmi_perf_domain_init_fc(handle, domain, &dom->fc_info);
> }
>
> handle->perf_ops = &perf_ops;
Reviewed-by: Peng Fan <peng.fan@nxp.com>
> --
> 2.17.1
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* Re: [PATCH] arm64: mm: add missing PTE_SPECIAL in pte_mkdevmap on arm64
From: Will Deacon @ 2019-08-07 9:09 UTC (permalink / raw)
To: Jia He
Cc: Mark Rutland, Anshuman Khandual, Catalin Marinas,
Christoffer Dall, linux-kernel, Jun Yao, Qian Cai, Punit Agrawal,
James Morse, Thomas Gleixner, Robin Murphy, Alex Van Brunt,
linux-arm-kernel
In-Reply-To: <20190807045851.10772-1-justin.he@arm.com>
On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 5fdcfe237338..e09760ece844 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -209,7 +209,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd)
>
> static inline pte_t pte_mkdevmap(pte_t pte)
> {
> - return set_pte_bit(pte, __pgprot(PTE_DEVMAP));
> + return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
> }
>
> static inline void set_pte(pte_t *ptep, pte_t pte)
> @@ -396,7 +396,10 @@ static inline int pmd_protnone(pmd_t pmd)
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
> #endif
> -#define pmd_mkdevmap(pmd) pte_pmd(pte_mkdevmap(pmd_pte(pmd)))
> +static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> +{
> + return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
> +}
>
> #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
> #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
Acked-by: Will Deacon <will@kernel.org>
I think Catalin can take this as a fix, although the commit message should
probably be trimmed down a bit to remove the two call traces etc.
Will
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* Re: [PATCH] cpufreq: mediatek-cpufreq: Add compatible for MT8516
From: Viresh Kumar @ 2019-08-07 9:05 UTC (permalink / raw)
To: Fabien Parent
Cc: linux-pm, rjw, linux-kernel, linux-mediatek, matthias.bgg,
linux-arm-kernel
In-Reply-To: <20190806095029.4758-1-fparent@baylibre.com>
On 06-08-19, 11:50, Fabien Parent wrote:
> Add the compatible for MT8516 in order to take advantage of the
> MediaTek CPUFreq driver for Mediatek's MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index f14f3a85f2f7..10bc06f5dd45 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -535,6 +535,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
> { .compatible = "mediatek,mt817x", },
> { .compatible = "mediatek,mt8173", },
> { .compatible = "mediatek,mt8176", },
> + { .compatible = "mediatek,mt8516", },
>
> { }
> };
Applied. Thanks.
--
viresh
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* [PATCH] ARM: debug-ll: Add support for r7s9210
From: Geert Uytterhoeven @ 2019-08-07 8:54 UTC (permalink / raw)
To: Russell King, Simon Horman, Magnus Damm
Cc: linux-renesas-soc, Chris Brandt, Geert Uytterhoeven,
linux-arm-kernel
Enable low-level debugging support for RZ/A2M (r7s9210).
The RZA2MEVB board uses either SCIF2 (SDRAM enabled) or SCIF4 (HyperRAM
only) for the serial console.
Note that "SCIFA" serial ports on RZ/A2 SoCs use a compressed register
layout, hence add support for that to renesas-scif.S.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/Kconfig.debug | 20 +++++++++++++++++++-
arch/arm/include/debug/renesas-scif.S | 6 +++++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 85710e078afb4878..9fe038aecc553deb 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -924,6 +924,20 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas RZ/A1H (R7S72100).
+ config DEBUG_R7S9210_SCIF2
+ bool "Kernel low-level debugging messages via SCIF2 on R7S9210"
+ depends on ARCH_R7S9210
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIF2 on Renesas RZ/A2M (R7S9210).
+
+ config DEBUG_R7S9210_SCIF4
+ bool "Kernel low-level debugging messages via SCIF4 on R7S9210"
+ depends on ARCH_R7S9210
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIF4 on Renesas RZ/A2M (R7S9210).
+
config DEBUG_RCAR_GEN1_SCIF0
bool "Kernel low-level debugging messages via SCIF0 on R8A7778"
depends on ARCH_R8A7778
@@ -1537,6 +1551,8 @@ config DEBUG_LL_INCLUDE
default "debug/msm.S" if DEBUG_QCOM_UARTDM
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2
+ default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF2
+ default "debug/renesas-scif.S" if DEBUG_R7S9210_SCIF4
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
@@ -1666,7 +1682,8 @@ config DEBUG_UART_PHYS
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
- default 0xe8008000 if DEBUG_R7S72100_SCIF2
+ default 0xe8008000 if DEBUG_R7S72100_SCIF2 || DEBUG_R7S9210_SCIF2
+ default 0xe8009000 if DEBUG_R7S9210_SCIF4
default 0xf0000000 if DEBUG_DIGICOLOR_UA0
default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
@@ -1699,6 +1716,7 @@ config DEBUG_UART_PHYS
DEBUG_LL_UART_EFM32 || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
+ DEBUG_R7S9210_SCIF2 || DEBUG_R7S9210_SCIF4 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S
index 1c5f795587fc5681..25f06663a9a4e2c1 100644
--- a/arch/arm/include/debug/renesas-scif.S
+++ b/arch/arm/include/debug/renesas-scif.S
@@ -11,7 +11,11 @@
#define SCIF_PHYS CONFIG_DEBUG_UART_PHYS
#define SCIF_VIRT ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
-#if CONFIG_DEBUG_UART_PHYS < 0xe6e00000
+#if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
+/* RZ/A2 SCIFA */
+#define FTDR 0x06
+#define FSR 0x08
+#elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
/* SCIFA */
#define FTDR 0x20
#define FSR 0x14
--
2.17.1
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* Re: [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations
From: Koenig, Christian @ 2019-08-07 8:53 UTC (permalink / raw)
To: Christoph Hellwig, Zhou1, Tao
Cc: linux-arm-kernel@lists.infradead.org,
kernel-build-reports@lists.linaro.org,
amd-gfx@lists.freedesktop.org, broonie@kernel.org,
linux-next@vger.kernel.org, Deucher, Alexander,
akpm@linux-foundation.org, Li, Dennis, Zhang, Hawking
In-Reply-To: <20190807070834.GA24792@infradead.org>
Am 07.08.19 um 09:08 schrieb Christoph Hellwig:
> On Wed, Aug 07, 2019 at 10:56:40AM +0800, Tao Zhou wrote:
>> readq/writeq are not supported on all architectures
> NAK. You must not use atomic_* on __iomem (MMIO) memory.
Well then what's the right thing to do here?
Essentially writeq/readq doesn't seems to be available on all
architectures either.
Regards,
Christian.
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* Re: [PATCH v3 10/41] media/ivtv: convert put_page() to put_user_page*()
From: Hans Verkuil @ 2019-08-07 8:51 UTC (permalink / raw)
To: john.hubbard, Andrew Morton
Cc: linux-fbdev, Jan Kara, kvm, Dave Hansen, Dave Chinner, dri-devel,
linux-mm, sparclinux, Ira Weiny, ceph-devel, devel, rds-devel,
linux-rdma, x86, amd-gfx, Christoph Hellwig, Jason Gunthorpe,
xen-devel, devel, linux-media, John Hubbard, intel-gfx,
linux-block, Jérôme Glisse, linux-rpi-kernel,
Dan Williams, Mauro Carvalho Chehab, linux-arm-kernel, linux-nfs,
Andy Walls, netdev, LKML, linux-xfs, linux-crypto, linux-fsdevel
In-Reply-To: <20190807013340.9706-11-jhubbard@nvidia.com>
On 8/7/19 3:33 AM, john.hubbard@gmail.com wrote:
> From: John Hubbard <jhubbard@nvidia.com>
>
> For pages that were retained via get_user_pages*(), release those pages
> via the new put_user_page*() routines, instead of via put_page() or
> release_pages().
>
> This is part a tree-wide conversion, as described in commit fc1d8e7cca2d
> ("mm: introduce put_user_page*(), placeholder versions").
>
> Cc: Andy Walls <awalls@md.metrocast.net>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Cc: linux-media@vger.kernel.org
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Regards,
Hans
> ---
> drivers/media/pci/ivtv/ivtv-udma.c | 14 ++++----------
> drivers/media/pci/ivtv/ivtv-yuv.c | 11 +++--------
> 2 files changed, 7 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/media/pci/ivtv/ivtv-udma.c b/drivers/media/pci/ivtv/ivtv-udma.c
> index 5f8883031c9c..7c7f33c2412b 100644
> --- a/drivers/media/pci/ivtv/ivtv-udma.c
> +++ b/drivers/media/pci/ivtv/ivtv-udma.c
> @@ -92,7 +92,7 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
> {
> struct ivtv_dma_page_info user_dma;
> struct ivtv_user_dma *dma = &itv->udma;
> - int i, err;
> + int err;
>
> IVTV_DEBUG_DMA("ivtv_udma_setup, dst: 0x%08x\n", (unsigned int)ivtv_dest_addr);
>
> @@ -119,8 +119,7 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
> IVTV_DEBUG_WARN("failed to map user pages, returned %d instead of %d\n",
> err, user_dma.page_count);
> if (err >= 0) {
> - for (i = 0; i < err; i++)
> - put_page(dma->map[i]);
> + put_user_pages(dma->map, err);
> return -EINVAL;
> }
> return err;
> @@ -130,9 +129,7 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
>
> /* Fill SG List with new values */
> if (ivtv_udma_fill_sg_list(dma, &user_dma, 0) < 0) {
> - for (i = 0; i < dma->page_count; i++) {
> - put_page(dma->map[i]);
> - }
> + put_user_pages(dma->map, dma->page_count);
> dma->page_count = 0;
> return -ENOMEM;
> }
> @@ -153,7 +150,6 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr,
> void ivtv_udma_unmap(struct ivtv *itv)
> {
> struct ivtv_user_dma *dma = &itv->udma;
> - int i;
>
> IVTV_DEBUG_INFO("ivtv_unmap_user_dma\n");
>
> @@ -170,9 +166,7 @@ void ivtv_udma_unmap(struct ivtv *itv)
> ivtv_udma_sync_for_cpu(itv);
>
> /* Release User Pages */
> - for (i = 0; i < dma->page_count; i++) {
> - put_page(dma->map[i]);
> - }
> + put_user_pages(dma->map, dma->page_count);
> dma->page_count = 0;
> }
>
> diff --git a/drivers/media/pci/ivtv/ivtv-yuv.c b/drivers/media/pci/ivtv/ivtv-yuv.c
> index cd2fe2d444c0..2c61a11d391d 100644
> --- a/drivers/media/pci/ivtv/ivtv-yuv.c
> +++ b/drivers/media/pci/ivtv/ivtv-yuv.c
> @@ -30,7 +30,6 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
> struct yuv_playback_info *yi = &itv->yuv_info;
> u8 frame = yi->draw_frame;
> struct yuv_frame_info *f = &yi->new_frame_info[frame];
> - int i;
> int y_pages, uv_pages;
> unsigned long y_buffer_offset, uv_buffer_offset;
> int y_decode_height, uv_decode_height, y_size;
> @@ -81,8 +80,7 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
> uv_pages, uv_dma.page_count);
>
> if (uv_pages >= 0) {
> - for (i = 0; i < uv_pages; i++)
> - put_page(dma->map[y_pages + i]);
> + put_user_pages(&dma->map[y_pages], uv_pages);
> rc = -EFAULT;
> } else {
> rc = uv_pages;
> @@ -93,8 +91,7 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
> y_pages, y_dma.page_count);
> }
> if (y_pages >= 0) {
> - for (i = 0; i < y_pages; i++)
> - put_page(dma->map[i]);
> + put_user_pages(dma->map, y_pages);
> /*
> * Inherit the -EFAULT from rc's
> * initialization, but allow it to be
> @@ -112,9 +109,7 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma,
> /* Fill & map SG List */
> if (ivtv_udma_fill_sg_list (dma, &uv_dma, ivtv_udma_fill_sg_list (dma, &y_dma, 0)) < 0) {
> IVTV_DEBUG_WARN("could not allocate bounce buffers for highmem userspace buffers\n");
> - for (i = 0; i < dma->page_count; i++) {
> - put_page(dma->map[i]);
> - }
> + put_user_pages(dma->map, dma->page_count);
> dma->page_count = 0;
> return -ENOMEM;
> }
>
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