* [PATCH v2 00/13] v2: ARM: move lpc32xx to multiplatform
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: linux-watchdog, Arnd Bergmann, Greg Kroah-Hartman, Linus Walleij,
linux-usb, linux-kernel, Vladimir Zapolskiy, linux-gpio, netdev,
Alan Stern, Guenter Roeck, linux-serial, Sylvain Lemieux,
David S. Miller, linux-arm-kernel
Version 2 contains some minor changes based on earlier feedback
and from the 0day build bot testing on other architectures. The
only patch that changed significantly is the one for the gpio driver.
I would suggest we merge this version into the soc tree directly
if there are no further concerns.
Arnd
Arnd Bergmann (12):
usb: ohci-nxp: enable compile-testing
usb: udc: lpc32xx: allow compile-testing
watchdog: pnx4008_wdt: allow compile-testing
serial: lpc32xx_hs: allow compile-testing
gpio: lpc32xx: allow building on non-lpc32xx targets
net: lpc-enet: factor out iram access
net: lpc-enet: move phy setup into platform code
net: lpc-enet: fix printk format strings
net: lpc-enet: allow compile testing
serial: lpc32xx: allow compile testing
ARM: lpc32xx: clean up header files
ARM: lpc32xx: allow multiplatform build
kbuild test robot (1):
net: lpc-enet: fix badzero.cocci warnings
arch/arm/Kconfig | 17 +--
arch/arm/configs/lpc32xx_defconfig | 2 +
arch/arm/mach-lpc32xx/Kconfig | 11 ++
arch/arm/mach-lpc32xx/common.c | 24 +++-
arch/arm/mach-lpc32xx/common.h | 1 -
arch/arm/mach-lpc32xx/include/mach/board.h | 15 ---
.../mach-lpc32xx/include/mach/entry-macro.S | 28 -----
arch/arm/mach-lpc32xx/include/mach/hardware.h | 25 ----
.../mach-lpc32xx/include/mach/uncompress.h | 50 --------
.../{include/mach/platform.h => lpc32xx.h} | 18 ++-
arch/arm/mach-lpc32xx/pm.c | 3 +-
arch/arm/mach-lpc32xx/serial.c | 33 ++++-
arch/arm/mach-lpc32xx/suspend.S | 3 +-
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile | 2 +-
drivers/gpio/gpio-lpc32xx.c | 118 ++++++++++--------
drivers/net/ethernet/nxp/Kconfig | 2 +-
drivers/net/ethernet/nxp/lpc_eth.c | 45 +++----
drivers/tty/serial/Kconfig | 3 +-
drivers/tty/serial/lpc32xx_hs.c | 37 +-----
drivers/usb/gadget/udc/Kconfig | 3 +-
drivers/usb/gadget/udc/lpc32xx_udc.c | 3 +-
drivers/usb/host/Kconfig | 3 +-
drivers/usb/host/ohci-nxp.c | 25 ++--
drivers/watchdog/Kconfig | 2 +-
drivers/watchdog/pnx4008_wdt.c | 1 -
include/linux/soc/nxp/lpc32xx-misc.h | 33 +++++
27 files changed, 242 insertions(+), 272 deletions(-)
create mode 100644 arch/arm/mach-lpc32xx/Kconfig
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/hardware.h
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/uncompress.h
rename arch/arm/mach-lpc32xx/{include/mach/platform.h => lpc32xx.h} (98%)
create mode 100644 include/linux/soc/nxp/lpc32xx-misc.h
--
2.20.0
Cc: soc@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-gpio@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-usb@vger.kernel.org
Cc: linux-watchdog@vger.kernel.org
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 01/13] usb: ohci-nxp: enable compile-testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Felipe Balbi, Arnd Bergmann, Greg Kroah-Hartman, linux-usb,
linux-kernel, Vladimir Zapolskiy, Alan Stern, Sylvain Lemieux,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The driver hardcodes a hardware I/O address the way one should
generally not do, and this prevents both compile-testing, and
moving the platform to CONFIG_ARCH_MULTIPLATFORM.
Change the code to be independent of the machine headers
to allow those two. Removing the hardcoded address would
be hard and is not necessary, so leave that in place for now.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/usb/host/Kconfig | 3 ++-
drivers/usb/host/ohci-nxp.c | 25 ++++++++++++++++++-------
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 40b5de597112..73d233d3bf4d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -441,7 +441,8 @@ config USB_OHCI_HCD_S3C2410
config USB_OHCI_HCD_LPC32XX
tristate "Support for LPC on-chip OHCI USB controller"
- depends on USB_OHCI_HCD && ARCH_LPC32XX
+ depends on USB_OHCI_HCD
+ depends on ARCH_LPC32XX || COMPILE_TEST
depends on USB_ISP1301
default y
---help---
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index f5f532601092..c561881d0e79 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -29,10 +29,7 @@
#include "ohci.h"
-#include <mach/hardware.h>
-
#define USB_CONFIG_BASE 0x31020000
-#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110)
/* USB_OTG_STAT_CONTROL bit defines */
#define TRANSPARENT_I2C_EN (1 << 7)
@@ -122,19 +119,33 @@ static inline void isp1301_vbus_off(void)
static void ohci_nxp_start_hc(void)
{
- unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
+ void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
+ unsigned long tmp;
+
+ if (WARN_ON(!usb_otg_stat_control))
+ return;
+
+ tmp = __raw_readl(usb_otg_stat_control) | HOST_EN;
- __raw_writel(tmp, USB_OTG_STAT_CONTROL);
+ __raw_writel(tmp, usb_otg_stat_control);
isp1301_vbus_on();
+
+ iounmap(usb_otg_stat_control);
}
static void ohci_nxp_stop_hc(void)
{
+ void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4);
unsigned long tmp;
+ if (WARN_ON(!usb_otg_stat_control))
+ return;
+
isp1301_vbus_off();
- tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
- __raw_writel(tmp, USB_OTG_STAT_CONTROL);
+ tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN;
+ __raw_writel(tmp, usb_otg_stat_control);
+
+ iounmap(usb_otg_stat_control);
}
static int ohci_hcd_nxp_probe(struct platform_device *pdev)
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 02/13] usb: udc: lpc32xx: allow compile-testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Felipe Balbi, Alexandre Belloni, Arnd Bergmann,
Greg Kroah-Hartman, linux-usb, linux-kernel, Vladimir Zapolskiy,
Sylvain Lemieux, linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The only thing that prevents building this driver on other
platforms is the mach/hardware.h include, which is not actually
used here at all, so remove the line and allow CONFIG_COMPILE_TEST.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/usb/gadget/udc/Kconfig | 3 ++-
drivers/usb/gadget/udc/lpc32xx_udc.c | 3 +--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig
index ef0259a950ba..d354036ff6c8 100644
--- a/drivers/usb/gadget/udc/Kconfig
+++ b/drivers/usb/gadget/udc/Kconfig
@@ -45,7 +45,8 @@ config USB_AT91
config USB_LPC32XX
tristate "LPC32XX USB Peripheral Controller"
- depends on ARCH_LPC32XX && I2C
+ depends on ARCH_LPC32XX || COMPILE_TEST
+ depends on I2C
select USB_ISP1301
help
This option selects the USB device controller in the LPC32xx SoC.
diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c
index 5f1b14f3e5a0..defe04d52e6d 100644
--- a/drivers/usb/gadget/udc/lpc32xx_udc.c
+++ b/drivers/usb/gadget/udc/lpc32xx_udc.c
@@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/prefetch.h>
#include <linux/proc_fs.h>
#include <linux/slab.h>
#include <linux/usb/ch9.h>
@@ -35,8 +36,6 @@
#include <linux/seq_file.h>
#endif
-#include <mach/hardware.h>
-
/*
* USB device configuration structure
*/
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 03/13] watchdog: pnx4008_wdt: allow compile-testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: linux-watchdog, Arnd Bergmann, linux-kernel, Vladimir Zapolskiy,
linux-arm-kernel, Sylvain Lemieux, Wim Van Sebroeck,
Guenter Roeck
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The only thing that prevents building this driver on other
platforms is the mach/hardware.h include, which is not actually
used here at all, so remove the line and allow CONFIG_COMPILE_TEST.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/watchdog/Kconfig | 2 +-
drivers/watchdog/pnx4008_wdt.c | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 8188963a405b..a45f9e3e442b 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -551,7 +551,7 @@ config OMAP_WATCHDOG
config PNX4008_WATCHDOG
tristate "LPC32XX Watchdog"
- depends on ARCH_LPC32XX
+ depends on ARCH_LPC32XX || COMPILE_TEST
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c
index 7b446b696f2b..e0ea133c1690 100644
--- a/drivers/watchdog/pnx4008_wdt.c
+++ b/drivers/watchdog/pnx4008_wdt.c
@@ -30,7 +30,6 @@
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/reboot.h>
-#include <mach/hardware.h>
/* WatchDog Timer - Chapter 23 Page 207 */
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 04/13] serial: lpc32xx_hs: allow compile-testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Greg Kroah-Hartman, Jiri Slaby, linux-kernel,
Vladimir Zapolskiy, linux-serial, Sylvain Lemieux,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The only thing that prevents building this driver on other
platforms is the mach/hardware.h include, which is not actually
used here at all, so remove the line and allow CONFIG_COMPILE_TEST.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/tty/serial/Kconfig | 3 ++-
drivers/tty/serial/lpc32xx_hs.c | 2 --
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 3083dbae35f7..518aac902e4b 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -739,7 +739,8 @@ config SERIAL_PNX8XXX_CONSOLE
config SERIAL_HS_LPC32XX
tristate "LPC32XX high speed serial port support"
- depends on ARCH_LPC32XX && OF
+ depends on ARCH_LPC32XX || COMPILE_TEST
+ depends on OF
select SERIAL_CORE
help
Support for the LPC32XX high speed serial ports (up to 900kbps).
diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c
index f4e27d0ad947..7f14cd8fac47 100644
--- a/drivers/tty/serial/lpc32xx_hs.c
+++ b/drivers/tty/serial/lpc32xx_hs.c
@@ -25,8 +25,6 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/of.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
/*
* High Speed UART register offsets
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, linux-gpio, Linus Walleij, linux-kernel,
Vladimir Zapolskiy, Bartosz Golaszewski, Sylvain Lemieux,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The driver uses hardwire MMIO addresses instead of the data
that is passed in device tree. Change it over to only
hardcode the register offset values and allow compile-testing.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/configs/lpc32xx_defconfig | 1 +
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile | 2 +-
drivers/gpio/gpio-lpc32xx.c | 118 +++++++++++++++++------------
4 files changed, 77 insertions(+), 51 deletions(-)
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 0cdc6c7974b3..3772d5a8975a 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -93,6 +93,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_PNX=y
+CONFIG_GPIO_LPC32XX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index bb13c266c329..8b40a578963c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -311,6 +311,13 @@ config GPIO_LPC18XX
Select this option to enable GPIO driver for
NXP LPC18XX/43XX devices.
+config GPIO_LPC32XX
+ tristate "NXP LPC32XX GPIO support"
+ depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST)
+ help
+ Select this option to enable GPIO driver for
+ NXP LPC32XX devices.
+
config GPIO_LYNXPOINT
tristate "Intel Lynxpoint GPIO support"
depends on ACPI && X86
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index a4e91175c708..87d659ae95eb 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o
obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o
obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o
obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o
-obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o
+obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o
obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o
obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o
obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
index 24885b3db3d5..4e626c4235c2 100644
--- a/drivers/gpio/gpio-lpc32xx.c
+++ b/drivers/gpio/gpio-lpc32xx.c
@@ -16,36 +16,33 @@
#include <linux/platform_device.h>
#include <linux/module.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
-#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
-#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
-#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
-#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
-#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
-#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
-#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
-#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
-#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
-#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
-#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
-#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
-#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
-#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
-#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
-#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
-#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
-#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
-#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
-#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
-#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
-#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
-#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
-#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
-#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
+#define LPC32XX_GPIO_P3_INP_STATE (0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET (0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
+#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
+#define LPC32XX_GPIO_P2_MUX_SET (0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
+#define LPC32XX_GPIO_P0_INP_STATE (0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET (0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
+#define LPC32XX_GPIO_P1_INP_STATE (0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET (0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
#define GPIO012_PIN_TO_BIT(x) (1 << (x))
#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
@@ -72,12 +69,12 @@
#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
struct gpio_regs {
- void __iomem *inp_state;
- void __iomem *outp_state;
- void __iomem *outp_set;
- void __iomem *outp_clr;
- void __iomem *dir_set;
- void __iomem *dir_clr;
+ unsigned long inp_state;
+ unsigned long outp_state;
+ unsigned long outp_set;
+ unsigned long outp_clr;
+ unsigned long dir_set;
+ unsigned long dir_clr;
};
/*
@@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = {
struct lpc32xx_gpio_chip {
struct gpio_chip chip;
struct gpio_regs *gpio_grp;
+ void __iomem *reg_base;
};
+static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
+{
+ return __raw_readl(group->reg_base + offset);
+}
+
+static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
+{
+ __raw_writel(val, group->reg_base + offset);
+}
+
static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int input)
{
if (input)
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_clr);
else
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->dir_set);
}
@@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (input)
- __raw_writel(u, group->gpio_grp->dir_clr);
+ gpreg_write(group, u, group->gpio_grp->dir_clr);
else
- __raw_writel(u, group->gpio_grp->dir_set);
+ gpreg_write(group, u, group->gpio_grp->dir_set);
}
static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_set);
else
- __raw_writel(GPIO012_PIN_TO_BIT(pin),
+ gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
group->gpio_grp->outp_clr);
}
@@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
u32 u = GPIO3_PIN_TO_BIT(pin);
if (high)
- __raw_writel(u, group->gpio_grp->outp_set);
+ gpreg_write(group, u, group->gpio_grp->outp_set);
else
- __raw_writel(u, group->gpio_grp->outp_clr);
+ gpreg_write(group, u, group->gpio_grp->outp_clr);
}
static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
unsigned pin, int high)
{
if (high)
- __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
else
- __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
+ gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
}
static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
+ return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
pin);
}
static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- int state = __raw_readl(group->gpio_grp->inp_state);
+ int state = gpreg_read(group, group->gpio_grp->inp_state);
/*
* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
@@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
+ return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
}
static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
unsigned pin)
{
- return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
+ return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
}
/*
@@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc,
static int lpc32xx_gpio_probe(struct platform_device *pdev)
{
int i;
+ void __iomem *reg_base;
+
+ reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg_base))
+ return PTR_ERR(reg_base);
for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
if (pdev->dev.of_node) {
lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
+ lpc32xx_gpiochip[i].reg_base = reg_base;
}
devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
&lpc32xx_gpiochip[i]);
@@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = {
};
module_platform_driver(lpc32xx_gpio_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 06/13] net: lpc-enet: factor out iram access
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, netdev, linux-kernel, Vladimir Zapolskiy,
Sylvain Lemieux, David S. Miller, linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The lpc_eth driver uses a platform specific method to find
the internal sram. This prevents building it on other machines.
Rework to only use one function call and keep the other platform
internals where they belong. Ideally this would look up the
sram location from DT, but as this is a rarely used driver,
I want to keep the modifications to a minimum.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-lpc32xx/common.c | 9 ++++++--
arch/arm/mach-lpc32xx/common.h | 1 -
arch/arm/mach-lpc32xx/include/mach/board.h | 15 --------------
drivers/net/ethernet/nxp/lpc_eth.c | 17 ++++++++-------
include/linux/soc/nxp/lpc32xx-misc.h | 24 ++++++++++++++++++++++
5 files changed, 39 insertions(+), 27 deletions(-)
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h
create mode 100644 include/linux/soc/nxp/lpc32xx-misc.h
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 5b71b4fab2cd..f648324d5fb4 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -8,6 +8,7 @@
*/
#include <linux/init.h>
+#include <linux/soc/nxp/lpc32xx-misc.h>
#include <asm/mach/map.h>
#include <asm/system_info.h>
@@ -32,7 +33,7 @@ void lpc32xx_get_uid(u32 devid[4])
*/
#define LPC32XX_IRAM_BANK_SIZE SZ_128K
static u32 iram_size;
-u32 lpc32xx_return_iram_size(void)
+u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
{
if (iram_size == 0) {
u32 savedval1, savedval2;
@@ -53,10 +54,14 @@ u32 lpc32xx_return_iram_size(void)
} else
iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
}
+ if (dmaaddr)
+ *dmaaddr = LPC32XX_IRAM_BASE;
+ if (mapbase)
+ *mapbase = io_p2v(LPC32XX_IRAM_BASE);
return iram_size;
}
-EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
+EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
static struct map_desc lpc32xx_io_desc[] __initdata = {
{
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 8e597ce48a73..32f0ad217807 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -23,7 +23,6 @@ extern void __init lpc32xx_serial_init(void);
*/
extern void lpc32xx_get_uid(u32 devid[4]);
-extern u32 lpc32xx_return_iram_size(void);
/*
* Pointers used for sizing and copying suspend function data
*/
diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h
deleted file mode 100644
index 476513d970a4..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/board.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arm/arch/mach-lpc32xx/include/mach/board.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-extern u32 lpc32xx_return_iram_size(void);
-
-#endif /* __ASM_ARCH_BOARD_H */
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index f7e11f1b0426..bcdd0adcfb0c 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -18,8 +18,8 @@
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
+#include <linux/soc/nxp/lpc32xx-misc.h>
-#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -1311,16 +1311,15 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
/* Get size of DMA buffers/descriptors region */
pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
- pldat->dma_buff_base_v = 0;
if (use_iram_for_net(dev)) {
- dma_handle = LPC32XX_IRAM_BASE;
- if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
- pldat->dma_buff_base_v =
- io_p2v(LPC32XX_IRAM_BASE);
- else
+ if (pldat->dma_buff_size >
+ lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) {
+ pldat->dma_buff_base_v = NULL;
+ pldat->dma_buff_size = 0;
netdev_err(ndev,
"IRAM not big enough for net buffers, using SDRAM instead.\n");
+ }
}
if (pldat->dma_buff_base_v == 0) {
@@ -1409,7 +1408,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
unregister_netdev(ndev);
err_out_dma_unmap:
if (!use_iram_for_net(dev) ||
- pldat->dma_buff_size > lpc32xx_return_iram_size())
+ pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
dma_free_coherent(dev, pldat->dma_buff_size,
pldat->dma_buff_base_v,
pldat->dma_buff_base_p);
@@ -1436,7 +1435,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev)
unregister_netdev(ndev);
if (!use_iram_for_net(&pldat->pdev->dev) ||
- pldat->dma_buff_size > lpc32xx_return_iram_size())
+ pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL))
dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
pldat->dma_buff_base_v,
pldat->dma_buff_base_p);
diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h
new file mode 100644
index 000000000000..f232e1a1bcdc
--- /dev/null
+++ b/include/linux/soc/nxp/lpc32xx-misc.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ */
+
+#ifndef __SOC_LPC32XX_MISC_H
+#define __SOC_LPC32XX_MISC_H
+
+#include <linux/types.h>
+
+#ifdef CONFIG_ARCH_LPC32XX
+extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr);
+#else
+static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
+{
+ *mapbase = NULL;
+ *dmaaddr = 0;
+ return 0;
+}
+#endif
+
+#endif /* __SOC_LPC32XX_MISC_H */
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 07/13] net: lpc-enet: move phy setup into platform code
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, netdev, linux-kernel, Vladimir Zapolskiy,
Sylvain Lemieux, David S. Miller, linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
Setting the phy mode requires touching a platform specific
register, which prevents us from building the driver without
its header files.
Move it into a separate function in arch/arm/mach/lpc32xx
to hide the core registers from the network driver.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-lpc32xx/common.c | 12 ++++++++++++
drivers/net/ethernet/nxp/lpc_eth.c | 12 +-----------
include/linux/soc/nxp/lpc32xx-misc.h | 5 +++++
3 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index f648324d5fb4..a475339333c1 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -63,6 +63,18 @@ u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
}
EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
+void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
+{
+ u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
+ tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+ if (mode == PHY_INTERFACE_MODE_MII)
+ tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
+ else
+ tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+ __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
+}
+EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
+
static struct map_desc lpc32xx_io_desc[] __initdata = {
{
.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index bcdd0adcfb0c..0893b77c385d 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -20,9 +20,6 @@
#include <linux/spinlock.h>
#include <linux/soc/nxp/lpc32xx-misc.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
#define MODNAME "lpc-eth"
#define DRV_VERSION "1.00"
@@ -1237,16 +1234,9 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
dma_addr_t dma_handle;
struct resource *res;
int irq, ret;
- u32 tmp;
/* Setup network interface for RMII or MII mode */
- tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
- tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
- if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII)
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
- else
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
- __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
+ lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev));
/* Get platform resources */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h
index f232e1a1bcdc..af4f82f6cf3b 100644
--- a/include/linux/soc/nxp/lpc32xx-misc.h
+++ b/include/linux/soc/nxp/lpc32xx-misc.h
@@ -9,9 +9,11 @@
#define __SOC_LPC32XX_MISC_H
#include <linux/types.h>
+#include <linux/phy.h>
#ifdef CONFIG_ARCH_LPC32XX
extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr);
+extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode);
#else
static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
{
@@ -19,6 +21,9 @@ static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaadd
*dmaaddr = 0;
return 0;
}
+static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
+{
+}
#endif
#endif /* __SOC_LPC32XX_MISC_H */
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 08/13] net: lpc-enet: fix badzero.cocci warnings
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: kbuild test robot, Arnd Bergmann, netdev, linux-kernel,
Vladimir Zapolskiy, Sylvain Lemieux, David S. Miller,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
From: kbuild test robot <lkp@intel.com>
drivers/net/ethernet/nxp/lpc_eth.c:1316:31-32: WARNING comparing pointer to 0
Compare pointer-typed values to NULL rather than 0
Semantic patch information:
This makes an effort to choose between !x and x == NULL. !x is used
if it has previously been used with the function used to initialize x.
This relies on type information. More type information can be obtained
using the option -all_includes and the option -I to specify an
include path.
Generated by: scripts/coccinelle/null/badzero.cocci
Fixes: e42016eb3844 ("net: lpc-enet: allow compile testing")
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/net/ethernet/nxp/lpc_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 0893b77c385d..797bdbbcef76 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -1312,7 +1312,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
}
}
- if (pldat->dma_buff_base_v == 0) {
+ if (pldat->dma_buff_base_v == NULL) {
ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret)
goto err_out_free_irq;
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 09/13] net: lpc-enet: fix printk format strings
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: kbuild test robot, Arnd Bergmann, netdev, linux-kernel,
Vladimir Zapolskiy, Sylvain Lemieux, David S. Miller,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
compile-testing this driver on other architectures showed
multiple warnings:
drivers/net/ethernet/nxp/lpc_eth.c: In function 'lpc_eth_drv_probe':
drivers/net/ethernet/nxp/lpc_eth.c:1337:19: warning: format '%d' expects argument of type 'int', but argument 4 has type 'resource_size_t {aka long long unsigned int}' [-Wformat=]
drivers/net/ethernet/nxp/lpc_eth.c:1342:19: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'dma_addr_t {aka long long unsigned int}' [-Wformat=]
Use format strings that work on all architectures.
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/net/ethernet/nxp/lpc_eth.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 797bdbbcef76..96d509c418bf 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -1333,13 +1333,14 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
pldat->dma_buff_base_p = dma_handle;
netdev_dbg(ndev, "IO address space :%pR\n", res);
- netdev_dbg(ndev, "IO address size :%d\n", resource_size(res));
+ netdev_dbg(ndev, "IO address size :%zd\n",
+ (size_t)resource_size(res));
netdev_dbg(ndev, "IO address (mapped) :0x%p\n",
pldat->net_base);
netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);
- netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size);
- netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
- pldat->dma_buff_base_p);
+ netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size);
+ netdev_dbg(ndev, "DMA buffer P address :%pad\n",
+ &pldat->dma_buff_base_p);
netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
pldat->dma_buff_base_v);
@@ -1386,8 +1387,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev)
if (ret)
goto err_out_unregister_netdev;
- netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
- res->start, ndev->irq);
+ netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n",
+ (unsigned long)res->start, ndev->irq);
device_init_wakeup(dev, 1);
device_set_wakeup_enable(dev, 0);
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 10/13] net: lpc-enet: allow compile testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, netdev, linux-kernel, Vladimir Zapolskiy,
Sylvain Lemieux, David S. Miller, linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The lpc-enet driver can now be built on all platforms, so
allow compile testing as well.
Add one missing header inclusion that is required in some
configurations.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/net/ethernet/nxp/Kconfig | 2 +-
drivers/net/ethernet/nxp/lpc_eth.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/nxp/Kconfig b/drivers/net/ethernet/nxp/Kconfig
index 261f107e2be0..418afb84c84b 100644
--- a/drivers/net/ethernet/nxp/Kconfig
+++ b/drivers/net/ethernet/nxp/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config LPC_ENET
tristate "NXP ethernet MAC on LPC devices"
- depends on ARCH_LPC32XX
+ depends on ARCH_LPC32XX || COMPILE_TEST
select PHYLIB
help
Say Y or M here if you want to use the NXP ethernet MAC included on
diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c
index 96d509c418bf..141571e2ec11 100644
--- a/drivers/net/ethernet/nxp/lpc_eth.c
+++ b/drivers/net/ethernet/nxp/lpc_eth.c
@@ -14,6 +14,7 @@
#include <linux/crc32.h>
#include <linux/etherdevice.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH v3 05/21] ARM: dts: add recovery for I2C for iMX7
From: Marcel Ziswiler @ 2019-08-09 14:45 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: s.hauer@pengutronix.de, linux-kernel@vger.kernel.org,
Oleksandr Suvorov, linux-imx@nxp.com, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190807082556.5013-6-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> From: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
>
> - add recovery mode for applicable i2c buses for
> Colibri iMX7 module.
>
> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/imx7-colibri.dtsi | 25 +++++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi
> b/arch/arm/boot/dts/imx7-colibri.dtsi
> index a8d992f3e897..2480623c92ff 100644
> --- a/arch/arm/boot/dts/imx7-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri.dtsi
> @@ -140,8 +140,12 @@
>
> &i2c1 {
> clock-frequency = <100000>;
> - pinctrl-names = "default";
> + pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
> + pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
> + scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> +
> status = "okay";
>
> codec: sgtl5000@a {
> @@ -242,8 +246,11 @@
>
> &i2c4 {
> clock-frequency = <100000>;
> - pinctrl-names = "default";
> + pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pinctrl_i2c4>;
> + pinctrl-1 = <&pinctrl_i2c4_recovery>;
> + scl-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
> };
>
> &lcdif {
> @@ -540,6 +547,13 @@
> >;
> };
>
> + pinctrl_i2c4_recovery: i2c4-recoverygrp {
> + fsl,pins = <
> + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x400
> 0007f
> + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x400
> 0007f
> + >;
> + };
> +
> pinctrl_lcdif_dat: lcdif-dat-grp {
> fsl,pins = <
> MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
> @@ -740,6 +754,13 @@
> >;
> };
>
> + pinctrl_i2c1_recovery: i2c1-recoverygrp {
> + fsl,pins = <
> + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x400
> 0007f
> + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x400
> 0007f
> + >;
> + };
> +
> pinctrl_cd_usdhc1: usdhc1-cd-grp {
> fsl,pins = <
> MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59
> /* CD */
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 11/13] serial: lpc32xx: allow compile testing
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Arnd Bergmann, Greg Kroah-Hartman, Jiri Slaby, linux-kernel,
Vladimir Zapolskiy, linux-serial, Sylvain Lemieux,
linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
The lpc32xx_loopback_set() function in hte lpc32xx_hs driver is the
one thing that relies on platform header files. Move that into the
core platform code so we only need a variable declaration for it,
and enable COMPILE_TEST building.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-lpc32xx/serial.c | 30 ++++++++++++++++++++++++
drivers/tty/serial/lpc32xx_hs.c | 35 ++++------------------------
include/linux/soc/nxp/lpc32xx-misc.h | 4 ++++
3 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 3f9b30df9f0e..cfb35e5691cd 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -60,6 +60,36 @@ static struct uartinit uartinit_data[] __initdata = {
},
};
+/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
+void lpc32xx_loopback_set(resource_size_t mapbase, int state)
+{
+ int bit;
+ u32 tmp;
+
+ switch (mapbase) {
+ case LPC32XX_HS_UART1_BASE:
+ bit = 0;
+ break;
+ case LPC32XX_HS_UART2_BASE:
+ bit = 1;
+ break;
+ case LPC32XX_HS_UART7_BASE:
+ bit = 6;
+ break;
+ default:
+ WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
+ return;
+ }
+
+ tmp = readl(LPC32XX_UARTCTL_CLOOP);
+ if (state)
+ tmp |= (1 << bit);
+ else
+ tmp &= ~(1 << bit);
+ writel(tmp, LPC32XX_UARTCTL_CLOOP);
+}
+EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
+
void __init lpc32xx_serial_init(void)
{
u32 tmp, clkmodes = 0;
diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c
index 7f14cd8fac47..d3843f722182 100644
--- a/drivers/tty/serial/lpc32xx_hs.c
+++ b/drivers/tty/serial/lpc32xx_hs.c
@@ -25,6 +25,8 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/of.h>
+#include <linux/sizes.h>
+#include <linux/soc/nxp/lpc32xx-misc.h>
/*
* High Speed UART register offsets
@@ -79,6 +81,8 @@
#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
+#define LPC32XX_MAIN_OSC_FREQ 13000000
+
#define MODNAME "lpc32xx_hsuart"
struct lpc32xx_hsuart_port {
@@ -149,8 +153,6 @@ static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
local_irq_restore(flags);
}
-static void lpc32xx_loopback_set(resource_size_t mapbase, int state);
-
static int __init lpc32xx_hsuart_console_setup(struct console *co,
char *options)
{
@@ -437,35 +439,6 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port,
spin_unlock_irqrestore(&port->lock, flags);
}
-/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
-static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
-{
- int bit;
- u32 tmp;
-
- switch (mapbase) {
- case LPC32XX_HS_UART1_BASE:
- bit = 0;
- break;
- case LPC32XX_HS_UART2_BASE:
- bit = 1;
- break;
- case LPC32XX_HS_UART7_BASE:
- bit = 6;
- break;
- default:
- WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
- return;
- }
-
- tmp = readl(LPC32XX_UARTCTL_CLOOP);
- if (state)
- tmp |= (1 << bit);
- else
- tmp &= ~(1 << bit);
- writel(tmp, LPC32XX_UARTCTL_CLOOP);
-}
-
/* port->lock is not held. */
static int serial_lpc32xx_startup(struct uart_port *port)
{
diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h
index af4f82f6cf3b..699c6f1e3aab 100644
--- a/include/linux/soc/nxp/lpc32xx-misc.h
+++ b/include/linux/soc/nxp/lpc32xx-misc.h
@@ -14,6 +14,7 @@
#ifdef CONFIG_ARCH_LPC32XX
extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr);
extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode);
+extern void lpc32xx_loopback_set(resource_size_t mapbase, int state);
#else
static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
{
@@ -24,6 +25,9 @@ static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaadd
static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
{
}
+static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state)
+{
+}
#endif
#endif /* __SOC_LPC32XX_MISC_H */
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 12/13] ARM: lpc32xx: clean up header files
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc, Vladimir Zapolskiy, Sylvain Lemieux
Cc: Arnd Bergmann, linux-kernel, linux-arm-kernel
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
All device drivers have stopped relying on mach/*.h headers,
so move the remaining headers into arch/arm/mach-lpc32xx/lpc32xx.h
to prepare for multiplatform builds.
The mach/entry-macro.S file has been unused for a long time now
and can simply get removed.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-lpc32xx/common.c | 3 +-
.../mach-lpc32xx/include/mach/entry-macro.S | 28 -------------------
arch/arm/mach-lpc32xx/include/mach/hardware.h | 25 -----------------
.../mach-lpc32xx/include/mach/uncompress.h | 4 +--
.../{include/mach/platform.h => lpc32xx.h} | 18 ++++++++++--
arch/arm/mach-lpc32xx/pm.c | 3 +-
arch/arm/mach-lpc32xx/serial.c | 3 +-
arch/arm/mach-lpc32xx/suspend.S | 3 +-
8 files changed, 21 insertions(+), 66 deletions(-)
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/hardware.h
rename arch/arm/mach-lpc32xx/{include/mach/platform.h => lpc32xx.h} (98%)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index a475339333c1..304ea61a0716 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -13,8 +13,7 @@
#include <asm/mach/map.h>
#include <asm/system_info.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
+#include "lpc32xx.h"
#include "common.h"
/*
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
deleted file mode 100644
index eec0f5f7e722..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
-#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
- .endm
-
-/*
- * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
- * as set if an interrupt is pending.
- */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
- clz \irqnr, \irqstat
- rsb \irqnr, \irqnr, #31
- teq \irqstat, #0
- .endm
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
deleted file mode 100644
index 4866f096ffce..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * Start of virtual addresses for IO devices
- */
-#define IO_BASE 0xF0000000
-
-/*
- * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
- */
-#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
- IO_BASE)
-
-#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
-#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
index a568812a0b91..74b7aa0da0e4 100644
--- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -12,15 +12,13 @@
#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
/*
* Uncompress output is hardcoded to standard UART 5
*/
#define UART_FIFO_CTL_TX_RESET (1 << 2)
#define UART_STATUS_TX_MT (1 << 6)
+#define LPC32XX_UART5_BASE 0x40090000
#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/lpc32xx.h
similarity index 98%
rename from arch/arm/mach-lpc32xx/include/mach/platform.h
rename to arch/arm/mach-lpc32xx/lpc32xx.h
index 1c53790444fc..5eeb884a1993 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/lpc32xx.h
@@ -7,8 +7,8 @@
* Copyright (C) 2010 NXP Semiconductors
*/
-#ifndef __ASM_ARCH_PLATFORM_H
-#define __ASM_ARCH_PLATFORM_H
+#ifndef __ARM_LPC32XX_H
+#define __ARM_LPC32XX_H
#define _SBF(f, v) ((v) << (f))
#define _BIT(n) _SBF(n, 1)
@@ -700,4 +700,18 @@
#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
+/*
+ * Start of virtual addresses for IO devices
+ */
+#define IO_BASE 0xF0000000
+
+/*
+ * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
+ */
+#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+ IO_BASE)
+
+#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
+#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
+
#endif
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 32bca351a73b..b27fa1b9f56c 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -70,8 +70,7 @@
#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
+#include "lpc32xx.h"
#include "common.h"
#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index cfb35e5691cd..3e765c4bf986 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -16,8 +16,7 @@
#include <linux/clk.h>
#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
+#include "lpc32xx.h"
#include "common.h"
#define LPC32XX_SUART_FIFO_SIZE 64
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index 374f9f07fe48..3f0a8282ef6f 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -11,8 +11,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/platform.h>
-#include <mach/hardware.h>
+#include "lpc32xx.h"
/* Using named register defines makes the code easier to follow */
#define WORK1_REG r0
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 13/13] ARM: lpc32xx: allow multiplatform build
From: Arnd Bergmann @ 2019-08-09 14:40 UTC (permalink / raw)
To: soc
Cc: Sylvain Lemieux, Arnd Bergmann, linux-kernel, linux-arm-kernel,
Vladimir Zapolskiy
In-Reply-To: <20190809144043.476786-1-arnd@arndb.de>
All preparation work is done, so the platform can finally
be moved into ARCH_MULTIPLATFORM. This requires a small
change to the defconfig file to enable the platform.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig | 17 +------
arch/arm/configs/lpc32xx_defconfig | 1 +
arch/arm/mach-lpc32xx/Kconfig | 11 +++++
.../mach-lpc32xx/include/mach/uncompress.h | 48 -------------------
4 files changed, 14 insertions(+), 63 deletions(-)
create mode 100644 arch/arm/mach-lpc32xx/Kconfig
delete mode 100644 arch/arm/mach-lpc32xx/include/mach/uncompress.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 33b00579beff..65808e17cb3b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -478,21 +478,6 @@ config ARCH_W90X900
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
-config ARCH_LPC32XX
- bool "NXP LPC32XX"
- select ARM_AMBA
- select CLKDEV_LOOKUP
- select CLKSRC_LPC32XX
- select COMMON_CLK
- select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
- select GENERIC_IRQ_MULTI_HANDLER
- select GPIOLIB
- select SPARSE_IRQ
- select USE_OF
- help
- Support for the NXP LPC32XX family of processors
-
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@@ -746,6 +731,8 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
+source "arch/arm/mach-lpc32xx/Kconfig"
+
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 3772d5a8975a..09deb57db942 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_LPC32XX=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 000000000000..ec87c65f4536
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config ARCH_LPC32XX
+ bool "NXP LPC32XX"
+ depends on ARCH_MULTI_V5
+ select ARM_AMBA
+ select CLKSRC_LPC32XX
+ select CPU_ARM926T
+ select GPIOLIB
+ help
+ Support for the NXP LPC32XX family of processors
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
deleted file mode 100644
index 74b7aa0da0e4..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/include/mach/uncompress.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
-#define __ASM_ARM_ARCH_UNCOMPRESS_H
-
-#include <linux/io.h>
-
-/*
- * Uncompress output is hardcoded to standard UART 5
- */
-
-#define UART_FIFO_CTL_TX_RESET (1 << 2)
-#define UART_STATUS_TX_MT (1 << 6)
-#define LPC32XX_UART5_BASE 0x40090000
-
-#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
-
-#define LPC32XX_UART_DLLFIFO_O 0x00
-#define LPC32XX_UART_IIRFCR_O 0x08
-#define LPC32XX_UART_LSR_O 0x14
-
-static inline void putc(int ch)
-{
- /* Wait for transmit FIFO to empty */
- while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
- UART_STATUS_TX_MT) == 0)
- ;
-
- __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
-}
-
-static inline void flush(void)
-{
- __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
- UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
-}
-
-/* NULL functions; we don't presently need them */
-#define arch_decomp_setup()
-
-#endif
--
2.20.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH v3 06/21] ARM: dts: imx7-colibri: add GPIO wakeup key
From: Marcel Ziswiler @ 2019-08-09 14:46 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: Stefan Agner, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190807082556.5013-7-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Add wakeup GPIO key which is able to wake the system from sleep
> modes (e.g. Suspend-to-Memory).
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 14 ++++++++++++++
> arch/arm/boot/dts/imx7-colibri.dtsi | 7 ++++++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> index 3f2746169181..d4dbc4fc1adf 100644
> --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> @@ -52,6 +52,20 @@
> clock-frequency = <16000000>;
> };
>
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpiokeys>;
> +
> + power {
> + label = "Wake-Up";
> + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
> + linux,code = <KEY_WAKEUP>;
> + debounce-interval = <10>;
> + gpio-key,wakeup;
> + };
> + };
> +
> panel: panel {
> compatible = "edt,et057090dhu";
> backlight = <&bl>;
> diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi
> b/arch/arm/boot/dts/imx7-colibri.dtsi
> index 2480623c92ff..16d1a1ed1aff 100644
> --- a/arch/arm/boot/dts/imx7-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri.dtsi
> @@ -741,12 +741,17 @@
>
> pinctrl_gpio_lpsr: gpio1-grp {
> fsl,pins = <
> - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
> MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
> MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
> >;
> };
>
> + pinctrl_gpiokeys: gpiokeysgrp {
> + fsl,pins = <
> + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
> + >;
> + };
> +
> pinctrl_i2c1: i2c1-grp {
> fsl,pins = <
> MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x400
> 0007f
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 07/21] ARM: dts: imx7-colibri: fix 1.8V/UHS support
From: Marcel Ziswiler @ 2019-08-09 14:48 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: Stefan Agner, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190807082556.5013-8-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Add pinmuxing and do not specify voltage restrictions for the usdhc
> instance available on the modules edge connector. This allows to use
> SD-cards with higher transfer modes if supported by the carrier
> board.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3:
> - Add new commit message from Stefan's proposal on ML
>
> Changes in v2: None
>
> arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi
> b/arch/arm/boot/dts/imx7-colibri.dtsi
> index 16d1a1ed1aff..67f5e0c87fdc 100644
> --- a/arch/arm/boot/dts/imx7-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri.dtsi
> @@ -326,7 +326,6 @@
> &usdhc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
> - no-1-8-v;
> cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> disable-wp;
> vqmmc-supply = <®_LDO2>;
> @@ -671,6 +670,28 @@
> >;
> };
>
> + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> + fsl,pins = <
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
> + fsl,pins = <
> + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
> + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
> + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
> + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
> + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
> + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
> + >;
> + };
> +
> pinctrl_usdhc3: usdhc3grp {
> fsl,pins = <
> MX7D_PAD_SD3_CMD__SD3_CMD 0x59
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/6] arm64: dts: ti: k3-j721e: Add gpio nodes in main domain
From: Keerthy @ 2019-08-09 14:53 UTC (permalink / raw)
To: Lokesh Vutla, Tero Kristo, Nishanth Menon, linus.walleij
Cc: linux-gpio, Rob Herring, Linux ARM Mailing List,
Device Tree Mailing List
In-Reply-To: <20190809082947.30590-3-lokeshvutla@ti.com>
On 09/08/19 1:59 PM, Lokesh Vutla wrote:
> There are 8 instances of gpio modules in main domain divided into 2 groups:
> - Group1: gpio0, gpio2, gpio4, gpio6
> - Group2: gpio1, gpio3, gpio5, gpio7
>
> Groups are created to provide protection between two different processor
> virtual worlds. There are x gpio lines coming out of each group. Each module
> in a group has equal x gpio lines pinned out. There is a top level mux for
> selecting the module instance for each pin coming out of group. Exactly
> one module can be selected to control the corresponding pin. This muxing
> can be controlled along the pad mux configuration registers.
>
> Group1 pins out 128 lines(8 banks). Group 2 pins out 36 lines(2 banks).
>
> Add DT nodes for each module instance in the main domain. Users should
> make sure that correct gpio instance is selected in their pad configuration.
Reviewed-by: Keerthy <j-keerthy@ti.com>
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 132 ++++++++++++++++++++++
> 1 file changed, 132 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 01661c22c39d..199bc9a00b20 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -240,4 +240,136 @@
> clocks = <&k3_clks 286 0>;
> clock-names = "fclk";
> };
> +
> + main_gpio0: gpio@600000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00600000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
> + <105 4>, <105 5>, <105 6>, <105 7>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <128>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 105 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio1: gpio@601000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00601000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <106 0>, <106 1>, <106 2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <36>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 106 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio2: gpio@610000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00610000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
> + <107 4>, <107 5>, <107 6>, <107 7>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <128>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 107 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio3: gpio@611000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00611000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <108 0>, <108 1>, <108 2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <36>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 108 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio4: gpio@620000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00620000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
> + <109 4>, <109 5>, <109 6>, <109 7>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <128>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 109 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio5: gpio@621000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00621000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <110 0>, <110 1>, <110 2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <36>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 110 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio6: gpio@630000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00630000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
> + <111 4>, <111 5>, <111 6>, <111 7>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <128>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 111 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio7: gpio@631000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x00631000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <112 0>, <112 1>, <112 2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <36>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 112 0>;
> + clock-names = "gpio";
> + };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 3/6] arm64: dts: ti: k3-j721e: Add gpio nodes in wakeup domain
From: Keerthy @ 2019-08-09 14:54 UTC (permalink / raw)
To: Lokesh Vutla, Tero Kristo, Nishanth Menon, linus.walleij
Cc: linux-gpio, Rob Herring, Linux ARM Mailing List,
Device Tree Mailing List
In-Reply-To: <20190809082947.30590-4-lokeshvutla@ti.com>
On 09/08/19 1:59 PM, Lokesh Vutla wrote:
> Similar to the gpio groups in main domain, there is one gpio group
> in wakup domain with 2 module instances in it. This gpio group pins
> out 84 lines(6 banks). Add DT node for these 2 gpio module instances.
Reviewed-by: Keerthy <j-keerthy@ti.com>
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index e616c2481f51..555dc7b7aedc 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -87,4 +87,38 @@
> ti,sci-dst-id = <14>;
> ti,sci-rm-range-girq = <0x5>;
> };
> +
> + wkup_gpio0: gpio@42110000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x42110000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&wkup_gpio_intr>;
> + interrupts = <113 0>, <113 1>, <113 2>,
> + <113 3>, <113 4>, <113 5>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <84>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 113 0>;
> + clock-names = "gpio";
> + };
> +
> + wkup_gpio1: gpio@42100000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x0 0x42100000 0x0 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&wkup_gpio_intr>;
> + interrupts = <114 0>, <114 1>, <114 2>,
> + <114 3>, <114 4>, <114 5>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <84>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 114 0>;
> + clock-names = "gpio";
> + };
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 4/6] arm64: dts: ti: k3-j721e-common-proc-board: Disable unused gpio modules
From: Keerthy @ 2019-08-09 14:55 UTC (permalink / raw)
To: Lokesh Vutla, Tero Kristo, Nishanth Menon, linus.walleij
Cc: linux-gpio, Rob Herring, Linux ARM Mailing List,
Device Tree Mailing List
In-Reply-To: <20190809082947.30590-5-lokeshvutla@ti.com>
On 09/08/19 1:59 PM, Lokesh Vutla wrote:
> There are 10 gpio instances inside SoC with 3 groups as below:
> - Group1: main_gpio0, main_gpio2, main_gpio4, main_gpio6
> - Group2: main_gpio1, main_gpio3, main_gpio5, main_gpio7
> - Group3: wkup_gpio0, wkup_gpio1
>
> Only one instance can be used in each group at a time. So use main_gpio0,
> main_gpio1 and wkup_gpio0 for the current linux context and mark other
> gpio nodes as disabled.
Reviewed-by: Keerthy <j-keerthy@ti.com>
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../dts/ti/k3-j721e-common-proc-board.dts | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 63b47b839388..509579ca3db2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -52,3 +52,31 @@
> /* UART not brought out */
> status = "disabled";
> };
> +
> +&main_gpio2 {
> + status = "disabled";
> +};
> +
> +&main_gpio3 {
> + status = "disabled";
> +};
> +
> +&main_gpio4 {
> + status = "disabled";
> +};
> +
> +&main_gpio5 {
> + status = "disabled";
> +};
> +
> +&main_gpio6 {
> + status = "disabled";
> +};
> +
> +&main_gpio7 {
> + status = "disabled";
> +};
> +
> +&wkup_gpio1 {
> + status = "disabled";
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 08/21] ARM: dts: imx7-colibri: Add touch controllers
From: Marcel Ziswiler @ 2019-08-09 14:56 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: linux-imx@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20190807082556.5013-9-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> Add touch controller that is connected over an I2C bus.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3:
> - Fix commit message
>
> Changes in v2:
> - Deleted touchrevolution downstream stuff
> - Use generic node name
> - Better comment
>
> arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 24
> +++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> index d4dbc4fc1adf..576dec9ff81c 100644
> --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> @@ -145,6 +145,21 @@
> &i2c4 {
> status = "okay";
>
> + /*
> + * Touchscreen is using SODIMM 28/30, also used for PWM<B>,
> PWM<C>,
> + * aka pwm2, pwm3. so if you enable touchscreen, disable the
> pwms
> + */
> + touchscreen@4a {
> + compatible = "atmel,maxtouch";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpiotouch>;
> + reg = <0x4a>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /*
> SODIMM 28 */
> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /*
> SODIMM 30 */
> + status = "disabled";
> + };
> +
> /* M41T0M6 real time clock on carrier board */
> rtc: m41t0m6@68 {
> compatible = "st,m41t0";
> @@ -200,3 +215,12 @@
> vmmc-supply = <®_3v3>;
> status = "okay";
> };
> +
> +&iomuxc {
> + pinctrl_gpiotouch: touchgpios {
> + fsl,pins = <
> + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
> + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
> + >;
> + };
> +};
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 6/6] arm64: dts: k3-j721e: Add gpio-keys on common processor board
From: Keerthy @ 2019-08-09 14:56 UTC (permalink / raw)
To: Lokesh Vutla, Tero Kristo, Nishanth Menon, linus.walleij
Cc: linux-gpio, Rob Herring, Linux ARM Mailing List,
Device Tree Mailing List
In-Reply-To: <20190809082947.30590-7-lokeshvutla@ti.com>
On 09/08/19 1:59 PM, Lokesh Vutla wrote:
> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>
> Common processor board for K3 J721E platform has two push buttons
> namely SW10 and SW11.
> Add a gpio-keys device node to model them as input keys in Linux.
> Add required pinmux nodes to set GPIO pins as input.
Reviewed-by: Keerthy <j-keerthy@ti.com>
>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
> .../dts/ti/k3-j721e-common-proc-board.dts | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 509579ca3db2..d2894d55fbbe 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -6,12 +6,49 @@
> /dts-v1/;
>
> #include "k3-j721e-som-p0.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
>
> / {
> chosen {
> stdout-path = "serial2:115200n8";
> bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
> };
> +
> + gpio_keys: gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
> +
> + sw10: sw10 {
> + label = "GPIO Key USER1";
> + linux,code = <BTN_0>;
> + gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
> + };
> +
> + sw11: sw11 {
> + label = "GPIO Key USER2";
> + linux,code = <BTN_1>;
> + gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> +
> +&main_pmx0 {
> + sw10_button_pins_default: sw10_button_pins_default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
> + >;
> + };
> +};
> +
> +&wkup_pmx0 {
> + sw11_button_pins_default: sw11_button_pins_default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
> + >;
> + };
> };
>
> &wkup_uart0 {
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 09/21] ARM: dts: imx6qdl-colibri: add phy to fec
From: Marcel Ziswiler @ 2019-08-09 14:59 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: linux-imx@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20190807082556.5013-10-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> Add the phy-node and mdio bus to the fec-node, represented as is on
> hardware.
> This commit includes micrel,led-mode that is set to the default
> value, prepared for someone who wants to change this.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> index 1beac22266ed..019dda6b88ad 100644
> --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -140,7 +140,18 @@
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_enet>;
> phy-mode = "rmii";
> + phy-handle = <ðphy>;
> status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy@0 {
> + reg = <0>;
> + micrel,led-mode = <0>;
> + };
> + };
> };
>
> &hdmi {
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 10/21] ARM: dts: imx6qdl-colibri: Add missing pin declaration in iomuxc
From: Marcel Ziswiler @ 2019-08-09 15:00 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: linux-imx@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20190807082556.5013-11-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> This adds the muxing for the optional pins usb-oc (overcurrent) and
> usb-id.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> index 019dda6b88ad..9a63debab0b5 100644
> --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -615,6 +615,13 @@
> >;
> };
>
> + pinctrl_usbh_oc_1: usbh_oc-1 {
> + fsl,pins = <
> + /* USBH_OC */
> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0
> b0
> + >;
> + };
> +
> pinctrl_spdif: spdifgrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> @@ -681,6 +688,13 @@
> >;
> };
>
> + pinctrl_usbc_id_1: usbc_id-1 {
> + fsl,pins = <
> + /* USBC_ID */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0
> b0
> + >;
> + };
> +
> pinctrl_usdhc1: usdhc1grp {
> fsl,pins = <
> MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 11/21] ARM: dts: imx6qdl-apalis: Add sleep state to can interfaces
From: Marcel Ziswiler @ 2019-08-09 15:02 UTC (permalink / raw)
To: Max Krummenacher, stefan@agner.ch, Philippe Schenker,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, festevam@gmail.com,
robh+dt@kernel.org
Cc: linux-imx@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20190807082556.5013-12-philippe.schenker@toradex.com>
On Wed, 2019-08-07 at 08:26 +0000, Philippe Schenker wrote:
> This patch prepares the devicetree for the new Ixora V1.2 where we
> are
> able to turn off the supply of the can transceiver. This implies to
> use
> a sleep state on transmission pins in order to prevent backfeeding.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Changed commit title to '...imx6qdl-apalis:...'
>
> arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 +++++++++++++++++++++--
> ----
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index 7c4ad541c3f5..59ed2e4a1fd1 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -148,14 +148,16 @@
> };
>
> &can1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_flexcan1>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_flexcan1_default>;
> + pinctrl-1 = <&pinctrl_flexcan1_sleep>;
> status = "disabled";
> };
>
> &can2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_flexcan2>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_flexcan2_default>;
> + pinctrl-1 = <&pinctrl_flexcan2_sleep>;
> status = "disabled";
> };
>
> @@ -599,19 +601,32 @@
> >;
> };
>
> - pinctrl_flexcan1: flexcan1grp {
> + pinctrl_flexcan1_default: flexcan1defgrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> >;
> };
>
> - pinctrl_flexcan2: flexcan2grp {
> + pinctrl_flexcan1_sleep: flexcan1slpgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
> + >;
> + };
> +
> + pinctrl_flexcan2_default: flexcan2defgrp {
> fsl,pins = <
> MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> >;
> };
> + pinctrl_flexcan2_sleep: flexcan2slpgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
> + >;
> + };
>
> pinctrl_gpio_bl_on: gpioblon {
> fsl,pins = <
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox