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* [PATCH 2/5] can: xilinx_can: Fix FSR register handling in the rx path
From: Appana Durga Kedareswara rao @ 2019-08-12  7:28 UTC (permalink / raw)
  To: wg, mkl, davem, michal.simek
  Cc: netdev, Appana Durga Kedareswara rao, linux-kernel,
	linux-arm-kernel, linux-can
In-Reply-To: <1565594914-18999-1-git-send-email-appana.durga.rao@xilinx.com>

After commit c223da689324 ("can: xilinx_can: Add support for
CANFD FD frames") Driver is updating the FSR IRI index multiple
times(i.e in xcanfd_rx() and xcan_rx_fifo_get_next_frame()),
It should be updated once per rx packet this patch fixes this issue,
also this patch removes the unnecessary fsr register checks in
xcanfd_rx() API.

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/net/can/xilinx_can.c | 139 ++++++++++++++++++++-----------------------
 1 file changed, 63 insertions(+), 76 deletions(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index ac175ab..2d3399e 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -819,91 +819,78 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base)
 	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, fsr, readindex;
 
 	fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
-	if (fsr & XCAN_FSR_FL_MASK) {
-		readindex = fsr & XCAN_FSR_RI_MASK;
-		id_xcan = priv->read_reg(priv,
-					 XCAN_FRAME_ID_OFFSET(frame_base));
-		dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
-		if (dlc & XCAN_DLCR_EDL_MASK)
-			skb = alloc_canfd_skb(ndev, &cf);
-		else
-			skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
+	readindex = fsr & XCAN_FSR_RI_MASK;
+	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));
+	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
+	if (dlc & XCAN_DLCR_EDL_MASK)
+		skb = alloc_canfd_skb(ndev, &cf);
+	else
+		skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
 
-		if (unlikely(!skb)) {
-			stats->rx_dropped++;
-			return 0;
-		}
+	if (unlikely(!skb)) {
+		stats->rx_dropped++;
+		return 0;
+	}
 
-		/* Change Xilinx CANFD data length format to socketCAN data
-		 * format
-		 */
-		if (dlc & XCAN_DLCR_EDL_MASK)
-			cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >>
+	/* Change Xilinx CANFD data length format to socketCAN data
+	 * format
+	 */
+	if (dlc & XCAN_DLCR_EDL_MASK)
+		cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >>
+				  XCAN_DLCR_DLC_SHIFT);
+	else
+		cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >>
 					  XCAN_DLCR_DLC_SHIFT);
-		else
-			cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >>
-						  XCAN_DLCR_DLC_SHIFT);
-
-		/* Change Xilinx CAN ID format to socketCAN ID format */
-		if (id_xcan & XCAN_IDR_IDE_MASK) {
-			/* The received frame is an Extended format frame */
-			cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
-			cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
-					XCAN_IDR_ID2_SHIFT;
-			cf->can_id |= CAN_EFF_FLAG;
-			if (id_xcan & XCAN_IDR_RTR_MASK)
-				cf->can_id |= CAN_RTR_FLAG;
-		} else {
-			/* The received frame is a standard format frame */
-			cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
-					XCAN_IDR_ID1_SHIFT;
-			if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan &
-						XCAN_IDR_SRR_MASK))
-				cf->can_id |= CAN_RTR_FLAG;
-		}
 
-		/* Check the frame received is FD or not*/
-		if (dlc & XCAN_DLCR_EDL_MASK) {
-			for (i = 0; i < cf->len; i += 4) {
-				if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
-					data[0] = priv->read_reg(priv,
+	/* Change Xilinx CAN ID format to socketCAN ID format */
+	if (id_xcan & XCAN_IDR_IDE_MASK) {
+		/* The received frame is an Extended format frame */
+		cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
+		cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
+				XCAN_IDR_ID2_SHIFT;
+		cf->can_id |= CAN_EFF_FLAG;
+		if (id_xcan & XCAN_IDR_RTR_MASK)
+			cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		/* The received frame is a standard format frame */
+		cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
+				XCAN_IDR_ID1_SHIFT;
+		if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan &
+					XCAN_IDR_SRR_MASK))
+			cf->can_id |= CAN_RTR_FLAG;
+	}
+
+	/* Check the frame received is FD or not*/
+	if (dlc & XCAN_DLCR_EDL_MASK) {
+		for (i = 0; i < cf->len; i += 4) {
+			if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
+				data[0] = priv->read_reg(priv,
 					(XCAN_RXMSG_2_FRAME_OFFSET(readindex) +
 					(dwindex * XCANFD_DW_BYTES)));
-				else
-					data[0] = priv->read_reg(priv,
+			else
+				data[0] = priv->read_reg(priv,
 					(XCAN_RXMSG_FRAME_OFFSET(readindex) +
-						(dwindex * XCANFD_DW_BYTES)));
-				*(__be32 *)(cf->data + i) =
-						cpu_to_be32(data[0]);
-				dwindex++;
-			}
-		} else {
-			for (i = 0; i < cf->len; i += 4) {
-				if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
-					data[0] = priv->read_reg(priv,
-						XCAN_RXMSG_2_FRAME_OFFSET(readindex) + i);
-				else
-					data[0] = priv->read_reg(priv,
-						XCAN_RXMSG_FRAME_OFFSET(readindex) + i);
-				*(__be32 *)(cf->data + i) =
-						cpu_to_be32(data[0]);
-			}
+					(dwindex * XCANFD_DW_BYTES)));
+			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
+			dwindex++;
+		}
+	} else {
+		for (i = 0; i < cf->len; i += 4) {
+			if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
+				data[0] = priv->read_reg(priv,
+					XCAN_RXMSG_2_FRAME_OFFSET(readindex) +
+								  i);
+			else
+				data[0] = priv->read_reg(priv,
+					XCAN_RXMSG_FRAME_OFFSET(readindex) + i);
+			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
 		}
-		/* Update FSR Register so that next packet will save to
-		 * buffer
-		 */
-		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
-		fsr |= XCAN_FSR_IRI_MASK;
-		priv->write_reg(priv, XCAN_FSR_OFFSET, fsr);
-		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
-		stats->rx_bytes += cf->len;
-		stats->rx_packets++;
-		netif_receive_skb(skb);
-
-		return 1;
 	}
-	/* If FSR Register is not updated with fill level */
-	return 0;
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+
+	return 1;
 }
 
 /**
-- 
2.7.4


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* [PATCH 3/5] can: xilinx_can: Fix the data updation logic for CANFD FD frames
From: Appana Durga Kedareswara rao @ 2019-08-12  7:28 UTC (permalink / raw)
  To: wg, mkl, davem, michal.simek
  Cc: netdev, Appana Durga Kedareswara rao, linux-kernel,
	linux-arm-kernel, linux-can
In-Reply-To: <1565594914-18999-1-git-send-email-appana.durga.rao@xilinx.com>

commit c223da689324 ("can: xilinx_can: Add support for CANFD FD frames")
is writing data to a wrong offset for FD frames.

This patch fixes this issue.

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/net/can/xilinx_can.c | 29 ++++++++---------------------
 1 file changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 2d3399e..c9b951b 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -66,8 +66,7 @@ enum xcan_reg {
 #define XCAN_FRAME_DLC_OFFSET(frame_base)	((frame_base) + 0x04)
 #define XCAN_FRAME_DW1_OFFSET(frame_base)	((frame_base) + 0x08)
 #define XCAN_FRAME_DW2_OFFSET(frame_base)	((frame_base) + 0x0C)
-#define XCANFD_FRAME_DW_OFFSET(frame_base, n)	(((frame_base) + 0x08) + \
-						 ((n) * XCAN_CANFD_FRAME_SIZE))
+#define XCANFD_FRAME_DW_OFFSET(frame_base)	((frame_base) + 0x08)
 
 #define XCAN_CANFD_FRAME_SIZE		0x48
 #define XCAN_TXMSG_FRAME_OFFSET(n)	(XCAN_TXMSG_BASE_OFFSET + \
@@ -600,7 +599,7 @@ static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb,
 	if (priv->devtype.cantype == XAXI_CANFD ||
 	    priv->devtype.cantype == XAXI_CANFD_2_0) {
 		for (i = 0; i < cf->len; i += 4) {
-			ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset, dwindex) +
+			ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) +
 					(dwindex * XCANFD_DW_BYTES);
 			priv->write_reg(priv, ramoff,
 					be32_to_cpup((__be32 *)(cf->data + i)));
@@ -816,10 +815,8 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base)
 	struct net_device_stats *stats = &ndev->stats;
 	struct canfd_frame *cf;
 	struct sk_buff *skb;
-	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, fsr, readindex;
+	u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset;
 
-	fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
-	readindex = fsr & XCAN_FSR_RI_MASK;
 	id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));
 	dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
 	if (dlc & XCAN_DLCR_EDL_MASK)
@@ -863,26 +860,16 @@ static int xcanfd_rx(struct net_device *ndev, int frame_base)
 	/* Check the frame received is FD or not*/
 	if (dlc & XCAN_DLCR_EDL_MASK) {
 		for (i = 0; i < cf->len; i += 4) {
-			if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
-				data[0] = priv->read_reg(priv,
-					(XCAN_RXMSG_2_FRAME_OFFSET(readindex) +
-					(dwindex * XCANFD_DW_BYTES)));
-			else
-				data[0] = priv->read_reg(priv,
-					(XCAN_RXMSG_FRAME_OFFSET(readindex) +
-					(dwindex * XCANFD_DW_BYTES)));
+			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) +
+					(dwindex * XCANFD_DW_BYTES);
+			data[0] = priv->read_reg(priv, dw_offset);
 			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
 			dwindex++;
 		}
 	} else {
 		for (i = 0; i < cf->len; i += 4) {
-			if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
-				data[0] = priv->read_reg(priv,
-					XCAN_RXMSG_2_FRAME_OFFSET(readindex) +
-								  i);
-			else
-				data[0] = priv->read_reg(priv,
-					XCAN_RXMSG_FRAME_OFFSET(readindex) + i);
+			dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base);
+			data[0] = priv->read_reg(priv, dw_offset + i);
 			*(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
 		}
 	}
-- 
2.7.4


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* [PATCH 4/5] can: xilinx_can: Fix FSR register FL and RI mask values for canfd 2.0
From: Appana Durga Kedareswara rao @ 2019-08-12  7:28 UTC (permalink / raw)
  To: wg, mkl, davem, michal.simek
  Cc: netdev, Appana Durga Kedareswara rao, linux-kernel,
	linux-arm-kernel, linux-can
In-Reply-To: <1565594914-18999-1-git-send-email-appana.durga.rao@xilinx.com>

For CANFD 2.0 IP configuration existing driver is using incorrect mask
values for FSR register FL and RI fields.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/net/can/xilinx_can.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index c9b951b..4cb8c1c9 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -123,8 +123,10 @@ enum xcan_reg {
 #define XCAN_IDR_RTR_MASK		0x00000001 /* Remote TX request */
 #define XCAN_DLCR_DLC_MASK		0xF0000000 /* Data length code */
 #define XCAN_FSR_FL_MASK		0x00003F00 /* RX Fill Level */
+#define XCAN_2_FSR_FL_MASK		0x00007F00 /* RX Fill Level */
 #define XCAN_FSR_IRI_MASK		0x00000080 /* RX Increment Read Index */
 #define XCAN_FSR_RI_MASK		0x0000001F /* RX Read Index */
+#define XCAN_2_FSR_RI_MASK		0x0000003F /* RX Read Index */
 #define XCAN_DLCR_EDL_MASK		0x08000000 /* EDL Mask in DLC */
 #define XCAN_DLCR_BRS_MASK		0x04000000 /* BRS Mask in DLC */
 
@@ -1138,7 +1140,7 @@ static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv)
 	int offset;
 
 	if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) {
-		u32 fsr;
+		u32 fsr, mask;
 
 		/* clear RXOK before the is-empty check so that any newly
 		 * received frame will reassert it without a race
@@ -1148,12 +1150,17 @@ static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv)
 		fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
 
 		/* check if RX FIFO is empty */
-		if (!(fsr & XCAN_FSR_FL_MASK))
+		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
+			mask = XCAN_2_FSR_FL_MASK;
+		else
+			mask = XCAN_FSR_FL_MASK;
+
+		if (!(fsr & mask))
 			return -ENOENT;
 
 		if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
 			offset =
-			  XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
+			  XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK);
 		else
 			offset =
 			  XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
-- 
2.7.4


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* [PATCH 0/5] can: xilinx_can: Bug fixes
From: Appana Durga Kedareswara rao @ 2019-08-12  7:28 UTC (permalink / raw)
  To: wg, mkl, davem, michal.simek
  Cc: netdev, Appana Durga Kedareswara rao, linux-kernel,
	linux-arm-kernel, linux-can

This patch series fixes below issues
--> Bugs in the driver w.r.to CANFD 2.0 IP support
--> Defer the probe if clock is not found

Appana Durga Kedareswara rao (3):
  can: xilinx_can: Fix FSR register handling in the rx path
  can: xilinx_can: Fix the data updation logic for CANFD FD frames
  can: xilinx_can: Fix FSR register FL and RI mask values for canfd 2.0

Srinivas Neeli (1):
  can: xilinx_can: Fix the data phase btr1 calculation

Venkatesh Yadav Abbarapu (1):
  can: xilinx_can: defer the probe if clock is not found

 drivers/net/can/xilinx_can.c | 162 +++++++++++++++++++------------------------
 1 file changed, 72 insertions(+), 90 deletions(-)

-- 
2.7.4


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* [PATCH 1/5] can: xilinx_can: defer the probe if clock is not found
From: Appana Durga Kedareswara rao @ 2019-08-12  7:28 UTC (permalink / raw)
  To: wg, mkl, davem, michal.simek
  Cc: netdev, Venkatesh Yadav Abbarapu, linux-kernel, linux-arm-kernel,
	linux-can
In-Reply-To: <1565594914-18999-1-git-send-email-appana.durga.rao@xilinx.com>

From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>

It's not always the case that clock is already available when can
driver get probed at the first time, e.g. the clock is provided by
clock wizard which may be probed after can driver. So let's defer
the probe when devm_clk_get() call fails and give it chance to
try later.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/net/can/xilinx_can.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index bd95cfa..ac175ab 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -1791,7 +1791,8 @@ static int xcan_probe(struct platform_device *pdev)
 	/* Getting the CAN can_clk info */
 	priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
 	if (IS_ERR(priv->can_clk)) {
-		dev_err(&pdev->dev, "Device clock not found.\n");
+		if (PTR_ERR(priv->can_clk) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Device clock not found.\n");
 		ret = PTR_ERR(priv->can_clk);
 		goto err_free;
 	}
-- 
2.7.4


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* Re: [linux-sunxi] [PATCH v5 1/3] arm64: dts: allwinner: Add SPDIF node for Allwinner H6
From: Clément Péron @ 2019-08-12  7:11 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: devicetree, Maxime Ripard, linux-kernel, linux-sunxi, Rob Herring,
	linux-arm-kernel
In-Reply-To: <CAGb2v67N5Ykzo6myKqrNMgu6PCH2pJTzw9JJ5t0MGP_p=0ae9g@mail.gmail.com>

Hi Chen-Yu,

On Mon, 12 Aug 2019 at 08:35, Chen-Yu Tsai <wens@kernel.org> wrote:
>
> On Mon, Aug 12, 2019 at 12:52 PM Chen-Yu Tsai <wens@kernel.org> wrote:
> >
> > Hi,
> >
> > On Mon, Aug 12, 2019 at 4:31 AM Clément Péron <peron.clem@gmail.com> wrote:
> > >
> > > The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
> > >
> > > Only one pinmuxing is available so set it as default.
> > >
> > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > > ---
> > >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++
> > >  1 file changed, 38 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > index 7628a7c83096..677eb374678d 100644
> > > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > > @@ -83,6 +83,24 @@
> > >                 method = "smc";
> > >         };
> > >
> > > +       sound-spdif {
> > > +               compatible = "simple-audio-card";
> > > +               simple-audio-card,name = "sun50i-h6-spdif";
> > > +
> > > +               simple-audio-card,cpu {
> > > +                       sound-dai = <&spdif>;
> > > +               };
> > > +
> > > +               simple-audio-card,codec {
> > > +                       sound-dai = <&spdif_out>;
> > > +               };
> > > +       };
> > > +
> > > +       spdif_out: spdif-out {
> > > +               #sound-dai-cells = <0>;
> > > +               compatible = "linux,spdif-dit";
> > > +       };
> > > +
> >
> > We've always had this part in the board dts. It isn't relevant to boards
> > that don't have SPDIF output.
> >
> > Also, not so relevant here, but there are different simple sound card
> > constructs. Some support multiple audio streams with dynamic PCM routing.
> > How these are configured really depends on what interfaces are usable.
> >
> > So keeping this at the board level is IMO a better choice.

I Agree, I try to keep coherency with sun50i-a64.dtsi.
But sound routing is really at board level not SoC one.

Regards,
Clément

>
> Forgot to mention. Both patches and all parts in this patch are OK. It's
> just the parts the need to be moved.
>
>
> > ChenYu
> >
> >
> > >         timer {
> > >                 compatible = "arm,armv8-timer";
> > >                 interrupts = <GIC_PPI 13
> > > @@ -282,6 +300,11 @@
> > >                                 bias-pull-up;
> > >                         };
> > >
> > > +                       spdif_tx_pin: spdif-tx-pin {
> > > +                               pins = "PH7";
> > > +                               function = "spdif";
> > > +                       };
> > > +
> > >                         uart0_ph_pins: uart0-ph-pins {
> > >                                 pins = "PH0", "PH1";
> > >                                 function = "uart0";
> > > @@ -411,6 +434,21 @@
> > >                         };
> > >                 };
> > >
> > > +               spdif: spdif@5093000 {
> > > +                       #sound-dai-cells = <0>;
> > > +                       compatible = "allwinner,sun50i-h6-spdif";
> > > +                       reg = <0x05093000 0x400>;
> > > +                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> > > +                       clock-names = "apb", "spdif";
> > > +                       resets = <&ccu RST_BUS_SPDIF>;
> > > +                       dmas = <&dma 2>;
> > > +                       dma-names = "tx";
> > > +                       pinctrl-names = "default";
> > > +                       pinctrl-0 = <&spdif_tx_pin>;
> > > +                       status = "disabled";
> > > +               };
> > > +
> > >                 usb2otg: usb@5100000 {
> > >                         compatible = "allwinner,sun50i-h6-musb",
> > >                                      "allwinner,sun8i-a33-musb";
> > > --
> > > 2.20.1
> > >
> > > --
> > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190811203144.5999-2-peron.clem%40gmail.com.

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* RE: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
From: Biwen Li @ 2019-08-12  7:11 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: wsa@the-dreams.de, shawnguo@kernel.org,
	linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
	kernel@pengutronix.de, Laurentiu Tudor, festevam@gmail.com,
	linux-arm-kernel@lists.infradead.org, dl-linux-imx
In-Reply-To: <20190812063822.7odhnj5ueqjam3g6@pengutronix.de>

> Subject: Re: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
> 
> Caution: EXT Email
> 
> On Fri, Aug 09, 2019 at 04:04:45AM +0000, Biwen Li wrote:
> > >
> > > Hi,
> > >
> > > On Thu, Aug 08, 2019 at 11:53:43AM +0800, Biwen Li wrote:
> > > > The patch supports slave mode for imx I2C driver
> > > >
> > > > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > > > ---
> > > >  drivers/i2c/busses/i2c-imx.c | 199
> > > > ++++++++++++++++++++++++++++++++---
> > > >  1 file changed, 185 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/i2c/busses/i2c-imx.c
> > > > b/drivers/i2c/busses/i2c-imx.c index b1b8b938d7f4..f7583a9fa56f
> > > > 100644
> > > > --- a/drivers/i2c/busses/i2c-imx.c
> > > > +++ b/drivers/i2c/busses/i2c-imx.c
> > > > @@ -202,6 +202,9 @@ struct imx_i2c_struct {
> > > >       struct pinctrl_state *pinctrl_pins_gpio;
> > > >
> > > >       struct imx_i2c_dma      *dma;
> > > > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > > > +     struct i2c_client               *slave;
> > > > +#endif /* CONFIG_I2C_SLAVE */
> > >
> > > Other drivers just do a "select I2C_SLAVE" in Kconfig to get rid of
> > > these #ifs. We should do the same.
> > Hi sascha, I don't know your meaning, could you let it clearer?
> 
> Other drivers have "select I2C_SLAVE" in Kconfig, so they do not need any #ifdef
> CONFIG_I2C_SLAVE as this is always true.
Okay, sascha, got it, I will remove the option in v2, thanks.
> 
> Sascha
> 
> --
> Pengutronix e.K.                           |
> |
> Industrial Linux Solutions                 |
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pe
> ngutronix.de%2F&amp;data=02%7C01%7Cbiwen.li%40nxp.com%7C2ad7a8ef
> 04c84f224a9808d71eefaf43%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C637011887098895560&amp;sdata=Dde7Hi6eMWcg7SM8T63eBtgY
> XsQPu3HFJaZMt6z8Vck%3D&amp;reserved=0  |
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> |
> Amtsgericht Hildesheim, HRA 2686           | Fax:
> +49-5121-206917-5555 |

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* Re: [PATCH v2 05/13] gpio: lpc32xx: allow building on non-lpc32xx targets
From: Bartosz Golaszewski @ 2019-08-12  7:09 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Linus Walleij, LKML, Vladimir Zapolskiy, linux-gpio, soc,
	Sylvain Lemieux, arm-soc
In-Reply-To: <20190809144043.476786-6-arnd@arndb.de>

pt., 9 sie 2019 o 16:43 Arnd Bergmann <arnd@arndb.de> napisał(a):
>
> The driver uses hardwire MMIO addresses instead of the data
> that is passed in device tree. Change it over to only
> hardcode the register offset values and allow compile-testing.
>
> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  arch/arm/configs/lpc32xx_defconfig |   1 +
>  drivers/gpio/Kconfig               |   7 ++
>  drivers/gpio/Makefile              |   2 +-
>  drivers/gpio/gpio-lpc32xx.c        | 118 +++++++++++++++++------------
>  4 files changed, 77 insertions(+), 51 deletions(-)
>
> diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
> index 0cdc6c7974b3..3772d5a8975a 100644
> --- a/arch/arm/configs/lpc32xx_defconfig
> +++ b/arch/arm/configs/lpc32xx_defconfig
> @@ -93,6 +93,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
>  # CONFIG_HW_RANDOM is not set
>  CONFIG_I2C_CHARDEV=y
>  CONFIG_I2C_PNX=y
> +CONFIG_GPIO_LPC32XX=y
>  CONFIG_SPI=y
>  CONFIG_SPI_PL022=y
>  CONFIG_GPIO_SYSFS=y
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index bb13c266c329..8b40a578963c 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -311,6 +311,13 @@ config GPIO_LPC18XX
>           Select this option to enable GPIO driver for
>           NXP LPC18XX/43XX devices.
>
> +config GPIO_LPC32XX
> +       tristate "NXP LPC32XX GPIO support"
> +       depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST)
> +       help
> +         Select this option to enable GPIO driver for
> +         NXP LPC32XX devices.
> +
>  config GPIO_LYNXPOINT
>         tristate "Intel Lynxpoint GPIO support"
>         depends on ACPI && X86
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index a4e91175c708..87d659ae95eb 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943)             += gpio-lp3943.o
>  obj-$(CONFIG_GPIO_LP873X)              += gpio-lp873x.o
>  obj-$(CONFIG_GPIO_LP87565)             += gpio-lp87565.o
>  obj-$(CONFIG_GPIO_LPC18XX)             += gpio-lpc18xx.o
> -obj-$(CONFIG_ARCH_LPC32XX)             += gpio-lpc32xx.o
> +obj-$(CONFIG_GPIO_LPC32XX)             += gpio-lpc32xx.o
>  obj-$(CONFIG_GPIO_LYNXPOINT)           += gpio-lynxpoint.o
>  obj-$(CONFIG_GPIO_MADERA)              += gpio-madera.o
>  obj-$(CONFIG_GPIO_MAX3191X)            += gpio-max3191x.o
> diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c
> index 24885b3db3d5..4e626c4235c2 100644
> --- a/drivers/gpio/gpio-lpc32xx.c
> +++ b/drivers/gpio/gpio-lpc32xx.c
> @@ -16,36 +16,33 @@
>  #include <linux/platform_device.h>
>  #include <linux/module.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> -
> -#define LPC32XX_GPIO_P3_INP_STATE              _GPREG(0x000)
> -#define LPC32XX_GPIO_P3_OUTP_SET               _GPREG(0x004)
> -#define LPC32XX_GPIO_P3_OUTP_CLR               _GPREG(0x008)
> -#define LPC32XX_GPIO_P3_OUTP_STATE             _GPREG(0x00C)
> -#define LPC32XX_GPIO_P2_DIR_SET                        _GPREG(0x010)
> -#define LPC32XX_GPIO_P2_DIR_CLR                        _GPREG(0x014)
> -#define LPC32XX_GPIO_P2_DIR_STATE              _GPREG(0x018)
> -#define LPC32XX_GPIO_P2_INP_STATE              _GPREG(0x01C)
> -#define LPC32XX_GPIO_P2_OUTP_SET               _GPREG(0x020)
> -#define LPC32XX_GPIO_P2_OUTP_CLR               _GPREG(0x024)
> -#define LPC32XX_GPIO_P2_MUX_SET                        _GPREG(0x028)
> -#define LPC32XX_GPIO_P2_MUX_CLR                        _GPREG(0x02C)
> -#define LPC32XX_GPIO_P2_MUX_STATE              _GPREG(0x030)
> -#define LPC32XX_GPIO_P0_INP_STATE              _GPREG(0x040)
> -#define LPC32XX_GPIO_P0_OUTP_SET               _GPREG(0x044)
> -#define LPC32XX_GPIO_P0_OUTP_CLR               _GPREG(0x048)
> -#define LPC32XX_GPIO_P0_OUTP_STATE             _GPREG(0x04C)
> -#define LPC32XX_GPIO_P0_DIR_SET                        _GPREG(0x050)
> -#define LPC32XX_GPIO_P0_DIR_CLR                        _GPREG(0x054)
> -#define LPC32XX_GPIO_P0_DIR_STATE              _GPREG(0x058)
> -#define LPC32XX_GPIO_P1_INP_STATE              _GPREG(0x060)
> -#define LPC32XX_GPIO_P1_OUTP_SET               _GPREG(0x064)
> -#define LPC32XX_GPIO_P1_OUTP_CLR               _GPREG(0x068)
> -#define LPC32XX_GPIO_P1_OUTP_STATE             _GPREG(0x06C)
> -#define LPC32XX_GPIO_P1_DIR_SET                        _GPREG(0x070)
> -#define LPC32XX_GPIO_P1_DIR_CLR                        _GPREG(0x074)
> -#define LPC32XX_GPIO_P1_DIR_STATE              _GPREG(0x078)
> +#define LPC32XX_GPIO_P3_INP_STATE              (0x000)
> +#define LPC32XX_GPIO_P3_OUTP_SET               (0x004)
> +#define LPC32XX_GPIO_P3_OUTP_CLR               (0x008)
> +#define LPC32XX_GPIO_P3_OUTP_STATE             (0x00C)
> +#define LPC32XX_GPIO_P2_DIR_SET                        (0x010)
> +#define LPC32XX_GPIO_P2_DIR_CLR                        (0x014)
> +#define LPC32XX_GPIO_P2_DIR_STATE              (0x018)
> +#define LPC32XX_GPIO_P2_INP_STATE              (0x01C)
> +#define LPC32XX_GPIO_P2_OUTP_SET               (0x020)
> +#define LPC32XX_GPIO_P2_OUTP_CLR               (0x024)
> +#define LPC32XX_GPIO_P2_MUX_SET                        (0x028)
> +#define LPC32XX_GPIO_P2_MUX_CLR                        (0x02C)
> +#define LPC32XX_GPIO_P2_MUX_STATE              (0x030)
> +#define LPC32XX_GPIO_P0_INP_STATE              (0x040)
> +#define LPC32XX_GPIO_P0_OUTP_SET               (0x044)
> +#define LPC32XX_GPIO_P0_OUTP_CLR               (0x048)
> +#define LPC32XX_GPIO_P0_OUTP_STATE             (0x04C)
> +#define LPC32XX_GPIO_P0_DIR_SET                        (0x050)
> +#define LPC32XX_GPIO_P0_DIR_CLR                        (0x054)
> +#define LPC32XX_GPIO_P0_DIR_STATE              (0x058)
> +#define LPC32XX_GPIO_P1_INP_STATE              (0x060)
> +#define LPC32XX_GPIO_P1_OUTP_SET               (0x064)
> +#define LPC32XX_GPIO_P1_OUTP_CLR               (0x068)
> +#define LPC32XX_GPIO_P1_OUTP_STATE             (0x06C)
> +#define LPC32XX_GPIO_P1_DIR_SET                        (0x070)
> +#define LPC32XX_GPIO_P1_DIR_CLR                        (0x074)
> +#define LPC32XX_GPIO_P1_DIR_STATE              (0x078)
>
>  #define GPIO012_PIN_TO_BIT(x)                  (1 << (x))
>  #define GPIO3_PIN_TO_BIT(x)                    (1 << ((x) + 25))
> @@ -72,12 +69,12 @@
>  #define LPC32XX_GPO_P3_GRP     (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
>
>  struct gpio_regs {
> -       void __iomem *inp_state;
> -       void __iomem *outp_state;
> -       void __iomem *outp_set;
> -       void __iomem *outp_clr;
> -       void __iomem *dir_set;
> -       void __iomem *dir_clr;
> +       unsigned long inp_state;
> +       unsigned long outp_state;
> +       unsigned long outp_set;
> +       unsigned long outp_clr;
> +       unsigned long dir_set;
> +       unsigned long dir_clr;
>  };
>
>  /*
> @@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = {
>  struct lpc32xx_gpio_chip {
>         struct gpio_chip        chip;
>         struct gpio_regs        *gpio_grp;
> +       void __iomem            *reg_base;
>  };
>
> +static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
> +{
> +       return __raw_readl(group->reg_base + offset);
> +}
> +
> +static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
> +{
> +       __raw_writel(val, group->reg_base + offset);
> +}
> +
>  static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
>         unsigned pin, int input)
>  {
>         if (input)
> -               __raw_writel(GPIO012_PIN_TO_BIT(pin),
> +               gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
>                         group->gpio_grp->dir_clr);
>         else
> -               __raw_writel(GPIO012_PIN_TO_BIT(pin),
> +               gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
>                         group->gpio_grp->dir_set);
>  }
>
> @@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
>         u32 u = GPIO3_PIN_TO_BIT(pin);
>
>         if (input)
> -               __raw_writel(u, group->gpio_grp->dir_clr);
> +               gpreg_write(group, u, group->gpio_grp->dir_clr);
>         else
> -               __raw_writel(u, group->gpio_grp->dir_set);
> +               gpreg_write(group, u, group->gpio_grp->dir_set);
>  }
>
>  static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
>         unsigned pin, int high)
>  {
>         if (high)
> -               __raw_writel(GPIO012_PIN_TO_BIT(pin),
> +               gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
>                         group->gpio_grp->outp_set);
>         else
> -               __raw_writel(GPIO012_PIN_TO_BIT(pin),
> +               gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
>                         group->gpio_grp->outp_clr);
>  }
>
> @@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
>         u32 u = GPIO3_PIN_TO_BIT(pin);
>
>         if (high)
> -               __raw_writel(u, group->gpio_grp->outp_set);
> +               gpreg_write(group, u, group->gpio_grp->outp_set);
>         else
> -               __raw_writel(u, group->gpio_grp->outp_clr);
> +               gpreg_write(group, u, group->gpio_grp->outp_clr);
>  }
>
>  static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
>         unsigned pin, int high)
>  {
>         if (high)
> -               __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
> +               gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
>         else
> -               __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
> +               gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
>  }
>
>  static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
>         unsigned pin)
>  {
> -       return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
> +       return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
>                 pin);
>  }
>
>  static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
>         unsigned pin)
>  {
> -       int state = __raw_readl(group->gpio_grp->inp_state);
> +       int state = gpreg_read(group, group->gpio_grp->inp_state);
>
>         /*
>          * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
> @@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
>  static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
>         unsigned pin)
>  {
> -       return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
> +       return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
>  }
>
>  static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
>         unsigned pin)
>  {
> -       return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
> +       return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
>  }
>
>  /*
> @@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc,
>  static int lpc32xx_gpio_probe(struct platform_device *pdev)
>  {
>         int i;
> +       void __iomem *reg_base;
> +
> +       reg_base = devm_platform_ioremap_resource(pdev, 0);
> +       if (IS_ERR(reg_base))
> +               return PTR_ERR(reg_base);
>
>         for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
>                 if (pdev->dev.of_node) {
>                         lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
>                         lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
>                         lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
> +                       lpc32xx_gpiochip[i].reg_base = reg_base;
>                 }
>                 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
>                                   &lpc32xx_gpiochip[i]);
> @@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = {
>  };
>
>  module_platform_driver(lpc32xx_gpio_driver);
> +
> +MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
> --
> 2.20.0
>

Applied, thanks!

Bart

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^ permalink raw reply

* Re: [PATCH v2] arm64: dts: allwinner: a64: Enable eMMC on A64-OLinuXino
From: Maxime Ripard @ 2019-08-12  7:00 UTC (permalink / raw)
  To: Chen-Yu Tsai; +Cc: Sunil Mohan Adapa, Martin Ayotte, linux-arm-kernel
In-Reply-To: <CAGb2v66EjQ-_QNsJ+xR0LcR983whU-hF9SZ2dSX_i5v7qcEyww@mail.gmail.com>

On Thu, Aug 08, 2019 at 01:12:37PM +0800, Chen-Yu Tsai wrote:
> On Wed, Aug 7, 2019 at 10:45 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > On Wed, Aug 07, 2019 at 08:09:19PM +0800, Chen-Yu Tsai wrote:
> > > On Wed, Aug 7, 2019 at 8:01 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > > >
> > > > On Tue, Aug 06, 2019 at 02:25:17PM +0800, Chen-Yu Tsai wrote:
> > > > > On Mon, Aug 5, 2019 at 8:58 PM Martin Ayotte <martinayotte@gmail.com> wrote:
> > > > > >
> > > > > > Fine for me too.
> > > > > >
> > > > > > Thanks .
> > > > > >
> > > > > > -----Message d'origine-----
> > > > > > De : Sunil Mohan Adapa [mailto:sunil@medhas.org]
> > > > > > Envoyé : Monday, August 05, 2019 1:25 AM
> > > > > > Ą : Chen-Yu Tsai
> > > > > > Cc : Maxime Ripard; Martin Ayotte; linux-arm-kernel
> > > > > > Objet : Re: [PATCH v2] arm64: dts: allwinner: a64: Enable eMMC on
> > > > > > A64-OLinuXino
> > > > > >
> > > > > > On 04/08/19 8:33 pm, Chen-Yu Tsai wrote:
> > > > > > > On Fri, Aug 2, 2019 at 2:47 AM Sunil Mohan Adapa <sunil@medhas.org> wrote:
> > > > > > >>
> > > > > > >> On 01/08/19 6:49 am, Martin Ayotte wrote:
> > > > > > >>> If my SOB could help here, I don't mind since I've done the commit
> > > > > > >>> more than a year ago for Armbian ...
> > > > > > >>>
> > > > > > >>> Signed-off-by: Martin Ayotte <martinayotte@gmai.com>
> > > > > > >>> Tested-by: Martin Ayotte <martinayotte@gmai.com>
> > > > > > >> gmai.com is likely a typo.
> > > > > > >>
> > > > > > >>> On Wed, Jul 31, 2019 at 10:42 PM Chen-Yu Tsai <wens@csie.org
> > > > > > >>>
> > > > > > >>>> Thanks. The patch looks good overall. The authorship is a little
> > > > > > >>>> confusing though. If it was initially done by Martin (CC-ed), then
> > > > > > >>>> he should be the author, and we should get his Signed-off-by if
> > > > > > >>>> possible.
> > > > > > >>
> > > > > > >> Martin is indeed the original author of the patch. Thank you for
> > > > > > reviewing.
> > > > > > >
> > > > > > > I'd like to apply this patch with Martin as the author, if that's OK with
> > > > > > you
> > > > > > > both?
> > > > > >
> > > > > > That is completely okay with me.
> > > > >
> > > > > Applied for 5.4.
> > > > >
> > > > > I reordered the tags so they make more sense:
> > > > >
> > > > > https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/commit/?h=sunxi/dt-for-5.4&id=0834887732df5af41b59b2e4d530fc1f5478965f
> > > >
> > > > Sorry for being late on this, but it looks like the eMMC, NAND and SPI
> > > > pins are conflicting on the A64-Olinuxino design.
> > > >
> > > > There's no configuration with a NAND, so we don't really need to worry
> > > > about that, but if we merge this in the main DT, we'll prevent anyone
> > > > from using that DT on an olinuxino with a SPI flash.
> > > >
> > > > I think we should just create emmc and SPI-flash variants of that DT.
> > >
> > > Actually they aren't. Olimex specifically uses eMMC modules that don't
> > > use the data strobe line, so SPI can be used together.
> >
> > Ah, right.
> >
> > Still, this creates a precedent that I'm not really comfortable
> > with. Three actually.
> >
> > Merging this in the main DT means three things:
> >   - We're not consistent anymore, including within the olinuxino
> >     boards only. A20 Olinuxino is pretty much in the same situation,
> >     yet we dealt with it differently.
> >   - This means that this will create a spurious device and report
> >     errors in the kernel message and whenever someone will try to
> >     access the device on boards that don't have it wired. This
> >     shouldn't happen and we really shouldn't expose devices that just
> >     aren't there, just like you don't have all the devices that are
> >     not connected on your USB connector.
> >   - Finally, this means that in order to keep it somewhat consistent,
> >     we would have to merge the SPI flash in the main DT too. This will
> >     prevent people without a SPI flash to use the SPI signals on the
> >     UEXT connector for something else, which again goes against the
> >     policy we've had for basically any other board.
>
> OK. Shall we back it out and figure out something else?

I guess we can send a new patch on top to move it to a separate file

Maxime

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* Re: [PATCH v1] MAINTAINERS: i2c-imx: take over maintainership
From: Uwe Kleine-König @ 2019-08-12  6:48 UTC (permalink / raw)
  To: Oleksij Rempel
  Cc: Aisheng Dong, Wolfram Sang, Andrey Smirnov, Sascha Hauer,
	Russell King - ARM Linux admin, linux-i2c,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Shawn Guo,
	Chris Healy, linux-arm-kernel
In-Reply-To: <20190812050817.23279-1-o.rempel@pengutronix.de>

On Mon, Aug 12, 2019 at 07:08:17AM +0200, Oleksij Rempel wrote:
> I would like to maintain the i2c-imx driver. Since I work with
> different i.MX variants and have access to the hardware, I can spend
> some time on the reviewing of this driver.
> 
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
>  MAINTAINERS | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e81e60bd7c26..ddc1cf5cb0b9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6441,6 +6441,14 @@ S:	Maintained
>  F:	drivers/perf/fsl_imx8_ddr_perf.c
>  F:	Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
>  
> +FREESCALE IMX I2C DRIVER
> +M:	Oleksij Rempel <o.rempel@pengutronix.de>
> +R:	Pengutronix Kernel Team <kernel@pengutronix.de>
> +L:	linux-i2c@vger.kernel.org
> +S:	Maintained
> +F:	drivers/i2c/busses/i2c-imx.c
> +F:	Documentation/devicetree/bindings/i2c/i2c-imx.txt
> +

Even without this patch the generic "ARM/FREESCALE IMX / MXC ARM
ARCHITECTURE" entry matches the i2c-imx driver. Maybe it is worth to
point that out in the commit log?

Other than that arch/arm/mach-imx/devices/platform-imx-i2c.c might be
related, but not sure this is still used at all.

Great you pick that up.

Best regards
Uwe

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* Re: [PATCH v4 2/3] dt-bindings: eeprom: at25: Add Anvo ANV32E61W
From: Krzysztof Kozlowski @ 2019-08-12  6:43 UTC (permalink / raw)
  To: Schrempf Frieder
  Cc: Mark Rutland, devicetree@vger.kernel.org, Shawn Guo, Sascha Hauer,
	linux-kernel@vger.kernel.org, Rob Herring, NXP Linux Team,
	Pengutronix Kernel Team, Fabio Estevam,
	linux-arm-kernel@lists.infradead.org, notify@kernel.org
In-Reply-To: <de032954-2b6e-5aa9-0d91-c37417c8e162@kontron.de>

On Thu, 8 Aug 2019 at 20:09, Schrempf Frieder
<frieder.schrempf@kontron.de> wrote:
>
> On 08.08.19 19:26, Krzysztof Kozlowski wrote:
> > Document the compatible for ANV32E61W EEPROM chip.
>
> This chip is actually not an EEPROM, but a SPI nvSRAM. It can be
> interfaced by the at25 driver similar to an EEPROM. This is not the
> ideal solution, but it works until there's a proper driver for such
> chips. Maybe you can add some of these details to the commit message
> here. Also there is more information on this topic here:
> https://patchwork.ozlabs.org/patch/1043950/.

Indeed, I'll correct the description of commit.

Best regards,
Krzysztof

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* Re: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
From: Sascha Hauer @ 2019-08-12  6:38 UTC (permalink / raw)
  To: Biwen Li
  Cc: wsa@the-dreams.de, shawnguo@kernel.org,
	linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
	kernel@pengutronix.de, Laurentiu Tudor, festevam@gmail.com,
	linux-arm-kernel@lists.infradead.org, dl-linux-imx
In-Reply-To: <DB7PR04MB4490F2C2C4B69F0F011420C98FD60@DB7PR04MB4490.eurprd04.prod.outlook.com>

On Fri, Aug 09, 2019 at 04:04:45AM +0000, Biwen Li wrote:
> > 
> > Hi,
> > 
> > On Thu, Aug 08, 2019 at 11:53:43AM +0800, Biwen Li wrote:
> > > The patch supports slave mode for imx I2C driver
> > >
> > > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > > ---
> > >  drivers/i2c/busses/i2c-imx.c | 199
> > > ++++++++++++++++++++++++++++++++---
> > >  1 file changed, 185 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/i2c/busses/i2c-imx.c
> > > b/drivers/i2c/busses/i2c-imx.c index b1b8b938d7f4..f7583a9fa56f 100644
> > > --- a/drivers/i2c/busses/i2c-imx.c
> > > +++ b/drivers/i2c/busses/i2c-imx.c
> > > @@ -202,6 +202,9 @@ struct imx_i2c_struct {
> > >       struct pinctrl_state *pinctrl_pins_gpio;
> > >
> > >       struct imx_i2c_dma      *dma;
> > > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > > +     struct i2c_client               *slave;
> > > +#endif /* CONFIG_I2C_SLAVE */
> > 
> > Other drivers just do a "select I2C_SLAVE" in Kconfig to get rid of these #ifs. We
> > should do the same.
> Hi sascha, I don't know your meaning, could you let it clearer?

Other drivers have "select I2C_SLAVE" in Kconfig, so they do not need
any #ifdef CONFIG_I2C_SLAVE as this is always true.

Sascha

-- 
Pengutronix e.K.                           |                             |
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Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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* Re: [linux-sunxi] [PATCH v5 3/3] arm64: defconfig: Enable Sun4i SPDIF module
From: Chen-Yu Tsai @ 2019-08-12  6:37 UTC (permalink / raw)
  To: Clément Péron
  Cc: devicetree, Maxime Ripard, linux-kernel, linux-sunxi, Rob Herring,
	linux-arm-kernel
In-Reply-To: <20190811203144.5999-4-peron.clem@gmail.com>

On Mon, Aug 12, 2019 at 4:32 AM Clément Péron <peron.clem@gmail.com> wrote:
>
> Allwinner A64 and H6 use the Sun4i SPDIF driver.
>
> Enable this to allow a proper support.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>

Applied. Thanks.

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* Re: [linux-sunxi] [PATCH v5 1/3] arm64: dts: allwinner: Add SPDIF node for Allwinner H6
From: Chen-Yu Tsai @ 2019-08-12  6:34 UTC (permalink / raw)
  To: Clément Péron
  Cc: devicetree, Maxime Ripard, linux-kernel, linux-sunxi, Rob Herring,
	Chen-Yu Tsai, linux-arm-kernel
In-Reply-To: <CAGb2v67T3h_KTVZ20NVWNd78xqCa2ZhYiCJr4oOwYjUM3OaZXA@mail.gmail.com>

On Mon, Aug 12, 2019 at 12:52 PM Chen-Yu Tsai <wens@kernel.org> wrote:
>
> Hi,
>
> On Mon, Aug 12, 2019 at 4:31 AM Clément Péron <peron.clem@gmail.com> wrote:
> >
> > The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
> >
> > Only one pinmuxing is available so set it as default.
> >
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++
> >  1 file changed, 38 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 7628a7c83096..677eb374678d 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -83,6 +83,24 @@
> >                 method = "smc";
> >         };
> >
> > +       sound-spdif {
> > +               compatible = "simple-audio-card";
> > +               simple-audio-card,name = "sun50i-h6-spdif";
> > +
> > +               simple-audio-card,cpu {
> > +                       sound-dai = <&spdif>;
> > +               };
> > +
> > +               simple-audio-card,codec {
> > +                       sound-dai = <&spdif_out>;
> > +               };
> > +       };
> > +
> > +       spdif_out: spdif-out {
> > +               #sound-dai-cells = <0>;
> > +               compatible = "linux,spdif-dit";
> > +       };
> > +
>
> We've always had this part in the board dts. It isn't relevant to boards
> that don't have SPDIF output.
>
> Also, not so relevant here, but there are different simple sound card
> constructs. Some support multiple audio streams with dynamic PCM routing.
> How these are configured really depends on what interfaces are usable.
>
> So keeping this at the board level is IMO a better choice.

Forgot to mention. Both patches and all parts in this patch are OK. It's
just the parts the need to be moved.


> ChenYu
>
>
> >         timer {
> >                 compatible = "arm,armv8-timer";
> >                 interrupts = <GIC_PPI 13
> > @@ -282,6 +300,11 @@
> >                                 bias-pull-up;
> >                         };
> >
> > +                       spdif_tx_pin: spdif-tx-pin {
> > +                               pins = "PH7";
> > +                               function = "spdif";
> > +                       };
> > +
> >                         uart0_ph_pins: uart0-ph-pins {
> >                                 pins = "PH0", "PH1";
> >                                 function = "uart0";
> > @@ -411,6 +434,21 @@
> >                         };
> >                 };
> >
> > +               spdif: spdif@5093000 {
> > +                       #sound-dai-cells = <0>;
> > +                       compatible = "allwinner,sun50i-h6-spdif";
> > +                       reg = <0x05093000 0x400>;
> > +                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> > +                       clock-names = "apb", "spdif";
> > +                       resets = <&ccu RST_BUS_SPDIF>;
> > +                       dmas = <&dma 2>;
> > +                       dma-names = "tx";
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&spdif_tx_pin>;
> > +                       status = "disabled";
> > +               };
> > +
> >                 usb2otg: usb@5100000 {
> >                         compatible = "allwinner,sun50i-h6-musb",
> >                                      "allwinner,sun8i-a33-musb";
> > --
> > 2.20.1
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190811203144.5999-2-peron.clem%40gmail.com.

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* [PATCH v1] MAINTAINERS: i2c-imx: take over maintainership
From: Oleksij Rempel @ 2019-08-12  5:08 UTC (permalink / raw)
  To: Wolfram Sang, Shawn Guo, Sascha Hauer
  Cc: Aisheng Dong, Andrey Smirnov, Russell King - ARM Linux admin,
	Oleksij Rempel, linux-i2c, Pengutronix Kernel Team, Fabio Estevam,
	Chris Healy, linux-arm-kernel, NXP Linux Team

I would like to maintain the i2c-imx driver. Since I work with
different i.MX variants and have access to the hardware, I can spend
some time on the reviewing of this driver.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e81e60bd7c26..ddc1cf5cb0b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6441,6 +6441,14 @@ S:	Maintained
 F:	drivers/perf/fsl_imx8_ddr_perf.c
 F:	Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
 
+FREESCALE IMX I2C DRIVER
+M:	Oleksij Rempel <o.rempel@pengutronix.de>
+R:	Pengutronix Kernel Team <kernel@pengutronix.de>
+L:	linux-i2c@vger.kernel.org
+S:	Maintained
+F:	drivers/i2c/busses/i2c-imx.c
+F:	Documentation/devicetree/bindings/i2c/i2c-imx.txt
+
 FREESCALE IMX LPI2C DRIVER
 M:	Dong Aisheng <aisheng.dong@nxp.com>
 L:	linux-i2c@vger.kernel.org
-- 
2.20.1


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* Re: [linux-sunxi] [PATCH v5 1/3] arm64: dts: allwinner: Add SPDIF node for Allwinner H6
From: Chen-Yu Tsai @ 2019-08-12  4:52 UTC (permalink / raw)
  To: Clément Péron
  Cc: devicetree, Maxime Ripard, linux-kernel, linux-sunxi, Rob Herring,
	linux-arm-kernel
In-Reply-To: <20190811203144.5999-2-peron.clem@gmail.com>

Hi,

On Mon, Aug 12, 2019 at 4:31 AM Clément Péron <peron.clem@gmail.com> wrote:
>
> The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
>
> Only one pinmuxing is available so set it as default.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 7628a7c83096..677eb374678d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -83,6 +83,24 @@
>                 method = "smc";
>         };
>
> +       sound-spdif {
> +               compatible = "simple-audio-card";
> +               simple-audio-card,name = "sun50i-h6-spdif";
> +
> +               simple-audio-card,cpu {
> +                       sound-dai = <&spdif>;
> +               };
> +
> +               simple-audio-card,codec {
> +                       sound-dai = <&spdif_out>;
> +               };
> +       };
> +
> +       spdif_out: spdif-out {
> +               #sound-dai-cells = <0>;
> +               compatible = "linux,spdif-dit";
> +       };
> +

We've always had this part in the board dts. It isn't relevant to boards
that don't have SPDIF output.

Also, not so relevant here, but there are different simple sound card
constructs. Some support multiple audio streams with dynamic PCM routing.
How these are configured really depends on what interfaces are usable.

So keeping this at the board level is IMO a better choice.

ChenYu


>         timer {
>                 compatible = "arm,armv8-timer";
>                 interrupts = <GIC_PPI 13
> @@ -282,6 +300,11 @@
>                                 bias-pull-up;
>                         };
>
> +                       spdif_tx_pin: spdif-tx-pin {
> +                               pins = "PH7";
> +                               function = "spdif";
> +                       };
> +
>                         uart0_ph_pins: uart0-ph-pins {
>                                 pins = "PH0", "PH1";
>                                 function = "uart0";
> @@ -411,6 +434,21 @@
>                         };
>                 };
>
> +               spdif: spdif@5093000 {
> +                       #sound-dai-cells = <0>;
> +                       compatible = "allwinner,sun50i-h6-spdif";
> +                       reg = <0x05093000 0x400>;
> +                       interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> +                       clock-names = "apb", "spdif";
> +                       resets = <&ccu RST_BUS_SPDIF>;
> +                       dmas = <&dma 2>;
> +                       dma-names = "tx";
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&spdif_tx_pin>;
> +                       status = "disabled";
> +               };
> +
>                 usb2otg: usb@5100000 {
>                         compatible = "allwinner,sun50i-h6-musb",
>                                      "allwinner,sun8i-a33-musb";
> --
> 2.20.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190811203144.5999-2-peron.clem%40gmail.com.

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* RE: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
From: Biwen Li @ 2019-08-12  4:22 UTC (permalink / raw)
  To: Wolfram Sang, Leo Li
  Cc: shawnguo@kernel.org, s.hauer@pengutronix.de,
	linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
	dl-linux-imx, kernel@pengutronix.de, Laurentiu Tudor,
	festevam@gmail.com, linux-arm-kernel@lists.infradead.org,
	Joshua Frkuska
In-Reply-To: <20190809151035.GB5099@ninjato>

> On Fri, Aug 09, 2019 at 03:18:01AM +0000, Biwen Li wrote:
> > > > The patch supports slave mode for imx I2C driver
> > > >
> > > > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > >
> > > Wow, this is much simpler than the other approach flying around:
> > >
> > > http://patchwork.ozlabs.org/patch/1124048/
> > >
> > > Can this one be master and slave on the same bus, too?
> > At the same time, the same bus is in master mode or slave mode.
> 
> So, can someone kindly point out the key differences to me?
The I2C module cannot be a master and a slave simultaneously.
Such as: if the i2c module is used in slave mode with command
'echo slave-24c02 0x64 > /sys/bus/i2c/devices/i2c-0/new_device',
At the mean time, you cannot do master operations(i2cset/i2cget). 
You can switch mode from slave to master with command 'echo 0x64
 > /sys/bus/i2c/devices/i2c-0/delete_device', then you can do master
operations.

Adding Leo to this version too.

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* Re: [PATCH 2/2] arm64: allwinner: h6: enable i2c0 in PineH64
From: Chen-Yu Tsai @ 2019-08-12  4:19 UTC (permalink / raw)
  To: Bhushan Shah
  Cc: Mark Rutland, devicetree, Maxime Ripard, linux-kernel,
	Rob Herring, linux-arm-kernel, Icenowy Zheng
In-Reply-To: <20190811090503.32396-3-bshah@kde.org>

On Sun, Aug 11, 2019 at 5:05 PM Bhushan Shah <bshah@kde.org> wrote:
>
> i2c0 bus is exposed by PI-2 BUS in the PineH64, model B.
>
> Signed-off-by: Bhushan Shah <bshah@kde.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> index 684d1daa3081..a184361bc10d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> @@ -160,6 +160,14 @@
>         vcc-pg-supply = <&reg_aldo1>;
>  };
>
> +&i2c0 {
> +       status = "okay";

We don't enable interfaces that are exposed on the extension headers
by default. Instead we let the users enable it themselves, by modifying
the device tree either with overlays or through U-boot commands.

Please set this to "disabled", and add a comment mentioning that it is
on the PI-2 BUS. Having it explicitly listed in the source serves as a
pointer to people looking at how to enable stuff.

ChenYu

> +};
> +
> +&i2c0_pins {
> +       bias-pull-up;
> +};
> +
>  &r_i2c {
>         status = "okay";
>
> --
> 2.17.1
>

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* Re: [PATCH 1/2] arm64: allwinner: h6: add I2C nodes
From: Chen-Yu Tsai @ 2019-08-12  4:12 UTC (permalink / raw)
  To: Bhushan Shah
  Cc: Mark Rutland, devicetree, Maxime Ripard, linux-kernel,
	Rob Herring, linux-arm-kernel, Icenowy Zheng
In-Reply-To: <20190811090503.32396-2-bshah@kde.org>

On Sun, Aug 11, 2019 at 5:05 PM Bhushan Shah <bshah@kde.org> wrote:
>
> Add device-tree nodes for i2c0 to i2c2, and also add relevant pinctrl
> nodes.
>
> Suggested-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Bhushan Shah <bshah@kde.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++
>  1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index bcecca17d61d..1d9ad3ec0b65 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -329,6 +329,21 @@
>                                 function = "hdmi";
>                         };
>
> +                       i2c0_pins: i2c0-pins {
> +                               pins = "PD25", "PD26";
> +                               function = "i2c0";
> +                       };
> +
> +                       i2c1_pins: i2c1-pins {
> +                               pins = "PH5", "PH6";
> +                               function = "i2c1";
> +                       };
> +
> +                       i2c2_pins: i2c2-pins {
> +                               pins = "PD23", "PD24";
> +                               function = "i2c2";
> +                       };
> +
>                         mmc0_pins: mmc0-pins {
>                                 pins = "PF0", "PF1", "PF2", "PF3",
>                                        "PF4", "PF5";
> @@ -464,6 +479,45 @@
>                         status = "disabled";
>                 };
>
> +               i2c0: i2c@5002000 {
> +                       compatible = "allwinner,sun6i-a31-i2c";

Please add an soc-specific compatible string, like "allwinner,sun50i-h6-i2c".
This is a last-resort way out in case the hardware isn't so compatible with
the A31.

You'll also need to update the bindings in

    Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml

The file also shows that we do this for other chips, such as the A23,
A64 and A83T.

ChenYu

> +                       reg = <0x05002000 0x400>;
> +                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C0>;
> +                       resets = <&ccu RST_BUS_I2C0>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&i2c0_pins>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               i2c1: i2c@5002400 {
> +                       compatible = "allwinner,sun6i-a31-i2c";
> +                       reg = <0x05002400 0x400>;
> +                       interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C1>;
> +                       resets = <&ccu RST_BUS_I2C1>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&i2c1_pins>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               i2c2: i2c@5002800 {
> +                       compatible = "allwinner,sun6i-a31-i2c";
> +                       reg = <0x05002800 0x400>;
> +                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C2>;
> +                       resets = <&ccu RST_BUS_I2C2>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&i2c2_pins>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
>                 emac: ethernet@5020000 {
>                         compatible = "allwinner,sun50i-h6-emac",
>                                      "allwinner,sun50i-a64-emac";
> --
> 2.17.1
>

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* RE: [PATCH 1/4] dt-bindings: watchdog: Add i.MX7ULP bindings
From: Anson Huang @ 2019-08-12  2:03 UTC (permalink / raw)
  To: Guenter Roeck
  Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Leonard Crestez,
	schnitzeltony@gmail.com, linux-watchdog@vger.kernel.org,
	otavio@ossystems.com.br, festevam@gmail.com,
	s.hauer@pengutronix.de, jan.tuerk@emtrion.com,
	linux@armlinux.org.uk, linux-kernel@vger.kernel.org,
	robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de,
	u.kleine-koenig@pengutronix.de, wim@linux-watchdog.org,
	shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190809164245.GA17136@roeck-us.net>

Hi, Guenter

> On Fri, Aug 09, 2019 at 03:13:59PM +0800, Anson Huang wrote:
> > Add the watchdog bindings for Freescale i.MX7ULP.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> >  .../bindings/watchdog/fsl-imx7ulp-wdt.txt          | 22
> ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > new file mode 100644
> > index 0000000..d83fc5c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > @@ -0,0 +1,22 @@
> > +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,imx7ulp-wdt"
> > +- reg : Should contain WDT registers location and length
> > +- interrupts : Should contain WDT interrupt
> > +- clocks: Should contain a phandle pointing to the gated peripheral clock.
> 
> The driver as submitted does not include clock or interrupt handling.
> Why are those properties listed as mandatory if they are not really needed
> (nor used) ?

I missed the clk part in driver, it is working ONLY because the wdog clock is enabled
unexpected, I will add it in V2, thanks for pointing out such big mistake!

Anson

> 
> > +
> > +Optional properties:
> > +- timeout-sec : Contains the watchdog timeout in seconds
> > +
> > +Examples:
> > +
> > +wdog1: wdog@403d0000 {
> > +	compatible = "fsl,imx7ulp-wdt";
> > +	reg = <0x403d0000 0x10000>;
> > +	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> > +	clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > +	assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > +	assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
> > +	timeout-sec = <40>;
> > +};
> > --
> > 2.7.4
> >
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* RE: [PATCH 2/4] watchdog: Add i.MX7ULP watchdog support
From: Anson Huang @ 2019-08-12  1:41 UTC (permalink / raw)
  To: Guenter Roeck
  Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Leonard Crestez,
	schnitzeltony@gmail.com, linux-watchdog@vger.kernel.org,
	otavio@ossystems.com.br, festevam@gmail.com,
	s.hauer@pengutronix.de, jan.tuerk@emtrion.com,
	linux@armlinux.org.uk, linux-kernel@vger.kernel.org,
	robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de,
	u.kleine-koenig@pengutronix.de, wim@linux-watchdog.org,
	shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190809161956.GA6248@roeck-us.net>

Hi, Guenter

> On Fri, Aug 09, 2019 at 03:14:00PM +0800, Anson Huang wrote:
> > The i.MX7ULP Watchdog Timer (WDOG) module is an independent timer
> that
> > is available for system use.
> > It provides a safety feature to ensure that software is executing as
> > planned and that the CPU is not stuck in an infinite loop or executing
> > unintended code. If the WDOG module is not serviced
> > (refreshed) within a certain period, it resets the MCU.
> >
> > Add driver support for i.MX7ULP watchdog.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> >  drivers/watchdog/Kconfig       |  13 +++
> >  drivers/watchdog/Makefile      |   1 +
> >  drivers/watchdog/imx7ulp_wdt.c | 221
> > +++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 235 insertions(+)
> >  create mode 100644 drivers/watchdog/imx7ulp_wdt.c
> >
> > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index
> > 8188963..0884e53 100644
> > --- a/drivers/watchdog/Kconfig
> > +++ b/drivers/watchdog/Kconfig
> > @@ -740,6 +740,19 @@ config IMX_SC_WDT
> >  	  To compile this driver as a module, choose M here: the
> >  	  module will be called imx_sc_wdt.
> >
> > +config IMX7ULP_WDT
> > +	tristate "IMX7ULP Watchdog"
> > +	depends on ARCH_MXC || COMPILE_TEST
> > +	select WATCHDOG_CORE
> > +	help
> > +	  This is the driver for the hardware watchdog on the Freescale
> > +	  IMX7ULP and later processors. If you have one of these
> > +	  processors and wish to have watchdog support enabled,
> > +	  say Y, otherwise say N.
> > +
> > +	  To compile this driver as a module, choose M here: the
> > +	  module will be called imx7ulp_wdt.
> > +
> >  config UX500_WATCHDOG
> >  	tristate "ST-Ericsson Ux500 watchdog"
> >  	depends on MFD_DB8500_PRCMU
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index 7caa920..7d32537 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -69,6 +69,7 @@ obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o
> >  obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
> >  obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
> >  obj-$(CONFIG_IMX_SC_WDT) += imx_sc_wdt.o
> > +obj-$(CONFIG_IMX7ULP_WDT) += imx7ulp_wdt.o
> >  obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
> >  obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
> >  obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o diff --git
> > a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c
> new
> > file mode 100644 index 0000000..8d56023
> > --- /dev/null
> > +++ b/drivers/watchdog/imx7ulp_wdt.c
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2019 NXP.
> > + */
> > +
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reboot.h>
> > +#include <linux/watchdog.h>
> > +
> > +#define WDOG_CS			0x0
> > +#define WDOG_CS_CMD32EN		(1 << 13)
> > +#define WDOG_CS_ULK		(1 << 11)
> > +#define WDOG_CS_RCS		(1 << 10)
> > +#define WDOG_CS_EN		(1 << 7)
> > +#define WDOG_CS_UPDATE		(1 << 5)
> > +
> 
> Please use BIT() where appropriate.

Got it.

> 
> > +#define WDOG_CNT	0x4
> > +#define WDOG_TOVAL	0x8
> > +
> > +#define REFRESH_SEQ0	0xA602
> > +#define REFRESH_SEQ1	0xB480
> > +#define REFRESH		((REFRESH_SEQ1 << 16) | (REFRESH_SEQ0))
> 
> The inner ( ) are unnecessary. While I would accept it for readability for the
> first part, (REFRESH_SEQ0) really doesn't add value.

Got it.

> 
> > +
> > +#define UNLOCK_SEQ0	0xC520
> > +#define UNLOCK_SEQ1	0xD928
> > +#define UNLOCK		((UNLOCK_SEQ1 << 16) | (UNLOCK_SEQ0))
> 
> Same as above.

Got it.

> 
> > +
> > +#define DEFAULT_TIMEOUT 60
> > +#define MAX_TIMEOUT 128
> 
> tabs after _TIMEOUT, please

Got it.

> 
> > +
> > +static bool nowayout = WATCHDOG_NOWAYOUT;
> module_param(nowayout,
> > +bool, 0000); MODULE_PARM_DESC(nowayout, "Watchdog cannot be
> stopped
> > +once started (default="
> > +		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> > +
> > +struct imx7ulp_wdt_device {
> > +	struct notifier_block restart_handler;
> > +	struct watchdog_device wdd;
> > +	void __iomem *base;
> > +	int rate;
> > +};
> > +
> > +static inline void imx7ulp_wdt_enable(void __iomem *base, bool
> > +enable) {
> > +	u32 val = readl(base + WDOG_CS);
> > +
> > +	writel(UNLOCK, base + WDOG_CNT);
> > +	if (enable)
> > +		writel(val | WDOG_CS_EN, base + WDOG_CS);
> > +	else
> > +		writel(val & ~WDOG_CS_EN, base + WDOG_CS); }
> > +
> > +static inline bool imx7ulp_wdt_is_enabled(void __iomem *base) {
> > +	u32 val = readl(base + WDOG_CS);
> > +
> > +	return val & WDOG_CS_EN;
> > +}
> > +
> > +static int imx7ulp_wdt_ping(struct watchdog_device *wdog) {
> > +	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > +	writel(REFRESH, wdt->base + WDOG_CNT);
> > +
> > +	return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_start(struct watchdog_device *wdog) {
> > +	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > +	imx7ulp_wdt_enable(wdt->base, true);
> > +
> > +	return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_stop(struct watchdog_device *wdog) {
> > +	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > +	imx7ulp_wdt_enable(wdt->base, false);
> > +
> > +	return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
> > +				   unsigned int timeout)
> > +{
> > +	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +	u32 val = wdt->rate * timeout;
> > +
> > +	writel(UNLOCK, wdt->base + WDOG_CNT);
> > +	writel(val, wdt->base + WDOG_TOVAL);
> > +
> > +	wdog->timeout = timeout;
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct watchdog_ops imx7ulp_wdt_ops = {
> > +	.owner = THIS_MODULE,
> > +	.start = imx7ulp_wdt_start,
> > +	.stop  = imx7ulp_wdt_stop,
> > +	.ping  = imx7ulp_wdt_ping,
> > +	.set_timeout = imx7ulp_wdt_set_timeout, };
> > +
> > +static const struct watchdog_info imx7ulp_wdt_info = {
> > +	.identity = "i.MX7ULP watchdog timer",
> > +	.options  = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
> > +		    WDIOF_MAGICCLOSE,
> > +};
> > +
> > +static inline void imx7ulp_wdt_init(void __iomem *base, unsigned int
> > +timeout) {
> > +	u32 val;
> > +
> > +	/* unlock the wdog for reconfiguration */
> > +	writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
> > +	writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
> > +
> > +	/* set an initial timeout value in TOVAL */
> > +	writel(timeout, base + WDOG_TOVAL);
> > +	/* enable 32bit command sequence and reconfigure */
> > +	val = (1 << 13) | (1 << 8) | (1 << 5);
> 
> Please use BIT()

Got it.

> 
> > +	writel(val, base + WDOG_CS);
> > +}
> > +
> > +static int imx7ulp_wdt_probe(struct platform_device *pdev) {
> > +	struct imx7ulp_wdt_device *imx7ulp_wdt;
> > +	struct device *dev = &pdev->dev;
> > +	struct watchdog_device *wdog;
> > +	int ret;
> > +
> > +	imx7ulp_wdt = devm_kzalloc(&pdev->dev,
> > +				   sizeof(*imx7ulp_wdt), GFP_KERNEL);
> > +	if (!imx7ulp_wdt)
> > +		return -ENOMEM;
> > +
> > +	platform_set_drvdata(pdev, imx7ulp_wdt);
> > +
> > +	imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
> > +	if (IS_ERR(imx7ulp_wdt->base))
> > +		return PTR_ERR(imx7ulp_wdt->base);
> > +
> > +	imx7ulp_wdt->rate = 1000;
> > +	wdog = &imx7ulp_wdt->wdd;
> > +	wdog->info = &imx7ulp_wdt_info;
> > +	wdog->ops = &imx7ulp_wdt_ops;
> > +	wdog->min_timeout = 1;
> > +	wdog->max_timeout = MAX_TIMEOUT;
> > +	wdog->parent = dev;
> > +	wdog->timeout = DEFAULT_TIMEOUT;
> > +
> > +	watchdog_init_timeout(wdog, 0, dev);
> > +	watchdog_stop_on_reboot(wdog);
> > +	watchdog_stop_on_unregister(wdog);
> > +	watchdog_set_drvdata(wdog, imx7ulp_wdt);
> > +	imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout *
> > +imx7ulp_wdt->rate);
> > +
> > +	ret = devm_watchdog_register_device(dev, wdog);
> > +	if (ret)
> > +		dev_err(dev, "Failed to register watchdog device\n");
> 
> An error message is already displayed by the watchdog core.

Got it.

> 
> > +
> > +	return ret;
> > +}
> > +
> > +static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev) {
> > +	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
> > +
> > +	if (watchdog_active(&imx7ulp_wdt->wdd))
> > +		imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __maybe_unused imx7ulp_wdt_resume(struct device *dev) {
> > +	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
> > +	u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->rate;
> > +
> > +	if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
> > +		imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
> > +
> If I understand correctly, imx7ulp_wdt_is_enabled() returns true if the
> watchdog is running. Since it was stopped on suspend, that means that it was
> started in BIOS/rommon during resume.
> 
> With that, the above translates to "If the watchdog was started by
> BIOS/rommon, re-initialize it. Otherwise do nothing". This doesn't really
> make much sense to me. What if the watchdog was reprogrammed by the
> BIOS/rommon, but not started ? In other words, why not call
> imx7ulp_wdt_init() unconditionally ?

The i.MX7ULP hardware design is, if A7 domain is powered off during suspend (mem suspend),
watchdog will be always reset and re-started by boot ROM. If A7 domain is NOT powered off during
suspend (standby suspend), the watchdog does NOT lose context and boot ROM NOT
run again after resume. 

> 
> Also, if it is possible that the watchdog is started by BIOS/rommon, why not
> keep it enabled and tell the watchdog core about it in the probe function ?

There are 2 cases of watchdog status during suspend/resume, i.MX7ULP supports
both standby suspend and mem suspend, for mem suspend, the whole A7 domain
will be powered off, and after resume, watchdog will be re-started by boot ROM (BIOS),
while for standby suspend, the watchdog does NOT re-started by boot ROM, as A7
domain is NOT powered off. That is why I added the check here, since there are 2 cases
sharing same suspend/resume callback. Does it make sense to you?

Thanks,
Anson

> 
> > +	if (watchdog_active(&imx7ulp_wdt->wdd))
> > +		imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
> > +
> > +	return 0;
> > +}
> > +
> > +static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops,
> imx7ulp_wdt_suspend,
> > +			 imx7ulp_wdt_resume);
> > +
> > +static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
> > +	{ .compatible = "fsl,imx7ulp-wdt", },
> > +	{ /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
> > +
> > +static struct platform_driver imx7ulp_wdt_driver = {
> > +	.probe		= imx7ulp_wdt_probe,
> > +	.driver		= {
> > +		.name	= "imx7ulp-wdt",
> > +		.pm	= &imx7ulp_wdt_pm_ops,
> > +		.of_match_table = imx7ulp_wdt_dt_ids,
> > +	},
> > +};
> > +module_platform_driver(imx7ulp_wdt_driver);
> > +
> > +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
> > +MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.7.4
> >
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* Re: [PATCH] pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter
From: Andrew Jeffery @ 2019-08-12  0:51 UTC (permalink / raw)
  To: Linus Walleij, Nathan Chancellor
  Cc: linux-aspeed, clang-built-linux, OpenBMC Maillist,
	linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM,
	Joel Stanley, Linux ARM
In-Reply-To: <CACRpkdbDgOQXfxgM4dEyzBRhtske3=V+858B7J8jGExnJE5fJQ@mail.gmail.com>



On Sat, 10 Aug 2019, at 17:43, Linus Walleij wrote:
> On Wed, Aug 7, 2019 at 2:32 AM Nathan Chancellor
> <natechancellor@gmail.com> wrote:
> 
> > clang errors:
> >
> > drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible
> > pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const
> > struct aspeed_sig_expr *, bool)' with an expression of type 'int (const
> > struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)'
> > [-Werror,-Wincompatible-pointer-types]
> >         .set = aspeed_g6_sig_expr_set,
> >                ^~~~~~~~~~~~~~~~~~~~~~
> > 1 error generated.
> >
> > Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
> > changed the set function pointer declaration and the g6 one wasn't
> > updated (I assume because it wasn't merged yet).
> >
> > Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
> > Link: https://github.com/ClangBuiltLinux/linux/issues/632
> > Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
> 
> Patch applied with Andrew's ACK.

FYI this fixes pinctrl/for-next which is likely where Nathan ran into the issue,
however to fix pinctrl/devel we'll need a back-merge of pinctrl/fixes, or to
apply 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps") to
pinctrl/devel also.

Fixing that bug was unfortunate timing wrt the 2600 driver.

Andrew

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* [PATCH v2] ARM: dts: add device tree for Mecer Xtreme Mini S6
From: Justin Swartz @ 2019-08-11 23:00 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, Heiko Stuebner
  Cc: devicetree, Justin Swartz, linux-kernel, linux-arm-kernel,
	linux-rockchip

The Mecer Xtreme Mini S6 features a Rockchip RK3229 SoC,
1GB DDR3 RAM, 8GB eMMC, MicroSD port, 10/100Mbps Ethernet,
Realtek 8723BS WLAN module, 2 x USB 2.0 ports, HDMI output,
and S/PDIF output.

Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
---
 .../devicetree/bindings/arm/rockchip.yaml          |   5 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/rk3229-xms6.dts                  | 283 +++++++++++++++++++++
 4 files changed, 291 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3229-xms6.dts

diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 34865042f4e4..4abd91c2b0bd 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -329,6 +329,11 @@ properties:
               - khadas,edge-v
           - const: rockchip,rk3399
 
+      - description: Mecer Xtreme Mini S6
+        items:
+          - const: mecer,xms6
+          - const: rockchip,rk3229
+
       - description: mqmaker MiQi
         items:
           - const: mqmaker,miqi
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6992bbbbffab..97992fccfc3d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -549,6 +549,8 @@ patternProperties:
     description: mCube
   "^meas,.*":
     description: Measurement Specialties
+  "^mecer,.*":
+    description: Mustek Limited
   "^mediatek,.*":
     description: MediaTek Inc.
   "^megachips,.*":
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..4567c0b045c2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -905,6 +905,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3188-radxarock.dtb \
 	rk3228-evb.dtb \
 	rk3229-evb.dtb \
+	rk3229-xms6.dtb \
 	rk3288-evb-act8846.dtb \
 	rk3288-evb-rk808.dtb \
 	rk3288-fennec.dtb \
diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts
new file mode 100644
index 000000000000..4b6ab4954dd4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-xms6.dts
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "rk3229.dtsi"
+
+/ {
+	model = "Mecer Xtreme Mini S6";
+	compatible = "mecer,xms6", "rockchip,rk3229";
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	ext_gmac: ext_gmac {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+		#clock-cells = <0>;
+	};
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+
+	power-led {
+		compatible = "gpio-leds";
+
+		blue {
+			gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	vcc_host: vcc-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc_phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vccio_1v8>;
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vccio_1v8: vccio-1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vccio_3v3: vccio-3v3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_arm: vdd-arm-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_arm";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_log: vdd-log-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC_SRC>;
+	assigned-clock-rates = <50000000>;
+	clock_in_out = "output";
+	phy-supply = <&vcc_phy>;
+	phy-mode = "rmii";
+	phy-handle = <&phy>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: phy@0 {
+			compatible = "ethernet-phy-id1234.d400",
+			             "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			clocks = <&cru SCLK_MAC_PHY>;
+			resets = <&cru SRST_MACPHY>;
+			phy-is-integrated;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	vccio1-supply = <&vccio_3v3>;
+	vccio2-supply = <&vccio_1v8>;
+	vccio4-supply = <&vccio_3v3>;
+};
+
+&pinctrl {
+	usb {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdmmc {
+	cap-mmc-highspeed;
+	disable-wp;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&uart2 {
+	pinctrl-0 = <&uart21_xfer>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_ehci {
+	status = "okay";
+};
+
+&usb_host2_ohci {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
-- 
2.11.0


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* Re: [PATCH v5 00/18] add thermal driver for h6
From: Clément Péron @ 2019-08-11 21:14 UTC (permalink / raw)
  To: Yangtao Li, rui.zhang, edubezval, daniel.lezcano, robh+dt,
	mark.rutland, maxime.ripard, wens, mchehab+samsung, davem, gregkh,
	Jonathan.Cameron, nicolas.ferre
  Cc: devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>

Hi Yangtao,

On 10/08/2019 07:28, Yangtao Li wrote:
> This patchset add support for A64, H3, H5, H6 and R40 thermal sensor.

Could you add the device-tree configuration in the same series?
This will allow user to test it.

Thanks,
Clément

> 
> Thx to Icenowy and Vasily.
> 
> BTY, do a cleanup in thermal makfile.
> 
> Icenowy Zheng (3):
>    thermal: sun8i: allow to use custom temperature calculation function
>    thermal: sun8i: add support for Allwinner H5 thermal sensor
>    thermal: sun8i: add support for Allwinner R40 thermal sensor
> 
> Vasily Khoruzhick (1):
>    thermal: sun8i: add thermal driver for A64
> 
> Yangtao Li (14):
>    thermal: sun8i: add thermal driver for h6
>    dt-bindings: thermal: add binding document for h6 thermal controller
>    thermal: fix indentation in makefile
>    thermal: sun8i: get ths sensor number from device compatible
>    thermal: sun8i: rework for sun8i_ths_get_temp()
>    thermal: sun8i: get ths init func from device compatible
>    thermal: sun8i: rework for ths irq handler func
>    thermal: sun8i: support mod clocks
>    thermal: sun8i: rework for ths calibrate func
>    dt-bindings: thermal: add binding document for h3 thermal controller
>    thermal: sun8i: add thermal driver for h3
>    dt-bindings: thermal: add binding document for a64 thermal controller
>    dt-bindings: thermal: add binding document for h5 thermal controller
>    dt-bindings: thermal: add binding document for r40 thermal controller
> 
>   .../bindings/thermal/sun8i-thermal.yaml       | 157 +++++
>   MAINTAINERS                                   |   7 +
>   drivers/thermal/Kconfig                       |  14 +
>   drivers/thermal/Makefile                      |   9 +-
>   drivers/thermal/sun8i_thermal.c               | 596 ++++++++++++++++++
>   5 files changed, 779 insertions(+), 4 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
>   create mode 100644 drivers/thermal/sun8i_thermal.c
> ---
> v5:
> -add more support
> -some trival fix
> ---
> 2.17.1
> 
> 

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* Re: [PATCH v4 0/4] Add drivers for auo, kd101n80-45na and boe, tv101wum-nl6 panels
From: Sam Ravnborg @ 2019-08-11 21:11 UTC (permalink / raw)
  To: Jitao Shi
  Cc: Mark Rutland, devicetree, David Airlie, stonea168, dri-devel,
	Ajay Kumar, Vincent Palatin, cawa.cheng, yingjoe.chen,
	Thierry Reding, Sean Paul, linux-pwm, Pawel Moll, Ian Campbell,
	Rob Herring, linux-mediatek, Russell King, Matthias Brugger,
	eddie.huang, linux-arm-kernel, Rahul Sharma, srv_heupstream,
	linux-kernel, Sascha Hauer, Andy Yan
In-Reply-To: <20190811091001.49555-1-jitao.shi@mediatek.com>

Hi Jitao.

>  .../display/panel/auo,kd101n80-45na.txt       |  34 +
>  .../display/panel/boe,tv101wum-nl6.txt        |  34 +

panel bindings are in the process of being migrated to the new
meta-schema format.
Therefore new bindings should preferably also follow the new format.

Can you please look into this.
In upstream and drm-misc-next there is already some examples.

Note: It is not a hard rule that new bindings shall be in
the new meta-schema format (.yaml extension), but as this is
best practice now it is preferred.
Same goes for display bindings btw.

	Sam

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