* Re: [PATCH 04/18] ARM: dts: bcm283x: Define MMC interfaces at board level
From: Stefan Wahren @ 2019-08-12 21:03 UTC (permalink / raw)
To: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Nicolas Saenz Julienne, Matthias Brugger, Rob Herring,
Mark Rutland, Linus Walleij, Michael Turquette, Stephen Boyd,
Ulf Hansson, Adrian Hunter
Cc: linux-gpio, linux-mmc, linux-rpi-kernel, linux-arm-kernel,
bcm-kernel-feedback-list
In-Reply-To: <1563774880-8061-5-git-send-email-wahrenst@gmx.net>
Am 22.07.19 um 07:54 schrieb Stefan Wahren:
> Starting with RPi 4 this is the first board, which doesn't use sdhost
> as default SD interface. So the MMC interfaces should be defined finally at
> board level. Since all boards using sdhci already does this, we can drop the
> pinctrl part from bcm2835-rpi.dtsi.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Applied to bcm2835-dt-next
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* Re: [PATCH 05/18] ARM: dts: bcm283x: Define memory at board level
From: Stefan Wahren @ 2019-08-12 21:02 UTC (permalink / raw)
To: Eric Anholt, Florian Fainelli, Ray Jui, Scott Branden,
Nicolas Saenz Julienne, Matthias Brugger, Rob Herring,
Mark Rutland, Linus Walleij, Michael Turquette, Stephen Boyd,
Ulf Hansson, Adrian Hunter
Cc: linux-gpio, linux-mmc, linux-rpi-kernel, linux-arm-kernel,
bcm-kernel-feedback-list
In-Reply-To: <1563774880-8061-6-git-send-email-wahrenst@gmx.net>
Am 22.07.19 um 07:54 schrieb Stefan Wahren:
> Now with the varity of several RPi boards, the memory should be defined
> at board level. This step gives us the chance to fix the memory size
> of the RPi 1 B+, Zero (incl. W) and Compute Module 1.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Applied to bcm2835-dt-next
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* RE: [PATCH] arm64: dts: ls1028a: fix gpio nodes
From: Leo Li @ 2019-08-12 21:01 UTC (permalink / raw)
To: Shawn Guo, Hui Song
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Linus Walleij,
linux-kernel@vger.kernel.org, Bartosz Golaszewski, Rob Herring,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190812134716.GF27041@X250>
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, August 12, 2019 8:47 AM
> To: Hui Song <hui.song_1@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Linus Walleij <linus.walleij@linaro.org>; Bartosz
> Golaszewski <bgolaszewski@baylibre.com>; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org
> Subject: Re: [PATCH] arm64: dts: ls1028a: fix gpio nodes
>
> On Mon, Aug 05, 2019 at 02:57:00PM +0800, Hui Song wrote:
> > From: Song Hui <hui.song_1@nxp.com>
> >
> > Update the nodes to include little-endian property to be consistent
> > with the hardware.
> >
> > Signed-off-by: Song Hui <hui.song_1@nxp.com>
>
> @Leo, looks good?
Acked-by: Li Yang <leoyang.li@nxp.com>
>
> Shawn
>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 ++++++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index aef5b06..7ccbbfc 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -277,33 +277,36 @@
> > };
> >
> > gpio1: gpio@2300000 {
> > - compatible = "fsl,qoriq-gpio";
> > + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
> > reg = <0x0 0x2300000 0x0 0x10000>;
> > interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > + little-endian;
> > };
> >
> > gpio2: gpio@2310000 {
> > - compatible = "fsl,qoriq-gpio";
> > + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
> > reg = <0x0 0x2310000 0x0 0x10000>;
> > interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > + little-endian;
> > };
> >
> > gpio3: gpio@2320000 {
> > - compatible = "fsl,qoriq-gpio";
> > + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
> > reg = <0x0 0x2320000 0x0 0x10000>;
> > interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > + little-endian;
> > };
> >
> > usb0: usb@3100000 {
> > --
> > 2.9.5
> >
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* RE: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
From: Leo Li @ 2019-08-12 20:59 UTC (permalink / raw)
To: Shawn Guo, Chuanhua Han
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
robh+dt@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190812141722.GJ27041@X250>
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, August 12, 2019 9:17 AM
> To: Chuanhua Han <chuanhua.han@nxp.com>
> Cc: Leo Li <leoyang.li@nxp.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/4] arm64: dts: ls1088a: Fix incorrect I2C clock divider
>
> On Tue, Aug 06, 2019 at 04:42:20PM +0800, Chuanhua Han wrote:
> > Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
> > (this is the hardware connection), other clock divider can not get the
> > correct i2c clock, resulting in the output of SCL pin clock is not
> > accurate.
> >
> > Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
>
> @Leo, looks good?
Yes.
Acked-by: Li Yang <leoyang.li@nxp.com>
>
> Shawn
>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > index 20f5ebd..30b760e 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> > @@ -324,7 +324,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2000000 0x0 0x10000>;
> > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -334,7 +334,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2010000 0x0 0x10000>;
> > interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -344,7 +344,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2020000 0x0 0x10000>;
> > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > @@ -354,7 +354,7 @@
> > #size-cells = <0>;
> > reg = <0x0 0x2030000 0x0 0x10000>;
> > interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&clockgen 4 3>;
> > + clocks = <&clockgen 4 7>;
> > status = "disabled";
> > };
> >
> > --
> > 2.9.5
> >
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* Re: [PATCH] arm64: cpufeature: Don't treat granule sizes as strict
From: Kevin Hilman @ 2019-08-12 20:57 UTC (permalink / raw)
To: Will Deacon, linux-arm-kernel
Cc: Mark Rutland, Suzuki Poulose, Marc Zyngier, Catalin Marinas,
linux-amlogic, Will Deacon
In-Reply-To: <20190812150225.25386-1-will@kernel.org>
Will Deacon <will@kernel.org> writes:
> If a CPU doesn't support the page size for which the kernel is
> configured, then we will complain and refuse to bring it online. For
> secondary CPUs (and the boot CPU on a system booting with EFI), we will
> also print an error identifying the mismatch.
>
> Consequently, the only time that the cpufeature code can detect a
> granule size mismatch is for a granule other than the one that is
> currently being used. Although we would rather such systems didn't
> exist, we've unfortunately lost that battle and Kevin reports that
> on his amlogic S922X (odroid-n2 board) we end up warning and taining
> with defconfig because 16k pages are not supported by all of the CPUs.
>
> In such a situation, we don't actually care about the feature mismatch,
> particularly now that KVM only exposes the sanitised view of the CPU
> registers. Treat the granule fields as non-strict and let Kevin run
> without a tainted kernel.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Kevin Hilman <khilman@baylibre.com>
> Signed-off-by: Will Deacon <will@kernel.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Thanks for the fix Will!
Kevin
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* Re: [PATCH 0/6] arm64: g12a: add support for DVFS
From: Kevin Hilman @ 2019-08-12 20:54 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <7hk1bn43fq.fsf@baylibre.com>
Kevin Hilman <khilman@baylibre.com> writes:
> Kevin Hilman <khilman@baylibre.com> writes:
>
>> Neil Armstrong <narmstrong@baylibre.com> writes:
>>
>>> The G12A & G12B SoCs has kernel controllable CPU clocks and PWMs for
>>> voltage regulators.
>>>
>>> This patchsets moves the meson-g12a.dtsi to meson-g12-common.dtsi to simplify
>>> handling the G12A & G12B differences in the meson-g12a.dtsi & meson-g12b.dtsi
>>> files, like the OPPs and CPU nodes.
>>>
>>> Then G12A & G12B OPP tables are added, followed by the CPU voltages regulators
>>> in each boards DT.
>>>
>>> It was voluntary chosen to enabled DVFS (CPU regulator and CPU clocks) only
>>> in boards, to make sure only tested boards has DVFS enabled.
>>>
>>> This patchset :
>>> - moves the G12A DT to a common g12a-common dtsi
>>> - adds the G12A and G12B OPPs
>>> - enables DVFS on all supported boards
>>>
>>> Dependencies:
>>> - None
>>
>> Not quite. The last patch to enable DVFS on odroid-n2 has a build-time
>> dependency on the clock series that adds the CPUB clock.
>>
>> I'll apply the rest of the series to v5.4/dt64 until there's a stable
>> clock tag I can use for the clocks.
>
> In order to test this, I noticed another dependency needed for the PWM
> regulators to work:
>
> https://lore.kernel.org/linux-amlogic/20190729125838.6498-1-narmstrong@baylibre.com/
>
> With that and the clock deps, it's working well on my odroid-n2.
>
> Tested-by: Kevin Hilman <khilman@baylibre.com>
After merging Jerome's tag for clk DT, I've queued this for v5.4,
Thanks,
Kevin
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* Re: [PATCH 1/2] dts: add vendor prefix "acme" for "Acme Systems srl"
From: Alexandre Belloni @ 2019-08-12 20:54 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Mark Rutland, devicetree, Ludovic Desroches, Rob Herring, info,
linux-arm-kernel
In-Reply-To: <20190728210403.2730-2-uwe@kleine-koenig.org>
On 28/07/2019 23:04:02+0200, Uwe Kleine-König wrote:
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH 0/1] ARM: dts: meson8b: persistent MAC address for Odroid-C1
From: Kevin Hilman @ 2019-08-12 20:47 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: narmstrong, ottuzzi, linux-kernel, Martin Blumenstingl,
linux-arm-kernel
In-Reply-To: <20190812175004.24943-1-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> This series makes Odroid-C1 use the MAC address which is programmed into
> the eFuse.
>
> build-time dependencies:
> none
>
> runtime dependencies (without these a random MAC address is assigned,
> just like before these patches), both are already part of -next:
> - "nvmem: meson-mx-efuse: allow reading data smaller than word_size"
> from [1]
> - "net: stmmac: manage errors returned by of_get_mac_address()" from [1]
>
>
> Changes since v1 at [2]:
> - only add the nvmem cell to meson8b-odroidc1.dts as suggested by Neil.
> It turns out that neither MXQ and EC-100 have the MAC address in eFuse
> (which means only 1/3 boards has it at the given eFuse offset, so it's
> not worth having it the common .dtsi)
>
> Kevin: you already have v1 of this series in your tree. Feel free to
> replace the two patches from v1 with this single one.
Replaced. Thanks for the update.
Kevin
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* Re: [PATCH v2] arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
From: Kevin Hilman @ 2019-08-12 20:31 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-amlogic, Christian Hewitt, linux-kernel, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190812074857.8133-1-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> From: Christian Hewitt <christianshewitt@gmail.com>
>
> The Khadas VIM3 uses the Amlogic S922X or A311S SoC, both based on the
> Amlogic G12B SoC family, on a board with the same form factor as the
> VIM/VIM2 models. It ships in two variants; basic and
> pro which differ in RAM and eMMC size:
>
> - 2GB (basic) or 4GB (pro) LPDDR4 RAM
> - 16GB (basic) or 32GB (pro) eMMC 5.1 storage
> - 16MB SPI flash
> - 10/100/1000 Base-T Ethernet
> - AP6398S Wireless (802.11 a/b/g/n/ac, BT5.0)
> - HDMI 2.1 video
> - 1x USB 2.0 + 1x USB 3.0 ports
> - 1x USB-C (power) with USB 2.0 OTG
> - 3x LED's (1x red, 1x blue, 1x white)
> - 3x buttons (power, function, reset)
> - IR receiver
> - M2 socket with PCIe, USB, ADC & I2C
> - 40pin GPIO Header
> - 1x micro SD card slot
>
> A common meson-g12b-khadas-vim3.dtsi is added to support both S922X and
> A311D SoCs supported by two variants of the board.
>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This still has a build-time dependency on the CPUB clock patch.
Looks like Jerome has sent a PR w/tag today that includes that, so I'll
merge that tag and then queue this patch.
Thanks,
Kevin
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* Re: [PATCH v3 4/4] perf: Use CAP_SYS_ADMIN instead of euid==0 with ftrace
From: Arnaldo Carvalho de Melo @ 2019-08-12 20:29 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20190812202706.GH9280@kernel.org>
Em Mon, Aug 12, 2019 at 05:27:06PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Mon, Aug 12, 2019 at 05:22:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Wed, Aug 07, 2019 at 10:44:17AM -0400, Igor Lubashev escreveu:
> > > @@ -281,7 +283,7 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> > > .events = POLLIN,
> > > };
> > >
> > > - if (geteuid() != 0) {
> > > + if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> > > pr_err("ftrace only works for root!\n");
> >
> > I guess we should update the error message too?
> >
>
> I.e. I applied this as a follow up patch:
>
> diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
> index 01a5bb58eb04..ba8b65c2f9dc 100644
> --- a/tools/perf/builtin-ftrace.c
> +++ b/tools/perf/builtin-ftrace.c
> @@ -284,7 +284,12 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> };
>
> if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> - pr_err("ftrace only works for root!\n");
> + pr_err("ftrace only works for %s!\n",
> +#ifdef HAVE_LIBCAP_SUPPORT
> + "users with the SYS_ADMIN capability"
> +#else
> + "root"
> +#endif
);
:-)
> return -1;
> }
>
I've pushed the whole set to my tmp.perf/cap branch, please chec
- Arnaldo
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* Re: [PATCH v3 4/4] perf: Use CAP_SYS_ADMIN instead of euid==0 with ftrace
From: Arnaldo Carvalho de Melo @ 2019-08-12 20:27 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20190812202251.GG9280@kernel.org>
Em Mon, Aug 12, 2019 at 05:22:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Wed, Aug 07, 2019 at 10:44:17AM -0400, Igor Lubashev escreveu:
> > Kernel requires CAP_SYS_ADMIN instead of euid==0 to mount debugfs for ftrace.
> > Make perf do the same.
> >
> > Signed-off-by: Igor Lubashev <ilubashe@akamai.com>
> > ---
> > tools/perf/builtin-ftrace.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
> > index ae1466aa3b26..d09eac8a6d57 100644
> > --- a/tools/perf/builtin-ftrace.c
> > +++ b/tools/perf/builtin-ftrace.c
> > @@ -13,6 +13,7 @@
> > #include <signal.h>
> > #include <fcntl.h>
> > #include <poll.h>
> > +#include <linux/capability.h>
> >
> > #include "debug.h"
> > #include <subcmd/parse-options.h>
> > @@ -21,6 +22,7 @@
> > #include "target.h"
> > #include "cpumap.h"
> > #include "thread_map.h"
> > +#include "util/cap.h"
> > #include "util/config.h"
> >
> >
> > @@ -281,7 +283,7 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> > .events = POLLIN,
> > };
> >
> > - if (geteuid() != 0) {
> > + if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> > pr_err("ftrace only works for root!\n");
>
> I guess we should update the error message too?
>
I.e. I applied this as a follow up patch:
diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
index 01a5bb58eb04..ba8b65c2f9dc 100644
--- a/tools/perf/builtin-ftrace.c
+++ b/tools/perf/builtin-ftrace.c
@@ -284,7 +284,12 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
};
if (!perf_cap__capable(CAP_SYS_ADMIN)) {
- pr_err("ftrace only works for root!\n");
+ pr_err("ftrace only works for %s!\n",
+#ifdef HAVE_LIBCAP_SUPPORT
+ "users with the SYS_ADMIN capability"
+#else
+ "root"
+#endif
return -1;
}
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* Re: [PATCH v3 4/4] perf: Use CAP_SYS_ADMIN instead of euid==0 with ftrace
From: Arnaldo Carvalho de Melo @ 2019-08-12 20:22 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <bd8763b72ed4d58d0b42d44fbc7eb474d32e53a3.1565188228.git.ilubashe@akamai.com>
Em Wed, Aug 07, 2019 at 10:44:17AM -0400, Igor Lubashev escreveu:
> Kernel requires CAP_SYS_ADMIN instead of euid==0 to mount debugfs for ftrace.
> Make perf do the same.
>
> Signed-off-by: Igor Lubashev <ilubashe@akamai.com>
> ---
> tools/perf/builtin-ftrace.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
> index ae1466aa3b26..d09eac8a6d57 100644
> --- a/tools/perf/builtin-ftrace.c
> +++ b/tools/perf/builtin-ftrace.c
> @@ -13,6 +13,7 @@
> #include <signal.h>
> #include <fcntl.h>
> #include <poll.h>
> +#include <linux/capability.h>
>
> #include "debug.h"
> #include <subcmd/parse-options.h>
> @@ -21,6 +22,7 @@
> #include "target.h"
> #include "cpumap.h"
> #include "thread_map.h"
> +#include "util/cap.h"
> #include "util/config.h"
>
>
> @@ -281,7 +283,7 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> .events = POLLIN,
> };
>
> - if (geteuid() != 0) {
> + if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> pr_err("ftrace only works for root!\n");
I guess we should update the error message too?
> return -1;
> }
> --
> 2.7.4
--
- Arnaldo
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^ permalink raw reply
* Re: [PATCH v3 2/4] perf: Use CAP_SYS_ADMIN with perf_event_paranoid checks
From: Arnaldo Carvalho de Melo @ 2019-08-12 20:15 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20190812200134.GE9280@kernel.org>
Em Mon, Aug 12, 2019 at 05:01:34PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Wed, Aug 07, 2019 at 10:44:15AM -0400, Igor Lubashev escreveu:
> > +++ b/tools/perf/util/evsel.c
> > @@ -279,7 +279,7 @@ struct evsel *perf_evsel__new_idx(struct perf_event_attr *attr, int idx)
>
> > static bool perf_event_can_profile_kernel(void)
> > {
> > - return geteuid() == 0 || perf_event_paranoid() == -1;
> > + return perf_event_paranoid_check(-1);
> > }
>
> While looking at your changes I think the pre-existing code is wrong,
> i.e. the check in sys_perf_event_open(), in the kernel is:
>
> if (!attr.exclude_kernel) {
> if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
> return -EACCES;
> }
>
> And:
>
> static inline bool perf_paranoid_kernel(void)
> {
> return sysctl_perf_event_paranoid > 1;
> }
>
> So we have to change that perf_event_paranoit_check(-1) to pass 1
> instead?
>
> bool perf_event_paranoid_check(int max_level)
> {
> return perf_cap__capable(CAP_SYS_ADMIN) ||
> perf_event_paranoid() <= max_level;
> }
>
> Also you defined perf_cap__capable(anything) as:
>
> #ifdef HAVE_LIBCAP_SUPPORT
>
> #include <sys/capability.h>
>
> bool perf_cap__capable(cap_value_t cap);
>
> #else
>
> static inline bool perf_cap__capable(int cap __maybe_unused)
> {
> return false;
> }
>
> #endif /* HAVE_LIBCAP_SUPPORT */
>
>
> I think we should have:
>
> #else
>
> static inline bool perf_cap__capable(int cap __maybe_unused)
> {
> return geteuid() == 0;
> }
>
> #endif /* HAVE_LIBCAP_SUPPORT */
>
> Right?
>
> So I am removing the introduction of perf_cap__capable() from the first
> patch you sent, leaving it with _only_ the feature detection part, using
> that feature detection to do anything is then moved to a separate patch,
> after we finish this discussion about what we should fallback to when
> libcap-devel isn't available, i.e. we should use the previous checks,
> etc.
So, please take a look at the tmp.perf/cap branch in my git repo:
https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/log/?h=tmp.perf/cap
I split the patch and made perf_cap__capable() fallback to 'return
geteuid() == 0;' when libcap-devel isn't available, i.e. keep the
checks made prior to your patchset.
Jiri, can I keep your Acked-by?
- Arnaldo
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^ permalink raw reply
* Re: [PATCH v3 2/4] perf: Use CAP_SYS_ADMIN with perf_event_paranoid checks
From: Arnaldo Carvalho de Melo @ 2019-08-12 20:01 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <ad56df5452eeafb99dda9fc3d30f0f487aace503.1565188228.git.ilubashe@akamai.com>
Em Wed, Aug 07, 2019 at 10:44:15AM -0400, Igor Lubashev escreveu:
> +++ b/tools/perf/util/evsel.c
> @@ -279,7 +279,7 @@ struct evsel *perf_evsel__new_idx(struct perf_event_attr *attr, int idx)
> static bool perf_event_can_profile_kernel(void)
> {
> - return geteuid() == 0 || perf_event_paranoid() == -1;
> + return perf_event_paranoid_check(-1);
> }
While looking at your changes I think the pre-existing code is wrong,
i.e. the check in sys_perf_event_open(), in the kernel is:
if (!attr.exclude_kernel) {
if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
return -EACCES;
}
And:
static inline bool perf_paranoid_kernel(void)
{
return sysctl_perf_event_paranoid > 1;
}
So we have to change that perf_event_paranoit_check(-1) to pass 1
instead?
bool perf_event_paranoid_check(int max_level)
{
return perf_cap__capable(CAP_SYS_ADMIN) ||
perf_event_paranoid() <= max_level;
}
Also you defined perf_cap__capable(anything) as:
#ifdef HAVE_LIBCAP_SUPPORT
#include <sys/capability.h>
bool perf_cap__capable(cap_value_t cap);
#else
static inline bool perf_cap__capable(int cap __maybe_unused)
{
return false;
}
#endif /* HAVE_LIBCAP_SUPPORT */
I think we should have:
#else
static inline bool perf_cap__capable(int cap __maybe_unused)
{
return geteuid() == 0;
}
#endif /* HAVE_LIBCAP_SUPPORT */
Right?
So I am removing the introduction of perf_cap__capable() from the first
patch you sent, leaving it with _only_ the feature detection part, using
that feature detection to do anything is then moved to a separate patch,
after we finish this discussion about what we should fallback to when
libcap-devel isn't available, i.e. we should use the previous checks,
etc.
- Arnaldo
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^ permalink raw reply
* [PATCH v3] coresight: Serialize enabling/disabling a link device.
From: Yabin Cui @ 2019-08-12 19:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Yabin Cui, linux-kernel, linux-arm-kernel
When tracing etm data of multiple threads on multiple cpus through perf
interface, some link devices are shared between paths of different cpus.
It creates race conditions when different cpus wants to enable/disable
the same link device at the same time.
Example 1:
Two cpus want to enable different ports of a coresight funnel, thus
calling the funnel enable operation at the same time. But the funnel
enable operation isn't reentrantable.
Example 2:
For an enabled coresight dynamic replicator with refcnt=1, one cpu wants
to disable it, while another cpu wants to enable it. Ideally we still have
an enabled replicator with refcnt=1 at the end. But in reality the result
is uncertain.
Since coresight devices claim themselves when enabled for self-hosted
usage, the race conditions above usually make the link devices not usable
after many cycles.
To fix the race conditions, this patch adds a spinlock to serialize
enabling/disabling a link device.
Fixes: a06ae8609b3d ("coresight: add CoreSight core layer framework")
Signed-off-by: Yabin Cui <yabinc@google.com>
---
v2 -> v3: extend lock range to protect csdev->enable for link devices.
Add fixes tag.
---
drivers/hwtracing/coresight/coresight.c | 12 +++++++++++-
include/linux/coresight.h | 3 +++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 55db77f6410b..c069ada151b8 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -256,6 +256,7 @@ static int coresight_enable_link(struct coresight_device *csdev,
int ret;
int link_subtype;
int refport, inport, outport;
+ unsigned long flags;
if (!parent || !child)
return -EINVAL;
@@ -274,17 +275,20 @@ static int coresight_enable_link(struct coresight_device *csdev,
if (refport < 0)
return refport;
+ spin_lock_irqsave(&csdev->spinlock, flags);
if (atomic_inc_return(&csdev->refcnt[refport]) == 1) {
if (link_ops(csdev)->enable) {
ret = link_ops(csdev)->enable(csdev, inport, outport);
if (ret) {
atomic_dec(&csdev->refcnt[refport]);
+ spin_unlock_irqrestore(&csdev->spinlock, flags);
return ret;
}
}
}
csdev->enable = true;
+ spin_unlock_irqrestore(&csdev->spinlock, flags);
return 0;
}
@@ -296,6 +300,7 @@ static void coresight_disable_link(struct coresight_device *csdev,
int i, nr_conns;
int link_subtype;
int refport, inport, outport;
+ unsigned long flags;
if (!parent || !child)
return;
@@ -315,16 +320,20 @@ static void coresight_disable_link(struct coresight_device *csdev,
nr_conns = 1;
}
+ spin_lock_irqsave(&csdev->spinlock, flags);
if (atomic_dec_return(&csdev->refcnt[refport]) == 0) {
if (link_ops(csdev)->disable)
link_ops(csdev)->disable(csdev, inport, outport);
}
for (i = 0; i < nr_conns; i++)
- if (atomic_read(&csdev->refcnt[i]) != 0)
+ if (atomic_read(&csdev->refcnt[i]) != 0) {
+ spin_unlock_irqrestore(&csdev->spinlock, flags);
return;
+ }
csdev->enable = false;
+ spin_unlock_irqrestore(&csdev->spinlock, flags);
}
static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
@@ -1225,6 +1234,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc)
csdev->subtype = desc->subtype;
csdev->ops = desc->ops;
csdev->orphan = false;
+ spin_lock_init(&csdev->spinlock);
csdev->dev.type = &coresight_dev_type[desc->type];
csdev->dev.groups = desc->groups;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index a2b68823717b..dd28d9ab841d 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -9,6 +9,7 @@
#include <linux/device.h>
#include <linux/perf_event.h>
#include <linux/sched.h>
+#include <linux/spinlock.h>
/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4 0xfd0
@@ -153,6 +154,7 @@ struct coresight_connection {
* activated but not yet enabled. Enabling for a _sink_
* appens when a source has been selected for that it.
* @ea: Device attribute for sink representation under PMU directory.
+ * @spinlock: Serialize enabling/disabling this device.
*/
struct coresight_device {
struct coresight_platform_data *pdata;
@@ -166,6 +168,7 @@ struct coresight_device {
/* sink specific fields */
bool activated; /* true only if a sink is part of a path */
struct dev_ext_attribute *ea;
+ spinlock_t spinlock;
};
/*
--
2.23.0.rc1.153.gdeed80330f-goog
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^ permalink raw reply related
* Re: [PATCH] coresight: tmc-etr: Fix updating buffer in not-snapshot mode.
From: Mathieu Poirier @ 2019-08-12 19:52 UTC (permalink / raw)
To: Yabin Cui
Cc: Alexander Shishkin, Linux Kernel Mailing List, linux-arm-kernel,
Suzuki K Poulose
In-Reply-To: <20190805233738.136357-1-yabinc@google.com>
Good day Yabin,
With this patch you are addressing a long time itch I had - please read on.
On Mon, 5 Aug 2019 at 17:37, Yabin Cui <yabinc@google.com> wrote:
>
> TMC etr always copies all available data to perf aux buffer, which
> may exceed the available space in perf aux buffer. It isn't suitable
> for not-snapshot mode, because:
> 1) It may overwrite previously written data.
> 2) It may make the perf_event_mmap_page->aux_head report having more
> or less data than the reality.
>
> Signed-off-by: Yabin Cui <yabinc@google.com>
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 17006705287a..697e68d492af 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1410,9 +1410,10 @@ static void tmc_free_etr_buffer(void *config)
> * tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware
> * buffer to the perf ring buffer.
> */
> -static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
> +static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
> + unsigned long to_copy)
> {
> - long bytes, to_copy;
> + long bytes;
> long pg_idx, pg_offset, src_offset;
> unsigned long head = etr_perf->head;
> char **dst_pages, *src_buf;
> @@ -1423,7 +1424,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf)
> pg_offset = head & (PAGE_SIZE - 1);
> dst_pages = (char **)etr_perf->pages;
> src_offset = etr_buf->offset;
> - to_copy = etr_buf->len;
>
> while (to_copy > 0) {
> /*
> @@ -1501,7 +1501,11 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> size = etr_buf->len;
> - tmc_etr_sync_perf_buffer(etr_perf);
> + if (!etr_perf->snapshot && size > handle->size) {
> + size = handle->size;
> + lost = true;
> + }
Perfect - this is in line with what is done for ETB and ETF.
> + tmc_etr_sync_perf_buffer(etr_perf, size);
Here tmc_etr_sync_perf_buffer() will copy data to the perf ring buffer
starting at @etr_perf->offset for @size, clipping the _end_ of the
trace data accumulated in the trace buffer. This is contrary to what
is done for ETB and ETF where the equivalent of @etr_perf->offset is
moved forward (clipping the _beginning_ of the trace data) in order to
keep as much of the end as possible.
I would rather enact the same heuristic here.
Thanks,
Mathieu
>
> /*
> * In snapshot mode we simply increment the head by the number of byte
> --
> 2.22.0.770.g0f2c4a37fd-goog
>
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^ permalink raw reply
* Re: [PATCH 4/7] dt-bindings: devfreq: Add bindings for imx ddr controller
From: Rob Herring @ 2019-08-12 19:51 UTC (permalink / raw)
To: Leonard Crestez
Cc: Mark Rutland, Artur Świgoń, Jacky Bai, Viresh Kumar,
Michael Turquette, Alexandre Bailon, Will Deacon, Abel Vesa,
Saravana Kannan, Krzysztof Kozlowski, Chanwoo Choi, MyungJoo Ham,
NXP Linux Team, devicetree, open list:THERMAL,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Dong Aisheng, Anson Huang, Stephen Boyd, Kyungmin Park,
Sascha Hauer, Fabio Estevam, Shawn Guo, Georgi Djakov
In-Reply-To: <4cbddd75652c63aab19866c93faa0b784b56d53f.1565633880.git.leonard.crestez@nxp.com>
On Mon, Aug 12, 2019 at 12:50 PM Leonard Crestez
<leonard.crestez@nxp.com> wrote:
>
> Add devicetree bindings for the i.MX DDR Controller on imx8m series
> chips. It supports dynamic frequency switching between multiple data
> rates and this is exposed to Linux via the devfreq subsystem.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> .../devicetree/bindings/devfreq/imx-ddrc.yaml | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
>
> diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
> new file mode 100644
> index 000000000000..fa20280a682f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/imx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX DDR Controller
> +
> +maintainers:
> + - Leonard Crestez <leonard.crestez@nxp.com>
> +
> +properties:
> + compatible:
> + contains:
Don't use 'contains'.
> + enum:
> + - fsl,imx8m-ddrc
> +
> + reg:
> + maxItems: 1
> + description: DDR Controller registers
Don't really need a description for a standard property with a single item.
> +
> + clocks:
> + minItems: 5
Just maxItems is sufficient unless there's a variable number of items.
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: dram_core
> + - const: dram_pll
> + - const: dram_alt_root
> + - const: dram_alt
> + - const: dram_apb
> +
> +required:
> + - reg
> + - compatible
> + - clocks
> + - clock-names
You should add an 'additionalProperties: false' here.
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + ddrc: dram-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "dram_core", "dram_pll", "dram_alt_root", "dram_alt", "dram_apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT_ROOT>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + operating-points-v2 = <&ddrc_opp_table>;
Not documented. You can assume a common property has a type definition
already (this one doesn't yet), so just this is enough:
operating-points-v2: true
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^ permalink raw reply
* Re: [PATCH 2/7] dt-bindings: devfreq: Add bindings for generic imx buses
From: Rob Herring @ 2019-08-12 19:46 UTC (permalink / raw)
To: Leonard Crestez
Cc: Mark Rutland, Artur Świgoń, Jacky Bai, Viresh Kumar,
Michael Turquette, Alexandre Bailon, Will Deacon, Abel Vesa,
Saravana Kannan, Krzysztof Kozlowski, Chanwoo Choi, MyungJoo Ham,
NXP Linux Team, devicetree, open list:THERMAL,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Dong Aisheng, Anson Huang, Stephen Boyd, Kyungmin Park,
Sascha Hauer, Fabio Estevam, Shawn Guo, Georgi Djakov
In-Reply-To: <97b0bff95ddb85b06ef3d2f8079faa36562a956d.1565633880.git.leonard.crestez@nxp.com>
On Mon, Aug 12, 2019 at 12:49 PM Leonard Crestez
<leonard.crestez@nxp.com> wrote:
>
> Add initial dt bindings for the interconnects inside i.MX chips.
> Multiple external IPs are involved but SOC integration means the
> software controllable interfaces are very similar.
>
> This is initially only for imx8mm but add an "fsl,imx8m-nic" fallback
> similar to exynos-bus.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> .../devicetree/bindings/devfreq/imx.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
>
> diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml
> new file mode 100644
> index 000000000000..0e2ee3a5205e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/imx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Generic i.MX bus frequency device
> +
> +maintainers:
> + - Leonard Crestez <leonard.crestez@nxp.com>
> +
> +description: |
> + The i.MX SoC family has multiple buses for which clock frequency (and sometimes
> + voltage) can be adjusted.
> +
> + Some of those buses expose register areas mentioned in the memory maps as GPV
> + ("Global Programmers View") but not all. Access to this area might be denied for
> + normal world.
> +
> + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
> + FlexNOC but DT bindings are specific to the integration of these bus
> + interconnect IPs into imx SOCs.
No need to use the interconnect binding?
> +
> +properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8m-noc
> + - fsl,imx8m-nic
This means any combination of these 2 strings is valid. I suspect you
want a given node to have only one of them, so drop 'contains'
> +
> + reg:
> + maxItems: 1
> + description: GPV area
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - clocks
reg?
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + noc: noc@32700000 {
> + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
Doesn't match the schema. (Well, it does with 'contains', but
fsl,imx8mm-noc is not documented.)
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MM_CLK_NOC>;
> + operating-points-v2 = <&noc_opp_table>;
Not documented.
> + };
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [PATCH v3 1/4] perf: Add capability-related utilities
From: Arnaldo Carvalho de Melo @ 2019-08-12 19:43 UTC (permalink / raw)
To: Igor Lubashev
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, linux-kernel, James Morris, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <8a1e76cf5c7c9796d0d4d240fbaa85305298aafa.1565188228.git.ilubashe@akamai.com>
Em Wed, Aug 07, 2019 at 10:44:14AM -0400, Igor Lubashev escreveu:
> Add utilities to help checking capabilities of the running procss.
> Make perf link with libcap, if it is available. If no libcap-dev[el],
> assume no capabilities.
Applied and added the text at the end of this message on the commit log,
I'm also adding NO_LIBCAP=1 to the minimum build in
make -C tools/perf build-test
I.e.:
diff --git a/tools/perf/tests/make b/tools/perf/tests/make
index 5363a12a8b9b..70c48475896d 100644
--- a/tools/perf/tests/make
+++ b/tools/perf/tests/make
@@ -108,6 +108,7 @@ make_minimal += NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1
make_minimal += NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1
make_minimal += NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1
make_minimal += NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1 NO_LIBZSTD=1
+make_minimal += NO_LIBCAP=1
# $(run) contains all available tests
run := make_pure
Thanks,
- Arnaldo
Committer testing:
$ make O=/tmp/build/perf -C tools/perf install-bin
make: Entering directory '/home/acme/git/perf/tools/perf'
BUILD: Doing 'make -j8' parallel build
Auto-detecting system features:
<SNIP>
... libbfd: [ on ]
... libcap: [ OFF ]
... libelf: [ on ]
<SNIP>
Makefile.config:833: No libcap found, disables capability support, please install libcap-devel/libcap-dev
<SNIP>
$ grep libcap /tmp/build/perf/FEATURE-DUMP
feature-libcap=0
$ cat /tmp/build/perf/feature/test-libcap.make.output
test-libcap.c:2:10: fatal error: sys/capability.h: No such file or directory
2 | #include <sys/capability.h>
| ^~~~~~~~~~~~~~~~~~
compilation terminated.
$
Now install libcap-devel and try again:
$ make O=/tmp/build/perf -C tools/perf install-bin
make: Entering directory '/home/acme/git/perf/tools/perf'
BUILD: Doing 'make -j8' parallel build
Warning: Kernel ABI header at 'tools/include/linux/bits.h' differs from latest version at 'include/linux/bits.h'
diff -u tools/include/linux/bits.h include/linux/bits.h
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Auto-detecting system features:
... dwarf: [ on ]
... dwarf_getlocations: [ on ]
... glibc: [ on ]
... gtk2: [ on ]
... libaudit: [ on ]
... libbfd: [ on ]
... libcap: [ on ]
... libelf: [ on ]
<SNIP>>
CC /tmp/build/perf/jvmti/libjvmti.o
<SNIP>>
$ grep libcap /tmp/build/perf/FEATURE-DUMP
feature-libcap=1
$ cat /tmp/build/perf/feature/test-libcap.make.output
$ ldd /tmp/build/perf/feature/test-libcap.make.bin
ldd: /tmp/build/perf/feature/test-libcap.make.bin: No such file or directory
$ ldd /tmp/build/perf/feature/test-libcap.bin
linux-vdso.so.1 (0x00007ffc35bfe000)
libcap.so.2 => /lib64/libcap.so.2 (0x00007ff9c62ff000)
libc.so.6 => /lib64/libc.so.6 (0x00007ff9c6139000)
/lib64/ld-linux-x86-64.so.2 (0x00007ff9c6326000)
$
$ ldd ~/bin/perf | grep libcap
libcap.so.2 => /lib64/libcap.so.2 (0x00007fe20ea19000)
$
Signed-off-by: Igor Lubashev <ilubashe@akamai.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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^ permalink raw reply related
* Re: [PATCH v2 4/6] irqchip/irq-pruss-intc: Add helper functions to configure internal mapping
From: Suman Anna @ 2019-08-12 19:39 UTC (permalink / raw)
To: David Lechner, Marc Zyngier, Thomas Gleixner, Jason Cooper
Cc: devicetree, Grygorii Strashko, Tony Lindgren, Sekhar Nori,
linux-kernel, Andrew F. Davis, Lokesh Vutla, Rob Herring,
Murali Karicheri, linux-omap, linux-arm-kernel, Roger Quadros
In-Reply-To: <124b03b8-f8e7-682b-8767-13a739329da2@lechnology.com>
Hi David,
On 8/8/19 12:09 PM, David Lechner wrote:
> On 8/2/19 4:26 PM, Suman Anna wrote:
>> Point is different applications might use mapping differently as per
>> their firmware and driver/application design and their split across one
>> or more PRUs (design by contract). And we need to set this up at runtime
>> when the application driver is getting run. We will have either the Soft
>> UART or the Ethernet running at a time depending on the end goal desired
>>
>>> I have an idea that we can use multiple struct irq_domains to make
>>> this work in the existing IRQ framework, but it would be helpful to
>>> know more about the bigger picture first.
>>
>> Yeah, would be great if there is a way this can be solved without having
>> to introduce additional API.
>>
>
>
> Here is what I came up with to use existing IRQ APIs to implement event
> mapping.
> Basically it is the same as my previous suggestion [1], with the
> addition of
> multiple IRQ domains.
First of all, many thanks for looking into the problem and providing
patches for the alternate solutions. If we were to not use any exported
functions, this approach does seem to be a viable solution. I am going
to play around with both [1] and this patch with all our existing
usecases and see if I run into any issues.
So, w.r.t this patch compared to [1], is the multiple IRQ domain solving
anything specifically? Our main issue is the re-purposing of a event
(and its mapping depending on the application), and the same issue will
remain whether we have multiple domains or not. Also, now we would
expect an event to migrate between different domains based on its usage.
>
> The idea is that each external interrupt controller (or DMA controller,
> etc.)
> that is connected to the PRUSS interrupt controller is considered an
> interrupt
> domain. One of the objections to my previous patch was that we could
> only have
> one IRQ descriptor per event. Now we can have one descriptor per event per
> domain.
>
> I am still proposing that we use the interrupt-cells and identical vendor
> resource data structures in the PRU firmware be used to provide the mapping
> information. (As a side note, I still think it is important to include
> EVTSEL
> on AM18xx in order to fully describe the event.)
W.r.t EVTSEL, it is a global value and applies to a range of events. I
have another equivalent register/functionality on most of the other SoCs
as well (a register in PRUSS_CFG space) that muxes standard events vs
MII_RT events. Again, that is limited to only a subset of all the system
events. So, should this continue to be a per event specifier, it will be
yet another mapping configuration data item (my idea was to manage this
once per application within the PRU remoteproc driver along with the
fwspec mapping).
regards
Suman
>
> The bindings will have N = 4 cells (or N = 5 when EVTSEL is required to
> fully
> describe the event):
>
> Cell 0: The PRUSS event number, e.g. 0 to 64 for most PRUSSs
> Cell 1: The EVTSEL value (omitted when N == 4), e.g. 0, 1 or
> TI_PRUSS_INTC_EVTSEL_ANY if the event is the same for all EVTSEL
> values. On AM18xx, external events will all require 0 or 1 while
> system events will always be TI_PRUSS_INTC_EVTSEL_ANY.
> Cell N-3: The channel that the event gets mapped to, e.g. 0 to 9
> Cell N-2: The host that the channel gets mapped to, e.g. 0 to 9
> Cell N-1: The interrupt domain, e.g. TI_PRUSS_INTC_DOMAIN_PRU or
> TI_PRUSS_INTC_DOMAIN_MCU
>
> The TI_PRUSS_INTC_DOMAIN_* values are just arbitrary numbers assigned to
> the
> possible domains. For example, on AM18xx and AM33xx, there are just two
> domains,
> the PRU domain for host 0 and host 1 and the MCU domain for host 2 thru 9.
> Looking at the AM65xx manual, it looks like it would have 4 domains, the
> PRU
> domain, the RTU PRU domain, the MCU domain and a task manager domain.
> (And I
> suppose that domains could even be more granular if needed, e.g. we
> could drop
> the arbitrary domain number and treat each host interrupt/event as an
> interrupt
> domain, then there would be an IRQ descriptor per PRU INTC event per host.)
>
> The AM18xx example I have been using will look like this in the device
> tree:
>
> interrupts = <63 TI_PRUSS_INTC_EVTSEL_ANY 0 0
> TI_PRUSS_INTC_DOMAIN_PRU>,
> <62 TI_PRUSS_INTC_EVTSEL_ANY 2 2 TI_PRUSS_INTC_DOMAIN_MCU>;
>
> To keep parsing simple, the PRU firmware can include vendor resources
> that have
> essentially the same format as the device tree bindings. For example:
>
> enum {
> /* IRQ descriptor without EVTSEL */
> TI_PRU_VENDOR_RESOURCE_IRQ = RSC_VENDOR_START,
> /* IRQ descriptor with EVTSEL */
> TI_PRU_VENDOR_RESOURCE_IRQ2,
> };
>
> struct ti_pru_vendor_resource_irq {
> __le32 event;
> __le32 channel;
> __le32 host;
> __le32 domain;
> };
>
> struct ti_pru_vendor_resource_irq2 {
> __le32 event;
> __le32 evt_sel;
> __le32 channel;
> __le32 host;
> __le32 domain;
> };
>
> Then we can provide a vendor resource hook in the remoteproc driver to
> handle
> these resources:
>
> static int ti_pru_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type,
> void *rsc,
> int offset, int avail)
> {
> struct ti_pru_data *pru = rproc->priv;
> struct irq_fwspec fwspec;
> unsigned int virq;
>
> switch (rsc_type) {
> case TI_PRU_VENDOR_RESOURCE_IRQ:
> {
> struct ti_pru_vendor_resource_irq *rsc_irq = rsc;
>
> fwspec.fwnode = pru->intc_fwnode;
> fwspec.param[0] = le32_to_cpu(rsc_irq->event);
> fwspec.param[1] = le32_to_cpu(rsc_irq->channel);
> fwspec.param[2] = le32_to_cpu(rsc_irq->host);
> fwspec.param[3] = le32_to_cpu(rsc_irq->domain);
> fwspec.param_count = 4;
> }
> break;
> case TI_PRU_VENDOR_RESOURCE_IRQ2:
> {
> struct ti_pru_vendor_resource_irq2 *rsc_irq2 = rsc;
>
> fwspec.fwnode = pru->intc_fwnode;
> fwspec.param[0] = le32_to_cpu(rsc_irq2->event);
> fwspec.param[1] = le32_to_cpu(rsc_irq2->evt_sel);
> fwspec.param[2] = le32_to_cpu(rsc_irq2->channel);
> fwspec.param[3] = le32_to_cpu(rsc_irq2->host);
> fwspec.param[4] = le32_to_cpu(rsc_irq2->domain);
> fwspec.param_count = 5;
> break;
> }
> default:
> return RSC_IGNORED;
> }
>
> virq = irq_create_fwspec_mapping(&fwspec);
> if (!virq)
> return -EINVAL;
>
> /* TODO: save virq (and other metadata) for later use */
>
> return RSC_HANDLED;
> }
>
> static const struct rproc_ops ti_pru_rproc_ops = {
> .start = ti_pru_rproc_start,
> .stop = ti_pru_rproc_stop,
> .kick = ti_pru_rproc_kick,
> .da_to_va = ti_pru_rproc_da_to_va,
> .handle_rsc = ti_pru_rproc_handle_rsc,
> };
>
> The handle_rsc callback is called for each resource when the PRU is booted.
> The function irq_create_fwspec_mapping() causes the IRQ to be mapped in
> hardware. From what I understand from the previous discussions, this is
> exactly
> when we want this to happen.
>
> This patch applies on top of "irqchip/irq-pruss-intc: Add a PRUSS
> irqchip driver
> for PRUSS interrupts", "irqchip/irq-pruss-intc: Add support for shared and
> invalid interrupts" and "irqchip/irq-pruss-intc: Implement irq_{get,set}
> _irqchip_state ops" from [PATCH v2 0/6] "Add TI PRUSS Local Interrupt
> Controller
> IRQChip driver" [2].
>
> A working copy along with some remoteproc and rpmsg hacks can be found
> on my
> GitHub [3].
>
> [1]:
> https://lore.kernel.org/lkml/fb2bdb7b-4d4d-508f-722a-554888280145@lechnology.com/
>
> [2]: https://lore.kernel.org/lkml/20190731224149.11153-1-s-anna@ti.com/
> [3]: https://github.com/dlech/linux/commits/pruss-2019-08-08
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Andrew F. Davis <afd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
> drivers/irqchip/irq-pruss-intc.c | 387 +++++++++++++++++-
> .../interrupt-controller/ti-pruss.h | 27 ++
> 2 files changed, 396 insertions(+), 18 deletions(-)
> create mode 100644 include/dt-bindings/interrupt-controller/ti-pruss.h
>
> diff --git a/drivers/irqchip/irq-pruss-intc.c
> b/drivers/irqchip/irq-pruss-intc.c
> index c1fd6c09f2f2..da4349df08c3 100644
> --- a/drivers/irqchip/irq-pruss-intc.c
> +++ b/drivers/irqchip/irq-pruss-intc.c
> @@ -5,6 +5,8 @@
> * Copyright (C) 2016-2019 Texas Instruments Incorporated -
> http://www.ti.com/
> * Andrew F. Davis <afd@ti.com>
> * Suman Anna <s-anna@ti.com>
> + *
> + * Copyright (C) 2019 David Lechner <david@lechnology.com>
> */
>
> #include <linux/interrupt.h>
> @@ -14,6 +16,14 @@
> #include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <dt-bindings/interrupt-controller/ti-pruss.h>
> +
> +/* The number of possible interrupt domains, see TI_PRUSS_INTC_DOMAIN_* in
> + * dt-bindings/interrupt-controller/ti-pruss.h
> + */
> +#define NUM_TI_PRUSS_INTC_DOMAIN 5
>
> /*
> * Number of host interrupts reaching the main MPU sub-system. Note
> that this
> @@ -25,6 +35,12 @@
> /* minimum starting host interrupt number for MPU */
> #define MIN_PRU_HOST_INT 2
>
> +/* maximum number of host interrupts */
> +#define MAX_PRU_HOST_INT 10
> +
> +/* maximum number of interrupt channels */
> +#define MAX_PRU_CHANNELS 10
> +
> /* maximum number of system events */
> #define MAX_PRU_SYS_EVENTS 64
>
> @@ -57,27 +73,83 @@
> #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
> #define PRU_INTC_HIER 0x1500
>
> +/* CMR register bit-field macros */
> +#define CMR_EVT_MAP_MASK 0xf
> +#define CMR_EVT_MAP_BITS 8
> +#define CMR_EVT_PER_REG 4
> +
> +/* HMR register bit-field macros */
> +#define HMR_CH_MAP_MASK 0xf
> +#define HMR_CH_MAP_BITS 8
> +#define HMR_CH_PER_REG 4
> +
> /* HIPIR register bit-fields */
> #define INTC_HIPIR_NONE_HINT 0x80000000
>
> +/**
> + * struct pruss_intc_hwirq_data - additional metadata associated with a
> PRU
> + * system event
> + * @evtsel: The event select index (AM18xx only)
> + * @channel: The PRU INTC channel that the system event should be
> mapped to
> + * @host: The PRU INTC host that the channel should be mapped to
> + */
> +struct pruss_intc_hwirq_data {
> + u8 evtsel;
> + u8 channel;
> + u8 host;
> +};
> +
> +/**
> + * struct pruss_intc_map_record - keeps track of actual mapping state
> + * @value: The currently mapped value (evtsel, channel or host)
> + * @ref_count: Keeps track of number of current users of this resource
> + */
> +struct pruss_intc_map_record {
> + u8 value;
> + u8 ref_count;
> +};
> +
> +/**
> + * struct pruss_intc_domain - information specific to an external IRQ
> domain
> + * @hwirq_data: Table of additional mapping data received from device tree
> + * or PRU firmware
> + * @domain: irq domain
> + * @intc: the interrupt controller
> + * @id: Unique domain identifier (from device tree bindings)
> + */
> +struct pruss_intc_domain {
> + struct pruss_intc_hwirq_data hwirq_data[MAX_PRU_SYS_EVENTS];
> + struct irq_domain *domain;
> + struct pruss_intc *intc;
> + u32 id;
> +};
> +
> /**
> * struct pruss_intc - PRUSS interrupt controller structure
> + * @domain: External interrupt domains
> + * @evtsel: Tracks the current state of CFGCHIP3[3].PRUSSEVTSEL (AM18xx
> only)
> + * @event_channel: Tracks the current state of system event to channel
> mappings
> + * @channel_host: Tracks the current state of channel to host mappings
> * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
> * @base: base virtual address of INTC register space
> * @irqchip: irq chip for this interrupt controller
> - * @domain: irq domain for this interrupt controller
> * @lock: mutex to serialize access to INTC
> * @shared_intr: bit-map denoting if the MPU host interrupt is shared
> * @invalid_intr: bit-map denoting if host interrupt is not connected
> to MPU
> + * @has_evtsel: indicates that the chip has an event select mux
> */
> struct pruss_intc {
> + struct pruss_intc_domain domain[NUM_ISA_INTERRUPTS];
> + struct pruss_intc_map_record evtsel;
> + struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
> + struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
> unsigned int irqs[MAX_NUM_HOST_IRQS];
> void __iomem *base;
> struct irq_chip *irqchip;
> - struct irq_domain *domain;
> struct mutex lock; /* PRUSS INTC lock */
> u16 shared_intr;
> u16 invalid_intr;
> + bool has_evtsel;
> };
>
> static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned
> int reg)
> @@ -105,6 +177,172 @@ static int pruss_intc_check_write(struct
> pruss_intc *intc, unsigned int reg,
> return 0;
> }
>
> +/**
> + * pruss_intc_map() - configure the PRUSS INTC
> + * @domain: pru intc domain pointer
> + * @hwirq: the system event number
> + *
> + * Configures the PRUSS INTC with the provided configuration from the one
> + * parsed in the xlate function. Any existing event to channel mappings or
> + * channel to host interrupt mappings are checked to make sure there
> are no
> + * conflicting configuration between both the PRU cores.
> + *
> + * Returns 0 on success, or a suitable error code otherwise
> + */
> +static int pruss_intc_map(struct pruss_intc_domain *domain, unsigned
> long hwirq)
> +{
> + struct pruss_intc *intc = domain->intc;
> + struct device* dev = intc->irqchip->parent_device;
> + u32 val;
> + int idx, ret;
> + u8 evtsel, ch, host;
> +
> + if (hwirq >= MAX_PRU_SYS_EVENTS)
> + return -EINVAL;
> +
> + mutex_lock(&intc->lock);
> +
> + evtsel = domain->hwirq_data[hwirq].evtsel;
> + ch = domain->hwirq_data[hwirq].channel;
> + host = domain->hwirq_data[hwirq].host;
> +
> + if (intc->has_evtsel && intc->evtsel.ref_count > 0 &&
> + intc->evtsel.value != evtsel) {
> + dev_err(dev, "event %lu (req. evtsel %d) already assigned to
> evtsel %d\n",
> + hwirq, evtsel, intc->evtsel.value);
> + ret = -EBUSY;
> + goto unlock;
> + }
> +
> + /* check if sysevent already assigned */
> + if (intc->event_channel[hwirq].ref_count > 0 &&
> + intc->event_channel[hwirq].value != ch) {
> + dev_err(dev, "event %lu (req. channel %d) already assigned to
> channel %d\n",
> + hwirq, ch, intc->event_channel[hwirq].value);
> + ret = -EBUSY;
> + goto unlock;
> + }
> +
> + /* check if channel already assigned */
> + if (intc->channel_host[ch].ref_count > 0 &&
> + intc->channel_host[ch].value != host) {
> + dev_err(dev, "channel %d (req. host %d) already assigned to
> host %d\n",
> + ch, host, intc->channel_host[ch].value);
> + ret = -EBUSY;
> + goto unlock;
> + }
> +
> + if (++intc->evtsel.ref_count == 1) {
> + intc->evtsel.value = evtsel;
> +
> + /* TODO: need to implement CFGCHIP3[3].PRUSSEVTSEL */
> + }
> +
> + if (++intc->event_channel[hwirq].ref_count == 1) {
> + intc->event_channel[hwirq].value = ch;
> +
> + /*
> + * configure channel map registers - each register holds map
> + * info for 4 events, with each event occupying the lower nibble
> + * in a register byte address in little-endian fashion
> + */
> + idx = hwirq / CMR_EVT_PER_REG;
> +
> + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
> + val &= ~(CMR_EVT_MAP_MASK <<
> + ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS));
> + val |= ch << ((hwirq % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS);
> + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
> +
> + dev_dbg(dev, "SYSEV%lu -> CH%d (CMR%d 0x%08x)\n", hwirq, ch,
> + idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
> +
> + /* clear and enable system event */
> + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
> + pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
> + }
> +
> + if (++intc->channel_host[ch].ref_count == 1) {
> + intc->channel_host[ch].value = host;
> +
> + /*
> + * set host map registers - each register holds map info for
> + * 4 channels, with each channel occupying the lower nibble in
> + * a register byte address in little-endian fashion
> + */
> + idx = ch / HMR_CH_PER_REG;
> +
> + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
> + val &= ~(HMR_CH_MAP_MASK <<
> + ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS));
> + val |= host << ((ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS);
> + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
> +
> + dev_dbg(dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
> + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
> +
> + /* enable host interrupts */
> + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
> + }
> +
> + dev_info(dev, "mapped system_event = %lu channel = %d host = %d
> domain = %u\n",
> + hwirq, ch, host, domain->id);
> +
> + /* global interrupt enable */
> + pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
> +
> + mutex_unlock(&intc->lock);
> + return 0;
> +
> +unlock:
> + mutex_unlock(&intc->lock);
> + return ret;
> +}
> +
> +/**
> + * pruss_intc_unmap() - unconfigure the PRUSS INTC
> + * @domain: pru intc domain pointer
> + * @hwirq: the system event number
> + *
> + * Undo whatever was done in pruss_intc_map() for a PRU core.
> + * Mappings are reference counted, so resources are only disabled when
> there
> + * are no longer any users.
> + */
> +static void pruss_intc_unmap(struct pruss_intc_domain *domain, unsigned
> long hwirq)
> +{
> + struct pruss_intc *intc = domain->intc;
> + struct device* dev = intc->irqchip->parent_device;
> + u8 ch, host;
> +
> + if (hwirq >= MAX_PRU_SYS_EVENTS)
> + return;
> +
> + mutex_lock(&intc->lock);
> +
> + ch = intc->event_channel[hwirq].value;
> + host = intc->channel_host[ch].value;
> +
> + if (--intc->channel_host[ch].ref_count == 0) {
> + /* disable host interrupts */
> + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
> + }
> +
> + if (--intc->event_channel[hwirq].ref_count == 0) {
> + /* disable system events */
> + pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
> + /* clear any pending status */
> + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
> + }
> +
> + if (intc->has_evtsel)
> + intc->evtsel.ref_count--;
> +
> + dev_info(dev, "unmapped system_event = %lu channel = %d host = %d\n",
> + hwirq, ch, host);
> +
> + mutex_unlock(&intc->lock);
> +}
> +
> static void pruss_intc_init(struct pruss_intc *intc)
> {
> int i;
> @@ -198,10 +436,83 @@ static int pruss_intc_irq_set_irqchip_state(struct
> irq_data *data,
> return pruss_intc_check_write(intc, PRU_INTC_SICR, data->hwirq);
> }
>
> +static int pruss_intc_irq_domain_select(struct irq_domain *d,
> + struct irq_fwspec *fwspec,
> + enum irq_domain_bus_token bus_token)
> +{
> + struct pruss_intc_domain *domain = d->host_data;
> + int num_cells = domain->intc->has_evtsel ? 5 : 4;
> + u32 domain_id;
> +
> + if (!fwspec || fwspec->fwnode != domain->domain->fwnode)
> + return 0;
> +
> + if (bus_token != DOMAIN_BUS_ANY && bus_token !=
> domain->domain->bus_token)
> + return 0;
> +
> + if (WARN_ON_ONCE(fwspec->param_count != num_cells))
> + return 0;
> +
> + domain_id = fwspec->param[fwspec->param_count - 1];
> + if (domain_id != domain->id)
> + return 0;
> +
> + return 1;
> +}
> +
> +static int
> +pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node
> *node,
> + const u32 *intspec, unsigned int intsize,
> + unsigned long *out_hwirq, unsigned int *out_type)
> +{
> + struct pruss_intc_domain *domain = d->host_data;
> + struct pruss_intc *intc = domain->intc;
> + int num_cells = intc->has_evtsel ? 5 : 4;
> + u32 sys_event, channel, host, domain_id;
> + u32 evtsel = 0;
> +
> + if (WARN_ON_ONCE(intsize != num_cells))
> + return -EINVAL;
> +
> + sys_event = intspec[0];
> + if (sys_event >= MAX_PRU_SYS_EVENTS)
> + return -EINVAL;
> +
> + if (intc->has_evtsel)
> + evtsel = intspec[1];
> +
> + channel = intspec[intsize - 3];
> + if (channel >= MAX_PRU_CHANNELS)
> + return -EINVAL;
> +
> + host = intspec[intsize - 2];
> + if (host >= MAX_PRU_HOST_INT)
> + return -EINVAL;
> +
> + domain_id = intspec[intsize - 1];
> + if (domain_id != domain->id)
> + return -EINVAL;
> +
> + domain->hwirq_data[sys_event].evtsel = evtsel;
> + domain->hwirq_data[sys_event].channel = channel;
> + domain->hwirq_data[sys_event].host = host;
> +
> + *out_hwirq = sys_event;
> + *out_type = IRQ_TYPE_NONE;
> +
> + return 0;
> +}
> +
> static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int
> virq,
> irq_hw_number_t hw)
> {
> - struct pruss_intc *intc = d->host_data;
> + struct pruss_intc_domain *domain = d->host_data;
> + struct pruss_intc *intc = domain->intc;
> + int err;
> +
> + err = pruss_intc_map(domain, hw);
> + if (err < 0)
> + return err;
>
> irq_set_chip_data(virq, intc);
> irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq);
> @@ -211,12 +522,17 @@ static int pruss_intc_irq_domain_map(struct
> irq_domain *d, unsigned int virq,
>
> static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned
> int virq)
> {
> + struct pruss_intc_domain *domain = d->host_data;
> + unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
> +
> irq_set_chip_and_handler(virq, NULL, NULL);
> irq_set_chip_data(virq, NULL);
> + pruss_intc_unmap(domain, hwirq);
> }
>
> static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
> - .xlate = irq_domain_xlate_onecell,
> + .select = pruss_intc_irq_domain_select,
> + .xlate = pruss_intc_irq_domain_xlate,
> .map = pruss_intc_irq_domain_map,
> .unmap = pruss_intc_irq_domain_unmap,
> };
> @@ -245,7 +561,8 @@ static void pruss_intc_irq_handler(struct irq_desc
> *desc)
> hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i));
> while (!(hipir & INTC_HIPIR_NONE_HINT)) {
> hwirq = hipir & GENMASK(9, 0);
> - virq = irq_linear_revmap(intc->domain, hwirq);
> + virq = irq_linear_revmap(
> + intc->domain[TI_PRUSS_INTC_DOMAIN_MCU].domain, hwirq);
>
> /*
> * NOTE: manually ACK any system events that do not have a
> @@ -272,7 +589,8 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
> struct pruss_intc *intc;
> struct resource *res;
> struct irq_chip *irqchip;
> - int i, irq, count;
> + int i, err, irq, count;
> + u32 num_cells;
> u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
>
> intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
> @@ -323,13 +641,22 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
> }
> }
>
> + err = of_property_read_u32(dev->of_node, "#interrupt-cells",
> &num_cells);
> + if (!err && num_cells == 5)
> + intc->has_evtsel = true;
> +
> mutex_init(&intc->lock);
>
> + pm_runtime_enable(dev);
> + pm_runtime_get_sync(dev);
> +
> pruss_intc_init(intc);
>
> irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
> - if (!irqchip)
> - return -ENOMEM;
> + if (!irqchip) {
> + err = -ENOMEM;
> + goto fail_alloc;
> + }
>
> irqchip->irq_ack = pruss_intc_irq_ack;
> irqchip->irq_mask = pruss_intc_irq_mask;
> @@ -338,14 +665,24 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
> irqchip->irq_release_resources = pruss_intc_irq_relres;
> irqchip->irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state;
> irqchip->irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state;
> + irqchip->parent_device = dev;
> irqchip->name = dev_name(dev);
> intc->irqchip = irqchip;
>
> - /* always 64 events */
> - intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS,
> - &pruss_intc_irq_domain_ops, intc);
> - if (!intc->domain)
> - return -ENOMEM;
> + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
> + intc->domain[i].intc = intc;
> + intc->domain[i].id = i;
> + /* always 64 events */
> + intc->domain[i].domain = irq_domain_add_linear(dev->of_node,
> + MAX_PRU_SYS_EVENTS, &pruss_intc_irq_domain_ops,
> + &intc->domain[i]);
> + if (!intc->domain[i].domain) {
> + while (--i >= 0)
> + irq_domain_remove(intc->domain[i].domain);
> + err = -ENOMEM;
> + goto fail_alloc;
> + }
> + }
>
> for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
> irq = platform_get_irq_byname(pdev, irq_names[i]);
> @@ -356,6 +693,7 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
>
> dev_err(dev, "platform_get_irq_byname failed for %s : %d\n",
> irq_names[i], irq);
> + err = irq;
> goto fail_irq;
> }
>
> @@ -372,13 +710,20 @@ static int pruss_intc_probe(struct platform_device
> *pdev)
> irq_set_chained_handler_and_data(intc->irqs[i], NULL,
> NULL);
> }
> - irq_domain_remove(intc->domain);
> - return irq;
> + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++)
> + irq_domain_remove(intc->domain[i].domain);
> +
> +fail_alloc:
> + pm_runtime_put(dev);
> + pm_runtime_disable(dev);
> +
> + return err;
> }
>
> static int pruss_intc_remove(struct platform_device *pdev)
> {
> struct pruss_intc *intc = platform_get_drvdata(pdev);
> + struct device *dev = &pdev->dev;
> unsigned int hwirq;
> int i;
>
> @@ -388,9 +733,15 @@ static int pruss_intc_remove(struct platform_device
> *pdev)
> NULL);
> }
>
> - for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
> - irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
> - irq_domain_remove(intc->domain);
> + for (i = 0; i < NUM_TI_PRUSS_INTC_DOMAIN; i++) {
> + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++)
> + irq_dispose_mapping(irq_find_mapping(
> + intc->domain[i].domain, hwirq));
> + irq_domain_remove(intc->domain[i].domain);
> + }
> +
> + pm_runtime_put(dev);
> + pm_runtime_disable(dev);
>
> return 0;
> }
> diff --git a/include/dt-bindings/interrupt-controller/ti-pruss.h
> b/include/dt-bindings/interrupt-controller/ti-pruss.h
> new file mode 100644
> index 000000000000..326a68c31bce
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/ti-pruss.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * This header provides constants for the Texas Instruments Programmable
> + * Realtime Unit Subsystem (PRUSS) interrupt controller.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H
> +
> +/* interrupt specifier for optional cell 1 */
> +
> +#define TI_PRUSS_INTC_EVTSEL_ANY 0xffffffff
> +
> +/* interrupt specifier for cell #interrupt-cells - 1 */
> +
> +/* host interrupt is connected to PRU cores, e.g. host events 0 and 1 */
> +#define TI_PRUSS_INTC_DOMAIN_PRU 0
> +/* host interrupt is connected to MCU's interrupt controller */
> +#define TI_PRUSS_INTC_DOMAIN_MCU 1
> +/* host interrupt is connected to DSP's interrupt controller */
> +#define TI_PRUSS_INTC_DOMAIN_DSP 2
> +/* host interrupt is connected to the auxillary PRU cores */
> +#define TI_PRUSS_INTC_DOMAIN_RTU_PRU 3
> +/* host interrupt is connected to the task managers */
> +#define TI_PRUSS_INTC_DOMAIN_TASK 4
> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TI_PRUSS_H */
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^ permalink raw reply
* Re: [PATCH v2] ARM: dts: add device tree for Mecer Xtreme Mini S6
From: Rob Herring @ 2019-08-12 19:11 UTC (permalink / raw)
To: Justin Swartz
Cc: Mark Rutland, devicetree, Heiko Stuebner,
linux-kernel@vger.kernel.org, open list:ARM/Rockchip SoC...,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190811230015.28349-1-justin.swartz@risingedge.co.za>
On Sun, Aug 11, 2019 at 5:01 PM Justin Swartz
<justin.swartz@risingedge.co.za> wrote:
>
> The Mecer Xtreme Mini S6 features a Rockchip RK3229 SoC,
> 1GB DDR3 RAM, 8GB eMMC, MicroSD port, 10/100Mbps Ethernet,
> Realtek 8723BS WLAN module, 2 x USB 2.0 ports, HDMI output,
> and S/PDIF output.
>
> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
> ---
> .../devicetree/bindings/arm/rockchip.yaml | 5 +
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/rk3229-xms6.dts | 283 +++++++++++++++++++++
> 4 files changed, 291 insertions(+)
> create mode 100644 arch/arm/boot/dts/rk3229-xms6.dts
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply
* [PATCH v2] coresight: tmc-etr: Fix perf_data check.
From: Yabin Cui @ 2019-08-12 19:03 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Yabin Cui, linux-kernel, linux-arm-kernel
When tracing etm data of multiple threads on multiple cpus through
perf interface, each cpu has a unique etr_perf_buffer while sharing
the same etr device. There is no guarantee that the last cpu starts
etm tracing also stops last. This makes perf_data check fail.
Fix it by checking etr_buf instead of etr_perf_buffer.
Fixes: 3147da92a8a8 ("coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios")
Signed-off-by: Yabin Cui <yabinc@google.com>
---
v1 -> v2: rename perf_data to perf_buf. Add fixes tag.
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 +++---
drivers/hwtracing/coresight/coresight-tmc.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 17006705287a..90d1548ad268 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1484,7 +1484,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
goto out;
}
- if (WARN_ON(drvdata->perf_data != etr_perf)) {
+ if (WARN_ON(drvdata->perf_buf != etr_buf)) {
lost = true;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
goto out;
@@ -1497,7 +1497,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
CS_LOCK(drvdata->base);
/* Reset perf specific data */
- drvdata->perf_data = NULL;
+ drvdata->perf_buf = NULL;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
@@ -1556,7 +1556,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
}
etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf);
- drvdata->perf_data = etr_perf;
+ drvdata->perf_buf = etr_perf->etr_buf;
/*
* No HW configuration is needed if the sink is already in
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 1ed50411cc3c..f9a0c95e9ba2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -178,8 +178,8 @@ struct etr_buf {
* device configuration register (DEVID)
* @idr: Holds etr_bufs allocated for this ETR.
* @idr_mutex: Access serialisation for idr.
- * @perf_data: PERF buffer for ETR.
- * @sysfs_data: SYSFS buffer for ETR.
+ * @sysfs_buf: SYSFS buffer for ETR.
+ * @perf_buf: PERF buffer for ETR.
*/
struct tmc_drvdata {
void __iomem *base;
@@ -202,7 +202,7 @@ struct tmc_drvdata {
struct idr idr;
struct mutex idr_mutex;
struct etr_buf *sysfs_buf;
- void *perf_data;
+ struct etr_buf *perf_buf;
};
struct etr_buf_operations {
--
2.23.0.rc1.153.gdeed80330f-goog
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^ permalink raw reply related
* Re: [PATCH v2 1/6] dt-bindings: arm: fsl: Add the S32V234-EVB board
From: Rob Herring @ 2019-08-12 18:58 UTC (permalink / raw)
To: Stefan-gabriel Mirea
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Eddy Petrisor,
will@kernel.org, corbet@lwn.net, gregkh@linuxfoundation.org,
jslaby@suse.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Leo Li,
linux-serial@vger.kernel.org, catalin.marinas@arm.com,
shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190809112853.15846-2-stefan-gabriel.mirea@nxp.com>
On Fri, Aug 9, 2019 at 5:29 AM Stefan-gabriel Mirea
<stefan-gabriel.mirea@nxp.com> wrote:
>
> From: Eddy Petrișor <eddy.petrisor@nxp.com>
>
> Add entry for the NXP S32V234 Customer Evaluation Board to the board/SoC
> bindings.
>
> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
> Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply
* Re: [PATCH 01/19] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method
From: Rob Herring @ 2019-08-12 18:57 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Mark Rutland, devicetree, Jason Cooper, Stephen Boyd,
Marc Zyngier, Michael Turquette, Russell King,
Kishon Vijay Abraham I,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Olof Johansson, Thomas Gleixner, linux-clk,
linux-kernel@vger.kernel.org
In-Reply-To: <20190809093158.7969-2-lkundrak@v3.sk>
On Fri, Aug 9, 2019 at 3:32 AM Lubomir Rintel <lkundrak@v3.sk> wrote:
>
> Add the enable method for the second PJ4B core of the Marvell MMP3 SoC.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply
* [PATCH 7/7] arm64: dts: imx8mm: Add devfreq nodes
From: Leonard Crestez @ 2019-08-12 18:49 UTC (permalink / raw)
To: Stephen Boyd, MyungJoo Ham, Kyungmin Park, Rob Herring
Cc: Dong Aisheng, Artur Świgoń, Abel Vesa, Saravana Kannan,
Anson Huang, linux-arm-kernel, Viresh Kumar, Michael Turquette,
linux-pm, linux-imx, Krzysztof Kozlowski, Chanwoo Choi,
Will Deacon, Alexandre Bailon, kernel, Fabio Estevam,
Mark Rutland, Shawn Guo, Georgi Djakov, devicetree, Jacky Bai
In-Reply-To: <cover.1565633880.git.leonard.crestez@nxp.com>
Add initial support for bus scaling on imx8m, starting with noc and ddrc
because they're the biggest power hogs.
Add a devfreq-event link to the PMU in order to support on-demand
scaling of ddrc based on measured dram bandwith usage. Make ddrc a
parent of the NOC because all traffic to ddrc goes through
Support for proactive scaling via interconnect and support for scaling
additional NICs will come later. The high-performance bus masters which
need that (display, vpu, gpu) are not yet enabled in upstream anyway.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 51 ++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index e8560d15c130..a37d82133c06 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -122,10 +122,38 @@
clock-latency-ns = <150000>;
opp-suspend;
};
};
+ ddrc_opp_table: ddrc-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+
+ noc_opp_table: noc-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-150M {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp-375M {
+ opp-hz = /bits/ 64 <375000000>;
+ };
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
@@ -748,10 +776,18 @@
status = "disabled";
};
};
+ noc: noc@32700000 {
+ compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MM_CLK_NOC>;
+ devfreq = <&ddrc>;
+ operating-points-v2 = <&noc_opp_table>;
+ };
+
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
@@ -832,11 +868,24 @@
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- ddr-pmu@3d800000 {
+ ddrc: dram-controller@3d400000 {
+ compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+ reg = <0x3d400000 0x400000>;
+ clock-names = "dram_core", "dram_pll", "dram_alt_root", "dram_alt", "dram_apb";
+ clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+ <&clk IMX8MM_DRAM_PLL>,
+ <&clk IMX8MM_CLK_DRAM_ALT_ROOT>,
+ <&clk IMX8MM_CLK_DRAM_ALT>,
+ <&clk IMX8MM_CLK_DRAM_APB>;
+ devfreq-events = <&ddr_pmu>;
+ operating-points-v2 = <&ddrc_opp_table>;
+ };
+
+ ddr_pmu: ddr-pmu@3d800000 {
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.17.1
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