* [PATCH v3 1/2] dt-bindings: arm: imx: add imx8mq nitrogen support
From: Dafna Hirschfeld @ 2019-08-13 12:51 UTC (permalink / raw)
To: dafna.hirschfeld
Cc: mark.rutland, devicetree, ezequiel, s.hauer, linux-kernel,
Troy Kisky, Gary Bisson, robh+dt, kernel, kernel, shawnguo,
linux-arm-kernel
In-Reply-To: <20190813125147.29605-1-dafna.hirschfeld@collabora.com>
From: Gary Bisson <gary.bisson@boundarydevices.com>
The Nitrogen8M is an ARM based single board computer (SBC)
designed to leverage the full capabilities of NXP’s i.MX8M
Quad processor.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
[Dafna: porting vendor's code to mainline]
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 362bf827cad1..16db1c699ba7 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -224,6 +224,7 @@ properties:
- description: i.MX8MQ based Boards
items:
- enum:
+ - boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- purism,librem5-devkit # Purism Librem5 devkit
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
--
2.20.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v3 2/2] arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
From: Dafna Hirschfeld @ 2019-08-13 12:51 UTC (permalink / raw)
To: dafna.hirschfeld
Cc: mark.rutland, devicetree, ezequiel, s.hauer, linux-kernel,
Troy Kisky, Gary Bisson, robh+dt, kernel, kernel, shawnguo,
linux-arm-kernel
From: Gary Bisson <gary.bisson@boundarydevices.com>
Add basic dts support for i.MX8MQ NITROGEN8M.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
[Dafna: porting vendor's code to mainline]
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx8mq-nitrogen.dts | 400 ++++++++++++++++++
2 files changed, 401 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8c0c4343e586..e2c6c93f47b6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
new file mode 100644
index 000000000000..da25ea9055cd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx8mq.dtsi"
+
+/ {
+ model = "Boundary Devices i.MX8MQ Nitrogen8M";
+ compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ };
+ };
+
+ reg_vref_0v9: regulator-vref-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-0v9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_vref_2v5: regulator-vref-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ reg_vref_3v3: regulator-vref-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vref_5v: regulator-vref-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "nxp,pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+ reg = <0x70>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c1a: i2c1@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg_arm_dram: regulator@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_arm_dram>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1b: i2c1@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg_dram_1p1v: regulator@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
+ reg = <0x60>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1c: i2c1@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg_soc_gpu_vpu: regulator@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1d: i2c1@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rtc@68 {
+ compatible = "microcrystal,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+ };
+ };
+};
+
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ non-removable;
+ vmmc-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* J17 connector, odd */
+ MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
+ MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
+ MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
+ MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
+ MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
+ MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
+ MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
+ MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
+ MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
+ MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
+ MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
+ MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
+ MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
+ MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
+ MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
+ MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
+
+ /* J17 connector, even */
+ MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
+
+ /* J18 connector, odd */
+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
+ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
+
+ /* J18 connector, even */
+ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
+ MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
+ MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
+ MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
+ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
+
+ /* J13 Pin 2, WL_WAKE */
+ MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
+ /* J13 Pin 4, WL_IRQ, not needed for Silex */
+ MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
+ /* J13 pin 9, unused */
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ /* J13 Pin 41, BT_CLK_REQ */
+ MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
+ /* J13 Pin 42, BT_HOST_WAKE */
+ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
+
+ /* Clock for both CSI1 and CSI2 */
+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
+ /* test points */
+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ >;
+ };
+
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
+ >;
+ };
+
+ pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
+ >;
+ };
+
+ pinctrl_reg_arm_dram: reg-arm-dram {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
+ >;
+ };
+
+ pinctrl_reg_dram_1p1v: reg-dram-1p1v {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
+ >;
+ };
+
+ pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.20.1
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^ permalink raw reply related
* Re: [PATCH next v9 07/11] usb: roles: Add fwnode_usb_role_switch_get() function
From: Heikki Krogerus @ 2019-08-13 13:01 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mark Rutland, devicetree, Hans de Goede, Greg Kroah-Hartman,
Linus Walleij, linux-usb, linux-kernel, Biju Das,
Badhri Jagan Sridharan, Andy Shevchenko, Rob Herring,
linux-mediatek, Min Guo, Matthias Brugger, Nagarjuna Kristam,
Adam Thomson, linux-arm-kernel, Li Jun
In-Reply-To: <1565695634-9711-8-git-send-email-chunfeng.yun@mediatek.com>
On Tue, Aug 13, 2019 at 07:27:10PM +0800, Chunfeng Yun wrote:
> From: Heikki Krogerus <heikki.krogerus@linux.intel.com>
>
> The fwnode_usb_role_switch_get() function is exactly the
> same as usb_role_switch_get(), except that it takes struct
> fwnode_handle as parameter instead of struct device.
>
> Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Why is my SoB replaced with Suggested-by tag in this patch?
thanks,
--
heikki
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^ permalink raw reply
* Re: [PATCH v4 0/5] iommu/amd: Convert the AMD iommu driver to the dma-iommu api
From: Christoph Hellwig @ 2019-08-13 13:07 UTC (permalink / raw)
To: Tom Murphy
Cc: Heiko Stuebner, Will Deacon, virtualization, David Brown,
Thierry Reding, linux-s390, linux-samsung-soc,
Jean-Philippe Brucker, Joerg Roedel, Krzysztof Kozlowski,
Jonathan Hunter, Christoph Hellwig, linux-rockchip, Andy Gross,
Matthias Brugger, Gerald Schaefer, linux-arm-msm, linux-mediatek,
linux-tegra, linux-arm-kernel, Robin Murphy, linux-kernel, iommu,
Kukjin Kim, David Woodhouse
In-Reply-To: <CALQxJuvxBc3MH3_B_fZ3FvURHOM3F3dvvZ6x=GtALUAvyu7Qxw@mail.gmail.com>
On Tue, Aug 13, 2019 at 08:09:26PM +0800, Tom Murphy wrote:
> Hi Christoph,
>
> I quit my job and am having a great time traveling South East Asia.
Enjoy! I just returned from my vacation.
> I definitely don't want this work to go to waste and I hope to repost it
> later this week but I can't guarantee it.
>
> Let me know if you need this urgently.
It isn't in any strict sense urgent. I just have various DMA API plans
that I'd rather just implement in dma-direct and dma-iommu rather than
also in two additional commonly used iommu drivers. So on the one had
the sooner the better, on the other hand no real urgency.
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^ permalink raw reply
* Re: next/pending-fixes build: 222 builds: 3 failed, 219 passed, 3 errors, 425 warnings (v5.3-rc4-185-g260510fdbaa7)
From: Christoph Hellwig @ 2019-08-13 13:08 UTC (permalink / raw)
To: Mark Brown
Cc: linux-next, kernel-build-reports, Christoph Hellwig,
linux-arm-kernel, Russell King
In-Reply-To: <20190813123740.GD5093@sirena.co.uk>
On Tue, Aug 13, 2019 at 01:37:40PM +0100, Mark Brown wrote:
> On Tue, Aug 13, 2019 at 05:14:59AM -0700, kernelci.org bot wrote:
>
> For the past few days -next has been failing to build configurations
> with LPAE enabled:
>
> > arm:
> > axm55xx_defconfig: (gcc-8) FAIL
> > keystone_defconfig: (gcc-8) FAIL
> > multi_v7_defconfig+CONFIG_EFI=y+CONFIG_ARM_LPAE=y: (gcc-8) FAIL
>
> due to errors related to dma_atomic_pool_init()
>
The commit is completely bogus and slipped into my tree that gets pulled
into linux-next by accident. It has been dropped already.
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* Re: [PATCH V5 00/12] 52-bit kernel + user VAs
From: Will Deacon @ 2019-08-13 13:10 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: crecklin, Ard Biesheuvel, Catalin Marinas, bhsharma, Steve Capper,
Linux-Renesas, maz, Linux ARM
In-Reply-To: <CAMuHMdWvkWGoNC5HbWoZwtpg5VXxTZqRZqQy4BLPgQXZJtKnsQ@mail.gmail.com>
Hi Geert,
On Tue, Aug 13, 2019 at 02:43:23PM +0200, Geert Uytterhoeven wrote:
> On Fri, Aug 9, 2019 at 6:47 PM Will Deacon <will@kernel.org> wrote:
> > On Wed, Aug 07, 2019 at 04:55:12PM +0100, Steve Capper wrote:
> > > This patch series adds support for 52-bit kernel VAs using some of the
> > > machinery already introduced by the 52-bit userspace VA code in 5.0.
> >
> > Cheers, I've pushed this out on a for-next/52-bit-kva branch with one
> > small patch on top and Catalin's tags added.
>
> As of commit 14c127c957c1c607 ("arm64: mm: Flip kernel VA space"), the
> kernel log is spammed with
>
> virt_to_phys used for non-linear address: (____ptrval____)
> (__func__.6603+0x14d681/0x17fb3d)
> WARNING: CPU: 0 PID: 264 at arch/arm64/mm/physaddr.c:15
> __virt_to_phys+0x28/0x58
> Modules linked in:
> CPU: 0 PID: 264 Comm: mdev Not tainted
> 5.3.0-rc3-rcar3-initrd-00002-g14c127c957c1c607 #38
> Hardware name: Renesas Ebisu-4D board based on r8a77990 (DT)
> pstate: 60000005 (nZCv daif -PAN -UAO)
> pc : __virt_to_phys+0x28/0x58
> lr : __virt_to_phys+0x28/0x58
> sp : ffffffc011953c80
> x29: ffffffc011953c80 x28: ffffff8078790140
> x27: 0000000000000000 x26: 0000000000000000
> x25: ffffffc010a539b9 x24: ffffffc010a86000
> x23: ffffffc010a539ba x22: 0000000000000001
> x21: 0000000000202038 x20: 0000000000000001
> x19: ffffffc010a539b9 x18: 000000000000000a
> x17: 0000000000000000 x16: 0000000000000000
> x15: 00000000000ca51d x14: 0720072007200720
> x13: 0720072007200720 x12: 0720072007200720
> x11: 0720072007200720 x10: 0720072007200720
> x9 : 0720072007200720 x8 : 0000000000000001
> x7 : 0000000000000007 x6 : ffffff8079824f00
> x5 : 0000000000000140 x4 : 0000000000000000
> x3 : 0000000000000000 x2 : 00000000ffffffff
> x1 : 0713abbc9281cf00 x0 : 0000000000000000
> Call trace:
> __virt_to_phys+0x28/0x58
> __check_object_size+0xd0/0x1e0
> filldir64+0x1d8/0x2b0
> kernfs_fop_readdir+0x64/0x200
> iterate_dir+0x68/0x144
> ksys_getdents64+0x88/0x154
> __arm64_sys_getdents64+0x18/0x24
> el0_svc_common.constprop.0+0x84/0xe8
> el0_svc_compat_handler+0x18/0x20
> el0_svc_compat+0x8/0x10
> ---[ end trace 6980a45f636e18be ]---
>
> as soon as userspace starts.
Can you try the hack I posted here, please?
https://lkml.org/lkml/2019/8/13/555
Also, what .config are you using?
Will
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^ permalink raw reply
* Re: [PATCH v3 2/4] perf: Use CAP_SYS_ADMIN with perf_event_paranoid checks
From: Arnaldo Carvalho de Melo @ 2019-08-13 13:20 UTC (permalink / raw)
To: Lubashev, Igor
Cc: Mathieu Poirier, Suzuki K Poulose, Peter Zijlstra,
Alexey Budankov, Arnaldo Carvalho de Melo,
linux-kernel@vger.kernel.org, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, James Morris, Jiri Olsa,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <735aabdfa76f4435bdaff2c63d566044@usma1ex-dag1mb6.msg.corp.akamai.com>
Em Mon, Aug 12, 2019 at 10:33:07PM +0000, Lubashev, Igor escreveu:
> On Mon, August 12, 2019 at 4:16 PM Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote:
> > Em Mon, Aug 12, 2019 at 05:01:34PM -0300, Arnaldo Carvalho de Melo
> > escreveu:
> > > Em Wed, Aug 07, 2019 at 10:44:15AM -0400, Igor Lubashev escreveu:
> > > > +++ b/tools/perf/util/evsel.c
> > > > @@ -279,7 +279,7 @@ struct evsel *perf_evsel__new_idx(struct
> > > > perf_event_attr *attr, int idx)
> > >
> > > > static bool perf_event_can_profile_kernel(void)
> > > > {
> > > > - return geteuid() == 0 || perf_event_paranoid() == -1;
> > > > + return perf_event_paranoid_check(-1);
> > > > }
> > >
> > > While looking at your changes I think the pre-existing code is wrong,
> > > i.e. the check in sys_perf_event_open(), in the kernel is:
> > >
> > > if (!attr.exclude_kernel) {
> > > if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
> > > return -EACCES;
> > > }
> > >
> > > And:
> > >
> > > static inline bool perf_paranoid_kernel(void) {
> > > return sysctl_perf_event_paranoid > 1; }
> > >
> > > So we have to change that perf_event_paranoit_check(-1) to pass 1
> > > instead?
>
> Indeed. This seems right. It was a pre-existing problem.
>
>
> > > bool perf_event_paranoid_check(int max_level) {
> > > return perf_cap__capable(CAP_SYS_ADMIN) ||
> > > perf_event_paranoid() <= max_level; }
> > >
> > > Also you defined perf_cap__capable(anything) as:
> > >
> > > #ifdef HAVE_LIBCAP_SUPPORT
> > >
> > > #include <sys/capability.h>
> > >
> > > bool perf_cap__capable(cap_value_t cap);
> > >
> > > #else
> > >
> > > static inline bool perf_cap__capable(int cap __maybe_unused)
> > > {
> > > return false;
> > > }
> > >
> > > #endif /* HAVE_LIBCAP_SUPPORT */
> > >
> > >
> > > I think we should have:
> > >
> > > #else
> > >
> > > static inline bool perf_cap__capable(int cap __maybe_unused) {
> > > return geteuid() == 0;
> > > }
> > >
> > > #endif /* HAVE_LIBCAP_SUPPORT */
> > >
> > > Right?
>
> You can have EUID==0 and not have CAP_SYS_ADMIN, though this would be rare in practice. I did not to use EUID in leu of libcap, since kernel does not do so, and therefore it seemed a bit misleading. But this is a slight matter of taste, and I do not see a problem with choosing to fall back to EUID -- the kernel will do the right thing anyway.
>
> Now, if I were pedantic, I'd say that to use geteuid(), you need to #include <unistd.h> .
Right, and that is how I did it :-)
[acme@seventh perf]$ cat tools/perf/util/cap.h
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PERF_CAP_H
#define __PERF_CAP_H
#include <stdbool.h>
#include <linux/capability.h>
#include <linux/compiler.h>
#ifdef HAVE_LIBCAP_SUPPORT
#include <sys/capability.h>
bool perf_cap__capable(cap_value_t cap);
#else
#include <unistd.h>
#include <sys/types.h>
static inline bool perf_cap__capable(int cap __maybe_unused)
{
return geteuid() == 0;
}
#endif /* HAVE_LIBCAP_SUPPORT */
#endif /* __PERF_CAP_H */
[acme@seventh perf]$
>
> > > So I am removing the introduction of perf_cap__capable() from the
> > > first patch you sent, leaving it with _only_ the feature detection
> > > part, using that feature detection to do anything is then moved to a
> > > separate patch, after we finish this discussion about what we should
> > > fallback to when libcap-devel isn't available, i.e. we should use the
> > > previous checks, etc.
> >
> > So, please take a look at the tmp.perf/cap branch in my git repo:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/log/?h=tmp.p
> > erf/cap
> >
> > I split the patch and made perf_cap__capable() fallback to 'return
> > geteuid() == 0;' when libcap-devel isn't available, i.e. keep the checks made
> > prior to your patchset.
>
> Thank you. And thanks for updating "make_minimal".
Ok!
> >
> > Jiri, can I keep your Acked-by?
> >
> > - Arnaldo
--
- Arnaldo
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^ permalink raw reply
* Re: [PATCH v3 02/11] kselftest: arm64: adds first test and common utils
From: Cristian Marussi @ 2019-08-13 13:22 UTC (permalink / raw)
To: Amit Kachhap, linux-kselftest@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, shuah@kernel.org
Cc: andreyknvl@google.com, Dave P Martin
In-Reply-To: <23e44146-92cc-73de-0eab-a1e7b82ea3bc@arm.com>
Hi Amit
thanks for the review.
On 12/08/2019 13:43, Amit Kachhap wrote:
> Hi Cristian,
>
> On 8/2/19 10:32 PM, Cristian Marussi wrote:
>> Added some arm64/signal specific boilerplate and utility code to help
>> further testcase development.
>>
>> A simple testcase and related helpers are also introduced in this commit:
>> mangle_pstate_invalid_compat_toggle is a simple mangle testcase which
>> messes with the ucontext_t from within the sig_handler, trying to toggle
>> PSTATE state bits to switch the system between 32bit/64bit execution state.
>> Expects SIGSEGV on test PASS.
>>
>> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
>> ---
>> A few fixes:
>> - test_arm64_signals.sh runner script generation has been reviewed in order to
>> be safe against the .gitignore
>> - using kselftest.h officially provided defines for tests' return values
>> - removed SAFE_WRITE()/dump_uc()
>> - looking for si_code==SEGV_ACCERR on SEGV test cases to better understand if
>> the sigfault had been directly triggered by Kernel
>> ---
>> tools/testing/selftests/arm64/Makefile | 2 +-
>> .../testing/selftests/arm64/signal/.gitignore | 6 +
>> tools/testing/selftests/arm64/signal/Makefile | 88 ++++++
>> tools/testing/selftests/arm64/signal/README | 59 ++++
>> .../arm64/signal/test_arm64_signals.src_shell | 55 ++++
>> .../selftests/arm64/signal/test_signals.c | 26 ++
>> .../selftests/arm64/signal/test_signals.h | 137 +++++++++
>> .../arm64/signal/test_signals_utils.c | 261 ++++++++++++++++++
>> .../arm64/signal/test_signals_utils.h | 13 +
>> .../arm64/signal/testcases/.gitignore | 1 +
>> .../mangle_pstate_invalid_compat_toggle.c | 25 ++
>> .../arm64/signal/testcases/testcases.c | 150 ++++++++++
>> .../arm64/signal/testcases/testcases.h | 83 ++++++
>> 13 files changed, 905 insertions(+), 1 deletion(-)
>> create mode 100644 tools/testing/selftests/arm64/signal/.gitignore
>> create mode 100644 tools/testing/selftests/arm64/signal/Makefile
>> create mode 100644 tools/testing/selftests/arm64/signal/README
>> create mode 100755 tools/testing/selftests/arm64/signal/test_arm64_signals.src_shell
>> create mode 100644 tools/testing/selftests/arm64/signal/test_signals.c
>> create mode 100644 tools/testing/selftests/arm64/signal/test_signals.h
>> create mode 100644 tools/testing/selftests/arm64/signal/test_signals_utils.c
>> create mode 100644 tools/testing/selftests/arm64/signal/test_signals_utils.h
>> create mode 100644 tools/testing/selftests/arm64/signal/testcases/.gitignore
>> create mode 100644 tools/testing/selftests/arm64/signal/testcases/mangle_pstate_invalid_compat_toggle.c
>> create mode 100644 tools/testing/selftests/arm64/signal/testcases/testcases.c
>> create mode 100644 tools/testing/selftests/arm64/signal/testcases/testcases.h
>>
>> diff --git a/tools/testing/selftests/arm64/Makefile b/tools/testing/selftests/arm64/Makefile
>> index 03a0d4f71218..af59dc74e0dc 100644
>> --- a/tools/testing/selftests/arm64/Makefile
>> +++ b/tools/testing/selftests/arm64/Makefile
>> @@ -6,7 +6,7 @@ ARCH ?= $(shell uname -m)
>> ARCH := $(shell echo $(ARCH) | sed -e s/aarch64/arm64/)
>>
>> ifeq ("x$(ARCH)", "xarm64")
>> -SUBDIRS :=
>> +SUBDIRS := signal
>> else
>> SUBDIRS :=
>> endif
>> diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore
>> new file mode 100644
>> index 000000000000..434f65c15f03
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/.gitignore
>> @@ -0,0 +1,6 @@
>> +# Helper script's internal testcases list (TPROGS) is regenerated
>> +# each time by Makefile on standalone (non KSFT driven) runs.
>> +# Committing such list creates a dependency between testcases
>> +# patches such that they are no more easily revertable. Just ignore.
>> +test_arm64_signals.src_shell
>> +test_arm64_signals.sh
>> diff --git a/tools/testing/selftests/arm64/signal/Makefile b/tools/testing/selftests/arm64/signal/Makefile
>> new file mode 100644
>> index 000000000000..8c8d08be4b0d
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/Makefile
>> @@ -0,0 +1,88 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +# Copyright (C) 2019 ARM Limited
>> +
>> +# Supports also standalone invokation out of KSFT-tree
>> +# Compile standalone and run on your device with:
>> +#
>> +# $ make -C tools/testing/selftests/arm64/signal INSTALL_PATH=<your-dir> install
>> +#
>> +# Run standalone on device with:
>> +#
>> +# $ <your-device-instdir>/test_arm64_signals.sh [-k|-v]
>> +#
>> +# If INSTALL_PATH= is NOT provided it will default to ./install
>> +
>> +# A proper top_srcdir is needed both by KSFT(lib.mk)
>> +# and standalone builds
>> +top_srcdir = ../../../../..
>> +
>> +CFLAGS += -std=gnu99 -I. -I$(top_srcdir)/tools/testing/selftests/
>> +SRCS := $(filter-out testcases/testcases.c,$(wildcard testcases/*.c))
>> +PROGS := $(patsubst %.c,%,$(SRCS))
>> +
>> +# Guessing as best as we can where the Kernel headers
>> +# could have been installed depending on ENV config and
>> +# type of invocation.
>> +ifeq ($(KBUILD_OUTPUT),)
>> +khdr_dir = $(top_srcdir)/usr/include
>> +else
>> +ifeq (0,$(MAKELEVEL))
>> +khdr_dir = $(KBUILD_OUTPUT)/usr/include
>> +else
>> +# the KSFT preferred location when KBUILD_OUTPUT is set
>> +khdr_dir = $(KBUILD_OUTPUT)/kselftest/usr/include
>> +endif
>> +endif
>> +
>> +CFLAGS += -I$(khdr_dir)
>> +
>> +# Standalone run
>> +ifeq (0,$(MAKELEVEL))
>> +CC := $(CROSS_COMPILE)gcc
>> +RUNNER_SRC = test_arm64_signals.src_shell
>> +RUNNER = test_arm64_signals.sh
>> +INSTALL_PATH ?= install/
>> +
>> +all: $(RUNNER)
>> +
>> +$(RUNNER): $(PROGS)
>> + cp $(RUNNER_SRC) $(RUNNER)
>> + sed -i -e 's#PROGS=.*#PROGS="$(PROGS)"#' $@
>> +
>> +install: all
>> + mkdir -p $(INSTALL_PATH)/testcases
>> + cp $(PROGS) $(INSTALL_PATH)/testcases
>> + cp $(RUNNER) $(INSTALL_PATH)/
>> +
>> +.PHONY clean:
>> + rm -f $(PROGS)
>> +# KSFT run
>> +else
>> +# Generated binaries to be installed by top KSFT script
>> +TEST_GEN_PROGS := $(notdir $(PROGS))
>> +
>> +# Get Kernel headers installed and use them.
>> +KSFT_KHDR_INSTALL := 1
>> +
>> +# This include mk will also mangle the TEST_GEN_PROGS list
>> +# to account for any OUTPUT target-dirs optionally provided
>> +# by the toplevel makefile
>> +include ../../lib.mk
>> +
>> +$(TEST_GEN_PROGS): $(PROGS)
>> + cp $(PROGS) $(OUTPUT)/
>> +
>> +clean:
>> + $(CLEAN)
>> + rm -f $(PROGS)
>> +endif
>> +
>> +# Common test-unit targets to build common-layout test-cases executables
>> +# Needs secondary expansion to properly include the testcase c-file in pre-reqs
>> +.SECONDEXPANSION:
>> +$(PROGS): test_signals.c test_signals_utils.c testcases/testcases.c $$@.c test_signals.h test_signals_utils.h testcases/testcases.h
>
> I suppose *.h can be removed from the targets here.
*.h are in the pre-reqs, $(PROGS) represent the targets and it's comprised by the *.c file contained in testcases/ (excluding testcases.c)
If I remove the *.h from this rule, targets won't be rebuilt when headers are changed (like after having added an hypotethical inline)...
or am I missing something else ?
>
>
>> + @if [ ! -d $(khdr_dir) ]; then \
>> + echo -n "\n!!! WARNING: $(khdr_dir) NOT FOUND."; \
>> + echo "===> Are you sure Kernel Headers have been installed properly ?\n"; \
>> + fi
>> + $(CC) $(CFLAGS) $^ -o $@
>> diff --git a/tools/testing/selftests/arm64/signal/README b/tools/testing/selftests/arm64/signal/README
>> new file mode 100644
>> index 000000000000..53f005f7910a
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/README
>> @@ -0,0 +1,59 @@
>> +KSelfTest arm64/signal/
>> +=======================
>> +
>> +Signals Tests
>> ++++++++++++++
>> +
>> +- Tests are built around a common main compilation unit: such shared main
>> + enforces a standard sequence of operations needed to perform a single
>> + signal-test (setup/trigger/run/result/cleanup)
>> +
>> +- The above mentioned ops are configurable on a test-by-test basis: each test
>> + is described (and configured) using the descriptor signals.h::struct tdescr
>> +
>> +- Each signal testcase is compiled into its own executable: a separate
>> + executable is used for each test since many tests complete successfully
>> + by receiving some kind of fatal signal from the Kernel, so it's safer
>> + to run each test unit in its own standalone process, so as to start each
>> + test from a clean slate.
>> +
>> +- New tests can be simply defined in testcases/ dir providing a proper struct
>> + tdescr overriding all the defaults we wish to change (as of now providing a
>> + custom run method is mandatory though)
>> +
>> +- Signals' test-cases hereafter defined belong currently to two
>> + principal families:
>> +
>> + - 'mangle_' tests: a real signal (SIGUSR1) is raised and used as a trigger
>> + and then the test case code messes-up with the sigframe ucontext_t from
>> + inside the sighandler itself.
>> +
>> + - 'fake_sigreturn_' tests: a brand new custom artificial sigframe structure
>> + is placed on the stack and a sigreturn syscall is called to simulate a
>> + real signal return. This kind of tests does not use a trigger usually and
>> + they are just fired using some simple included assembly trampoline code.
>> +
>> + - Most of these tests are successfully passing if the process gets killed by
>> + some fatal signal: usually SIGSEGV or SIGBUS. Since while writing this
>> + kind of tests it is extremely easy in fact to end-up injecting other
>> + unrelated SEGV bugs in the testcases, it becomes extremely tricky to
>> + be really sure that the tests are really addressing what they are meant
>> + to address and they are not instead falling apart due to unplanned bugs
>> + in the test code.
>> + In order to alleviate the misery of the life of such test-developer, a few
>> + helpers are provided:
>> +
>> + - a couple of ASSERT_BAD/GOOD_CONTEXT() macros to easily parse a ucontext_t
>> + and verify if it is indeed GOOD or BAD (depending on what we were
>> + expecting), using the same logic/perspective as in the arm64 Kernel signals
>> + routines.
>> +
>> + - a sanity mechanism to be used in 'fake_sigreturn_'-alike tests: enabled by
>> + default it takes care to verify that the test-execution had at least
>> + successfully progressed up to the stage of triggering the fake sigreturn
>> + call.
>> +
>> + In both cases test results are expected in terms of:
>> + - some fatal signal sent by the Kernel to the test process
>> + or
>> + - analyzing some final regs state
>> diff --git a/tools/testing/selftests/arm64/signal/test_arm64_signals.src_shell b/tools/testing/selftests/arm64/signal/test_arm64_signals.src_shell
>> new file mode 100755
>> index 000000000000..163e941e2997
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/test_arm64_signals.src_shell
>> @@ -0,0 +1,55 @@
>> +#!/bin/sh
>> +# SPDX-License-Identifier: GPL-2.0
>> +# Copyright (C) 2019 ARM Limited
>> +
>> +ret=0
>> +keep_on_fail=0
>> +err_out="2> /dev/null"
>> +
>> +usage() {
>> + echo "Usage: `basename $0` [-v] [-k]"
>> + exit 1
>> +}
>> +
>> +# avoiding getopt to avoid compatibility issues on targets
>> +# with limited resources
>> +while [ $# -gt 0 ]
>> +do
>> + case $1 in
>> + "-k")
>> + keep_on_fail=1
>> + ;;
>> + "-v")
>> + err_out=
>> + ;;
>> + *)
>> + usage
>> + ;;
>> + esac
>> + shift
>> +done
>> +
>> +TPROGS=
>> +
>> +tot=$(echo $TPROGS | wc -w)
>> +
>> +# Tests are expected in testcases/ subdir inside the installation path
>> +workdir="`dirname $0 2>/dev/null`"
>> +[ -n $workdir ] && cd $workdir
>> +
>> +passed=0
>> +run=0
>> +for test in $TPROGS
>> +do
>> + run=$((run + 1))
>> + eval ./$test $err_out
>> + if [ $? != 0 ]; then
>> + [ $keep_on_fail = 0 ] && echo "===>>> FAILED:: $test <<<===" && ret=1 && break
>> + else
>> + passed=$((passed + 1))
>> + fi
>> +done
>> +
>> +echo "==>> PASSED: $passed/$run on $tot available tests."
>> +
>> +exit $ret
>> diff --git a/tools/testing/selftests/arm64/signal/test_signals.c b/tools/testing/selftests/arm64/signal/test_signals.c
>> new file mode 100644
>> index 000000000000..3447d7011aec
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/test_signals.c
>> @@ -0,0 +1,26 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (C) 2019 ARM Limited */
>> +
>> +#include <kselftest.h>
>> +
>> +#include "test_signals.h"
>> +#include "test_signals_utils.h"
>> +
>> +struct tdescr *current;
>> +extern struct tdescr tde;
>> +
>> +int main(int argc, char *argv[])
>> +{
>> + current = &tde;
>> +
>> + ksft_print_msg("%s :: %s - SIG_TRIG:%d SIG_OK:%d -- current:%p\n",
>> + current->name, current->descr, current->sig_trig,
>> + current->sig_ok, current);
>> + if (test_setup(current)) {
>> + if (test_run(current))
>> + test_result(current);
>> + test_cleanup(current);
>> + }
>> +
>> + return current->pass ? KSFT_PASS : KSFT_FAIL;
>> +}
>> diff --git a/tools/testing/selftests/arm64/signal/test_signals.h b/tools/testing/selftests/arm64/signal/test_signals.h
>> new file mode 100644
>> index 000000000000..85db3ac44b32
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/test_signals.h
>> @@ -0,0 +1,137 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (C) 2019 ARM Limited */
>> +
>> +#ifndef __TEST_SIGNALS_H__
>> +#define __TEST_SIGNALS_H__
>> +
>> +#include <assert.h>
>> +#include <stdbool.h>
>> +#include <signal.h>
>> +#include <ucontext.h>
>> +#include <stdint.h>
> Headers can be added in alphabetically order.
>
Ok I'll do.
Cheers
Cristian
> Thanks,
> Amit D
>> +
>> +/*
>> + * Using ARCH specific and sanitized Kernel headers installed by KSFT
>> + * framework since we asked for it by setting flag KSFT_KHDR_INSTALL
>> + * in our Makefile.
>> + */
>> +#include <asm/ptrace.h>
>> +#include <asm/hwcap.h>
>> +
>> +/* pasted from include/linux/stringify.h */
>> +#define __stringify_1(x...) #x
>> +#define __stringify(x...) __stringify_1(x)
>> +
>> +/*
>> + * Reads a sysreg using the, possibly provided, S3_ encoding in order to
>> + * avoid inject any dependency on the used toolchain regarding possibly
>> + * still unsupported ARMv8 extensions.
>> + *
>> + * Using a standard mnemonic here to indicate the specific sysreg (like SSBS)
>> + * would introduce a compile-time dependency on possibly unsupported ARMv8
>> + * Extensions: you could end-up failing to build the test depending on the
>> + * available toolchain.
>> + * This is undesirable since some tests, even if specifically targeted at some
>> + * ARMv8 Extensions, can be plausibly run even on hardware lacking the above
>> + * optional ARM features. (SSBS bit preservation is an example: Kernel handles
>> + * it transparently not caring at all about the effective set of supported
>> + * features).
>> + * On the other side we will expect to observe different behaviours if the
>> + * feature is supported or not: usually getting a SIGILL when trying to use
>> + * unsupported features. For this reason we have anyway in place some
>> + * preliminary run-time checks about the cpu effectively supported features.
>> + *
>> + * This helper macro is meant to be used for regs readable at EL0, BUT some
>> + * EL1 sysregs are indeed readable too through MRS emulation Kernel-mechanism
>> + * if the required reg is included in the supported encoding space:
>> + *
>> + * Documentation/arm64/cpu-feature-regsiters.txt
>> + *
>> + * "The infrastructure emulates only the following system register space:
>> + * Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
>> + */
>> +#define get_regval(regname, out) \
>> + asm volatile("mrs %0, " __stringify(regname) : "=r" (out) :: "memory")
>> +
>> +/* Regs encoding and masks naming copied in from sysreg.h */
>> +#define SYS_ID_AA64MMFR1_EL1 S3_0_C0_C7_1 /* MRS Emulated */
>> +#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2 /* MRS Emulated */
>> +#define ID_AA64MMFR1_PAN_SHIFT 20
>> +#define ID_AA64MMFR2_UAO_SHIFT 4
>> +
>> +/* Local Helpers */
>> +#define IS_PAN_SUPPORTED(val) \
>> + (!!((val) & (0xfUL << ID_AA64MMFR1_PAN_SHIFT)))
>> +#define IS_UAO_SUPPORTED(val) \
>> + (!!((val) & (0xfUL << ID_AA64MMFR2_UAO_SHIFT)))
>> +
>> +#define S3_MRS_SSBS_SYSREG S3_3_C4_C2_6 /* EL0 supported */
>> +
>> +/*
>> + * Feature flags used in tdescr.feats_required to specify
>> + * any feature by the test
>> + */
>> +enum {
>> + FSSBS_BIT,
>> + FPAN_BIT,
>> + FUAO_BIT,
>> + FMAX_END
>> +};
>> +
>> +#define FEAT_SSBS (1UL << FSSBS_BIT)
>> +#define FEAT_PAN (1UL << FPAN_BIT)
>> +#define FEAT_UAO (1UL << FUAO_BIT)
>> +
>> +/*
>> + * A descriptor used to describe and configure a test case.
>> + * Fields with a non-trivial meaning are described inline in the following.
>> + */
>> +struct tdescr {
>> + /* KEEP THIS FIELD FIRST for easier lookup from assembly */
>> + void *token;
>> + /* when disabled token based sanity checking is skipped in handler */
>> + bool sanity_disabled;
>> + /* just a name for the test-case; manadatory field */
>> + char *name;
>> + char *descr;
>> + unsigned long feats_required;
>> + /* bitmask of effectively supported feats: populated at run-time */
>> + unsigned long feats_supported;
>> + bool feats_ok;
>> + bool initialized;
>> + unsigned int minsigstksz;
>> + /* signum used as a test trigger. Zero if no trigger-signal is used */
>> + int sig_trig;
>> + /*
>> + * signum considered as a successful test completion.
>> + * Zero when no signal is expected on success
>> + */
>> + int sig_ok;
>> + /* signum expected on unsupported CPU features. */
>> + int sig_unsupp;
>> + /* a timeout in second for test completion */
>> + unsigned int timeout;
>> + bool triggered;
>> + bool pass;
>> + /* optional sa_flags for the installed handler */
>> + int sa_flags;
>> + ucontext_t saved_uc;
>> +
>> + /* a setup function to be called before test starts */
>> + int (*setup)(struct tdescr *td);
>> + void (*cleanup)(struct tdescr *td);
>> +
>> + /* an optional function to be used as a trigger for test starting */
>> + int (*trigger)(struct tdescr *td);
>> + /*
>> + * the actual test-core: invoked differently depending on the
>> + * presence of the trigger function above; this is mandatory
>> + */
>> + int (*run)(struct tdescr *td, siginfo_t *si, ucontext_t *uc);
>> +
>> + /* an optional function for custom results' processing */
>> + void (*check_result)(struct tdescr *td);
>> +
>> + void *priv;
>> +};
>> +#endif
>> diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.c b/tools/testing/selftests/arm64/signal/test_signals_utils.c
>> new file mode 100644
>> index 000000000000..ac0055f6340b
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/test_signals_utils.c
>> @@ -0,0 +1,261 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (C) 2019 ARM Limited */
>> +
>> +#include <stdio.h>
>> +#include <stdlib.h>
>> +#include <signal.h>
>> +#include <string.h>
>> +#include <unistd.h>
>> +#include <assert.h>
>> +#include <sys/auxv.h>
>> +#include <linux/auxvec.h>
>> +#include <ucontext.h>
>> +
>> +#include "test_signals.h"
>> +#include "test_signals_utils.h"
>> +#include "testcases/testcases.h"
>> +
>> +extern struct tdescr *current;
>> +
>> +static char *feats_store[FMAX_END] = {
>> + "SSBS",
>> + "PAN",
>> + "UAO"
>> +};
>> +
>> +#define MAX_FEATS_SZ 128
>> +static inline char *feats_to_string(unsigned long feats)
>> +{
>> + static char feats_string[MAX_FEATS_SZ];
>> +
>> + for (int i = 0; i < FMAX_END && feats_store[i][0]; i++) {
>> + if (feats & 1UL << i)
>> + snprintf(feats_string, MAX_FEATS_SZ - 1, "%s %s ",
>> + feats_string, feats_store[i]);
>> + }
>> +
>> + return feats_string;
>> +}
>> +
>> +static void unblock_signal(int signum)
>> +{
>> + sigset_t sset;
>> +
>> + sigemptyset(&sset);
>> + sigaddset(&sset, signum);
>> + sigprocmask(SIG_UNBLOCK, &sset, NULL);
>> +}
>> +
>> +static void default_result(struct tdescr *td, bool force_exit)
>> +{
>> + if (td->pass)
>> + fprintf(stderr, "==>> completed. PASS(1)\n");
>> + else
>> + fprintf(stdout, "==>> completed. FAIL(0)\n");
>> + if (force_exit)
>> + exit(td->pass ? EXIT_SUCCESS : EXIT_FAILURE);
>> +}
>> +
>> +static inline bool are_feats_ok(struct tdescr *td)
>> +{
>> + return td ? td->feats_required == td->feats_supported : 0;
>> +}
>> +
>> +static void default_handler(int signum, siginfo_t *si, void *uc)
>> +{
>> + if (current->sig_trig && signum == current->sig_trig) {
>> + fprintf(stderr, "Handling SIG_TRIG\n");
>> + current->triggered = 1;
>> + /* ->run was asserted NON-NULL in test_setup() already */
>> + current->run(current, si, uc);
>> + } else if (signum == SIGILL && !current->initialized) {
>> + /*
>> + * A SIGILL here while still not initialized means we failed
>> + * even to asses the existence of features during init
>> + */
>> + fprintf(stdout,
>> + "Got SIGILL test_init. Marking ALL features UNSUPPORTED.\n");
>> + current->feats_supported = 0;
>> + } else if (current->sig_ok && signum == current->sig_ok) {
>> + /* it's a bug in the test code when this assert fail */
>> + assert(!current->sig_trig || current->triggered);
>> + fprintf(stderr,
>> + "SIG_OK -- SP:%p si_addr@:0x%p si_code:%d token@:0x%p offset:%ld\n",
>> + ((ucontext_t *)uc)->uc_mcontext.sp,
>> + si->si_addr, si->si_code, current->token,
>> + current->token - si->si_addr);
>> + /*
>> + * fake_sigreturn tests, which have sanity_enabled=1, set, at
>> + * the very last time, the token field to the SP address used
>> + * to place the fake sigframe: so token==0 means we never made
>> + * it to the end, segfaulting well-before, and the test is
>> + * possibly broken.
>> + */
>> + if (!current->sanity_disabled && !current->token) {
>> + fprintf(stdout,
>> + "current->token ZEROED...test is probably broken!\n");
>> + assert(0);
>> + }
>> + /*
>> + * Trying to narrow down the SEGV to the ones generated by
>> + * Kernel itself via arm64_notify_segfault()
>> + */
>> + if (current->sig_ok == SIGSEGV && si->si_code != SEGV_ACCERR) {
>> + fprintf(stdout,
>> + "si_code != SEGV_ACCERR...test is probably broken!\n");
>> + assert(0);
>> + }
>> + fprintf(stderr, "Handling SIG_OK\n");
>> + current->pass = 1;
>> + /*
>> + * Some tests can lead to SEGV loops: in such a case we want
>> + * to terminate immediately exiting straight away
>> + */
>> + default_result(current, 1);
>> + } else {
>> + if (signum == current->sig_unsupp && !are_feats_ok(current)) {
>> + fprintf(stderr, "-- RX SIG_UNSUPP on unsupported feature...OK\n");
>> + current->pass = 1;
>> + } else if (signum == SIGALRM && current->timeout) {
>> + fprintf(stderr, "-- Timeout !\n");
>> + } else {
>> + fprintf(stderr,
>> + "-- RX UNEXPECTED SIGNAL: %d\n", signum);
>> + }
>> + default_result(current, 1);
>> + }
>> +}
>> +
>> +static int default_setup(struct tdescr *td)
>> +{
>> + struct sigaction sa;
>> +
>> + sa.sa_sigaction = default_handler;
>> + sa.sa_flags = SA_SIGINFO;
>> + if (td->sa_flags)
>> + sa.sa_flags |= td->sa_flags;
>> + sigemptyset(&sa.sa_mask);
>> + /* uncatchable signals naturally skipped ... */
>> + for (int sig = 1; sig < 32; sig++)
>> + sigaction(sig, &sa, NULL);
>> + /*
>> + * RT Signals default disposition is Term but they cannot be
>> + * generated by the Kernel in response to our tests; so just catch
>> + * them all and report them as UNEXPECTED signals.
>> + */
>> + for (int sig = SIGRTMIN; sig <= SIGRTMAX; sig++)
>> + sigaction(sig, &sa, NULL);
>> +
>> + /* just in case...unblock explicitly all we need */
>> + if (td->sig_trig)
>> + unblock_signal(td->sig_trig);
>> + if (td->sig_ok)
>> + unblock_signal(td->sig_ok);
>> + if (td->sig_unsupp)
>> + unblock_signal(td->sig_unsupp);
>> +
>> + if (td->timeout) {
>> + unblock_signal(SIGALRM);
>> + alarm(td->timeout);
>> + }
>> + fprintf(stderr, "Registered handlers for all signals.\n");
>> +
>> + return 1;
>> +}
>> +
>> +static inline int default_trigger(struct tdescr *td)
>> +{
>> + return !raise(td->sig_trig);
>> +}
>> +
>> +static int test_init(struct tdescr *td)
>> +{
>> + td->minsigstksz = getauxval(AT_MINSIGSTKSZ);
>> + if (!td->minsigstksz)
>> + td->minsigstksz = MINSIGSTKSZ;
>> + fprintf(stderr, "Detected MINSTKSIGSZ:%d\n", td->minsigstksz);
>> +
>> + if (td->feats_required) {
>> + bool feats_ok = false;
>> + td->feats_supported = 0;
>> + /*
>> + * Checking for CPU required features using both the
>> + * auxval and the arm64 MRS Emulation to read sysregs.
>> + */
>> + if (getauxval(AT_HWCAP) & HWCAP_CPUID) {
>> + uint64_t val = 0;
>> +
>> + if (td->feats_required & FEAT_SSBS) {
>> + /* Uses HWCAP to check capability */
>> + if (getauxval(AT_HWCAP) & HWCAP_SSBS)
>> + td->feats_supported |= FEAT_SSBS;
>> + }
>> + if (td->feats_required & FEAT_PAN) {
>> + /* Uses MRS emulation to check capability */
>> + get_regval(SYS_ID_AA64MMFR1_EL1, val);
>> + if (IS_PAN_SUPPORTED(val))
>> + td->feats_supported |= FEAT_PAN;
>> + }
>> + if (td->feats_required & FEAT_UAO) {
>> + /* Uses MRS emulation to check capability */
>> + get_regval(SYS_ID_AA64MMFR2_EL1 , val);
>> + if (IS_UAO_SUPPORTED(val))
>> + td->feats_supported |= FEAT_UAO;
>> + }
>> + } else {
>> + fprintf(stderr,
>> + "HWCAP_CPUID NOT available. Mark ALL feats UNSUPPORTED.\n");
>> + }
>> + feats_ok = are_feats_ok(td);
>> + fprintf(stderr,
>> + "Required Features: [%s] %ssupported\n",
>> + feats_ok ? feats_to_string(td->feats_supported) :
>> + feats_to_string(td->feats_required ^ td->feats_supported),
>> + !feats_ok ? "NOT " : "");
>> + }
>> +
>> + td->initialized = 1;
>> + return 1;
>> +}
>> +
>> +int test_setup(struct tdescr *td)
>> +{
>> + /* assert core invariants symptom of a rotten testcase */
>> + assert(current);
>> + assert(td);
>> + assert(td->name);
>> + assert(td->run);
>> +
>> + if (!test_init(td))
>> + return 0;
>> +
>> + if (td->setup)
>> + return td->setup(td);
>> + else
>> + return default_setup(td);
>> +}
>> +
>> +int test_run(struct tdescr *td)
>> +{
>> + if (td->sig_trig) {
>> + if (td->trigger)
>> + return td->trigger(td);
>> + else
>> + return default_trigger(td);
>> + } else {
>> + return td->run(td, NULL, NULL);
>> + }
>> +}
>> +
>> +void test_result(struct tdescr *td)
>> +{
>> + if (td->check_result)
>> + td->check_result(td);
>> + default_result(td, 0);
>> +}
>> +
>> +void test_cleanup(struct tdescr *td)
>> +{
>> + if (td->cleanup)
>> + td->cleanup(td);
>> +}
>> diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.h b/tools/testing/selftests/arm64/signal/test_signals_utils.h
>> new file mode 100644
>> index 000000000000..8658d1a7d4b9
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/test_signals_utils.h
>> @@ -0,0 +1,13 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (C) 2019 ARM Limited */
>> +
>> +#ifndef __TEST_SIGNALS_UTILS_H__
>> +#define __TEST_SIGNALS_UTILS_H__
>> +
>> +#include "test_signals.h"
>> +
>> +int test_setup(struct tdescr *td);
>> +void test_cleanup(struct tdescr *td);
>> +int test_run(struct tdescr *td);
>> +void test_result(struct tdescr *td);
>> +#endif
>> diff --git a/tools/testing/selftests/arm64/signal/testcases/.gitignore b/tools/testing/selftests/arm64/signal/testcases/.gitignore
>> new file mode 100644
>> index 000000000000..8651272e3cfc
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/testcases/.gitignore
>> @@ -0,0 +1 @@
>> +mangle_pstate_invalid_compat_toggle
>> diff --git a/tools/testing/selftests/arm64/signal/testcases/mangle_pstate_invalid_compat_toggle.c b/tools/testing/selftests/arm64/signal/testcases/mangle_pstate_invalid_compat_toggle.c
>> new file mode 100644
>> index 000000000000..971193e7501b
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/testcases/mangle_pstate_invalid_compat_toggle.c
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright (C) 2019 ARM Limited */
>> +
>> +#include "test_signals_utils.h"
>> +#include "testcases.h"
>> +
>> +static int mangle_invalid_pstate_run(struct tdescr *td, siginfo_t *si,
>> + ucontext_t *uc)
>> +{
>> + ASSERT_GOOD_CONTEXT(uc);
>> +
>> + /* This config should trigger a SIGSEGV by Kernel */
>> + uc->uc_mcontext.pstate ^= PSR_MODE32_BIT;
>> +
>> + return 1;
>> +}
>> +
>> +struct tdescr tde = {
>> + .sanity_disabled = true,
>> + .name = "MANGLE_PSTATE_INVALID_STATE_TOGGLE",
>> + .descr = "Mangling uc_mcontext with INVALID STATE_TOGGLE",
>> + .sig_trig = SIGUSR1,
>> + .sig_ok = SIGSEGV,
>> + .run = mangle_invalid_pstate_run,
>> +};
>> diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c
>> new file mode 100644
>> index 000000000000..a59785092e1f
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c
>> @@ -0,0 +1,150 @@
>> +#include "testcases.h"
>> +
>> +struct _aarch64_ctx *get_header(struct _aarch64_ctx *head, uint32_t magic,
>> + size_t resv_sz, size_t *offset)
>> +{
>> + size_t offs = 0;
>> + struct _aarch64_ctx *found = NULL;
>> +
>> + if (!head || resv_sz < HDR_SZ)
>> + return found;
>> +
>> + do {
>> + if (head->magic == magic) {
>> + found = head;
>> + break;
>> + }
>> + offs += head->size;
>> + head = GET_RESV_NEXT_HEAD(head);
>> + } while (offs < resv_sz - HDR_SZ);
>> +
>> + if (offset)
>> + *offset = offs;
>> +
>> + return found;
>> +}
>> +
>> +bool validate_extra_context(struct extra_context *extra, char **err)
>> +{
>> + struct _aarch64_ctx *term;
>> +
>> + if (!extra || !err)
>> + return false;
>> +
>> + fprintf(stderr, "Validating EXTRA...\n");
>> + term = GET_RESV_NEXT_HEAD(extra);
>> + if (!term || term->magic || term->size) {
>> + *err = "UN-Terminated EXTRA context";
>> + return false;
>> + }
>> + if (extra->datap & 0x0fUL)
>> + *err = "Extra DATAP misaligned";
>> + else if (extra->size & 0x0fUL)
>> + *err = "Extra SIZE misaligned";
>> + else if (extra->datap != (uint64_t)term + sizeof(*term))
>> + *err = "Extra DATAP misplaced (not contiguos)";
>> + if (*err)
>> + return false;
>> +
>> + return true;
>> +}
>> +
>> +bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err)
>> +{
>> + bool terminated = false;
>> + size_t offs = 0;
>> + int flags = 0;
>> + struct extra_context *extra = NULL;
>> + struct _aarch64_ctx *head =
>> + (struct _aarch64_ctx *)uc->uc_mcontext.__reserved;
>> +
>> + if (!err)
>> + return false;
>> + /* Walk till the end terminator verifying __reserved contents */
>> + while (head && !terminated && offs < resv_sz) {
>> + if ((uint64_t)head & 0x0fUL) {
>> + *err = "Misaligned HEAD";
>> + return false;
>> + }
>> +
>> + switch (head->magic) {
>> + case 0:
>> + if (head->size)
>> + *err = "Bad size for MAGIC0";
>> + else
>> + terminated = true;
>> + break;
>> + case FPSIMD_MAGIC:
>> + if (flags & FPSIMD_CTX)
>> + *err = "Multiple FPSIMD_MAGIC";
>> + else if (head->size !=
>> + sizeof(struct fpsimd_context))
>> + *err = "Bad size for fpsimd_context";
>> + flags |= FPSIMD_CTX;
>> + break;
>> + case ESR_MAGIC:
>> + if (head->size != sizeof(struct esr_context))
>> + fprintf(stderr,
>> + "Bad size for esr_context is not an error...just ignore.\n");
>> + break;
>> + case SVE_MAGIC:
>> + if (flags & SVE_CTX)
>> + *err = "Multiple SVE_MAGIC";
>> + else if (head->size !=
>> + sizeof(struct sve_context))
>> + *err = "Bad size for sve_context";
>> + flags |= SVE_CTX;
>> + break;
>> + case EXTRA_MAGIC:
>> + if (flags & EXTRA_CTX)
>> + *err = "Multiple EXTRA_MAGIC";
>> + else if (head->size !=
>> + sizeof(struct extra_context))
>> + *err = "Bad size for extra_context";
>> + flags |= EXTRA_CTX;
>> + extra = (struct extra_context *)head;
>> + break;
>> + case KSFT_BAD_MAGIC:
>> + /*
>> + * This is a BAD magic header defined
>> + * artificially by a testcase and surely
>> + * unknown to the Kernel parse_user_sigframe().
>> + * It MUST cause a Kernel induced SEGV
>> + */
>> + *err = "BAD MAGIC !";
>> + break;
>> + default:
>> + /*
>> + * A still unknown Magic: potentially freshly added
>> + * to the Kernel code and still unknown to the
>> + * tests.
>> + */
>> + fprintf(stdout,
>> + "SKIP Unknown MAGIC: 0x%X - Is KSFT arm64/signal up to date ?\n",
>> + head->magic);
>> + break;
>> + }
>> +
>> + if (*err)
>> + return false;
>> +
>> + offs += head->size;
>> + if (resv_sz - offs < sizeof(*head)) {
>> + *err = "HEAD Overrun";
>> + return false;
>> + }
>> +
>> + if (flags & EXTRA_CTX)
>> + if (!validate_extra_context(extra, err))
>> + return false;
>> +
>> + head = GET_RESV_NEXT_HEAD(head);
>> + }
>> +
>> + if (terminated && !(flags & FPSIMD_CTX)) {
>> + *err = "Missing FPSIMD";
>> + return false;
>> + }
>> +
>> + return true;
>> +}
>> diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.h b/tools/testing/selftests/arm64/signal/testcases/testcases.h
>> new file mode 100644
>> index 000000000000..624717c71b1d
>> --- /dev/null
>> +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.h
>> @@ -0,0 +1,83 @@
>> +#ifndef __TESTCASES_H__
>> +#define __TESTCASES_H__
>> +
>> +#include <stdio.h>
>> +#include <stdbool.h>
>> +#include <stdint.h>
>> +#include <unistd.h>
>> +#include <ucontext.h>
>> +#include <assert.h>
>> +
>> +/* Architecture specific sigframe definitions */
>> +#include <asm/sigcontext.h>
>> +
>> +#define FPSIMD_CTX (1 << 0)
>> +#define SVE_CTX (1 << 1)
>> +#define EXTRA_CTX (1 << 2)
>> +
>> +#define KSFT_BAD_MAGIC 0xdeadbeef
>> +
>> +#define HDR_SZ \
>> + sizeof(struct _aarch64_ctx)
>> +
>> +#define GET_SF_RESV_HEAD(sf) \
>> + (struct _aarch64_ctx *)(&(sf).uc.uc_mcontext.__reserved)
>> +
>> +#define GET_SF_RESV_SIZE(sf) \
>> + sizeof((sf).uc.uc_mcontext.__reserved)
>> +
>> +#define GET_UCP_RESV_SIZE(ucp) \
>> + sizeof((ucp)->uc_mcontext.__reserved)
>> +
>> +#define ASSERT_BAD_CONTEXT(uc) do { \
>> + char *err = NULL; \
>> + assert(!validate_reserved((uc), GET_UCP_RESV_SIZE((uc)), &err));\
>> + if (err) \
>> + fprintf(stderr, \
>> + "Using badly built context - ERR: %s\n", err); \
>> +} while(0)
>> +
>> +#define ASSERT_GOOD_CONTEXT(uc) do { \
>> + char *err = NULL; \
>> + if (!validate_reserved((uc), GET_UCP_RESV_SIZE((uc)), &err)) { \
>> + if (err) \
>> + fprintf(stderr, \
>> + "Detected BAD context - ERR: %s\n", err);\
>> + assert(0); \
>> + } else { \
>> + fprintf(stderr, "uc context validated.\n"); \
>> + } \
>> +} while(0)
>> +
>> +/* head->size accounts both for payload and header _aarch64_ctx size ! */
>> +#define GET_RESV_NEXT_HEAD(h) \
>> + (struct _aarch64_ctx *)((char *)(h) + (h)->size)
>> +
>> +struct fake_sigframe {
>> + siginfo_t info;
>> + ucontext_t uc;
>> +};
>> +
>> +
>> +bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err);
>> +
>> +bool validate_extra_context(struct extra_context *extra, char **err);
>> +
>> +struct _aarch64_ctx *get_header(struct _aarch64_ctx *head, uint32_t magic,
>> + size_t resv_sz, size_t *offset);
>> +
>> +static inline struct _aarch64_ctx *get_terminator(struct _aarch64_ctx *head,
>> + size_t resv_sz,
>> + size_t *offset)
>> +{
>> + return get_header(head, 0, resv_sz, offset);
>> +}
>> +
>> +static inline void write_terminator_record(struct _aarch64_ctx *tail)
>> +{
>> + if (tail) {
>> + tail->magic = 0;
>> + tail->size = 0;
>> + }
>> +}
>> +#endif
>>
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* Re: [PATCH 2/2] net: gmii2rgmii: Switch priv field in mdio device structure
From: Andrew Lunn @ 2019-08-13 13:23 UTC (permalink / raw)
To: Harini Katakam
Cc: Florian Fainelli, netdev, radhey.shyam.pandey, Michal Simek,
linux-kernel, Harini Katakam, David Miller, linux-arm-kernel,
Heiner Kallweit
In-Reply-To: <CAFcVEC+DyVhLzbMdSDsadivbnZJxSEg-0kUF5_Q+mtSbBnmhSA@mail.gmail.com>
On Tue, Aug 13, 2019 at 04:46:40PM +0530, Harini Katakam wrote:
> Hi Andrew,
>
> On Thu, Aug 1, 2019 at 9:36 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > On Wed, Jul 31, 2019 at 03:06:19PM +0530, Harini Katakam wrote:
> > > Use the priv field in mdio device structure instead of the one in
> > > phy device structure. The phy device priv field may be used by the
> > > external phy driver and should not be overwritten.
> >
> > Hi Harini
> >
> > I _think_ you could use dev_set_drvdata(&mdiodev->dev) in xgmiitorgmii_probe() and
> > dev_get_drvdata(&phydev->mdiomdio.dev) in _read_status()
>
> Thanks for the review. This works if I do:
> dev_set_drvdata(&priv->phy_dev->mdio.dev->dev) in probe
> and then
> dev_get_drvdata(&phydev->mdio.dev) in _read_status()
>
> i.e mdiodev in gmii2rgmii probe and priv->phy_dev->mdio are not the same.
>
> If this is acceptable, I can send a v2.
Hi Harini
I think this is better, making use of the central driver
infrastructure, rather than inventing something new.
The kernel does have a few helper, spi_get_drvdata, pci_get_drvdata,
hci_get_drvdata. So maybe had add phydev_get_drvdata(struct phy_device
*phydev)?
Thanks
Andrew
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* Re: [PATCH v3 4/4] perf: Use CAP_SYS_ADMIN instead of euid==0 with ftrace
From: Arnaldo Carvalho de Melo @ 2019-08-13 13:23 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Suzuki K Poulose, Peter Zijlstra, Alexey Budankov, Igor Lubashev,
Arnaldo Carvalho de Melo, Linux Kernel Mailing List,
Alexander Shishkin, Ingo Molnar, Namhyung Kim, James Morris,
Jiri Olsa, linux-arm-kernel
In-Reply-To: <CANLsYkwjdhzVMwrWboTTOw+P3NajtoswxfxhodK0DdeexFCR3w@mail.gmail.com>
Em Mon, Aug 12, 2019 at 03:42:17PM -0600, Mathieu Poirier escreveu:
> On Mon, 12 Aug 2019 at 14:29, Arnaldo Carvalho de Melo
> <arnaldo.melo@gmail.com> wrote:
> >
> > Em Mon, Aug 12, 2019 at 05:27:06PM -0300, Arnaldo Carvalho de Melo escreveu:
> > > Em Mon, Aug 12, 2019 at 05:22:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> > > > Em Wed, Aug 07, 2019 at 10:44:17AM -0400, Igor Lubashev escreveu:
> > > > > @@ -281,7 +283,7 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> > > > > .events = POLLIN,
> > > > > };
> > > > >
> > > > > - if (geteuid() != 0) {
> > > > > + if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> > > > > pr_err("ftrace only works for root!\n");
> > > >
> > > > I guess we should update the error message too?
> > > >
> > >
> > > I.e. I applied this as a follow up patch:
> > >
> > > diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c
> > > index 01a5bb58eb04..ba8b65c2f9dc 100644
> > > --- a/tools/perf/builtin-ftrace.c
> > > +++ b/tools/perf/builtin-ftrace.c
> > > @@ -284,7 +284,12 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace, int argc, const char **argv)
> > > };
> > >
> > > if (!perf_cap__capable(CAP_SYS_ADMIN)) {
> > > - pr_err("ftrace only works for root!\n");
> > > + pr_err("ftrace only works for %s!\n",
> > > +#ifdef HAVE_LIBCAP_SUPPORT
> > > + "users with the SYS_ADMIN capability"
> > > +#else
> > > + "root"
> > > +#endif
> >
> > );
> >
> > :-)
> >
> > > return -1;
> > > }
> > >
> >
> > I've pushed the whole set to my tmp.perf/cap branch, please chec
>
> Please hold on before moving further - I'm getting a segmentation
> fault on ARM64 that I'm still trying to figure out.
This is just sitting in my tmp branch, and in my local perf/core branch,
so that I can test it with the containers, etc.
Is this related to the following fix?
commit 3e70008a6021fffd2cd1614734603ea970773060
Author: Leo Yan <leo.yan@linaro.org>
Date: Fri Aug 9 18:47:52 2019 +0800
perf trace: Fix segmentation fault when access syscall info on arm64
'perf trace' reports the segmentation fault as below on Arm64:
# perf trace -e string -e augmented_raw_syscalls.c
LLVM: dumping tools/perf/examples/bpf/augmented_raw_syscalls.o
perf: Segmentation fault
Obtained 12 stack frames.
perf(sighandler_dump_stack+0x47) [0xaaaaac96ac87]
linux-vdso.so.1(+0x5b7) [0xffffadbeb5b7]
/lib/aarch64-linux-gnu/libc.so.6(strlen+0x10) [0xfffface7d5d0]
/lib/aarch64-linux-gnu/libc.so.6(_IO_vfprintf+0x1ac7) [0xfffface49f97]
/lib/aarch64-linux-gnu/libc.so.6(__vsnprintf_chk+0xc7) [0xffffacedfbe7]
perf(scnprintf+0x97) [0xaaaaac9ca3ff]
perf(+0x997bb) [0xaaaaac8e37bb]
perf(cmd_trace+0x28e7) [0xaaaaac8ec09f]
perf(+0xd4a13) [0xaaaaac91ea13]
perf(main+0x62f) [0xaaaaac8a147f]
/lib/aarch64-linux-gnu/libc.so.6(__libc_start_main+0xe3) [0xfffface22d23]
perf(+0x57723) [0xaaaaac8a1723]
Segmentation fault
This issue is introduced by commit 30a910d7d3e0 ("perf trace:
Preallocate the syscall table"), it allocates trace->syscalls.table[]
array and the element count is 'trace->sctbl->syscalls.nr_entries'; but
on Arm64, the system call number is not continuously used; e.g. the
syscall maximum id is 436 but the real entries is only 281.
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* [PATCH v2] clocksource/drivers/tcb_clksrc: register delay timer
From: Alexandre Belloni @ 2019-08-13 13:30 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Alexandre Belloni, Alexander Dahl, Sebastian Andrzej Siewior,
linux-kernel, Thomas Gleixner, linux-arm-kernel
Implement and register delay timer to allow get_cycles() to work properly.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
Change in v2:
- depend on ARM to prevent build issue
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-atmel-tcb.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5e9317dc3d39..a642c23b2fba 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -429,7 +429,7 @@ config ATMEL_ST
config ATMEL_TCB_CLKSRC
bool "Atmel TC Block timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
+ depends on ARM && HAS_IOMEM
select TIMER_OF if OF
help
Support for Timer Counter Blocks on Atmel SoCs.
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 6ed31f9def7e..7427b07495a8 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -6,6 +6,7 @@
#include <linux/irq.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
@@ -125,6 +126,18 @@ static u64 notrace tc_sched_clock_read32(void)
return tc_get_cycles32(&clksrc);
}
+static struct delay_timer tc_delay_timer;
+
+static unsigned long tc_delay_timer_read(void)
+{
+ return tc_get_cycles(&clksrc);
+}
+
+static unsigned long notrace tc_delay_timer_read32(void)
+{
+ return tc_get_cycles32(&clksrc);
+}
+
#ifdef CONFIG_GENERIC_CLOCKEVENTS
struct tc_clkevt_device {
@@ -432,6 +445,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup ony channel 0 */
tcb_setup_single_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read32;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read32;
} else {
/* we have three clocks no matter what the
* underlying platform supports.
@@ -444,6 +458,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read;
}
/* and away we go! */
@@ -458,6 +473,9 @@ static int __init tcb_clksrc_init(struct device_node *node)
sched_clock_register(tc_sched_clock, 32, divided_rate);
+ tc_delay_timer.freq = divided_rate;
+ register_current_timer_delay(&tc_delay_timer);
+
return 0;
err_unregister_clksrc:
--
2.21.0
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* [v4, 4/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
This adds dt-binding documentation of cci devfreq
for Mediatek MT8183 SoC platform.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
.../bindings/devfreq/mt8183-cci-devfreq.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt
diff --git a/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt b/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt
new file mode 100644
index 000000000000..a65a70bb9f09
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt
@@ -0,0 +1,20 @@
+* Mediatek Cache Coherent Interconnect(CCI) frequency device
+
+Required properties:
+- compatible: should contain "mediatek,mt8183-cci" for frequency scaling of CCI
+- clocks: for frequency scaling of CCI
+- clock-names: for frequency scaling of CCI driver to reference
+- regulator: for voltage scaling of CCI
+- operating-points-v2: for frequency scaling of CCI opp table
+
+Example:
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ &cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
\ No newline at end of file
--
2.12.5
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* [v4, 1/8] cpufreq: mediatek: change to regulator_get_optional
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
For new mediatek chip mt8183,
cci and little cluster share the same buck,
so need to modify the attribute of regulator from exclusive to optional
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index f14f3a85f2f7..a370577ffc73 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -338,7 +338,7 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
goto out_free_resources;
}
- proc_reg = regulator_get_exclusive(cpu_dev, "proc");
+ proc_reg = regulator_get_optional(cpu_dev, "proc");
if (IS_ERR(proc_reg)) {
if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
pr_warn("proc regulator for cpu%d not ready, retry.\n",
--
2.12.5
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* [v4, 5/8] devfreq: add mediatek cci devfreq
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
This adds a devfreq driver for the Cache Coherent Interconnect (CCI)
of the Mediatek MT8183.
On the MT8183 the CCI is supplied by the same regulator as the LITTLE
cores. The driver is notified when the regulator voltage changes
(driven by cpufreq) and adjusts the CCI frequency to the maximum
possible value.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/devfreq/Kconfig | 10 ++
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mt8183-cci-devfreq.c | 247 +++++++++++++++++++++++++++++++++++
3 files changed, 258 insertions(+)
create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index ba98a4e3ad33..0c8204d6b78a 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -92,6 +92,16 @@ config ARM_EXYNOS_BUS_DEVFREQ
and adjusts the operating frequencies and voltages with OPP support.
This does not yet operate with optimal voltages.
+config ARM_MT8183_CCI_DEVFREQ
+ tristate "MT8183 CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ
+ help
+ This adds a devfreq driver for Cache Coherent Interconnect
+ of Mediatek MT8183, which is shared the same regulator
+ with cpu cluster.
+ It can track buck voltage and update a proper cci frequency.
+ Use notification to get regulator status.
+
config ARM_TEGRA_DEVFREQ
tristate "Tegra DEVFREQ Driver"
depends on ARCH_TEGRA_124_SOC
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 32b8d4d3f12c..817dde779f16 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
+obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
new file mode 100644
index 000000000000..818a167c442f
--- /dev/null
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+
+ * Author: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+
+#include "governor.h"
+
+struct cci_devfreq {
+ struct devfreq *devfreq;
+ struct regulator *proc_reg;
+ unsigned long proc_reg_uV;
+ struct clk *cci_clk;
+ struct notifier_block nb;
+};
+
+static int cci_devfreq_regulator_notifier(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ int ret;
+ struct cci_devfreq *cci_df =
+ container_of(nb, struct cci_devfreq, nb);
+
+ /* deal with reduce frequency */
+ if (val & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
+ struct pre_voltage_change_data *pvc_data = data;
+
+ if (pvc_data->min_uV < pvc_data->old_uV) {
+ cci_df->proc_reg_uV =
+ (unsigned long)(pvc_data->min_uV);
+ mutex_lock(&cci_df->devfreq->lock);
+ ret = update_devfreq(cci_df->devfreq);
+ if (ret)
+ pr_err("Fail to reduce cci frequency: %d\n",
+ ret);
+ mutex_unlock(&cci_df->devfreq->lock);
+ }
+ } else if ((val & REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE) &&
+ ((unsigned long)data > cci_df->proc_reg_uV)) {
+ cci_df->proc_reg_uV = (unsigned long)data;
+ mutex_lock(&cci_df->devfreq->lock);
+ ret = update_devfreq(cci_df->devfreq);
+ if (ret)
+ pr_err("Fail to raise cci frequency back: %d\n", ret);
+ mutex_unlock(&cci_df->devfreq->lock);
+ } else if ((val & REGULATOR_EVENT_VOLTAGE_CHANGE) &&
+ (cci_df->proc_reg_uV < (unsigned long)data)) {
+ /* deal with increase frequency */
+ cci_df->proc_reg_uV = (unsigned long)data;
+ mutex_lock(&cci_df->devfreq->lock);
+ ret = update_devfreq(cci_df->devfreq);
+ if (ret)
+ pr_err("Fail to raise cci frequency: %d\n", ret);
+ mutex_unlock(&cci_df->devfreq->lock);
+ }
+
+ return 0;
+}
+
+static int mtk_cci_governor_get_target(struct devfreq *devfreq,
+ unsigned long *freq)
+{
+ struct cci_devfreq *cci_df;
+ struct dev_pm_opp *opp;
+
+ cci_df = dev_get_drvdata(devfreq->dev.parent);
+
+ /* find available frequency */
+ opp = dev_pm_opp_find_freq_ceil_by_volt(devfreq->dev.parent,
+ cci_df->proc_reg_uV);
+ *freq = dev_pm_opp_get_freq(opp);
+
+ return 0;
+}
+
+static int mtk_cci_governor_event_handler(struct devfreq *devfreq,
+ unsigned int event, void *data)
+{
+ int ret;
+ struct cci_devfreq *cci_df;
+ struct notifier_block *nb;
+
+ cci_df = dev_get_drvdata(devfreq->dev.parent);
+ nb = &cci_df->nb;
+
+ switch (event) {
+ case DEVFREQ_GOV_START:
+ case DEVFREQ_GOV_RESUME:
+ nb->notifier_call = cci_devfreq_regulator_notifier;
+ ret = regulator_register_notifier(cci_df->proc_reg,
+ nb);
+ if (ret)
+ pr_err("%s: failed to add governor: %d\n", __func__,
+ ret);
+ break;
+
+ case DEVFREQ_GOV_STOP:
+ case DEVFREQ_GOV_SUSPEND:
+ ret = regulator_unregister_notifier(cci_df->proc_reg,
+ nb);
+ if (ret)
+ pr_err("%s: failed to add governor: %d\n", __func__,
+ ret);
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static struct devfreq_governor mtk_cci_devfreq_governor = {
+ .name = "mtk_cci_vmon",
+ .get_target_freq = mtk_cci_governor_get_target,
+ .event_handler = mtk_cci_governor_event_handler,
+ .immutable = true
+};
+
+static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ int ret;
+ struct cci_devfreq *cci_df = dev_get_drvdata(dev);
+
+ if (!cci_df)
+ return -EINVAL;
+
+ ret = clk_set_rate(cci_df->cci_clk, *freq);
+ if (ret) {
+ pr_err("%s: failed cci to set rate: %d\n", __func__,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct devfreq_dev_profile cci_devfreq_profile = {
+ .target = mtk_cci_devfreq_target,
+};
+
+static int mtk_cci_devfreq_probe(struct platform_device *pdev)
+{
+ struct device *cci_dev = &pdev->dev;
+ struct cci_devfreq *cci_df;
+ int ret;
+
+ cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
+ if (!cci_df)
+ return -ENOMEM;
+
+ cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock");
+ ret = PTR_ERR_OR_ZERO(cci_df->cci_clk);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get clock for CCI: %d\n",
+ ret);
+ return ret;
+ }
+ cci_df->proc_reg = devm_regulator_get_optional(cci_dev, "proc");
+ ret = PTR_ERR_OR_ZERO(cci_df->proc_reg);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = dev_pm_opp_of_add_table(cci_dev);
+ if (ret) {
+ dev_err(cci_dev, "Fail to init CCI OPP table: %d\n", ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, cci_df);
+
+ cci_df->devfreq = devm_devfreq_add_device(cci_dev,
+ &cci_devfreq_profile,
+ "mtk_cci_vmon",
+ NULL);
+ if (IS_ERR(cci_df->devfreq)) {
+ ret = PTR_ERR(cci_df->devfreq);
+ dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret);
+ dev_pm_opp_of_remove_table(cci_dev);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const __maybe_unused struct of_device_id
+ mediatek_cci_devfreq_of_match[] = {
+ { .compatible = "mediatek,mt8183-cci" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mediatek_cci_devfreq_of_match);
+
+static struct platform_driver cci_devfreq_driver = {
+ .probe = mtk_cci_devfreq_probe,
+ .driver = {
+ .name = "mediatek-cci-devfreq",
+ .of_match_table = of_match_ptr(mediatek_cci_devfreq_of_match),
+ },
+};
+
+static int __init mtk_cci_devfreq_init(void)
+{
+ int ret;
+
+ ret = devfreq_add_governor(&mtk_cci_devfreq_governor);
+ if (ret) {
+ pr_err("%s: failed to add governor: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = platform_driver_register(&cci_devfreq_driver);
+ if (ret)
+ devfreq_remove_governor(&mtk_cci_devfreq_governor);
+
+ return ret;
+}
+module_init(mtk_cci_devfreq_init)
+
+static void __exit mtk_cci_devfreq_exit(void)
+{
+ int ret;
+
+ ret = devfreq_remove_governor(&mtk_cci_devfreq_governor);
+ if (ret)
+ pr_err("%s: failed to remove governor: %d\n", __func__, ret);
+
+ platform_driver_unregister(&cci_devfreq_driver);
+}
+module_exit(mtk_cci_devfreq_exit)
+
+MODULE_DESCRIPTION("Mediatek CCI devfreq driver");
+MODULE_AUTHOR("Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.12.5
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^ permalink raw reply related
* [v4, 0/8] Add cpufreq and cci devfreq for mt8183, and SVS support
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
MT8183 supports CPU DVFS and CCI DVFS, and LITTLE cpus and CCI are in the same voltage domain.
So, this series is to add drivers to handle the voltage coupling between CPU and CCI DVFS.
For SVS support, add OPP_EVENT_ADJUST_VOLTAGE and corresponding reaction.
Change since v3:
- modify example of dt-binding
- change rcu implementation in Support adjusting OPP patch
- Add mutex init in cpufreq driver
Andrew-sh.Cheng (7):
cpufreq: mediatek: change to regulator_get_optional
cpufreq: mediatek: add clock enable for intermediate clock
cpufreq: mediatek: Add support for mt8183
dt-bindings: devfreq: add compatible for mt8183 cci devfreq
devfreq: add mediatek cci devfreq
cpufreq: mediatek: add opp notification for SVS support
devfreq: mediatek: cci devfreq register opp notification for SVS
support
Stephen Boyd (1):
PM / OPP: Support adjusting OPP voltages at runtime
.../bindings/devfreq/mt8183-cci-devfreq.txt | 20 ++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/mediatek-cpufreq.c | 94 ++++++-
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mt8183-cci-devfreq.c | 309 +++++++++++++++++++++
drivers/opp/core.c | 63 +++++
include/linux/pm_opp.h | 11 +
8 files changed, 507 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci-devfreq.txt
create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c
--
2.12.5
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^ permalink raw reply
* [v4, 6/8] PM / OPP: Support adjusting OPP voltages at runtime
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, srv_heupstream, linux-pm, Roger Lu, Stephen Boyd,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: Stephen Boyd <sboyd@codeaurora.org>
On some SoCs the Adaptive Voltage Scaling (AVS) technique is
employed to optimize the operating voltage of a device. At a
given frequency, the hardware monitors dynamic factors and either
makes a suggestion for how much to adjust a voltage for the
current frequency, or it automatically adjusts the voltage
without software intervention. Add an API to the OPP library for
the former case, so that AVS type devices can update the voltages
for an OPP when the hardware determines the voltage should
change. The assumption is that drivers like CPUfreq or devfreq
will register for the OPP notifiers and adjust the voltage
according to suggestions that AVS makes.
This patch is devired from [1] submitted by Stephen.
[1] https://lore.kernel.org/patchwork/patch/599279/
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
---
drivers/opp/core.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/pm_opp.h | 11 +++++++++
2 files changed, 74 insertions(+)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index c094d5d20fd7..407a07f29b12 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -2054,6 +2054,69 @@ static int _opp_set_availability(struct device *dev, unsigned long freq,
}
/**
+ * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP
+ * @dev: device for which we do this operation
+ * @freq: OPP frequency to adjust voltage of
+ * @u_volt: new OPP voltage
+ *
+ * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the
+ * copy operation, returns 0 if no modifcation was done OR modification was
+ * successful.
+ */
+int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
+ unsigned long u_volt)
+{
+ struct opp_table *opp_table;
+ struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV);
+ int r = 0;
+
+ /* Find the opp_table */
+ opp_table = _find_opp_table(dev);
+ if (IS_ERR(opp_table)) {
+ r = PTR_ERR(opp_table);
+ dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r);
+ return r;
+ }
+
+ mutex_lock(&opp_table->lock);
+
+ /* Do we have the frequency? */
+ list_for_each_entry(tmp_opp, &opp_table->opp_list, node) {
+ if (tmp_opp->rate == freq) {
+ opp = tmp_opp;
+ break;
+ }
+ }
+
+ if (IS_ERR(opp)) {
+ r = PTR_ERR(opp);
+ goto adjust_unlock;
+ }
+
+ /* Is update really needed? */
+ if (opp->supplies->u_volt == u_volt)
+ goto adjust_unlock;
+
+ opp->supplies->u_volt = u_volt;
+
+ dev_pm_opp_get(opp);
+ mutex_unlock(&opp_table->lock);
+
+ /* Notify the voltage change of the OPP */
+ blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE,
+ opp);
+
+ dev_pm_opp_put(opp);
+ goto adjust_put_table;
+
+adjust_unlock:
+ mutex_unlock(&opp_table->lock);
+adjust_put_table:
+ dev_pm_opp_put_opp_table(opp_table);
+ return r;
+}
+
+/**
* dev_pm_opp_enable() - Enable a specific OPP
* @dev: device for which we do this operation
* @freq: OPP frequency to enable
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index af5021f27cb7..86947d53e8c4 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -22,6 +22,7 @@ struct opp_table;
enum dev_pm_opp_event {
OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE,
+ OPP_EVENT_ADJUST_VOLTAGE,
};
/**
@@ -111,6 +112,9 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq,
void dev_pm_opp_remove(struct device *dev, unsigned long freq);
void dev_pm_opp_remove_all_dynamic(struct device *dev);
+int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
+ unsigned long u_volt);
+
int dev_pm_opp_enable(struct device *dev, unsigned long freq);
int dev_pm_opp_disable(struct device *dev, unsigned long freq);
@@ -234,6 +238,13 @@ static inline void dev_pm_opp_remove_all_dynamic(struct device *dev)
{
}
+static inline int
+dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
+ unsigned long u_volt)
+{
+ return 0;
+}
+
static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq)
{
return 0;
--
2.12.5
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^ permalink raw reply related
* [v4, 2/8] cpufreq: mediatek: add clock enable for intermediate clock
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
Intermediate clock is not always enabled by ccf in different projects,
so cpufreq should always enable it by itself.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index a370577ffc73..acd9539e95de 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
goto out_free_resources;
}
+ ret = clk_prepare_enable(inter_clk);
+ if (ret)
+ goto out_free_opp_table;
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
if (IS_ERR(opp)) {
pr_err("failed to get intermediate opp for cpu%d\n", cpu);
ret = PTR_ERR(opp);
- goto out_free_opp_table;
+ goto out_disable_clock;
}
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
@@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
return 0;
+out_disable_clock:
+ clk_disable_unprepare(inter_clk);
+
out_free_opp_table:
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
@@ -419,6 +426,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
clk_put(info->cpu_clk);
if (!IS_ERR(info->inter_clk))
clk_put(info->inter_clk);
+ if (!IS_ERR(info->inter_clk)) {
+ clk_disable_unprepare(info->inter_clk);
+ clk_put(info->inter_clk);
+ }
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
}
--
2.12.5
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^ permalink raw reply related
* [v4, 3/8] cpufreq: mediatek: Add support for mt8183
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
Add compatible string for mediatek mt8183
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/mediatek-cpufreq.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 03dc4244ab00..0f7e837a264e 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -117,6 +117,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "mediatek,mt817x", },
{ .compatible = "mediatek,mt8173", },
{ .compatible = "mediatek,mt8176", },
+ { .compatible = "mediatek,mt8183", },
{ .compatible = "nvidia,tegra124", },
{ .compatible = "nvidia,tegra210", },
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index acd9539e95de..4dce41b18369 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -546,6 +546,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt817x", },
{ .compatible = "mediatek,mt8173", },
{ .compatible = "mediatek,mt8176", },
+ { .compatible = "mediatek,mt8183", },
{ }
};
--
2.12.5
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* [v4, 7/8] cpufreq: mediatek: add opp notification for SVS support
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
cpufreq should listen opp notification and do proper actions
when receiving disable and voltage adjustment events,
which are triggered when SVS is enabled.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 78 ++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 4dce41b18369..9820c8003507 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -42,6 +42,10 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ struct mutex lock; /* avoid notify and policy race condition */
+ struct notifier_block opp_nb;
+ int opp_cpu;
+ unsigned long opp_freq;
};
static LIST_HEAD(dvfs_info_list);
@@ -231,6 +235,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_lock(&info->lock);
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -242,6 +247,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pr_err("cpu%d: failed to scale up voltage!\n",
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
}
@@ -253,6 +259,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, old_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -263,6 +270,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, old_vproc);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -273,6 +281,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
WARN_ON(1);
+ mutex_unlock(&info->lock);
return ret;
}
@@ -288,15 +297,74 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, old_freq_hz);
clk_set_parent(cpu_clk, armpll);
+ mutex_unlock(&info->lock);
return ret;
}
}
+ info->opp_freq = freq_hz;
+ mutex_unlock(&info->lock);
+
return 0;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *opp_item;
+ struct mtk_cpu_dvfs_info *info =
+ container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev, "failed to scale voltage: %d\n",
+ ret);
+ }
+ mutex_unlock(&info->lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = info->opp_freq;
+ opp_item = dev_pm_opp_find_freq_ceil(info->cpu_dev, &freq);
+ if (!IS_ERR(opp_item))
+ dev_pm_opp_put(opp_item);
+ else
+ freq = 0;
+
+ /* case of current opp is disabled */
+ if (freq == 0 || freq != info->opp_freq) {
+ // find an enable opp item
+ freq = 1;
+ opp_item = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (!IS_ERR(opp_item)) {
+ dev_pm_opp_put(opp_item);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy,
+ freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ } else
+ pr_err("%s: all opp items are disabled\n",
+ __func__);
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -383,11 +451,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ pr_warn("cannot register opp notification\n");
+ goto out_free_opp_table;
+ }
+
+ mutex_init(&info->lock);
info->cpu_dev = cpu_dev;
info->proc_reg = proc_reg;
info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
info->cpu_clk = cpu_clk;
info->inter_clk = inter_clk;
+ info->opp_freq = clk_get_rate(cpu_clk);
/*
* If SRAM regulator is present, software "voltage tracking" is needed
--
2.12.5
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^ permalink raw reply related
* [v4, 8/8] devfreq: mediatek: cci devfreq register opp notification for SVS support
From: Andrew-sh.Cheng @ 2019-08-13 13:31 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, Andrew-sh.Cheng, srv_heupstream, linux-pm,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-1-git-send-email-andrew-sh.cheng@mediatek.com>
From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
SVS will change the voltage of opp item.
CCI devfreq need to react to change frequency.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
---
drivers/devfreq/mt8183-cci-devfreq.c | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c
index 818a167c442f..bc5c75d55c03 100644
--- a/drivers/devfreq/mt8183-cci-devfreq.c
+++ b/drivers/devfreq/mt8183-cci-devfreq.c
@@ -19,7 +19,10 @@ struct cci_devfreq {
struct regulator *proc_reg;
unsigned long proc_reg_uV;
struct clk *cci_clk;
+ unsigned long freq;
struct notifier_block nb;
+ struct notifier_block opp_nb;
+ int cci_min_freq;
};
static int cci_devfreq_regulator_notifier(struct notifier_block *nb,
@@ -65,17 +68,61 @@ static int cci_devfreq_regulator_notifier(struct notifier_block *nb,
return 0;
}
+static int ccidevfreq_opp_notifier(struct notifier_block *nb,
+unsigned long event, void *data)
+{
+ int ret;
+ struct dev_pm_opp *opp = data;
+ struct cci_devfreq *cci_df = container_of(nb, struct cci_devfreq,
+ opp_nb);
+ unsigned long freq, volt, cur_volt;
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+ /* current opp item is changed */
+ if (freq == cci_df->freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ cur_volt = regulator_get_voltage(cci_df->proc_reg);
+
+ if (volt > cur_volt) {
+ /* need reduce freq */
+ mutex_lock(&cci_df->devfreq->lock);
+ ret = update_devfreq(cci_df->devfreq);
+ if (ret)
+ pr_err("Fail to reduce cci frequency by opp notification: %d\n",
+ ret);
+ mutex_unlock(&cci_df->devfreq->lock);
+ }
+ }
+
+ if (freq == cci_df->cci_min_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ regulator_set_voltage(cci_df->proc_reg, volt, INT_MAX);
+ }
+ }
+
+ return 0;
+}
+
+
static int mtk_cci_governor_get_target(struct devfreq *devfreq,
unsigned long *freq)
{
struct cci_devfreq *cci_df;
struct dev_pm_opp *opp;
+ int ret;
cci_df = dev_get_drvdata(devfreq->dev.parent);
/* find available frequency */
opp = dev_pm_opp_find_freq_ceil_by_volt(devfreq->dev.parent,
cci_df->proc_reg_uV);
+ ret = PTR_ERR_OR_ZERO(opp);
+ if (ret) {
+ pr_err("%s[%d], cannot find opp with voltage=%d: %d\n",
+ __func__, __LINE__, cci_df->proc_reg_uV, ret);
+ return ret;
+ }
*freq = dev_pm_opp_get_freq(opp);
return 0;
@@ -87,9 +134,11 @@ static int mtk_cci_governor_event_handler(struct devfreq *devfreq,
int ret;
struct cci_devfreq *cci_df;
struct notifier_block *nb;
+ struct notifier_block *opp_nb;
cci_df = dev_get_drvdata(devfreq->dev.parent);
nb = &cci_df->nb;
+ opp_nb = &cci_df->opp_nb;
switch (event) {
case DEVFREQ_GOV_START:
@@ -100,6 +149,8 @@ static int mtk_cci_governor_event_handler(struct devfreq *devfreq,
if (ret)
pr_err("%s: failed to add governor: %d\n", __func__,
ret);
+ opp_nb->notifier_call = ccidevfreq_opp_notifier;
+ dev_pm_opp_register_notifier(devfreq->dev.parent, opp_nb);
break;
case DEVFREQ_GOV_STOP:
@@ -141,6 +192,8 @@ static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq,
return ret;
}
+ cci_df->freq = *freq;
+
return 0;
}
@@ -152,6 +205,8 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
{
struct device *cci_dev = &pdev->dev;
struct cci_devfreq *cci_df;
+ unsigned long freq, volt;
+ struct dev_pm_opp *opp;
int ret;
cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL);
@@ -181,6 +236,13 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev)
return ret;
}
+ /* set voltage lower bound */
+ freq = 1;
+ opp = dev_pm_opp_find_freq_ceil(cci_dev, &freq);
+ cci_df->cci_min_freq = dev_pm_opp_get_freq(opp);
+ volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
platform_set_drvdata(pdev, cci_df);
cci_df->devfreq = devm_devfreq_add_device(cci_dev,
--
2.12.5
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^ permalink raw reply related
* Re: [PATCH V5 00/12] 52-bit kernel + user VAs
From: Geert Uytterhoeven @ 2019-08-13 13:36 UTC (permalink / raw)
To: Will Deacon
Cc: crecklin, Ard Biesheuvel, Catalin Marinas, bhsharma, Steve Capper,
Linux-Renesas, maz, Linux ARM
In-Reply-To: <20190813131013.vpc5a2vlxwghizxa@willie-the-truck>
[-- Attachment #1: Type: text/plain, Size: 3129 bytes --]
Hi Will,
On Tue, Aug 13, 2019 at 3:10 PM Will Deacon <will@kernel.org> wrote:
> On Tue, Aug 13, 2019 at 02:43:23PM +0200, Geert Uytterhoeven wrote:
> > On Fri, Aug 9, 2019 at 6:47 PM Will Deacon <will@kernel.org> wrote:
> > > On Wed, Aug 07, 2019 at 04:55:12PM +0100, Steve Capper wrote:
> > > > This patch series adds support for 52-bit kernel VAs using some of the
> > > > machinery already introduced by the 52-bit userspace VA code in 5.0.
> > >
> > > Cheers, I've pushed this out on a for-next/52-bit-kva branch with one
> > > small patch on top and Catalin's tags added.
> >
> > As of commit 14c127c957c1c607 ("arm64: mm: Flip kernel VA space"), the
> > kernel log is spammed with
> >
> > virt_to_phys used for non-linear address: (____ptrval____)
> > (__func__.6603+0x14d681/0x17fb3d)
> > WARNING: CPU: 0 PID: 264 at arch/arm64/mm/physaddr.c:15
> > __virt_to_phys+0x28/0x58
> > Modules linked in:
> > CPU: 0 PID: 264 Comm: mdev Not tainted
> > 5.3.0-rc3-rcar3-initrd-00002-g14c127c957c1c607 #38
> > Hardware name: Renesas Ebisu-4D board based on r8a77990 (DT)
> > pstate: 60000005 (nZCv daif -PAN -UAO)
> > pc : __virt_to_phys+0x28/0x58
> > lr : __virt_to_phys+0x28/0x58
> > sp : ffffffc011953c80
> > x29: ffffffc011953c80 x28: ffffff8078790140
> > x27: 0000000000000000 x26: 0000000000000000
> > x25: ffffffc010a539b9 x24: ffffffc010a86000
> > x23: ffffffc010a539ba x22: 0000000000000001
> > x21: 0000000000202038 x20: 0000000000000001
> > x19: ffffffc010a539b9 x18: 000000000000000a
> > x17: 0000000000000000 x16: 0000000000000000
> > x15: 00000000000ca51d x14: 0720072007200720
> > x13: 0720072007200720 x12: 0720072007200720
> > x11: 0720072007200720 x10: 0720072007200720
> > x9 : 0720072007200720 x8 : 0000000000000001
> > x7 : 0000000000000007 x6 : ffffff8079824f00
> > x5 : 0000000000000140 x4 : 0000000000000000
> > x3 : 0000000000000000 x2 : 00000000ffffffff
> > x1 : 0713abbc9281cf00 x0 : 0000000000000000
> > Call trace:
> > __virt_to_phys+0x28/0x58
> > __check_object_size+0xd0/0x1e0
> > filldir64+0x1d8/0x2b0
> > kernfs_fop_readdir+0x64/0x200
> > iterate_dir+0x68/0x144
> > ksys_getdents64+0x88/0x154
> > __arm64_sys_getdents64+0x18/0x24
> > el0_svc_common.constprop.0+0x84/0xe8
> > el0_svc_compat_handler+0x18/0x20
> > el0_svc_compat+0x8/0x10
> > ---[ end trace 6980a45f636e18be ]---
> >
> > as soon as userspace starts.
>
> Can you try the hack I posted here, please?
>
> https://lkml.org/lkml/2019/8/13/555
Thanks, that seems to do the trick!
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Also, what .config are you using?
Attached.
Probably CONFIG_DEBUG_VIRTUAL=y is what you're missing.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[-- Attachment #2: ebisu-config.gz --]
[-- Type: application/gzip, Size: 27834 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: media: i2c: Add IMX290 CMOS sensor binding
From: Manivannan Sadhasivam @ 2019-08-13 13:52 UTC (permalink / raw)
To: Sakari Ailus
Cc: devicetree, c.barrett, linux-kernel, a.brela, robh+dt, mchehab,
linux-arm-kernel, linux-media
In-Reply-To: <20190813122212.GE2527@valkosipuli.retiisi.org.uk>
Hi Sakari,
On Tue, Aug 13, 2019 at 03:22:12PM +0300, Sakari Ailus wrote:
> Hi Manivannan,
>
> On Tue, Aug 13, 2019 at 05:44:00PM +0530, Manivannan Sadhasivam wrote:
> > Hi Sakari,
> >
> > On Tue, Aug 13, 2019 at 02:46:43PM +0300, Sakari Ailus wrote:
> > > Hi Manivannan,
> > >
> > > On Tue, Aug 13, 2019 at 05:03:58PM +0530, Manivannan Sadhasivam wrote:
> > > > Hi Sakari,
> > > >
> > > > Thanks for the review!
> > > >
> > > > On Tue, Aug 13, 2019 at 12:45:26PM +0300, Sakari Ailus wrote:
> > > > > Hi Manivannan,
> > > > >
> > > > > On Tue, Aug 06, 2019 at 06:39:36PM +0530, Manivannan Sadhasivam wrote:
> > > > > > Add devicetree binding for IMX290 CMOS image sensor.
> > > > > >
> > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > > .../devicetree/bindings/media/i2c/imx290.txt | 51 +++++++++++++++++++
> > > > > > 1 file changed, 51 insertions(+)
> > > > > > create mode 100644 Documentation/devicetree/bindings/media/i2c/imx290.txt
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/media/i2c/imx290.txt b/Documentation/devicetree/bindings/media/i2c/imx290.txt
> > > > > > new file mode 100644
> > > > > > index 000000000000..7535b5b5b24b
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/media/i2c/imx290.txt
> > > > > > @@ -0,0 +1,51 @@
> > > > > > +* Sony IMX290 1/2.8-Inch CMOS Image Sensor
> > > > > > +
> > > > > > +The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with
> > > > > > +Square Pixel for Color Cameras. It is programmable through I2C and 4-wire
> > > > > > +interfaces. The sensor output is available via CMOS logic parallel SDR output,
> > > > > > +Low voltage LVDS DDR output and CSI-2 serial data output.
> > > > >
> > > > > If there are three to choose from, then you should specify which one is in
> > > > > use. Given that I think chances remain slim we'd add support for the other
> > > > > two (it's certainly not ruled out though), CSI-2 could be the default. But
> > > > > this needs to be documented.
> > > > >
> > > >
> > > > Hmm... I'm not sure here. Bindings should describe the hardware and not the
> > > > limitations of the driver. Here as you said, the sensor can output frames
> > > > in 3 different modes/formats but the driver only supports CSI2. I can add a
> > > > note in the driver but not sure whether dt-binding is the right place or not!
> > >
> > > I guess alternatively you could document the necessary bindings for the
> > > other two busses.
> > >
> > > But what I'm saying here is that it's highly unlikely they'll be ever
> > > needed, and it'd be mostly a waste of time to implement that. (That said, I
> > > have nothing against the use of these busses, but I've never seen anyone
> > > using them.) Many other devices use defaults for more contentious settings.
> > >
> >
> > Agree with you but my question was, whether I could document the supported
> > mode in bindings or not! I have seen comments from Rob in the past that the
> > binding should not document the limitations of the driver. But anyway, one
> > can infer from the current binding that only CSI2 is supported for now, it's
> > just stating it explicitly makes me doubtful!
>
> I think it could be e.g.:
>
> The CSI-2 bus is the default. No bindings have been defined for the other
> busses.
>
Ack.
> ...
>
> > > > > I suppose you can't change the lane order, so clock-lanes is redundant
> > > > > (don't use it in the example) and data-lanes should be monotonically
> > > > > incrementing series from 1 to 4.
> > > > >
> > > >
> > > > We can change the order and the example here illustrates how it has been
> > > > wired in FRAMOS module. If I change the lane order like you said, it won't
> > > > work.
> > >
> > > I highly doubt that. Neither the driver nor the sensor uses the lane
> > > ordering information.
> > >
> >
> > Agree but CSI2 host will need this informtion, right? Please correct me if
> > I'm wrong!
>
> The CSI-2 receiver may need that configuration, but it's not addressed by a
> sensor's binding documentation (it's configured in the endpoint on the
> receiver's side).
>
Yes but I thought that documenting the sensor lane configuration based on one
example implementation might help interfacing w/ different hosts. Anyway, to be
host agnostic, I can drop the clock lane and make data lane start from 1 as you
suggested.
Thanks,
Mani
> --
> Sakari Ailus
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^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: irq: Convert Allwinner NMI Controller to a schema
From: Rob Herring @ 2019-08-13 13:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Jason Cooper, maz, Chen-Yu Tsai,
Thomas Gleixner, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190813054738.ge2jdu6qn2vaoasd@flea>
On Mon, Aug 12, 2019 at 11:47 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> Hi Rob,
>
> On Tue, Jul 23, 2019 at 10:32:41AM -0600, Rob Herring wrote:
> > On Tue, Jul 23, 2019 at 7:27 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > The Allwinner SoCs have an interrupt controller called NMI supported in
> > > Linux, with a matching Device Tree binding.
> > >
> > > Now that we have the DT validation in place, let's convert the device tree
> > > bindings for that controller over to a YAML schemas.
> > >
> > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > > ---
> > > .../allwinner,sun7i-a20-sc-nmi.yaml | 83 +++++++++++++++++++
> > > .../allwinner,sunxi-nmi.txt | 29 -------
> > > 2 files changed, 83 insertions(+), 29 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
> > > new file mode 100644
> > > index 000000000000..cb8077b0c8dd
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
> > > @@ -0,0 +1,83 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Chen-Yu Tsai <wens@csie.org>
> > > + - Maxime Ripard <maxime.ripard@bootlin.com>
> > > +
> > > +allOf:
> > > + - $ref: /schemas/interrupt-controller.yaml#
> > > +
> > > +select:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - allwinner,sun6i-a31-r-intc
> > > + - allwinner,sun7i-a20-sc-nmi
> > > + - allwinner,sun9i-a80-sc-nmi
> >
> > This should have all the possible compatibles in case all are not
> > listed.
>
> I'm sorry, but I'm not sure I understood what you meant here :/
You are missing these from the list:
allwinner,sun8i-a83t-r-intc
allwinner,sun50i-a64-r-intc
allwinner,sun50i-h6-r-intc
We need them all to catch any DTs with only the above strings.
>
> >
> > > +
> > > + # Deprecated
> > > + - allwinner,sun6i-a31-sc-nmi
> >
> > I know we already did things this way before, but perhaps this should
> > be listed below with the 'deprecated' property. The tools can include
> > it in select, but then remove it from compatible property.
>
> Can we have more than just one of the choice for an enum?
>
> In this particular case, since we have oneOf it's not really too much
> of an issue, but there's a significant amount of users of enum for the
> compatibles.
I think we have to use oneOf here. There's not that many cases of
deprecated compatibles.
Rob
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^ permalink raw reply
* Re: "arm64/for-next/core" causes boot panic
From: Steve Capper @ 2019-08-13 14:04 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, linux-kernel@vger.kernel.org, Qian Cai,
Andrey Konovalov, nd, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190813120643.25y5px4andu6cfwp@willie-the-truck>
Hi Will,
On Tue, Aug 13, 2019 at 01:06:44PM +0100, Will Deacon wrote:
> [+Steve]
>
> On Tue, Aug 13, 2019 at 11:58:52AM +0100, Will Deacon wrote:
> > On Tue, Aug 13, 2019 at 10:02:01AM +0100, Will Deacon wrote:
> > > On Mon, Aug 12, 2019 at 05:51:35PM -0400, Qian Cai wrote:
> > > > Booting today's linux-next on an arm64 server triggers a panic with
> > > > CONFIG_KASAN_SW_TAGS=y pointing to this line,
> > >
> > > Is this the only change on top of defconfig? If not, please can you share
> > > your full .config?
> > >
> > > > kfree()->virt_to_head_page()->compound_head()
> > > >
> > > > unsigned long head = READ_ONCE(page->compound_head);
> > > >
> > > > The bisect so far indicates one of those could be bad,
> > >
> > > I guess that means the issue is reproducible on the arm64 for-next/core
> > > branch. Once I have your .config, I'll give it a go.
> >
> > FWIW, I've managed to reproduce this using defconfig + SW_TAGS on
> > for-next/core, so I'll keep investigating.
I've installed clang-8 and enabled CONFIG_KASAN_SW_TAGS and was able to
reproduce the problem quite rapidly. Many apologies for missing this
before in my testing.
>
> Right, hacky diff below seems to resolve this, so I'll split this up into
> some proper patches as there is more than one bug here.
>
> Thanks,
>
> Will
>
> --->8
>
> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
FWIW, this fixed the crashes I experienced, I'll run some additional
tests.
Cheers,
--
Steve
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^ permalink raw reply
* Re: [PATCH 2/7] dt-bindings: devfreq: Add bindings for generic imx buses
From: Rob Herring @ 2019-08-13 14:06 UTC (permalink / raw)
To: Leonard Crestez
Cc: Mark Rutland, Artur Świgoń, Jacky Bai, Viresh Kumar,
Michael Turquette, Alexandre Bailon, Will Deacon, Abel Vesa,
Saravana Kannan, Krzysztof Kozlowski, Chanwoo Choi, MyungJoo Ham,
dl-linux-imx, devicetree@vger.kernel.org, open list:THERMAL,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Aisheng Dong, Anson Huang, Stephen Boyd, Kyungmin Park,
Sascha Hauer, Fabio Estevam, Shawn Guo, Georgi Djakov
In-Reply-To: <VI1PR04MB702300C8C78BC033D16EDB85EED20@VI1PR04MB7023.eurprd04.prod.outlook.com>
On Mon, Aug 12, 2019 at 7:32 PM Leonard Crestez <leonard.crestez@nxp.com> wrote:
>
> On 8/12/2019 10:47 PM, Rob Herring wrote:
> > On Mon, Aug 12, 2019 at 12:49 PM Leonard Crestez <leonard.crestez@nxp.com> wrote:
>
> >> Add initial dt bindings for the interconnects inside i.MX chips.
> >> Multiple external IPs are involved but SOC integration means the
> >> software controllable interfaces are very similar.
> >>
> >> +description: |
> >> + The i.MX SoC family has multiple buses for which clock frequency (and sometimes
> >> + voltage) can be adjusted.
> >> +
> >> + Some of those buses expose register areas mentioned in the memory maps as GPV
> >> + ("Global Programmers View") but not all. Access to this area might be denied for
> >> + normal world.
> >> +
> >> + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
> >> + FlexNOC but DT bindings are specific to the integration of these bus
> >> + interconnect IPs into imx SOCs.
> >
> > No need to use the interconnect binding?
>
> Separate RFC: https://patchwork.kernel.org/patch/11078673/
>
> The interconnect is represented by a separate "virtual" node which might
> not be OK. There was also a recent RFC from samsung which turns devfreq
> nodes into interconnect providers:
> https://patchwork.kernel.org/cover/11054417/
>
> Is that preferable?
Virtual nodes are not OK.
>
> >> +required:
> >> + - compatible
> >> + - clocks
> >
> > reg?
>
> This is deliberately optional: for some NICs the GPV register area is
> not exposed in the memory map. This is unusual but an accurate
> description of the hardware.
Different h/w blocks should have different compatibles. GPV is an Arm
thing and I'd expect FlexNOC to be different.
> The current driver doesn't even attempt to map registers, it only
> adjusts the clock.
Irrelevant to the binding...
>
> >> +examples:
> >> + - |
> >> + #include <dt-bindings/clock/imx8mm-clock.h>
> >> + noc: noc@32700000 {
> >> + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
> >
> > Doesn't match the schema. (Well, it does with 'contains', but
> > fsl,imx8mm-noc is not documented.)
>
> I'm confused about how per-SOC compatible strings works with validation.
> There is a rule that every SOC dtsi needs to add soc prefix to all
> device nodes but of_device_id in driver code doesn't need to be updated.
>
> Without using "contains" on the "compatible" property then all
> SOC-specific compatible strings would need to be mentioned in every yaml
> files. Unless I'm missing something this means updating update every
> binding file for each new SOC?
Yes. The main exception is if various SoCs are just packaging,
binning, or fuse differences.
>
> I guess it can be useful because it also validates the compatible
> sequence itself.
Right. Order matters.
>
> For this current example something like this seems to work:
>
> compatible:
> oneOf:
> - items:
> - enum:
> - fsl,imx8mm-nic
> - fsl,imx8mq-nic
> - const: fsl,imx8m-nic
> - items:
> - enum:
> - fsl,imx8mm-noc
> - fsl,imx8mq-noc
> - const: fsl,imx8m-noc
Looks correct.
Rob
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