* [PATCH v5 02/15] ASoC: sun4i-i2s: Add set_tdm_slot functionality
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Codecs without a control connection such as i2s based HDMI audio and
the Pine64 DAC require a different amount of bit clocks per frame than
what is calculated by the sample width. Use the tdm slot bindings to
provide this mechanism.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 8201334a059b..7c37b6291df0 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -195,6 +195,9 @@ struct sun4i_i2s {
struct regmap_field *field_rxchansel;
const struct sun4i_i2s_quirks *variant;
+
+ unsigned int tdm_slots;
+ unsigned int slot_width;
};
struct sun4i_i2s_clk_div {
@@ -346,7 +349,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
if (i2s->variant->has_fmt_set_lrck_period)
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
- SUN8I_I2S_FMT0_LRCK_PERIOD(32));
+ SUN8I_I2S_FMT0_LRCK_PERIOD(word_size));
/* Set sign extension to pad out LSB with 0 */
regmap_field_write(i2s->field_fmt_sext, 0);
@@ -450,7 +453,8 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
regmap_field_write(i2s->field_fmt_sr, sr);
return sun4i_i2s_set_clk_rate(dai, params_rate(params),
- params_width(params));
+ i2s->tdm_slots ?
+ i2s->slot_width : params_width(params));
}
static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
@@ -693,10 +697,25 @@ static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
return 0;
}
+static int sun4i_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
+ unsigned int tx_mask,
+ unsigned int rx_mask,
+ int slots, int width)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+
+ i2s->tdm_slots = slots;
+
+ i2s->slot_width = width;
+
+ return 0;
+}
+
static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
.hw_params = sun4i_i2s_hw_params,
.set_fmt = sun4i_i2s_set_fmt,
.set_sysclk = sun4i_i2s_set_sysclk,
+ .set_tdm_slot = sun4i_i2s_set_dai_tdm_slot,
.trigger = sun4i_i2s_trigger,
};
--
2.22.0
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* [PATCH v5 03/15] ASoC: sun4i-i2s: Correct divider calculations
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
The clock division circuitry is different on the H3 and later SoCs.
The division of bclk is now based on pll2.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 73 +++++++++++++++++++++++++------------
1 file changed, 49 insertions(+), 24 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 7c37b6291df0..34f31439ae7b 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -127,8 +127,6 @@ struct sun4i_i2s;
* @has_chsel_offset: SoC uses offset for selecting dai operational mode.
* @reg_offset_txdata: offset of the tx fifo.
* @sun4i_i2s_regmap: regmap config to use.
- * @mclk_offset: Value by which mclkdiv needs to be adjusted.
- * @bclk_offset: Value by which bclkdiv needs to be adjusted.
* @field_clkdiv_mclk_en: regmap field to enable mclk output.
* @field_fmt_wss: regmap field to set word select size.
* @field_fmt_sr: regmap field to set sample resolution.
@@ -150,8 +148,6 @@ struct sun4i_i2s_quirks {
bool has_chsel_offset;
unsigned int reg_offset_txdata; /* TX FIFO */
const struct regmap_config *sun4i_i2s_regmap;
- unsigned int mclk_offset;
- unsigned int bclk_offset;
/* Register fields for i2s */
struct reg_field field_clkdiv_mclk_en;
@@ -212,7 +208,25 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
{ .div = 8, .val = 3 },
{ .div = 12, .val = 4 },
{ .div = 16, .val = 5 },
- /* TODO - extend divide ratio supported by newer SoCs */
+};
+
+static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
+ { .div = 0, .val = 0 },
+ { .div = 1, .val = 1 },
+ { .div = 2, .val = 2 },
+ { .div = 4, .val = 3 },
+ { .div = 6, .val = 4 },
+ { .div = 8, .val = 5 },
+ { .div = 12, .val = 6 },
+ { .div = 16, .val = 7 },
+ { .div = 24, .val = 8 },
+ { .div = 32, .val = 9 },
+ { .div = 48, .val = 10 },
+ { .div = 64, .val = 11 },
+ { .div = 96, .val = 12 },
+ { .div = 128, .val = 13 },
+ { .div = 176, .val = 14 },
+ { .div = 192, .val = 15 },
};
static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
@@ -224,21 +238,21 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
{ .div = 12, .val = 5 },
{ .div = 16, .val = 6 },
{ .div = 24, .val = 7 },
- /* TODO - extend divide ratio supported by newer SoCs */
};
static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
unsigned int oversample_rate,
- unsigned int word_size)
+ unsigned int word_size,
+ const struct sun4i_i2s_clk_div *bdiv,
+ unsigned int size)
{
int div = oversample_rate / word_size / 2;
int i;
- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
- const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
-
+ for (i = 0; i < size; i++) {
if (bdiv->div == div)
return bdiv->val;
+ bdiv++;
}
return -EINVAL;
@@ -247,16 +261,17 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
unsigned int oversample_rate,
unsigned int module_rate,
- unsigned int sampling_rate)
+ unsigned int sampling_rate,
+ const struct sun4i_i2s_clk_div *mdiv,
+ unsigned int size)
{
int div = module_rate / sampling_rate / oversample_rate;
int i;
- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
- const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
-
+ for (i = 0; i < size; i++) {
if (mdiv->div == div)
return mdiv->val;
+ mdiv++;
}
return -EINVAL;
@@ -321,24 +336,36 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return -EINVAL;
}
- bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
- word_size);
+ if (i2s->variant->has_fmt_set_lrck_period)
+ bclk_div = sun4i_i2s_get_bclk_div(i2s, clk_rate / rate,
+ word_size,
+ sun8i_i2s_clk_div,
+ ARRAY_SIZE(sun8i_i2s_clk_div));
+ else
+ bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
+ word_size,
+ sun4i_i2s_bclk_div,
+ ARRAY_SIZE(sun4i_i2s_bclk_div));
if (bclk_div < 0) {
dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
return -EINVAL;
}
- mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
- clk_rate, rate);
+ if (i2s->variant->has_fmt_set_lrck_period)
+ mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
+ clk_rate, rate,
+ sun8i_i2s_clk_div,
+ ARRAY_SIZE(sun8i_i2s_clk_div));
+ else
+ mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
+ clk_rate, rate,
+ sun4i_i2s_mclk_div,
+ ARRAY_SIZE(sun4i_i2s_mclk_div));
if (mclk_div < 0) {
dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
return -EINVAL;
}
- /* Adjust the clock division values if needed */
- bclk_div += i2s->variant->bclk_offset;
- mclk_div += i2s->variant->mclk_offset;
-
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
@@ -994,8 +1021,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
- .mclk_offset = 1,
- .bclk_offset = 2,
.has_fmt_set_lrck_period = true,
.has_chcfg = true,
.has_chsel_tx_chen = true,
--
2.22.0
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* [PATCH v5 04/15] ASoC: sun4i-i2s: Support more formats on newer SoCs
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
There is a need to support more formats on the newer SoCs(H3 and later).
Extend the formats supported to include DSP_A and DSP_B modes.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 87 +++++++++++++++++++++++++++----------
1 file changed, 63 insertions(+), 24 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 34f31439ae7b..3553c17318b0 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -27,6 +27,8 @@
#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
+#define SUN4I_I2S_CTRL_PCM BIT(4)
+#define SUN4I_I2S_CTRL_LOOP BIT(3)
#define SUN4I_I2S_CTRL_TX_EN BIT(2)
#define SUN4I_I2S_CTRL_RX_EN BIT(1)
#define SUN4I_I2S_CTRL_GL_EN BIT(0)
@@ -91,6 +93,9 @@
/* Defines required for sun8i-h3 support */
#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
+#define SUN8I_I2S_CTRL_MODE_RIGHT_J (2 << 0)
+#define SUN8I_I2S_CTRL_MODE_I2S_LEFT_J (1 << 0)
+#define SUN8I_I2S_CTRL_MODE_PCM (0 << 0)
#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
@@ -164,6 +169,7 @@ struct sun4i_i2s_quirks {
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
+ int (*set_format)(struct sun4i_i2s *, unsigned int);
};
struct sun4i_i2s {
@@ -194,6 +200,7 @@ struct sun4i_i2s {
unsigned int tdm_slots;
unsigned int slot_width;
+ unsigned int offset;
};
struct sun4i_i2s_clk_div {
@@ -484,19 +491,14 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
i2s->slot_width : params_width(params));
}
-static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+static int sun4i_i2s_set_format(struct sun4i_i2s *i2s, unsigned int fmt)
{
- struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
- u32 offset = 0;
- u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
- u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val = SUN4I_I2S_FMT0_FMT_I2S;
- offset = 1;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = SUN4I_I2S_FMT0_FMT_LEFT_J;
@@ -505,32 +507,64 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
break;
default:
- dev_err(dai->dev, "Unsupported format: %d\n",
- fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
- if (i2s->variant->has_chsel_offset) {
- /*
- * offset being set indicates that we're connected to an i2s
- * device, however offset is only used on the sun8i block and
- * i2s shares the same setting with the LJ format. Increment
- * val so that the bit to value to write is correct.
- */
- if (offset > 0)
- val++;
- /* blck offset determines whether i2s or LJ */
- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
- SUN8I_I2S_TX_CHAN_OFFSET_MASK,
- SUN8I_I2S_TX_CHAN_OFFSET(offset));
+ regmap_field_write(i2s->field_fmt_mode, val);
+
+ return 0;
+}
+
+static int sun8i_i2s_set_format(struct sun4i_i2s *i2s, unsigned int fmt)
+{
+ u32 val;
- regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
- SUN8I_I2S_TX_CHAN_OFFSET_MASK,
- SUN8I_I2S_TX_CHAN_OFFSET(offset));
+ /* DAI Mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ i2s->offset = 1;
+ case SND_SOC_DAIFMT_LEFT_J:
+ val = SUN8I_I2S_CTRL_MODE_I2S_LEFT_J;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ val = SUN8I_I2S_CTRL_MODE_RIGHT_J;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ i2s->offset = 1;
+ case SND_SOC_DAIFMT_DSP_B:
+ val = SUN8I_I2S_CTRL_MODE_PCM;
+ break;
+
+ default:
+ return -EINVAL;
}
+ /*
+ * bclk offset determines whether i2s or LJ if in i2s mode and
+ * DSP_A or DSP_B if in PCM mode.
+ */
+ i2s->variant->set_txchanoffset(i2s, 0);
+ i2s->variant->set_rxchanoffset(i2s);
+
regmap_field_write(i2s->field_fmt_mode, val);
+ return 0;
+}
+
+static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ u32 val;
+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+
+ /* Set DAI Mode */
+ if (i2s->variant->set_format(i2s, fmt) != 0) {
+ dev_err(dai->dev, "Unsupported format: %d\n",
+ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+ return -EINVAL;
+ }
+
/* DAI clock polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
@@ -976,6 +1010,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
+ .set_format = sun4i_i2s_set_format,
};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
@@ -996,6 +1031,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
+ .set_format = sun4i_i2s_set_format,
};
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
@@ -1015,6 +1051,7 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
+ .set_format = sun4i_i2s_set_format,
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
@@ -1038,6 +1075,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
+ .set_format = sun8i_i2s_set_format,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
@@ -1058,6 +1096,7 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
+ .set_format = sun4i_i2s_set_format,
};
static int sun4i_i2s_init_regmap_fields(struct device *dev,
--
2.22.0
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* [PATCH v5 05/15] ASoC: sun4i-i2s: Add functions for RX and TX channel offsets
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Newer SoCs like the H6 have the channel offset bits in a different
position to what is on the H3. As we will eventually add multi-
channel support then create function calls as opposed to regmap
fields to add support for different devices.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 3553c17318b0..4a748747ccd7 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -112,7 +112,7 @@
#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
-#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
+#define SUN8I_I2S_TX_CHAN_OFFSET(offset) ((offset) << 12)
#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
@@ -170,6 +170,8 @@ struct sun4i_i2s_quirks {
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
int (*set_format)(struct sun4i_i2s *, unsigned int);
+ void (*set_txchanoffset)(const struct sun4i_i2s *, int);
+ void (*set_rxchanoffset)(const struct sun4i_i2s *);
};
struct sun4i_i2s {
@@ -424,6 +426,24 @@ static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
return (width - 8) / 4 + 1;
}
+static void sun8i_i2s_set_txchanoffset(const struct sun4i_i2s *i2s, int output)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset));
+ }
+}
+
+static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset));
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -1076,6 +1096,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_format = sun8i_i2s_set_format,
+ .set_txchanoffset = sun8i_i2s_set_txchanoffset,
+ .set_rxchanoffset = sun8i_i2s_set_rxchanoffset,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
--
2.22.0
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^ permalink raw reply related
* [PATCH v5 06/15] ASoC: sun4i-i2s: Add functions for RX and TX channel enables
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Newer SoCs like the H6 have the channel enable bits in a different
position to what is on the H3. As we will eventually add multi-
channel support then create function calls as opposed to regmap
fields to add support for different devices.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 4a748747ccd7..ad2ff83deeb7 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -172,6 +172,8 @@ struct sun4i_i2s_quirks {
int (*set_format)(struct sun4i_i2s *, unsigned int);
void (*set_txchanoffset)(const struct sun4i_i2s *, int);
void (*set_rxchanoffset)(const struct sun4i_i2s *);
+ void (*set_txchanen)(const struct sun4i_i2s *, int, int);
+ void (*set_rxchanen)(const struct sun4i_i2s *, int);
};
struct sun4i_i2s {
@@ -444,6 +446,25 @@ static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s)
SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset));
}
+static void sun8i_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN8I_I2S_TX_CHAN_EN_MASK,
+ SUN8I_I2S_TX_CHAN_EN(channel));
+ }
+}
+
+static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_EN_MASK,
+ SUN8I_I2S_TX_CHAN_EN(channel));
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -479,10 +500,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
regmap_field_write(i2s->field_rxchansel,
SUN4I_I2S_CHAN_SEL(params_channels(params)));
- if (i2s->variant->has_chsel_tx_chen)
- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
- SUN8I_I2S_TX_CHAN_EN_MASK,
- SUN8I_I2S_TX_CHAN_EN(channels));
+ if (i2s->variant->set_txchanen)
+ i2s->variant->set_txchanen(i2s, 0, channels);
+
+ if (i2s->variant->set_rxchanen)
+ i2s->variant->set_rxchanen(i2s, channels);
switch (params_physical_width(params)) {
case 16:
@@ -1098,6 +1120,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.set_format = sun8i_i2s_set_format,
.set_txchanoffset = sun8i_i2s_set_txchanoffset,
.set_rxchanoffset = sun8i_i2s_set_rxchanoffset,
+ .set_txchanen = sun8i_i2s_set_txchanen,
+ .set_rxchanen = sun8i_i2s_set_rxchanen,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
--
2.22.0
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^ permalink raw reply related
* [PATCH v5 07/15] ASoC: sun4i-i2s: Add functions for RX and TX channel selects
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Newer SoCs like the H6 have the channel select bits in a different
positions than what is on the H3. As we will eventually add multi-
channel support then create function calls as opposed to regmap
fields to add support for different devices.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 87 ++++++++++++++++++++++---------------
1 file changed, 53 insertions(+), 34 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index ad2ff83deeb7..0b98adde0717 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -115,6 +115,8 @@
#define SUN8I_I2S_TX_CHAN_OFFSET(offset) ((offset) << 12)
#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
+#define SUN8I_I2S_TX_CHAN_SEL_MASK GENMASK(2, 0)
+#define SUN8I_I2S_TX_CHAN_SEL(chan) (chan - 1)
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
@@ -141,8 +143,6 @@ struct sun4i_i2s;
* @field_fmt_sext: regmap field to set the sign extension.
* @field_txchanmap: location of the tx channel mapping register.
* @field_rxchanmap: location of the rx channel mapping register.
- * @field_txchansel: location of the tx channel select bit fields.
- * @field_rxchansel: location of the rx channel select bit fields.
*/
struct sun4i_i2s_quirks {
bool has_reset;
@@ -164,8 +164,6 @@ struct sun4i_i2s_quirks {
struct reg_field field_fmt_sext;
struct reg_field field_txchanmap;
struct reg_field field_rxchanmap;
- struct reg_field field_txchansel;
- struct reg_field field_rxchansel;
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
@@ -174,6 +172,8 @@ struct sun4i_i2s_quirks {
void (*set_rxchanoffset)(const struct sun4i_i2s *);
void (*set_txchanen)(const struct sun4i_i2s *, int, int);
void (*set_rxchanen)(const struct sun4i_i2s *, int);
+ void (*set_txchansel)(const struct sun4i_i2s *, int, int);
+ void (*set_rxchansel)(const struct sun4i_i2s *, int);
};
struct sun4i_i2s {
@@ -197,8 +197,6 @@ struct sun4i_i2s {
struct regmap_field *field_fmt_sext;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
- struct regmap_field *field_txchansel;
- struct regmap_field *field_rxchansel;
const struct sun4i_i2s_quirks *variant;
@@ -465,6 +463,42 @@ static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel)
SUN8I_I2S_TX_CHAN_EN(channel));
}
+static void sun4i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ /* Configure the channels */
+ regmap_write(i2s->regmap,
+ SUN4I_I2S_TX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL(channel));
+}
+
+static void sun8i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN8I_I2S_TX_CHAN_SEL_MASK,
+ SUN8I_I2S_TX_CHAN_SEL(channel));
+ }
+}
+
+static void sun4i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel)
+{
+ /* Configure the channels */
+ regmap_write(i2s->regmap,
+ SUN4I_I2S_RX_CHAN_SEL_REG,
+ SUN4I_I2S_CHAN_SEL(channel));
+}
+
+static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_SEL_MASK,
+ SUN8I_I2S_TX_CHAN_SEL(channel));
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -494,11 +528,8 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
regmap_field_write(i2s->field_rxchanmap, 0x00003210);
/* Configure the channels */
- regmap_field_write(i2s->field_txchansel,
- SUN4I_I2S_CHAN_SEL(params_channels(params)));
-
- regmap_field_write(i2s->field_rxchansel,
- SUN4I_I2S_CHAN_SEL(params_channels(params)));
+ i2s->variant->set_txchansel(i2s, 0, channels);
+ i2s->variant->set_rxchansel(i2s, channels);
if (i2s->variant->set_txchanen)
i2s->variant->set_txchanen(i2s, 0, channels);
@@ -1048,11 +1079,11 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
+ .set_txchansel = sun4i_i2s_set_txchansel,
+ .set_rxchansel = sun4i_i2s_set_rxchansel,
};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
@@ -1069,11 +1100,11 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
+ .set_txchansel = sun4i_i2s_set_txchansel,
+ .set_rxchansel = sun4i_i2s_set_rxchansel,
};
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
@@ -1089,11 +1120,11 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_format = sun4i_i2s_set_format,
+ .set_txchansel = sun4i_i2s_set_txchansel,
+ .set_rxchansel = sun4i_i2s_set_rxchansel,
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
@@ -1113,8 +1144,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5),
.field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
- .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
- .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_format = sun8i_i2s_set_format,
@@ -1122,6 +1151,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.set_rxchanoffset = sun8i_i2s_set_rxchanoffset,
.set_txchanen = sun8i_i2s_set_txchanen,
.set_rxchanen = sun8i_i2s_set_rxchanen,
+ .set_txchansel = sun8i_i2s_set_txchansel,
+ .set_rxchansel = sun8i_i2s_set_rxchansel,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
@@ -1138,11 +1169,11 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
.field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
- .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
- .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
+ .set_txchansel = sun4i_i2s_set_txchansel,
+ .set_rxchansel = sun4i_i2s_set_rxchansel,
};
static int sun4i_i2s_init_regmap_fields(struct device *dev,
@@ -1199,19 +1230,7 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
i2s->field_rxchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_rxchanmap);
- if (IS_ERR(i2s->field_rxchanmap))
- return PTR_ERR(i2s->field_rxchanmap);
-
- i2s->field_txchansel =
- devm_regmap_field_alloc(dev, i2s->regmap,
- i2s->variant->field_txchansel);
- if (IS_ERR(i2s->field_txchansel))
- return PTR_ERR(i2s->field_txchansel);
-
- i2s->field_rxchansel =
- devm_regmap_field_alloc(dev, i2s->regmap,
- i2s->variant->field_rxchansel);
- return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
+ return PTR_ERR_OR_ZERO(i2s->field_rxchanmap);
}
static int sun4i_i2s_probe(struct platform_device *pdev)
--
2.22.0
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^ permalink raw reply related
* [PATCH v5 08/15] ASoC: sun4i-i2s: Add functions for channel mapping
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
As we will eventually add multi-channel audio support to the i2s
then create function calls as opposed to regmap fields to add
support for different devices.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 71 +++++++++++++++++++++----------------
1 file changed, 40 insertions(+), 31 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 0b98adde0717..6de3cb41aaf6 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -141,8 +141,6 @@ struct sun4i_i2s;
* @field_fmt_lrclk: regmap field to set frame polarity.
* @field_fmt_mode: regmap field to set the operational mode.
* @field_fmt_sext: regmap field to set the sign extension.
- * @field_txchanmap: location of the tx channel mapping register.
- * @field_rxchanmap: location of the rx channel mapping register.
*/
struct sun4i_i2s_quirks {
bool has_reset;
@@ -162,8 +160,6 @@ struct sun4i_i2s_quirks {
struct reg_field field_fmt_lrclk;
struct reg_field field_fmt_mode;
struct reg_field field_fmt_sext;
- struct reg_field field_txchanmap;
- struct reg_field field_rxchanmap;
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
@@ -174,6 +170,8 @@ struct sun4i_i2s_quirks {
void (*set_rxchanen)(const struct sun4i_i2s *, int);
void (*set_txchansel)(const struct sun4i_i2s *, int, int);
void (*set_rxchansel)(const struct sun4i_i2s *, int);
+ void (*set_txchanmap)(const struct sun4i_i2s *, int, int);
+ void (*set_rxchanmap)(const struct sun4i_i2s *, int);
};
struct sun4i_i2s {
@@ -195,8 +193,6 @@ struct sun4i_i2s {
struct regmap_field *field_fmt_lrclk;
struct regmap_field *field_fmt_mode;
struct regmap_field *field_fmt_sext;
- struct regmap_field *field_txchanmap;
- struct regmap_field *field_rxchanmap;
const struct sun4i_i2s_quirks *variant;
@@ -499,6 +495,31 @@ static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel)
SUN8I_I2S_TX_CHAN_SEL(channel));
}
+static void sun4i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, channel);
+}
+
+static void sun8i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_write(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_MAP_REG + (output * 4), channel);
+ }
+}
+
+static void sun4i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, channel);
+}
+
+static void sun8i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, channel);
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -524,8 +545,8 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
}
/* Map the channels for playback and capture */
- regmap_field_write(i2s->field_txchanmap, 0x76543210);
- regmap_field_write(i2s->field_rxchanmap, 0x00003210);
+ i2s->variant->set_txchanmap(i2s, 0, 0x76543210);
+ i2s->variant->set_rxchanmap(i2s, 0x00003210);
/* Configure the channels */
i2s->variant->set_txchansel(i2s, 0, channels);
@@ -1077,13 +1098,13 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.has_slave_select_bit = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
.set_txchansel = sun4i_i2s_set_txchansel,
.set_rxchansel = sun4i_i2s_set_rxchansel,
+ .set_txchanmap = sun4i_i2s_set_txchanmap,
+ .set_rxchanmap = sun4i_i2s_set_rxchanmap,
};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
@@ -1098,13 +1119,13 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.has_slave_select_bit = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
.set_txchansel = sun4i_i2s_set_txchansel,
.set_rxchansel = sun4i_i2s_set_rxchansel,
+ .set_txchanmap = sun4i_i2s_set_txchanmap,
+ .set_rxchanmap = sun4i_i2s_set_rxchanmap,
};
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
@@ -1118,13 +1139,13 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.has_slave_select_bit = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_format = sun4i_i2s_set_format,
.set_txchansel = sun4i_i2s_set_txchansel,
.set_rxchansel = sun4i_i2s_set_rxchansel,
+ .set_txchanmap = sun4i_i2s_set_txchanmap,
+ .set_rxchanmap = sun4i_i2s_set_rxchanmap,
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
@@ -1142,8 +1163,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
.field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5),
- .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
- .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_format = sun8i_i2s_set_format,
@@ -1153,6 +1172,8 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.set_rxchanen = sun8i_i2s_set_rxchanen,
.set_txchansel = sun8i_i2s_set_txchansel,
.set_rxchansel = sun8i_i2s_set_rxchansel,
+ .set_txchanmap = sun8i_i2s_set_txchanmap,
+ .set_rxchanmap = sun8i_i2s_set_rxchanmap,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
@@ -1167,13 +1188,13 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8),
- .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
- .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_format = sun4i_i2s_set_format,
.set_txchansel = sun4i_i2s_set_txchansel,
.set_rxchansel = sun4i_i2s_set_rxchansel,
+ .set_txchanmap = sun4i_i2s_set_txchanmap,
+ .set_rxchanmap = sun4i_i2s_set_rxchanmap,
};
static int sun4i_i2s_init_regmap_fields(struct device *dev,
@@ -1218,19 +1239,7 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
i2s->field_fmt_sext =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_fmt_sext);
- if (IS_ERR(i2s->field_fmt_sext))
- return PTR_ERR(i2s->field_fmt_sext);
-
- i2s->field_txchanmap =
- devm_regmap_field_alloc(dev, i2s->regmap,
- i2s->variant->field_txchanmap);
- if (IS_ERR(i2s->field_txchanmap))
- return PTR_ERR(i2s->field_txchanmap);
-
- i2s->field_rxchanmap =
- devm_regmap_field_alloc(dev, i2s->regmap,
- i2s->variant->field_rxchanmap);
- return PTR_ERR_OR_ZERO(i2s->field_rxchanmap);
+ return PTR_ERR_OR_ZERO(i2s->field_fmt_sext);
}
static int sun4i_i2s_probe(struct platform_device *pdev)
--
2.22.0
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* [PATCH v5 09/15] clk: sunxi-ng: h6: Allow I2S to change parent rate
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: Jernej Skrabec, alsa-devel, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Jernej Skrabec <jernej.skrabec@siol.net>
I2S doesn't work if parent rate couldn't be change. Difference between
wanted and actual rate is too big.
Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index aebef4af9861..d89353a3cdec 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -505,7 +505,7 @@ static struct ccu_div i2s3_clk = {
.hw.init = CLK_HW_INIT_PARENTS("i2s3",
audio_parents,
&ccu_div_ops,
- 0),
+ CLK_SET_RATE_PARENT),
},
};
@@ -518,7 +518,7 @@ static struct ccu_div i2s0_clk = {
.hw.init = CLK_HW_INIT_PARENTS("i2s0",
audio_parents,
&ccu_div_ops,
- 0),
+ CLK_SET_RATE_PARENT),
},
};
@@ -531,7 +531,7 @@ static struct ccu_div i2s1_clk = {
.hw.init = CLK_HW_INIT_PARENTS("i2s1",
audio_parents,
&ccu_div_ops,
- 0),
+ CLK_SET_RATE_PARENT),
},
};
@@ -544,7 +544,7 @@ static struct ccu_div i2s2_clk = {
.hw.init = CLK_HW_INIT_PARENTS("i2s2",
audio_parents,
&ccu_div_ops,
- 0),
+ CLK_SET_RATE_PARENT),
},
};
--
2.22.0
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* [PATCH v5 10/15] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: Jernej Skrabec, alsa-devel, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Jernej Skrabec <jernej.skrabec@siol.net>
H6 I2S is very similar to H3, except that it supports up to 16 channels
and thus few registers have fields on different position.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
index eb3992138eec..6928d0a1dcc8 100644
--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- const: allwinner,sun50i-a64-i2s
- const: allwinner,sun8i-h3-i2s
+ - const: allwinner,sun50i-h6-i2s
reg:
maxItems: 1
@@ -59,6 +60,7 @@ allOf:
- allwinner,sun8i-a83t-i2s
- allwinner,sun8i-h3-i2s
- allwinner,sun50i-a64-codec-i2s
+ - allwinner,sun50i-h6-i2s
then:
required:
--
2.22.0
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^ permalink raw reply related
* [PATCH v5 11/15] ASoC: sun4i-i2s: Add support for H6 I2S
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: Jernej Skrabec, alsa-devel, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Jernej Skrabec <jernej.skrabec@siol.net>
H6 I2S is very similar to that in H3, except it supports up to 16
channels.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
sound/soc/sunxi/sun4i-i2s.c | 148 ++++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 6de3cb41aaf6..a8d98696fe7c 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -121,6 +121,21 @@
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
+/* Defines required for sun50i-h6 support */
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
+#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
+#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
+
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+
+#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
+#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
+
struct sun4i_i2s;
/**
@@ -440,6 +455,25 @@ static void sun8i_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s)
SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset));
}
+static void sun50i_h6_i2s_set_txchanoffset(const struct sun4i_i2s *i2s, int output)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(i2s->offset));
+ }
+
+}
+
+static void sun50i_h6_i2s_set_rxchanoffset(const struct sun4i_i2s *i2s)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(i2s->offset));
+}
+
static void sun8i_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output,
int channel)
{
@@ -459,6 +493,26 @@ static void sun8i_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel)
SUN8I_I2S_TX_CHAN_EN(channel));
}
+
+static void sun50i_h6_i2s_set_txchanen(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channel));
+ }
+}
+
+static void sun50i_h6_i2s_set_rxchanen(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_EN_MASK,
+ SUN50I_H6_I2S_TX_CHAN_EN(channel));
+}
+
static void sun4i_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output,
int channel)
{
@@ -495,6 +549,25 @@ static void sun8i_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel)
SUN8I_I2S_TX_CHAN_SEL(channel));
}
+static void sun50i_h6_i2s_set_txchansel(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_update_bits(i2s->regmap,
+ SUN8I_I2S_TX_CHAN_SEL_REG + (output * 4),
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channel));
+ }
+}
+
+static void sun50i_h6_i2s_set_rxchansel(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_update_bits(i2s->regmap,
+ SUN50I_H6_I2S_RX_CHAN_SEL_REG,
+ SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
+ SUN50I_H6_I2S_TX_CHAN_SEL(channel));
+}
+
static void sun4i_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output,
int channel)
{
@@ -520,6 +593,20 @@ static void sun8i_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel)
regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, channel);
}
+static void sun50i_h6_i2s_set_txchanmap(const struct sun4i_i2s *i2s, int output,
+ int channel)
+{
+ if (output >= 0 && output < 4) {
+ regmap_write(i2s->regmap,
+ SUN50I_H6_I2S_TX_CHAN_MAP1_REG + (output * 8), channel);
+ }
+}
+
+static void sun50i_h6_i2s_set_rxchanmap(const struct sun4i_i2s *i2s, int channel)
+{
+ regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, channel);
+}
+
static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -996,6 +1083,22 @@ static const struct reg_default sun8i_i2s_reg_defaults[] = {
{ SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
};
+static const struct reg_default sun50i_i2s_reg_defaults[] = {
+ { SUN4I_I2S_CTRL_REG, 0x00060000 },
+ { SUN4I_I2S_FMT0_REG, 0x00000033 },
+ { SUN4I_I2S_FMT1_REG, 0x00000030 },
+ { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
+ { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
+ { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
+ { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
+ { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
+ { SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 },
+ { SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
+ { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
+};
+
static const struct regmap_config sun4i_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -1023,6 +1126,19 @@ static const struct regmap_config sun8i_i2s_regmap_config = {
.volatile_reg = sun8i_i2s_volatile_reg,
};
+static const struct regmap_config sun50i_i2s_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = SUN50I_H6_I2S_RX_CHAN_MAP1_REG,
+ .cache_type = REGCACHE_FLAT,
+ .reg_defaults = sun50i_i2s_reg_defaults,
+ .num_reg_defaults = ARRAY_SIZE(sun50i_i2s_reg_defaults),
+ .writeable_reg = sun4i_i2s_wr_reg,
+ .readable_reg = sun8i_i2s_rd_reg,
+ .volatile_reg = sun8i_i2s_volatile_reg,
+};
+
static int sun4i_i2s_runtime_resume(struct device *dev)
{
struct sun4i_i2s *i2s = dev_get_drvdata(dev);
@@ -1197,6 +1313,34 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.set_rxchanmap = sun4i_i2s_set_rxchanmap,
};
+static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = {
+ .has_reset = true,
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
+ .sun4i_i2s_regmap = &sun50i_i2s_regmap_config,
+ .has_fmt_set_lrck_period = true,
+ .has_chcfg = true,
+ .has_chsel_tx_chen = true,
+ .has_chsel_offset = true,
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
+ .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
+ .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
+ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5),
+ .get_sr = sun8i_i2s_get_sr_wss,
+ .get_wss = sun8i_i2s_get_sr_wss,
+ .set_format = sun8i_i2s_set_format,
+ .set_txchanoffset = sun50i_h6_i2s_set_txchanoffset,
+ .set_rxchanoffset = sun50i_h6_i2s_set_rxchanoffset,
+ .set_txchanen = sun50i_h6_i2s_set_txchanen,
+ .set_rxchanen = sun50i_h6_i2s_set_rxchanen,
+ .set_txchansel = sun50i_h6_i2s_set_txchansel,
+ .set_rxchansel = sun50i_h6_i2s_set_rxchansel,
+ .set_txchanmap = sun50i_h6_i2s_set_txchanmap,
+ .set_rxchanmap = sun50i_h6_i2s_set_rxchanmap,
+};
+
static int sun4i_i2s_init_regmap_fields(struct device *dev,
struct sun4i_i2s *i2s)
{
@@ -1389,6 +1533,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
.compatible = "allwinner,sun50i-a64-codec-i2s",
.data = &sun50i_a64_codec_i2s_quirks,
},
+ {
+ .compatible = "allwinner,sun50i-h6-i2s",
+ .data = &sun50i_h6_i2s_quirks,
+ },
{}
};
MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
--
2.22.0
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^ permalink raw reply related
* [PATCH v5 12/15] ASoC: sun4i-i2s: Add multi-lane functionality
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
The i2s block supports multi-lane i2s output however this functionality
is only possible in earlier SoCs where the pins are exposed and for
the i2s block used for HDMI audio on the later SoCs.
To enable this functionality, an optional property has been added to
the bindings.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index a8d98696fe7c..a020c3b372a8 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -23,7 +23,7 @@
#define SUN4I_I2S_CTRL_REG 0x00
#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
-#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
+#define SUN4I_I2S_CTRL_SDO_EN(lines) (((1 << lines) - 1) << 8)
#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
@@ -614,6 +614,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int sr, wss, channels;
u32 width;
+ int lines;
channels = params_channels(params);
if (channels != 2) {
@@ -622,6 +623,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
return -EINVAL;
}
+ lines = (channels + 1) / 2;
+
+ /* Enable the required output lines */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_SDO_EN_MASK,
+ SUN4I_I2S_CTRL_SDO_EN(lines));
+
if (i2s->variant->has_chcfg) {
regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
@@ -1389,9 +1397,10 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
static int sun4i_i2s_probe(struct platform_device *pdev)
{
struct sun4i_i2s *i2s;
+ struct snd_soc_dai_driver *soc_dai;
struct resource *res;
void __iomem *regs;
- int irq, ret;
+ int irq, ret, val;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
@@ -1456,6 +1465,19 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
i2s->capture_dma_data.maxburst = 8;
+ soc_dai = devm_kmemdup(&pdev->dev, &sun4i_i2s_dai,
+ sizeof(*soc_dai), GFP_KERNEL);
+ if (!soc_dai) {
+ ret = -ENOMEM;
+ goto err_pm_disable;
+ }
+
+ if (!of_property_read_u32(pdev->dev.of_node,
+ "allwinner,playback-channels", &val)) {
+ if (val >= 2 && val <= 8)
+ soc_dai->playback.channels_max = val;
+ }
+
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = sun4i_i2s_runtime_resume(&pdev->dev);
@@ -1465,7 +1487,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
ret = devm_snd_soc_register_component(&pdev->dev,
&sun4i_i2s_component,
- &sun4i_i2s_dai, 1);
+ soc_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
--
2.22.0
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* [PATCH v5 13/15] ASoC: sun4i-i2s: Add multichannel functionality
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
The i2s block can be used to pass PCM data over multiple channels
and is sometimes used for the audio side of an HDMI connection.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 93 +++++++++++++++++++++++++------------
1 file changed, 63 insertions(+), 30 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index a020c3b372a8..a71969167053 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -617,41 +617,74 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
int lines;
channels = params_channels(params);
- if (channels != 2) {
- dev_err(dai->dev, "Unsupported number of channels: %d\n",
- channels);
- return -EINVAL;
- }
-
- lines = (channels + 1) / 2;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ if ((channels > dai->driver->playback.channels_max) ||
+ (channels < dai->driver->playback.channels_min)) {
+ dev_err(dai->dev, "Unsupported number of channels: %d\n",
+ channels);
+ return -EINVAL;
+ }
- /* Enable the required output lines */
- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
- SUN4I_I2S_CTRL_SDO_EN_MASK,
- SUN4I_I2S_CTRL_SDO_EN(lines));
-
- if (i2s->variant->has_chcfg) {
- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
- }
+ lines = (channels + 1) / 2;
- /* Map the channels for playback and capture */
- i2s->variant->set_txchanmap(i2s, 0, 0x76543210);
- i2s->variant->set_rxchanmap(i2s, 0x00003210);
+ /* Enable the required output lines */
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_SDO_EN_MASK,
+ SUN4I_I2S_CTRL_SDO_EN(lines));
+
+ i2s->variant->set_txchanmap(i2s, 0, 0x10);
+ i2s->variant->set_txchansel(i2s, 0, channels > 1 ? 2:1);
+
+ if (i2s->variant->set_txchanen)
+ i2s->variant->set_txchanen(i2s, 0, 2);
+
+ if (i2s->variant->has_chcfg) {
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
+
+ if (channels > 2) {
+ i2s->variant->set_txchanmap(i2s, 1, 0x32);
+ i2s->variant->set_txchanoffset(i2s, 1);
+ i2s->variant->set_txchansel(i2s, 1,
+ channels > 3 ? 2:1);
+ i2s->variant->set_txchanen(i2s, 1, 2);
+ }
+ if (channels > 4) {
+ i2s->variant->set_txchanmap(i2s, 2, 0x54);
+ i2s->variant->set_txchanoffset(i2s, 2);
+ i2s->variant->set_txchansel(i2s, 2,
+ channels > 5 ? 2:1);
+ i2s->variant->set_txchanen(i2s, 2, 2);
+ }
+ if (channels > 6) {
+ i2s->variant->set_txchanmap(i2s, 3, 0x76);
+ i2s->variant->set_txchanoffset(i2s, 3);
+ i2s->variant->set_txchansel(i2s, 3,
+ channels > 6 ? 2:1);
+ i2s->variant->set_txchanen(i2s, 3, 2);
+ }
+ }
+ } else {
+ if ((channels > dai->driver->capture.channels_max) ||
+ (channels < dai->driver->capture.channels_min)) {
+ dev_err(dai->dev, "Unsupported number of channels: %d\n",
+ channels);
+ return -EINVAL;
+ }
- /* Configure the channels */
- i2s->variant->set_txchansel(i2s, 0, channels);
- i2s->variant->set_rxchansel(i2s, channels);
+ /* Map the channels for capture */
+ i2s->variant->set_rxchanmap(i2s, 0x10);
+ i2s->variant->set_rxchansel(i2s, channels);
- if (i2s->variant->set_txchanen)
- i2s->variant->set_txchanen(i2s, 0, channels);
+ if (i2s->variant->set_rxchanen)
+ i2s->variant->set_rxchanen(i2s, channels);
- if (i2s->variant->set_rxchanen)
- i2s->variant->set_rxchanen(i2s, channels);
+ if (i2s->variant->has_chcfg)
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
+ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
+ }
switch (params_physical_width(params)) {
case 16:
--
2.22.0
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* [PATCH v5 15/15] ASoC: sun4i-i2s: Adjust regmap settings
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
to reflect this.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index d3c8789f70bb..ecfc1ed79379 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -876,9 +876,11 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
{
/* Flush RX FIFO */
+ regcache_cache_bypass(i2s->regmap, true);
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
+ regcache_cache_bypass(i2s->regmap, false);
/* Clear RX counter */
regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
@@ -897,9 +899,11 @@ static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
{
/* Flush TX FIFO */
+ regcache_cache_bypass(i2s->regmap, true);
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
+ regcache_cache_bypass(i2s->regmap, false);
/* Clear TX counter */
regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
@@ -1053,13 +1057,7 @@ static const struct snd_soc_component_driver sun4i_i2s_component = {
static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
{
- switch (reg) {
- case SUN4I_I2S_FIFO_TX_REG:
- return false;
-
- default:
- return true;
- }
+ return true;
}
static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
@@ -1078,6 +1076,8 @@ static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SUN4I_I2S_FIFO_RX_REG:
+ case SUN4I_I2S_FIFO_TX_REG:
+ case SUN4I_I2S_FIFO_STA_REG:
case SUN4I_I2S_INT_STA_REG:
case SUN4I_I2S_RX_CNT_REG:
case SUN4I_I2S_TX_CNT_REG:
@@ -1088,23 +1088,12 @@ static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
}
}
-static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
-{
- switch (reg) {
- case SUN8I_I2S_FIFO_TX_REG:
- return false;
-
- default:
- return true;
- }
-}
-
static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg == SUN8I_I2S_INT_STA_REG)
return true;
if (reg == SUN8I_I2S_FIFO_TX_REG)
- return false;
+ return true;
return sun4i_i2s_volatile_reg(dev, reg);
}
@@ -1175,7 +1164,7 @@ static const struct regmap_config sun8i_i2s_regmap_config = {
.reg_defaults = sun8i_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
.writeable_reg = sun4i_i2s_wr_reg,
- .readable_reg = sun8i_i2s_rd_reg,
+ .readable_reg = sun4i_i2s_rd_reg,
.volatile_reg = sun8i_i2s_volatile_reg,
};
@@ -1188,7 +1177,7 @@ static const struct regmap_config sun50i_i2s_regmap_config = {
.reg_defaults = sun50i_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sun50i_i2s_reg_defaults),
.writeable_reg = sun4i_i2s_wr_reg,
- .readable_reg = sun8i_i2s_rd_reg,
+ .readable_reg = sun4i_i2s_rd_reg,
.volatile_reg = sun8i_i2s_volatile_reg,
};
--
2.22.0
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* [PATCH v5 14/15] ASoc: sun4i-i2s: Add 20, 24 and 32 bit support
From: codekipper @ 2019-08-14 6:08 UTC (permalink / raw)
To: maxime.ripard, wens, linux-sunxi
Cc: alsa-devel, Marcus Cooper, lgirdwood, linux-kernel, be17068,
broonie, linux-arm-kernel
In-Reply-To: <20190814060854.26345-1-codekipper@gmail.com>
From: Marcus Cooper <codekipper@gmail.com>
Extend the functionality of the driver to include support of 20 and
24 bits per sample for the earlier SoCs.
Newer SoCs can also handle 32bit samples.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
---
sound/soc/sunxi/sun4i-i2s.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index a71969167053..d3c8789f70bb 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -690,6 +690,11 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
+ case 20:
+ case 24:
+ case 32:
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ break;
default:
dev_err(dai->dev, "Unsupported physical sample width: %d\n",
params_physical_width(params));
@@ -1015,6 +1020,13 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
return 0;
}
+#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+#define SUN8I_FORMATS (SUN4I_FORMATS | \
+ SNDRV_PCM_FMTBIT_S32_LE)
+
static struct snd_soc_dai_driver sun4i_i2s_dai = {
.probe = sun4i_i2s_dai_probe,
.capture = {
@@ -1022,14 +1034,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .formats = SUN4I_FORMATS,
},
.ops = &sun4i_i2s_dai_ops,
.symmetric_rates = 1,
@@ -1505,6 +1517,11 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
goto err_pm_disable;
}
+ if (i2s->variant->has_fmt_set_lrck_period) {
+ soc_dai->playback.formats = SUN8I_FORMATS;
+ soc_dai->capture.formats = SUN8I_FORMATS;
+ }
+
if (!of_property_read_u32(pdev->dev.of_node,
"allwinner,playback-channels", &val)) {
if (val >= 2 && val <= 8)
--
2.22.0
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* Re: [PATCH] ARM: dts: sunxi: Add mdio bus sub-node to GMAC
From: Maxime Ripard @ 2019-08-14 6:17 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-arm-kernel
In-Reply-To: <20190814042208.9646-1-wens@kernel.org>
[-- Attachment #1.1: Type: text/plain, Size: 1120 bytes --]
On Wed, Aug 14, 2019 at 12:22:08PM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The DWMAC binding never supported having the Ethernet PHY node as a
> direct child to the controller, nor did it support the "phy" property
> as a way to specify which Ethernet PHY to use. What seemed to work
> was simply the implementation ignoring the "phy" property and instead
> probing all addresses on the MDIO bus and using the first available
> one.
>
> The recent switch from "phy" to "phy-handle" breaks the assumptions
> of the implementation, and does not match what the binding requires.
> The binding requires that if an MDIO bus is described, it shall be
> a sub-node with the "snps,dwmac-mdio" compatible string.
>
> Add a device node for the MDIO bus, and move the Ethernet PHY node
> under it. Also fix up the #address-cells and #size-cells properties
> where needed.
>
> Fixes: de332de26d19 ("ARM: dts: sunxi: Switch from phy to phy-handle")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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* Regression in Linux next with show wakeup sources stats in sysfs
From: Tony Lindgren @ 2019-08-14 6:38 UTC (permalink / raw)
To: Tri Vo, Greg Kroah-Hartman, Stephen Boyd, Kalesh Singh,
Rafael J. Wysocki
Cc: linux-omap, linux-kernel, linux-arm-kernel, linux-pm
Hi all,
Looks like commit 986845e747af ("PM / wakeup: Show wakeup sources stats
in sysfs") has caused a regression in Linux next where I can now get
some errors like this during the boot:
kobject_add_internal failed for wakeup10 (error: -2 parent: usb)
Any ideas why this might be happening? Maybe some deferred probe
related issue?
Regards,
Tony
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* Re: Regression in Linux next with show wakeup sources stats in sysfs
From: Stephen Boyd @ 2019-08-14 7:08 UTC (permalink / raw)
To: Rafael J. Wysocki, Greg Kroah-Hartman, Kalesh Singh,
Tony Lindgren, Tri Vo
Cc: linux-omap, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190814063803.GY52127@atomide.com>
Quoting Tony Lindgren (2019-08-13 23:38:03)
> Hi all,
>
> Looks like commit 986845e747af ("PM / wakeup: Show wakeup sources stats
> in sysfs") has caused a regression in Linux next where I can now get
> some errors like this during the boot:
>
> kobject_add_internal failed for wakeup10 (error: -2 parent: usb)
>
> Any ideas why this might be happening? Maybe some deferred probe
> related issue?
>
Yeah! Take a look at this thread[1] and please test out patches I'm
throwing out there like a total cowboy(d).
[1] https://lkml.kernel.org/r/1565731976.8572.16.camel@lca.pw
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* [PATCH v1 1/4] arm64: dts: ls1028a-rdb: enable emmc hs400 mode
From: Yinbo Zhu @ 2019-08-14 7:26 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Adrian Hunter, Ulf Hansson, Li Yang, Claudiu Manoil, Amit Jain,
Yangbo Lu, Vabhav Sharma, Rajesh Bhagat, Ashish Kumar, devicetree,
linux-arm-kernel, linux-kernel, linux-mmc
Cc: Alison Wang, Alex Marginean, xiaobo.xie, Catalin Horghidan,
Rajat Srivastava, jiafei.pan, linuxppc-dev, yinbo.zhu
This patch is to enable emmc hs400 mode for ls1028ardb
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 8a725409e881..f1e46cc4cea1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -92,8 +92,10 @@
};
&esdhc1 {
- status = "okay";
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
};
&i2c0 {
--
2.17.1
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* [PATCH v1 2/4] soc: fsl: guts: Add definition for LS1028A
From: Yinbo Zhu @ 2019-08-14 7:26 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Adrian Hunter, Ulf Hansson, Li Yang, Claudiu Manoil, Amit Jain,
Yangbo Lu, Vabhav Sharma, Rajesh Bhagat, Ashish Kumar, devicetree,
linux-arm-kernel, linux-kernel, linux-mmc
Cc: Alison Wang, Alex Marginean, xiaobo.xie, Catalin Horghidan,
Rajat Srivastava, jiafei.pan, linuxppc-dev, yinbo.zhu
In-Reply-To: <20190814072649.8237-1-yinbo.zhu@nxp.com>
Adding compatible string "ls1028a-dcfg" to initialize guts driver
for ls1028 and SoC die attribute definition for LS1028A
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
drivers/soc/fsl/guts.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 1ef8068c8dd3..34810f9bb2ee 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -102,6 +102,11 @@ static const struct fsl_soc_die_attr fsl_soc_die[] = {
.svr = 0x87360000,
.mask = 0xff3f0000,
},
+ /* Die: LS1028A, SoC: LS1028A */
+ { .die = "LS1028A",
+ .svr = 0x870b0000,
+ .mask = 0xff3f0000,
+ },
{ },
};
@@ -224,6 +229,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
{ .compatible = "fsl,lx2160a-dcfg", },
+ { .compatible = "fsl,ls1028a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
--
2.17.1
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* [PATCH v1 3/4] arm64: dts: ls1028a: fix little-big endian issue for dcfg
From: Yinbo Zhu @ 2019-08-14 7:26 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Adrian Hunter, Ulf Hansson, Li Yang, Claudiu Manoil, Amit Jain,
Yangbo Lu, Vabhav Sharma, Rajesh Bhagat, Ashish Kumar, devicetree,
linux-arm-kernel, linux-kernel, linux-mmc
Cc: Alison Wang, Alex Marginean, xiaobo.xie, Catalin Horghidan,
Rajat Srivastava, jiafei.pan, linuxppc-dev, yinbo.zhu
In-Reply-To: <20190814072649.8237-1-yinbo.zhu@nxp.com>
dcfg use little endian that SoC register value will be correct
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b0d4f8916ede..5538e8e354b2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -162,7 +162,7 @@
dcfg: syscon@1e00000 {
compatible = "fsl,ls1028a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>;
- big-endian;
+ little-endian;
};
scfg: syscon@1fc0000 {
--
2.17.1
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* [PATCH v1 4/4] mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoC
From: Yinbo Zhu @ 2019-08-14 7:26 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Adrian Hunter, Ulf Hansson, Li Yang, Claudiu Manoil, Amit Jain,
Yangbo Lu, Vabhav Sharma, Rajesh Bhagat, Ashish Kumar, devicetree,
linux-arm-kernel, linux-kernel, linux-mmc
Cc: Alison Wang, Alex Marginean, xiaobo.xie, Catalin Horghidan,
Rajat Srivastava, jiafei.pan, linuxppc-dev, yinbo.zhu
In-Reply-To: <20190814072649.8237-1-yinbo.zhu@nxp.com>
This patch is to add erratum A011334 support in ls1028a 1.0 SoC
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
drivers/mmc/host/sdhci-of-esdhc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index b16f7d440f78..eb2b290447fc 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1006,6 +1006,7 @@ static struct soc_device_attribute soc_incorrect_hostver[] = {
static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
{ .family = "QorIQ LX2160A", .revision = "1.0", },
{ .family = "QorIQ LX2160A", .revision = "2.0", },
+ { .family = "QorIQ LS1028A", .revision = "1.0", },
{ },
};
--
2.17.1
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* Re: Regression in Linux next with show wakeup sources stats in sysfs
From: Tony Lindgren @ 2019-08-14 7:32 UTC (permalink / raw)
To: Stephen Boyd
Cc: Tri Vo, linux-pm, Greg Kroah-Hartman, Rafael J. Wysocki,
linux-kernel, Sebastian Reichel, Kalesh Singh, linux-omap,
linux-arm-kernel
In-Reply-To: <5d53b378.1c69fb81.31b2e.5077@mx.google.com>
* Stephen Boyd <swboyd@chromium.org> [190814 07:09]:
> Quoting Tony Lindgren (2019-08-13 23:38:03)
> > Hi all,
> >
> > Looks like commit 986845e747af ("PM / wakeup: Show wakeup sources stats
> > in sysfs") has caused a regression in Linux next where I can now get
> > some errors like this during the boot:
> >
> > kobject_add_internal failed for wakeup10 (error: -2 parent: usb)
> >
> > Any ideas why this might be happening? Maybe some deferred probe
> > related issue?
> >
>
> Yeah! Take a look at this thread[1] and please test out patches I'm
> throwing out there like a total cowboy(d).
>
> [1] https://lkml.kernel.org/r/1565731976.8572.16.camel@lca.pw
Oh OK thanks, looks like I'm a bit behind then. My test case turned
out to be caused by device_init_wakeup() called before device_add() for
power_supply in case that helps. In that case create_dir() will fail
for kobject_add_internal(). Doing something like below fixes the
issue, but seems like we probably have other similar issues as well.
Adding Sebastian to Cc in case this might be a real problem despite
the other issues.
Regards,
Tony
8< -----------------------
diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c
--- a/drivers/power/supply/power_supply_core.c
+++ b/drivers/power/supply/power_supply_core.c
@@ -1051,14 +1051,14 @@ __power_supply_register(struct device *parent,
}
spin_lock_init(&psy->changed_lock);
- rc = device_init_wakeup(dev, ws);
- if (rc)
- goto wakeup_init_failed;
-
rc = device_add(dev);
if (rc)
goto device_add_failed;
+ rc = device_init_wakeup(dev, ws);
+ if (rc)
+ goto wakeup_init_failed;
+
rc = psy_register_thermal(psy);
if (rc)
goto register_thermal_failed;
@@ -1100,9 +1100,9 @@ __power_supply_register(struct device *parent,
register_cooler_failed:
psy_unregister_thermal(psy);
register_thermal_failed:
+wakeup_init_failed:
device_del(dev);
device_add_failed:
-wakeup_init_failed:
check_supplies_failed:
dev_set_name_failed:
put_device(dev);
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* Re: [PATCH] soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain
From: Michal Simek @ 2019-08-14 7:32 UTC (permalink / raw)
To: Jolly Shah, matthias.bgg, andy.gross, shawnguo, geert+renesas,
bjorn.andersson, sean.wang, m.szyprowski, michal.simek
Cc: Tejas Patel, Jolly Shah, rajanv, linux-kernel, linux-arm-kernel
In-Reply-To: <1565290836-18204-1-git-send-email-jolly.shah@xilinx.com>
On 08. 08. 19 21:00, Jolly Shah wrote:
> From: Tejas Patel <tejas.patel@xilinx.com>
>
> For "0" requirement which is used to inform firmware that
> device is not required currently by master, Versal LibPM disables
This could be the first time when LibPM is mentioned in connection to
Versal. That's why you should also say what's that and when it runs to
make it clear.
> clock, power it down and reset the device. genpd_power_off()
> is being called during runtime suspend also. So, if any device
> goes to runtime suspend state during resumes it needs to be
> re-initialized again. It is possible that drivers do not
> reinitialize device upon resume from runtime suspend every time.
>
> In LibPM new PM_CAP_UNUSABLE capability is added, which disables
> clock only and avoids power down and reset.
> So, set CAPABILITY_UNUSABLE requirement during zynqmp_gpd_power_off()
> if platform is other than zynqmp.
>
> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
> Signed-off-by: Jolly Shah <jollys@xilinx.com>
> ---
> drivers/soc/xilinx/zynqmp_pm_domains.c | 10 ++++++++--
> include/linux/firmware/xlnx-zynqmp.h | 3 ++-
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c
> index 600f57c..23d90cb 100644
> --- a/drivers/soc/xilinx/zynqmp_pm_domains.c
> +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c
> @@ -2,7 +2,7 @@
> /*
> * ZynqMP Generic PM domain support
> *
> - * Copyright (C) 2015-2018 Xilinx, Inc.
> + * Copyright (C) 2015-2019 Xilinx, Inc.
> *
> * Davorin Mista <davorin.mista@aggios.com>
> * Jolly Shah <jollys@xilinx.com>
> @@ -25,6 +25,8 @@
>
> static const struct zynqmp_eemi_ops *eemi_ops;
>
> +static int min_capability;
> +
> /**
> * struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
> * @gpd: Generic power domain
> @@ -106,7 +108,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain)
> int ret;
> struct pm_domain_data *pdd, *tmp;
> struct zynqmp_pm_domain *pd;
> - u32 capabilities = 0;
> + u32 capabilities = min_capability;
> bool may_wakeup;
>
> if (!eemi_ops->set_requirement)
> @@ -283,6 +285,10 @@ static int zynqmp_gpd_probe(struct platform_device *pdev)
> if (!domains)
> return -ENOMEM;
>
> + if (!of_device_is_compatible(dev->parent->of_node,
> + "xlnx,zynqmp-firmware"))
> + min_capability = ZYNQMP_PM_CAPABILITY_UNUSABLE;
> +
> for (i = 0; i < ZYNQMP_NUM_DOMAINS; i++, pd++) {
> pd->node_id = 0;
> pd->gpd.name = kasprintf(GFP_KERNEL, "domain%d", i);
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 778abbb..b8a7c22 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -2,7 +2,7 @@
> /*
> * Xilinx Zynq MPSoC Firmware layer
> *
> - * Copyright (C) 2014-2018 Xilinx
> + * Copyright (C) 2014-2019 Xilinx
> *
> * Michal Simek <michal.simek@xilinx.com>
> * Davorin Mista <davorin.mista@aggios.com>
> @@ -46,6 +46,7 @@
> #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
> #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
> #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
> +#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
Please align it with other macros (or fix that macros).
Other then two small nits patch is fine.
Thanks,
Michal
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* Re: [PATCH v2 0/2] ARM: zynq: smp improvements
From: Michal Simek @ 2019-08-14 7:40 UTC (permalink / raw)
To: Luis Araneda, linux, michal.simek; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <20190808125243.31046-1-luaraneda@gmail.com>
On 08. 08. 19 14:52, Luis Araneda wrote:
> This series adds support for kernel compiled in Thumb mode
> and fixes a kernel panic on smp bring-up when FORTIFY_SOURCE
> is enabled.
>
> The series started with the second patch as an RFC, and
> the first patch were suggested on the review to complement
> the fix.
>
> The changes were run-tested on a Digilent Zybo Z7 board
> ---
> Changes:
> v1 -> v2:
> - Reword commit messages to include related commits
> - Add Fixes tag to relevant commits
> - Add Cc to stable to relevant commits
>
>
> Luis Araneda (2):
> ARM: zynq: support smp in thumb mode
> ARM: zynq: Use memcpy_toio instead of memcpy on smp bring-up
>
> arch/arm/mach-zynq/headsmp.S | 2 ++
> arch/arm/mach-zynq/platsmp.c | 4 ++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
Applied both.
M
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* Re: [PATCH 14/22] ARM: omap1: use pci_ioremap_io() for omap_cf
From: Tony Lindgren @ 2019-08-14 7:49 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Aaro Koskinen, Greg Kroah-Hartman, Linus Walleij,
Bartlomiej Zolnierkiewicz, Linux Kernel Mailing List,
Dominik Brodowski, Tomi Valkeinen, linux-omap, Linux ARM
In-Reply-To: <CAK8P3a0LjKrc+7c5Ht9OL7LfYyLnG9=y7u+w24ujA1xAid_yCQ@mail.gmail.com>
* Arnd Bergmann <arnd@arndb.de> [190813 19:34]:
> On Tue, Aug 13, 2019 at 8:12 PM Aaro Koskinen <aaro.koskinen@iki.fi> wrote:
> > On Tue, Aug 13, 2019 at 01:02:16PM +0200, Arnd Bergmann wrote:
> > > On Tue, Aug 13, 2019 at 12:36 PM Tony Lindgren <tony@atomide.com> wrote:
> >
> > > - I force CONFIG_PCI to be enabled here in order to keep the
> > > asm/io.h logic unchanged. If PCI support in itself is an issue,
> > > then turning on CONFIG_PCI without the rest of this patch
> > > should also break.
> >
> > The board dies early, probably in pci_reserve_io():
> >
> > Starting kernel ...
> >
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Linux version 5.3.0-rc4-osk-los_80efa+-00028-g09f6f22a63e9 (aaro@amd-fx-6350) (gcc version 8.3.0 (GCC)) #1 Tue Aug 13 20:50:11 EEST 2019
> > [ 0.000000] CPU: ARM926EJ-S [41069263] revision 3 (ARMv5TEJ), cr=0005317f
> > [ 0.000000] CPU: VIVT data cache, VIVT instruction cache
> > [ 0.000000] Machine: TI-OSK
> > [ 0.000000] Ignoring tag cmdline (using the default kernel command line)
> > [ 0.000000] printk: bootconsole [earlycon0] enabled
> > [ 0.000000] Memory policy: Data cache writeback
> > [ 0.000000] Internal error: Oops - undefined instruction: 0 [#1] ARM
> > [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.3.0-rc4-osk-los_80efa+-00028-g09f6f22a63e9 #1
> > [ 0.000000] Hardware name: TI-OSK
> > [ 0.000000] PC is at vm_area_add_early+0x1c/0x74
>
> That sounds like an address conflict in the virtual addres space.
>
> In multiplatform kernels, PCI I/O space is hardwired to addresses
> 0xfee00000-0xfeffffff,
> which happened to be available on all the other machines that needed it so far.
>
> OMAP1_IO_VIRT is 0xfefb0000-0xfefeffff, which clearly overlaps with the end of
> the PCI I/O area.
>
> We only really need 4KB of I/O space rather than the full 2MB, but it
> would also be
> good not to make this too machine specific.
>
> Could we change OMAP1_IO_OFFSET to stay out of that area? Something like
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 97c114c1ef80..3b66d203dc98 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -1794,9 +1794,9 @@ config DEBUG_UART_VIRT
> default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
> default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
> default 0xfef36000 if DEBUG_HIGHBANK_UART
> - default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
> - default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
> - default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
> + default 0xff000000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
> + default 0xff000800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
> + default 0xff009800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
> default 0xff003000 if DEBUG_U300_UART
> default 0xffd01000 if DEBUG_HIP01_UART
> default DEBUG_UART_PHYS if !MMU
> diff --git a/arch/arm/mach-omap1/hardware.h b/arch/arm/mach-omap1/hardware.h
> index 232b8deef907..9fc76a3c9e57 100644
> --- a/arch/arm/mach-omap1/hardware.h
> +++ b/arch/arm/mach-omap1/hardware.h
> @@ -61,7 +61,7 @@ static inline u32 omap_cs3_phys(void)
>
> #endif /* ifndef __ASSEMBLER__ */
>
> -#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO
> = 0xfefb0000 */
> +#define OMAP1_IO_OFFSET 0x00fb0000 /* Virtual IO
> = 0xff000000 */
> #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
>
> #include "serial.h"
Oh OK yeah sounds like that's the issue.
> There may be additional locations that hardcode the virtual address.
Those should be in mach-omap1/io.c, and I recall innovator had some
hardcoded fpga address that should also be checked.
Regards,
Tony
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