* [PATCH v3 5/5] Documentation: arm64: Document PMU counters access from userspace
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
In-Reply-To: <20190816125934.18509-1-raphael.gault@arm.com>
Add a documentation file to describe the access to the pmu hardware
counters from userspace
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
.../arm64/pmu_counter_user_access.txt | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/arm64/pmu_counter_user_access.txt
diff --git a/Documentation/arm64/pmu_counter_user_access.txt b/Documentation/arm64/pmu_counter_user_access.txt
new file mode 100644
index 000000000000..6788b1107381
--- /dev/null
+++ b/Documentation/arm64/pmu_counter_user_access.txt
@@ -0,0 +1,42 @@
+Access to PMU hardware counter from userspace
+=============================================
+
+Overview
+--------
+The perf user-space tool relies on the PMU to monitor events. It offers an
+abstraction layer over the hardware counters since the underlying
+implementation is cpu-dependent.
+Arm64 allows userspace tools to have access to the registers storing the
+hardware counters' values directly.
+
+This targets specifically self-monitoring tasks in order to reduce the overhead
+by directly accessing the registers without having to go through the kernel.
+
+How-to
+------
+The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu
+registers is enable and that the userspace have access to the relevent
+information in order to use them.
+
+In order to have access to the hardware counter it is necessary to open the event
+using the perf tool interface: the sys_perf_event_open syscall returns a fd which
+can subsequently be used with the mmap syscall in order to retrieve a page of memory
+containing information about the event.
+The PMU driver uses this page to expose to the user the hardware counter's
+index. Using this index enables the user to access the PMU registers using the
+`mrs` instruction.
+
+Have a look `at tools/perf/arch/arm64/tests/user-events.c` for an example. It can be
+run using the perf tool to check that the access to the registers works
+correctly from userspace:
+
+./perf test -v
+
+About chained events
+--------------------
+When the user requests for an event to be counted on 64 bits, two hardware
+counters are used and need to be combined to retrieve the correct value:
+
+val = read_counter(idx);
+if ((event.attr.config1 & 0x1))
+ val = (val << 32) | read_counter(idx - 1);
--
2.17.1
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* [PATCH v3 4/5] arm64: perf: Enable pmu counter direct access for perf event on armv8
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
In-Reply-To: <20190816125934.18509-1-raphael.gault@arm.com>
Keep track of event opened with direct access to the hardware counters
and modify permissions while they are open.
The strategy used here is the same which x86 uses: everytime an event
is mapped, the permissions are set if required. The atomic field added
in the mm_context helps keep track of the different event opened and
de-activate the permissions when all are unmapped.
We also need to update the permissions in the context switch code so
that tasks keep the right permissions.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/include/asm/mmu.h | 6 +++++
arch/arm64/include/asm/mmu_context.h | 2 ++
arch/arm64/include/asm/perf_event.h | 14 ++++++++++
drivers/perf/arm_pmu.c | 38 ++++++++++++++++++++++++++++
4 files changed, 60 insertions(+)
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index fd6161336653..88ed4466bd06 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -18,6 +18,12 @@
typedef struct {
atomic64_t id;
+
+ /*
+ * non-zero if userspace have access to hardware
+ * counters directly.
+ */
+ atomic_t pmu_direct_access;
void *vdso;
unsigned long flags;
} mm_context_t;
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 7ed0adb187a8..6e66ff940494 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -21,6 +21,7 @@
#include <asm-generic/mm_hooks.h>
#include <asm/cputype.h>
#include <asm/pgtable.h>
+#include <asm/perf_event.h>
#include <asm/sysreg.h>
#include <asm/tlbflush.h>
@@ -224,6 +225,7 @@ static inline void __switch_mm(struct mm_struct *next)
}
check_and_switch_context(next, cpu);
+ perf_switch_user_access(next);
}
static inline void
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index 2bdbc79bbd01..ba58fa726631 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -8,6 +8,7 @@
#include <asm/stack_pointer.h>
#include <asm/ptrace.h>
+#include <linux/mm_types.h>
#define ARMV8_PMU_MAX_COUNTERS 32
#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
@@ -223,4 +224,17 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
(regs)->pstate = PSR_MODE_EL1h; \
}
+static inline void perf_switch_user_access(struct mm_struct *mm)
+{
+ if (!IS_ENABLED(CONFIG_PERF_EVENTS))
+ return;
+
+ if (atomic_read(&mm->context.pmu_direct_access)) {
+ write_sysreg(ARMV8_PMU_USERENR_ER|ARMV8_PMU_USERENR_CR,
+ pmuserenr_el0);
+ } else {
+ write_sysreg(0, pmuserenr_el0);
+ }
+}
+
#endif
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index df352b334ea7..3a48cc9f17af 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -25,6 +25,7 @@
#include <linux/irqdesc.h>
#include <asm/irq_regs.h>
+#include <asm/mmu_context.h>
static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
static DEFINE_PER_CPU(int, cpu_irq);
@@ -778,6 +779,41 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
&cpu_pmu->node);
}
+static void refresh_pmuserenr(void *mm)
+{
+ perf_switch_user_access(mm);
+}
+
+static void armpmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
+{
+ if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
+ return;
+
+ /*
+ * This function relies on not being called concurrently in two
+ * tasks in the same mm. Otherwise one task could observe
+ * pmu_direct_access > 1 and return all the way back to
+ * userspace with user access disabled while another task is still
+ * doing on_each_cpu_mask() to enable user access.
+ *
+ * For now, this can't happen because all callers hold mmap_sem
+ * for write. If this changes, we'll need a different solution.
+ */
+ lockdep_assert_held_write(&mm->mmap_sem);
+
+ if (atomic_inc_return(&mm->context.pmu_direct_access) == 1)
+ on_each_cpu(refresh_pmuserenr, mm, 1);
+}
+
+static void armpmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
+{
+ if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
+ return;
+
+ if (atomic_dec_and_test(&mm->context.pmu_direct_access))
+ on_each_cpu_mask(mm_cpumask(mm), refresh_pmuserenr, NULL, 1);
+}
+
static struct arm_pmu *__armpmu_alloc(gfp_t flags)
{
struct arm_pmu *pmu;
@@ -799,6 +835,8 @@ static struct arm_pmu *__armpmu_alloc(gfp_t flags)
.pmu_enable = armpmu_enable,
.pmu_disable = armpmu_disable,
.event_init = armpmu_event_init,
+ .event_mapped = armpmu_event_mapped,
+ .event_unmapped = armpmu_event_unmapped,
.add = armpmu_add,
.del = armpmu_del,
.start = armpmu_start,
--
2.17.1
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* [PATCH v3 3/5] arm64: pmu: Add function implementation to update event index in userpage.
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
In-Reply-To: <20190816125934.18509-1-raphael.gault@arm.com>
In order to be able to access the counter directly for userspace,
we need to provide the index of the counter using the userpage.
We thus need to override the event_idx function to retrieve and
convert the perf_event index to armv8 hardware index.
Since the arm_pmu driver can be used by any implementation, even
if not armv8, two components play a role into making sure the
behaviour is correct and consistent with the PMU capabilities:
* the ARMPMU_EL0_RD_CNTR flag which denotes the capability to access
counter from userspace.
* the event_idx call back, which is implemented and initialized by
the PMU implementation: if no callback is provided, the default
behaviour applies, returning 0 as index value.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/kernel/perf_event.c | 22 ++++++++++++++++++++++
include/linux/perf/arm_pmu.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index a0b4f1bca491..9fe3f6909513 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -818,6 +818,22 @@ static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
clear_bit(idx - 1, cpuc->used_mask);
}
+static int armv8pmu_access_event_idx(struct perf_event *event)
+{
+ if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
+ return 0;
+
+ /*
+ * We remap the cycle counter index to 32 to
+ * match the offset applied to the rest of
+ * the counter indeces.
+ */
+ if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
+ return 32;
+
+ return event->hw.idx;
+}
+
/*
* Add an event filter to a given event.
*/
@@ -911,6 +927,9 @@ static int __armv8_pmuv3_map_event(struct perf_event *event,
if (armv8pmu_event_is_64bit(event))
event->hw.flags |= ARMPMU_EVT_64BIT;
+ if (!cpus_have_const_cap(ARM64_HAS_HETEROGENEOUS_PMU))
+ event->hw.flags |= ARMPMU_EL0_RD_CNTR;
+
/* Only expose micro/arch events supported by this PMU */
if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
&& test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
@@ -1031,6 +1050,8 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
cpu_pmu->filter_match = armv8pmu_filter_match;
+ cpu_pmu->pmu.event_idx = armv8pmu_access_event_idx;
+
return 0;
}
@@ -1209,6 +1230,7 @@ void arch_perf_update_userpage(struct perf_event *event,
*/
freq = arch_timer_get_rate();
userpg->cap_user_time = 1;
+ userpg->cap_user_rdpmc = !!(event->hw.flags & ARMPMU_EL0_RD_CNTR);
clocks_calc_mult_shift(&userpg->time_mult, &shift, freq,
NSEC_PER_SEC, 0);
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 71f525a35ac2..1106a9ac00fd 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -26,6 +26,8 @@
*/
/* Event uses a 64bit counter */
#define ARMPMU_EVT_64BIT 1
+/* Allow access to hardware counter from userspace */
+#define ARMPMU_EL0_RD_CNTR 2
#define HW_OP_UNSUPPORTED 0xFFFF
#define C(_x) PERF_COUNT_HW_CACHE_##_x
--
2.17.1
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* [PATCH v3 2/5] arm64: cpufeature: Add feature to detect heterogeneous systems
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
In-Reply-To: <20190816125934.18509-1-raphael.gault@arm.com>
This feature is required in order to enable PMU counters direct
access from userspace only when the system is homogeneous.
This feature checks the model of each CPU brought online and compares it
to the boot CPU. If it differs then it is heterogeneous.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpufeature.c | 20 ++++++++++++++++++++
arch/arm64/kernel/perf_event.c | 1 +
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index f19fe4b9acc4..040370af38ad 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -52,7 +52,8 @@
#define ARM64_HAS_IRQ_PRIO_MASKING 42
#define ARM64_HAS_DCPODP 43
#define ARM64_WORKAROUND_1463225 44
+#define ARM64_HAS_HETEROGENEOUS_PMU 45
-#define ARM64_NCAPS 45
+#define ARM64_NCAPS 46
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9323bcc40a58..bbdd809f12a6 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1260,6 +1260,15 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
}
#endif
+static bool has_heterogeneous_pmu(const struct arm64_cpu_capabilities *entry,
+ int scope)
+{
+ u32 model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
+ struct cpuinfo_arm64 *boot = &per_cpu(cpu_data, 0);
+
+ return (boot->reg_midr & MIDR_CPU_MODEL_MASK) != model;
+}
+
static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "GIC system register CPU interface",
@@ -1560,6 +1569,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.min_field_value = 1,
},
#endif
+ {
+ /*
+ * Detect whether the system is heterogeneous or
+ * homogeneous
+ */
+ .desc = "Detect whether we have heterogeneous CPUs",
+ .capability = ARM64_HAS_HETEROGENEOUS_PMU,
+ .type = ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU,
+ .matches = has_heterogeneous_pmu,
+ },
{},
};
@@ -1727,6 +1746,7 @@ static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
cap_set_elf_hwcap(hwcaps);
}
+
static void update_cpu_capabilities(u16 scope_mask)
{
int i;
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 2d3bdebdf6df..a0b4f1bca491 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -19,6 +19,7 @@
#include <linux/of.h>
#include <linux/perf/arm_pmu.h>
#include <linux/platform_device.h>
+#include <linux/smp.h>
/* ARMv8 Cortex-A53 specific event types. */
#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
--
2.17.1
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* [PATCH v3 1/5] perf: arm64: Add test to check userspace access to hardware counters.
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
In-Reply-To: <20190816125934.18509-1-raphael.gault@arm.com>
This test relies on the fact that the PMU registers are accessible
from userspace. It then uses the perf_event_mmap_page to retrieve
the counter index and access the underlying register.
This test uses sched_setaffinity(2) in order to run on all CPU and thus
check the behaviour of the PMU of all cpus in a big.LITTLE environment.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/perf/arch/arm64/include/arch-tests.h | 7 +
tools/perf/arch/arm64/tests/Build | 1 +
tools/perf/arch/arm64/tests/arch-tests.c | 4 +
tools/perf/arch/arm64/tests/user-events.c | 254 +++++++++++++++++++++
4 files changed, 266 insertions(+)
create mode 100644 tools/perf/arch/arm64/tests/user-events.c
diff --git a/tools/perf/arch/arm64/include/arch-tests.h b/tools/perf/arch/arm64/include/arch-tests.h
index 90ec4c8cb880..6a8483de1015 100644
--- a/tools/perf/arch/arm64/include/arch-tests.h
+++ b/tools/perf/arch/arm64/include/arch-tests.h
@@ -2,11 +2,18 @@
#ifndef ARCH_TESTS_H
#define ARCH_TESTS_H
+#include <linux/compiler.h>
+
#ifdef HAVE_DWARF_UNWIND_SUPPORT
struct thread;
struct perf_sample;
+int test__arch_unwind_sample(struct perf_sample *sample,
+ struct thread *thread);
#endif
extern struct test arch_tests[];
+int test__rd_pmevcntr(struct test *test __maybe_unused,
+ int subtest __maybe_unused);
+
#endif
diff --git a/tools/perf/arch/arm64/tests/Build b/tools/perf/arch/arm64/tests/Build
index a61c06bdb757..3f9a20c17fc6 100644
--- a/tools/perf/arch/arm64/tests/Build
+++ b/tools/perf/arch/arm64/tests/Build
@@ -1,4 +1,5 @@
perf-y += regs_load.o
perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
+perf-y += user-events.o
perf-y += arch-tests.o
diff --git a/tools/perf/arch/arm64/tests/arch-tests.c b/tools/perf/arch/arm64/tests/arch-tests.c
index 5b1543c98022..57df9b89dede 100644
--- a/tools/perf/arch/arm64/tests/arch-tests.c
+++ b/tools/perf/arch/arm64/tests/arch-tests.c
@@ -10,6 +10,10 @@ struct test arch_tests[] = {
.func = test__dwarf_unwind,
},
#endif
+ {
+ .desc = "User counter access",
+ .func = test__rd_pmevcntr,
+ },
{
.func = NULL,
},
diff --git a/tools/perf/arch/arm64/tests/user-events.c b/tools/perf/arch/arm64/tests/user-events.c
new file mode 100644
index 000000000000..b048d7e392bc
--- /dev/null
+++ b/tools/perf/arch/arm64/tests/user-events.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <asm/bug.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sched.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include <sys/sysinfo.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <linux/types.h>
+#include "perf.h"
+#include "debug.h"
+#include "tests/tests.h"
+#include "cloexec.h"
+#include "util.h"
+#include "arch-tests.h"
+
+/*
+ * ARMv8 ARM reserves the following encoding for system registers:
+ * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
+ * C5.2, version:ARM DDI 0487A.f)
+ * [20-19] : Op0
+ * [18-16] : Op1
+ * [15-12] : CRn
+ * [11-8] : CRm
+ * [7-5] : Op2
+ */
+#define Op0_shift 19
+#define Op0_mask 0x3
+#define Op1_shift 16
+#define Op1_mask 0x7
+#define CRn_shift 12
+#define CRn_mask 0xf
+#define CRm_shift 8
+#define CRm_mask 0xf
+#define Op2_shift 5
+#define Op2_mask 0x7
+
+#define __stringify(x) #x
+
+#define read_sysreg(r) ({ \
+ u64 __val; \
+ asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
+ __val; \
+})
+
+#define PMEVCNTR_READ_CASE(idx) \
+ case idx: \
+ return read_sysreg(pmevcntr##idx##_el0)
+
+#define PMEVCNTR_CASES(readwrite) \
+ PMEVCNTR_READ_CASE(0); \
+ PMEVCNTR_READ_CASE(1); \
+ PMEVCNTR_READ_CASE(2); \
+ PMEVCNTR_READ_CASE(3); \
+ PMEVCNTR_READ_CASE(4); \
+ PMEVCNTR_READ_CASE(5); \
+ PMEVCNTR_READ_CASE(6); \
+ PMEVCNTR_READ_CASE(7); \
+ PMEVCNTR_READ_CASE(8); \
+ PMEVCNTR_READ_CASE(9); \
+ PMEVCNTR_READ_CASE(10); \
+ PMEVCNTR_READ_CASE(11); \
+ PMEVCNTR_READ_CASE(12); \
+ PMEVCNTR_READ_CASE(13); \
+ PMEVCNTR_READ_CASE(14); \
+ PMEVCNTR_READ_CASE(15); \
+ PMEVCNTR_READ_CASE(16); \
+ PMEVCNTR_READ_CASE(17); \
+ PMEVCNTR_READ_CASE(18); \
+ PMEVCNTR_READ_CASE(19); \
+ PMEVCNTR_READ_CASE(20); \
+ PMEVCNTR_READ_CASE(21); \
+ PMEVCNTR_READ_CASE(22); \
+ PMEVCNTR_READ_CASE(23); \
+ PMEVCNTR_READ_CASE(24); \
+ PMEVCNTR_READ_CASE(25); \
+ PMEVCNTR_READ_CASE(26); \
+ PMEVCNTR_READ_CASE(27); \
+ PMEVCNTR_READ_CASE(28); \
+ PMEVCNTR_READ_CASE(29); \
+ PMEVCNTR_READ_CASE(30)
+
+/*
+ * Read a value direct from PMEVCNTR<idx>
+ */
+static u64 read_evcnt_direct(int idx)
+{
+ switch (idx) {
+ PMEVCNTR_CASES(READ);
+ default:
+ WARN_ON(1);
+ }
+
+ return 0;
+}
+
+static u64 mmap_read_self(void *addr)
+{
+ struct perf_event_mmap_page *pc = addr;
+ u32 seq, idx, time_mult = 0, time_shift = 0;
+ u64 count, cyc = 0, time_offset = 0, enabled, running, delta;
+
+ do {
+ seq = READ_ONCE(pc->lock);
+ barrier();
+
+ enabled = READ_ONCE(pc->time_enabled);
+ running = READ_ONCE(pc->time_running);
+
+ if (enabled != running) {
+ cyc = read_sysreg(cntvct_el0);
+ time_mult = READ_ONCE(pc->time_mult);
+ time_shift = READ_ONCE(pc->time_shift);
+ time_offset = READ_ONCE(pc->time_offset);
+ }
+
+ idx = READ_ONCE(pc->index);
+ count = READ_ONCE(pc->offset);
+ if (idx)
+ count += read_evcnt_direct(idx - 1);
+
+ barrier();
+ } while (READ_ONCE(pc->lock) != seq);
+
+ if (enabled != running) {
+ u64 quot, rem;
+
+ quot = (cyc >> time_shift);
+ rem = cyc & (((u64)1 << time_shift) - 1);
+ delta = time_offset + quot * time_mult +
+ ((rem * time_mult) >> time_shift);
+
+ enabled += delta;
+ if (idx)
+ running += delta;
+
+ quot = count / running;
+ rem = count % running;
+ count = quot * enabled + (rem * enabled) / running;
+ }
+
+ return count;
+}
+
+static int __test__rd_pmevcntr(void)
+{
+ volatile int tmp = 0;
+ u64 i, loops = 1000;
+ int n;
+ int fd;
+ void *addr;
+ struct perf_event_attr attr = {
+ .type = PERF_TYPE_HARDWARE,
+ .config = PERF_COUNT_HW_INSTRUCTIONS,
+ .exclude_kernel = 1,
+ };
+ u64 delta_sum = 0;
+ char sbuf[STRERR_BUFSIZE];
+
+ fd = sys_perf_event_open(&attr, 0, -1, -1,
+ perf_event_open_cloexec_flag());
+ if (fd < 0) {
+ pr_err("Error: sys_perf_event_open() syscall returned with %d (%s)\n", fd,
+ str_error_r(errno, sbuf, sizeof(sbuf)));
+ return -1;
+ }
+
+ addr = mmap(NULL, page_size, PROT_READ, MAP_SHARED, fd, 0);
+ if (addr == (void *)(-1)) {
+ pr_err("Error: mmap() syscall returned with (%s)\n",
+ str_error_r(errno, sbuf, sizeof(sbuf)));
+ goto out_close;
+ }
+
+ for (n = 0; n < 6; n++) {
+ u64 stamp, now, delta;
+
+ stamp = mmap_read_self(addr);
+
+ for (i = 0; i < loops; i++)
+ tmp++;
+
+ now = mmap_read_self(addr);
+ loops *= 10;
+
+ delta = now - stamp;
+ pr_debug("%14d: %14llu\n", n, (long long)delta);
+
+ delta_sum += delta;
+ }
+
+ munmap(addr, page_size);
+ pr_debug(" ");
+
+out_close:
+ close(fd);
+
+ if (!delta_sum)
+ return -1;
+
+ return 0;
+}
+
+int test__rd_pmevcntr(struct test __maybe_unused *test,
+ int __maybe_unused subtest)
+{
+ int status = 0;
+ int wret = 0;
+ int ret = 0;
+ int pid;
+ int cpu;
+ cpu_set_t cpu_set;
+
+ pid = fork();
+ if (pid < 0)
+ return -1;
+
+ if (!pid) {
+ for (cpu = 0; cpu < get_nprocs(); cpu++) {
+ pr_info("setting affinity to cpu: %d\n", cpu);
+ CPU_ZERO(&cpu_set);
+ CPU_SET(cpu, &cpu_set);
+ if (sched_setaffinity(getpid(),
+ sizeof(cpu_set),
+ &cpu_set) == -1) {
+ pr_err("Error: impossible to set cpu (%d) affinity\n",
+ cpu);
+ continue;
+ }
+ ret = __test__rd_pmevcntr();
+ }
+ exit(ret);
+ }
+
+ wret = waitpid(pid, &status, 0);
+ if (wret < 0)
+ return -1;
+
+ if (WIFSIGNALED(status)) {
+ pr_err("Error: the child process was interrupted by a signal\n");
+ return -1;
+ }
+
+ if (WIFEXITED(status) && WEXITSTATUS(status)) {
+ pr_err("Error: the child process exited with: %d\n",
+ WEXITSTATUS(status));
+ return -1;
+ }
+
+ return 0;
+}
--
2.17.1
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^ permalink raw reply related
* [PATCH v3 0/5] arm64: Enable access to pmu registers by user-space
From: Raphael Gault @ 2019-08-16 12:59 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, acme, Raphael Gault, mingo
Hi,
Changes since v2:
* Rebased on linux-next/master again (next-20190814)
* Use linux/compiler.h header as suggested by Arnaldo
The perf user-space tool relies on the PMU to monitor events. It offers an
abstraction layer over the hardware counters since the underlying
implementation is cpu-dependent. We want to allow userspace tools to have
access to the registers storing the hardware counters' values directly.
This targets specifically self-monitoring tasks in order to reduce the
overhead by directly accessing the registers without having to go
through the kernel.
In order to do this we need to setup the pmu so that it exposes its registers
to userspace access.
The first patch add a test to the perf tool so that we can test that the
access to the registers works correctly from userspace.
The second patch add a capability in the arm64 cpufeatures framework in
order to detect when we are running on a heterogeneous system.
The third patch focuses on the armv8 pmuv3 PMU support and makes sure that
the access to the pmu registers is enable and that the userspace have
access to the relevent information in order to use them.
The fourth patch put in place callbacks to enable access to the hardware
counters from userspace when a compatible event is opened using the perf
API.
The fifth patch adds a short documentation about PMU counters direct
access from userspace.
Raphael Gault (5):
perf: arm64: Add test to check userspace access to hardware counters.
arm64: cpufeature: Add feature to detect heterogeneous systems
arm64: pmu: Add function implementation to update event index in
userpage.
arm64: perf: Enable pmu counter direct access for perf event on armv8
Documentation: arm64: Document PMU counters access from userspace
.../arm64/pmu_counter_user_access.txt | 42 +++
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/mmu.h | 6 +
arch/arm64/include/asm/mmu_context.h | 2 +
arch/arm64/include/asm/perf_event.h | 14 +
arch/arm64/kernel/cpufeature.c | 20 ++
arch/arm64/kernel/perf_event.c | 23 ++
drivers/perf/arm_pmu.c | 38 +++
include/linux/perf/arm_pmu.h | 2 +
tools/perf/arch/arm64/include/arch-tests.h | 7 +
tools/perf/arch/arm64/tests/Build | 1 +
tools/perf/arch/arm64/tests/arch-tests.c | 4 +
tools/perf/arch/arm64/tests/user-events.c | 254 ++++++++++++++++++
13 files changed, 415 insertions(+), 1 deletion(-)
create mode 100644 Documentation/arm64/pmu_counter_user_access.txt
create mode 100644 tools/perf/arch/arm64/tests/user-events.c
--
2.17.1
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^ permalink raw reply
* Re: [PATCH v2] arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
From: Heiko Stuebner @ 2019-08-16 12:42 UTC (permalink / raw)
To: Andy Yan
Cc: devicetree, robh+dt, linux-kernel, linux-arm-kernel,
linux-rockchip
In-Reply-To: <20190805124037.10597-1-andyshrk@gmail.com>
Am Montag, 5. August 2019, 14:40:37 CEST schrieb Andy Yan:
> P710 is a RK3399 based SBC, designed by Leez [0].
>
> Specification
> - Rockchip RK3399
> - 4/2GB LPDDR4
> - TF sd scard slot
> - eMMC
> - M.2 B-Key for 4G LTE
> - AP6256 for WiFi + BT
> - Gigabit ethernet
> - HDMI out
> - 40 pin header
> - USB 2.0 x 2
> - USB 3.0 x 1
> - USB 3.0 Type-C x 1
> - TYPE-C Power supply
>
> [0]https://leez.lenovo.com
>
> Signed-off-by: Andy Yan <andyshrk@gmail.com>
applied for 5.4 - I did correct the alphabetical sorting a tiny bit though.
Thanks
Heiko
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^ permalink raw reply
* Re: [PATCH 01/10] PCI: designware-ep: Add multiple PFs support for DWC
From: Andrew Murray @ 2019-08-16 12:35 UTC (permalink / raw)
To: Xiaowei Bao
Cc: mark.rutland@arm.com, Roy Zang, lorenzo.pieralisi@arm.com,
arnd@arndb.de, gregkh@linuxfoundation.org, jingoohan1@gmail.com,
Z.q. Hou, linuxppc-dev@lists.ozlabs.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
kishon@ti.com, M.h. Lian, devicetree@vger.kernel.org,
gustavo.pimentel@synopsys.com, Leo Li, shawnguo@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <AM5PR04MB32997C516770A0555970330BF5AF0@AM5PR04MB3299.eurprd04.prod.outlook.com>
On Fri, Aug 16, 2019 at 11:00:01AM +0000, Xiaowei Bao wrote:
>
>
> > -----Original Message-----
> > From: Andrew Murray <andrew.murray@arm.com>
> > Sent: 2019年8月16日 17:45
> > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com;
> > mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> > <leoyang.li@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com;
> > arnd@arndb.de; gregkh@linuxfoundation.org; M.h. Lian
> > <minghuan.lian@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> > linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > linuxppc-dev@lists.ozlabs.org; Z.q. Hou <zhiqiang.hou@nxp.com>
> > Subject: Re: [PATCH 01/10] PCI: designware-ep: Add multiple PFs support for
> > DWC
> >
> > On Fri, Aug 16, 2019 at 02:55:41AM +0000, Xiaowei Bao wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Andrew Murray <andrew.murray@arm.com>
> > > > Sent: 2019年8月15日 19:32
> > > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com;
> > > > bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com;
> > > > lorenzo.pieralisi@arm.com; arnd@arndb.de;
> > > > gregkh@linuxfoundation.org; M.h. Lian <minghuan.lian@nxp.com>;
> > > > Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> > > > linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> > > > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > > linuxppc-dev@lists.ozlabs.org
> > > > Subject: Re: [PATCH 01/10] PCI: designware-ep: Add multiple PFs
> > > > support for DWC
> > > >
> > > > On Thu, Aug 15, 2019 at 04:37:07PM +0800, Xiaowei Bao wrote:
> > > > > Add multiple PFs support for DWC, different PF have different
> > > > > config space, we use pf-offset property which get from the DTS to
> > > > > access the different pF config space.
> > > >
> > > > Thanks for the patch. I haven't seen a cover letter for this series,
> > > > is there one missing?
> > > Maybe I miss, I will add you to review next time, thanks a lot for your
> > comments.
> > > >
> > > >
> > > > >
> > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > > ---
> > > > > drivers/pci/controller/dwc/pcie-designware-ep.c | 97
> > > > +++++++++++++---------
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 105
> > > > ++++++++++++++++++++++--
> > > > > drivers/pci/controller/dwc/pcie-designware.h | 10 ++-
> > > > > include/linux/pci-epc.h | 1 +
> > > > > 4 files changed, 164 insertions(+), 49 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > index 2bf5a35..75e2955 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > @@ -19,12 +19,14 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep
> > *ep)
> > > > > pci_epc_linkup(epc);
> > > > > }
> > > > >
> > > > > -static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum
> > > > > pci_barno
> > > > bar,
> > > > > - int flags)
> > > > > +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> > > > > + enum pci_barno bar, int flags)
> > > > > {
> > > > > u32 reg;
> > > > > + struct pci_epc *epc = pci->ep.epc;
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > >
> > > > > - reg = PCI_BASE_ADDRESS_0 + (4 * bar);
> > > > > + reg = pf_base + PCI_BASE_ADDRESS_0 + (4 * bar);
> > > >
> > > > I think I'd rather see this arithmetic (and the one for determining
> > > > pf_base) inside a macro or inline header function. This would make
> > > > this code more readable and reduce the chances of an error by avoiding
> > duplication of code.
> > > >
> > > > For example look at cdns_pcie_ep_fn_writeb and
> > > > ROCKCHIP_PCIE_EP_FUNC_BASE for examples of other EP drivers that do
> > > > this.
> > > Agree, this looks fine, thanks a lot for your comments, I will use
> > > this way to access the registers in next version patch.
> > > >
> > > >
> > > > > dw_pcie_dbi_ro_wr_en(pci);
> > > > > dw_pcie_writel_dbi2(pci, reg, 0x0);
> > > > > dw_pcie_writel_dbi(pci, reg, 0x0); @@ -37,7 +39,12 @@ static
> > > > > void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno
> > > > > bar,
> > > > >
> > > > > void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> > {
> > > > > - __dw_pcie_ep_reset_bar(pci, bar, 0);
> > > > > + u8 func_no, funcs;
> > > > > +
> > > > > + funcs = pci->ep.epc->max_functions;
> > > > > +
> > > > > + for (func_no = 0; func_no < funcs; func_no++)
> > > > > + __dw_pcie_ep_reset_bar(pci, func_no, bar, 0);
> > > > > }
> > > > >
> > > > > static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8
> > > > > cap_ptr, @@ -78,28 +85,29 @@ static int
> > > > > dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, {
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > >
> > > > > dw_pcie_dbi_ro_wr_en(pci);
> > > > > - dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
> > > > > - dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
> > > > > - dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
> > > > > - dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
> > > > > - dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
> > > > > + dw_pcie_writew_dbi(pci, pf_base + PCI_VENDOR_ID,
> > hdr->vendorid);
> > > > > + dw_pcie_writew_dbi(pci, pf_base + PCI_DEVICE_ID, hdr->deviceid);
> > > > > + dw_pcie_writeb_dbi(pci, pf_base + PCI_REVISION_ID, hdr->revid);
> > > > > + dw_pcie_writeb_dbi(pci, pf_base + PCI_CLASS_PROG,
> > hdr->progif_code);
> > > > > + dw_pcie_writew_dbi(pci, pf_base + PCI_CLASS_DEVICE,
> > > > > hdr->subclass_code | hdr->baseclass_code << 8);
> > > > > - dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
> > > > > + dw_pcie_writeb_dbi(pci, pf_base + PCI_CACHE_LINE_SIZE,
> > > > > hdr->cache_line_size);
> > > > > - dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
> > > > > + dw_pcie_writew_dbi(pci, pf_base + PCI_SUBSYSTEM_VENDOR_ID,
> > > > > hdr->subsys_vendor_id);
> > > > > - dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
> > > > > - dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
> > > > > + dw_pcie_writew_dbi(pci, pf_base + PCI_SUBSYSTEM_ID,
> > > > hdr->subsys_id);
> > > > > + dw_pcie_writeb_dbi(pci, pf_base + PCI_INTERRUPT_PIN,
> > > > > hdr->interrupt_pin);
> > > > > dw_pcie_dbi_ro_wr_dis(pci);
> > > > >
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum
> > > > pci_barno bar,
> > > > > - dma_addr_t cpu_addr,
> > > > > +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8
> > func_no,
> > > > > + enum pci_barno bar, dma_addr_t cpu_addr,
> > > > > enum dw_pcie_as_type as_type) {
> > > > > int ret;
> > > > > @@ -112,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct
> > > > dw_pcie_ep *ep, enum pci_barno bar,
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
> > > > > + ret = dw_pcie_prog_inbound_atu(pci, func_no, free_win, bar,
> > > > > +cpu_addr,
> > > > > as_type);
> > > > > if (ret < 0) {
> > > > > dev_err(pci->dev, "Failed to program IB window\n"); @@
> > -125,7
> > > > > +133,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep,
> > > > enum pci_barno bar,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > > > > phys_addr_t phys_addr,
> > > > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8
> > func_no,
> > > > > + phys_addr_t phys_addr,
> > > > > u64 pci_addr, size_t size) {
> > > > > u32 free_win;
> > > > > @@ -137,8 +146,8 @@ static int dw_pcie_ep_outbound_atu(struct
> > > > dw_pcie_ep *ep, phys_addr_t phys_addr,
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> > > > > - phys_addr, pci_addr, size);
> > > > > + dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win,
> > > > PCIE_ATU_TYPE_MEM,
> > > > > + phys_addr, pci_addr, size);
> > > > >
> > > > > set_bit(free_win, ep->ob_window_map);
> > > > > ep->outbound_addr[free_win] = phys_addr; @@ -154,7 +163,7
> > @@
> > > > static
> > > > > void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
> > > > > enum pci_barno bar = epf_bar->barno;
> > > > > u32 atu_index = ep->bar_to_atu[bar];
> > > > >
> > > > > - __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
> > > > > + __dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags);
> > > > >
> > > > > dw_pcie_disable_atu(pci, atu_index,
> > DW_PCIE_REGION_INBOUND);
> > > > > clear_bit(atu_index, ep->ib_window_map); @@ -170,14 +179,16
> > @@
> > > > > static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
> > > > > size_t size = epf_bar->size;
> > > > > int flags = epf_bar->flags;
> > > > > enum dw_pcie_as_type as_type;
> > > > > - u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > + u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar) + pf_base;
> > > > >
> > > > > if (!(flags & PCI_BASE_ADDRESS_SPACE))
> > > > > as_type = DW_PCIE_AS_MEM;
> > > > > else
> > > > > as_type = DW_PCIE_AS_IO;
> > > > >
> > > > > - ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr,
> > as_type);
> > > > > + ret = dw_pcie_ep_inbound_atu(ep, func_no, bar,
> > > > > + epf_bar->phys_addr, as_type);
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > @@ -235,7 +246,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc
> > > > *epc, u8 func_no,
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > >
> > > > > - ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
> > > > > + ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr,
> > > > > +size);
> > > > > if (ret) {
> > > > > dev_err(pci->dev, "Failed to enable address\n");
> > > > > return ret;
> > > > > @@ -248,12 +259,13 @@ static int dw_pcie_ep_get_msi(struct pci_epc
> > > > > *epc, u8 func_no) {
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u32 val, reg;
> > > > >
> > > > > if (!ep->msi_cap)
> > > > > return -EINVAL;
> > > > >
> > > > > - reg = ep->msi_cap + PCI_MSI_FLAGS;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_FLAGS;
> > > > > val = dw_pcie_readw_dbi(pci, reg);
> > > > > if (!(val & PCI_MSI_FLAGS_ENABLE))
> > > > > return -EINVAL;
> > > > > @@ -267,12 +279,13 @@ static int dw_pcie_ep_set_msi(struct pci_epc
> > > > > *epc, u8 func_no, u8 interrupts) {
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u32 val, reg;
> > > > >
> > > > > if (!ep->msi_cap)
> > > > > return -EINVAL;
> > > > >
> > > > > - reg = ep->msi_cap + PCI_MSI_FLAGS;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_FLAGS;
> > > > > val = dw_pcie_readw_dbi(pci, reg);
> > > > > val &= ~PCI_MSI_FLAGS_QMASK;
> > > > > val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; @@ -287,12
> > > > > +300,13 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8
> > func_no) {
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u32 val, reg;
> > > > >
> > > > > if (!ep->msix_cap)
> > > > > return -EINVAL;
> > > > >
> > > > > - reg = ep->msix_cap + PCI_MSIX_FLAGS;
> > > > > + reg = ep->msix_cap + pf_base + PCI_MSIX_FLAGS;
> > > > > val = dw_pcie_readw_dbi(pci, reg);
> > > > > if (!(val & PCI_MSIX_FLAGS_ENABLE))
> > > > > return -EINVAL;
> > > > > @@ -306,12 +320,13 @@ static int dw_pcie_ep_set_msix(struct
> > > > > pci_epc *epc, u8 func_no, u16 interrupts) {
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u32 val, reg;
> > > > >
> > > > > if (!ep->msix_cap)
> > > > > return -EINVAL;
> > > > >
> > > > > - reg = ep->msix_cap + PCI_MSIX_FLAGS;
> > > > > + reg = ep->msix_cap + pf_base + PCI_MSIX_FLAGS;
> > > > > val = dw_pcie_readw_dbi(pci, reg);
> > > > > val &= ~PCI_MSIX_FLAGS_QSIZE;
> > > > > val |= interrupts;
> > > > > @@ -400,6 +415,7 @@ int dw_pcie_ep_raise_msi_irq(struct
> > dw_pcie_ep
> > > > *ep, u8 func_no,
> > > > > unsigned int aligned_offset;
> > > > > u16 msg_ctrl, msg_data;
> > > > > u32 msg_addr_lower, msg_addr_upper, reg;
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u64 msg_addr;
> > > > > bool has_upper;
> > > > > int ret;
> > > > > @@ -408,19 +424,19 @@ int dw_pcie_ep_raise_msi_irq(struct
> > > > dw_pcie_ep *ep, u8 func_no,
> > > > > return -EINVAL;
> > > > >
> > > > > /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1.
> > */
> > > > > - reg = ep->msi_cap + PCI_MSI_FLAGS;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_FLAGS;
> > > > > msg_ctrl = dw_pcie_readw_dbi(pci, reg);
> > > > > has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
> > > > > - reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_ADDRESS_LO;
> > > > > msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
> > > > > if (has_upper) {
> > > > > - reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_ADDRESS_HI;
> > > > > msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
> > > > > - reg = ep->msi_cap + PCI_MSI_DATA_64;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_DATA_64;
> > > > > msg_data = dw_pcie_readw_dbi(pci, reg);
> > > > > } else {
> > > > > msg_addr_upper = 0;
> > > > > - reg = ep->msi_cap + PCI_MSI_DATA_32;
> > > > > + reg = ep->msi_cap + pf_base + PCI_MSI_DATA_32;
> > > > > msg_data = dw_pcie_readw_dbi(pci, reg);
> > > > > }
> > > > > aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
> > @@
> > > > > -439,7 +455,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep
> > > > > *ep,
> > > > > u8 func_no, }
> > > > >
> > > > > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > > > - u16 interrupt_num)
> > > > > + u16 interrupt_num)
> > > > > {
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > struct pci_epc *epc = ep->epc;
> > > > > @@ -447,16 +463,17 @@ int dw_pcie_ep_raise_msix_irq(struct
> > > > dw_pcie_ep *ep, u8 func_no,
> > > > > u32 bar_addr_upper, bar_addr_lower;
> > > > > u32 msg_addr_upper, msg_addr_lower;
> > > > > u32 reg, msg_data, vec_ctrl;
> > > > > + u32 pf_base = func_no * epc->pf_offset;
> > > > > u64 tbl_addr, msg_addr, reg_u64;
> > > > > void __iomem *msix_tbl;
> > > > > int ret;
> > > > >
> > > > > - reg = ep->msix_cap + PCI_MSIX_TABLE;
> > > > > + reg = ep->msix_cap + pf_base + PCI_MSIX_TABLE;
> > > > > tbl_offset = dw_pcie_readl_dbi(pci, reg);
> > > > > bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
> > > > > tbl_offset &= PCI_MSIX_TABLE_OFFSET;
> > > > >
> > > > > - reg = PCI_BASE_ADDRESS_0 + (4 * bir);
> > > > > + reg = PCI_BASE_ADDRESS_0 + pf_base + (4 * bir);
> > > > > bar_addr_upper = 0;
> > > > > bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
> > > > > reg_u64 = (bar_addr_lower &
> > PCI_BASE_ADDRESS_MEM_TYPE_MASK);
> > > > @@
> > > > > -592,13 +609,17 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > > > > ep->epc = epc;
> > > > > epc_set_drvdata(epc, ep);
> > > > >
> > > > > - if (ep->ops->ep_init)
> > > > > - ep->ops->ep_init(ep);
> > > > > -
> > > > > ret = of_property_read_u8(np, "max-functions",
> > &epc->max_functions);
> > > > > if (ret < 0)
> > > > > epc->max_functions = 1;
> > > > >
> > > > > + ret = of_property_read_u32(np, "pf-offset", &epc->pf_offset);
> > > > > + if (ret < 0)
> > > > > + epc->pf_offset = 0;
> > > >
> > > > Bad things will likely happen if max_functions > 1 and pf-offset isn't set.
> > > > I think the driver should bail in this situation. It would be very
> > > > easy for someone to misconfigure this.
> > > Yes, you are right, but if the max-functions have defined in DTS,
> > > require the pf-offset must define in DTS, I am not sure the correct
> > > value of pf-offsetfor other platforms, so I think the max-functions and
> > pf-offset should not have the dependence.
> >
> > Yes you're correct. I hadn't really thought about this beyond layerscape. It's
> > also possible that other hardware could support multiple PFs without relying
> > on an offset and perhaps employ some other mechanism to access different
> > functions. So whilst this property can be optional for the majority of dwc
> > controllers - it must be set and cannot be zero for layerscape.
> >
> > Perhaps inside ls_pcie_ep_init, you can set max_functions to 1 if pf_offset is
> > 0 and print a WARN to explain why? (Or ls_pcie_ep_init returns failure and
> > dw_pcie_ep_init checks it and bails).
> >
> > The assumption is being made here that future dw controllers may also use
> > pf_offset (is this likely?) - otherwise why is this in pcie-designware-ep.c and
> > not pci-layerscape-ep.c and why is this value not just hard-coded for lp?
>
> Thanks a lot for your detail comments, this give me a lot of help.
> Yes, I agree your point, and I will seriously consider a best way to fix this potential issue.
> Based on your experience, how do other platforms implement the multiple functions?
> The DWC core difference the different PF by signal "client0_tlp_func_num[(PF_WD-1):0]"
I don't know, though looking at the kernel drivers suggests that the
existing EP controllers have a large address space which contains multiple
PFs. They are accessed via macros (ROCKCHIP_PCIE_EP_FUNC_BASE(fn),
CDNS_PCIE_EP_FUNC_BASE(fn)). It would be possible, but probably not desirable
to have a smaller address space (window) and a register that selects which
function the window refers to. This is why I'm slight nervous of assuming
that a pf-offset will cover all future dw drivers - I may be wrong.
> >
> >
> > > even though I didn't define pf-offset when I defined max-functions,
> > > the pf-offset is 0, the DWC ep driver can continue run the progress of
> > > INIT but not return, of course, thus the PF1 will not work, I don't know which
> > way is better.
> Hi Andrew,
> > > >
> > > >
> > > > > +
> > > > > + if (ep->ops->ep_init)
> > > > > + ep->ops->ep_init(ep);
> > > > > +
> > > > > ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
> > > > > ep->page_size);
> > > > > if (ret < 0) {
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > index 7d25102..c99cee4 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > @@ -158,6 +158,43 @@ static void dw_pcie_writel_ob_unroll(struct
> > > > dw_pcie *pci, u32 index, u32 reg,
> > > > > dw_pcie_writel_atu(pci, offset + reg, val); }
> > > > >
> > > > > +static void dw_pcie_prog_ep_outbound_atu_unroll(struct dw_pcie
> > > > > +*pci, u8
> > > > func_no,
> > > > > + int index, int type,
> > > > > + u64 cpu_addr, u64 pci_addr,
> > > > > + u32 size)
> > > > > +{
> > > > > + u32 retries, val;
> > > > > +
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_LOWER_BASE,
> > > > > + lower_32_bits(cpu_addr));
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_UPPER_BASE,
> > > > > + upper_32_bits(cpu_addr));
> > > > > + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
> > > > > + lower_32_bits(cpu_addr + size - 1));
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_LOWER_TARGET,
> > > > > + lower_32_bits(pci_addr));
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_UPPER_TARGET,
> > > > > + upper_32_bits(pci_addr));
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_REGION_CTRL1,
> > > > > + type | PCIE_ATU_FUNC_NUM(func_no));
> > > >
> > > > With the exception of this line, the rest of this function is
> > > > identical to dw_pcie_prog_outbound_atu_unroll.
> > > Yes, I can integrate the same code, but I think we'd better use the
> > > different outbound window set function between RC and EP, because the RC
> > don't need the func_num parameter.
> >
> >
> >
> > > >
> > > > > + dw_pcie_writel_ob_unroll(pci, index,
> > PCIE_ATU_UNR_REGION_CTRL2,
> > > > > + PCIE_ATU_ENABLE);
> > > > > +
> > > > > + /*
> > > > > + * Make sure ATU enable takes effect before any subsequent config
> > > > > + * and I/O accesses.
> > > > > + */
> > > > > + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> > {
> > > > > + val = dw_pcie_readl_ob_unroll(pci, index,
> > > > > + PCIE_ATU_UNR_REGION_CTRL2);
> > > > > + if (val & PCIE_ATU_ENABLE)
> > > > > + return;
> > > > > +
> > > > > + mdelay(LINK_WAIT_IATU);
> > > > > + }
> > > > > + dev_err(pci->dev, "Outbound iATU is not being enabled\n"); }
> > > > > +
> > > > > static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci,
> > > > > int
> > > > index,
> > > > > int type, u64 cpu_addr,
> > > > > u64 pci_addr, u32 size) @@ -194,6
> > +231,51 @@ static
> > > > > void
> > > > dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
> > > > > dev_err(pci->dev, "Outbound iATU is not being enabled\n"); }
> > > > >
> > > > > +void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8
> > > > > +func_no, int
> > > > index,
> > > > > + int type, u64 cpu_addr, u64 pci_addr,
> > > > > + u32 size)
> > > > > +{
> > > > > + u32 retries, val;
> > > > > +
> > > > > + if (pci->ops->cpu_addr_fixup)
> > > > > + cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > > > > +
> > > > > + if (pci->iatu_unroll_enabled) {
> > > > > + dw_pcie_prog_ep_outbound_atu_unroll(pci, func_no, index,
> > type,
> > > > > + cpu_addr, pci_addr, size);
> > > > > + return;
> > > > > + }
> > > > > +
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
> > > > > + PCIE_ATU_REGION_OUTBOUND | index);
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
> > > > > + lower_32_bits(cpu_addr));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
> > > > > + upper_32_bits(cpu_addr));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
> > > > > + lower_32_bits(cpu_addr + size - 1));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
> > > > > + lower_32_bits(pci_addr));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
> > > > > + upper_32_bits(pci_addr));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> > > > > + PCIE_ATU_FUNC_NUM(func_no));
> > > >
> > > > The same here, this is identical to dw_pcie_prog_outbound_atu with
> > > > the exception of this line.
> > > >
> > > > Is there a way you can avoid all of this duplicated code?
> > > As above, I can integrate the same code, but I keep to think the
> > > different outbound Window set function should be used between RC and EP.
> >
> > Or, is it possible to keep and use the existing functions, but use them
> > differently, e.g:
> >
> >
> > @@ -137,8 +146,8 @@ static int dw_pcie_ep_outbound_atu(struct
> > dw_pcie_ep *ep, phys_addr_t phys_addr,
> > return -EINVAL;
> > }
> >
> > - dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> > - phys_addr, pci_addr, size);
> > + dw_pcie_prog_outbound_atu(pci, free_win,
> > PCIE_ATU_TYPE_MEM_FUNC(func_no),
> > + phys_addr, pci_addr, size);
> >
> > set_bit(free_win, ep->ob_window_map);
> > ep->outbound_addr[free_win] = phys_addr;
> >
> >
> > Supported with:
> >
> > #define PCIE_ATU_TYPE_MEM 0x0
> > #define PCIE_ATU_TYPE_MEM_FUNC(func_no) (PCIE_ATU_TYPE_MEM |
> > PCIE_ATU_FUNC_NUM(func_no))
> >
> >
> > This is just a suggestion, but I'm keen to avoid code duplication.
> Thanks, I have think of a way as follow:
>
> This is a good way, but I think PCIE_ATU_TYPE_MEM_FUNC(func_no) will give
> Someone confused meaning, because PCIE_ATU_TYPE_MEM indicate the type of TLP,
> and the location in the bit[0:3] of register CR1, but the PCIE_ATU_FUNC_NUM is bit[20:24],
> I have another way:
> @@ -137,8 +146,8 @@ static int dw_pcie_ep_outbound_atu(struct
> dw_pcie_ep *ep, phys_addr_t phys_addr,
> return -EINVAL;
> }
>
> dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> phys_addr, pci_addr, size);
> + val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR1);
> + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val | PCIE_ATU_FUNC_NUM(func_no));
> or
> +void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> + int type, u64 cpu_addr, u64 pci_addr,
> + u32 size)
> +{
> + dw_pcie_prog_outbound_atu(pci, index, type, cpu_addr, pci_addr, size);
> + val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR1);
> + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val | PCIE_ATU_FUNC_NUM(func_no));
> +}
>
> Which do you think is better of these three ways?
Building upon your idea, how about:
@@ -137,8 +146,8 @@ static int dw_pcie_ep_outbound_atu(struct
dw_pcie_ep *ep, phys_addr_t phys_addr,
return -EINVAL;
}
- dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
+ dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM
+ phys_addr, pci_addr, size);
set_bit(free_win, ep->ob_window_map);
ep->outbound_addr[free_win] = phys_addr;
+void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size)
+{
+ __dw_pcie_prog_outbound_atu(pci, func_no, index, type, cpu_addr, pci_addr, size);
+}
+
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
+ int type, u64 cpu_addr, u64 pci_addr,
+ u32 size)
+{
+ __dw_pcie_prog_outbound_atu(pci, 0, index, type, cpu_addr, pci_addr, size);
+}
In other words dw_pcie_prog_outbound_atu is updated (and renamed) to always
take a func_no and for host controllers this is always set to zero. Or you
could follow the approach taken in the cadence drivers for their implementation
of cdns_pcie_set_outbound_region - this always takes a func_no and is used
by host controller and endpoint drivers (except they don't have the helper
wrapper functions above thus exposing fn=0 to host controllers).
> >
> > > >
> > > > Thanks,
> > > >
> > > > Andrew Murray
> > > >
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> > > > > +
> > > > > + /*
> > > > > + * Make sure ATU enable takes effect before any subsequent config
> > > > > + * and I/O accesses.
> > > > > + */
> > > > > + for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> > {
> > > > > + val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> > > > > + if (val & PCIE_ATU_ENABLE)
> > > > > + return;
> > > > > +
> > > > > + mdelay(LINK_WAIT_IATU);
> > > > > + }
> > > > > + dev_err(pci->dev, "Outbound iATU is not being enabled\n"); }
> > > > > +
> > > > > void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int
> > type,
> > > > > u64 cpu_addr, u64 pci_addr, u32 size) { @@
> > -252,8
> > > > +334,8
> > > > > @@ static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32
> > > > > index,
> > > > u32 reg,
> > > > > dw_pcie_writel_atu(pci, offset + reg, val); }
> > > > >
> > > > > -static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int
> > index,
> > > > > - int bar, u64 cpu_addr,
> > > > > +static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci,
> > > > > +u8
> > > > func_no,
> > > > > + int index, int bar, u64 cpu_addr,
> > > > > enum dw_pcie_as_type as_type) {
> > > > > int type;
> > > > > @@ -275,8 +357,10 @@ static int
> > > > > dw_pcie_prog_inbound_atu_unroll(struct
> > > > dw_pcie *pci, int index,
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - dw_pcie_writel_ib_unroll(pci, index,
> > PCIE_ATU_UNR_REGION_CTRL1,
> > > > type);
> > > > > + dw_pcie_writel_ib_unroll(pci, index,
> > PCIE_ATU_UNR_REGION_CTRL1,
> > > > type |
> > > > > + PCIE_ATU_FUNC_NUM(func_no));
> > > > > dw_pcie_writel_ib_unroll(pci, index,
> > PCIE_ATU_UNR_REGION_CTRL2,
> > > > > + PCIE_ATU_FUNC_NUM_MATCH_EN |
> > > > > PCIE_ATU_ENABLE |
> > > > > PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
> > > > >
> > > > > @@ -297,14 +381,15 @@ static int
> > > > dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
> > > > > return -EBUSY;
> > > > > }
> > > > >
> > > > > -int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
> > > > > - u64 cpu_addr, enum dw_pcie_as_type as_type)
> > > > > +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int
> > index,
> > > > > + int bar, u64 cpu_addr,
> > > > > + enum dw_pcie_as_type as_type)
> > > > > {
> > > > > int type;
> > > > > u32 retries, val;
> > > > >
> > > > > if (pci->iatu_unroll_enabled)
> > > > > - return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
> > > > > + return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index,
> > > > > +bar,
> > > > > cpu_addr, as_type);
> > > > >
> > > > > dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
> > > > PCIE_ATU_REGION_INBOUND |
> > > > > @@ -323,9 +408,11 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie
> > > > *pci, int index, int bar,
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
> > > > > - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
> > > > > - | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> > > > > + PCIE_ATU_FUNC_NUM(func_no));
> > > > > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
> > > > > + PCIE_ATU_FUNC_NUM_MATCH_EN |
> > > > > + PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
> > > > >
> > > > > /*
> > > > > * Make sure ATU enable takes effect before any subsequent
> > > > > config diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > index ffed084..2b291e8 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > @@ -71,9 +71,11 @@
> > > > > #define PCIE_ATU_TYPE_IO 0x2
> > > > > #define PCIE_ATU_TYPE_CFG0 0x4
> > > > > #define PCIE_ATU_TYPE_CFG1 0x5
> > > > > +#define PCIE_ATU_FUNC_NUM(pf) (pf << 20)
> > > > > #define PCIE_ATU_CR2 0x908
> > > > > #define PCIE_ATU_ENABLE BIT(31)
> > > > > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > > > > +#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > > > > #define PCIE_ATU_LOWER_BASE 0x90C
> > > > > #define PCIE_ATU_UPPER_BASE 0x910
> > > > > #define PCIE_ATU_LIMIT 0x914
> > > > > @@ -265,8 +267,12 @@ int dw_pcie_wait_for_link(struct dw_pcie
> > > > > *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> > > > > int type, u64 cpu_addr, u64 pci_addr,
> > > > > u32 size);
> > > > > -int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
> > > > > - u64 cpu_addr, enum dw_pcie_as_type as_type);
> > > > > +void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8
> > > > > +func_no, int
> > > > index,
> > > > > + int type, u64 cpu_addr, u64 pci_addr,
> > > > > + u32 size);
> > > > > +int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int
> > index,
> > > > > + int bar, u64 cpu_addr,
> > > > > + enum dw_pcie_as_type as_type);
> > > > > void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
> > > > > enum dw_pcie_region_type type); void
> > dw_pcie_setup(struct
> > > > > dw_pcie *pci); diff --git a/include/linux/pci-epc.h
> > > > > b/include/linux/pci-epc.h index f641bad..fc2feee 100644
> > > > > --- a/include/linux/pci-epc.h
> > > > > +++ b/include/linux/pci-epc.h
> > > > > @@ -96,6 +96,7 @@ struct pci_epc {
> > > > > const struct pci_epc_ops *ops;
> > > > > struct pci_epc_mem *mem;
> > > > > u8 max_functions;
> > > > > + u32 pf_offset;
> >
> > Also pf_offset is an implementation detail needed only by the driver to
> > calculate where the PF is - it doesn't seem right that we share this with the EP
> > controller framework (whereas max_functions is used as a bounds check for
> > func_no in the framework calls).
> >
> > I'd suggest that pf_offset is moved to a dwc structure, perhaps dw_pcie_ep?
> I add the variable to this struct is consider that all PF is belong to a PCIe controller,
> and the pci_epc indicate a PCIe controller, so I add this variable to this struct, what
> do you think about this? I am not sure whether I should add this variable to dw_pcie_ep.
The EPC framework won't use the pf_offset and doesn't need it. It abstracts
the complexity of writing to the config address space (and similar) through
the pci_epc_ops. I'd suggest that the EPC framework (and pci_epc struct) only
needs to contain what *it* needs. Especially given that not all ep drivers
have a pf_offset or similar.
I understand the logic that pci_epc represents a EP controller, but I think
you should consider that it actually represents a *generic* EP controller in
the context of a framework which solely serves the purpose of connecting
controllers with functions. Whereas the dw_pcie_ep represents a specific type
of controller (DW) - as the pf_offset is (so far) relating to only DW
controllers (and as confirmed by the DT mapping) then it makes sense to not
move pf_offset from the specialised specific controller to the generic
controller. (Or at least this is how I rationalise it, though the EPC
framework is something quite unfamiliar to me).
Thanks,
Andrew Murray
> >
> > Thanks,
> >
> > Andrew Murray
> >
> > > > > struct config_group *group;
> > > > > /* spinlock to protect against concurrent access of EP controller */
> > > > > spinlock_t lock;
> > > > > --
> > > > > 2.9.5
> > > > >
> > > > >
> > > > > _______________________________________________
> > > > > linux-arm-kernel mailing list
> > > > > linux-arm-kernel@lists.infradead.org
> > > > > http://lists
> > > > > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=0
> > 2
> > > > > %
> > > > 7C0
> > > > >
> > > >
> > 1%7Cxiaowei.bao%40nxp.com%7C0e39168f6f144db6840308d721742040%7
> > > > C686ea1d
> > > > >
> > > >
> > 3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637014654998524452&sd
> > > > ata=bP7eh
> > > > > cjlGXCMVFE2b4f12Q6fGV7lQ%2F5i9qIi9FoPlbI%3D&reserved=0
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^ permalink raw reply
* [RFC v4 18/18] objtool: arm64: Enable stack validation for arm64
From: Raphael Gault @ 2019-08-16 12:24 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3adcec05b1f6..dc3de85b2502 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -163,6 +163,7 @@ config ARM64
select HAVE_RCU_TABLE_FREE
select HAVE_RSEQ
select HAVE_STACKPROTECTOR
+ select HAVE_STACK_VALIDATION
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_KPROBES
select HAVE_KRETPROBES
--
2.17.1
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* [RFC v4 17/18] arm64: kernel: Annotate non-standard stack frame functions
From: Raphael Gault @ 2019-08-16 12:24 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Annotate assembler functions which are callable but do not
setup a correct stack frame.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/kernel/hyp-stub.S | 3 +++
arch/arm64/kvm/hyp-init.S | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 73d46070b315..8917d42f38c7 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -6,6 +6,7 @@
* Author: Marc Zyngier <marc.zyngier@arm.com>
*/
+#include <linux/frame.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/irqchip/arm-gic-v3.h>
@@ -42,6 +43,7 @@ ENTRY(__hyp_stub_vectors)
ventry el1_fiq_invalid // FIQ 32-bit EL1
ventry el1_error_invalid // Error 32-bit EL1
ENDPROC(__hyp_stub_vectors)
+asm_stack_frame_non_standard __hyp_stub_vectors
.align 11
@@ -69,6 +71,7 @@ el1_sync:
9: mov x0, xzr
eret
ENDPROC(el1_sync)
+asm_stack_frame_non_standard el1_sync
.macro invalid_vector label
\label:
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index 160be2b4696d..63deea39313d 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -12,6 +12,7 @@
#include <asm/pgtable-hwdef.h>
#include <asm/sysreg.h>
#include <asm/virt.h>
+#include <linux/frame.h>
.text
.pushsection .hyp.idmap.text, "ax"
@@ -118,6 +119,7 @@ CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
/* Hello, World! */
eret
ENDPROC(__kvm_hyp_init)
+asm_stack_frame_non_standard __kvm_hyp_init
ENTRY(__kvm_handle_stub_hvc)
cmp x0, #HVC_SOFT_RESTART
@@ -159,6 +161,7 @@ reset:
eret
ENDPROC(__kvm_handle_stub_hvc)
+asm_stack_frame_non_standard __kvm_handle_stub_hvc
.ltorg
--
2.17.1
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^ permalink raw reply related
* [RFC v4 16/18] arm64: crypto: Add exceptions for crypto object to prevent stack analysis
From: Raphael Gault @ 2019-08-16 12:24 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Some crypto modules contain `.word` of data in the .text section.
Since objtool can't make the distinction between data and incorrect
instruction, it gives a warning about the instruction beeing unknown
and stops the analysis of the object file.
The exception can be removed if the data are moved to another section
or if objtool is tweaked to handle this particular case.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/crypto/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index 0435f2a0610e..e2a25919ebaa 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -43,9 +43,11 @@ aes-neon-blk-y := aes-glue-neon.o aes-neon.o
obj-$(CONFIG_CRYPTO_SHA256_ARM64) += sha256-arm64.o
sha256-arm64-y := sha256-glue.o sha256-core.o
+OBJECT_FILES_NON_STANDARD_sha256-core.o := y
obj-$(CONFIG_CRYPTO_SHA512_ARM64) += sha512-arm64.o
sha512-arm64-y := sha512-glue.o sha512-core.o
+OBJECT_FILES_NON_STANDARD_sha512-core.o := y
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
chacha-neon-y := chacha-neon-core.o chacha-neon-glue.o
@@ -58,6 +60,7 @@ aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
obj-$(CONFIG_CRYPTO_AES_ARM64_BS) += aes-neon-bs.o
aes-neon-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
+OBJECT_FILES_NON_STANDARD_aes-neonbs-core.o := y
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
--
2.17.1
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* [RFC v4 15/18] arm64: kernel: Add exception on kuser32 to prevent stack analysis
From: Raphael Gault @ 2019-08-16 12:24 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
kuser32 being used for compatibility, it contains a32 instructions
which are not recognised by objtool when trying to analyse arm64
object files. Thus, we add an exception to skip validation on this
particular file.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/kernel/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 478491f07b4f..1239c7da4c02 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -33,6 +33,9 @@ ifneq ($(CONFIG_COMPAT_VDSO), y)
obj-$(CONFIG_COMPAT) += sigreturn32.o
endif
obj-$(CONFIG_KUSER_HELPERS) += kuser32.o
+
+OBJECT_FILES_NON_STANDARD_kuser32.o := y
+
obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_ARM64_MODULE_PLTS) += module-plts.o
--
2.17.1
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* [RFC v4 13/18] arm64: sleep: Prevent stack frame warnings from objtool
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
This code doesn't respect the Arm PCS but it is intended this
way. Adapting it to respect the PCS would result in altering the
behaviour.
In order to suppress objtool's warnings, we setup a stack frame
for __cpu_suspend_enter and annotate cpu_resume and _cpu_resume
as having non-standard stack frames.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/kernel/sleep.S | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index f5b04dd8a710..55c7c099d32c 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/errno.h>
+#include <linux/frame.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
@@ -90,6 +91,7 @@ ENTRY(__cpu_suspend_enter)
str x0, [x1]
add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
stp x29, lr, [sp, #-16]!
+ mov x29, sp
bl cpu_do_suspend
ldp x29, lr, [sp], #16
mov x0, #1
@@ -146,3 +148,6 @@ ENTRY(_cpu_resume)
mov x0, #0
ret
ENDPROC(_cpu_resume)
+
+ asm_stack_frame_non_standard cpu_resume
+ asm_stack_frame_non_standard _cpu_resume
--
2.17.1
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* [RFC v4 14/18] arm64: kvm: Annotate non-standard stack frame functions
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Both __guest_entry and __guest_exit functions do not setup
a correct stack frame. Because they can be considered as callable
functions, even if they are particular cases, we chose to silence
the warnings given by objtool by annotating them as non-standard.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/kvm/hyp/entry.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
index e5cc8d66bf53..c3443bfd0944 100644
--- a/arch/arm64/kvm/hyp/entry.S
+++ b/arch/arm64/kvm/hyp/entry.S
@@ -15,6 +15,7 @@
#include <asm/kvm_asm.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_ptrauth.h>
+#include <linux/frame.h>
#define CPU_GP_REG_OFFSET(x) (CPU_GP_REGS + x)
#define CPU_XREG_OFFSET(x) CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
@@ -97,6 +98,7 @@ alternative_else_nop_endif
eret
sb
ENDPROC(__guest_enter)
+asm_stack_frame_non_standard __guest_enter
ENTRY(__guest_exit)
// x0: return code
@@ -193,3 +195,4 @@ abort_guest_exit_end:
orr x0, x0, x5
1: ret
ENDPROC(__guest_exit)
+asm_stack_frame_non_standard __guest_exit
--
2.17.1
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* [RFC v4 12/18] arm64: assembler: Add macro to annotate asm function having non standard stack-frame.
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Some functions don't have standard stack-frames but are intended
this way. In order for objtool to ignore those particular cases
we add a macro that enables us to annotate the cases we chose
to mark as particular.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
include/linux/frame.h | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/linux/frame.h b/include/linux/frame.h
index 02d3ca2d9598..1e35e58ab259 100644
--- a/include/linux/frame.h
+++ b/include/linux/frame.h
@@ -11,14 +11,31 @@
*
* For more information, see tools/objtool/Documentation/stack-validation.txt.
*/
+#ifndef __ASSEMBLY__
#define STACK_FRAME_NON_STANDARD(func) \
static void __used __section(.discard.func_stack_frame_non_standard) \
*__func_stack_frame_non_standard_##func = func
+#else
+ /*
+ * This macro is the arm64 assembler equivalent of the
+ * macro STACK_FRAME_NON_STANDARD define at
+ * ~/include/linux/frame.h
+ */
+ .macro asm_stack_frame_non_standard func
+ .pushsection ".discard.func_stack_frame_non_standard"
+ .quad \func
+ .popsection
+ .endm
+#endif /* __ASSEMBLY__ */
#else /* !CONFIG_STACK_VALIDATION */
+#ifndef __ASSEMBLY__
#define STACK_FRAME_NON_STANDARD(func)
-
+#else
+ .macro asm_stack_frame_non_standard func
+ .endm
+#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STACK_VALIDATION */
#endif /* _LINUX_FRAME_H */
--
2.17.1
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* [RFC v4 10/18] objtool: arm64: Implement functions to add switch tables alternatives
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
This patch implements the functions required to identify and add as
alternatives all the possible destinations of the switch table.
This implementation relies on the new plugin introduced previously which
records information about the switch-table in a .objtool_data section.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch/arm64/arch_special.c | 132 +++++++++++++++++-
.../objtool/arch/arm64/include/arch_special.h | 10 ++
.../objtool/arch/arm64/include/insn_decode.h | 3 +-
tools/objtool/check.c | 6 +-
tools/objtool/check.h | 2 +
5 files changed, 146 insertions(+), 7 deletions(-)
diff --git a/tools/objtool/arch/arm64/arch_special.c b/tools/objtool/arch/arm64/arch_special.c
index 17a8a06aac2a..11284066157c 100644
--- a/tools/objtool/arch/arm64/arch_special.c
+++ b/tools/objtool/arch/arm64/arch_special.c
@@ -12,8 +12,13 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#include <stdlib.h>
+#include <string.h>
+
#include "../../special.h"
#include "arch_special.h"
+#include "bit_operations.h"
void arch_force_alt_path(unsigned short feature,
bool uaccess,
@@ -21,9 +26,133 @@ void arch_force_alt_path(unsigned short feature,
{
}
+static u32 next_offset(u8 *table, u8 entry_size)
+{
+ switch (entry_size) {
+ case 1:
+ return table[0];
+ case 2:
+ return *(u16 *)(table);
+ default:
+ return *(u32 *)(table);
+ }
+}
+
+static u32 get_table_entry_size(u32 insn)
+{
+ unsigned char size = (insn >> 30) & ONES(2);
+ switch (size) {
+ case 0:
+ return 1;
+ case 1:
+ return 2;
+ default:
+ return 4;
+ }
+}
+
+static int add_possible_branch(struct objtool_file *file,
+ struct instruction *insn,
+ u32 base, u32 offset)
+{
+ struct instruction *dest_insn;
+ struct alternative *alt;
+ offset = base + 4 * offset;
+
+ alt = calloc(1, sizeof(*alt));
+ if (alt == NULL) {
+ WARN("allocation failure, can't add jump alternative");
+ return -1;
+ }
+
+ dest_insn = find_insn(file, insn->sec, offset);
+ if (dest_insn == NULL) {
+ free(alt);
+ return 0;
+ }
+ alt->insn = dest_insn;
+ alt->skip_orig = true;
+ list_add_tail(&alt->list, &insn->alts);
+ return 0;
+}
+
int arch_add_jump_table(struct objtool_file *file, struct instruction *insn,
struct rela *table, struct rela *next_table)
{
+ struct rela *objtool_data_rela = NULL;
+ struct switch_table_info *swt_info = NULL;
+ struct section *objtool_data = find_section_by_name(file->elf, ".objtool_data");
+ struct section *rodata_sec = find_section_by_name(file->elf, ".rodata");
+ struct section *branch_sec = NULL;
+ u8 *switch_table = NULL;
+ u64 base_offset = 0;
+ struct instruction *pre_jump_insn;
+ u32 sec_size = 0;
+ u32 entry_size = 0;
+ u32 offset = 0;
+ u32 i, j;
+
+ if (objtool_data == NULL)
+ return 0;
+
+ /*
+ * 1. Using rela, Identify entry for the switch table
+ * 2. Retrieve base offset
+ * 3. Retrieve branch instruction
+ * 3. For all entries in switch table:
+ * 3.1. Compute new offset
+ * 3.2. Create alternative instruction
+ * 3.3. Add alt_instr to insn->alts list
+ */
+ sec_size = objtool_data->sh.sh_size;
+ for (i = 0, swt_info = (void *)objtool_data->data->d_buf;
+ i < sec_size / sizeof(struct switch_table_info);
+ i++, swt_info++) {
+ offset = i * sizeof(struct switch_table_info);
+ objtool_data_rela = find_rela_by_dest_range(objtool_data, offset,
+ sizeof(u64));
+ /* retrieving the objtool data of the switch table we need */
+ if (objtool_data_rela == NULL ||
+ table->sym->sec != objtool_data_rela->sym->sec ||
+ table->addend != objtool_data_rela->addend)
+ continue;
+
+ /* retrieving switch table content */
+ switch_table = (u8 *)(rodata_sec->data->d_buf + table->addend);
+
+ /* retrieving pre jump instruction (ldr) */
+ branch_sec = insn->sec;
+ pre_jump_insn = find_insn(file, branch_sec,
+ insn->offset - 3 * sizeof(u32));
+ entry_size = get_table_entry_size(*(u32 *)(branch_sec->data->d_buf + pre_jump_insn->offset));
+
+ /*
+ * iterating over the pre-jumps instruction in order to
+ * retrieve switch base offset.
+ */
+ while (pre_jump_insn != NULL &&
+ pre_jump_insn->offset <= insn->offset) {
+ if (pre_jump_insn->stack_op.src.reg == ADR_SOURCE) {
+ base_offset = pre_jump_insn->offset +
+ pre_jump_insn->immediate;
+ /*
+ * Once we have the switch table entry size
+ * we add every possible destination using
+ * alternatives of the original branch
+ * instruction
+ */
+ for (j = 0; j < swt_info->nb_entries; j++) {
+ if (add_possible_branch(file, insn,
+ base_offset,
+ next_offset(switch_table, entry_size))) {
+ return -1;
+ }
+ switch_table += entry_size;
+ }
+ }
+ pre_jump_insn = next_insn_same_sec(file, pre_jump_insn);
+ }
+ }
return 0;
}
@@ -32,6 +161,5 @@ struct rela *arch_find_switch_table(struct objtool_file *file,
struct section *rodata_sec,
unsigned long table_offset)
{
- file->ignore_unreachables = true;
- return NULL;
+ return text_rela;
}
diff --git a/tools/objtool/arch/arm64/include/arch_special.h b/tools/objtool/arch/arm64/include/arch_special.h
index 185103be8a51..cba432fed80f 100644
--- a/tools/objtool/arch/arm64/include/arch_special.h
+++ b/tools/objtool/arch/arm64/include/arch_special.h
@@ -15,6 +15,8 @@
#ifndef _ARM64_ARCH_SPECIAL_H
#define _ARM64_ARCH_SPECIAL_H
+#include <linux/types.h>
+
#define EX_ENTRY_SIZE 8
#define EX_ORIG_OFFSET 0
#define EX_NEW_OFFSET 4
@@ -30,6 +32,14 @@
#define ALT_ORIG_LEN_OFFSET 10
#define ALT_NEW_LEN_OFFSET 11
+#define ADR_SOURCE 255
+
+struct switch_table_info {
+ u64 switch_table_label;
+ u64 nb_entries;
+ u64 offset_unsigned;
+} __attribute__((__packed__));
+
static inline bool arch_should_ignore_feature(unsigned short feature)
{
return false;
diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h
index a01d76306749..65b6efecd68f 100644
--- a/tools/objtool/arch/arm64/include/insn_decode.h
+++ b/tools/objtool/arch/arm64/include/insn_decode.h
@@ -18,6 +18,7 @@
#define _ARM_INSN_DECODE_H
#include "../../../arch.h"
+#include "arch_special.h"
#define INSN_RESERVED 0b0000
#define INSN_UNALLOC_1 0b0001
@@ -58,8 +59,6 @@
#define COMPOSED_INSN_REGS_NUM 2
#define INSN_COMPOSED 1
-#define ADR_SOURCE -1
-
typedef int (*arm_decode_class)(u32 instr, unsigned char *type,
unsigned long *immediate, struct stack_op *op);
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 18f7fb47392a..2c4ea51041e1 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -35,8 +35,8 @@ struct instruction *find_insn(struct objtool_file *file,
return NULL;
}
-static struct instruction *next_insn_same_sec(struct objtool_file *file,
- struct instruction *insn)
+struct instruction *next_insn_same_sec(struct objtool_file *file,
+ struct instruction *insn)
{
struct instruction *next = list_next_entry(insn, list);
@@ -1856,7 +1856,7 @@ static int validate_sibling_call(struct instruction *insn, struct insn_state *st
{
if (arch_is_insn_sibling_call(insn) && has_modified_stack_frame(state)) {
WARN_FUNC("sibling call from callable instruction with modified stack frame",
- insn->sec, insn->offset);
+ insn->sec, insn->offset);
return 1;
}
diff --git a/tools/objtool/check.h b/tools/objtool/check.h
index 267759760a3d..5833f85f71c3 100644
--- a/tools/objtool/check.h
+++ b/tools/objtool/check.h
@@ -66,6 +66,8 @@ int check(const char *objname, bool orc);
struct instruction *find_insn(struct objtool_file *file,
struct section *sec, unsigned long offset);
+struct instruction *next_insn_same_sec(struct objtool_file *file,
+ struct instruction *insn);
#define for_each_insn(file, insn) \
list_for_each_entry(insn, &file->insn_list, list)
--
2.17.1
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^ permalink raw reply related
* [RFC v4 11/18] arm64: alternative: Mark .altinstr_replacement as containing executable instructions
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Until now, the section .altinstr_replacement wasn't marked as containing
executable instructions on arm64. This patch changes that so that it is
coherent with what is done on x86.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
arch/arm64/include/asm/alternative.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/alternative.h b/arch/arm64/include/asm/alternative.h
index b9f8d787eea9..e9e6b81e3eb4 100644
--- a/arch/arm64/include/asm/alternative.h
+++ b/arch/arm64/include/asm/alternative.h
@@ -71,7 +71,7 @@ static inline void apply_alternatives_module(void *start, size_t length) { }
ALTINSTR_ENTRY(feature,cb) \
".popsection\n" \
" .if " __stringify(cb) " == 0\n" \
- ".pushsection .altinstr_replacement, \"a\"\n" \
+ ".pushsection .altinstr_replacement, \"ax\"\n" \
"663:\n\t" \
newinstr "\n" \
"664:\n\t" \
--
2.17.1
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* [RFC v4 07/18] objtool: Introduce INSN_UNKNOWN type
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
On arm64 some object files contain data stored in the .text section.
This data is interpreted by objtool as instruction but can't be
identified as a valid one. In order to keep analysing those files we
introduce INSN_UNKNOWN type. The "unknown instruction" warning will thus
only be raised if such instructions are uncountered while validating an
execution branch.
This change doesn't impact the x86 decoding logic since 0 is still used
as a way to specify an unknown type, raising the "unknown instruction"
warning during the decoding phase still.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch.h | 1 +
tools/objtool/arch/arm64/decode.c | 8 ++++----
tools/objtool/arch/arm64/include/insn_decode.h | 4 ++--
tools/objtool/check.c | 10 +++++++++-
4 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index 68d6371a24a2..9f2590e1df79 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -28,6 +28,7 @@ enum insn_type {
INSN_CLAC,
INSN_STD,
INSN_CLD,
+ INSN_UNKNOWN,
INSN_OTHER,
};
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index be3d2eb10227..4cb9402d6fe1 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -37,9 +37,9 @@
*/
static arm_decode_class aarch64_insn_class_decode_table[] = {
[INSN_RESERVED] = arm_decode_reserved,
- [INSN_UNKNOWN] = arm_decode_unknown,
+ [INSN_UNALLOC_1] = arm_decode_unknown,
[INSN_SVE_ENC] = arm_decode_sve_encoding,
- [INSN_UNALLOC] = arm_decode_unknown,
+ [INSN_UNALLOC_2] = arm_decode_unknown,
[INSN_LD_ST_4] = arm_decode_ld_st,
[INSN_DP_REG_5] = arm_decode_dp_reg,
[INSN_LD_ST_6] = arm_decode_ld_st,
@@ -191,7 +191,7 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
int arm_decode_unknown(u32 instr, unsigned char *type,
unsigned long *immediate, struct stack_op *op)
{
- *type = 0;
+ *type = INSN_UNKNOWN;
return 0;
}
@@ -206,7 +206,7 @@ int arm_decode_reserved(u32 instr, unsigned char *type,
unsigned long *immediate, struct stack_op *op)
{
*immediate = instr & ONES(16);
- *type = INSN_BUG;
+ *type = INSN_UNKNOWN;
return 0;
}
diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h
index eb54fc39dca5..a01d76306749 100644
--- a/tools/objtool/arch/arm64/include/insn_decode.h
+++ b/tools/objtool/arch/arm64/include/insn_decode.h
@@ -20,9 +20,9 @@
#include "../../../arch.h"
#define INSN_RESERVED 0b0000
-#define INSN_UNKNOWN 0b0001
+#define INSN_UNALLOC_1 0b0001
#define INSN_SVE_ENC 0b0010
-#define INSN_UNALLOC 0b0011
+#define INSN_UNALLOC_2 0b0011
#define INSN_DP_IMM 0b1001 //0x100x
#define INSN_BRANCH 0b1011 //0x101x
#define INSN_LD_ST_4 0b0100 //0bx1x0
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 519569b0329f..baa6a93f37cd 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -1981,6 +1981,13 @@ static int validate_branch(struct objtool_file *file, struct symbol *func,
while (1) {
next_insn = next_insn_same_sec(file, insn);
+ if (insn->type == INSN_UNKNOWN) {
+ WARN("%s+0x%lx unknown instruction type, should never be reached",
+ insn->sec->name,
+ insn->offset);
+ return 1;
+ }
+
if (file->c_file && func && insn->func && func != insn->func->pfunc) {
WARN("%s() falls through to next function %s()",
func->name, insn->func->name);
@@ -2414,7 +2421,8 @@ static int validate_reachable_instructions(struct objtool_file *file)
return 0;
for_each_insn(file, insn) {
- if (insn->visited || ignore_unreachable_insn(insn))
+ if (insn->visited || ignore_unreachable_insn(insn) ||
+ insn->type == INSN_UNKNOWN)
continue;
WARN_FUNC("unreachable instruction", insn->sec, insn->offset);
--
2.17.1
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^ permalink raw reply related
* [RFC v4 04/18] objtool: arm64: Add required implementation for supporting the aarch64 architecture in objtool.
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Provide implementation for the arch-dependent functions that are called by
the main check function of objtool. The ORC unwinder is not yet supported
by the arm64 architecture so we only provide a dummy interface for now.
The decoding of the instruction is split into classes and subclasses as
described into the Instruction Encoding in the ArmV8.5 Architecture
Reference Manual.
In order to handle the load/store instructions for a pair of registers
we add an extra field to the stack_op structure.
We consider that the hypervisor/secure-monitor is behaving
correctly. This enables us to handle hvc/smc/svc context switching
instructions as nop since we consider that the context is restored
correctly.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch.h | 7 +
tools/objtool/arch/arm64/Build | 7 +
tools/objtool/arch/arm64/bit_operations.c | 67 +
tools/objtool/arch/arm64/decode.c | 2787 +++++++++++++++++
.../objtool/arch/arm64/include/arch_special.h | 36 +
.../arch/arm64/include/asm/orc_types.h | 96 +
.../arch/arm64/include/bit_operations.h | 24 +
tools/objtool/arch/arm64/include/cfi.h | 74 +
.../objtool/arch/arm64/include/insn_decode.h | 211 ++
tools/objtool/arch/arm64/orc_dump.c | 26 +
tools/objtool/arch/arm64/orc_gen.c | 40 +
11 files changed, 3375 insertions(+)
create mode 100644 tools/objtool/arch/arm64/Build
create mode 100644 tools/objtool/arch/arm64/bit_operations.c
create mode 100644 tools/objtool/arch/arm64/decode.c
create mode 100644 tools/objtool/arch/arm64/include/arch_special.h
create mode 100644 tools/objtool/arch/arm64/include/asm/orc_types.h
create mode 100644 tools/objtool/arch/arm64/include/bit_operations.h
create mode 100644 tools/objtool/arch/arm64/include/cfi.h
create mode 100644 tools/objtool/arch/arm64/include/insn_decode.h
create mode 100644 tools/objtool/arch/arm64/orc_dump.c
create mode 100644 tools/objtool/arch/arm64/orc_gen.c
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index e91e12807678..bb5ce810fb6e 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -62,9 +62,16 @@ struct op_src {
int offset;
};
+struct op_extra {
+ unsigned char used;
+ unsigned char reg;
+ int offset;
+};
+
struct stack_op {
struct op_dest dest;
struct op_src src;
+ struct op_extra extra;
};
struct instruction;
diff --git a/tools/objtool/arch/arm64/Build b/tools/objtool/arch/arm64/Build
new file mode 100644
index 000000000000..bf7a32c2b9e9
--- /dev/null
+++ b/tools/objtool/arch/arm64/Build
@@ -0,0 +1,7 @@
+objtool-y += decode.o
+objtool-y += orc_dump.o
+objtool-y += orc_gen.o
+objtool-y += bit_operations.o
+
+
+CFLAGS_decode.o += -I$(OUTPUT)arch/arm64/lib
diff --git a/tools/objtool/arch/arm64/bit_operations.c b/tools/objtool/arch/arm64/bit_operations.c
new file mode 100644
index 000000000000..f457a14a7f5d
--- /dev/null
+++ b/tools/objtool/arch/arm64/bit_operations.c
@@ -0,0 +1,67 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "bit_operations.h"
+
+#include "../../warn.h"
+
+u64 replicate(u64 x, int size, int n)
+{
+ u64 ret = 0;
+
+ while (n >= 0) {
+ ret = (ret | x) << size;
+ n--;
+ }
+ return ret | x;
+}
+
+u64 ror(u64 x, int size, int shift)
+{
+ int m = shift % size;
+
+ if (shift == 0)
+ return x;
+ return ZERO_EXTEND((x >> m) | (x << (size - m)), size);
+}
+
+int highest_set_bit(u32 x)
+{
+ int i;
+
+ for (i = 31; i >= 0; i--, x <<= 1)
+ if (x & 0x80000000)
+ return i;
+ return 0;
+}
+
+/* imms and immr are both 6 bit long */
+__uint128_t decode_bit_masks(unsigned char N, unsigned char imms,
+ unsigned char immr, bool immediate)
+{
+ u64 tmask, wmask;
+ u32 diff, S, R, esize, welem, telem;
+ unsigned char levels = 0, len = 0;
+
+ len = highest_set_bit((N << 6) | ((~imms) & ONES(6)));
+ levels = ZERO_EXTEND(ONES(len), 6);
+
+ if (immediate && ((imms & levels) == levels)) {
+ WARN("unknown instruction");
+ return -1;
+ }
+
+ S = imms & levels;
+ R = immr & levels;
+ diff = ZERO_EXTEND(S - R, 6);
+
+ esize = 1 << len;
+ diff = diff & ONES(len);
+
+ welem = ZERO_EXTEND(ONES(S + 1), esize);
+ telem = ZERO_EXTEND(ONES(diff + 1), esize);
+
+ wmask = replicate(ror(welem, esize, R), esize, 64 / esize);
+ tmask = replicate(telem, esize, 64 / esize);
+
+ return ((__uint128_t)wmask << 64) | tmask;
+}
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
new file mode 100644
index 000000000000..395c5777afab
--- /dev/null
+++ b/tools/objtool/arch/arm64/decode.c
@@ -0,0 +1,2787 @@
+/*
+ * Copyright (C) 2019 Raphael Gault <raphael.gault@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "insn_decode.h"
+#include "cfi.h"
+#include "bit_operations.h"
+
+#include "../../check.h"
+#include "../../arch.h"
+#include "../../elf.h"
+#include "../../warn.h"
+
+/*
+ * static int (*arm_decode_class)(u32 instr,
+ * unsigned int *len,
+ * unsigned char *type,
+ * unsigned long *immediate,
+ * struct stack_op *op);
+ */
+static arm_decode_class aarch64_insn_class_decode_table[] = {
+ [INSN_RESERVED] = arm_decode_reserved,
+ [INSN_UNKNOWN] = arm_decode_unknown,
+ [INSN_SVE_ENC] = arm_decode_sve_encoding,
+ [INSN_UNALLOC] = arm_decode_unknown,
+ [INSN_LD_ST_4] = arm_decode_ld_st,
+ [INSN_DP_REG_5] = arm_decode_dp_reg,
+ [INSN_LD_ST_6] = arm_decode_ld_st,
+ [INSN_DP_SIMD_7] = arm_decode_dp_simd,
+ [0b1000 ... INSN_DP_IMM] = arm_decode_dp_imm,
+ [0b1010 ... INSN_BRANCH] = arm_decode_br_sys,
+ [INSN_LD_ST_C] = arm_decode_ld_st,
+ [INSN_DP_REG_D] = arm_decode_dp_reg,
+ [INSN_LD_ST_E] = arm_decode_ld_st,
+ [INSN_DP_SIMD_F] = arm_decode_dp_simd,
+};
+
+static arm_decode_class aarch64_insn_dp_imm_decode_table[] = {
+ [0 ... INSN_PCREL] = arm_decode_pcrel,
+ [INSN_ADD_SUB] = arm_decode_add_sub,
+ [INSN_ADD_TAG] = arm_decode_add_sub_tags,
+ [INSN_LOGICAL] = arm_decode_logical,
+ [INSN_MOVE_WIDE] = arm_decode_move_wide,
+ [INSN_BITFIELD] = arm_decode_bitfield,
+ [INSN_EXTRACT] = arm_decode_extract,
+};
+
+bool arch_callee_saved_reg(unsigned char reg)
+{
+ switch (reg) {
+ case CFI_R19:
+ case CFI_R20:
+ case CFI_R21:
+ case CFI_R22:
+ case CFI_R23:
+ case CFI_R24:
+ case CFI_R25:
+ case CFI_R26:
+ case CFI_R27:
+ case CFI_R28:
+ case CFI_FP:
+ case CFI_R30:
+ return true;
+ default:
+ return false;
+ }
+}
+
+void arch_initial_func_cfi_state(struct cfi_state *state)
+{
+ int i;
+
+ for (i = 0; i < CFI_NUM_REGS; i++) {
+ state->regs[i].base = CFI_UNDEFINED;
+ state->regs[i].offset = 0;
+ }
+
+ /* initial CFA (call frame address) */
+ state->cfa.base = CFI_CFA;
+ state->cfa.offset = 0;
+
+ /* initial RA (return address) */
+ state->regs[CFI_LR].base = CFI_CFA;
+ state->regs[CFI_LR].offset = -8;
+}
+
+unsigned long arch_dest_rela_offset(int addend)
+{
+ return addend;
+}
+
+static int is_arm64(struct elf *elf)
+{
+ switch (elf->ehdr.e_machine) {
+ case EM_AARCH64: //0xB7
+ return 1;
+ default:
+ WARN("unexpected ELF machine type %x",
+ elf->ehdr.e_machine);
+ return 0;
+ }
+}
+
+/*
+ * Arm A64 Instruction set' decode groups (based on op0 bits[28:25]):
+ * Ob0000 - Reserved
+ * 0b0001/0b001x - Unallocated
+ * 0b100x - Data Processing -- Immediate
+ * 0b101x - Branch, Exception Gen., System Instructions.
+ * 0bx1x0 - Loads and Stores
+ * 0bx101 - Data Processing -- Registers
+ * 0bx111 - Data Processing -- Scalar Floating-Points, Advanced SIMD
+ */
+
+int arch_decode_instruction(struct elf *elf, struct section *sec,
+ unsigned long offset, unsigned int maxlen,
+ unsigned int *len, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ int arm64 = 0;
+ u32 insn = 0;
+
+ *len = 4;
+ *immediate = 0;
+
+ op->dest.type = 0;
+ op->dest.reg = 0;
+ op->dest.offset = 0;
+ op->src.type = 0;
+ op->src.reg = 0;
+ op->src.offset = 0;
+
+ //test architucture (make sure it is arm64)
+ arm64 = is_arm64(elf);
+ if (arm64 != 1)
+ return -1;
+
+ //retrieve instruction (from sec->data->offset)
+ insn = *(u32 *)(sec->data->d_buf + offset);
+
+ //dispatch according to encoding classes
+ return aarch64_insn_class_decode_table[(insn >> 25) & 0xf](insn, type,
+ immediate, op);
+}
+
+int arm_decode_unknown(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ *type = 0;
+ return 0;
+}
+
+int arm_decode_dp_simd(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_reserved(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ *immediate = instr & ONES(16);
+ *type = INSN_BUG;
+ return 0;
+}
+
+int arm_decode_dp_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ return aarch64_insn_dp_imm_decode_table[(instr >> 23) & 0x7](instr,
+ type, immediate, op);
+}
+
+int arm_decode_pcrel(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char rd = 0, page = 0;
+ u32 immhi = 0, immlo = 0;
+
+ page = EXTRACT_BIT(instr, 31);
+ rd = instr & 0x1F;
+ immhi = (instr >> 5) & ONES(19);
+ immlo = (instr >> 29) & ONES(2);
+
+ *immediate = SIGN_EXTEND((immhi << 2) | immlo, 21);
+
+ if (page)
+ *immediate = SIGN_EXTEND(*immediate << 12, 33);
+
+ *type = INSN_OTHER;
+ op->src.reg = ADR_SOURCE;
+ op->dest.reg = rd;
+
+ return 0;
+}
+
+int arm_decode_add_sub(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned long imm12 = 0, imm = 0;
+ unsigned char sf = 0, sh = 0, S = 0, op_bit = 0;
+ unsigned char rn = 0, rd = 0;
+
+ S = EXTRACT_BIT(instr, 29);
+ op_bit = EXTRACT_BIT(instr, 30);
+ sf = EXTRACT_BIT(instr, 31);
+ sh = EXTRACT_BIT(instr, 22);
+ rd = instr & ONES(5);
+ rn = (instr >> 5) & ONES(5);
+ imm12 = (instr >> 10) & ONES(12);
+ imm = ZERO_EXTEND(imm12 << (sh * 12), (sf + 1) * 32);
+
+ *type = INSN_OTHER;
+
+ if ((!S && rd == CFI_SP) || rn == CFI_SP) {
+ *type = INSN_STACK;
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+ op->dest.reg = rd;
+ op->src.type = imm12 ? OP_SRC_ADD : OP_SRC_REG;
+ op->src.offset = op_bit ? -1 * imm : imm;
+ op->src.reg = rn;
+ }
+ return 0;
+}
+
+int arm_decode_add_sub_tags(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char decode_field = 0, rn = 0, rd = 0, uimm6 = 0;
+
+ decode_field = (instr >> 29) & ONES(3);
+ rd = instr & ONES(5);
+ rn = (instr >> 5) & ONES(5);
+ uimm6 = (instr >> 16) & ONES(6);
+
+ *immediate = uimm6;
+ *type = INSN_OTHER;
+
+#define ADDG_DECODE 4
+#define SUBG_DECODE 5
+ if (decode_field != ADDG_DECODE && decode_field != SUBG_DECODE)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+#undef ADDG_DECODE
+#undef SUBG_DECODE
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+ op->dest.reg = rd;
+ op->src.type = OP_SRC_ADD;
+ op->src.offset = 0;
+ op->src.reg = rn;
+
+ if (rd == CFI_SP)
+ *type = INSN_STACK;
+
+ return 0;
+}
+
+int arm_decode_logical(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, opc = 0, N = 0;
+ unsigned char imms = 0, immr = 0, rn = 0, rd = 0;
+
+ rd = instr & ONES(5);
+ rn = (instr >> 5) & ONES(5);
+
+ imms = (instr >> 10) & ONES(6);
+ immr = (instr >> 16) & ONES(6);
+
+ N = EXTRACT_BIT(instr, 22);
+ opc = (instr >> 29) & ONES(2);
+ sf = EXTRACT_BIT(instr, 31);
+
+ if (N == 1 && sf == 0)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ *immediate = (decode_bit_masks(N, imms, immr, true) >> 64);
+#define ANDS_DECODE 0b11
+ if (opc == ANDS_DECODE)
+ return 0;
+#undef ANDS_DECODE
+ if (rd == CFI_SP) {
+ *type = INSN_STACK;
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+ op->dest.reg = CFI_SP;
+
+ op->src.type = OP_SRC_AND;
+ op->src.offset = 0;
+ op->src.reg = rn;
+ }
+
+ return 0;
+}
+
+int arm_decode_move_wide(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 imm16 = 0;
+ unsigned char hw = 0, opc = 0, sf = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ opc = (instr >> 29) & ONES(2);
+ hw = (instr >> 21) & ONES(2);
+ imm16 = (instr >> 5) & ONES(16);
+
+ if ((sf == 0 && (hw & 0x2)) || opc == 0x1)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ *immediate = imm16;
+
+ return 0;
+}
+
+int arm_decode_bitfield(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, opc = 0, N = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ opc = (instr >> 29) & ONES(2);
+ N = EXTRACT_BIT(instr, 22);
+
+ if (opc == 0x3 || sf != N)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+
+ return 0;
+}
+
+int arm_decode_extract(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, op21 = 0, N = 0, o0 = 0;
+ unsigned char imms = 0;
+ unsigned char decode_field = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ op21 = (instr >> 29) & ONES(2);
+ N = EXTRACT_BIT(instr, 22);
+ o0 = EXTRACT_BIT(instr, 21);
+ imms = (instr >> 10) & ONES(6);
+
+ decode_field = (sf << 4) | (op21 << 2) | (N << 1) | o0;
+ *type = INSN_OTHER;
+ *immediate = imms;
+
+ if ((decode_field == 0 && !EXTRACT_BIT(imms, 5)) ||
+ decode_field == 0b10010)
+ return 0;
+
+ return arm_decode_unknown(instr, type, immediate, op);
+}
+
+static struct aarch64_insn_decoder br_sys_decoder[] = {
+ {
+ .mask = 0b1111000000000000000000,
+ .value = 0b0100000000000000000000,
+ .decode_func = arm_decode_br_cond_imm,
+ },
+ {
+ .mask = 0b1111100000000000000000,
+ .value = 0b1100000000000000000000,
+ .decode_func = arm_decode_except_gen,
+ },
+ {
+ .mask = 0b1111111111111111111111,
+ .value = 0b1100100000011001011111,
+ .decode_func = arm_decode_hints,
+ },
+ {
+ .mask = 0b1111111111111111100000,
+ .value = 0b1100100000011001100000,
+ .decode_func = arm_decode_barriers,
+ },
+ {
+ .mask = 0b1111111111000111100000,
+ .value = 0b1100100000000010000000,
+ .decode_func = arm_decode_pstate,
+ },
+ {
+ .mask = 0b1111111011000000000000,
+ .value = 0b1100100001000000000000,
+ .decode_func = arm_decode_system_insn,
+ },
+ {
+ .mask = 0b1111111010000000000000,
+ .value = 0b1100100010000000000000,
+ .decode_func = arm_decode_system_regs,
+ },
+ {
+ .mask = 0b1111000000000000000000,
+ .value = 0b1101000000000000000000,
+ .decode_func = arm_decode_br_uncond_reg,
+ },
+ {
+ .mask = 0b0110000000000000000000,
+ .value = 0b0000000000000000000000,
+ .decode_func = arm_decode_br_uncond_imm,
+ },
+ {
+ .mask = 0b0111000000000000000000,
+ .value = 0b0010000000000000000000,
+ .decode_func = arm_decode_br_comp_imm,
+ },
+ {
+ .mask = 0b0111000000000000000000,
+ .value = 0b0011000000000000000000,
+ .decode_func = arm_decode_br_tst_imm,
+ },
+
+};
+
+int arm_decode_br_sys(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 decode_field = 0, op1 = 0;
+ unsigned char op0 = 0, op2 = 0;
+ int i = 0;
+
+ op0 = (instr >> 29) & ONES(3);
+ op1 = (instr >> 12) & ONES(14);
+ op2 = instr & ONES(5);
+
+ decode_field = op0;
+ decode_field = (decode_field << 19) | (op1 << 5) | op2;
+
+ for (i = 0; i < ARRAY_SIZE(br_sys_decoder); i++) {
+ if ((decode_field & br_sys_decoder[i].mask) ==
+ br_sys_decoder[i].value) {
+ return br_sys_decoder[i].decode_func(instr,
+ type,
+ immediate,
+ op);
+ }
+ }
+
+ return arm_decode_unknown(instr, type, immediate, op);
+}
+
+int arm_decode_br_cond_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char o0 = 0, o1 = 0;
+ u32 imm19;
+
+ o0 = EXTRACT_BIT(instr, 4);
+ o1 = EXTRACT_BIT(instr, 24);
+ imm19 = (instr >> 5) & ONES(19);
+
+ *immediate = SIGN_EXTEND(imm19 << 2, 19);
+
+ if ((o1 << 1) | o0)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_JUMP_CONDITIONAL;
+
+ return 0;
+}
+
+static struct aarch64_insn_decoder except_gen_decoder[] = {
+ {
+ .mask = 0b00000100,
+ .value = 0b00000100,
+ },
+ {
+ .mask = 0b00001000,
+ .value = 0b00001000,
+ },
+ {
+ .mask = 0b00010000,
+ .value = 0b00010000,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b00000000,
+ },
+ {
+ .mask = 0b11111101,
+ .value = 0b00100001,
+ },
+ {
+ .mask = 0b11111110,
+ .value = 0b00100010,
+ },
+ {
+ .mask = 0b11111101,
+ .value = 0b01000001,
+ },
+ {
+ .mask = 0b11111110,
+ .value = 0b01000010,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b01100001,
+ },
+ {
+ .mask = 0b11111110,
+ .value = 0b01100010,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b10000000,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b10100000,
+ },
+ {
+ .mask = 0b11111100,
+ .value = 0b11000000,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b11100001,
+ },
+ {
+ .mask = 0b11111110,
+ .value = 0b11100010,
+ },
+};
+
+int arm_decode_except_gen(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 imm16 = 0;
+ unsigned char opc = 0, op2 = 0, LL = 0, decode_field = 0;
+ int i = 0;
+
+ imm16 = (instr >> 5) & ONES(16);
+ opc = (instr >> 21) & ONES(3);
+ op2 = (instr >> 2) & ONES(3);
+ LL = instr & ONES(2);
+ decode_field = (opc << 5) | (op2 << 2) | LL;
+
+ for (i = 0; i < ARRAY_SIZE(except_gen_decoder); i++) {
+ if ((decode_field & except_gen_decoder[i].mask) ==
+ except_gen_decoder[i].value) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+ }
+
+#define INSN_SVC 0b00000001
+#define INSN_HVC 0b00000010
+#define INSN_SMC 0b00000011
+#define INSN_BRK 0b00100000
+#define INSN_HLT 0b01000000
+#define INSN_DCPS1 0b10100001
+#define INSN_DCPS2 0b10100010
+#define INSN_DCPS3 0b10100011
+
+ switch (decode_field) {
+ case INSN_SVC:
+ case INSN_HVC:
+ case INSN_SMC:
+ /*
+ * We consider that the context will be restored correctly
+ * with an unchanged sp and the same general registers
+ */
+ *type = INSN_NOP;
+ return 0;
+ case INSN_BRK:
+ /*
+ * brk #0x800 is generated by the BUG()/WARN() linux API and is
+ * thus a particular case. Since those are not necessarily
+ * compiled in, the surrounding code should work properly
+ * without it. We thus consider it as a nop.
+ */
+ if (imm16 == 0x800)
+ *type = INSN_NOP;
+ else if (imm16 == 0x100 || imm16 >= 0x900)
+ *type = INSN_CONTEXT_SWITCH;
+ else
+ *type = INSN_OTHER;
+ return 0;
+ case INSN_HLT:
+ case INSN_DCPS1:
+ case INSN_DCPS2:
+ case INSN_DCPS3:
+ *immediate = imm16;
+ *type = INSN_OTHER;
+ return 0;
+ default:
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+#undef INSN_SVC
+#undef INSN_HVC
+#undef INSN_SMC
+#undef INSN_BRK
+#undef INSN_HLT
+#undef INSN_DCPS1
+#undef INSN_DCPS2
+#undef INSN_DCPS3
+}
+
+int arm_decode_hints(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ *type = INSN_NOP;
+ return 0;
+}
+
+int arm_decode_barriers(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ /* TODO:check unallocated */
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_pstate(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ /* TODO:check unallocated */
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_system_insn(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ /* TODO:check unallocated */
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_system_regs(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ /* TODO:check unallocated */
+ *type = INSN_OTHER;
+ return 0;
+}
+
+static struct aarch64_insn_decoder ret_decoder[] = {
+ /*
+ * RET, RETAA, RETAB
+ */
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0010111110000000000000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111111111111111,
+ .value = 0b0010111110000101111111111,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111111111111111,
+ .value = 0b0010111110000111111111111,
+ .decode_func = NULL,
+ },
+};
+
+static struct aarch64_insn_decoder br_decoder[] = {
+ /*
+ * BR, BRAA, BRAAZ, BRAB, BRABZ
+ */
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0000111110000000000000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0000111110000100000011111,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0000111110000110000011111,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000000000,
+ .value = 0b1000111110000100000000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000000000,
+ .value = 0b1000111110000110000000000,
+ .decode_func = NULL,
+ },
+};
+
+#define INSN_DRPS_FIELD 0b0101111110000001111100000
+#define INSN_DRPS_MASK 0b1111111111111111111111111
+
+static struct aarch64_insn_decoder ct_sw_decoder[] = {
+ /*
+ * ERET, ERETAA, ERETAB
+ */
+ {
+ .mask = INSN_DRPS_MASK,
+ .value = 0b0100111110000001111100000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = INSN_DRPS_MASK,
+ .value = 0b0100111110000101111111111,
+ .decode_func = NULL,
+ },
+ {
+ .mask = INSN_DRPS_MASK,
+ .value = 0b0100111110000111111111111,
+ .decode_func = NULL,
+ },
+};
+
+static struct aarch64_insn_decoder call_decoder[] = {
+ /*
+ * BLR, BLRAA, BLRAAZ, BLRAB, BLRABZ
+ */
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0001111110000000000000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000011111,
+ .value = 0b0001111110000100000011111,
+ .decode_func = NULL,
+ },
+ {
+ 0b1111111111111110000011111,
+ 0b0001111110000110000011111,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000000000,
+ .value = 0b1001111110000100000000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b1111111111111110000000000,
+ .value = 0b1001111110000110000000000,
+ .decode_func = NULL,
+ },
+};
+
+int arm_decode_br_uncond_reg(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 decode_field = 0;
+ int i = 0;
+
+ decode_field = instr & ONES(25);
+ *type = 0;
+ for (i = 0; i < ARRAY_SIZE(br_decoder); i++) {
+ if ((decode_field & br_decoder[i].mask) == br_decoder[i].value)
+ *type = INSN_JUMP_DYNAMIC;
+ }
+ for (i = 0; i < ARRAY_SIZE(call_decoder); i++) {
+ if ((decode_field & call_decoder[i].value) ==
+ call_decoder[i].value)
+ *type = INSN_CALL_DYNAMIC;
+ }
+ for (i = 0; i < ARRAY_SIZE(ret_decoder); i++) {
+ if ((decode_field & ret_decoder[i].mask) ==
+ ret_decoder[i].value)
+ *type = INSN_RETURN;
+ }
+ for (i = 0; i < ARRAY_SIZE(ct_sw_decoder); i++) {
+ if ((decode_field & ct_sw_decoder[i].mask) ==
+ ct_sw_decoder[i].value)
+ *type = INSN_CONTEXT_SWITCH;
+ }
+ if ((decode_field & INSN_DRPS_MASK) == INSN_DRPS_FIELD)
+ *type = INSN_OTHER;
+ if (*type == 0)
+ return arm_decode_unknown(instr, type, immediate, op);
+ return 0;
+}
+
+#undef INSN_DRPS_FIELD
+#undef INSN_DRPS_MASK
+
+int arm_decode_br_uncond_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char decode_field = 0;
+ u32 imm26 = 0;
+
+ decode_field = EXTRACT_BIT(instr, 31);
+ imm26 = instr & ONES(26);
+
+ *immediate = SIGN_EXTEND(imm26 << 2, 28);
+ if (decode_field == 0)
+ *type = INSN_JUMP_UNCONDITIONAL;
+ else
+ *type = INSN_CALL;
+
+ return 0;
+}
+
+int arm_decode_br_comp_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 imm19 = (instr >> 5) & ONES(19);
+
+ *immediate = SIGN_EXTEND(imm19 << 2, 21);
+ *type = INSN_JUMP_CONDITIONAL;
+ return 0;
+}
+
+int arm_decode_br_tst_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 imm14 = (instr >> 5) & ONES(14);
+
+ *immediate = SIGN_EXTEND(imm14 << 2, 16);
+ *type = INSN_JUMP_CONDITIONAL;
+ return 0;
+}
+
+static struct aarch64_insn_decoder ld_st_decoder[] = {
+ {
+ .mask = 0b101111111111100,
+ .value = 0b000010000000000,
+ .decode_func = arm_decode_adv_simd_mult,
+ },
+ {
+ .mask = 0b101111110000000,
+ .value = 0b000010100000000,
+ .decode_func = arm_decode_adv_simd_mult_post,
+ },
+ {
+ .mask = 0b101111101111100,
+ .value = 0b000011000000000,
+ .decode_func = arm_decode_adv_simd_single,
+ },
+ {
+ .mask = 0b101111100000000,
+ .value = 0b000011100000000,
+ .decode_func = arm_decode_adv_simd_single_post,
+ },
+ {
+ .mask = 0b111111010000000,
+ .value = 0b110101010000000,
+ .decode_func = arm_decode_ld_st_mem_tags,
+ },
+ {
+ .mask = 0b001111000000000,
+ .value = 0b000000000000000,
+ .decode_func = arm_decode_ld_st_exclusive,
+ },
+ {
+ .mask = 0b001111010000011,
+ .value = 0b000101000000000,
+ .decode_func = arm_decode_ldapr_stlr_unsc_imm,
+ },
+ {
+ .mask = 0b001101000000000,
+ .value = 0b000100000000000,
+ .decode_func = arm_decode_ld_regs_literal,
+ },
+ {
+ .mask = 0b001101100000000,
+ .value = 0b001000000000000,
+ .decode_func = arm_decode_ld_st_noalloc_pair_off,
+ },
+ {
+ .mask = 0b001101100000000,
+ .value = 0b001000100000000,
+ .decode_func = arm_decode_ld_st_regs_pair_post,
+ },
+ {
+ .mask = 0b001101100000000,
+ .value = 0b001001000000000,
+ .decode_func = arm_decode_ld_st_regs_pair_off,
+ },
+ {
+ .mask = 0b001101100000000,
+ .value = 0b001001100000000,
+ .decode_func = arm_decode_ld_st_regs_pair_pre,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100000000000,
+ .decode_func = arm_decode_ld_st_regs_unsc_imm,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100000000001,
+ .decode_func = arm_decode_ld_st_imm_post,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100000000010,
+ .decode_func = arm_decode_ld_st_imm_unpriv,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100000000011,
+ .decode_func = arm_decode_ld_st_imm_pre,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100010000000,
+ .decode_func = arm_decode_atomic,
+ },
+ {
+ .mask = 0b001101010000011,
+ .value = 0b001100010000010,
+ .decode_func = arm_decode_ld_st_regs_off,
+ },
+ {
+ .mask = 0b001101010000001,
+ .value = 0b001100010000001,
+ .decode_func = arm_decode_ld_st_regs_pac,
+ },
+ {
+ .mask = 0b001101000000000,
+ .value = 0b001101000000000,
+ .decode_func = arm_decode_ld_st_regs_unsigned,
+ },
+};
+
+int arm_decode_ld_st(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 decode_field = 0;
+ int i = 0;
+ unsigned char op0 = 0, op1 = 0, op2 = 0, op3 = 0, op4 = 0;
+
+ op0 = (instr >> 28) & ONES(4);
+ op1 = EXTRACT_BIT(instr, 26);
+ op2 = (instr >> 23) & ONES(2);
+ op3 = (instr >> 16) & ONES(6);
+ op4 = (instr >> 10) & ONES(2);
+ decode_field = (op0 << 3) | (op1 << 2) | op2;
+ decode_field = (decode_field << 8) | (op3 << 2) | op4;
+
+ for (i = 0; i < ARRAY_SIZE(ld_st_decoder); i++) {
+ if ((decode_field & ld_st_decoder[i].mask) ==
+ ld_st_decoder[i].value) {
+ return ld_st_decoder[i].decode_func(instr,
+ type,
+ immediate,
+ op);
+ }
+ }
+ return arm_decode_unknown(instr, type, immediate, op);
+}
+
+static int adv_simd_mult_fields[] = {
+ 0b00000,
+ 0b00010,
+ 0b00100,
+ 0b00110,
+ 0b00111,
+ 0b01000,
+ 0b01010,
+ 0b10000,
+ 0b10010,
+ 0b10100,
+ 0b10110,
+ 0b10111,
+ 0b11000,
+ 0b11010,
+};
+
+int arm_decode_adv_simd_mult(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char L = 0, opcode = 0, rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+ int i = 0;
+
+ L = EXTRACT_BIT(instr, 22);
+ opcode = (instr >> 12) & ONES(4);
+
+ decode_field = (L << 4) | opcode;
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+ *type = INSN_OTHER;
+
+ for (i = 0; i < ARRAY_SIZE(adv_simd_mult_fields); i++) {
+ if ((decode_field & 0b11111) == adv_simd_mult_fields[i]) {
+ if (rn != 31)
+ return 0;
+ *type = INSN_STACK;
+ }
+ }
+ if (*type != INSN_STACK)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ if (!L) {
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = 0;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ } else {
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = 0;
+ op->dest.type = OP_SRC_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ }
+
+ return 0;
+}
+
+int arm_decode_adv_simd_mult_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ /* same opcode as for the no offset variant */
+ unsigned char rm = 0;
+ int ret = 0;
+
+ rm = (instr >> 16) & ONES(5);
+
+ ret = arm_decode_adv_simd_mult(instr, type, immediate, op);
+
+ /*
+ * This is actually irrelevant if the offset is given by a register
+ * however there is no way to know the offset value from the encoding
+ * in such a case.
+ */
+ if (op->dest.type == OP_DEST_REG_INDIRECT)
+ op->dest.offset = rm;
+ if (op->src.type == OP_SRC_REG_INDIRECT)
+ op->src.offset = rm;
+ return ret;
+}
+
+static struct aarch64_insn_decoder simd_single_decoder[] = {
+ {
+ .mask = 0b11111000,
+ .value = 0b00000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b00001000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b00010000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b00011000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b00100000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b00100001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b00101000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b00101001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b01000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b01001000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b01010000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b01011000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b01100000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b01100001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b01101000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b01101001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b10000000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b10001000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b10010000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b10011000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b10100000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b10100001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b10101000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b10101001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111100,
+ .value = 0b10110000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111100,
+ .value = 0b10111000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11000000,
+ .value = 0b11111000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111000,
+ .value = 0b11001000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b11010000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b11011000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b11100000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b11100001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b11101000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b11101001,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111100,
+ .value = 0b11110000,
+ .decode_func = NULL,
+ },
+ {
+ .mask = 0b11111100,
+ .value = 0b11111000,
+ .decode_func = NULL,
+ },
+};
+
+int arm_decode_adv_simd_single(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char L = 0, R = 0, S = 0, opcode = 0, size = 0;
+ unsigned char rn = 0, rt = 0, dfield = 0;
+ int i = 0;
+
+ L = EXTRACT_BIT(instr, 22);
+ R = EXTRACT_BIT(instr, 21);
+ S = EXTRACT_BIT(instr, 12);
+ opcode = (instr >> 13) & ONES(3);
+ size = (instr >> 10) & ONES(2);
+
+ dfield = (L << 7) | (R << 6) | (opcode << 3) | (S << 2) | size;
+
+ *type = INSN_OTHER;
+ rn = (instr << 5) & ONES(5);
+
+ for (i = 0; i < ARRAY_SIZE(simd_single_decoder); i++) {
+ if ((dfield & simd_single_decoder[i].mask) ==
+ simd_single_decoder[i].value) {
+ if (rn != CFI_SP)
+ return 0;
+ *type = INSN_STACK;
+ }
+ }
+
+ if (*type == INSN_OTHER)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ rt = instr & ONES(5);
+ if (!L) {
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = 0;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ } else {
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = 0;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ }
+ return 0;
+}
+
+int arm_decode_adv_simd_single_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ /* same opcode as for the no offset variant */
+ unsigned char rm = 0;
+ int ret = 0;
+
+ rm = (instr >> 16) & ONES(5);
+
+ ret = arm_decode_adv_simd_single(instr, type, immediate, op);
+
+ /*
+ * This is actually irrelevant if the offset is given by a register
+ * however there is no way to know the offset value from the encoding
+ * in such a case.
+ */
+ if (op->dest.type == OP_DEST_REG_INDIRECT)
+ op->dest.offset = rm;
+ if (op->src.type == OP_SRC_REG_INDIRECT)
+ op->src.offset = rm;
+ return ret;
+}
+
+int arm_decode_ld_st_mem_tags(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ u32 imm9 = 0;
+ unsigned char opc = 0, op2 = 0, rn = 0, rt = 0, decode_field = 0;
+
+ imm9 = (instr >> 12) & ONES(9);
+ opc = (instr >> 22) & ONES(2);
+ op2 = (instr >> 10) & ONES(2);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(6);
+
+ decode_field = (opc << 2) | op2;
+
+ if (decode_field == 0x0 ||
+ (decode_field == 0x8 && imm9 != 0) ||
+ (decode_field == 0xC && imm9 != 0)) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ *type = INSN_STACK;
+ *immediate = imm9;
+
+ /*
+ * Offset should normally be shifted to the
+ * left of LOG2_TAG_GRANULE
+ */
+ switch (decode_field) {
+ case 1:
+ case 5:
+ case 9:
+ case 13:
+ /* post index */
+ case 3:
+ case 7:
+ case 8:
+ case 11:
+ case 15:
+ /* pre index */
+ op->dest.reg = CFI_SP;
+ op->dest.type = OP_DEST_PUSH;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ op->src.reg = rt;
+ op->src.type = OP_SRC_REG;
+ op->src.offset = 0;
+ return 0;
+ case 2:
+ case 6:
+ case 10:
+ case 14:
+ /* store */
+ op->dest.reg = CFI_SP;
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ op->src.reg = rt;
+ op->src.type = OP_SRC_REG;
+ op->src.offset = 0;
+ return 0;
+ case 4:
+ case 12:
+ /* load */
+ op->src.reg = CFI_SP;
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.offset = SIGN_EXTEND(imm9, 9);
+ op->dest.reg = rt;
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+ return 0;
+ }
+
+ return -1;
+}
+
+#define ST_EXCL_UNALLOC_1 0b001010
+#define ST_EXCL_UNALLOC_2 0b000010
+
+#define LDXRB 0b000100
+#define LDAXRB 0b000101
+#define LDLARB 0b001100
+#define LDARB 0b001101
+#define LDXRH 0b010100
+#define LDAXRH 0b010101
+#define LDLARH 0b011100
+#define LDARH 0b011101
+#define LDXR 0b100100
+#define LDAXR 0b100101
+#define LDXP 0b100110
+#define LDAXP 0b100111
+#define LDLAR 0b101100
+#define LDAR 0b101101
+#define LDXR_64 0b110100
+#define LDAXR_64 0b110101
+#define LDXP_64 0b110110
+#define LDAXP_64 0b110111
+#define LDLAR_64 0b111100
+#define LDAR_64 0b111101
+
+#define LD_EXCL_NUMBER 20
+
+static int ld_excl_masks[] = {
+ LDXRB,
+ LDAXRB,
+ LDLARB,
+ LDARB,
+ LDXRH,
+ LDAXRH,
+ LDLARH,
+ LDARH,
+ LDXR,
+ LDAXR,
+ LDXP,
+ LDAXP,
+ LDLAR,
+ LDAR,
+ LDXR_64,
+ LDAXR_64,
+ LDXP_64,
+ LDAXP_64,
+ LDLAR_64,
+ LDAR_64,
+};
+
+int arm_decode_ld_st_exclusive(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char size = 0, o2 = 0, L = 0, o1 = 0, o0 = 0;
+ unsigned char rt = 0, rt2 = 0, rn = 0;
+ unsigned char decode_field = 0;
+ int i = 0;
+
+ size = (instr >> 30) & ONES(2);
+ o2 = EXTRACT_BIT(instr, 23);
+ L = EXTRACT_BIT(instr, 22);
+ o1 = EXTRACT_BIT(instr, 21);
+ o0 = EXTRACT_BIT(instr, 15);
+
+ rt2 = (instr >> 10) & ONES(5);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+
+ decode_field = (size << 4) | (o2 << 3) | (L << 2) | (o1 << 1) | o0;
+
+ if ((decode_field & ST_EXCL_UNALLOC_1) == ST_EXCL_UNALLOC_1 ||
+ (decode_field & 0b101010) == ST_EXCL_UNALLOC_2) {
+ if (rt2 != 31)
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+ if (rn != 31) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+
+ *type = INSN_STACK;
+ for (i = 0; i < LD_EXCL_NUMBER; i++) {
+ if ((decode_field & 0b111111) == ld_excl_masks[i]) {
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = 0;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ return 0;
+ }
+ }
+
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = 0;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+
+ return 0;
+}
+
+#undef ST_EXCL_UNALLOC_1
+#undef ST_EXCL_UNALLOC_2
+
+#undef LD_EXCL_NUMBER
+
+#undef LDXRB
+#undef LDAXRB
+#undef LDLARB
+#undef LDARB
+#undef LDXRH
+#undef LDAXRH
+#undef LDLARH
+#undef LDARH
+#undef LDXR
+#undef LDAXR
+#undef LDXP
+#undef LDAXP
+#undef LDLAR
+#undef LDAR
+#undef LDXR_64
+#undef LDAXR_64
+#undef LDXP_64
+#undef LDAXP_64
+#undef LDLAR_64
+#undef LDAR_64
+
+int arm_decode_ldapr_stlr_unsc_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ u32 imm9 = 0;
+ unsigned char size = 0, opc = 0, rn = 0, rt = 0, decode_field = 0;
+
+ imm9 = (instr >> 12) & ONES(9);
+ size = (instr >> 30) & ONES(2);
+ opc = (instr >> 22) & ONES(2);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+
+ decode_field = (size << 2) | opc;
+ if (decode_field == 0xB ||
+ decode_field == 0xE ||
+ decode_field == 0xF) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+ if (rn != 31) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ *type = INSN_STACK;
+ *immediate = imm9;
+ switch (decode_field) {
+ case 1:
+ case 2:
+ case 3:
+ case 5:
+ case 6:
+ case 7:
+ case 9:
+ case 10:
+ case 13:
+ /* load */
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = SIGN_EXTEND(imm9, 9);
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ break;
+ default:
+ /* store */
+ op->dest.type = OP_SRC_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ op->src.type = OP_SRC_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ break;
+ }
+
+ return 0;
+}
+
+int arm_decode_ld_regs_literal(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char opc = 0, V = 0;
+
+ opc = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+
+ if (((opc << 1) | V) == 0x7)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_ld_st_noalloc_pair_off(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ unsigned char opc = 0, V = 0, L = 0;
+ unsigned char decode_field = 0;
+
+ opc = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ L = EXTRACT_BIT(instr, 22);
+
+ decode_field = (opc << 2) | (V << 1) | L;
+
+ if (decode_field == 0x4 ||
+ decode_field == 0x5 ||
+ decode_field >= 12) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+ return arm_decode_ld_st_regs_pair_off(instr, type, immediate, op);
+}
+
+int arm_decode_ld_st_regs_pair_off(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ unsigned char opc = 0, V = 0, L = 0, bit = 0;
+ unsigned char imm7 = 0, rt2 = 0, rt = 0, rn = 0;
+ unsigned char decode_field = 0;
+ int scale = 0;
+
+ opc = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ L = EXTRACT_BIT(instr, 22);
+ imm7 = (instr >> 15) & ONES(7);
+ rt2 = (instr >> 10) & ONES(5);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+ bit = EXTRACT_BIT(opc, 1);
+ scale = 2 + bit;
+
+ decode_field = (opc << 2) | (V << 1) | L;
+
+ if (decode_field >= 0xC)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *immediate = (SIGN_EXTEND(imm7, 7)) << scale;
+
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+
+ *type = INSN_STACK;
+
+ switch (decode_field) {
+ case 1:
+ case 3:
+ case 5:
+ case 7:
+ case 9:
+ case 11:
+ /* load */
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = 0;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ op->extra.used = 1;
+ op->extra.reg = rt2;
+ op->extra.offset = 8;
+ break;
+ default:
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = 8;
+ op->src.type = OP_SRC_REG;
+ op->src.reg = rt2;
+ op->src.offset = 0;
+ op->extra.used = 1;
+ op->extra.reg = rt;
+ op->extra.offset = 0;
+ /* store */
+ }
+ return 0;
+}
+
+int arm_decode_ld_st_regs_pair_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ int ret = 0;
+
+ ret = arm_decode_ld_st_regs_pair_off(instr, type, immediate, op);
+ if (ret < 0 || *type == INSN_OTHER)
+ return ret;
+ if (op->dest.type == OP_DEST_REG_INDIRECT) {
+ op->dest.type = OP_DEST_PUSH;
+ op->dest.reg = CFI_SP;
+ }
+
+ if (op->src.type == OP_SRC_REG_INDIRECT) {
+ op->src.type = OP_SRC_POP;
+ op->src.reg = CFI_SP;
+ }
+
+ return ret;
+}
+
+int arm_decode_ld_st_regs_pair_pre(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ return arm_decode_ld_st_regs_pair_post(instr, type, immediate, op);
+}
+
+int arm_decode_ld_st_regs_unsc_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ u32 imm9 = 0;
+ unsigned char size = 0, V = 0, opc = 0, rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ opc = (instr >> 22) & ONES(2);
+
+ imm9 = (instr >> 12) & ONES(9);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+
+ decode_field = (size << 2) | (V << 2) | opc;
+
+ switch (decode_field) {
+ case 0b01110:
+ case 0b01111:
+ case 0b11110:
+ case 0b11111:
+ case 0b10011:
+ case 0b11011:
+ case 0b10110:
+ case 0b10111:
+ return arm_decode_unknown(instr, type, immediate, op);
+ case 26:
+ /* prefetch */
+ *type = INSN_OTHER;
+ return 0;
+ case 1:
+ case 2:
+ case 3:
+ case 5:
+ case 7:
+ case 9:
+ case 10:
+ case 11:
+ case 13:
+ case 17:
+ case 18:
+ case 21:
+ case 25:
+ case 29:
+ /* load */
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = SIGN_EXTEND(imm9, 9);
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ break;
+ default:
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ op->src.type = OP_DEST_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ break;
+ }
+
+ *type = INSN_STACK;
+ return 0;
+}
+
+static struct aarch64_insn_decoder ld_unsig_unalloc_decoder[] = {
+ {
+ .mask = 0b01110,
+ .value = 0b01110,
+ },
+ {
+ .mask = 0b10111,
+ .value = 0b10011,
+ },
+ {
+ .mask = 0b10110,
+ .value = 0b10110,
+ },
+};
+
+int arm_decode_ld_st_regs_unsigned(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ unsigned char size = 0, V = 0, opc = 0, rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+ u32 imm12 = 0;
+ int i = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ opc = (instr >> 22) & ONES(2);
+
+ decode_field = (size << 3) | (V << 2) | opc;
+ for (i = 0; i < ARRAY_SIZE(ld_unsig_unalloc_decoder); i++) {
+ if ((decode_field & ld_unsig_unalloc_decoder[i].mask) ==
+ ld_unsig_unalloc_decoder[i].value) {
+ return arm_decode_unknown(instr, type,
+ immediate, op);
+ }
+ }
+
+ imm12 = (instr >> 10) & ONES(12);
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+
+ if (rn != CFI_SP || decode_field == 26) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+
+ *type = INSN_STACK;
+
+ switch (decode_field) {
+ case 1:
+ case 2:
+ case 3:
+ case 5:
+ case 7:
+ case 9:
+ case 10:
+ case 11:
+ case 13:
+ case 17:
+ case 18:
+ case 21:
+ case 25:
+ /* load */
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = imm12;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ break;
+ default: /* store */
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = imm12;
+ op->src.type = OP_DEST_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ }
+
+ return 0;
+}
+
+int arm_decode_ld_st_imm_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ unsigned char size = 0, V = 0, opc = 0;
+ unsigned char decode_field = 0;
+ u32 imm9 = 0;
+ int ret = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ opc = (instr >> 22) & ONES(2);
+
+ imm9 = (instr >> 12) & ONES(9);
+
+ decode_field = (size << 2) | (V << 2) | opc;
+
+ if (decode_field == 0b11010)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ ret = arm_decode_ld_st_regs_unsigned(instr, type, immediate, op);
+ if (ret < 0 || *type == INSN_OTHER)
+ return ret;
+
+ if (op->dest.type == OP_DEST_REG_INDIRECT) {
+ op->dest.type = OP_DEST_PUSH;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ }
+
+ if (op->src.type == OP_SRC_REG_INDIRECT) {
+ op->src.type = OP_SRC_POP;
+ op->src.reg = CFI_SP;
+ op->src.offset = SIGN_EXTEND(imm9, 9);
+ }
+
+ return 0;
+}
+
+int arm_decode_ld_st_imm_pre(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ return arm_decode_ld_st_imm_post(instr, type, immediate, op);
+}
+
+#define LD_UNPR_UNALLOC_1 0b10011
+#define LD_UNPR_UNALLOC_2 0b11010
+int arm_decode_ld_st_imm_unpriv(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char size = 0, V = 0, opc = 0, rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+ u32 imm9 = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ opc = (instr >> 22) & ONES(2);
+
+ imm9 = (instr >> 12) & ONES(9);
+
+ decode_field = (size << 3) | (V << 2) | opc;
+ if (V == 1 ||
+ (decode_field & 0b10111) == LD_UNPR_UNALLOC_1 ||
+ (decode_field & 0b11111) == LD_UNPR_UNALLOC_2) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+#undef LD_UNPR_UNALLOC_1
+#undef LD_UNPR_UNALLOC_2
+
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ *type = INSN_STACK;
+
+ switch (decode_field) {
+ case 1:
+ case 2:
+ case 3:
+ case 9:
+ case 10:
+ case 11:
+ case 17:
+ case 18:
+ case 25:
+ /* load */
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = SIGN_EXTEND(imm9, 9);
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ break;
+ default:
+ /* store */
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = SIGN_EXTEND(imm9, 9);
+ op->src.type = OP_DEST_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ break;
+ }
+ return 0;
+}
+
+static struct aarch64_insn_decoder atom_unallocs_decoder[] = {
+ {
+ .mask = 0b1001111,
+ .value = 0b0001001,
+ },
+ {
+ .mask = 0b1001110,
+ .value = 0b0001010,
+ },
+ {
+ .mask = 0b1001111,
+ .value = 0b0001101,
+ },
+ {
+ .mask = 0b1001110,
+ .value = 0b0001110,
+ },
+ {
+ .mask = 0b1101111,
+ .value = 0b0001100,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0111100,
+ },
+ {
+ .mask = 0b1000000,
+ .value = 0b1000000,
+ },
+};
+
+int arm_decode_atomic(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op)
+{
+ unsigned char V = 0, A = 0, R = 0, o3 = 0, opc = 0;
+ unsigned char rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+ int i = 0;
+
+ V = EXTRACT_BIT(instr, 26);
+ A = EXTRACT_BIT(instr, 23);
+ R = EXTRACT_BIT(instr, 22);
+ o3 = EXTRACT_BIT(instr, 15);
+ opc = (instr >> 12) & ONES(3);
+
+ decode_field = (V << 6) | (A << 5) | (R << 4) | (o3 << 3) | opc;
+
+ for (i = 0; i < ARRAY_SIZE(atom_unallocs_decoder); i++) {
+ if ((decode_field & atom_unallocs_decoder[i].mask) ==
+ atom_unallocs_decoder[i].value) {
+ return arm_decode_unknown(instr,
+ type,
+ immediate,
+ op);
+ }
+ }
+
+ rn = (instr >> 5) & ONES(5);
+ rt = instr & ONES(5);
+
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+ *type = INSN_STACK;
+ op->src.reg = CFI_SP;
+ op->src.type = OP_DEST_REG_INDIRECT;
+ op->src.offset = 0;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+
+ return 0;
+}
+
+int arm_decode_ld_st_regs_off(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char size = 0, V = 0, opc = 0, option = 0;
+ unsigned char rm = 0, rn = 0, rt = 0;
+ unsigned char decode_field = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ opc = (instr >> 22) & ONES(2);
+ option = (instr >> 13) & ONES(3);
+
+#define LD_ROFF_UNALLOC_1 0b01110
+#define LD_ROFF_UNALLOC_2 0b10110
+#define LD_ROFF_UNALLOC_3 0b10011
+ decode_field = (size << 3) | (V << 2) | opc;
+ if (!EXTRACT_BIT(option, 1) ||
+ (decode_field & LD_ROFF_UNALLOC_1) == LD_ROFF_UNALLOC_1 ||
+ (decode_field & LD_ROFF_UNALLOC_2) == LD_ROFF_UNALLOC_2 ||
+ (decode_field & 0b10111) == LD_ROFF_UNALLOC_3) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+#undef LD_ROFF_UNALLOC_1
+#undef LD_ROFF_UNALLOC_2
+#undef LD_ROFF_UNALLOC_3
+
+ rn = (instr >> 5) & ONES(5);
+
+#define LD_ROFF_PRFM 0b11010
+ if (rn != CFI_SP || decode_field == LD_ROFF_PRFM) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+#undef LD_ROFF_PRFM
+
+ rt = instr & ONES(5);
+ rm = (instr >> 16) & ONES(5);
+
+ switch (decode_field & ONES(3)) {
+ case 0b001:
+ case 0b010:
+ case 0b011:
+ case 0b101:
+ case 0b111:
+ /* load */
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ op->src.offset = rm;
+ op->dest.type = OP_DEST_REG;
+ op->dest.reg = rt;
+ op->dest.offset = 0;
+ break;
+ default:
+ /* store */
+ op->dest.type = OP_DEST_REG_INDIRECT;
+ op->dest.reg = CFI_SP;
+ op->dest.offset = rm;
+ op->src.type = OP_DEST_REG;
+ op->src.reg = rt;
+ op->src.offset = 0;
+ break;
+ }
+
+ return 0;
+}
+
+int arm_decode_ld_st_regs_pac(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char size = 0, V = 0, W = 0, S = 0;
+ unsigned char rn = 0, rt = 0;
+ u32 imm9 = 0, s10 = 0;
+
+ size = (instr >> 30) & ONES(2);
+ V = EXTRACT_BIT(instr, 26);
+ W = EXTRACT_BIT(instr, 11);
+
+ if (size != 3 || V == 1)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ rn = (instr >> 5) & ONES(5);
+
+ if (rn != CFI_SP) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+
+ S = EXTRACT_BIT(instr, 22);
+ s10 = (S << 9) | imm9;
+
+ op->dest.reg = rt;
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+ op->src.offset = (SIGN_EXTEND(s10, 9) << 3);
+ if (W) { /* pre-indexed/writeback */
+ op->src.type = OP_SRC_POP;
+ op->src.reg = CFI_SP;
+ } else {
+ op->src.type = OP_SRC_REG_INDIRECT;
+ op->src.reg = CFI_SP;
+ }
+
+ return 0;
+}
+
+static struct aarch64_insn_decoder dp_reg_decoder[] = {
+ {
+ .mask = 0b111111000000,
+ .value = 0b010110000000,
+ .decode_func = arm_decode_dp_reg_2src,
+ },
+ {
+ .mask = 0b111111000000,
+ .value = 0b110110000000,
+ .decode_func = arm_decode_dp_reg_1src,
+ },
+ {
+ .mask = 0b011000000000,
+ .value = 0b000000000000,
+ .decode_func = arm_decode_dp_reg_logi,
+ },
+ {
+ .mask = 0b011001000000,
+ .value = 0b001000000000,
+ .decode_func = arm_decode_dp_reg_adds,
+ },
+ {
+ .mask = 0b011001000000,
+ .value = 0b001001000000,
+ .decode_func = arm_decode_dp_reg_adde,
+ },
+ {
+ .mask = 0b011111111111,
+ .value = 0b010000000000,
+ .decode_func = arm_decode_dp_reg_addc,
+ },
+ {
+ .mask = 0b011111011111,
+ .value = 0b010000000001,
+ .decode_func = arm_decode_dp_reg_rota,
+ },
+ {
+ .mask = 0b011111001111,
+ .value = 0b010000000010,
+ .decode_func = arm_decode_dp_reg_eval,
+ },
+ {
+ .mask = 0b011111000010,
+ .value = 0b010010000000,
+ .decode_func = arm_decode_dp_reg_cmpr,
+ },
+ {
+ .mask = 0b011111000010,
+ .value = 0b010010000010,
+ .decode_func = arm_decode_dp_reg_cmpi,
+ },
+ {
+ .mask = 0b011111000000,
+ .value = 0b010100000000,
+ .decode_func = arm_decode_dp_reg_csel,
+ },
+ {
+ .mask = 0b011000000000,
+ .value = 0b011000000000,
+ .decode_func = arm_decode_dp_reg_3src,
+ },
+};
+
+int arm_decode_dp_reg(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char op0 = 0, op1 = 0, op2 = 0, op3 = 0;
+ u32 decode_field = 0;
+ int i = 0;
+
+ op0 = EXTRACT_BIT(instr, 30);
+ op1 = EXTRACT_BIT(instr, 28);
+ op2 = (instr >> 21) & ONES(4);
+ op3 = (instr >> 10) & ONES(6);
+ decode_field = (op0 << 5) | (op1 << 4) | op2;
+ decode_field = (decode_field << 6) | op3;
+
+ for (i = 0; i < ARRAY_SIZE(dp_reg_decoder); i++) {
+ if ((decode_field & dp_reg_decoder[i].mask) ==
+ dp_reg_decoder[i].value) {
+ return dp_reg_decoder[i].decode_func(instr, type,
+ immediate, op);
+ }
+ }
+ return arm_decode_unknown(instr, type, immediate, op);
+}
+
+static struct aarch64_insn_decoder dp_reg_2src_decoder[] = {
+ {
+ .mask = 0b00111111,
+ .value = 0b00000001,
+ },
+ {
+ .mask = 0b00111000,
+ .value = 0b00011000,
+ },
+ {
+ .mask = 0b00100000,
+ .value = 0b00100000,
+ },
+ {
+ .mask = 0b01111111,
+ .value = 0b00000101,
+ },
+ {
+ .mask = 0b01111100,
+ .value = 0b00001100,
+ },
+ {
+ .mask = 0b01111110,
+ .value = 0b01000010,
+ },
+ {
+ .mask = 0b01111100,
+ .value = 0b01000100,
+ },
+ {
+ .mask = 0b01111000,
+ .value = 0b01001000,
+ },
+ {
+ .mask = 0b01110000,
+ .value = 0b01010000,
+ },
+ {
+ .mask = 0b10111111,
+ .value = 0b00000000,
+ },
+ {
+ .mask = 0b11111111,
+ .value = 0b00000100,
+ },
+ {
+ .mask = 0b11111110,
+ .value = 0b00000110,
+ },
+ {
+ .mask = 0b11111011,
+ .value = 0b00010011,
+ },
+ {
+ .mask = 0b11111001,
+ .value = 0b10010000,
+ },
+ {
+ .mask = 0b11111010,
+ .value = 0b10010000,
+ },
+};
+
+static int dp_reg_2src_stack_fields[] = {
+ 0b10000000,
+ 0b10000100,
+ 0b10000101,
+ 0b10001100,
+ 0b11000000,
+};
+
+int arm_decode_dp_reg_2src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, S = 0, opcode = 0, rn = 0, rd = 0;
+ unsigned char decode_field = 0;
+ int i = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ S = EXTRACT_BIT(instr, 29);
+ opcode = (instr >> 10) & ONES(6);
+
+ decode_field = (sf << 7) | (S << 6) | opcode;
+
+ for (i = 0; i < ARRAY_SIZE(dp_reg_2src_decoder); i++) {
+ if ((decode_field & dp_reg_2src_decoder[i].mask) ==
+ dp_reg_2src_decoder[i].value) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+ }
+
+ *type = 0;
+ for (i = 0; i < ARRAY_SIZE(dp_reg_2src_stack_fields); i++) {
+ if (opcode == dp_reg_2src_stack_fields[i]) {
+ *type = INSN_OTHER;
+ break;
+ }
+ }
+ if (*type == 0) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+
+ rn = (instr >> 5) & ONES(5);
+ rd = instr & ONES(5);
+
+#define IRG_OPCODE 0b10000100
+ if ((rn != CFI_SP && opcode != IRG_OPCODE) ||
+ (opcode == IRG_OPCODE && rd != CFI_SP &&
+ rn != CFI_SP)) {
+ *type = INSN_OTHER;
+ return 0;
+ }
+#undef IRG_OPCODE
+
+ *type = INSN_STACK;
+ op->dest.reg = rd;
+ op->dest.type = OP_DEST_REG;
+ op->dest.offset = 0;
+
+ op->src.reg = rn;
+ op->src.type = OP_DEST_REG;
+ op->src.offset = 0;
+
+ return 0;
+}
+
+static struct aarch64_insn_decoder dp_reg_1src_decoder[] = {
+ {
+ .mask = 0b0000000001000,
+ .value = 0b0000000001000,
+ },
+ {
+ .mask = 0b0000000010000,
+ .value = 0b0000000010000,
+ },
+ {
+ .mask = 0b0000000100000,
+ .value = 0b0000000100000,
+ },
+ {
+ .mask = 0b0000001000000,
+ .value = 0b0000001000000,
+ },
+ {
+ .mask = 0b0000010000000,
+ .value = 0b0000010000000,
+ },
+ {
+ .mask = 0b0000100000000,
+ .value = 0b0000100000000,
+ },
+ {
+ .mask = 0b0001000000000,
+ .value = 0b0001000000000,
+ },
+ {
+ .mask = 0b0010000000000,
+ .value = 0b0010000000000,
+ },
+ {
+ .mask = 0b0111111111110,
+ .value = 0b0000000000110,
+ },
+ {
+ .mask = 0b0100000000000,
+ .value = 0b0100000000000,
+ },
+};
+
+int arm_decode_dp_reg_1src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, S = 0, opcode2 = 0, opcode = 0;
+ u32 decode_field = 0;
+ int i = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ S = EXTRACT_BIT(instr, 29);
+ opcode2 = (instr >> 16) & ONES(5);
+ opcode = (instr >> 10) & ONES(6);
+
+ decode_field = (sf << 6) | (S << 5) | opcode2;
+ decode_field = (decode_field << 6) | opcode;
+
+ for (i = 0; i < ARRAY_SIZE(dp_reg_1src_decoder); i++) {
+ if ((decode_field & dp_reg_1src_decoder[i].mask) ==
+ dp_reg_1src_decoder[i].value) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+ }
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_logi(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, imm6 = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ imm6 = (instr >> 10) & ONES(6);
+
+ if (imm6 >= 0b100000 && !sf)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_adds(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, shift = 0, imm6 = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ shift = (instr >> 22) & ONES(2);
+ imm6 = (instr >> 10) & ONES(6);
+
+ if ((imm6 >= 0b100000 && !sf) || shift == 0b11)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_adde(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char S = 0, opt = 0, imm3 = 0, rn = 0, rd = 0;
+
+ S = EXTRACT_BIT(instr, 29);
+ opt = (instr >> 22) & ONES(2);
+ imm3 = (instr >> 10) & ONES(3);
+ rn = (instr >> 5) & ONES(5);
+ rd = instr & ONES(5);
+
+ if (opt != 0 || imm3 >= 0b101)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ if (rd == CFI_SP && S == 0) {
+ *type = INSN_STACK;
+ op->dest.reg = CFI_SP;
+ op->dest.type = OP_DEST_REG;
+ op->src.type = OP_SRC_ADD;
+ op->src.reg = rn;
+
+ return 0;
+ }
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_addc(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_rota(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, S = 0, op_bit = 0, o2 = 0;
+ unsigned char decode_field = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ op_bit = EXTRACT_BIT(instr, 30);
+ S = EXTRACT_BIT(instr, 29);
+ o2 = EXTRACT_BIT(instr, 4);
+
+ decode_field = (sf << 3) | (op_bit << 2) | (S << 1) | o2;
+
+ if (decode_field != 0b1010)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_eval(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, S = 0, op_bit = 0, o3 = 0, sz = 0;
+ unsigned char opcode2 = 0, mask = 0;
+ u32 decode_field = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ op_bit = EXTRACT_BIT(instr, 30);
+ S = EXTRACT_BIT(instr, 29);
+ sz = EXTRACT_BIT(instr, 14);
+ o3 = EXTRACT_BIT(instr, 4);
+
+ opcode2 = (instr >> 15) & ONES(6);
+ mask = instr & ONES(4);
+
+ decode_field = (sf << 2) | (op_bit << 1) | S;
+ decode_field = (decode_field << 12) | (opcode2 << 6) | (sz << 5);
+ decode_field |= (o3 << 4) | mask;
+
+#define DP_EVAL_SETF_1 0b001000000001101
+#define DP_EVAL_SETF_2 0b001000000101101
+
+ if (decode_field != DP_EVAL_SETF_1 &&
+ decode_field != DP_EVAL_SETF_2) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+ *type = INSN_OTHER;
+ return 0;
+#undef DP_EVAL_SETF_1
+#undef DP_EVAL_SETF_2
+}
+
+int arm_decode_dp_reg_cmpr(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char S = 0, o2 = 0, o3 = 0;
+
+ S = EXTRACT_BIT(instr, 29);
+ o2 = EXTRACT_BIT(instr, 10);
+ o3 = EXTRACT_BIT(instr, 4);
+
+ if (!S || o2 || o3)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_csel(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char S = 0, op2 = 0;
+
+ S = EXTRACT_BIT(instr, 29);
+ op2 = (instr >> 10) & ONES(2);
+
+ if (S || op2 >= 0b10)
+ return arm_decode_unknown(instr, type, immediate, op);
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+int arm_decode_dp_reg_cmpi(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ return arm_decode_dp_reg_cmpr(instr, type, immediate, op);
+}
+
+static int dp_reg_3src_fields[] = {
+};
+
+static struct aarch64_insn_decoder dp_reg_3src_decoder[] = {
+ {
+ .mask = 0b0111111,
+ .value = 0b0000101,
+ },
+ {
+ .mask = 0b0111110,
+ .value = 0b0000110,
+ },
+ {
+ .mask = 0b0111110,
+ .value = 0b0001000,
+ },
+ {
+ .mask = 0b0111111,
+ .value = 0b0001101,
+ },
+ {
+ .mask = 0b0111110,
+ .value = 0b0001110,
+ },
+ {
+ .mask = 0b0110000,
+ .value = 0b0010000,
+ },
+ {
+ .mask = 0b0100000,
+ .value = 0b0100000,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0000010,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0000011,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0000100,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0001010,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0001011,
+ },
+ {
+ .mask = 0b1111111,
+ .value = 0b0001100,
+ },
+};
+
+int arm_decode_dp_reg_3src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ unsigned char sf = 0, op54 = 0, op31 = 0, o0 = 0;
+ unsigned char decode_field = 0;
+ int i = 0;
+
+ sf = EXTRACT_BIT(instr, 31);
+ op54 = (instr >> 29) & ONES(2);
+ op31 = (instr >> 21) & ONES(3);
+ o0 = EXTRACT_BIT(instr, 15);
+
+ decode_field = (sf << 6) | (op54 << 4) | (op31 << 1) | o0;
+
+ for (i = 0; i < ARRAY_SIZE(dp_reg_3src_fields); i++) {
+ if ((decode_field & dp_reg_3src_decoder[i].mask) ==
+ dp_reg_3src_decoder[i].value) {
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+ }
+
+ *type = INSN_OTHER;
+ return 0;
+}
+
+unsigned long arch_jump_destination(struct instruction *insn)
+{
+ return insn->offset + insn->immediate;
+}
+
+static struct aarch64_insn_decoder sve_enc_decoder[] = {
+ {
+ .mask = 0b1111010000111000,
+ .value = 0b0000010000011000,
+ },
+ {
+ .mask = 0b1111110000111000,
+ .value = 0b0001110000000000,
+ },
+ {
+ .mask = 0b1111010000110000,
+ .value = 0b0011010000010000,
+ },
+ {
+ .mask = 0b1111011100111000,
+ .value = 0b0011010100101000,
+ },
+ {
+ .mask = 0b1111011000110000,
+ .value = 0b0011011000100000,
+ },
+ {
+ .mask = 0b1111010000100000,
+ .value = 0b0100000000100000,
+ },
+ {
+ .mask = 0b1111000000000000,
+ .value = 0b0101000000000000,
+ },
+ {
+ .mask = 0b1111011111111000,
+ .value = 0b0110000000101000,
+ },
+ {
+ .mask = 0b1111011111110000,
+ .value = 0b0110000000110000,
+ },
+ {
+ .mask = 0b1111011111100000,
+ .value = 0b0110000001100000,
+ },
+ {
+ .mask = 0b1111011110100000,
+ .value = 0b0110000010100000,
+ },
+ {
+ .mask = 0b1111011100100000,
+ .value = 0b0110000100100000,
+ },
+ {
+ .mask = 0b1111011000100000,
+ .value = 0b0110001000100000,
+ },
+ {
+ .mask = 0b1111010000110110,
+ .value = 0b0110010000000010,
+ },
+ {
+ .mask = 0b1111010000111111,
+ .value = 0b0110010000001001,
+ },
+ {
+ .mask = 0b1111010000111100,
+ .value = 0b0110010000001100,
+ },
+ {
+ .mask = 0b1111010000110000,
+ .value = 0b0110010000010000,
+ },
+ {
+ .mask = 0b1111010000100000,
+ .value = 0b0110010000100000,
+ },
+ {
+ .mask = 0b1111011100111100,
+ .value = 0b0111000100001000,
+ },
+};
+
+/*
+ * Since these instructions are optional (not present on all arm processors)
+ * we consider that they will never be used to save/restore stack frame.
+ */
+int arm_decode_sve_encoding(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op)
+{
+ int i = 0;
+ unsigned char op0 = 0, op1 = 0, op2 = 0, op3 = 0;
+ u32 decode_field = 0;
+
+ op0 = (instr >> 29) & ONES(3);
+ op1 = (instr >> 23) & ONES(2);
+ op2 = (instr >> 17) & ONES(5);
+ op3 = (instr >> 10) & ONES(6);
+
+ decode_field = (op0 << 2) | op1;
+ decode_field = (decode_field << 5) | op2;
+ decode_field = (decode_field << 6) | op3;
+
+ for (i = 0; i < ARRAY_SIZE(sve_enc_decoder); i++) {
+ if ((decode_field & sve_enc_decoder[i].mask) ==
+ sve_enc_decoder[i].value)
+ return arm_decode_unknown(instr, type, immediate, op);
+ }
+
+ *type = INSN_OTHER;
+
+ return 0;
+}
diff --git a/tools/objtool/arch/arm64/include/arch_special.h b/tools/objtool/arch/arm64/include/arch_special.h
new file mode 100644
index 000000000000..63da775d0581
--- /dev/null
+++ b/tools/objtool/arch/arm64/include/arch_special.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _ARM64_ARCH_SPECIAL_H
+#define _ARM64_ARCH_SPECIAL_H
+
+#define EX_ENTRY_SIZE 8
+#define EX_ORIG_OFFSET 0
+#define EX_NEW_OFFSET 4
+
+#define JUMP_ENTRY_SIZE 16
+#define JUMP_ORIG_OFFSET 0
+#define JUMP_NEW_OFFSET 4
+
+#define ALT_ENTRY_SIZE 12
+#define ALT_ORIG_OFFSET 0
+#define ALT_NEW_OFFSET 4
+#define ALT_FEATURE_OFFSET 8
+#define ALT_ORIG_LEN_OFFSET 10
+#define ALT_NEW_LEN_OFFSET 11
+
+#define X86_FEATURE_POPCNT (4 * 32 + 23)
+#define X86_FEATURE_SMAP (9 * 32 + 20)
+
+#endif /* _ARM64_ARCH_SPECIAL_H */
diff --git a/tools/objtool/arch/arm64/include/asm/orc_types.h b/tools/objtool/arch/arm64/include/asm/orc_types.h
new file mode 100644
index 000000000000..9b04885eb785
--- /dev/null
+++ b/tools/objtool/arch/arm64/include/asm/orc_types.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017 Josh Poimboeuf <jpoimboe@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ORC_TYPES_H
+#define _ORC_TYPES_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+/*
+ * The ORC_REG_* registers are base registers which are used to find other
+ * registers on the stack.
+ *
+ * ORC_REG_PREV_SP, also known as DWARF Call Frame Address (CFA), is the
+ * address of the previous frame: the caller's SP before it called the current
+ * function.
+ *
+ * ORC_REG_UNDEFINED means the corresponding register's value didn't change in
+ * the current frame.
+ *
+ * The most commonly used base registers are SP and BP -- which the previous SP
+ * is usually based on -- and PREV_SP and UNDEFINED -- which the previous BP is
+ * usually based on.
+ *
+ * The rest of the base registers are needed for special cases like entry code
+ * and GCC realigned stacks.
+ */
+#define ORC_REG_UNDEFINED 0
+#define ORC_REG_PREV_SP 1
+#define ORC_REG_DX 2
+#define ORC_REG_DI 3
+#define ORC_REG_BP 4
+#define ORC_REG_SP 5
+#define ORC_REG_R10 6
+#define ORC_REG_R13 7
+#define ORC_REG_BP_INDIRECT 8
+#define ORC_REG_SP_INDIRECT 9
+#define ORC_REG_MAX 15
+
+/*
+ * ORC_TYPE_CALL: Indicates that sp_reg+sp_offset resolves to PREV_SP (the
+ * caller's SP right before it made the call). Used for all callable
+ * functions, i.e. all C code and all callable asm functions.
+ *
+ * ORC_TYPE_REGS: Used in entry code to indicate that sp_reg+sp_offset points
+ * to a fully populated pt_regs from a syscall, interrupt, or exception.
+ *
+ * ORC_TYPE_REGS_IRET: Used in entry code to indicate that sp_reg+sp_offset
+ * points to the iret return frame.
+ *
+ * The UNWIND_HINT macros are used only for the unwind_hint struct. They
+ * aren't used in struct orc_entry due to size and complexity constraints.
+ * Objtool converts them to real types when it converts the hints to orc
+ * entries.
+ */
+#define ORC_TYPE_CALL 0
+#define ORC_TYPE_REGS 1
+#define ORC_TYPE_REGS_IRET 2
+#define UNWIND_HINT_TYPE_SAVE 3
+#define UNWIND_HINT_TYPE_RESTORE 4
+
+#ifndef __ASSEMBLY__
+/*
+ * This struct is more or less a vastly simplified version of the DWARF Call
+ * Frame Information standard. It contains only the necessary parts of DWARF
+ * CFI, simplified for ease of access by the in-kernel unwinder. It tells the
+ * unwinder how to find the previous SP and BP (and sometimes entry regs) on
+ * the stack for a given code address. Each instance of the struct corresponds
+ * to one or more code locations.
+ */
+struct orc_entry {
+ s16 sp_offset;
+ s16 bp_offset;
+ unsigned sp_reg:4;
+ unsigned bp_reg:4;
+ unsigned type:2;
+ unsigned end:1;
+} __packed;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ORC_TYPES_H */
diff --git a/tools/objtool/arch/arm64/include/bit_operations.h b/tools/objtool/arch/arm64/include/bit_operations.h
new file mode 100644
index 000000000000..c198c0724b7c
--- /dev/null
+++ b/tools/objtool/arch/arm64/include/bit_operations.h
@@ -0,0 +1,24 @@
+#ifndef _BIT_OPERATIONS_H
+#define _BIT_OPERATIONS_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <linux/types.h>
+
+#define ONES(N) (((__uint128_t)1 << (N)) - 1)
+#define ZERO_EXTEND(X, N) ((X) & ONES(N))
+#define EXTRACT_BIT(X, N) (((X) >> (N)) & ONES(1))
+#define SIGN_EXTEND(X, N) ((((unsigned long)-1 + (EXTRACT_BIT(X, (N) - 1) ^ 1)) << (N)) | X)
+
+u64 replicate(u64 x, int size, int n);
+
+u64 ror(u64 x, int size, int shift);
+
+int highest_set_bit(u32 x);
+
+__uint128_t decode_bit_masks(unsigned char N,
+ unsigned char imms,
+ unsigned char immr,
+ bool immediate);
+
+#endif /* _BIT_OPERATIONS_H */
diff --git a/tools/objtool/arch/arm64/include/cfi.h b/tools/objtool/arch/arm64/include/cfi.h
new file mode 100644
index 000000000000..dbe973c4fe68
--- /dev/null
+++ b/tools/objtool/arch/arm64/include/cfi.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015-2017 Josh Poimboeuf <jpoimboe@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OBJTOOL_CFI_H
+#define _OBJTOOL_CFI_H
+
+#define CFI_UNDEFINED -1
+#define CFI_CFA -2
+#define CFI_SP_INDIRECT -3
+#define CFI_BP_INDIRECT -4
+
+#define CFI_R0 0
+#define CFI_R1 1
+#define CFI_R2 2
+#define CFI_R3 3
+#define CFI_R4 4
+#define CFI_R5 5
+#define CFI_R6 6
+#define CFI_R7 7
+#define CFI_R8 8
+#define CFI_R9 9
+#define CFI_R10 10
+#define CFI_R11 11
+#define CFI_R12 12
+#define CFI_R13 13
+#define CFI_R14 14
+#define CFI_R15 15
+#define CFI_R16 16
+#define CFI_R17 17
+#define CFI_R18 18
+#define CFI_R19 19
+#define CFI_R20 20
+#define CFI_R21 21
+#define CFI_R22 22
+#define CFI_R23 23
+#define CFI_R24 24
+#define CFI_R25 25
+#define CFI_R26 26
+#define CFI_R27 27
+#define CFI_R28 28
+#define CFI_R29 29
+#define CFI_FP CFI_R29
+#define CFI_BP CFI_FP
+#define CFI_R30 30
+#define CFI_LR CFI_R30
+#define CFI_SP 31
+
+#define CFI_NUM_REGS 32
+
+struct cfi_reg {
+ int base;
+ int offset;
+};
+
+struct cfi_state {
+ struct cfi_reg cfa;
+ struct cfi_reg regs[CFI_NUM_REGS];
+};
+
+#endif /* _OBJTOOL_CFI_H */
diff --git a/tools/objtool/arch/arm64/include/insn_decode.h b/tools/objtool/arch/arm64/include/insn_decode.h
new file mode 100644
index 000000000000..eb54fc39dca5
--- /dev/null
+++ b/tools/objtool/arch/arm64/include/insn_decode.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2019 Raphael Gault <raphael.gault@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ARM_INSN_DECODE_H
+#define _ARM_INSN_DECODE_H
+
+#include "../../../arch.h"
+
+#define INSN_RESERVED 0b0000
+#define INSN_UNKNOWN 0b0001
+#define INSN_SVE_ENC 0b0010
+#define INSN_UNALLOC 0b0011
+#define INSN_DP_IMM 0b1001 //0x100x
+#define INSN_BRANCH 0b1011 //0x101x
+#define INSN_LD_ST_4 0b0100 //0bx1x0
+#define INSN_LD_ST_6 0b0110 //0bx1x0
+#define INSN_LD_ST_C 0b1100 //0bx1x0
+#define INSN_LD_ST_E 0b1110 //0bx1x0
+#define INSN_DP_REG_5 0b0101 //0bx101
+#define INSN_DP_REG_D 0b1101 //0bx101
+#define INSN_DP_SIMD_7 0b0111 //0bx111
+#define INSN_DP_SIMD_F 0b1111 //0bx111
+
+#define INSN_PCREL 0b001 //0b00x
+#define INSN_ADD_SUB 0b010
+#define INSN_ADD_TAG 0b011
+#define INSN_LOGICAL 0b100
+#define INSN_MOVE_WIDE 0b101
+#define INSN_BITFIELD 0b110
+#define INSN_EXTRACT 0b111
+
+#define INSN_BR_UNCOND_IMM_L 0b0001
+#define INSN_CP_BR_IMM_L 0b0010
+#define INSN_TST_BR_IMM_L 0b0011
+#define INSN_BR_COND_IMM 0b0100
+#define INSN_BR_UNKNOWN_IMM 0b0111
+#define INSN_BR_UNCOND_IMM_H 0b1001
+#define INSN_CP_BR_IMM_H 0b1010
+#define INSN_TST_BR_IMM_H 0b1011
+#define INSN_BR_SYS_NO_IMM 0b1101
+
+#define INSN_OP1_HINTS 0b01000000110010
+#define INSN_OP1_BARRIERS 0b01000000110011
+
+#define COMPOSED_INSN_REGS_NUM 2
+#define INSN_COMPOSED 1
+
+#define ADR_SOURCE -1
+
+typedef int (*arm_decode_class)(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+struct aarch64_insn_decoder {
+ u32 mask;
+ u32 value;
+ arm_decode_class decode_func;
+};
+
+/* arm64 instruction classes */
+int arm_decode_reserved(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_sve_encoding(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_br_sys(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_simd(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_unknown(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+/* arm64 data processing -- immediate subclasses */
+int arm_decode_pcrel(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_add_sub(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_add_sub_tags(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_logical(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_move_wide(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_bitfield(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_extract(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+/* arm64 branch, exception generation, system insn subclasses */
+int arm_decode_br_uncond_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_br_comp_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_br_tst_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_br_cond_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+int arm_decode_br_uncond_reg(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+int arm_decode_br_reg(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_except_gen(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_hints(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_barriers(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_pstate(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_system_insn(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_system_regs(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+/* arm64 load/store instructions */
+int arm_decode_adv_simd_mult(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_adv_simd_mult_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_adv_simd_single(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_adv_simd_single_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_mem_tags(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ldapr_stlr_unsc_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_regs_literal(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_noalloc_pair_off(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_regs_pair_post(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_regs_pair_off(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_regs_pair_pre(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_regs_unsc_imm(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+int arm_decode_ld_st_imm_post(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_imm_unpriv(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_imm_pre(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_atomic(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_regs_off(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_regs_pac(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_ld_st_regs_unsigned(u32 instr, unsigned char *type,
+ unsigned long *immediate,
+ struct stack_op *op);
+
+int arm_decode_ld_st_exclusive(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+
+/* arm64 data processing -- registers instructions */
+int arm_decode_dp_reg_1src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_2src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_3src(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_adde(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_cmpi(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_eval(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_cmpr(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_rota(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_csel(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_addc(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_adds(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+int arm_decode_dp_reg_logi(u32 instr, unsigned char *type,
+ unsigned long *immediate, struct stack_op *op);
+#endif /* _ARM_INSN_DECODE_H */
diff --git a/tools/objtool/arch/arm64/orc_dump.c b/tools/objtool/arch/arm64/orc_dump.c
new file mode 100644
index 000000000000..d1dc39829c9e
--- /dev/null
+++ b/tools/objtool/arch/arm64/orc_dump.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2017 Josh Poimboeuf <jpoimboe@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <unistd.h>
+#include "../../orc.h"
+#include "../../warn.h"
+
+int orc_dump(const char *_objname)
+{
+ WARN("arm64 architecture does not yet support orc");
+ return -1;
+}
diff --git a/tools/objtool/arch/arm64/orc_gen.c b/tools/objtool/arch/arm64/orc_gen.c
new file mode 100644
index 000000000000..81383d34a743
--- /dev/null
+++ b/tools/objtool/arch/arm64/orc_gen.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2017 Josh Poimboeuf <jpoimboe@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../orc.h"
+#include "../../check.h"
+#include "../../warn.h"
+
+int arch_create_orc(struct objtool_file *file)
+{
+ WARN("arm64 architecture does not yet support orc");
+ return -1;
+}
+
+int arch_create_orc_sections(struct objtool_file *file)
+{
+ WARN("arm64 architecture does not yet support orc");
+ return -1;
+}
+
+int arch_orc_read_unwind_hints(struct objtool_file *file)
+{
+ return 0;
+}
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [RFC v4 09/18] gcc-plugins: objtool: Add plugin to detect switch table on arm64
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
This plugins comes into play before the final 2 RTL passes of GCC and
detects switch-tables that are to be outputed in the ELF and writes
information in an "objtool_data" section which will be used by objtool.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
scripts/Makefile.gcc-plugins | 2 +
scripts/gcc-plugins/Kconfig | 9 +++
.../arm64_switch_table_detection_plugin.c | 58 +++++++++++++++++++
3 files changed, 69 insertions(+)
create mode 100644 scripts/gcc-plugins/arm64_switch_table_detection_plugin.c
diff --git a/scripts/Makefile.gcc-plugins b/scripts/Makefile.gcc-plugins
index 5f7df50cfe7a..a56736df9dc2 100644
--- a/scripts/Makefile.gcc-plugins
+++ b/scripts/Makefile.gcc-plugins
@@ -44,6 +44,8 @@ ifdef CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK
endif
export DISABLE_ARM_SSP_PER_TASK_PLUGIN
+gcc-plugin-$(CONFIG_GCC_PLUGIN_SWITCH_TABLES) += arm64_switch_table_detection_plugin.so
+
# All the plugin CFLAGS are collected here in case a build target needs to
# filter them out of the KBUILD_CFLAGS.
GCC_PLUGINS_CFLAGS := $(strip $(addprefix -fplugin=$(objtree)/scripts/gcc-plugins/, $(gcc-plugin-y)) $(gcc-plugin-cflags-y))
diff --git a/scripts/gcc-plugins/Kconfig b/scripts/gcc-plugins/Kconfig
index d33de0b9f4f5..1daeffb55dce 100644
--- a/scripts/gcc-plugins/Kconfig
+++ b/scripts/gcc-plugins/Kconfig
@@ -113,4 +113,13 @@ config GCC_PLUGIN_ARM_SSP_PER_TASK
bool
depends on GCC_PLUGINS && ARM
+config GCC_PLUGIN_SWITCH_TABLES
+ bool "GCC Plugin: Identify switch tables at compile time"
+ default y
+ depends on STACK_VALIDATION && ARM64
+ help
+ Plugin to identify switch tables generated at compile time and store
+ them in a .objtool_data section. Objtool will then use that section
+ to analyse the different execution path of the switch table.
+
endmenu
diff --git a/scripts/gcc-plugins/arm64_switch_table_detection_plugin.c b/scripts/gcc-plugins/arm64_switch_table_detection_plugin.c
new file mode 100644
index 000000000000..d7f0e13910d5
--- /dev/null
+++ b/scripts/gcc-plugins/arm64_switch_table_detection_plugin.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <stdio.h>
+#include "gcc-common.h"
+
+__visible int plugin_is_GPL_compatible;
+
+static unsigned int arm64_switchtbl_rtl_execute(void)
+{
+ rtx_insn *insn;
+ rtx_insn *labelp = NULL;
+ rtx_jump_table_data *tablep = NULL;
+ section *sec = get_section(".objtool_data", SECTION_STRINGS, NULL);
+ section *curr_sec = current_function_section();
+
+ for (insn = get_insns(); insn; insn = NEXT_INSN(insn)) {
+ /*
+ * Find a tablejump_p INSN (using a dispatch table)
+ */
+ if (!tablejump_p(insn, &labelp, &tablep))
+ continue;
+
+ if (labelp && tablep) {
+ switch_to_section(sec);
+ assemble_integer_with_op(".quad ", gen_rtx_LABEL_REF(Pmode, labelp));
+ assemble_integer_with_op(".quad ", GEN_INT(GET_NUM_ELEM(tablep->get_labels())));
+ assemble_integer_with_op(".quad ", GEN_INT(ADDR_DIFF_VEC_FLAGS(tablep).offset_unsigned));
+ switch_to_section(curr_sec);
+ }
+ }
+ return 0;
+}
+
+#define PASS_NAME arm64_switchtbl_rtl
+
+#define NO_GATE
+#include "gcc-generate-rtl-pass.h"
+
+__visible int plugin_init(struct plugin_name_args *plugin_info,
+ struct plugin_gcc_version *version)
+{
+ const char * const plugin_name = plugin_info->base_name;
+ int tso = 0;
+ int i;
+
+ if (!plugin_default_version_check(version, &gcc_version)) {
+ error(G_("incompatible gcc/plugin versions"));
+ return 1;
+ }
+
+ PASS_INFO(arm64_switchtbl_rtl, "outof_cfglayout", 1,
+ PASS_POS_INSERT_AFTER);
+
+ register_callback(plugin_info->base_name, PLUGIN_PASS_MANAGER_SETUP,
+ NULL, &arm64_switchtbl_rtl_pass_info);
+
+ return 0;
+}
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [RFC v4 08/18] objtool: Refactor switch-tables code to support other architectures
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
The way to identify switch-tables and retrieves all the data necessary
to handle the different execution branches is not the same on all
architecture. In order to be able to add other architecture support,
this patch defines arch-dependent functions to process jump-tables.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch/arm64/arch_special.c | 15 ++++
tools/objtool/arch/arm64/decode.c | 4 +-
tools/objtool/arch/x86/arch_special.c | 79 ++++++++++++++++++++
tools/objtool/check.c | 95 +------------------------
tools/objtool/check.h | 7 ++
tools/objtool/special.h | 10 ++-
6 files changed, 114 insertions(+), 96 deletions(-)
diff --git a/tools/objtool/arch/arm64/arch_special.c b/tools/objtool/arch/arm64/arch_special.c
index a21d28876317..17a8a06aac2a 100644
--- a/tools/objtool/arch/arm64/arch_special.c
+++ b/tools/objtool/arch/arm64/arch_special.c
@@ -20,3 +20,18 @@ void arch_force_alt_path(unsigned short feature,
struct special_alt *alt)
{
}
+
+int arch_add_jump_table(struct objtool_file *file, struct instruction *insn,
+ struct rela *table, struct rela *next_table)
+{
+ return 0;
+}
+
+struct rela *arch_find_switch_table(struct objtool_file *file,
+ struct rela *text_rela,
+ struct section *rodata_sec,
+ unsigned long table_offset)
+{
+ file->ignore_unreachables = true;
+ return NULL;
+}
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 4cb9402d6fe1..a20725c1bfd7 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -159,7 +159,7 @@ static int is_arm64(struct elf *elf)
int arch_decode_instruction(struct elf *elf, struct section *sec,
unsigned long offset, unsigned int maxlen,
- unsigned int *len, unsigned char *type,
+ unsigned int *len, enum insn_type *type,
unsigned long *immediate, struct stack_op *op)
{
int arm64 = 0;
@@ -184,7 +184,7 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
insn = *(u32 *)(sec->data->d_buf + offset);
//dispatch according to encoding classes
- return aarch64_insn_class_decode_table[(insn >> 25) & 0xf](insn, type,
+ return aarch64_insn_class_decode_table[(insn >> 25) & 0xf](insn, (unsigned char *)type,
immediate, op);
}
diff --git a/tools/objtool/arch/x86/arch_special.c b/tools/objtool/arch/x86/arch_special.c
index 6583a1770bb2..c097001d805b 100644
--- a/tools/objtool/arch/x86/arch_special.c
+++ b/tools/objtool/arch/x86/arch_special.c
@@ -26,3 +26,82 @@ void arch_force_alt_path(unsigned short feature,
alt->skip_alt = true;
}
}
+
+int arch_add_jump_table(struct objtool_file *file, struct instruction *insn,
+ struct rela *table, struct rela *next_table)
+{
+ struct rela *rela = table;
+ struct instruction *dest_insn;
+ struct alternative *alt;
+ struct symbol *pfunc = insn->func->pfunc;
+ unsigned int prev_offset = 0;
+
+ /*
+ * Each @rela is a switch table relocation which points to the target
+ * instruction.
+ */
+ list_for_each_entry_from(rela, &table->sec->rela_list, list) {
+
+ /* Check for the end of the table: */
+ if (rela != table && rela->jump_table_start)
+ break;
+
+ /* Make sure the table entries are consecutive: */
+ if (prev_offset && rela->offset != prev_offset + 8)
+ break;
+
+ /* Detect function pointers from contiguous objects: */
+ if (rela->sym->sec == pfunc->sec &&
+ rela->addend == pfunc->offset)
+ break;
+
+ dest_insn = find_insn(file, rela->sym->sec, rela->addend);
+ if (!dest_insn)
+ break;
+
+ /* Make sure the destination is in the same function: */
+ if (!dest_insn->func || dest_insn->func->pfunc != pfunc)
+ break;
+
+ alt = malloc(sizeof(*alt));
+ if (!alt) {
+ WARN("malloc failed");
+ return -1;
+ }
+
+ alt->insn = dest_insn;
+ list_add_tail(&alt->list, &insn->alts);
+ prev_offset = rela->offset;
+ }
+
+ if (!prev_offset) {
+ WARN_FUNC("can't find switch jump table",
+ insn->sec, insn->offset);
+ return -1;
+ }
+
+ return 0;
+}
+
+struct rela *arch_find_switch_table(struct objtool_file *file,
+ struct rela *text_rela,
+ struct section *rodata_sec,
+ unsigned long table_offset)
+{
+ struct rela *rodata_rela;
+
+ rodata_rela = find_rela_by_dest(rodata_sec, table_offset);
+ if (rodata_rela) {
+ /*
+ * Use of RIP-relative switch jumps is quite rare, and
+ * indicates a rare GCC quirk/bug which can leave dead
+ * code behind.
+ */
+ if (text_rela->type == R_X86_64_PC32)
+ file->ignore_unreachables = true;
+
+ return rodata_rela;
+ }
+
+ return NULL;
+}
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index baa6a93f37cd..18f7fb47392a 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -20,12 +20,6 @@
#define C_JUMP_TABLE_SECTION ".rodata..c_jump_table"
-struct alternative {
- struct list_head list;
- struct instruction *insn;
- bool skip_orig;
-};
-
const char *objname;
struct cfi_state initial_func_cfi;
@@ -901,62 +895,6 @@ static int add_special_section_alts(struct objtool_file *file)
return ret;
}
-static int add_jump_table(struct objtool_file *file, struct instruction *insn,
- struct rela *table)
-{
- struct rela *rela = table;
- struct instruction *dest_insn;
- struct alternative *alt;
- struct symbol *pfunc = insn->func->pfunc;
- unsigned int prev_offset = 0;
-
- /*
- * Each @rela is a switch table relocation which points to the target
- * instruction.
- */
- list_for_each_entry_from(rela, &table->sec->rela_list, list) {
-
- /* Check for the end of the table: */
- if (rela != table && rela->jump_table_start)
- break;
-
- /* Make sure the table entries are consecutive: */
- if (prev_offset && rela->offset != prev_offset + 8)
- break;
-
- /* Detect function pointers from contiguous objects: */
- if (rela->sym->sec == pfunc->sec &&
- rela->addend == pfunc->offset)
- break;
-
- dest_insn = find_insn(file, rela->sym->sec, rela->addend);
- if (!dest_insn)
- break;
-
- /* Make sure the destination is in the same function: */
- if (!dest_insn->func || dest_insn->func->pfunc != pfunc)
- break;
-
- alt = malloc(sizeof(*alt));
- if (!alt) {
- WARN("malloc failed");
- return -1;
- }
-
- alt->insn = dest_insn;
- list_add_tail(&alt->list, &insn->alts);
- prev_offset = rela->offset;
- }
-
- if (!prev_offset) {
- WARN_FUNC("can't find switch jump table",
- insn->sec, insn->offset);
- return -1;
- }
-
- return 0;
-}
-
/*
* find_jump_table() - Given a dynamic jump, find the switch jump table in
* .rodata associated with it.
@@ -1058,38 +996,9 @@ static struct rela *find_jump_table(struct objtool_file *file,
continue;
/* Each table entry has a rela associated with it. */
- table_rela = find_rela_by_dest(table_sec, table_offset);
+ table_rela = arch_find_switch_table(file, text_rela, table_sec, table_offset);
if (!table_rela)
continue;
- /*
- * If we are on arm64 architecture, we now that we
- * are in presence of a switch table thanks to
- * the `br <Xn>` insn. but we can't retrieve it yet.
- * So we just ignore unreachable for this file.
- */
- if (!arch_support_switch_table()) {
- file->ignore_unreachables = true;
- return NULL;
- }
-
- rodata_rela = find_rela_by_dest(rodata_sec, table_offset);
- if (rodata_rela) {
- /*
- * Use of RIP-relative switch jumps is quite rare, and
- * indicates a rare GCC quirk/bug which can leave dead
- * code behind.
- */
- if (text_rela->type == R_X86_64_PC32)
- file->ignore_unreachables = true;
-
- /*
- * Use of RIP-relative switch jumps is quite rare, and
- * indicates a rare GCC quirk/bug which can leave dead code
- * behind.
- */
- if (text_rela->type == R_X86_64_PC32)
- file->ignore_unreachables = true;
-
return table_rela;
}
@@ -1145,7 +1054,7 @@ static int add_func_jump_tables(struct objtool_file *file,
if (!insn->jump_table)
continue;
- ret = add_jump_table(file, insn, insn->jump_table);
+ ret = arch_add_jump_table(file, insn, insn->jump_table, NULL);
if (ret)
return ret;
}
diff --git a/tools/objtool/check.h b/tools/objtool/check.h
index af87b55db454..267759760a3d 100644
--- a/tools/objtool/check.h
+++ b/tools/objtool/check.h
@@ -13,6 +13,7 @@
#include "orc.h"
#include "arch_special.h"
#include <linux/hashtable.h>
+;
struct insn_state {
struct cfi_reg cfa;
@@ -48,6 +49,12 @@ struct instruction {
struct orc_entry orc;
};
+struct alternative {
+ struct list_head list;
+ struct instruction *insn;
+ bool skip_orig;
+};
+
struct objtool_file {
struct elf *elf;
struct list_head insn_list;
diff --git a/tools/objtool/special.h b/tools/objtool/special.h
index 90626a7e41cf..9b1f968a4325 100644
--- a/tools/objtool/special.h
+++ b/tools/objtool/special.h
@@ -7,7 +7,10 @@
#define _SPECIAL_H
#include <stdbool.h>
+#include <stdlib.h>
+#include "check.h"
#include "elf.h"
+#include "warn.h"
struct special_alt {
struct list_head list;
@@ -30,5 +33,10 @@ int special_get_alts(struct elf *elf, struct list_head *alts);
void arch_force_alt_path(unsigned short feature,
bool uaccess,
struct special_alt *alt);
-
+int arch_add_jump_table(struct objtool_file *file, struct instruction *insn,
+ struct rela *table, struct rela *next_table);
+struct rela *arch_find_switch_table(struct objtool_file *file,
+ struct rela *text_rela,
+ struct section *rodata_sec,
+ unsigned long table_offset);
#endif /* _SPECIAL_H */
--
2.17.1
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* [RFC v4 06/18] objtool: arm64: Adapt the stack frame checks for arm architecture
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
Since the way the initial stack frame when entering a function is different
that what is done in the x86_64 architecture, we need to add some more
check to support the different cases. As opposed as for x86_64, the return
address is not stored by the call instruction but is instead loaded in a
register. The initial stack frame is thus empty when entering a function
and 2 push operations are needed to set it up correctly. All the different
combinations need to be taken into account.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch.h | 2 +
tools/objtool/arch/arm64/decode.c | 28 +++++++++
tools/objtool/arch/x86/decode.c | 5 ++
tools/objtool/check.c | 100 ++++++++++++++++++++++++++++--
tools/objtool/elf.c | 3 +-
5 files changed, 131 insertions(+), 7 deletions(-)
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index bb5ce810fb6e..68d6371a24a2 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -91,4 +91,6 @@ unsigned long arch_jump_destination(struct instruction *insn);
unsigned long arch_dest_rela_offset(int addend);
+bool arch_is_insn_sibling_call(struct instruction *insn);
+
#endif /* _ARCH_H */
diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 395c5777afab..be3d2eb10227 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -106,6 +106,34 @@ unsigned long arch_dest_rela_offset(int addend)
return addend;
}
+/*
+ * In order to know if we are in presence of a sibling
+ * call and not in presence of a switch table we look
+ * back at the previous instructions and see if we are
+ * jumping inside the same function that we are already
+ * in.
+ */
+bool arch_is_insn_sibling_call(struct instruction *insn)
+{
+ struct instruction *prev;
+ struct list_head *l;
+ struct symbol *sym;
+ list_for_each_prev(l, &insn->list) {
+ prev = list_entry(l, struct instruction, list);
+ if (!prev->func ||
+ prev->func->pfunc != insn->func->pfunc)
+ return false;
+ if (prev->stack_op.src.reg != ADR_SOURCE)
+ continue;
+ sym = find_symbol_containing(insn->sec, insn->immediate);
+ if (!sym || sym->type != STT_FUNC)
+ return false;
+ else if (sym->type == STT_FUNC)
+ return true;
+ break;
+ }
+ return false;
+}
static int is_arm64(struct elf *elf)
{
switch (elf->ehdr.e_machine) {
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index fa33b3465722..98726990714d 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -72,6 +72,11 @@ unsigned long arch_dest_rela_offset(int addend)
return addend + 4;
}
+bool arch_is_insn_sibling_call(struct instruction *insn)
+{
+ return true;
+}
+
int arch_decode_instruction(struct elf *elf, struct section *sec,
unsigned long offset, unsigned int maxlen,
unsigned int *len, enum insn_type *type,
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 4af6422d3428..519569b0329f 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -566,10 +566,10 @@ static int add_jump_destinations(struct objtool_file *file)
dest_off = arch_jump_destination(insn);
} else if (rela->sym->type == STT_SECTION) {
dest_sec = rela->sym->sec;
- dest_off = rela->addend + 4;
+ dest_off = arch_dest_rela_offset(rela->addend);
} else if (rela->sym->sec->idx) {
dest_sec = rela->sym->sec;
- dest_off = rela->sym->sym.st_value + rela->addend + 4;
+ dest_off = rela->sym->sym.st_value + arch_dest_rela_offset(rela->addend);
} else if (strstr(rela->sym->name, "_indirect_thunk_")) {
/*
* Retpoline jumps are really dynamic jumps in
@@ -1368,8 +1368,8 @@ static void save_reg(struct insn_state *state, unsigned char reg, int base,
static void restore_reg(struct insn_state *state, unsigned char reg)
{
- state->regs[reg].base = CFI_UNDEFINED;
- state->regs[reg].offset = 0;
+ state->regs[reg].base = initial_func_cfi.regs[reg].base;
+ state->regs[reg].offset = initial_func_cfi.regs[reg].offset;
}
/*
@@ -1525,8 +1525,32 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
/* add imm, %rsp */
state->stack_size -= op->src.offset;
- if (cfa->base == CFI_SP)
+ if (cfa->base == CFI_SP) {
cfa->offset -= op->src.offset;
+ if (state->stack_size == 0 &&
+ initial_func_cfi.cfa.base == CFI_CFA) {
+ cfa->base = CFI_CFA;
+ cfa->offset = 0;
+ }
+ }
+ /*
+ * on arm64 the save/restore of sp into fp is not automatic
+ * and the first one can be done without the other so we
+ * need to be careful not to invalidate the stack frame in such
+ * cases.
+ */
+ else if (cfa->base == CFI_BP) {
+ if (state->stack_size == 0 &&
+ initial_func_cfi.cfa.base == CFI_CFA) {
+ cfa->base = CFI_CFA;
+ cfa->offset = 0;
+ restore_reg(state, CFI_BP);
+ }
+ } else if (cfa->base == CFI_CFA) {
+ cfa->base = CFI_SP;
+ if (state->stack_size >= 16)
+ cfa->offset = 16;
+ }
break;
}
@@ -1537,6 +1561,15 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
break;
}
+ if (op->src.reg == CFI_SP && op->dest.reg == CFI_BP &&
+ cfa->base == CFI_SP &&
+ regs[CFI_BP].base == CFI_CFA &&
+ regs[CFI_BP].offset == -cfa->offset) {
+ /* mov %rsp, %rbp */
+ cfa->base = op->dest.reg;
+ state->bp_scratch = false;
+ break;
+ }
if (op->src.reg == CFI_SP && cfa->base == CFI_SP) {
/* drap: lea disp(%rsp), %drap */
@@ -1629,6 +1662,22 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
state->stack_size -= 8;
if (cfa->base == CFI_SP)
cfa->offset -= 8;
+ if (cfa->base == CFI_SP &&
+ cfa->offset == 0 &&
+ initial_func_cfi.cfa.base == CFI_CFA)
+ cfa->base = CFI_CFA;
+
+ if (op->extra.used) {
+ if (regs[op->extra.reg].offset == -state->stack_size)
+ restore_reg(state, op->extra.reg);
+ state->stack_size -= 8;
+ if (cfa->base == CFI_SP)
+ cfa->offset -= 8;
+ if (cfa->base == CFI_SP &&
+ cfa->offset == 0 &&
+ initial_func_cfi.cfa.base == CFI_CFA)
+ cfa->base = CFI_CFA;
+ }
break;
@@ -1648,12 +1697,22 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
/* drap: mov disp(%rbp), %reg */
restore_reg(state, op->dest.reg);
+ if (op->extra.used &&
+ op->src.reg == CFI_BP &&
+ op->extra.offset == regs[op->extra.reg].offset)
+ restore_reg(state, op->extra.reg);
+
} else if (op->src.reg == cfa->base &&
op->src.offset == regs[op->dest.reg].offset + cfa->offset) {
/* mov disp(%rbp), %reg */
/* mov disp(%rsp), %reg */
restore_reg(state, op->dest.reg);
+
+ if (op->extra.used &&
+ op->src.reg == cfa->base &&
+ op->extra.offset == regs[op->extra.reg].offset + cfa->offset)
+ restore_reg(state, op->extra.reg);
}
break;
@@ -1669,6 +1728,8 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
case OP_DEST_PUSH:
case OP_DEST_PUSHF:
state->stack_size += 8;
+ if (cfa->base == CFI_CFA)
+ cfa->base = CFI_SP;
if (cfa->base == CFI_SP)
cfa->offset += 8;
@@ -1702,6 +1763,21 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
save_reg(state, op->src.reg, CFI_CFA, -state->stack_size);
}
+ if (op->extra.used) {
+ state->stack_size += 8;
+ if (cfa->base == CFI_CFA)
+ cfa->base = CFI_SP;
+ if (cfa->base == CFI_SP)
+ cfa->offset += 8;
+ if (!state->drap ||
+ (!(op->extra.reg == cfa->base &&
+ op->extra.reg == state->drap_reg) &&
+ !(op->extra.reg == CFI_BP &&
+ cfa->base == state->drap_reg) &&
+ regs[op->extra.reg].base == CFI_UNDEFINED))
+ save_reg(state, op->extra.reg, CFI_CFA,
+ -state->stack_size);
+ }
/* detect when asm code uses rbp as a scratch register */
if (!no_fp && insn->func && op->src.reg == CFI_BP &&
cfa->base != CFI_BP)
@@ -1720,11 +1796,19 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
/* save drap offset so we know when to restore it */
state->drap_offset = op->dest.offset;
}
+ if (op->extra.used && op->extra.reg == cfa->base &&
+ op->extra.reg == state->drap_reg) {
+ cfa->base = CFI_BP_INDIRECT;
+ cfa->offset = op->extra.offset;
+ }
else if (regs[op->src.reg].base == CFI_UNDEFINED) {
/* drap: mov reg, disp(%rbp) */
save_reg(state, op->src.reg, CFI_BP, op->dest.offset);
+ if (op->extra.used)
+ save_reg(state, op->extra.reg, CFI_BP,
+ op->extra.offset);
}
} else if (op->dest.reg == cfa->base) {
@@ -1733,8 +1817,12 @@ static int update_insn_state(struct instruction *insn, struct insn_state *state)
/* mov reg, disp(%rsp) */
save_reg(state, op->src.reg, CFI_CFA,
op->dest.offset - state->cfa.offset);
+ if (op->extra.used)
+ save_reg(state, op->extra.reg, CFI_CFA,
+ op->extra.offset - state->cfa.offset);
}
+
break;
case OP_DEST_LEAVE:
@@ -1857,7 +1945,7 @@ static int validate_call(struct instruction *insn, struct insn_state *state)
static int validate_sibling_call(struct instruction *insn, struct insn_state *state)
{
- if (has_modified_stack_frame(state)) {
+ if (arch_is_insn_sibling_call(insn) && has_modified_stack_frame(state)) {
WARN_FUNC("sibling call from callable instruction with modified stack frame",
insn->sec, insn->offset);
return 1;
diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c
index edba4745f25a..c6ac0b771b73 100644
--- a/tools/objtool/elf.c
+++ b/tools/objtool/elf.c
@@ -62,7 +62,8 @@ struct symbol *find_symbol_by_offset(struct section *sec, unsigned long offset)
struct symbol *sym;
list_for_each_entry(sym, &sec->symbol_list, list)
- if (sym->type != STT_SECTION &&
+ if (sym->type != STT_NOTYPE &&
+ sym->type != STT_SECTION &&
sym->offset == offset)
return sym;
--
2.17.1
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* [RFC v4 05/18] objtool: special: Adapt special section handling
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
This patch abstracts the few architecture dependent tests that are
perform when handling special section and switch tables. It enables any
architecture to ignore a particular CPU feature or not to handle switch
tables.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch/arm64/Build | 1 +
tools/objtool/arch/arm64/arch_special.c | 22 +++++++++++++++
.../objtool/arch/arm64/include/arch_special.h | 10 +++++--
tools/objtool/arch/x86/Build | 1 +
tools/objtool/arch/x86/arch_special.c | 28 +++++++++++++++++++
tools/objtool/arch/x86/include/arch_special.h | 9 ++++++
tools/objtool/check.c | 24 ++++++++++++++--
tools/objtool/special.c | 9 ++----
tools/objtool/special.h | 3 ++
9 files changed, 96 insertions(+), 11 deletions(-)
create mode 100644 tools/objtool/arch/arm64/arch_special.c
create mode 100644 tools/objtool/arch/x86/arch_special.c
diff --git a/tools/objtool/arch/arm64/Build b/tools/objtool/arch/arm64/Build
index bf7a32c2b9e9..3d09be745a84 100644
--- a/tools/objtool/arch/arm64/Build
+++ b/tools/objtool/arch/arm64/Build
@@ -1,3 +1,4 @@
+objtool-y += arch_special.o
objtool-y += decode.o
objtool-y += orc_dump.o
objtool-y += orc_gen.o
diff --git a/tools/objtool/arch/arm64/arch_special.c b/tools/objtool/arch/arm64/arch_special.c
new file mode 100644
index 000000000000..a21d28876317
--- /dev/null
+++ b/tools/objtool/arch/arm64/arch_special.c
@@ -0,0 +1,22 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "../../special.h"
+#include "arch_special.h"
+
+void arch_force_alt_path(unsigned short feature,
+ bool uaccess,
+ struct special_alt *alt)
+{
+}
diff --git a/tools/objtool/arch/arm64/include/arch_special.h b/tools/objtool/arch/arm64/include/arch_special.h
index 63da775d0581..185103be8a51 100644
--- a/tools/objtool/arch/arm64/include/arch_special.h
+++ b/tools/objtool/arch/arm64/include/arch_special.h
@@ -30,7 +30,13 @@
#define ALT_ORIG_LEN_OFFSET 10
#define ALT_NEW_LEN_OFFSET 11
-#define X86_FEATURE_POPCNT (4 * 32 + 23)
-#define X86_FEATURE_SMAP (9 * 32 + 20)
+static inline bool arch_should_ignore_feature(unsigned short feature)
+{
+ return false;
+}
+static inline bool arch_support_switch_table(void)
+{
+ return false;
+}
#endif /* _ARM64_ARCH_SPECIAL_H */
diff --git a/tools/objtool/arch/x86/Build b/tools/objtool/arch/x86/Build
index 1f11b45999d0..63e167775bc8 100644
--- a/tools/objtool/arch/x86/Build
+++ b/tools/objtool/arch/x86/Build
@@ -1,3 +1,4 @@
+objtool-y += arch_special.o
objtool-y += decode.o
objtool-y += orc_dump.o
objtool-y += orc_gen.o
diff --git a/tools/objtool/arch/x86/arch_special.c b/tools/objtool/arch/x86/arch_special.c
new file mode 100644
index 000000000000..6583a1770bb2
--- /dev/null
+++ b/tools/objtool/arch/x86/arch_special.c
@@ -0,0 +1,28 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "../../special.h"
+#include "arch_special.h"
+
+void arch_force_alt_path(unsigned short feature,
+ bool uaccess,
+ struct special_alt *alt)
+{
+ if (feature == X86_FEATURE_SMAP) {
+ if (uaccess)
+ alt->skip_orig = true;
+ else
+ alt->skip_alt = true;
+ }
+}
diff --git a/tools/objtool/arch/x86/include/arch_special.h b/tools/objtool/arch/x86/include/arch_special.h
index 424ce47013e3..fce2b1193194 100644
--- a/tools/objtool/arch/x86/include/arch_special.h
+++ b/tools/objtool/arch/x86/include/arch_special.h
@@ -33,4 +33,13 @@
#define X86_FEATURE_POPCNT (4 * 32 + 23)
#define X86_FEATURE_SMAP (9 * 32 + 20)
+static inline bool arch_should_ignore_feature(unsigned short feature)
+{
+ return feature == X86_FEATURE_POPCNT;
+}
+
+static inline bool arch_support_switch_table(void)
+{
+ return true;
+}
#endif /* _X86_ARCH_SPECIAL_H */
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 30e147391dcb..4af6422d3428 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -729,7 +729,7 @@ static int handle_group_alt(struct objtool_file *file,
last_orig_insn = insn;
}
- if (next_insn_same_sec(file, last_orig_insn)) {
+ if (last_orig_insn && next_insn_same_sec(file, last_orig_insn)) {
fake_jump = malloc(sizeof(*fake_jump));
if (!fake_jump) {
WARN("malloc failed");
@@ -1061,6 +1061,26 @@ static struct rela *find_jump_table(struct objtool_file *file,
table_rela = find_rela_by_dest(table_sec, table_offset);
if (!table_rela)
continue;
+ /*
+ * If we are on arm64 architecture, we now that we
+ * are in presence of a switch table thanks to
+ * the `br <Xn>` insn. but we can't retrieve it yet.
+ * So we just ignore unreachable for this file.
+ */
+ if (!arch_support_switch_table()) {
+ file->ignore_unreachables = true;
+ return NULL;
+ }
+
+ rodata_rela = find_rela_by_dest(rodata_sec, table_offset);
+ if (rodata_rela) {
+ /*
+ * Use of RIP-relative switch jumps is quite rare, and
+ * indicates a rare GCC quirk/bug which can leave dead
+ * code behind.
+ */
+ if (text_rela->type == R_X86_64_PC32)
+ file->ignore_unreachables = true;
/*
* Use of RIP-relative switch jumps is quite rare, and
@@ -1864,7 +1884,7 @@ static int validate_branch(struct objtool_file *file, struct symbol *func,
insn = first;
sec = insn->sec;
- if (insn->alt_group && list_empty(&insn->alts)) {
+ if (!insn->visited && insn->alt_group && list_empty(&insn->alts)) {
WARN_FUNC("don't know how to handle branch to middle of alternative instruction group",
sec, insn->offset);
return 1;
diff --git a/tools/objtool/special.c b/tools/objtool/special.c
index b8ccee1b5382..7a0092d6e5b3 100644
--- a/tools/objtool/special.c
+++ b/tools/objtool/special.c
@@ -81,7 +81,7 @@ static int get_alt_entry(struct elf *elf, struct special_entry *entry,
* feature path which is a "very very small percentage of
* machines".
*/
- if (feature == X86_FEATURE_POPCNT)
+ if (arch_should_ignore_feature(feature))
alt->skip_orig = true;
/*
@@ -93,12 +93,7 @@ static int get_alt_entry(struct elf *elf, struct special_entry *entry,
* find paths that see the STAC but take the NOP instead of
* CLAC and the other way around.
*/
- if (feature == X86_FEATURE_SMAP) {
- if (uaccess)
- alt->skip_orig = true;
- else
- alt->skip_alt = true;
- }
+ arch_force_alt_path(feature, uaccess, alt);
}
orig_rela = find_rela_by_dest(sec, offset + entry->orig);
diff --git a/tools/objtool/special.h b/tools/objtool/special.h
index 35061530e46e..90626a7e41cf 100644
--- a/tools/objtool/special.h
+++ b/tools/objtool/special.h
@@ -27,5 +27,8 @@ struct special_alt {
};
int special_get_alts(struct elf *elf, struct list_head *alts);
+void arch_force_alt_path(unsigned short feature,
+ bool uaccess,
+ struct special_alt *alt);
#endif /* _SPECIAL_H */
--
2.17.1
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* [RFC v4 03/18] objtool: Move registers and control flow to arch-dependent code
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
The control flow information and register macro definitions were based on
the x86_64 architecture but should be abstract so that each architecture
can define the correct values for the registers, especially the registers
related to the stack frame (Frame Pointer, Stack Pointer and possibly
Return Address).
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/arch/x86/include/arch_special.h | 36 +++++++++++++++++++
tools/objtool/{ => arch/x86/include}/cfi.h | 0
tools/objtool/check.h | 1 +
tools/objtool/special.c | 19 +---------
4 files changed, 38 insertions(+), 18 deletions(-)
create mode 100644 tools/objtool/arch/x86/include/arch_special.h
rename tools/objtool/{ => arch/x86/include}/cfi.h (100%)
diff --git a/tools/objtool/arch/x86/include/arch_special.h b/tools/objtool/arch/x86/include/arch_special.h
new file mode 100644
index 000000000000..424ce47013e3
--- /dev/null
+++ b/tools/objtool/arch/x86/include/arch_special.h
@@ -0,0 +1,36 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _X86_ARCH_SPECIAL_H
+#define _X86_ARCH_SPECIAL_H
+
+#define EX_ENTRY_SIZE 12
+#define EX_ORIG_OFFSET 0
+#define EX_NEW_OFFSET 4
+
+#define JUMP_ENTRY_SIZE 16
+#define JUMP_ORIG_OFFSET 0
+#define JUMP_NEW_OFFSET 4
+
+#define ALT_ENTRY_SIZE 13
+#define ALT_ORIG_OFFSET 0
+#define ALT_NEW_OFFSET 4
+#define ALT_FEATURE_OFFSET 8
+#define ALT_ORIG_LEN_OFFSET 10
+#define ALT_NEW_LEN_OFFSET 11
+
+#define X86_FEATURE_POPCNT (4 * 32 + 23)
+#define X86_FEATURE_SMAP (9 * 32 + 20)
+
+#endif /* _X86_ARCH_SPECIAL_H */
diff --git a/tools/objtool/cfi.h b/tools/objtool/arch/x86/include/cfi.h
similarity index 100%
rename from tools/objtool/cfi.h
rename to tools/objtool/arch/x86/include/cfi.h
diff --git a/tools/objtool/check.h b/tools/objtool/check.h
index 6d875ca6fce0..af87b55db454 100644
--- a/tools/objtool/check.h
+++ b/tools/objtool/check.h
@@ -11,6 +11,7 @@
#include "cfi.h"
#include "arch.h"
#include "orc.h"
+#include "arch_special.h"
#include <linux/hashtable.h>
struct insn_state {
diff --git a/tools/objtool/special.c b/tools/objtool/special.c
index fdbaa611146d..b8ccee1b5382 100644
--- a/tools/objtool/special.c
+++ b/tools/objtool/special.c
@@ -14,24 +14,7 @@
#include "builtin.h"
#include "special.h"
#include "warn.h"
-
-#define EX_ENTRY_SIZE 12
-#define EX_ORIG_OFFSET 0
-#define EX_NEW_OFFSET 4
-
-#define JUMP_ENTRY_SIZE 16
-#define JUMP_ORIG_OFFSET 0
-#define JUMP_NEW_OFFSET 4
-
-#define ALT_ENTRY_SIZE 13
-#define ALT_ORIG_OFFSET 0
-#define ALT_NEW_OFFSET 4
-#define ALT_FEATURE_OFFSET 8
-#define ALT_ORIG_LEN_OFFSET 10
-#define ALT_NEW_LEN_OFFSET 11
-
-#define X86_FEATURE_POPCNT (4*32+23)
-#define X86_FEATURE_SMAP (9*32+20)
+#include "arch_special.h"
struct special_entry {
const char *sec;
--
2.17.1
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* [RFC v4 02/18] objtool: orc: Refactor ORC API for other architectures to implement.
From: Raphael Gault @ 2019-08-16 12:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, jpoimboe
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
Raphael Gault, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-1-raphael.gault@arm.com>
The ORC unwinder is only supported on x86 at the moment and should thus be
in the x86 architecture code. In order not to break the whole structure in
case another architecture decides to support the ORC unwinder via objtool
we choose to let the implementation be done in the architecture dependent
code.
Signed-off-by: Raphael Gault <raphael.gault@arm.com>
---
tools/objtool/Build | 2 -
tools/objtool/arch.h | 3 +
tools/objtool/arch/x86/Build | 2 +
tools/objtool/{ => arch/x86}/orc_dump.c | 4 +-
tools/objtool/{ => arch/x86}/orc_gen.c | 104 ++++++++++++++++++++++--
tools/objtool/check.c | 99 +---------------------
tools/objtool/orc.h | 4 +-
7 files changed, 111 insertions(+), 107 deletions(-)
rename tools/objtool/{ => arch/x86}/orc_dump.c (98%)
rename tools/objtool/{ => arch/x86}/orc_gen.c (66%)
diff --git a/tools/objtool/Build b/tools/objtool/Build
index 8dc4f0848362..d069d26d97fa 100644
--- a/tools/objtool/Build
+++ b/tools/objtool/Build
@@ -2,8 +2,6 @@ objtool-y += arch/$(SRCARCH)/
objtool-y += builtin-check.o
objtool-y += builtin-orc.o
objtool-y += check.o
-objtool-y += orc_gen.o
-objtool-y += orc_dump.o
objtool-y += elf.o
objtool-y += special.o
objtool-y += objtool.o
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index a9a50a25ca66..e91e12807678 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -10,6 +10,7 @@
#include <linux/list.h>
#include "elf.h"
#include "cfi.h"
+#include "orc.h"
enum insn_type {
INSN_JUMP_CONDITIONAL,
@@ -77,6 +78,8 @@ int arch_decode_instruction(struct elf *elf, struct section *sec,
bool arch_callee_saved_reg(unsigned char reg);
+int arch_orc_read_unwind_hints(struct objtool_file *file);
+
unsigned long arch_jump_destination(struct instruction *insn);
unsigned long arch_dest_rela_offset(int addend);
diff --git a/tools/objtool/arch/x86/Build b/tools/objtool/arch/x86/Build
index b998412c017d..1f11b45999d0 100644
--- a/tools/objtool/arch/x86/Build
+++ b/tools/objtool/arch/x86/Build
@@ -1,4 +1,6 @@
objtool-y += decode.o
+objtool-y += orc_dump.o
+objtool-y += orc_gen.o
inat_tables_script = arch/x86/tools/gen-insn-attr-x86.awk
inat_tables_maps = arch/x86/lib/x86-opcode-map.txt
diff --git a/tools/objtool/orc_dump.c b/tools/objtool/arch/x86/orc_dump.c
similarity index 98%
rename from tools/objtool/orc_dump.c
rename to tools/objtool/arch/x86/orc_dump.c
index 13ccf775a83a..cfe8f96bdd68 100644
--- a/tools/objtool/orc_dump.c
+++ b/tools/objtool/arch/x86/orc_dump.c
@@ -4,8 +4,8 @@
*/
#include <unistd.h>
-#include "orc.h"
-#include "warn.h"
+#include "../../orc.h"
+#include "../../warn.h"
static const char *reg_name(unsigned int reg)
{
diff --git a/tools/objtool/orc_gen.c b/tools/objtool/arch/x86/orc_gen.c
similarity index 66%
rename from tools/objtool/orc_gen.c
rename to tools/objtool/arch/x86/orc_gen.c
index 27a4112848c2..b4f285bf5271 100644
--- a/tools/objtool/orc_gen.c
+++ b/tools/objtool/arch/x86/orc_gen.c
@@ -6,11 +6,11 @@
#include <stdlib.h>
#include <string.h>
-#include "orc.h"
-#include "check.h"
-#include "warn.h"
+#include "../../orc.h"
+#include "../../check.h"
+#include "../../warn.h"
-int create_orc(struct objtool_file *file)
+int arch_create_orc(struct objtool_file *file)
{
struct instruction *insn;
@@ -116,7 +116,7 @@ static int create_orc_entry(struct section *u_sec, struct section *ip_relasec,
return 0;
}
-int create_orc_sections(struct objtool_file *file)
+int arch_create_orc_sections(struct objtool_file *file)
{
struct instruction *insn, *prev_insn;
struct section *sec, *u_sec, *ip_relasec;
@@ -209,3 +209,97 @@ int create_orc_sections(struct objtool_file *file)
return 0;
}
+
+int arch_orc_read_unwind_hints(struct objtool_file *file)
+{
+ struct section *sec, *relasec;
+ struct rela *rela;
+ struct unwind_hint *hint;
+ struct instruction *insn;
+ struct cfi_reg *cfa;
+ int i;
+
+ sec = find_section_by_name(file->elf, ".discard.unwind_hints");
+ if (!sec)
+ return 0;
+
+ relasec = sec->rela;
+ if (!relasec) {
+ WARN("missing .rela.discard.unwind_hints section");
+ return -1;
+ }
+
+ if (sec->len % sizeof(struct unwind_hint)) {
+ WARN("struct unwind_hint size mismatch");
+ return -1;
+ }
+
+ file->hints = true;
+
+ for (i = 0; i < sec->len / sizeof(struct unwind_hint); i++) {
+ hint = (struct unwind_hint *)sec->data->d_buf + i;
+
+ rela = find_rela_by_dest(sec, i * sizeof(*hint));
+ if (!rela) {
+ WARN("can't find rela for unwind_hints[%d]", i);
+ return -1;
+ }
+
+ insn = find_insn(file, rela->sym->sec, rela->addend);
+ if (!insn) {
+ WARN("can't find insn for unwind_hints[%d]", i);
+ return -1;
+ }
+
+ cfa = &insn->state.cfa;
+
+ if (hint->type == UNWIND_HINT_TYPE_SAVE) {
+ insn->save = true;
+ continue;
+
+ } else if (hint->type == UNWIND_HINT_TYPE_RESTORE) {
+ insn->restore = true;
+ insn->hint = true;
+ continue;
+ }
+
+ insn->hint = true;
+
+ switch (hint->sp_reg) {
+ case ORC_REG_UNDEFINED:
+ cfa->base = CFI_UNDEFINED;
+ break;
+ case ORC_REG_SP:
+ cfa->base = CFI_SP;
+ break;
+ case ORC_REG_BP:
+ cfa->base = CFI_BP;
+ break;
+ case ORC_REG_SP_INDIRECT:
+ cfa->base = CFI_SP_INDIRECT;
+ break;
+ case ORC_REG_R10:
+ cfa->base = CFI_R10;
+ break;
+ case ORC_REG_R13:
+ cfa->base = CFI_R13;
+ break;
+ case ORC_REG_DI:
+ cfa->base = CFI_DI;
+ break;
+ case ORC_REG_DX:
+ cfa->base = CFI_DX;
+ break;
+ default:
+ WARN_FUNC("unsupported unwind_hint sp base reg %d",
+ insn->sec, insn->offset, hint->sp_reg);
+ return -1;
+ }
+
+ cfa->offset = hint->sp_offset;
+ insn->state.type = hint->type;
+ insn->state.end = hint->end;
+ }
+
+ return 0;
+}
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index 479fab46b656..30e147391dcb 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -1162,99 +1162,6 @@ static int add_jump_table_alts(struct objtool_file *file)
return 0;
}
-static int read_unwind_hints(struct objtool_file *file)
-{
- struct section *sec, *relasec;
- struct rela *rela;
- struct unwind_hint *hint;
- struct instruction *insn;
- struct cfi_reg *cfa;
- int i;
-
- sec = find_section_by_name(file->elf, ".discard.unwind_hints");
- if (!sec)
- return 0;
-
- relasec = sec->rela;
- if (!relasec) {
- WARN("missing .rela.discard.unwind_hints section");
- return -1;
- }
-
- if (sec->len % sizeof(struct unwind_hint)) {
- WARN("struct unwind_hint size mismatch");
- return -1;
- }
-
- file->hints = true;
-
- for (i = 0; i < sec->len / sizeof(struct unwind_hint); i++) {
- hint = (struct unwind_hint *)sec->data->d_buf + i;
-
- rela = find_rela_by_dest(sec, i * sizeof(*hint));
- if (!rela) {
- WARN("can't find rela for unwind_hints[%d]", i);
- return -1;
- }
-
- insn = find_insn(file, rela->sym->sec, rela->addend);
- if (!insn) {
- WARN("can't find insn for unwind_hints[%d]", i);
- return -1;
- }
-
- cfa = &insn->state.cfa;
-
- if (hint->type == UNWIND_HINT_TYPE_SAVE) {
- insn->save = true;
- continue;
-
- } else if (hint->type == UNWIND_HINT_TYPE_RESTORE) {
- insn->restore = true;
- insn->hint = true;
- continue;
- }
-
- insn->hint = true;
-
- switch (hint->sp_reg) {
- case ORC_REG_UNDEFINED:
- cfa->base = CFI_UNDEFINED;
- break;
- case ORC_REG_SP:
- cfa->base = CFI_SP;
- break;
- case ORC_REG_BP:
- cfa->base = CFI_BP;
- break;
- case ORC_REG_SP_INDIRECT:
- cfa->base = CFI_SP_INDIRECT;
- break;
- case ORC_REG_R10:
- cfa->base = CFI_R10;
- break;
- case ORC_REG_R13:
- cfa->base = CFI_R13;
- break;
- case ORC_REG_DI:
- cfa->base = CFI_DI;
- break;
- case ORC_REG_DX:
- cfa->base = CFI_DX;
- break;
- default:
- WARN_FUNC("unsupported unwind_hint sp base reg %d",
- insn->sec, insn->offset, hint->sp_reg);
- return -1;
- }
-
- cfa->offset = hint->sp_offset;
- insn->state.type = hint->type;
- insn->state.end = hint->end;
- }
-
- return 0;
-}
static int read_retpoline_hints(struct objtool_file *file)
{
@@ -1354,7 +1261,7 @@ static int decode_sections(struct objtool_file *file)
if (ret)
return ret;
- ret = read_unwind_hints(file);
+ ret = arch_orc_read_unwind_hints(file);
if (ret)
return ret;
@@ -2479,11 +2386,11 @@ int check(const char *_objname, bool orc)
}
if (orc) {
- ret = create_orc(&file);
+ ret = arch_create_orc(&file);
if (ret < 0)
goto out;
- ret = create_orc_sections(&file);
+ ret = arch_create_orc_sections(&file);
if (ret < 0)
goto out;
diff --git a/tools/objtool/orc.h b/tools/objtool/orc.h
index ee2832221e62..fd7fa1d34a81 100644
--- a/tools/objtool/orc.h
+++ b/tools/objtool/orc.h
@@ -10,8 +10,8 @@
struct objtool_file;
-int create_orc(struct objtool_file *file);
-int create_orc_sections(struct objtool_file *file);
+int arch_create_orc(struct objtool_file *file);
+int arch_create_orc_sections(struct objtool_file *file);
int orc_dump(const char *objname);
--
2.17.1
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