* Re: [PATCH 0/4] clk: imx8m: Fix incorrect parents
From: Shawn Guo @ 2019-08-19 11:55 UTC (permalink / raw)
To: Leonard Crestez
Cc: Dong Aisheng, Jacky Bai, Anson Huang, Stephen Boyd,
Michael Turquette, linux-imx, kernel, Fabio Estevam, linux-clk,
linux-arm-kernel, Abel Vesa
In-Reply-To: <cover.1565715590.git.leonard.crestez@nxp.com>
On Tue, Aug 13, 2019 at 08:05:27PM +0300, Leonard Crestez wrote:
> No checks are made to ensure the parents in the _sels arrays actually
> exist and it turns out that several are incorrect.
>
> I found the errors using a hack to clk core, is there a better way?
> Link: https://github.com/cdleonard/linux/commit/da32c2e76eb373e8a03aec905af2eef28a7997a7
>
> Also add imx8mn GIC clock while we're at it because otherwise parent
> could get disabled and lock the system.
>
> Leonard Crestez (4):
> clk: imx8mq: Fix sys3 pll references
> clk: imx8mm: Fix incorrect parents
> clk: imx8mn: Fix incorrect parents
> clk: imx8mn: Add GIC clock
Applied all, thanks.
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^ permalink raw reply
* Re: [PATCH 0/2] ARM: psci: cpuidle: defconfig updates
From: Shawn Guo @ 2019-08-19 11:53 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Ulf Hansson, Catalin Marinas, Daniel Lezcano, soc,
Sudeep Holla, Will Deacon, LAKML
In-Reply-To: <20190819102053.GA30692@e121166-lin.cambridge.arm.com>
On Mon, Aug 19, 2019 at 11:21:03AM +0100, Lorenzo Pieralisi wrote:
> On Mon, Aug 19, 2019 at 09:57:17AM +0200, Shawn Guo wrote:
> > On Wed, Aug 14, 2019 at 01:52:37PM +0100, Lorenzo Pieralisi wrote:
> > > Rerouting defconfig updates related to this patch series:
> > >
> > > https://lore.kernel.org/linux-arm-kernel/cover.1565348376.git.lorenzo.pieralisi@arm.com/
> > >
> > > to arm-soc, as agreed in:
> > >
> > > https://lore.kernel.org/linux-arm-kernel/58d9677db3510ed106fe23118090c84f78a44102.1565348376.git.lorenzo.pieralisi@arm.com/
> > >
> > > Patches [1-6] are already queued in the ARM64 tree.
> > >
> > > Please consider pulling these defconfig changes, thank you very much.
> >
> > We, platform maintainers, also send arch/arm64/configs/defconfig changes
> > to arm-soc folk. So I applied both patches to IMX tree and will send
> > them to arm-soc for 5.4 inclusion.
>
> Hi Shawn,
>
> there is no need, these updates were already pulled in arm-soc so
> there is nothing to do, please drop them.
Ah, okay. Dropped them.
Shawn
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^ permalink raw reply
* [PATCH] PCI: Fix misspelled words.
From: Krzysztof Wilczynski @ 2019-08-19 11:53 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Mark Rutland, devicetree, Richard Zhu, Thomas Petazzoni,
Fabio Estevam, Sascha Hauer, linux-kernel, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, linux-pci, Shawn Guo,
linux-arm-kernel, Lucas Stach
Fix misspelled words in include/linux/pci.h, drivers/pci/Kconfig,
and in the documentation for Freescale i.MX6 and Marvell Armada 7K/8K
PCIe interfaces. No functional change intended.
Related commit 96291d565550 ("PCI: Fix typos and whitespace errors").
Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 2 +-
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 2 +-
drivers/pci/Kconfig | 2 +-
include/linux/pci.h | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index a7f5f5afa0e6..de4b2baf91e8 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -50,7 +50,7 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
IP block
-- reset-names: Must contain the following entires:
+- reset-names: Must contain the following entries:
- "pciephy"
- "apps"
- "turnoff"
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..1aaa09254001 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -11,7 +11,7 @@ Required properties:
- reg-names:
- "ctrl" for the control register region
- "config" for the config space region
-- interrupts: Interrupt specifier for the PCIe controler
+- interrupts: Interrupt specifier for the PCIe controller
- clocks: reference to the PCIe controller clocks
- clock-names: mandatory if there is a second clock, in this case the
name must be "core" for the first clock and "reg" for the second
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 2ab92409210a..46f4912a370d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -170,7 +170,7 @@ config PCI_P2PDMA
Many PCIe root complexes do not support P2P transactions and
it's hard to tell which support it at all, so at this time,
- P2P DMA transations must be between devices behind the same root
+ P2P DMA transactions must be between devices behind the same root
port.
If unsure, say N.
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 463486016290..5a89854bd3cb 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -961,7 +961,7 @@ resource_size_t pcibios_align_resource(void *, const struct resource *,
resource_size_t,
resource_size_t);
-/* Weak but can be overriden by arch */
+/* Weak but can be overridden by arch */
void pci_fixup_cardbus(struct pci_bus *);
/* Generic PCI functions used internally */
--
2.22.0
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^ permalink raw reply related
* Re: [PATCH v3 2/2] arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
From: Shawn Guo @ 2019-08-19 11:49 UTC (permalink / raw)
To: Dafna Hirschfeld
Cc: mark.rutland, devicetree, s.hauer, linux-kernel, Troy Kisky,
Gary Bisson, robh+dt, kernel, kernel, ezequiel, linux-arm-kernel
In-Reply-To: <20190813125147.29605-1-dafna.hirschfeld@collabora.com>
On Tue, Aug 13, 2019 at 02:51:46PM +0200, Dafna Hirschfeld wrote:
> From: Gary Bisson <gary.bisson@boundarydevices.com>
>
> Add basic dts support for i.MX8MQ NITROGEN8M.
>
> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> [Dafna: porting vendor's code to mainline]
> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/imx8mq-nitrogen.dts | 400 ++++++++++++++++++
> 2 files changed, 401 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 8c0c4343e586..e2c6c93f47b6 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
> new file mode 100644
> index 000000000000..da25ea9055cd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
> @@ -0,0 +1,400 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2018 Boundary Devices
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "imx8mq.dtsi"
> +
> +/ {
> + model = "Boundary Devices i.MX8MQ Nitrogen8M";
> + compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000 0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + power {
> + label = "Power Button";
> + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + gpio-key,wakeup;
Please check Documentation/devicetree/bindings/power/wakeup-source.txt.
> + };
> + };
> +
> + reg_vref_0v9: regulator-vref-0v9 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-0v9";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + };
> +
> + reg_vref_1v8: regulator-vref-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + reg_vref_2v5: regulator-vref-2v5 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-2v5";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + };
> +
> + reg_vref_3v3: regulator-vref-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_vref_5v: regulator-vref-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +};
> +
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@4 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <4>;
> + interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + i2cmux@70 {
> + compatible = "nxp,pca9546";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_pca9546>;
> + reg = <0x70>;
> + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c1a: i2c1@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Please have a newline between property list and child node.
> + reg_arm_dram: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_arm_dram>;
> + reg = <0x60>;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1b: i2c1@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg_dram_1p1v: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
> + reg = <0x60>;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1c: i2c1@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg_soc_gpu_vpu: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
> + reg = <0x60>;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1d: i2c1@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + rtc@68 {
> + compatible = "microcrystal,rv4162";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
> + reg = <0x68>;
> + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
> + wakeup-source;
> + };
> + };
> + };
> +};
> +
> +&uart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
> + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
> + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + bus-width = <8>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + non-removable;
> + vmmc-supply = <®_vref_1v8>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
Have a newline.
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + /* J17 connector, odd */
> + MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
> + MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
> + MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
> + MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
> + MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
> + MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
> + MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
> + MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
> + MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
> + MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
> + MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
> + MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
> + MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
> + MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
> + MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
> + MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
> +
> + /* J17 connector, even */
> + MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
> + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
> + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
> +
> + /* J18 connector, odd */
> + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
> + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
> + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
> + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
> + MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
> +
> + /* J18 connector, even */
> + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
> + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
> + MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
> + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
> + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
> + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
> +
> + /* J13 Pin 2, WL_WAKE */
> + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
> + /* J13 Pin 4, WL_IRQ, not needed for Silex */
> + MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
> + /* J13 pin 9, unused */
> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
> + /* J13 Pin 41, BT_CLK_REQ */
> + MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
> + /* J13 Pin 42, BT_HOST_WAKE */
> + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
> +
> + /* Clock for both CSI1 and CSI2 */
> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
> + /* test points */
> + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpio-keysgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + >;
> + };
> +
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c1_pca9546: i2c1-pca9546grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
> + >;
> + };
> +
> + pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
> + >;
> + };
> +
> + pinctrl_reg_arm_dram: reg-arm-dram {
Please consistently name pinctrl nodes like:
pinctrl_xxx: xxxgrp {
...
};
Shawn
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
> + >;
> + };
> +
> + pinctrl_reg_dram_1p1v: reg-dram-1p1v {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
> + >;
> + };
> +
> + pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
> + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
> + MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +};
> --
> 2.20.1
>
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^ permalink raw reply
* Re: [Xen-devel] [PATCH 01/11] xen/arm: use dma-noncoherent.h calls for xen-swiotlb cache maintainance
From: Julien Grall @ 2019-08-19 11:45 UTC (permalink / raw)
To: Christoph Hellwig, Stefano Stabellini, Konrad Rzeszutek Wilk
Cc: xen-devel, iommu, x86, linux-kernel, linux-arm-kernel
In-Reply-To: <20190816130013.31154-2-hch@lst.de>
Hi Christoph,
On 8/16/19 2:00 PM, Christoph Hellwig wrote:
> +static inline void xen_dma_map_page(struct device *hwdev, struct page *page,
> + dma_addr_t dev_addr, unsigned long offset, size_t size,
> + enum dma_data_direction dir, unsigned long attrs)
> +{
> + unsigned long page_pfn = page_to_xen_pfn(page);
> + unsigned long dev_pfn = XEN_PFN_DOWN(dev_addr);
> + unsigned long compound_pages =
> + (1<<compound_order(page)) * XEN_PFN_PER_PAGE;
> + bool local = (page_pfn <= dev_pfn) &&
> + (dev_pfn - page_pfn < compound_pages);
> +
The Arm version as a comment here. Could we retain it?
> + if (local)
> + dma_direct_map_page(hwdev, page, offset, size, dir, attrs);
> + else
> + __xen_dma_map_page(hwdev, page, dev_addr, offset, size, dir, attrs);
> +}
> +
Cheers,
--
Julien Grall
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^ permalink raw reply
* [PATCH] arm64: kasan: fix phys_to_virt() false positive on tag-based kasan
From: Walter Wu @ 2019-08-19 11:44 UTC (permalink / raw)
To: Andrey Ryabinin, Alexander Potapenko, Dmitry Vyukov,
Catalin Marinas, Will Deacon, Matthias Brugger, Andrew Morton,
Andrey Konovalov
Cc: Walter Wu, wsd_upstream, linux-kernel, kasan-dev, linux-mediatek,
linux-arm-kernel
__arm_v7s_unmap() call iopte_deref() to translate pyh_to_virt address,
but it will modify pointer tag into 0xff, so there is a false positive.
When enable tag-based kasan, phys_to_virt() function need to rewrite
its original pointer tag in order to avoid kasan report an incorrect
memory corruption.
BUG: KASAN: double-free or invalid-free in __arm_v7s_unmap+0x720/0xda4
Pointer tag: [ff], memory tag: [c1]
Call trace:
dump_backtrace+0x0/0x1d4
show_stack+0x14/0x1c
dump_stack+0xe8/0x140
print_address_description+0x80/0x2f0
kasan_report_invalid_free+0x58/0x74
__kasan_slab_free+0x1e4/0x220
kasan_slab_free+0xc/0x18
kmem_cache_free+0xfc/0x884
__arm_v7s_unmap+0x720/0xda4
__arm_v7s_map+0xc8/0x774
arm_v7s_map+0x80/0x158
mtk_iommu_map+0xb4/0xe0
iommu_map+0x154/0x450
iommu_map_sg+0xe4/0x150
iommu_dma_map_sg+0x214/0x4ec
__iommu_map_sg_attrs+0xf0/0x110
ion_map_dma_buf+0xe8/0x114
dma_buf_map_attachment+0x4c/0x80
disp_sync_prepare_buf+0x378/0x820
_ioctl_prepare_buffer+0x130/0x870
mtk_disp_mgr_ioctl+0x5c4/0xab0
do_vfs_ioctl+0x8e0/0x15a4
__arm64_sys_ioctl+0x8c/0xb4
el0_svc_common+0xe4/0x1e0
el0_svc_handler+0x30/0x3c
el0_svc+0x8/0xc
Signed-off-by: Walter Wu <walter-zh.wu@mediatek.com>
---
arch/arm64/include/asm/kasan.h | 1 -
arch/arm64/include/asm/memory.h | 10 ++++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kasan.h b/arch/arm64/include/asm/kasan.h
index b52aacd2c526..59894cafad60 100644
--- a/arch/arm64/include/asm/kasan.h
+++ b/arch/arm64/include/asm/kasan.h
@@ -5,7 +5,6 @@
#ifndef __ASSEMBLY__
#include <linux/linkage.h>
-#include <asm/memory.h>
#include <asm/pgtable-types.h>
#define arch_kasan_set_tag(addr, tag) __tag_set(addr, tag)
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 8ffcf5a512bb..75af5ba9ff22 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -171,6 +171,7 @@
#include <linux/bitops.h>
#include <linux/mmdebug.h>
+#include <asm/kasan.h>
extern s64 memstart_addr;
/* PHYS_OFFSET - the physical address of the start of memory. */
@@ -282,7 +283,16 @@ static inline phys_addr_t virt_to_phys(const volatile void *x)
#define phys_to_virt phys_to_virt
static inline void *phys_to_virt(phys_addr_t x)
{
+#ifdef CONFIG_KASAN_SW_TAGS
+ unsigned long addr = __phys_to_virt(x);
+ u8 *tag = (void *)(addr >> KASAN_SHADOW_SCALE_SHIFT)
+ + KASAN_SHADOW_OFFSET;
+
+ addr = __tag_set(addr, *tag);
+ return (void *)addr;
+#else
return (void *)(__phys_to_virt(x));
+#endif
}
/*
--
2.18.0
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^ permalink raw reply related
* Re: [PATCH v2] arm64: dts: ls1088a: fix gpio node
From: Shawn Guo @ 2019-08-19 11:43 UTC (permalink / raw)
To: Hui Song
Cc: Mark Rutland, devicetree, linux-gpio, Linus Walleij, linux-kernel,
Li Yang, Bartosz Golaszewski, Rob Herring, linux-arm-kernel
In-Reply-To: <20190813020457.45370-1-hui.song_1@nxp.com>
On Tue, Aug 13, 2019 at 10:04:57AM +0800, Hui Song wrote:
> From: Song Hui <hui.song_1@nxp.com>
>
> Update the nodes to include little-endian
> property to be consistent with the hardware
> and add ls1088a gpio specify compatible.
>
> Signed-off-by: Song Hui <hui.song_1@nxp.com>
Applied, thanks.
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^ permalink raw reply
* Re: [PATCH v5 3/3] ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards
From: Shawn Guo @ 2019-08-19 11:41 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland, devicetree, Sascha Hauer, linux-kernel,
Schrempf Frieder, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190812165909.12387-3-krzk@kernel.org>
On Mon, Aug 12, 2019 at 06:59:09PM +0200, Krzysztof Kozlowski wrote:
> Add support for i.MX6UL modules from Kontron Electronics GmbH (before
> acquisition: Exceet Electronics) and evalkit boards based on it:
>
> 1. N6310 SOM: i.MX6 UL System-on-Module, a 25x25 mm solderable module
> (LGA pads and pin castellations) with 256 MB RAM, 1 MB NOR-Flash,
> 256 MB NAND and other interfaces,
> 2. N6310 S: evalkit, w/wo eMMC, without display,
> 3. N6310 S 43: evalkit with 4.3" display,
>
> The work is based on Exceet/Kontron source code (GPLv2) with numerous
> changes:
> 1. Reorganize files,
> 2. Rename Exceet -> Kontron,
> 3. Rename models/compatibles to match newest Kontron product naming,
> 4. Fix coding style errors and adjust to device tree coding guidelines,
> 5. Fix DTC warnings,
> 6. Extend compatibles so eval boards inherit the SoM compatible,
> 7. Use defines instead of GPIO and interrupt flag values,
> 8. Use proper vendor compatible for Macronix SPI NOR,
> 9. Replace deprecated bindings with proper ones,
> 10. Sort nodes alphabetically,
> 11. Remove Admatec display nodes (not yet supported).
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
>
> ---
>
> Changes since v4:
> None
>
> Changes since v3, after Shawn's review:
> 1. Split bindings update to patch 2/3,
> 2. Remove unsupported displays from (Admatec),
> 3. Remove N6310 S 50 board (same as N6310 S 43 since there is no Admatec
> display),
> 4. Order iomux nodes by name, minor cleanup,
> 5. Use wakeup-source instead of enable-sdio-wakeup,
> 6. Add review tags.
>
> Changes since v2, after Fabio's review:
> 1. Add "imx6ul" compatible to board name (that's what I understood from
> review),
> 2. Add vendor/device prefix to eeprom and document the compatible,
> 3. Use "admatecde" as vendor compatible to avoid confusion with Admatec
> AG in Switzerland (also making LCD panels),
> 4. Use generic names for nodes,
> 5. Use IRQ_TYPE_LEVEL_LOW,
> 6. Move iomux to the end of files,
> 7. Remove regulators node (include regulators in top level),
> 8. Remove cpu clock-frequency,
> 9. Other minor fixes pointed by Fabio.
>
> Changes since v1, after Frieder's review:
> 1. Remove unneeded license notes,
> 2. Add Kontron copyright (2018),
> 3. Rename the files/models/compatibles to new naming - N6310,
> 4. Remove unneeded CPU operating points override,
> 5. Switch regulator nodes into simple children nodes without addresses
> (so not simple bus),
> 6. Use proper vendor compatible for Macronix SPI NOR.
> ---
> .../devicetree/bindings/arm/fsl.yaml | 3 +
Sorry that I did not make it clear, but this needs to be a separate
patch as well.
Shawn
> arch/arm/boot/dts/Makefile | 2 +
> .../boot/dts/imx6ul-kontron-n6310-s-43.dts | 102 +++++
> arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts | 420 ++++++++++++++++++
> .../boot/dts/imx6ul-kontron-n6310-som.dtsi | 134 ++++++
> 5 files changed, 661 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 7294ac36f4c0..d07b3c06d7cf 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -161,6 +161,9 @@ properties:
> items:
> - enum:
> - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
> + - kontron,imx6ul-n6310-som # Kontron N6310 SOM
> + - kontron,imx6ul-n6310-s # Kontron N6310 S Board
> + - kontron,imx6ul-n6310-s-43 # Kontron N6310 S 43 Board
> - const: fsl,imx6ul
>
> - description: i.MX6ULL based Boards
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 9159fa2cea90..747eef501f95 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -569,6 +569,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-geam.dtb \
> imx6ul-isiot-emmc.dtb \
> imx6ul-isiot-nand.dtb \
> + imx6ul-kontron-n6310-s.dtb \
> + imx6ul-kontron-n6310-s-43.dtb \
> imx6ul-liteboard.dtb \
> imx6ul-opos6uldev.dtb \
> imx6ul-pico-hobbit.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
> new file mode 100644
> index 000000000000..5bad29683cc3
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + */
> +
> +#include "imx6ul-kontron-n6310-s.dts"
> +
> +/ {
> + model = "Kontron N6310 S 43";
> + compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s",
> + "kontron,imx6ul-n6310-som", "fsl,imx6ul";
> +
> + backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm7 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +};
> +
> +&i2c4 {
> + touchscreen@5d {
> + compatible = "goodix,gt928";
> + reg = <0x5d>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_cap_touch>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
> + reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
> + irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
> + /* Leave status disabled because of missing display panel node */
> +};
> +
> +&pwm7 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm7>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_cap_touch: captouchgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_pwm7: pwm7grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
> new file mode 100644
> index 000000000000..0205fd56d975
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
> @@ -0,0 +1,420 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul-kontron-n6310-som.dtsi"
> +
> +/ {
> + model = "Kontron N6310 S";
> + compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
> + "fsl,imx6ul";
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> + led1 {
> + label = "debug-led1";
> + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led2 {
> + label = "debug-led2";
> + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> +
> + led3 {
> + label = "debug-led3";
> + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + };
> +
> + pwm-beeper {
> + compatible = "pwm-beeper";
> + pwms = <&pwm8 0 5000>;
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_vref_adc: regulator-vref-adc {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-adc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +};
> +
> +&adc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_adc1>;
> + num-channels = <3>;
> + vref-supply = <®_vref_adc>;
> + status = "okay";
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + eeprom@0 {
> + compatible = "anvo,anv32e61w", "atmel,at25";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + spi-cpha;
> + spi-cpol;
> + pagesize = <1>;
> + size = <8192>;
> + address-width = <16>;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-0 = <&pinctrl_enet1>;
> + /delete-node/ mdio;
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy2>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + clock-names = "rmii-ref";
> + };
> +
> + ethphy2: ethernet-phy@2 {
> + reg = <2>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET2_REF>;
> + clock-names = "rmii-ref";
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + status = "okay";
> +
> + rtc@32 {
> + compatible = "epson,rx8900";
> + reg = <0x32>;
> + };
> +};
> +
> +&pwm8 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm8>;
> + status = "okay";
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + linux,rs485-enabled-at-boot-time;
> + rs485-rx-during-tx;
> + rs485-rts-active-low;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + dr_mode = "otg";
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + vbus-supply = <®_usb_otg1_vbus>;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_3v3>;
> + voltage-ranges = <3300 3300>;
> + no-1-8-v;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + non-removable;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_3v3>;
> + voltage-ranges = <3300 3300>;
> + no-1-8-v;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
> +
> + pinctrl_adc1: adc1grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
> + >;
> + };
> +
> + /* FRAM */
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
> + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
> + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
> + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
> + >;
> + };
> +
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
> + >;
> + };
> +
> + pinctrl_enet2_mdio: enet2mdiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp{
> + fsl,pins = <
> + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
> + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_gpio: gpiogrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
> + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
> + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
> + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioledsgrp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
> + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
> + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
> + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
> + >;
> + };
> +
> + pinctrl_pwm8: pwm8grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
> + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
> + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
> + /*
> + * mux unused RTS to make sure it doesn't cause
> + * any interrupts when it is undefined
> + */
> + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
> + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1 {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
> + >;
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
> new file mode 100644
> index 000000000000..a896b2348dd2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + */
> +
> +#include "imx6ul.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Kontron N6310 SOM";
> + compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul";
> +
> + memory@80000000 {
> + reg = <0x80000000 0x10000000>;
> + device_type = "memory";
> + };
> +};
> +
> +&ecspi2 {
> + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + status = "okay";
> +
> + spi-flash@0 {
> + compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy1>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + clock-names = "rmii-ref";
> + };
> + };
> +};
> +
> +&fec2 {
> + phy-mode = "rmii";
> + status = "disabled";
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-nand";
> + spi-max-frequency = <108000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + reg = <0>;
> +
> + partition@0 {
> + label = "ubi1";
> + reg = <0x00000000 0x08000000>;
> + };
> +
> + partition@8000000 {
> + label = "ubi2";
> + reg = <0x08000000 0x08000000>;
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reset_out>;
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
> + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
> + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
> + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
> + >;
> + };
> +
> + pinctrl_enet1: enet1grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
> + >;
> + };
> +
> + pinctrl_enet1_mdio: enet1mdiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
> + >;
> + };
> +
> + pinctrl_qspi: qspigrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
> + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
> + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
> + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
> + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
> + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
> + >;
> + };
> +
> + pinctrl_reset_out: rstoutgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
> + >;
> + };
> +};
> --
> 2.17.1
>
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [Xen-devel] [PATCH 04/11] xen/arm: remove xen_dma_ops
From: Julien Grall @ 2019-08-19 11:38 UTC (permalink / raw)
To: Christoph Hellwig, Stefano Stabellini, Konrad Rzeszutek Wilk
Cc: xen-devel, iommu, x86, linux-kernel, linux-arm-kernel
In-Reply-To: <20190816130013.31154-5-hch@lst.de>
Hi Christoph,
On 8/16/19 2:00 PM, Christoph Hellwig wrote:
> arm and arm64 can just use xen_swiotlb_dma_ops directly like x86, no
> need for a pointer indirection.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Cheers,
--
Julien Grall
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 4/4] arm64: implement KPROBES_ON_FTRACE
From: Jisheng Zhang @ 2019-08-19 11:38 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, Masami Hiramatsu,
David S. Miller, Anil S Keshavamurthy, Naveen N. Rao,
Steven Rostedt
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819192422.5ed79702@xhacker.debian>
This patch implements KPROBES_ON_FTRACE for arm64.
~ # mount -t debugfs debugfs /sys/kernel/debug/
~ # cd /sys/kernel/debug/
/sys/kernel/debug # echo 'p _do_fork' > tracing/kprobe_events
before the patch:
/sys/kernel/debug # cat kprobes/list
ffffff801009ff7c k _do_fork+0x4 [DISABLED]
after the patch:
/sys/kernel/debug # cat kprobes/list
ffffff801009ff7c k _do_fork+0x4 [DISABLED][FTRACE]
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/probes/Makefile | 1 +
arch/arm64/kernel/probes/ftrace.c | 16 ++++++++++++++++
3 files changed, 18 insertions(+)
create mode 100644 arch/arm64/kernel/probes/ftrace.c
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 663392d1eae2..928700f15e23 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -167,6 +167,7 @@ config ARM64
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_KPROBES
+ select HAVE_KPROBES_ON_FTRACE
select HAVE_KRETPROBES
select HAVE_GENERIC_VDSO
select IOMMU_DMA if IOMMU_SUPPORT
diff --git a/arch/arm64/kernel/probes/Makefile b/arch/arm64/kernel/probes/Makefile
index 8e4be92e25b1..4020cfc66564 100644
--- a/arch/arm64/kernel/probes/Makefile
+++ b/arch/arm64/kernel/probes/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_KPROBES) += kprobes.o decode-insn.o \
simulate-insn.o
obj-$(CONFIG_UPROBES) += uprobes.o decode-insn.o \
simulate-insn.o
+obj-$(CONFIG_KPROBES_ON_FTRACE) += ftrace.o
diff --git a/arch/arm64/kernel/probes/ftrace.c b/arch/arm64/kernel/probes/ftrace.c
new file mode 100644
index 000000000000..1fe8f105e02e
--- /dev/null
+++ b/arch/arm64/kernel/probes/ftrace.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Dynamic Ftrace based Kprobes Optimization
+ *
+ * Copyright (C) 2019 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <linux/kprobes.h>
+
+int arch_prepare_kprobe_ftrace(struct kprobe *p)
+{
+ p->ainsn.api.insn = NULL;
+ return 0;
+}
--
2.23.0.rc1
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^ permalink raw reply related
* [PATCH 3/4] kprobes: move kprobe_ftrace_handler() from x86 and make it weak
From: Jisheng Zhang @ 2019-08-19 11:37 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, Masami Hiramatsu,
David S. Miller, Anil S Keshavamurthy, Naveen N. Rao,
Steven Rostedt
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819192422.5ed79702@xhacker.debian>
This code could be reused. So move it from x86 to common code.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/x86/kernel/kprobes/ftrace.c | 44 --------------------------------
kernel/kprobes.c | 44 ++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/x86/kernel/kprobes/ftrace.c b/arch/x86/kernel/kprobes/ftrace.c
index c2ad0b9259ca..91ae1e3e65f7 100644
--- a/arch/x86/kernel/kprobes/ftrace.c
+++ b/arch/x86/kernel/kprobes/ftrace.c
@@ -12,50 +12,6 @@
#include "common.h"
-/* Ftrace callback handler for kprobes -- called under preepmt disabed */
-void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
- struct ftrace_ops *ops, struct pt_regs *regs)
-{
- struct kprobe *p;
- struct kprobe_ctlblk *kcb;
-
- /* Preempt is disabled by ftrace */
- p = get_kprobe((kprobe_opcode_t *)ip);
- if (unlikely(!p) || kprobe_disabled(p))
- return;
-
- kcb = get_kprobe_ctlblk();
- if (kprobe_running()) {
- kprobes_inc_nmissed_count(p);
- } else {
- unsigned long orig_ip = instruction_pointer(regs);
- /* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
- instruction_pointer_set(regs, ip + sizeof(kprobe_opcode_t));
-
- __this_cpu_write(current_kprobe, p);
- kcb->kprobe_status = KPROBE_HIT_ACTIVE;
- if (!p->pre_handler || !p->pre_handler(p, regs)) {
- /*
- * Emulate singlestep (and also recover regs->ip)
- * as if there is a 5byte nop
- */
- instruction_pointer_set(regs,
- (unsigned long)p->addr + MCOUNT_INSN_SIZE);
- if (unlikely(p->post_handler)) {
- kcb->kprobe_status = KPROBE_HIT_SSDONE;
- p->post_handler(p, regs, 0);
- }
- instruction_pointer_set(regs, orig_ip);
- }
- /*
- * If pre_handler returns !0, it changes regs->ip. We have to
- * skip emulating post_handler.
- */
- __this_cpu_write(current_kprobe, NULL);
- }
-}
-NOKPROBE_SYMBOL(kprobe_ftrace_handler);
-
int arch_prepare_kprobe_ftrace(struct kprobe *p)
{
p->ainsn.insn = NULL;
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index f8400753a8a9..479148ee1822 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -960,6 +960,50 @@ static struct kprobe *alloc_aggr_kprobe(struct kprobe *p)
#endif /* CONFIG_OPTPROBES */
#ifdef CONFIG_KPROBES_ON_FTRACE
+/* Ftrace callback handler for kprobes -- called under preepmt disabed */
+void __weak kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
+ struct ftrace_ops *ops, struct pt_regs *regs)
+{
+ struct kprobe *p;
+ struct kprobe_ctlblk *kcb;
+
+ /* Preempt is disabled by ftrace */
+ p = get_kprobe((kprobe_opcode_t *)ip);
+ if (unlikely(!p) || kprobe_disabled(p))
+ return;
+
+ kcb = get_kprobe_ctlblk();
+ if (kprobe_running()) {
+ kprobes_inc_nmissed_count(p);
+ } else {
+ unsigned long orig_ip = instruction_pointer(regs);
+ /* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
+ instruction_pointer_set(regs, ip + sizeof(kprobe_opcode_t));
+
+ __this_cpu_write(current_kprobe, p);
+ kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+ if (!p->pre_handler || !p->pre_handler(p, regs)) {
+ /*
+ * Emulate singlestep (and also recover regs->ip)
+ * as if there is a 5byte nop
+ */
+ instruction_pointer_set(regs,
+ (unsigned long)p->addr + MCOUNT_INSN_SIZE);
+ if (unlikely(p->post_handler)) {
+ kcb->kprobe_status = KPROBE_HIT_SSDONE;
+ p->post_handler(p, regs, 0);
+ }
+ instruction_pointer_set(regs, orig_ip);
+ }
+ /*
+ * If pre_handler returns !0, it changes regs->ip. We have to
+ * skip emulating post_handler.
+ */
+ __this_cpu_write(current_kprobe, NULL);
+ }
+}
+NOKPROBE_SYMBOL(kprobe_ftrace_handler);
+
static struct ftrace_ops kprobe_ftrace_ops __read_mostly = {
.func = kprobe_ftrace_handler,
.flags = FTRACE_OPS_FL_SAVE_REGS | FTRACE_OPS_FL_IPMODIFY,
--
2.23.0.rc1
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^ permalink raw reply related
* [PATCH 2/4] kprobes/x86: use instruction_pointer and instruction_pointer_set
From: Jisheng Zhang @ 2019-08-19 11:36 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, Masami Hiramatsu,
David S. Miller, Anil S Keshavamurthy, Naveen N. Rao,
Steven Rostedt
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819192422.5ed79702@xhacker.debian>
This is to make the kprobe_ftrace_handler() common, so we can move it
to common code in next patch.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/x86/kernel/kprobes/ftrace.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/kprobes/ftrace.c b/arch/x86/kernel/kprobes/ftrace.c
index 681a4b36e9bb..c2ad0b9259ca 100644
--- a/arch/x86/kernel/kprobes/ftrace.c
+++ b/arch/x86/kernel/kprobes/ftrace.c
@@ -28,9 +28,9 @@ void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
if (kprobe_running()) {
kprobes_inc_nmissed_count(p);
} else {
- unsigned long orig_ip = regs->ip;
+ unsigned long orig_ip = instruction_pointer(regs);
/* Kprobe handler expects regs->ip = ip + 1 as breakpoint hit */
- regs->ip = ip + sizeof(kprobe_opcode_t);
+ instruction_pointer_set(regs, ip + sizeof(kprobe_opcode_t));
__this_cpu_write(current_kprobe, p);
kcb->kprobe_status = KPROBE_HIT_ACTIVE;
@@ -39,12 +39,13 @@ void kprobe_ftrace_handler(unsigned long ip, unsigned long parent_ip,
* Emulate singlestep (and also recover regs->ip)
* as if there is a 5byte nop
*/
- regs->ip = (unsigned long)p->addr + MCOUNT_INSN_SIZE;
+ instruction_pointer_set(regs,
+ (unsigned long)p->addr + MCOUNT_INSN_SIZE);
if (unlikely(p->post_handler)) {
kcb->kprobe_status = KPROBE_HIT_SSDONE;
p->post_handler(p, regs, 0);
}
- regs->ip = orig_ip;
+ instruction_pointer_set(regs, orig_ip);
}
/*
* If pre_handler returns !0, it changes regs->ip. We have to
--
2.23.0.rc1
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^ permalink raw reply related
* [PATCH 1/4] kprobes: adjust kprobe addr for KPROBES_ON_FTRACE
From: Jisheng Zhang @ 2019-08-19 11:36 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, Masami Hiramatsu,
David S. Miller, Anil S Keshavamurthy, Naveen N. Rao,
Steven Rostedt
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819192422.5ed79702@xhacker.debian>
For KPROBES_ON_FTRACE case, we need to adjust the kprobe's addr
correspondingly.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
kernel/kprobes.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index 9873fc627d61..f8400753a8a9 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -1560,6 +1560,9 @@ int register_kprobe(struct kprobe *p)
addr = kprobe_addr(p);
if (IS_ERR(addr))
return PTR_ERR(addr);
+#ifdef CONFIG_KPROBES_ON_FTRACE
+ addr = (kprobe_opcode_t *)ftrace_call_adjust((unsigned long)addr);
+#endif
p->addr = addr;
ret = check_kprobe_rereg(p);
--
2.23.0.rc1
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^ permalink raw reply related
* [PATCH 0/4] arm64: KPROBES_ON_FTRACE
From: Jisheng Zhang @ 2019-08-19 11:35 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, Masami Hiramatsu,
David S. Miller, Anil S Keshavamurthy, Naveen N. Rao,
Steven Rostedt
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Implement KPROBES_ON_FTRACE for arm64.
Applied after FTRACE_WITH_REGS:
http://lists.infradead.org/pipermail/linux-arm-kernel/2019-August/674404.html
Jisheng Zhang (4):
kprobes: adjust kprobe addr for KPROBES_ON_FTRACE
kprobes/x86: use instruction_pointer and instruction_pointer_set
kprobes: move kprobe_ftrace_handler() from x86 and make it weak
arm64: implement KPROBES_ON_FTRACE
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/probes/Makefile | 1 +
arch/arm64/kernel/probes/ftrace.c | 16 +++++++++++
arch/x86/kernel/kprobes/ftrace.c | 43 ----------------------------
kernel/kprobes.c | 47 +++++++++++++++++++++++++++++++
5 files changed, 65 insertions(+), 43 deletions(-)
create mode 100644 arch/arm64/kernel/probes/ftrace.c
--
2.23.0.rc1
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^ permalink raw reply
* Re: [Xen-devel] [PATCH 02/11] xen/arm: use dev_is_dma_coherent
From: Julien Grall @ 2019-08-19 11:31 UTC (permalink / raw)
To: Christoph Hellwig, Stefano Stabellini, Konrad Rzeszutek Wilk
Cc: xen-devel, iommu, x86, linux-kernel, linux-arm-kernel
In-Reply-To: <20190816130013.31154-3-hch@lst.de>
Hi Christoph,
On 8/16/19 2:00 PM, Christoph Hellwig wrote:
> Use the dma-noncoherent dev_is_dma_coherent helper instead of the home
> grown variant.
It took me a bit of time to understand that dev->archdata.dma_coherent
and dev->dma_coherent will always contain the same value.
Would you mind it mention it in the commit message?
Other than that:
Reviewed-by: Julien Grall <julien.grall@arm.com>
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
Cheers,
--
Julien Grall
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^ permalink raw reply
* Re: [PATCH v4 12/21] ARM: dts: imx6-apalis: Add touchscreens used on Toradex eval boards
From: Shawn Guo @ 2019-08-19 11:30 UTC (permalink / raw)
To: Philippe Schenker
Cc: Mark Rutland, devicetree@vger.kernel.org, Michal Vokáč,
Pengutronix Kernel Team, Marcel Ziswiler, Sascha Hauer,
linux-kernel@vger.kernel.org, stefan@agner.ch, Rob Herring,
NXP Linux Team, Max Krummenacher, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190812142105.1995-13-philippe.schenker@toradex.com>
On Mon, Aug 12, 2019 at 02:21:33PM +0000, Philippe Schenker wrote:
> This commit adds the touchscreens from Toradex so one can enable it.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v4:
> - Add Marcel Ziswiler's Ack
>
> Changes in v3:
> - Fix commit title to "...imx6-apalis:..."
>
> Changes in v2:
> - Deleted touchrevolution downstream stuff
> - Use generic node name
> - Put a better comment in there
>
> arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 31 +++++++++++++++++++
> arch/arm/boot/dts/imx6q-apalis-eval.dts | 13 ++++++++
> arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 13 ++++++++
> arch/arm/boot/dts/imx6q-apalis-ixora.dts | 13 ++++++++
> 4 files changed, 70 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> index 9a5d6c94cca4..763fb5e90bd3 100644
> --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
> @@ -168,6 +168,21 @@
> &i2c3 {
> status = "okay";
>
> + /*
> + * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
> + * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
> + */
> + touchscreen@4a {
> + compatible = "atmel,maxtouch";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcap_1>;
> + reg = <0x4a>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
> + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
> + status = "disabled";
If you have a reason to keep this disabled, please comment or state in
the commit log.
> + };
> +
> /* M41T0M6 real time clock on carrier board */
> rtc_i2c: rtc@68 {
> compatible = "st,m41t0";
> @@ -175,6 +190,22 @@
> };
> };
>
> +&iomuxc {
> + pinctrl_pcap_1: pcap-1 {
Name pinctrl node more consistently like pinctrl_xxx: xxxgrp.
Shawn
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
> + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
> + >;
> + };
> +
> + pinctrl_mxt_ts: mxt-ts {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
> + >;
> + };
> +};
> +
> &ipu1_di0_disp0 {
> remote-endpoint = <&lcd_display_in>;
> };
> diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
> index 0edd3043d9c1..4665e15b196d 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
> @@ -167,6 +167,19 @@
> &i2c1 {
> status = "okay";
>
> + /*
> + * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
> + * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
> + */
> + touchscreen@4a {
> + compatible = "atmel,maxtouch";
> + reg = <0x4a>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
> + status = "disabled";
> + };
> +
> pcie-switch@58 {
> compatible = "plx,pex8605";
> reg = <0x58>;
> diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
> index b94bb687be6b..a3fa04a97d81 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
> @@ -172,6 +172,19 @@
> &i2c1 {
> status = "okay";
>
> + /*
> + * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
> + * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
> + */
> + touchscreen@4a {
> + compatible = "atmel,maxtouch";
> + reg = <0x4a>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
> + status = "disabled";
> + };
> +
> /* M41T0M6 real time clock on carrier board */
> rtc_i2c: rtc@68 {
> compatible = "st,m41t0";
> diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> index 302fd6adc8a7..5ba49d0f4880 100644
> --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
> @@ -171,6 +171,19 @@
> &i2c1 {
> status = "okay";
>
> + /*
> + * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
> + * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
> + */
> + touchscreen@4a {
> + compatible = "atmel,maxtouch";
> + reg = <0x4a>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
> + status = "disabled";
> + };
> +
> eeprom@50 {
> compatible = "atmel,24c02";
> reg = <0x50>;
> --
> 2.22.0
>
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^ permalink raw reply
* Re: [PATCH 1/3] ftrace: introdue ftrace_call_init
From: Jisheng Zhang @ 2019-08-19 11:30 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Steven Rostedt, Mark Rutland
Cc: Torsten Duwe, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819191622.57050fdf@xhacker.debian>
On Mon, 19 Aug 2019 19:16:22 +0800 Jisheng Zhang wrote:
> On some arch, the FTRACE_WITH_REGS is implemented with gcc's
> -fpatchable-function-entry (=2), gcc adds 2 NOPs at the beginning
> of each function, so this makes the MCOUNT_ADDR useless. In ftrace
> common framework, MCOUNT_ADDR is mostly used to "init" the nop, so
> let's introcude ftrace_call_init().
>
> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> ---
> include/linux/ftrace.h | 1 +
> kernel/trace/ftrace.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
> index 8a8cb3c401b2..8175ffb671f0 100644
> --- a/include/linux/ftrace.h
> +++ b/include/linux/ftrace.h
> @@ -458,6 +458,7 @@ extern void ftrace_regs_caller(void);
> extern void ftrace_call(void);
> extern void ftrace_regs_call(void);
> extern void mcount_call(void);
> +extern int ftrace_call_init(struct module *mod, struct dyn_ftrace *rec);
>
> void ftrace_modify_all_code(int command);
>
> diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
> index eca34503f178..9df5a66a6811 100644
> --- a/kernel/trace/ftrace.c
> +++ b/kernel/trace/ftrace.c
> @@ -2500,7 +2500,11 @@ ftrace_code_disable(struct module *mod, struct dyn_ftrace *rec)
> if (unlikely(ftrace_disabled))
> return 0;
>
> +#ifdef MCOUNT_ADDR
> ret = ftrace_make_nop(mod, rec, MCOUNT_ADDR);
> +#else
> + ret = ftrace_call_init(mod, rec);
> +#endif
If we want to remove MCOUNT_ADDR from all arch, I could cook patches for
this.
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* [PATCH 3/3] arm64: use -fpatchable-function-entry if available
From: Jisheng Zhang @ 2019-08-19 11:29 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Steven Rostedt, Mark Rutland
Cc: Torsten Duwe, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819191530.0f47b9b1@xhacker.debian>
From: Torsten Duwe <duwe@suse.de>
Test whether gcc supports -fpatchable-function-entry and use it to promote
DYNAMIC_FTRACE to DYNAMIC_FTRACE_WITH_REGS. Amend support for the new
object section that holds the locations (__patchable_function_entries) and
define a proper "notrace" attribute to switch it off.
Signed-off-by: Torsten Duwe <duwe@suse.de>
---
arch/arm64/Kconfig | 2 ++
arch/arm64/Makefile | 5 +++++
kernel/module.c | 7 ++++++-
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3adcec05b1f6..663392d1eae2 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -144,6 +144,8 @@ config ARM64
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS
select HAVE_DYNAMIC_FTRACE
+ select HAVE_DYNAMIC_FTRACE_WITH_REGS \
+ if $(cc-option,-fpatchable-function-entry=2)
select HAVE_EFFICIENT_UNALIGNED_ACCESS
select HAVE_FAST_GUP
select HAVE_FTRACE_MCOUNT_RECORD
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 61de992bbea3..e827ad0298ab 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -104,6 +104,11 @@ ifeq ($(CONFIG_ARM64_MODULE_PLTS),y)
KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/arm64/kernel/module.lds
endif
+ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_REGS),y)
+ KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
+ CC_FLAGS_FTRACE := -fpatchable-function-entry=2
+endif
+
# Default value
head-y := arch/arm64/kernel/head.o
diff --git a/kernel/module.c b/kernel/module.c
index 5933395af9a0..0759f89adbd3 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -3136,7 +3136,12 @@ static int find_module_sections(struct module *mod, struct load_info *info)
#endif
#ifdef CONFIG_FTRACE_MCOUNT_RECORD
/* sechdrs[0].sh_size is always zero */
- mod->ftrace_callsites = section_objs(info, "__mcount_loc",
+ mod->ftrace_callsites = section_objs(info,
+#ifdef CC_USING_PATCHABLE_FUNCTION_ENTRY
+ "__patchable_function_entries",
+#else
+ "__mcount_loc",
+#endif
sizeof(*mod->ftrace_callsites),
&mod->num_ftrace_callsites);
#endif
--
2.23.0.rc1
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^ permalink raw reply related
* Re: [PATCH v2] iommu/arm-smmu: Break insecure users by disabling bypass by default
From: Thierry Reding @ 2019-08-19 11:28 UTC (permalink / raw)
To: Robin Murphy
Cc: Marc Gonzalez, Joerg Roedel, Will Deacon, Douglas Anderson,
Jon Hunter, linux-tegra, Linux ARM
In-Reply-To: <94cf6d56-5dcb-051a-06da-5edfacde1655@arm.com>
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On Thu, May 02, 2019 at 03:27:55PM +0100, Robin Murphy wrote:
> On 02/05/2019 13:45, Thierry Reding wrote:
> > On Thu, May 02, 2019 at 12:08:21PM +0100, Will Deacon wrote:
> > > On Thu, May 02, 2019 at 12:59:12PM +0200, Thierry Reding wrote:
> > > > On Wed, Apr 24, 2019 at 12:52:31PM +0100, Will Deacon wrote:
> > > > > On Wed, Apr 24, 2019 at 01:36:58PM +0200, Marc Gonzalez wrote:
> > > > > > On 04/04/2019 17:00, Will Deacon wrote:
> > > > > >
> > > > > > > On Fri, Mar 01, 2019 at 11:20:17AM -0800, Douglas Anderson wrote:
> > > > > > >
> > > > > > > > If you're bisecting why your peripherals stopped working, it's
> > > > > > > > probably this CL. Specifically if you see this in your dmesg:
> > > > > > > > Unexpected global fault, this could be serious
> > > > > > > > ...then it's almost certainly this CL.
> > > > > > > >
> > > > > > > > Running your IOMMU-enabled peripherals with the IOMMU in bypass mode
> > > > > > > > is insecure and effectively disables the protection they provide.
> > > > > > > > There are few reasons to allow unmatched stream bypass, and even fewer
> > > > > > > > good ones.
> > > > > > > >
> > > > > > > > This patch starts the transition over to make it much harder to run
> > > > > > > > your system insecurely. Expected steps:
> > > > > > > >
> > > > > > > > 1. By default disable bypass (so anyone insecure will notice) but make
> > > > > > > > it easy for someone to re-enable bypass with just a KConfig change.
> > > > > > > > That's this patch.
> > > > > > > >
> > > > > > > > 2. After people have had a little time to come to grips with the fact
> > > > > > > > that they need to set their IOMMUs properly and have had time to
> > > > > > > > dig into how to do this, the KConfig will be eliminated and bypass
> > > > > > > > will simply be disabled. Folks who are truly upset and still
> > > > > > > > haven't fixed their system can either figure out how to add
> > > > > > > > 'arm-smmu.disable_bypass=n' to their command line or revert the
> > > > > > > > patch in their own private kernel. Of course these folks will be
> > > > > > > > less secure.
> > > > > > > >
> > > > > > > > Suggested-by: Robin Murphy <robin.murphy@arm.com>
> > > > > > > > Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > > > > > > > ---
> > > > > > > >
> > > > > > > > Changes in v2:
> > > > > > > > - Flipped default to 'yes' and changed comments a lot.
> > > > > > > >
> > > > > > > > drivers/iommu/Kconfig | 25 +++++++++++++++++++++++++
> > > > > > > > drivers/iommu/arm-smmu.c | 3 ++-
> > > > > > > > 2 files changed, 27 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > Cheers, I'll pick this one up for 5.2.
> > > > > >
> > > > > > Hello Will,
> > > > > >
> > > > > > You haven't pushed this patch out to linux-next AFAICT.
> > > > > >
> > > > > > Is that expected?
> > > > >
> > > > > It's on my branch for Joerg:
> > > > >
> > > > > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates
> > > > >
> > > > > which I'll send to him today. My SMMU stuff doesn't go directly into -next.
> > > >
> > > > This made it to linux-next yesterday (less than a week before the merge
> > > > window opens) and deliberately breaks existing configurations. That's a
> > > > little rude.
> > > >
> > > > At least give people a fair heads-up and a chance to fix things before
> > > > you start break things.
> > >
> > > Sorry about the inconvenience here.
> > >
> > > This patch has been floating around for a while (albeit not in -next, since
> > > I send my stuff via Joerg)
> >
> > You can't expect people to test random patches from the list if they're
> > not on Cc. I don't think it's safe to claim that patches have been well
> > tested until they've been in linux-next for at least a couple of days.
> >
> > > and is heading for 5.3, so you have ages to fix
> > > up your config!
> >
> > Last I checked, Joerg applied this for 5.2 because you sent it as part
> > of your "Updates for 5.2" pull request.
> >
> > > It would, of course, be better to configure the IOMMU to
> > > provide mappings for your DMA peripherals, but the trivial config change
> > > will be enough to keep things working. We won't remove that as long as
> > > people are relying on it.
> >
> > I don't think the Kconfig option is really useful. People nowadays want
> > to run standard distribution kernels on their devices, and distribution
> > maintainers will often rely on kernel developers' guidance on what good
> > defaults are. This patch suggests that the default should be to disable
> > bypass, so if this hits 5.2 final and distributions create their kernel
> > packages, they're likely going to go with this default and potentially
> > break things for many of their users.
> >
> > Luckily this seems like it's fairly easy to fix, but given that we're
> > past v5.1-rc6, fixes for this now need to get special treatment. That
> > would've been okay if this was a pressing issues, but this is changing
> > something that's worked this way for ages, so it's hardly urgent.
> >
> > > I don't expect most people to run into problems with this change (the new
> > > behaviour matches what SMMUv3 does already).
> >
> > I see the ARM SMMU v2 used in quite a few DTS files. Not all of these
> > may be problematic, but I'd be somewhat surprised if Tegra was the only
> > one impacted.
>
> If people have real technical reasons for needing unmatched stream bypass,
> then we'll probably need to consider some sort of per-SMMU override anyway,
> since well-meaning users rendering the system unusable by enabling a
> security option isn't ideal. I'm in the middle of a big rework to
> accommodate platform-specific extensions more easily, so that's certainly an
> angle I can try to plan for.
>
> On the other hand, if it's merely that nobody's yet got round to filling out
> the DT properly, then AIUI that's pretty much exactly what Doug wanted to
> motivate, so that the option *can* be used more widely by users who might
> want it. Hence the provocative title :)
I was just rebasing a set of patches that I've been working on for some
time that will eventually allow seamlessly transitioning display from a
firmware-controlled framebuffer to a DRM/KMS framebuffer.
The idea is to mark firmware-allocated buffers as reserved via the
standard reserved-memory DT bindings and hook them up in device tree to
the display controller nodes via memory-region properties. I've got this
working from a firmware/bootloader point of view, but I'm running into a
couple of issues during early boot.
I should mention that as part of this work I've also been meaning to
transition the Tegra SMMU driver that we use on Tegra210 and earlier to
register DMA IOMMU domains and then transition over the display driver
to use that instead of explicit IOMMU usage. One of the issues that I
ran into early on was that the Tegra SMMU would start faulting as soon
as the display controllers had been attached to the DMA IOMMU domain.
This is because the display hardware is still scanning out the frame-
buffer that firmware had set up when the DMA API hooks up to the IOMMU
domain. Currently we don't run into that because we explicitly only
attach to the IOMMU after the display hardware has been reinitialized.
This particular problem was fairly easy to fix by implementing the
IOMMU's ->get_resv_regions() and ->put_resv_regions() callbacks that
parse the memory-region properties for a device and create 1:1 mappings
for each region before "enabling" the domain.
I have patches to implement the same mechanism on Tegra186 where an ARM
SMMU is used. Unfortunately, with this patch to disable bypass by
default, this approach no longer works. The problem is that the ARM SMMU
starts faulting immediately after it's bound to the driver because all
stream IDs will now fault by default (and like I mentioned, the display
controller is still busy scanning out the framebuffer set up by the
firmware). The faults cause a massive amount of interrupt, slowing down
the boot process significantly, and cause the display hardware to read
the framebuffer as all-ones, so the display goes to complete white early
during boot.
Now, I realize that this is precisely what this patch intended. It's
quite nasty for the display hardware to just keep scanning stuff out
from where it may not be allowed to. On the other hand, if we're careful
about marking the firmware framebuffer region reserved, Linux won't be
touching it and it'd be fine for the hardware to keep reading from it.
We do need to make sure to establish that 1:1 mapping, though, to fix
these faults.
So, since you mentioned "real technical reasons", I'm wondering if you
have any ideas how to fix this. I understand that, strictly speaking, we
do violate the Linux boot requirements here (display hardware is not
quiesced), but surely seamless transition from a firmware boot splash to
the kernel display driver is a feature that we want to support.
I suppose an easy way would be to let the firmware add a command-line
argument to enable bypass, but that seems a little coarse and it would
enable bypass in general, again opening up the security issues that you
wanted to close with this.
Perhaps an alternative would be to add a property to the SMMU node that
lists a set of stream IDs for which to enable bypass by default. We
could let the firmware set that when the display hardware has been set
up. That way when the kernel boots we can keep scanning from the
reserved memory and the ARM SMMU driver would not disable bypass for the
display hardware. Only when the display hardware is actually attached to
the IOMMU domain, and the 1:1 mappings have been created would bypass be
disabled, and at that point there should be no SMMU faults anymore, so
we have cleanly transitioned to the kernel.
Any thoughts?
Thierry
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^ permalink raw reply
* Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API
From: Dariusz Marcinkiewicz @ 2019-08-19 11:28 UTC (permalink / raw)
To: Hans Verkuil
Cc: Kate Stewart, Neil Armstrong, Daniel Vetter, dri-devel, open list,
Hans Verkuil, Dhinakaran Pandiyan, Sam Ravnborg,
linux-samsung-soc, David Francis, amd-gfx, Leo Li,
Jerry (Fangzhi) Zuo, Allison Randal, nouveau, linux-media,
Jonas Karlman, Jani Nikula, intel-gfx, Russell King, Sean Paul,
Rodrigo Vivi, linux-tegra, Thomas Gleixner, linux-arm-kernel,
Thomas Lim, Jernej Skrabec, Greg Kroah-Hartman, Douglas Anderson,
Manasi Navare, Alex Deucher, Colin Ian King, Enrico Weigelt,
Laurent Pinchart
In-Reply-To: <42c7ef3c-b7e5-8c63-c7c2-bfc6c56100c6@xs4all.nl>
On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil <hverkuil-cisco@xs4all.nl> wrote:
>
> Hi all,
>
Hi Hans.
> The patches in this series can be applied independently from each other.
>
> If you maintain one of these drivers and you want to merge it for v5.4
> yourself, then please do so and let me know. If you prefer I commit it
> to drm-misc, then please review and (hopefully) Ack the patch.
>
> I would really like to get this in for v5.4 so I can get the userspace
> bits in for v5.4 as well through the media subsystem.
>
> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
>
Done.
I think it would be good to test v7 changes to dw-hdmi and tda998x on
a real hardware. Hans, do you think you would be able to test those?
Thank you.
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^ permalink raw reply
* [PATCH 2/3] arm64: implement ftrace with regs
From: Jisheng Zhang @ 2019-08-19 11:28 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Steven Rostedt, Mark Rutland
Cc: Torsten Duwe, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819191530.0f47b9b1@xhacker.debian>
From: Torsten Duwe <duwe@suse.de>
Implement ftrace with regs, based on the new gcc flag
-fpatchable-function-entry (=2)
Now that gcc8 added 2 NOPs at the beginning of each function, replace
the first NOP thus generated with a quick LR saver (move it to scratch
reg x9), so the 2nd replacement insn, the call to ftrace, does not
clobber the value. Ftrace will then generate the standard stack
frames.
Note that patchable-function-entry in GCC disables IPA-RA, which means
ABI register calling conventions are obeyed and scratch registers such
as x9 are available.
Introduce and handle an ftrace_regs_trampoline for module PLTs, right
after ftrace_trampoline in an ftrace_trampolines[2] array, and double
the size of the corresponding special section.
Signed-off-by: Torsten Duwe <duwe@suse.de>
---
arch/arm64/include/asm/ftrace.h | 12 ++-
arch/arm64/include/asm/module.h | 3 +-
arch/arm64/kernel/entry-ftrace.S | 125 ++++++++++++++++++++++++++--
arch/arm64/kernel/ftrace.c | 138 +++++++++++++++++++++++--------
arch/arm64/kernel/module-plts.c | 3 +-
arch/arm64/kernel/module.c | 2 +-
6 files changed, 239 insertions(+), 44 deletions(-)
diff --git a/arch/arm64/include/asm/ftrace.h b/arch/arm64/include/asm/ftrace.h
index 5ab5200b2bdc..fde94a905b25 100644
--- a/arch/arm64/include/asm/ftrace.h
+++ b/arch/arm64/include/asm/ftrace.h
@@ -11,9 +11,12 @@
#include <asm/insn.h>
#define HAVE_FUNCTION_GRAPH_FP_TEST
-#define MCOUNT_ADDR ((unsigned long)_mcount)
#define MCOUNT_INSN_SIZE AARCH64_INSN_SIZE
+#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
+#define ARCH_SUPPORTS_FTRACE_OPS 1
+#endif
+
#ifndef __ASSEMBLY__
#include <linux/compat.h>
@@ -30,6 +33,13 @@ extern void return_to_handler(void);
static inline unsigned long ftrace_call_adjust(unsigned long addr)
{
+ /*
+ * For -fpatchable-function-entry=2, there's first the
+ * LR saver, and only then the actual call insn.
+ * Advance addr accordingly.
+ */
+ if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS))
+ return (addr + AARCH64_INSN_SIZE);
/*
* addr is the address of the mcount call instruction.
* recordmcount does the necessary offset calculation.
diff --git a/arch/arm64/include/asm/module.h b/arch/arm64/include/asm/module.h
index f80e13cbf8ec..5463a2cf0165 100644
--- a/arch/arm64/include/asm/module.h
+++ b/arch/arm64/include/asm/module.h
@@ -21,7 +21,8 @@ struct mod_arch_specific {
struct mod_plt_sec init;
/* for CONFIG_DYNAMIC_FTRACE */
- struct plt_entry *ftrace_trampoline;
+ struct plt_entry *ftrace_trampolines;
+#define MOD_ARCH_NR_FTRACE_TRAMPOLINES 2
};
#endif
diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S
index 33d003d80121..4cfc0a886e4e 100644
--- a/arch/arm64/kernel/entry-ftrace.S
+++ b/arch/arm64/kernel/entry-ftrace.S
@@ -7,6 +7,7 @@
*/
#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include <asm/ftrace.h>
#include <asm/insn.h>
@@ -121,6 +122,7 @@ EXPORT_SYMBOL(_mcount)
NOKPROBE(_mcount)
#else /* CONFIG_DYNAMIC_FTRACE */
+#ifndef CONFIG_DYNAMIC_FTRACE_WITH_REGS
/*
* _mcount() is used to build the kernel with -pg option, but all the branch
* instructions to _mcount() are replaced to NOP initially at kernel start up,
@@ -160,11 +162,6 @@ GLOBAL(ftrace_graph_call) // ftrace_graph_caller();
mcount_exit
ENDPROC(ftrace_caller)
-#endif /* CONFIG_DYNAMIC_FTRACE */
-
-ENTRY(ftrace_stub)
- ret
-ENDPROC(ftrace_stub)
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
/*
@@ -184,7 +181,125 @@ ENTRY(ftrace_graph_caller)
mcount_exit
ENDPROC(ftrace_graph_caller)
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+#else /* CONFIG_DYNAMIC_FTRACE_WITH_REGS */
+
+ .macro ftrace_regs_entry, allregs=0
+ /* make room for pt_regs, plus a callee frame */
+ sub sp, sp, #(S_FRAME_SIZE + 16)
+
+ /* save function arguments */
+ stp x0, x1, [sp, #S_X0]
+ stp x2, x3, [sp, #S_X2]
+ stp x4, x5, [sp, #S_X4]
+ stp x6, x7, [sp, #S_X6]
+ stp x8, x9, [sp, #S_X8]
+
+ .if \allregs == 1
+ stp x10, x11, [sp, #S_X10]
+ stp x12, x13, [sp, #S_X12]
+ stp x14, x15, [sp, #S_X14]
+ stp x16, x17, [sp, #S_X16]
+ stp x18, x19, [sp, #S_X18]
+ stp x20, x21, [sp, #S_X20]
+ stp x22, x23, [sp, #S_X22]
+ stp x24, x25, [sp, #S_X24]
+ stp x26, x27, [sp, #S_X26]
+ .endif
+
+ /* Save fp and x28, which is used in this function. */
+ stp x28, x29, [sp, #S_X28]
+
+ /* The stack pointer as it was on ftrace_caller entry... */
+ add x28, sp, #(S_FRAME_SIZE + 16)
+ /* ...and the link Register at callee entry */
+ stp x9, x28, [sp, #S_LR] /* to pt_regs.r[30] and .sp */
+ /* The program counter just after the ftrace call site */
+ str lr, [sp, #S_PC]
+
+ /* Now fill in callee's preliminary stackframe. */
+ stp x29, x9, [sp, #S_FRAME_SIZE]
+ /* Let FP point to it. */
+ add x29, sp, #S_FRAME_SIZE
+
+ /* Our stackframe, stored inside pt_regs. */
+ stp x29, x30, [sp, #S_STACKFRAME]
+ add x29, sp, #S_STACKFRAME
+ .endm
+
+ENTRY(ftrace_regs_caller)
+ ftrace_regs_entry 1
+ b ftrace_common
+ENDPROC(ftrace_regs_caller)
+
+ENTRY(ftrace_caller)
+ ftrace_regs_entry 0
+ b ftrace_common
+ENDPROC(ftrace_caller)
+
+ENTRY(ftrace_common)
+
+ mov x3, sp /* pt_regs are @sp */
+ ldr_l x2, function_trace_op, x0
+ mov x1, x9 /* parent IP */
+ sub x0, lr, #AARCH64_INSN_SIZE
+
+GLOBAL(ftrace_call)
+ bl ftrace_stub
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+GLOBAL(ftrace_graph_call) // ftrace_graph_caller();
+ nop // If enabled, this will be replaced
+ // "b ftrace_graph_caller"
+#endif
+
+/*
+ * GCC's patchable-function-entry implicitly disables IPA-RA,
+ * so all non-argument registers are either scratch / dead
+ * or callee-saved (within the ftrace framework). Function
+ * arguments of the call we are intercepting right now however
+ * need to be preserved in any case.
+ */
+ftrace_common_return:
+ /* restore function args */
+ ldp x0, x1, [sp]
+ ldp x2, x3, [sp, #S_X2]
+ ldp x4, x5, [sp, #S_X4]
+ ldp x6, x7, [sp, #S_X6]
+ ldr x8, [sp, #S_X8]
+
+ /* restore fp and x28 */
+ ldp x28, x29, [sp, #S_X28]
+
+ ldr lr, [sp, #S_LR]
+ ldr x9, [sp, #S_PC]
+ /* clean up both frames, ours and callee preliminary */
+ add sp, sp, #S_FRAME_SIZE + 16
+
+ ret x9
+ENDPROC(ftrace_common)
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(ftrace_graph_caller)
+ ldr x0, [sp, #S_PC] /* pc */
+ sub x0, x0, #AARCH64_INSN_SIZE
+ add x1, sp, #S_LR /* &lr */
+ ldr x2, [sp, #S_FRAME_SIZE] /* fp */
+ bl prepare_ftrace_return
+ b ftrace_common_return
+ENDPROC(ftrace_graph_caller)
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+#endif /* CONFIG_DYNAMIC_FTRACE_WITH_REGS */
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+ENTRY(ftrace_stub)
+ ret
+ENDPROC(ftrace_stub)
+
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
/*
* void return_to_handler(void)
*
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index 171773257974..faf339e90319 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -62,6 +62,46 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
return ftrace_modify_code(pc, 0, new, false);
}
+#ifdef CONFIG_ARM64_MODULE_PLTS
+static int install_ftrace_trampoline(struct module *mod, unsigned long *addr)
+{
+ struct plt_entry trampoline, *mod_trampoline;
+
+ /*
+ * Iterate over
+ * mod->arch.ftrace_trampolines[MOD_ARCH_NR_FTRACE_TRAMPOLINES]
+ * The assignment to various ftrace functions happens here.
+ */
+ if (*addr == FTRACE_ADDR)
+ mod_trampoline = &mod->arch.ftrace_trampolines[0];
+ else if (*addr == FTRACE_REGS_ADDR)
+ mod_trampoline = &mod->arch.ftrace_trampolines[1];
+ else
+ return -EINVAL;
+
+ trampoline = get_plt_entry(*addr, mod_trampoline);
+
+ /*
+ * Note that PLTs are place relative, and plt_entries_equal()
+ * checks whether they point to the same target. Here, we need
+ * to check if the actual opcodes are in fact identical,
+ * regardless of the offset in memory so use memcmp() instead.
+ */
+ if (memcmp(mod_trampoline, &trampoline, sizeof(trampoline))) {
+ /* point the trampoline at our ftrace entry point */
+ module_disable_ro(mod);
+ *mod_trampoline = trampoline;
+ module_enable_ro(mod, true);
+
+ /* update trampoline before patching in the branch */
+ smp_wmb();
+ }
+ *addr = (unsigned long)(void *)mod_trampoline;
+
+ return 0;
+}
+#endif
+
/*
* Turn on the call to ftrace_caller() in instrumented function
*/
@@ -73,8 +113,8 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
if (offset < -SZ_128M || offset >= SZ_128M) {
#ifdef CONFIG_ARM64_MODULE_PLTS
- struct plt_entry trampoline, *dst;
struct module *mod;
+ int ret;
/*
* On kernels that support module PLTs, the offset between the
@@ -93,40 +133,13 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
if (WARN_ON(!mod))
return -EINVAL;
- /*
- * There is only one ftrace trampoline per module. For now,
- * this is not a problem since on arm64, all dynamic ftrace
- * invocations are routed via ftrace_caller(). This will need
- * to be revisited if support for multiple ftrace entry points
- * is added in the future, but for now, the pr_err() below
- * deals with a theoretical issue only.
- *
- * Note that PLTs are place relative, and plt_entries_equal()
- * checks whether they point to the same target. Here, we need
- * to check if the actual opcodes are in fact identical,
- * regardless of the offset in memory so use memcmp() instead.
- */
- dst = mod->arch.ftrace_trampoline;
- trampoline = get_plt_entry(addr, dst);
- if (memcmp(dst, &trampoline, sizeof(trampoline))) {
- if (plt_entry_is_initialized(dst)) {
- pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n");
- return -EINVAL;
- }
-
- /* point the trampoline to our ftrace entry point */
- module_disable_ro(mod);
- *dst = trampoline;
- module_enable_ro(mod, true);
-
- /*
- * Ensure updated trampoline is visible to instruction
- * fetch before we patch in the branch.
- */
- __flush_icache_range((unsigned long)&dst[0],
- (unsigned long)&dst[1]);
- }
- addr = (unsigned long)dst;
+ /* Check against our well-known list of ftrace entry points */
+ if (addr == FTRACE_ADDR || addr == FTRACE_REGS_ADDR) {
+ ret = install_ftrace_trampoline(mod, &addr);
+ if (ret < 0)
+ return ret;
+ } else
+ return -EINVAL;
#else /* CONFIG_ARM64_MODULE_PLTS */
return -EINVAL;
#endif /* CONFIG_ARM64_MODULE_PLTS */
@@ -138,6 +151,45 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
return ftrace_modify_code(pc, old, new, true);
}
+#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
+int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
+ unsigned long addr)
+{
+ unsigned long pc = rec->ip;
+ u32 old, new;
+
+ old = aarch64_insn_gen_branch_imm(pc, old_addr,
+ AARCH64_INSN_BRANCH_LINK);
+ new = aarch64_insn_gen_branch_imm(pc, addr, AARCH64_INSN_BRANCH_LINK);
+
+ return ftrace_modify_code(pc, old, new, true);
+}
+
+/*
+ * Ftrace with regs generates the tracer calls as close as possible to
+ * the function entry; no stack frame has been set up at that point.
+ * In order to make another call e.g to ftrace_caller, the LR must be
+ * saved from being overwritten.
+ * Between two functions, and with IPA-RA turned off, the scratch registers
+ * are available, so move the LR to x9 before calling into ftrace.
+ *
+ * This function is called once during kernel startup for each call site.
+ * The address passed is that of the actual branch, so patch in the LR saver
+ * just before that.
+ */
+static int ftrace_setup_lr_saver(unsigned long addr)
+{
+ u32 old, new;
+
+ old = aarch64_insn_gen_nop();
+ /* "mov x9, lr" is officially aliased from "orr x9, xzr, lr". */
+ new = aarch64_insn_gen_logical_shifted_reg(AARCH64_INSN_REG_9,
+ AARCH64_INSN_REG_ZR, AARCH64_INSN_REG_LR, 0,
+ AARCH64_INSN_VARIANT_64BIT, AARCH64_INSN_LOGIC_ORR);
+ return ftrace_modify_code(addr - AARCH64_INSN_SIZE, old, new, true);
+}
+#endif
+
/*
* Turn off the call to ftrace_caller() in instrumented function
*/
@@ -196,6 +248,22 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
return ftrace_modify_code(pc, old, new, validate);
}
+int ftrace_call_init(struct module *mod, struct dyn_ftrace *rec)
+{
+ unsigned long pc = rec->ip;
+
+ /*
+ * -fpatchable-function-entry= does not generate a profiling call
+ * initially; the NOPs are already there. So instead,
+ * put the LR saver there ahead of time, in order to avoid
+ * any race condition over patching 2 instructions.
+ */
+ if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS))
+ return ftrace_setup_lr_saver(pc);
+ else
+ return ftrace_make_nop(mod, rec, (unsigned long)_mcount);
+}
+
void arch_ftrace_update_code(int command)
{
command |= FTRACE_MAY_SLEEP;
diff --git a/arch/arm64/kernel/module-plts.c b/arch/arm64/kernel/module-plts.c
index 044c0ae4d6c8..acafb8a2244d 100644
--- a/arch/arm64/kernel/module-plts.c
+++ b/arch/arm64/kernel/module-plts.c
@@ -330,7 +330,8 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
tramp->sh_type = SHT_NOBITS;
tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
tramp->sh_addralign = __alignof__(struct plt_entry);
- tramp->sh_size = sizeof(struct plt_entry);
+ tramp->sh_size = MOD_ARCH_NR_FTRACE_TRAMPOLINES
+ * sizeof(struct plt_entry);
}
return 0;
diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c
index 03ff15bffbb6..4e1d99805c5a 100644
--- a/arch/arm64/kernel/module.c
+++ b/arch/arm64/kernel/module.c
@@ -483,7 +483,7 @@ int module_finalize(const Elf_Ehdr *hdr,
#ifdef CONFIG_ARM64_MODULE_PLTS
if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
!strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
- me->arch.ftrace_trampoline = (void *)s->sh_addr;
+ me->arch.ftrace_trampolines = (void *)s->sh_addr;
#endif
}
--
2.23.0.rc1
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^ permalink raw reply related
* Re: [PATCH v4 11/21] ARM: dts: imx6qdl-apalis: Add sleep state to can interfaces
From: Shawn Guo @ 2019-08-19 11:27 UTC (permalink / raw)
To: Philippe Schenker
Cc: Mark Rutland, devicetree@vger.kernel.org, Michal Vokáč,
Pengutronix Kernel Team, Marcel Ziswiler, Sascha Hauer,
linux-kernel@vger.kernel.org, stefan@agner.ch, Rob Herring,
NXP Linux Team, Max Krummenacher, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190812142105.1995-12-philippe.schenker@toradex.com>
On Mon, Aug 12, 2019 at 02:21:31PM +0000, Philippe Schenker wrote:
> This patch prepares the devicetree for the new Ixora V1.2 where we are
> able to turn off the supply of the can transceiver. This implies to use
> a sleep state on transmission pins in order to prevent backfeeding.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v4:
> - Add Marcel Ziswiler's Ack
>
> Changes in v3: None
> Changes in v2:
> - Changed commit title to '...imx6qdl-apalis:...'
>
> arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 +++++++++++++++++++++------
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> index 7c4ad541c3f5..59ed2e4a1fd1 100644
> --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> @@ -148,14 +148,16 @@
> };
>
> &can1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_flexcan1>;
This line doesn't need to be changed.
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_flexcan1_default>;
> + pinctrl-1 = <&pinctrl_flexcan1_sleep>;
> status = "disabled";
> };
>
> &can2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_flexcan2>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_flexcan2_default>;
> + pinctrl-1 = <&pinctrl_flexcan2_sleep>;
> status = "disabled";
> };
>
> @@ -599,19 +601,32 @@
> >;
> };
>
> - pinctrl_flexcan1: flexcan1grp {
Ditto. I take them as unnecessary changes.
Shawn
> + pinctrl_flexcan1_default: flexcan1defgrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> >;
> };
>
> - pinctrl_flexcan2: flexcan2grp {
> + pinctrl_flexcan1_sleep: flexcan1slpgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
> + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
> + >;
> + };
> +
> + pinctrl_flexcan2_default: flexcan2defgrp {
> fsl,pins = <
> MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> >;
> };
> + pinctrl_flexcan2_sleep: flexcan2slpgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
> + >;
> + };
>
> pinctrl_gpio_bl_on: gpioblon {
> fsl,pins = <
> --
> 2.22.0
>
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^ permalink raw reply
* [PATCH 1/3] ftrace: introdue ftrace_call_init
From: Jisheng Zhang @ 2019-08-19 11:27 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Steven Rostedt, Mark Rutland
Cc: Torsten Duwe, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819191530.0f47b9b1@xhacker.debian>
On some arch, the FTRACE_WITH_REGS is implemented with gcc's
-fpatchable-function-entry (=2), gcc adds 2 NOPs at the beginning
of each function, so this makes the MCOUNT_ADDR useless. In ftrace
common framework, MCOUNT_ADDR is mostly used to "init" the nop, so
let's introcude ftrace_call_init().
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
include/linux/ftrace.h | 1 +
kernel/trace/ftrace.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
index 8a8cb3c401b2..8175ffb671f0 100644
--- a/include/linux/ftrace.h
+++ b/include/linux/ftrace.h
@@ -458,6 +458,7 @@ extern void ftrace_regs_caller(void);
extern void ftrace_call(void);
extern void ftrace_regs_call(void);
extern void mcount_call(void);
+extern int ftrace_call_init(struct module *mod, struct dyn_ftrace *rec);
void ftrace_modify_all_code(int command);
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index eca34503f178..9df5a66a6811 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -2500,7 +2500,11 @@ ftrace_code_disable(struct module *mod, struct dyn_ftrace *rec)
if (unlikely(ftrace_disabled))
return 0;
+#ifdef MCOUNT_ADDR
ret = ftrace_make_nop(mod, rec, MCOUNT_ADDR);
+#else
+ ret = ftrace_call_init(mod, rec);
+#endif
if (ret) {
ftrace_bug_type = FTRACE_BUG_INIT;
ftrace_bug(ret, rec);
--
2.23.0.rc1
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^ permalink raw reply related
* [PATCH 0/3] arm64: ftrace with regs
From: Jisheng Zhang @ 2019-08-19 11:26 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Steven Rostedt, Mark Rutland
Cc: Torsten Duwe, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Try to make the arm64 ftrace with regs merged.
The later two patches are from Torsten.
The whole series applies cleanly on v5.3-rc5
Jisheng Zhang (1):
ftrace: introdue ftrace_call_init
Torsten Duwe (2):
arm64: implement ftrace with regs
arm64: use -fpatchable-function-entry if available
arch/arm64/Kconfig | 2 +
arch/arm64/Makefile | 5 ++
arch/arm64/include/asm/ftrace.h | 12 ++-
arch/arm64/include/asm/module.h | 3 +-
arch/arm64/kernel/entry-ftrace.S | 125 ++++++++++++++++++++++++++--
arch/arm64/kernel/ftrace.c | 138 +++++++++++++++++++++++--------
arch/arm64/kernel/module-plts.c | 3 +-
arch/arm64/kernel/module.c | 2 +-
include/linux/ftrace.h | 1 +
kernel/module.c | 7 +-
kernel/trace/ftrace.c | 4 +
11 files changed, 257 insertions(+), 45 deletions(-)
--
2.23.0.rc1
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^ permalink raw reply
* Re: [PATCH v4 10/21] ARM: dts: imx6qdl-colibri: Add missing pin declaration in iomuxc
From: Shawn Guo @ 2019-08-19 11:25 UTC (permalink / raw)
To: Philippe Schenker
Cc: Mark Rutland, devicetree@vger.kernel.org, Michal Vokáč,
Pengutronix Kernel Team, Marcel Ziswiler, Sascha Hauer,
linux-kernel@vger.kernel.org, stefan@agner.ch, Rob Herring,
NXP Linux Team, Max Krummenacher, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190812142105.1995-11-philippe.schenker@toradex.com>
On Mon, Aug 12, 2019 at 02:21:29PM +0000, Philippe Schenker wrote:
> This adds the muxing for the optional pins usb-oc (overcurrent) and
> usb-id.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> ---
>
> Changes in v4:
> - Add Marcel Ziswiler's Ack
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/boot/dts/imx6qdl-colibri.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> index 019dda6b88ad..9a63debab0b5 100644
> --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
> @@ -615,6 +615,13 @@
> >;
> };
>
> + pinctrl_usbh_oc_1: usbh_oc-1 {
Please name it consistently in the way like:
pinctrl_xxx: xxxgrp {
...
};
Also, it doesn't need to be separate patch but can just be added
together with the device referring to it.
Shawn
> + fsl,pins = <
> + /* USBH_OC */
> + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
> + >;
> + };
> +
> pinctrl_spdif: spdifgrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
> @@ -681,6 +688,13 @@
> >;
> };
>
> + pinctrl_usbc_id_1: usbc_id-1 {
> + fsl,pins = <
> + /* USBC_ID */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
> + >;
> + };
> +
> pinctrl_usdhc1: usdhc1grp {
> fsl,pins = <
> MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
> --
> 2.22.0
>
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