* Re: [v5,05/12] drm/modes: Rewrite the command line parser
From: Jernej Škrabec @ 2019-08-19 18:54 UTC (permalink / raw)
To: Maxime Ripard
Cc: eben, David Airlie, thomas.graichen, Maarten Lankhorst, dri-devel,
Paul Kocialkowski, Sean Paul, Thomas Petazzoni, Daniel Vetter,
Maxime Ripard, linux-arm-kernel
In-Reply-To: <e32cd4009153b184103554009135c7bf7c9975d7.1560783090.git-series.maxime.ripard@bootlin.com>
+CC: Thomas Graichen
Dne ponedeljek, 17. junij 2019 ob 16:51:32 CEST je Maxime Ripard napisal(a):
> From: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Rewrite the command line parser in order to get away from the state machine
> parsing the video mode lines.
>
> Hopefully, this will allow to extend it more easily to support named modes
> and / or properties set directly on the command line.
>
> Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thomas reported to me that this patch breaks "video=CONNECTOR:e" kernel
parameter which he currently uses as a workaround for H6 HDMI monitor
detection issue on one STB.
I suppose this is the same issue that Dmitry noticed.
Thomas Graichen (in CC) can provide more information if needed.
Best regards,
Jernej
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* Re: [PATCH v2 4/6] dt-bindings: watchdog: sun4i: Add the watchdog clock
From: Rob Herring @ 2019-08-19 18:56 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Maxime Ripard,
linux-kernel@vger.kernel.org, Chen-Yu Tsai,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Wim Van Sebroeck, Frank Rowand, Guenter Roeck
In-Reply-To: <20190819182039.24892-4-mripard@kernel.org>
On Mon, Aug 19, 2019 at 1:20 PM Maxime Ripard <mripard@kernel.org> wrote:
>
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The Allwinner watchdog has a clock that has been described in some DT, but
> not all of them.
>
> The binding is also completely missing that description. Let's add that
> property to be consistent.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v1:
> - New patch
> ---
> .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
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* Re: Build regression in Linux 5.3-rc5 with CONFIG_XEN=y
From: Robin Murphy @ 2019-08-19 19:02 UTC (permalink / raw)
To: Stefan Wahren, Christoph Hellwig, Marek Szyprowski
Cc: iommu, linux-arm-kernel
In-Reply-To: <ebd95b7c-d265-cbf1-be50-945db1dd06ad@gmx.net>
On 19/08/2019 19:37, Stefan Wahren wrote:
> Hi,
>
> i tried to cross compile arm/multi_v7_defconfig with CONFIG_XEN=y with
> Linux 5.3-rc5 and i'm getting this:
>
> arch/arm/mm/dma-mapping.c: In function ‘arch_setup_dma_ops’:
> arch/arm/mm/dma-mapping.c:2347:5: error: ‘struct device’ has no member
> named ‘dma_coherent’
> dev->dma_coherent = coherent;
> ^~
> arch/arm/mm/dma-mapping.c: At top level:
> arch/arm/mm/dma-mapping.c:2385:6: error: redefinition of
> ‘arch_sync_dma_for_device’
> void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
> ^~~~~~~~~~~~~~~~~~~~~~~~
> In file included from arch/arm/mm/dma-mapping.c:18:0:
> ./include/linux/dma-noncoherent.h:67:20: note: previous definition of
> ‘arch_sync_dma_for_device’ was here
> static inline void arch_sync_dma_for_device(struct device *dev,
> ^~~~~~~~~~~~~~~~~~~~~~~~
> arch/arm/mm/dma-mapping.c:2392:6: error: redefinition of
> ‘arch_sync_dma_for_cpu’
> void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
> ^~~~~~~~~~~~~~~~~~~~~
> In file included from arch/arm/mm/dma-mapping.c:18:0:
> ./include/linux/dma-noncoherent.h:77:20: note: previous definition of
> ‘arch_sync_dma_for_cpu’ was here
> static inline void arch_sync_dma_for_cpu(struct device *dev,
> ^~~~~~~~~~~~~~~~~~~~~
> In file included from ./arch/arm/include/asm/page.h:149:0,
> from ./arch/arm/include/asm/thread_info.h:14,
> from ./include/linux/thread_info.h:38,
> from ./include/asm-generic/preempt.h:5,
> from ./arch/arm/include/generated/asm/preempt.h:1,
> from ./include/linux/preempt.h:78,
> from ./include/linux/spinlock.h:51,
> from ./include/linux/seqlock.h:36,
> from ./include/linux/time.h:6,
> from ./include/linux/stat.h:19,
> from ./include/linux/module.h:10,
> from arch/arm/mm/dma-mapping.c:9:
>
> There is no build issue with Linux 5.2, so this must be introduced with
> 5.3-rc. I hope you have a clue without bisecting this.
Oh, that must be ad3c7b18c5b, since the dma-noncoherent stuff is only
selected by CONFIG_ARM_LPAE, but the references to it are guarded by
CONFIG_SWIOTLB, and CONFIG_XEN brings in the latter without the former.
Robin.
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^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: watchdog: Add YAML schemas for the generic watchdog bindings
From: Rob Herring @ 2019-08-19 19:04 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Maxime Ripard,
linux-kernel@vger.kernel.org, Chen-Yu Tsai,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Wim Van Sebroeck, Frank Rowand, Guenter Roeck
In-Reply-To: <20190819182039.24892-1-mripard@kernel.org>
On Mon, Aug 19, 2019 at 1:20 PM Maxime Ripard <mripard@kernel.org> wrote:
>
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The watchdogs have a bunch of generic properties that are needed in a
> device tree. Add a YAML schemas for those.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v1:
> - New patch
> ---
> .../bindings/watchdog/watchdog.yaml | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/watchdog/watchdog.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
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* [GIT PULL 1/3] Broadcom defconfig changes for 5.4
From: Florian Fainelli @ 2019-08-19 19:05 UTC (permalink / raw)
To: arm
Cc: Stefan Wahren, Florian Fainelli, arnd, khilman,
bcm-kernel-feedback-list, Stefan Wahren, olof,
Nicolas Saenz Julienne, linux-arm-kernel
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://github.com/Broadcom/stblinux.git tags/arm-soc/for-5.4/defconfig
for you to fetch changes up to c474106e1e8a8f335b1bd3e79e868943689ae74d:
Merge tag 'tags/bcm2835-defconfig-next-2019-08-15' into defconfig/next (2019-08-15 11:37:54 -0700)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based SoCs defconfig updates for
5.4, please pull the following:
- Nicolas enables the Raspberry Pi CPUFREQ driver in both
bcm2835_defconfig and multi_v7_defconfig
----------------------------------------------------------------
Florian Fainelli (1):
Merge tag 'tags/bcm2835-defconfig-next-2019-08-15' into defconfig/next
Nicolas Saenz Julienne (1):
ARM: defconfig: enable cpufreq driver for RPi
arch/arm/configs/bcm2835_defconfig | 9 +++++++++
arch/arm/configs/multi_v7_defconfig | 2 ++
2 files changed, 11 insertions(+)
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* [GIT PULL 2/3] Broadcom defconfig-arm64 changes for 5.4
From: Florian Fainelli @ 2019-08-19 19:05 UTC (permalink / raw)
To: arm
Cc: Stefan Wahren, Florian Fainelli, arnd, khilman,
bcm-kernel-feedback-list, Stefan Wahren, olof,
Nicolas Saenz Julienne, linux-arm-kernel
In-Reply-To: <20190819190552.11254-1-f.fainelli@gmail.com>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://github.com/Broadcom/stblinux.git tags/arm-soc/for-5.4/defconfig-arm64
for you to fetch changes up to d6cc9ddd23f8b113797152896462b27e2b213ece:
Merge tag 'tags/bcm2835-defconfig-64-next-2019-08-15' into defconfig-arm64/next (2019-08-15 11:38:29 -0700)
----------------------------------------------------------------
This pull request contains Broadcom ARM64-based SoCs defconfig updates
for 5.4, please pull the following:
- Nicolas enables the Raspberry Pi CPUFREQ driver in the ARM64 defconfig file
----------------------------------------------------------------
Florian Fainelli (1):
Merge tag 'tags/bcm2835-defconfig-64-next-2019-08-15' into defconfig-arm64/next
Nicolas Saenz Julienne (1):
arm64: defconfig: enable cpufreq support for RPi3
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
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* [GIT PULL 3/3] Broadcom devicetree changes for 5.4
From: Florian Fainelli @ 2019-08-19 19:05 UTC (permalink / raw)
To: arm
Cc: Florian Fainelli, arnd, khilman, Eric Anholt,
bcm-kernel-feedback-list, Stefan Wahren, olof, linux-arm-kernel
In-Reply-To: <20190819190552.11254-1-f.fainelli@gmail.com>
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://github.com/Broadcom/stblinux.git tags/arm-soc/for-5.4/devicetree
for you to fetch changes up to f1bace1efd6fa5d516b045379f34f6d736ec3bf0:
Merge tag 'tags/bcm2835-dt-next-2019-08-15' into devicetree/next (2019-08-15 11:37:14 -0700)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 5.4, please pull the following:
- Stefan does a bunch of preparatory work for supporting the Raspberry
Pi 4in the next merge window correct register ranges (SPI, I2C,
UART), define memory, HDMI and MMC properties at the board level
----------------------------------------------------------------
Florian Fainelli (1):
Merge tag 'tags/bcm2835-dt-next-2019-08-15' into devicetree/next
Stefan Wahren (4):
ARM: bcm283x: Reduce register ranges for UART, SPI and I2C
ARM: dts: bcm283x: Define MMC interfaces at board level
ARM: dts: bcm283x: Define memory at board level
ARM: dts: bcm283x: Enable HDMI at board level
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-a.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-b.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 9 +++++++++
arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi | 5 +++++
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 14 ++++++++++++++
arch/arm/boot/dts/bcm2835-rpi.dtsi | 23 -----------------------
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 10 ++++++++++
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 3 +++
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 3 +++
arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 3 +++
arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 9 +++++++++
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 1 +
arch/arm/boot/dts/bcm283x.dtsi | 6 +++---
17 files changed, 144 insertions(+), 26 deletions(-)
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* Re: [PATCH v2 2/6] dt-bindings: watchdog: Convert Allwinner watchdog to a schema
From: Rob Herring @ 2019-08-19 19:06 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Maxime Ripard,
linux-kernel@vger.kernel.org, Chen-Yu Tsai,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Wim Van Sebroeck, Frank Rowand, Guenter Roeck
In-Reply-To: <20190819182039.24892-2-mripard@kernel.org>
On Mon, Aug 19, 2019 at 1:20 PM Maxime Ripard <mripard@kernel.org> wrote:
>
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The Allwinner SoCs have a watchdog supported in Linux, with a matching
> Device Tree binding.
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for that controller over to a YAML schemas.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v1:
> - Use generic watchdog schema
> - Use unevaluatedProperties instead of additionalProperties
> ---
> .../watchdog/allwinner,sun4i-a10-wdt.yaml | 48 +++++++++++++++++++
> .../bindings/watchdog/sunxi-wdt.txt | 22 ---------
> 2 files changed, 48 insertions(+), 22 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> delete mode 100644 Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
Reviewed-by: Rob Herring <robh@kernel.org>
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* Re: [PATCH v4 1/2] dt-bindings: arm: imx: add imx8mq nitrogen support
From: Rob Herring @ 2019-08-19 19:08 UTC (permalink / raw)
To: Dafna Hirschfeld
Cc: Mark Rutland, devicetree, Ezequiel Garcia, Sascha Hauer,
linux-kernel@vger.kernel.org, Troy Kisky, Gary Bisson,
Sascha Hauer, kernel, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190819172606.6410-2-dafna.hirschfeld@collabora.com>
On Mon, Aug 19, 2019 at 12:26 PM Dafna Hirschfeld
<dafna.hirschfeld@collabora.com> wrote:
>
> From: Gary Bisson <gary.bisson@boundarydevices.com>
>
> The Nitrogen8M is an ARM based single board computer (SBC)
> designed to leverage the full capabilities of NXP’s i.MX8M
> Quad processor.
>
> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> [Dafna: porting vendor's code to mainline]
> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
> 1 file changed, 1 insertion(+)
Please add acks/reviewed-bys when posting new versions.
Rob
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* Re: Build regression in Linux 5.3-rc5 with CONFIG_XEN=y
From: Stefan Wahren @ 2019-08-19 19:12 UTC (permalink / raw)
To: Robin Murphy, Christoph Hellwig, Marek Szyprowski; +Cc: iommu, linux-arm-kernel
In-Reply-To: <825549ed-8aa4-b418-8812-15a9d3cc153e@arm.com>
Am 19.08.19 um 21:02 schrieb Robin Murphy:
> On 19/08/2019 19:37, Stefan Wahren wrote:
>> Hi,
>>
>> i tried to cross compile arm/multi_v7_defconfig with CONFIG_XEN=y with
>> Linux 5.3-rc5 and i'm getting this:
>>
>> arch/arm/mm/dma-mapping.c: In function ‘arch_setup_dma_ops’:
>> arch/arm/mm/dma-mapping.c:2347:5: error: ‘struct device’ has no member
>> named ‘dma_coherent’
>> dev->dma_coherent = coherent;
>> ^~
>> arch/arm/mm/dma-mapping.c: At top level:
>> arch/arm/mm/dma-mapping.c:2385:6: error: redefinition of
>> ‘arch_sync_dma_for_device’
>> void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
>> ^~~~~~~~~~~~~~~~~~~~~~~~
>> In file included from arch/arm/mm/dma-mapping.c:18:0:
>> ./include/linux/dma-noncoherent.h:67:20: note: previous definition of
>> ‘arch_sync_dma_for_device’ was here
>> static inline void arch_sync_dma_for_device(struct device *dev,
>> ^~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm/mm/dma-mapping.c:2392:6: error: redefinition of
>> ‘arch_sync_dma_for_cpu’
>> void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
>> ^~~~~~~~~~~~~~~~~~~~~
>> In file included from arch/arm/mm/dma-mapping.c:18:0:
>> ./include/linux/dma-noncoherent.h:77:20: note: previous definition of
>> ‘arch_sync_dma_for_cpu’ was here
>> static inline void arch_sync_dma_for_cpu(struct device *dev,
>> ^~~~~~~~~~~~~~~~~~~~~
>> In file included from ./arch/arm/include/asm/page.h:149:0,
>> from ./arch/arm/include/asm/thread_info.h:14,
>> from ./include/linux/thread_info.h:38,
>> from ./include/asm-generic/preempt.h:5,
>> from ./arch/arm/include/generated/asm/preempt.h:1,
>> from ./include/linux/preempt.h:78,
>> from ./include/linux/spinlock.h:51,
>> from ./include/linux/seqlock.h:36,
>> from ./include/linux/time.h:6,
>> from ./include/linux/stat.h:19,
>> from ./include/linux/module.h:10,
>> from arch/arm/mm/dma-mapping.c:9:
>>
>> There is no build issue with Linux 5.2, so this must be introduced with
>> 5.3-rc. I hope you have a clue without bisecting this.
>
> Oh, that must be ad3c7b18c5b, since the dma-noncoherent stuff is only
> selected by CONFIG_ARM_LPAE, but the references to it are guarded by
> CONFIG_SWIOTLB, and CONFIG_XEN brings in the latter without the former.
Yes, reverting ad3c7b18c5b ("arm: use swiotlb for bounce buffering on
LPAE configs") avoid this build issue.
>
> Robin.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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* Re: [PATCH 03/11] clocksource: sun4i: Add missing compatibles
From: Maxime Ripard @ 2019-08-19 19:13 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Rob Herring, tglx,
Frank Rowand, linux-arm-kernel
In-Reply-To: <0e36a6fe-33de-5af5-f4f9-4cedfc9d0cbf@linaro.org>
On Mon, Aug 19, 2019 at 03:45:40PM +0200, Daniel Lezcano wrote:
> On 19/08/2019 15:30, Maxime Ripard wrote:
> > On Mon, Aug 12, 2019 at 01:24:11PM +0200, Maxime Ripard wrote:
> >> On Mon, Aug 12, 2019 at 11:21:50AM +0200, Daniel Lezcano wrote:
> >>> On 12/08/2019 11:16, Maxime Ripard wrote:
> >>>> Hi,
> >>>>
> >>>> On Mon, Aug 12, 2019 at 10:59:51AM +0200, Daniel Lezcano wrote:
> >>>>> On 22/07/2019 10:12, Maxime Ripard wrote:
> >>>>>> Newer Allwinner SoCs have different number of interrupts, let's add
> >>>>>> different compatibles for all of them to deal with this properly.
> >>>>>>
> >>>>>> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> >>>>>
> >>>>> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> >>>>
> >>>> Thanks!
> >>>>
> >>>> Can you merge this through your tree (along with the bindings)? I'll
> >>>> merge the DT patches
> >>>
> >>> patches 1-4 then ?
> >>
> >> Yep, thanks!
> >
> > Ping?
>
> They are applied :)
Oh, my bad :)
Where is your tree these days? I couldn't find it in linux-next either
:/
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH v3 4/8] dt-bindings: clock: Add devicetree binding for BM1880 SoC
From: Rob Herring @ 2019-08-19 19:18 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: devicetree, Stephen Boyd, Michael Turquette,
linux-kernel@vger.kernel.org, darren.tsao, haitao.suo,
fisher.cheng, alec.lin, linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190819130143.18778-5-manivannan.sadhasivam@linaro.org>
On Mon, Aug 19, 2019 at 8:02 AM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Add YAML devicetree binding for Bitmain BM1880 SoC.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../bindings/clock/bitmain,bm1880-clk.yaml | 83 +++++++++++++++++++
> include/dt-bindings/clock/bm1880-clock.h | 82 ++++++++++++++++++
> 2 files changed, 165 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
> create mode 100644 include/dt-bindings/clock/bm1880-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
> new file mode 100644
> index 000000000000..a457f996287d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bitmain BM1880 Clock Controller
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +description: |
> + The Bitmain BM1880 clock controller generates and supplies clock to
> + various peripherals within the SoC.
> +
> + This binding uses common clock bindings
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - bitmain,bm1880-clk
Just 'const: bitmain,bm1880-clk' is enough.
> +
> + reg:
> + minItems: 2
> + maxItems: 2
These 2 are implied by the items list and can be dropped.
> + items:
> + - description: pll registers
> + - description: system registers
> +
> + reg-names:
> + items:
> + - const: pll
> + - const: sys
> +
> + clocks:
> + maxItems: 1
> + description: Phandle of the input reference clock
Don't need a description if there's only one entry.
> +
> + clock-names:
> + maxItems: 1
> + items:
> + - const: osc
Just:
clock-names:
const: osc
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - '#clock-cells'
> +
> +examples:
> + # Clock controller node:
> + - |
> + clk: clock-controller@e8 {
> + compatible = "bitmain,bm1880-clk";
> + reg = <0xe8 0x0c>, <0x800 0xb0>;
> + reg-names = "pll", "sys";
> + clocks = <&osc>;
> + clock-names = "osc";
> + #clock-cells = <1>;
> + };
> +
> + # Example UART controller node that consumes clock generated by the clock controller:
> + - |
> + uart0: serial@58018000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x58018000 0x0 0x2000>;
> + clocks = <&clk BM1880_CLK_UART_500M>;
> + <&clk BM1880_CLK_APB_UART>;
This won't build without includes. Please run 'make dt_binding_check'
before you submit bindings.
> + clock-names = "baudclk", "apb_pclk";
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h
> new file mode 100644
> index 000000000000..895646d66b07
> --- /dev/null
> +++ b/include/dt-bindings/clock/bm1880-clock.h
> @@ -0,0 +1,82 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Device Tree binding constants for Bitmain BM1880 SoC
> + *
> + * Copyright (c) 2019 Linaro Ltd.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_BM1880_H
> +#define __DT_BINDINGS_CLOCK_BM1880_H
> +
> +#define BM1880_CLK_OSC 0
> +#define BM1880_CLK_MPLL 1
> +#define BM1880_CLK_SPLL 2
> +#define BM1880_CLK_FPLL 3
> +#define BM1880_CLK_DDRPLL 4
> +#define BM1880_CLK_A53 5
> +#define BM1880_CLK_50M_A53 6
> +#define BM1880_CLK_AHB_ROM 7
> +#define BM1880_CLK_AXI_SRAM 8
> +#define BM1880_CLK_DDR_AXI 9
> +#define BM1880_CLK_EFUSE 10
> +#define BM1880_CLK_APB_EFUSE 11
> +#define BM1880_CLK_AXI5_EMMC 12
> +#define BM1880_CLK_EMMC 13
> +#define BM1880_CLK_100K_EMMC 14
> +#define BM1880_CLK_AXI5_SD 15
> +#define BM1880_CLK_SD 16
> +#define BM1880_CLK_100K_SD 17
> +#define BM1880_CLK_500M_ETH0 18
> +#define BM1880_CLK_AXI4_ETH0 19
> +#define BM1880_CLK_500M_ETH1 20
> +#define BM1880_CLK_AXI4_ETH1 21
> +#define BM1880_CLK_AXI1_GDMA 22
> +#define BM1880_CLK_APB_GPIO 23
> +#define BM1880_CLK_APB_GPIO_INTR 24
> +#define BM1880_CLK_GPIO_DB 25
> +#define BM1880_CLK_AXI1_MINER 26
> +#define BM1880_CLK_AHB_SF 27
> +#define BM1880_CLK_SDMA_AXI 28
> +#define BM1880_CLK_SDMA_AUD 29
> +#define BM1880_CLK_APB_I2C 30
> +#define BM1880_CLK_APB_WDT 31
> +#define BM1880_CLK_APB_JPEG 32
> +#define BM1880_CLK_JPEG_AXI 33
> +#define BM1880_CLK_AXI5_NF 34
> +#define BM1880_CLK_APB_NF 35
> +#define BM1880_CLK_NF 36
> +#define BM1880_CLK_APB_PWM 37
> +#define BM1880_CLK_DIV_0_RV 38
> +#define BM1880_CLK_DIV_1_RV 39
> +#define BM1880_CLK_MUX_RV 40
> +#define BM1880_CLK_RV 41
> +#define BM1880_CLK_APB_SPI 42
> +#define BM1880_CLK_TPU_AXI 43
> +#define BM1880_CLK_DIV_UART_500M 44
> +#define BM1880_CLK_UART_500M 45
> +#define BM1880_CLK_APB_UART 46
> +#define BM1880_CLK_APB_I2S 47
> +#define BM1880_CLK_AXI4_USB 48
> +#define BM1880_CLK_APB_USB 49
> +#define BM1880_CLK_125M_USB 50
> +#define BM1880_CLK_33K_USB 51
> +#define BM1880_CLK_DIV_12M_USB 52
> +#define BM1880_CLK_12M_USB 53
> +#define BM1880_CLK_APB_VIDEO 54
> +#define BM1880_CLK_VIDEO_AXI 55
> +#define BM1880_CLK_VPP_AXI 56
> +#define BM1880_CLK_APB_VPP 57
> +#define BM1880_CLK_DIV_0_AXI1 58
> +#define BM1880_CLK_DIV_1_AXI1 59
> +#define BM1880_CLK_AXI1 60
> +#define BM1880_CLK_AXI2 61
> +#define BM1880_CLK_AXI3 62
> +#define BM1880_CLK_AXI4 63
> +#define BM1880_CLK_AXI5 64
> +#define BM1880_CLK_DIV_0_AXI6 65
> +#define BM1880_CLK_DIV_1_AXI6 66
> +#define BM1880_CLK_MUX_AXI6 67
> +#define BM1880_CLK_AXI6 68
> +#define BM1880_NR_CLKS 69
> +
> +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [v5,05/12] drm/modes: Rewrite the command line parser
From: Thomas Graichen @ 2019-08-19 19:20 UTC (permalink / raw)
To: Jernej Škrabec
Cc: eben, Maxime Ripard, Maarten Lankhorst, dri-devel,
Paul Kocialkowski, David Airlie, Sean Paul, Thomas Petazzoni,
Daniel Vetter, Maxime Ripard, linux-arm-kernel
In-Reply-To: <5978761.uBj7R84RrF@jernej-laptop>
On Mon, Aug 19, 2019 at 8:54 PM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> +CC: Thomas Graichen
>
> Dne ponedeljek, 17. junij 2019 ob 16:51:32 CEST je Maxime Ripard napisal(a):
> > From: Maxime Ripard <maxime.ripard@free-electrons.com>
> >
> > Rewrite the command line parser in order to get away from the state machine
> > parsing the video mode lines.
> >
> > Hopefully, this will allow to extend it more easily to support named modes
> > and / or properties set directly on the command line.
> >
> > Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Thomas reported to me that this patch breaks "video=CONNECTOR:e" kernel
> parameter which he currently uses as a workaround for H6 HDMI monitor
> detection issue on one STB.
>
> I suppose this is the same issue that Dmitry noticed.
>
> Thomas Graichen (in CC) can provide more information if needed.
>
> Best regards,
> Jernej
as jernej already mentioned i am currently having to use the kernel
cmdline option video=HDMI-A-1:e to get a working hdmi output on an
eachlink h6 mini tv box and was wondering that i did not get any hdmi
output even with this option when switching from the
https://github.com/megous/linux oprange-pi-5.2 to the orange-pi-5.3
branch which seems to contain this patch. as i had no idea what might
have caused the breakage of the hdmi output and did a full bisect of
the kernel between those two versions, which ended reliably at exactly
this patch - so i guess there is a regression at least with the
video=CONNECTOR:e option (maybe others too?) with this patches code
which makes it not working anymore.
best wishes - thomas
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^ permalink raw reply
* [PATCH 00/21] ASoC: sun4i-i2s: Number of fixes and TDM Support
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
From: Maxime Ripard <maxime.ripard@bootlin.com>
Hi,
This series aims at fixing a number of issues in the current i2s driver,
mostly related to the i2s master support and the A83t support. It also uses
that occasion to cleanup a few things and simplify the driver. Finally, it
builds on those fixes and cleanups to introduce TDM and DSP formats support.
Let me know what you think,
Maxime
Marcus Cooper (1):
ASoC: sun4i-i2s: Fix the MCLK and BCLK dividers on newer SoCs
Maxime Ripard (20):
ASoC: sun4i-i2s: Register regmap and PCM before our component
ASoC: sun4i-i2s: Switch to devm for PCM register
ASoC: sun4i-i2s: Replace call to params_channels by local variable
ASoC: sun4i-i2s: Move the channel configuration to a callback
ASoC: sun4i-i2s: Move the format configuration to a callback
ASoC: sun4i-i2s: Rework MCLK divider calculation
ASoC: sun4i-i2s: Don't use the oversample to calculate BCLK
ASoC: sun4i-i2s: Use module clock as BCLK parent on newer SoCs
ASoC: sun4i-i2s: RX and TX counter registers are swapped
ASoC: sun4i-i2s: Use the actual format width instead of an hardcoded one
ASoC: sun4i-i2s: Fix LRCK and BCLK polarity offsets on newer SoCs
ASoC: sun4i-i2s: Fix the LRCK polarity
ASoC: sun4i-i2s: Fix WSS and SR fields for the A83t
ASoC: sun4i-i2s: Fix MCLK Enable bit offset on A83t
ASoC: sun4i-i2s: Fix the LRCK period on A83t
ASoC: sun4i-i2s: Remove duplicated quirks structure
ASoC: sun4i-i2s: Pass the channels number as an argument
ASoC: sun4i-i2s: Support more channels
ASoC: sun4i-i2s: Add support for TDM slots
ASoC: sun4i-i2s: Add support for DSP formats
sound/soc/sunxi/sun4i-i2s.c | 660 ++++++++++++++++++++-----------------
1 file changed, 372 insertions(+), 288 deletions(-)
base-commit: d45331b00ddb179e291766617259261c112db872
--
git-series 0.9.1
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^ permalink raw reply
* [PATCH 01/21] ASoC: sun4i-i2s: Register regmap and PCM before our component
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
So far the regmap and the dmaengine PCM are registered after our component
has been, which means that our driver isn't properly initialised by then.
Let's fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 7fa5c61169db..85c3b2c8cd77 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1148,11 +1148,9 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
goto err_pm_disable;
}
- ret = devm_snd_soc_register_component(&pdev->dev,
- &sun4i_i2s_component,
- &sun4i_i2s_dai, 1);
+ ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
if (ret) {
- dev_err(&pdev->dev, "Could not register DAI\n");
+ dev_err(&pdev->dev, "Could not initialise regmap fields\n");
goto err_suspend;
}
@@ -1162,9 +1160,11 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
goto err_suspend;
}
- ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &sun4i_i2s_component,
+ &sun4i_i2s_dai, 1);
if (ret) {
- dev_err(&pdev->dev, "Could not initialise regmap fields\n");
+ dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
}
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 02/21] ASoC: sun4i-i2s: Switch to devm for PCM register
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Since the introduction of the driver, a new managed helper for the
dmaengine PCM registration has been created. Let's use it to simplify a bit
our probe and remove functions.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 85c3b2c8cd77..1ed7670eae9c 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1154,7 +1154,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
goto err_suspend;
}
- ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
goto err_suspend;
@@ -1185,8 +1185,6 @@ static int sun4i_i2s_remove(struct platform_device *pdev)
{
struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
- snd_dmaengine_pcm_unregister(&pdev->dev);
-
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
sun4i_i2s_runtime_suspend(&pdev->dev);
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 03/21] ASoC: sun4i-i2s: Replace call to params_channels by local variable
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The sun4i_i2s_hw_params already has a variable holding the value returned
by params_channels, so let's just use that variable instead of calling
params_channels multiple times.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 1ed7670eae9c..ac84c29224eb 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -411,10 +411,9 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
/* Configure the channels */
regmap_field_write(i2s->field_txchansel,
- SUN4I_I2S_CHAN_SEL(params_channels(params)));
-
+ SUN4I_I2S_CHAN_SEL(channels));
regmap_field_write(i2s->field_rxchansel,
- SUN4I_I2S_CHAN_SEL(params_channels(params)));
+ SUN4I_I2S_CHAN_SEL(channels));
if (i2s->variant->has_chsel_tx_chen)
regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 14/21] ASoC: sun4i-i2s: Fix WSS and SR fields for the A83t
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The A83t has the same bit fields offsets than the A10 and A31, while this
was the first device with the new layout, fix that.
Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 9c9061621b15..b5c9774e2f60 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -1048,8 +1048,8 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
- .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
- .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.bclk_dividers = sun8i_i2s_clk_div,
.num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.mclk_dividers = sun8i_i2s_clk_div,
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 05/21] ASoC: sun4i-i2s: Move the format configuration to a callback
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The two main generations of our I2S controller require a slightly different
format configuration, mostly because of a quite different register layout
and some additional registers being needed on the newer generation.
This used to be controlled through a bunch of booleans, however this proved
to be quite impractical, especially since a bunch of SoCs forgot to set
those parameters and therefore were broken from that point of view.
Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 199 +++++++++++++++++++------------------
1 file changed, 106 insertions(+), 93 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 657041606c2f..fbbedb660cc6 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -93,6 +93,11 @@
#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
+#define SUN8I_I2S_CTRL_MODE_MASK GENMASK(5, 4)
+#define SUN8I_I2S_CTRL_MODE_RIGHT (2 << 4)
+#define SUN8I_I2S_CTRL_MODE_LEFT (1 << 4)
+#define SUN8I_I2S_CTRL_MODE_PCM (0 << 4)
+
#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
@@ -121,9 +126,7 @@ struct sun4i_i2s;
* struct sun4i_i2s_quirks - Differences between SoC variants.
*
* @has_reset: SoC needs reset deasserted.
- * @has_slave_select_bit: SoC has a bit to enable slave mode.
* @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
- * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
* @reg_offset_txdata: offset of the tx fifo.
* @sun4i_i2s_regmap: regmap config to use.
* @mclk_offset: Value by which mclkdiv needs to be adjusted.
@@ -133,13 +136,10 @@ struct sun4i_i2s;
* @field_fmt_sr: regmap field to set sample resolution.
* @field_fmt_bclk: regmap field to set clk polarity.
* @field_fmt_lrclk: regmap field to set frame polarity.
- * @field_fmt_mode: regmap field to set the operational mode.
*/
struct sun4i_i2s_quirks {
bool has_reset;
- bool has_slave_select_bit;
bool has_fmt_set_lrck_period;
- bool has_chsel_offset;
unsigned int reg_offset_txdata; /* TX FIFO */
const struct regmap_config *sun4i_i2s_regmap;
unsigned int mclk_offset;
@@ -151,12 +151,12 @@ struct sun4i_i2s_quirks {
struct reg_field field_fmt_sr;
struct reg_field field_fmt_bclk;
struct reg_field field_fmt_lrclk;
- struct reg_field field_fmt_mode;
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
int (*set_chan_cfg)(const struct sun4i_i2s *,
const struct snd_pcm_hw_params *);
+ int (*set_fmt)(const struct sun4i_i2s *, unsigned int);
};
struct sun4i_i2s {
@@ -176,7 +176,6 @@ struct sun4i_i2s {
struct regmap_field *field_fmt_sr;
struct regmap_field *field_fmt_bclk;
struct regmap_field *field_fmt_lrclk;
- struct regmap_field *field_fmt_mode;
const struct sun4i_i2s_quirks *variant;
};
@@ -466,52 +465,117 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
params_width(params));
}
-static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+ unsigned int fmt)
{
- struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
- u32 offset = 0;
- u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
- u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
val = SUN4I_I2S_FMT0_FMT_I2S;
- offset = 1;
break;
+
case SND_SOC_DAIFMT_LEFT_J:
val = SUN4I_I2S_FMT0_FMT_LEFT_J;
break;
+
case SND_SOC_DAIFMT_RIGHT_J:
val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
break;
+
default:
- dev_err(dai->dev, "Unsupported format: %d\n",
- fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
- if (i2s->variant->has_chsel_offset) {
- /*
- * offset being set indicates that we're connected to an i2s
- * device, however offset is only used on the sun8i block and
- * i2s shares the same setting with the LJ format. Increment
- * val so that the bit to value to write is correct.
- */
- if (offset > 0)
- val++;
- /* blck offset determines whether i2s or LJ */
- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
- SUN8I_I2S_TX_CHAN_OFFSET_MASK,
- SUN8I_I2S_TX_CHAN_OFFSET(offset));
-
- regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
- SUN8I_I2S_TX_CHAN_OFFSET_MASK,
- SUN8I_I2S_TX_CHAN_OFFSET(offset));
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
+ SUN4I_I2S_FMT0_FMT_MASK, val);
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ /* BCLK and LRCLK master */
+ val = SUN4I_I2S_CTRL_MODE_MASTER;
+ break;
+
+ case SND_SOC_DAIFMT_CBM_CFM:
+ /* BCLK and LRCLK slave */
+ val = SUN4I_I2S_CTRL_MODE_SLAVE;
+ break;
+
+ default:
+ return -EINVAL;
}
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN4I_I2S_CTRL_MODE_MASK, val);
+ return 0;
+}
- regmap_field_write(i2s->field_fmt_mode, val);
+static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
+ unsigned int fmt)
+{
+ u32 mode, val;
+ u8 offset;
+
+ /* DAI Mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 1;
+ break;
+
+ case SND_SOC_DAIFMT_LEFT_J:
+ mode = SUN8I_I2S_CTRL_MODE_LEFT;
+ offset = 0;
+ break;
+
+ case SND_SOC_DAIFMT_RIGHT_J:
+ mode = SUN8I_I2S_CTRL_MODE_RIGHT;
+ offset = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_MODE_MASK, mode);
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(offset));
+ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
+ SUN8I_I2S_TX_CHAN_OFFSET_MASK,
+ SUN8I_I2S_TX_CHAN_OFFSET(offset));
+
+ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ /* BCLK and LRCLK master */
+ val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
+ break;
+
+ case SND_SOC_DAIFMT_CBM_CFM:
+ /* BCLK and LRCLK slave */
+ val = 0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+ SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
+ val);
+
+ return 0;
+}
+
+static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+ int ret;
/* DAI clock polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -539,50 +603,10 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
- if (i2s->variant->has_slave_select_bit) {
- /* DAI clock master masks */
- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- case SND_SOC_DAIFMT_CBS_CFS:
- /* BCLK and LRCLK master */
- val = SUN4I_I2S_CTRL_MODE_MASTER;
- break;
- case SND_SOC_DAIFMT_CBM_CFM:
- /* BCLK and LRCLK slave */
- val = SUN4I_I2S_CTRL_MODE_SLAVE;
- break;
- default:
- dev_err(dai->dev, "Unsupported slave setting: %d\n",
- fmt & SND_SOC_DAIFMT_MASTER_MASK);
- return -EINVAL;
- }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
- SUN4I_I2S_CTRL_MODE_MASK,
- val);
- } else {
- /*
- * The newer i2s block does not have a slave select bit,
- * instead the clk pins are configured as inputs.
- */
- /* DAI clock master masks */
- switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- case SND_SOC_DAIFMT_CBS_CFS:
- /* BCLK and LRCLK master */
- val = SUN8I_I2S_CTRL_BCLK_OUT |
- SUN8I_I2S_CTRL_LRCK_OUT;
- break;
- case SND_SOC_DAIFMT_CBM_CFM:
- /* BCLK and LRCLK slave */
- val = 0;
- break;
- default:
- dev_err(dai->dev, "Unsupported slave setting: %d\n",
- fmt & SND_SOC_DAIFMT_MASTER_MASK);
- return -EINVAL;
- }
- regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
- SUN8I_I2S_CTRL_BCLK_OUT |
- SUN8I_I2S_CTRL_LRCK_OUT,
- val);
+ ret = i2s->variant->set_fmt(i2s, fmt);
+ if (ret) {
+ dev_err(dai->dev, "Unsupported format configuration\n");
+ return ret;
}
/* Set significant bits in our FIFOs */
@@ -934,11 +958,10 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
- .has_slave_select_bit = true,
- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
@@ -950,11 +973,10 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
- .has_slave_select_bit = true,
- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
@@ -966,11 +988,10 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
- .has_slave_select_bit = true,
- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun8i_i2s_set_chan_cfg,
+ .set_fmt = sun8i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
@@ -980,32 +1001,30 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.mclk_offset = 1,
.bclk_offset = 2,
.has_fmt_set_lrck_period = true,
- .has_chsel_offset = true,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
- .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun8i_i2s_set_chan_cfg,
+ .set_fmt = sun8i_i2s_set_soc_fmt,
};
static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
- .has_slave_select_bit = true,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
- .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
+ .set_fmt = sun4i_i2s_set_soc_fmt,
};
static int sun4i_i2s_init_regmap_fields(struct device *dev,
@@ -1041,12 +1060,6 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
if (IS_ERR(i2s->field_fmt_lrclk))
return PTR_ERR(i2s->field_fmt_lrclk);
- i2s->field_fmt_mode =
- devm_regmap_field_alloc(dev, i2s->regmap,
- i2s->variant->field_fmt_mode);
- if (IS_ERR(i2s->field_fmt_mode))
- return PTR_ERR(i2s->field_fmt_mode);
-
return 0;
}
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 06/21] ASoC: sun4i-i2s: Rework MCLK divider calculation
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The MCLK divider calculation is currently computing the ideal divider using
the oversample rate, the sample rate and the parent rate.
However, since we have access to the frequency is supposed to be running at
already, and as it turns out we're using it to compute the oversample rate,
we can just use the ratio between the parent rate and the MCLK rate to
simplify a bit the formula.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index fbbedb660cc6..3d7f4a97e0ba 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -225,11 +225,10 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
}
static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
- unsigned int oversample_rate,
- unsigned int module_rate,
- unsigned int sampling_rate)
+ unsigned long parent_rate,
+ unsigned long mclk_rate)
{
- int div = module_rate / sampling_rate / oversample_rate;
+ int div = parent_rate / mclk_rate;
int i;
for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
@@ -308,8 +307,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return -EINVAL;
}
- mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
- clk_rate, rate);
+ mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
if (mclk_div < 0) {
dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
return -EINVAL;
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 07/21] ASoC: sun4i-i2s: Don't use the oversample to calculate BCLK
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The BCLK divider should be calculated using the parameters that actually
make the BCLK rate: the number of channels, the sampling rate and the
sample width.
We've been using the oversample_rate previously because in the former SoCs,
the BCLK's parent is MCLK, which in turn is being used to generate the
oversample rate, so we end up with something like this:
oversample = mclk_rate / sampling_rate
bclk_div = oversample / word_size / channels
So, bclk_div = mclk_rate / sampling_rate / word_size / channels.
And this is actually better, since the oversampling ratio only plays a role
because the MCLK is its parent, not because of what BCLK is supposed to be.
Furthermore, that assumption of MCLK being the parent has been broken on
newer SoCs, so let's use the proper formula, and have the parent rate as an
argument.
Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3")
Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
Fixes: 66ecce332538 ("ASoC: sun4i-i2s: Add compatibility with A64 codec I2S")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 3d7f4a97e0ba..ee8ee3eb2087 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -208,10 +208,11 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
};
static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
- unsigned int oversample_rate,
+ unsigned long parent_rate,
+ unsigned int sampling_rate,
unsigned int word_size)
{
- int div = oversample_rate / word_size / 2;
+ int div = parent_rate / sampling_rate / word_size / 2;
int i;
for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
@@ -300,8 +301,8 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return -EINVAL;
}
- bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
- word_size);
+ bclk_div = sun4i_i2s_get_bclk_div(i2s, i2s->mclk_freq,
+ rate, word_size);
if (bclk_div < 0) {
dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
return -EINVAL;
--
git-series 0.9.1
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^ permalink raw reply related
* [PATCH 08/21] ASoC: sun4i-i2s: Use module clock as BCLK parent on newer SoCs
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
On the first generation of Allwinner SoCs (A10-A31), the i2s controller was
using the MCLK as BCLK parent. However, this changed since the introduction
of the A83t and BCLK now uses the module clock as its parent.
Let's introduce a hook to get the parent rate and use that in our divider
calculations.
Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3")
Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index ee8ee3eb2087..51be395102b2 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -152,6 +152,7 @@ struct sun4i_i2s_quirks {
struct reg_field field_fmt_bclk;
struct reg_field field_fmt_lrclk;
+ unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
int (*set_chan_cfg)(const struct sun4i_i2s *,
@@ -207,6 +208,16 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
/* TODO - extend divide ratio supported by newer SoCs */
};
+static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
+{
+ return i2s->mclk_freq;
+}
+
+static unsigned long sun8i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
+{
+ return clk_get_rate(i2s->mod_clk);
+}
+
static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
unsigned long parent_rate,
unsigned int sampling_rate,
@@ -259,7 +270,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
unsigned int word_size)
{
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
- unsigned int oversample_rate, clk_rate;
+ unsigned int oversample_rate, clk_rate, bclk_parent_rate;
int bclk_div, mclk_div;
int ret;
@@ -301,7 +312,8 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return -EINVAL;
}
- bclk_div = sun4i_i2s_get_bclk_div(i2s, i2s->mclk_freq,
+ bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s);
+ bclk_div = sun4i_i2s_get_bclk_div(i2s, bclk_parent_rate,
rate, word_size);
if (bclk_div < 0) {
dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
@@ -957,6 +969,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
@@ -972,6 +985,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
@@ -987,6 +1001,7 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun8i_i2s_set_chan_cfg,
@@ -1005,6 +1020,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
+ .get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
.set_chan_cfg = sun8i_i2s_set_chan_cfg,
@@ -1020,6 +1036,7 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
.set_chan_cfg = sun4i_i2s_set_chan_cfg,
--
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* [PATCH 09/21] ASoC: sun4i-i2s: Fix the MCLK and BCLK dividers on newer SoCs
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
From: Marcus Cooper <codekipper@gmail.com>
The clock division dividers have changed between the older (A10/A31) and
newer (H3, A64, etc) SoCs.
While this was addressed through an offset on some SoCs, it was missing
some dividers as well, so the support wasn't perfect. Let's introduce a
pointer in the quirk structure for the divider calculation functions to use
so we can have the proper range now.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
[Maxime: Fix the commit log, use a field in the quirk structure]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 63 +++++++++++++++++++++++++++++---------
1 file changed, 49 insertions(+), 14 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 51be395102b2..8d49ee7d2a95 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -129,8 +129,6 @@ struct sun4i_i2s;
* @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
* @reg_offset_txdata: offset of the tx fifo.
* @sun4i_i2s_regmap: regmap config to use.
- * @mclk_offset: Value by which mclkdiv needs to be adjusted.
- * @bclk_offset: Value by which bclkdiv needs to be adjusted.
* @field_clkdiv_mclk_en: regmap field to enable mclk output.
* @field_fmt_wss: regmap field to set word select size.
* @field_fmt_sr: regmap field to set sample resolution.
@@ -142,8 +140,6 @@ struct sun4i_i2s_quirks {
bool has_fmt_set_lrck_period;
unsigned int reg_offset_txdata; /* TX FIFO */
const struct regmap_config *sun4i_i2s_regmap;
- unsigned int mclk_offset;
- unsigned int bclk_offset;
/* Register fields for i2s */
struct reg_field field_clkdiv_mclk_en;
@@ -152,6 +148,11 @@ struct sun4i_i2s_quirks {
struct reg_field field_fmt_bclk;
struct reg_field field_fmt_lrclk;
+ const struct sun4i_i2s_clk_div *bclk_dividers;
+ unsigned int num_bclk_dividers;
+ const struct sun4i_i2s_clk_div *mclk_dividers;
+ unsigned int num_mclk_dividers;
+
unsigned long (*get_bclk_parent_rate)(const struct sun4i_i2s *);
s8 (*get_sr)(const struct sun4i_i2s *, int);
s8 (*get_wss)(const struct sun4i_i2s *, int);
@@ -208,6 +209,24 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
/* TODO - extend divide ratio supported by newer SoCs */
};
+static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = {
+ { .div = 1, .val = 1 },
+ { .div = 2, .val = 2 },
+ { .div = 4, .val = 3 },
+ { .div = 6, .val = 4 },
+ { .div = 8, .val = 5 },
+ { .div = 12, .val = 6 },
+ { .div = 16, .val = 7 },
+ { .div = 24, .val = 8 },
+ { .div = 32, .val = 9 },
+ { .div = 48, .val = 10 },
+ { .div = 64, .val = 11 },
+ { .div = 96, .val = 12 },
+ { .div = 128, .val = 13 },
+ { .div = 176, .val = 14 },
+ { .div = 192, .val = 15 },
+};
+
static unsigned long sun4i_i2s_get_bclk_parent_rate(const struct sun4i_i2s *i2s)
{
return i2s->mclk_freq;
@@ -223,11 +242,12 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
unsigned int sampling_rate,
unsigned int word_size)
{
+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;
int div = parent_rate / sampling_rate / word_size / 2;
int i;
- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
- const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
+ for (i = 0; i < i2s->variant->num_bclk_dividers; i++) {
+ const struct sun4i_i2s_clk_div *bdiv = ÷rs[i];
if (bdiv->div == div)
return bdiv->val;
@@ -240,11 +260,12 @@ static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
unsigned long parent_rate,
unsigned long mclk_rate)
{
+ const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;
int div = parent_rate / mclk_rate;
int i;
- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
- const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
+ for (i = 0; i < i2s->variant->num_mclk_dividers; i++) {
+ const struct sun4i_i2s_clk_div *mdiv = ÷rs[i];
if (mdiv->div == div)
return mdiv->val;
@@ -326,10 +347,6 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
return -EINVAL;
}
- /* Adjust the clock division values if needed */
- bclk_div += i2s->variant->bclk_offset;
- mclk_div += i2s->variant->mclk_offset;
-
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
@@ -969,6 +986,10 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
@@ -985,6 +1006,10 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
@@ -1001,6 +1026,10 @@ static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .bclk_dividers = sun8i_i2s_clk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .mclk_dividers = sun8i_i2s_clk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
@@ -1012,14 +1041,16 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
.has_reset = true,
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
- .mclk_offset = 1,
- .bclk_offset = 2,
.has_fmt_set_lrck_period = true,
.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
+ .bclk_dividers = sun8i_i2s_clk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
+ .mclk_dividers = sun8i_i2s_clk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
.get_sr = sun8i_i2s_get_sr_wss,
.get_wss = sun8i_i2s_get_sr_wss,
@@ -1036,6 +1067,10 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+ .bclk_dividers = sun4i_i2s_bclk_div,
+ .num_bclk_dividers = ARRAY_SIZE(sun4i_i2s_bclk_div),
+ .mclk_dividers = sun4i_i2s_mclk_div,
+ .num_mclk_dividers = ARRAY_SIZE(sun4i_i2s_mclk_div),
.get_bclk_parent_rate = sun4i_i2s_get_bclk_parent_rate,
.get_sr = sun4i_i2s_get_sr,
.get_wss = sun4i_i2s_get_wss,
--
git-series 0.9.1
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* [PATCH 10/21] ASoC: sun4i-i2s: RX and TX counter registers are swapped
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The RX and TX counters registers offset have been swapped, fix that.
Fixes: fa7c0d13cb26 ("ASoC: sunxi: Add Allwinner A10 Digital Audio driver")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 8d49ee7d2a95..08fc04ad3585 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -76,8 +76,8 @@
#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
-#define SUN4I_I2S_RX_CNT_REG 0x28
-#define SUN4I_I2S_TX_CNT_REG 0x2c
+#define SUN4I_I2S_TX_CNT_REG 0x28
+#define SUN4I_I2S_RX_CNT_REG 0x2c
#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
#define SUN4I_I2S_CHAN_SEL_MASK GENMASK(2, 0)
--
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* [PATCH 11/21] ASoC: sun4i-i2s: Use the actual format width instead of an hardcoded one
From: Maxime Ripard @ 2019-08-19 19:25 UTC (permalink / raw)
To: Chen-Yu Tsai, Maxime Ripard, lgirdwood, broonie
Cc: codekipper, alsa-devel, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.e08aa7e33afe117e1fa8f017119d465d47c98016.1566242458.git-series.maxime.ripard@bootlin.com>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The LRCK period field in the FMT0 register holds the number of LRCK period
for one channel in I2S mode.
This has been hardcoded to 32, while it really should be the physical width
of the format, which creates an improper clock when using a 16bit format,
with the i2s controller as LRCK master.
Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
sound/soc/sunxi/sun4i-i2s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 08fc04ad3585..2996beb4f092 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -357,7 +357,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
if (i2s->variant->has_fmt_set_lrck_period)
regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
- SUN8I_I2S_FMT0_LRCK_PERIOD(32));
+ SUN8I_I2S_FMT0_LRCK_PERIOD(params_physical_width(params)));
return 0;
}
--
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