Linux-ARM-Kernel Archive on lore.kernel.org

* Re: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Leonard Crestez @ 2019-08-21 20:39 UTC (permalink / raw)
  To: Daniel Baluta, shawnguo@kernel.org, Abel Vesa
  Cc: devicetree@vger.kernel.org, baruch@tkos.co.il, Jacky Bai,
	Anson Huang, ccaione@baylibre.com, andrew.smirnov@gmail.com,
	s.hauer@pengutronix.de, angus@akkea.ca, Stephen Boyd,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	agx@sigxcpu.org, dl-linux-imx, Peng Fan, festevam@gmail.com,
	S.j. Wang, linux-arm-kernel@lists.infradead.org,
	l.stach@pengutronix.de
In-Reply-To: <20190728152040.15323-1-daniel.baluta@nxp.com>

On 28.07.2019 18:20, Daniel Baluta wrote:
> From: Abel Vesa <abel.vesa@nxp.com>
> 
> Add the initial configuration for clocks that need default parent and rate
> setting. This is based on the vendor tree clock provider parents and rates
> configuration except this is doing the setup in dts rather then using clock
> consumer API in a clock provider driver.
> 
> Note that by adding the initial rate setting for audio_pll1/audio_pll
> setting we need to remove it from imx8mq-librem5-devkit.dts

Setting default rates for audio_pll1 and audio_pll2 in soc dtsi makes a 
lot of sense to me; the intention is for one to run at a multiple of 
44.1k and another at a multiple of 48k.

> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 02fbd0625318..a55d72ba2e05 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -494,6 +494,25 @@
>   				clock-names = "ckil", "osc_25m", "osc_27m",
>   				              "clk_ext1", "clk_ext2",
>   				              "clk_ext3", "clk_ext4";
> +				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> +					<&clk IMX8MQ_AUDIO_PLL1>,
> +					<&clk IMX8MQ_AUDIO_PLL2>,
> +					<&clk IMX8MQ_CLK_AHB>,
> +					<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> +					<&clk IMX8MQ_CLK_AUDIO_AHB>,
> +					<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> +					<&clk IMX8MQ_CLK_NOC>;
> +				assigned-clock-parents = <0>,
> +						<0>,
> +						<0> > +						<&clk IMX8MQ_SYS1_PLL_133M>,
> +						<&clk IMX8MQ_SYS1_PLL_266M>,
> +						<&clk IMX8MQ_SYS2_PLL_500M>,
> +						<&clk IMX8MQ_CLK_27M>,
> +						<&clk IMX8MQ_SYS1_PLL_800M>;
> +				assigned-clock-rates = <593999999>,
> +						<786432000>,
> +						<722534400>;

The audio PLLs should run below 650 mHz so please use 393216000 and 
361267200 instead of 786432000 and 722534400. For the 8mm equivalent see 
commit 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting").

You should also move the unbypassing of AUDIO_PLL1 and AUDIO_PLL2 here 
just add two more assigned-clocks and assigned-clock-parents.

--
Regards,
Leonard

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