* Re: [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Alexander Amelkin @ 2019-08-22 14:36 UTC (permalink / raw)
To: Guenter Roeck
Cc: linux-watchdog, linux-aspeed, Andrew Jeffery, linux-kernel,
Joel Stanley, Ivan Mikhaylov, Wim Van Sebroeck, linux-arm-kernel
In-Reply-To: <20190821181008.GB15127@roeck-us.net>
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21.08.2019 21:10, Guenter Roeck wrote:
> On Wed, Aug 21, 2019 at 08:42:24PM +0300, Alexander Amelkin wrote:
>> 21.08.2019 19:32, Guenter Roeck wrote:
>>> On Wed, Aug 21, 2019 at 06:57:43PM +0300, Ivan Mikhaylov wrote:
>>>> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
>>>> to clear out boot code source and re-enable access to the primary SPI flash
>>>> chip while booted via wdt2 from the alternate chip.
>>>>
>>>> AST2400 datasheet says:
>>>> "In the 2nd flash booting mode, all the address mapping to CS0# would be
>>>> re-directed to CS1#. And CS0# is not accessable under this mode. To access
>>>> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
>>>> register WDT30.bit[1]."
>>> Is there reason to not do this automatically when loading the module
>>> in alt-boot mode ? What means does userspace have to determine if CS0
>>> or CS1 is active at any given time ? If there is reason to ever have CS1
>>> active instead of CS0, what means would userspace have to enable it ?
>> Yes, there is. The driver is loaded long before the filesystems are mounted.
>> The filesystems, in the event of alternate/recovery boot, need to be mounted
>> from the same chip that the kernel was booted. For one reason because the main
>> chip at CS0 is most probably corrupt. If you clear that bit when driver is
>> loaded, your software will not know that and will try to mount the wrong
>> filesystems. The whole idea of ASPEED's switching chipselects is to have
>> identical firmware in both chips, without the need to process the alternate
>> boot state in any way except for indicating a successful boot and restoring
>> access to CS0 when needed.
>>
>> The userspace can read bootstatus sysfs node to determine if an alternate
>> boot has occured.
>>
>> With ASPEED, CS1 is activated automatically by wdt2 when system fails to boot
>> from the primary flash chip (at CS0) and disable the watchdog to indicate a
>> successful boot. When that happens, both CS0 and CS1 controls get routed in
>> hardware to CS1 line, making the primary flash chip inaccessible. Depending
>> on the architecture of the user-space software, it may choose to re-enable
>> access to the primary chip via CS0 at different times. There must be a way to do so.
>>
> So by activating cs0, userspace would essentially pull its own root file system
> from underneath itself ?
Exactly. That's why for alternate boot the firmware would usually copy
all filesystems to memory and mount from there. Some embedded systems
do that always, regardless of which chip they boot from.
However, to be able to recover the main flash chip, the system needs CS0
to function as such (not as CS1). That's why this control is needed.
As Ivan mentioned, for AST2500 and the upcoming AST2600 the behavior
is slightly different. They don't just connect both CS controls to CS1 but instead
swap them so the primary chip becomes secondary from the software point
of view. The means to restore the normal wiring may still be needed.
>
>> This code most probably adds nothing at the assembly level.
>>
> That seems quite unlikely. Please demonstrate.
Yes, you were right. It adds 7 instructions. We'll drop the check.
It's just my DO-178 background, I add 'robustness' checks everywhere.
>>>> + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
>>>> + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
>>>> + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
>>> The variable reflects the _boot status_. It should not change after booting.
>> Is there any documentation that dictates that? All I could find is
>>
>> "bootstatus: status of the device after booting". That doesn't look to me like it absolutely can not change to reflect the updated status (that is, to reflect that the originally set up alternate CS routing has been reset to normal).
>>
> You choose to interpret "after booting" in a kind of novel way,
> which I find a bit disturbing. I am not really sure how else to
> describe "boot status" in a way that does not permit such
> reinterpratation of the term.
How about "Reflects reasons that caused a reboot, remains constant until the next boot" ?
> On top of that, how specifically would "WDIOF_EXTERN1" reflect
> what you claim it does ? Not only you are hijacking bootstatus9
> (which is supposed to describe the reason for a reboot), you
> are also hijacking WDIOF_EXTERN1. That seems highly arbitrary
> to me, and is not really how an API/ABI should be used.
We used WDIOF_EXTERN1 because:
1. We thought that bootstatus _can_ change
2. We thought that adding extra bits wouldn't be appreciated
Now as you clarified that assumption 1 was wrong we are going to implement status as I proposed earlier:
>
>> I think we could make 'access_cs0' readable instead, so it could report the
>> current state of the boot code selection bit. Reverted, I suppose. That
>> way 'access_cs0' would report 1 after 1 has been written to it (it wouldn't
>> be possible to write a zero).
With best regards,
Alexander Amelkin,
BIOS/BMC Team Lead, YADRO
https://yadro.com
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* Re: [PATCH -next] ASoC: sun4i-i2s: Use PTR_ERR_OR_ZERO in sun4i_i2s_init_regmap_fields()
From: Yuehaibing @ 2019-08-22 14:34 UTC (permalink / raw)
To: Maxime Ripard
Cc: alsa-devel, linux-kernel, kernel-janitors, Takashi Iwai,
Liam Girdwood, Marcus Cooper, Chen-Yu Tsai, Mark Brown,
Jaroslav Kysela, linux-arm-kernel
In-Reply-To: <20190822141826.is6nizjpdgvhd7ra@flea>
On 2019/8/22 22:18, Maxime Ripard wrote:
> Hi,
>
> On Thu, Aug 22, 2019 at 06:52:52AM +0000, YueHaibing wrote:
>> Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
>>
>> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
>> ---
>> sound/soc/sunxi/sun4i-i2s.c | 5 +----
>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
>> index 9e691baee1e8..2071c54265f3 100644
>> --- a/sound/soc/sunxi/sun4i-i2s.c
>> +++ b/sound/soc/sunxi/sun4i-i2s.c
>> @@ -1095,10 +1095,7 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
>> i2s->field_fmt_sr =
>> devm_regmap_field_alloc(dev, i2s->regmap,
>> i2s->variant->field_fmt_sr);
>> - if (IS_ERR(i2s->field_fmt_sr))
>> - return PTR_ERR(i2s->field_fmt_sr);
>> -
>> - return 0;
>> + return PTR_ERR_OR_ZERO(i2s->field_fmt_sr);
>
> I'm not really convinced that this more readable or more maintainable
> though. Is there a reason for this other than we can do it?
No special reason, just suggested by scripts/coccinelle/api/ptr_ret.cocci
>
> Maxie
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
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* Re: [PATCH 1/2] Include mt8183-reset.h and add reset-cells in infracfg in dtsi file.
From: Matthias Brugger @ 2019-08-22 14:34 UTC (permalink / raw)
To: Yong Liang, mturquette, sboyd, robh+dt, mark.rutland, drinkcat,
weiyi.lu, jamesjj.liao, jasu, owen.chen, chunhui.dai, erin.lo,
eddie.huang
Cc: linux-mediatek, linux-clk, linux-arm-kernel
In-Reply-To: <20190725080957.17333-1-yong.liang@mediatek.com>
On 25/07/2019 10:09, Yong Liang wrote:
> From: "yong.liang" <yong.liang@mediatek.com>
>
> Change-Id: I46e0aca76a206ac86ee0477d9dbd67e1e924b118
> Signed-off-by: yong.liang <yong.liang@mediatek.com>
> ---
Somehow I only have patch 1 of the series in my inbox.
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 08274bfcebd8..2589e9461c6e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/mt8183-clk.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset-controller/mt8183-resets.h>
>
> / {
> compatible = "mediatek,mt8183";
> @@ -194,6 +195,7 @@
> compatible = "mediatek,mt8183-infracfg", "syscon";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
> };
>
> apmixedsys: syscon@1000c000 {
>
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* Re: [PATCH 1/2] Include mt8183-reset.h and add reset-cells in infracfg in dtsi file.
From: Matthias Brugger @ 2019-08-22 14:33 UTC (permalink / raw)
To: Yong Liang, mturquette, sboyd, robh+dt, mark.rutland, drinkcat,
weiyi.lu, jamesjj.liao, jasu, owen.chen, chunhui.dai, erin.lo,
eddie.huang
Cc: linux-mediatek, linux-clk, linux-arm-kernel
In-Reply-To: <20190725080957.17333-1-yong.liang@mediatek.com>
On 25/07/2019 10:09, Yong Liang wrote:
> From: "yong.liang" <yong.liang@mediatek.com>
>
Missing commit message.
Subject could be shorter, something like:
arm64: dts: add reset-cells for infracfg
> Change-Id: I46e0aca76a206ac86ee0477d9dbd67e1e924b118
Please delete Change-Id it's not meaning full for upstream work.
> Signed-off-by: yong.liang <yong.liang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 08274bfcebd8..2589e9461c6e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/mt8183-clk.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset-controller/mt8183-resets.h>
>
> / {
> compatible = "mediatek,mt8183";
> @@ -194,6 +195,7 @@
> compatible = "mediatek,mt8183-infracfg", "syscon";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
> };
>
> apmixedsys: syscon@1000c000 {
>
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* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
From: Robin Murphy @ 2019-08-22 14:30 UTC (permalink / raw)
To: Will Deacon, Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20190820120848.2m6gytilrpil4stu@willie-the-truck>
On 20/08/2019 13:08, Will Deacon wrote:
> Hi Gregory, Hanna,
>
> On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
>> From: Hanna Hawa <hannah@marvell.com>
>>
>> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
>> helpers, as preparation to add specific Marvell work-around for
>> accessing 64 bits width registers of ARM SMMU.
>>
>> Signed-off-by: Hanna Hawa <hannah@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> Sorry for the delay in replying to this -- Robin's been reworking the driver
> so that implementation quirks can be specified more cleanly. Please can you
> take a look at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
>
> and try to respin your patches on top of that?
Right, the arm_smmu_impl design was specifically anticipating this quirk
as well - it should just be a case of a cfg_probe hook to hide the
features which can't work, plus {read,write}_reg64 hooks to override any
remaining 64-bit accesses with the explicit hi_lo_* variants, munged
together (either statically or dynamically) with the standard MMU-500 hooks.
Robin.
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* Re: [PATCH net-next v2 1/3] net: ethernet: mediatek: Add basic PHYLINK support
From: Russell King - ARM Linux admin @ 2019-08-22 14:27 UTC (permalink / raw)
To: René van Dorst
Cc: Nelson Chang, Frank Wunderlich, netdev, Sean Wang, linux-mips,
linux-mediatek, John Crispin, Matthias Brugger, Stefan Roese,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190821144336.9259-2-opensource@vdorst.com>
On Wed, Aug 21, 2019 at 04:43:34PM +0200, René van Dorst wrote:
> +static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
> + phy_interface_t interface)
> +{
> + struct mtk_mac *mac = container_of(config, struct mtk_mac,
> + phylink_config);
>
> - return 0;
> + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
> }
You set the MAC_MCR_FORCE_MODE bit here...
> +static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode,
> + phy_interface_t interface,
> + struct phy_device *phy)
> {
> + struct mtk_mac *mac = container_of(config, struct mtk_mac,
> + phylink_config);
> + u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
>
> + mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
> + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
> +}
Looking at this, a link_down() followed by a link_up() would result in
this register containing MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
MAC_MCR_RX_EN ? Is that actually correct? (MAC_MCR_FORCE_LINK isn't
set, so it looks to me like it still forces the link down.)
Note that link up/down forcing should not be done for in-band AN.
> +static void mtk_validate(struct phylink_config *config,
> + unsigned long *supported,
> + struct phylink_link_state *state)
> +{
> + struct mtk_mac *mac = container_of(config, struct mtk_mac,
> + phylink_config);
> + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>
> + if (state->interface != PHY_INTERFACE_MODE_NA &&
> + state->interface != PHY_INTERFACE_MODE_MII &&
> + state->interface != PHY_INTERFACE_MODE_GMII &&
> + !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
> + phy_interface_mode_is_rgmii(state->interface)) &&
> + !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
> + !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII)) {
> + linkmode_zero(supported);
> + return;
> }
>
> + phylink_set_port_modes(mask);
> + phylink_set(mask, Autoneg);
>
> + if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
> + phylink_set(mask, 1000baseT_Full);
> + } else {
> + phylink_set(mask, 10baseT_Half);
> + phylink_set(mask, 10baseT_Full);
> + phylink_set(mask, 100baseT_Half);
> + phylink_set(mask, 100baseT_Full);
> +
> + if (state->interface != PHY_INTERFACE_MODE_MII) {
> + phylink_set(mask, 1000baseT_Half);
> + phylink_set(mask, 1000baseT_Full);
> + phylink_set(mask, 1000baseX_Full);
> + }
> + }
>
> + phylink_set(mask, Pause);
> + phylink_set(mask, Asym_Pause);
>
> + linkmode_and(supported, supported, mask);
> + linkmode_and(state->advertising, state->advertising, mask);
> }
This looks fine.
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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* [PATCH 6/6] arm64: dts: meson-sm1-sei610: enable DVFS
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
This enables DVFS for the Amlogic SM1 based SEI610 board by:
- Adding the SM1 SoC OPPs taken from the vendor tree
- Selecting the SM1 Clock controller instead of the G12A one
- Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.
Each power supply can achieve 0.69V to 1.05V using a single PWM
output clocked at 666KHz with an inverse duty-cycle.
DVFS has been tested by running the arm64 cpuburn at [1] and cycling
between all the possible cpufreq translations of each cluster and
checking the final frequency using the clock-measurer, script at [2].
[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../boot/dts/amlogic/meson-sm1-sei610.dts | 59 ++++++++++++++--
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++++++++++++++++++
2 files changed, 124 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
index 36ac2e4b970d..69966e2e0611 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
@@ -19,10 +19,6 @@
ethernet0 = ðmac;
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
@@ -136,6 +132,25 @@
regulator-always-on;
};
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vddio_ao1v8: regulator-vddio_ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
@@ -182,6 +197,34 @@
hdmi-phandle = <&hdmi_tx>;
};
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
ðmac {
status = "okay";
phy-handle = <&internal_ephy>;
@@ -220,6 +263,14 @@
clock-names = "clkin0";
};
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 37064d7f66c1..2b61406b0610 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -50,6 +50,71 @@
compatible = "cache";
};
};
+
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <730000>;
+ };
+
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <730000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <730000>;
+ };
+
+ opp-667000000 {
+ opp-hz = /bits/ 64 <666666666>;
+ opp-microvolt = <750000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <770000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <780000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <790000>;
+ };
+
+ opp-1512000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <800000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <810000>;
+ };
+
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <900000>;
+ };
+
+ opp-1908000000 {
+ opp-hz = /bits/ 64 <1908000000>;
+ opp-microvolt = <950000>;
+ };
+ };
};
&cecb_AO {
@@ -60,6 +125,10 @@
compatible = "amlogic,meson-sm1-clk-measure";
};
+&clkc {
+ compatible = "amlogic,sm1-clkc";
+};
+
ðmac {
power-domains = <&pwrc PWRC_SM1_ETH_ID>;
};
--
2.22.0
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^ permalink raw reply related
* [PATCH 4/6] clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.
But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.
They are set read-only because the early boot stages sets them to select
the CPU0 input clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 60 ++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 5 +++-
2 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index e00df17f800a..ea4c791f106d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -824,6 +824,60 @@ static struct clk_regmap sm1_dsu_final_clk = {
},
};
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
+static struct clk_regmap sm1_cpu1_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu1_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
+static struct clk_regmap sm1_cpu2_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu2_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
+static struct clk_regmap sm1_cpu3_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu3_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
static struct clk_regmap sm1_dsu_clk = {
.data = &(struct clk_regmap_mux_data){
@@ -4576,6 +4630,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
[CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
[CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
+ [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
+ [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
+ [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -4807,6 +4864,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&sm1_dsu_clk_dyn,
&sm1_dsu_final_clk,
&sm1_dsu_clk,
+ &sm1_cpu1_clk,
+ &sm1_cpu2_clk,
+ &sm1_cpu3_clk,
};
static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 66fd46940f91..4682a4442ae9 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -257,8 +257,11 @@
#define CLKID_DSU_CLK_DYN 250
#define CLKID_DSU_CLK_FINAL 251
#define CLKID_DSU_CLK 252
+#define CLKID_CPU1_CLK 253
+#define CLKID_CPU2_CLK 254
+#define CLKID_CPU3_CLK 255
-#define NR_CLKS 253
+#define NR_CLKS 256
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
--
2.22.0
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^ permalink raw reply related
* [PATCH 5/6] clk: meson: g12a: expose SM1 CPU 1, 2 & 3 clocks
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet, devicetree
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
Expose the newly added CPU1, CPU2 and CPU3 clocks bindings for the Amlogic
SM1 SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.h | 3 ---
include/dt-bindings/clock/g12a-clkc.h | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 4682a4442ae9..9c1dc6ade3d6 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -257,9 +257,6 @@
#define CLKID_DSU_CLK_DYN 250
#define CLKID_DSU_CLK_FINAL 251
#define CLKID_DSU_CLK 252
-#define CLKID_CPU1_CLK 253
-#define CLKID_CPU2_CLK 254
-#define CLKID_CPU3_CLK 255
#define NR_CLKS 256
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 8ccc29ac7a72..3cfefaf43315 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -138,5 +138,8 @@
#define CLKID_VDEC_HEVCF 210
#define CLKID_TS 212
#define CLKID_CPUB_CLK 224
+#define CLKID_CPU1_CLK 253
+#define CLKID_CPU2_CLK 254
+#define CLKID_CPU3_CLK 255
#endif /* __G12A_CLKC_H */
--
2.22.0
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^ permalink raw reply related
* [PATCH 3/6] clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the
CPU clock tree with a supplementaty mux to select the CPU0 clock instead.
Leave this as read-only since it's set up by the early boot stages.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 184 +++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 16 +++-
2 files changed, 199 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 34dfac4b4dc6..e00df17f800a 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -676,6 +676,172 @@ static struct clk_regmap g12b_cpub_clk = {
},
};
+static struct clk_regmap sm1_gp1_pll;
+
+/* Datasheet names this field as "premux0" */
+static struct clk_regmap sm1_dsu_clk_premux0 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x3,
+ .shift = 0,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn0_sel",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &g12a_fclk_div2.hw },
+ { .hw = &g12a_fclk_div3.hw },
+ { .hw = &sm1_gp1_pll.hw },
+ },
+ .num_parents = 4,
+ },
+};
+
+/* Datasheet names this field as "premux1" */
+static struct clk_regmap sm1_dsu_clk_premux1 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x3,
+ .shift = 16,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn1_sel",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &g12a_fclk_div2.hw },
+ { .hw = &g12a_fclk_div3.hw },
+ { .hw = &sm1_gp1_pll.hw },
+ },
+ .num_parents = 4,
+ },
+};
+
+/* Datasheet names this field as "Mux0_divn_tcnt" */
+static struct clk_regmap sm1_dsu_clk_mux0_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .shift = 4,
+ .width = 6,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn0_div",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_premux0.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "postmux0" */
+static struct clk_regmap sm1_dsu_clk_postmux0 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 2,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn0",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_premux0.hw,
+ &sm1_dsu_clk_mux0_div.hw,
+ },
+ .num_parents = 2,
+ },
+};
+
+/* Datasheet names this field as "Mux1_divn_tcnt" */
+static struct clk_regmap sm1_dsu_clk_mux1_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .shift = 20,
+ .width = 6,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn1_div",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_premux1.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "postmux1" */
+static struct clk_regmap sm1_dsu_clk_postmux1 = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 18,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn1",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_premux1.hw,
+ &sm1_dsu_clk_mux1_div.hw,
+ },
+ .num_parents = 2,
+ },
+};
+
+/* Datasheet names this field as "Final_dyn_mux_sel" */
+static struct clk_regmap sm1_dsu_clk_dyn = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 10,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_dyn",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_postmux0.hw,
+ &sm1_dsu_clk_postmux1.hw,
+ },
+ .num_parents = 2,
+ },
+};
+
+/* Datasheet names this field as "Final_mux_sel" */
+static struct clk_regmap sm1_dsu_final_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL5,
+ .mask = 0x1,
+ .shift = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk_final",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_dsu_clk_dyn.hw,
+ &g12a_sys_pll.hw,
+ },
+ .num_parents = 2,
+ },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
+static struct clk_regmap sm1_dsu_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 27,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "dsu_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ &sm1_dsu_final_clk.hw,
+ },
+ .num_parents = 2,
+ },
+};
+
static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
@@ -4401,6 +4567,15 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_TS] = &g12a_ts.hw,
[CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
[CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
+ [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
+ [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
+ [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
+ [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
+ [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
+ [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
+ [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
+ [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
+ [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -4623,6 +4798,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12b_cpub_clk_trace,
&sm1_gp1_pll_dco,
&sm1_gp1_pll,
+ &sm1_dsu_clk_premux0,
+ &sm1_dsu_clk_premux1,
+ &sm1_dsu_clk_mux0_div,
+ &sm1_dsu_clk_postmux0,
+ &sm1_dsu_clk_mux1_div,
+ &sm1_dsu_clk_postmux1,
+ &sm1_dsu_clk_dyn,
+ &sm1_dsu_final_clk,
+ &sm1_dsu_clk,
};
static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 4b3d22245609..66fd46940f91 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -80,6 +80,11 @@
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20C
+#define HHI_SYS_CPU_CLK_CNTL2 0x210
+#define HHI_SYS_CPU_CLK_CNTL3 0x214
+#define HHI_SYS_CPU_CLK_CNTL4 0x218
+#define HHI_SYS_CPU_CLK_CNTL5 0x21c
+#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
@@ -243,8 +248,17 @@
#define CLKID_CPUB_CLK_TRACE 241
#define CLKID_GP1_PLL_DCO 242
#define CLKID_GP1_PLL 243
+#define CLKID_DSU_CLK_DYN0_SEL 244
+#define CLKID_DSU_CLK_DYN0_DIV 245
+#define CLKID_DSU_CLK_DYN0 246
+#define CLKID_DSU_CLK_DYN1_SEL 247
+#define CLKID_DSU_CLK_DYN1_DIV 248
+#define CLKID_DSU_CLK_DYN1 249
+#define CLKID_DSU_CLK_DYN 250
+#define CLKID_DSU_CLK_FINAL 251
+#define CLKID_DSU_CLK 252
-#define NR_CLKS 242
+#define NR_CLKS 253
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
--
2.22.0
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^ permalink raw reply related
* [PATCH 2/6] clk: meson: g12a: add support for SM1 GP1 PLL
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.
This also adds a dedicated set of clock and compatible for SM1.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 300 +++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 10 ++
2 files changed, 310 insertions(+)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index c3f0ffc3280d..34dfac4b4dc6 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -1443,6 +1443,69 @@ static struct clk_regmap g12a_gp0_pll = {
},
};
+static struct clk_regmap sm1_gp1_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_GP1_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = HHI_GP1_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = HHI_GP1_PLL_CNTL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = HHI_GP1_PLL_CNTL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = HHI_GP1_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = HHI_GP1_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp1_pll_dco",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ /* This clock feeds the DSU, avoid disabling it */
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_regmap sm1_gp1_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_GP1_PLL_CNTL0,
+ .shift = 16,
+ .width = 3,
+ .flags = (CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_ROUND_CLOSEST),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp1_pll",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &sm1_gp1_pll_dco.hw
+ },
+ .num_parents = 1,
+ },
+};
+
/*
* Internal hifi pll emulation configuration parameters
*/
@@ -4121,6 +4184,228 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
.num = NR_CLKS,
};
+static struct clk_hw_onecell_data sm1_hw_onecell_data = {
+ .hws = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
+ [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
+ [NR_CLKS] = NULL,
+ },
+ .num = NR_CLKS,
+};
+
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_clk81,
@@ -4336,6 +4621,8 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12b_cpub_clk_axi,
&g12b_cpub_clk_trace_sel,
&g12b_cpub_clk_trace,
+ &sm1_gp1_pll_dco,
+ &sm1_gp1_pll,
};
static const struct reg_sequence g12a_init_regs[] = {
@@ -4532,6 +4819,15 @@ static const struct meson_g12a_data g12b_clkc_data = {
.dvfs_setup = meson_g12b_dvfs_setup,
};
+static const struct meson_g12a_data sm1_clkc_data = {
+ .eeclkc_data = {
+ .regmap_clks = g12a_clk_regmaps,
+ .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
+ .hw_onecell_data = &sm1_hw_onecell_data,
+ },
+ .dvfs_setup = meson_g12a_dvfs_setup,
+};
+
static const struct of_device_id clkc_match_table[] = {
{
.compatible = "amlogic,g12a-clkc",
@@ -4541,6 +4837,10 @@ static const struct of_device_id clkc_match_table[] = {
.compatible = "amlogic,g12b-clkc",
.data = &g12b_clkc_data.eeclkc_data
},
+ {
+ .compatible = "amlogic,sm1-clkc",
+ .data = &sm1_clkc_data.eeclkc_data
+ },
{}
};
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 559a34cfdfeb..4b3d22245609 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -29,6 +29,14 @@
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05C
+#define HHI_GP1_PLL_CNTL0 0x060
+#define HHI_GP1_PLL_CNTL1 0x064
+#define HHI_GP1_PLL_CNTL2 0x068
+#define HHI_GP1_PLL_CNTL3 0x06C
+#define HHI_GP1_PLL_CNTL4 0x070
+#define HHI_GP1_PLL_CNTL5 0x074
+#define HHI_GP1_PLL_CNTL6 0x078
+#define HHI_GP1_PLL_STS 0x07C
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09C
#define HHI_PCIE_PLL_CNTL2 0x0A0
@@ -233,6 +241,8 @@
#define CLKID_CPUB_CLK_AXI 239
#define CLKID_CPUB_CLK_TRACE_SEL 240
#define CLKID_CPUB_CLK_TRACE 241
+#define CLKID_GP1_PLL_DCO 242
+#define CLKID_GP1_PLL 243
#define NR_CLKS 242
--
2.22.0
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^ permalink raw reply related
* [PATCH 1/6] dt-bindings: clk: meson: add sm1 periph clock controller bindings
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet, devicetree
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-1-narmstrong@baylibre.com>
Update the documentation to support clock driver for the Amlogic SM1 SoC.
SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 6eaa52092313..7ccecd5c02c1 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -11,6 +11,7 @@ Required Properties:
"amlogic,axg-clkc" for AXG SoC.
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
+ "amlogic,sm1-clkc" for SM1 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
--
2.22.0
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^ permalink raw reply related
* [PATCH 0/6] arm64: meson-sm1: add support for DVFS
From: Neil Armstrong @ 2019-08-22 14:24 UTC (permalink / raw)
To: khilman, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
enables DVFS on the SM1 SoC for the SEI610 board.
The SM1 Clock structure is slightly different because of the Cortex-A55
core used, having the capability for each core of a same cluster to run
at a different frequency thanks to the newly used DynamIQ Shared Unit.
This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit,
with a bypass mux to use the CPU0 instead of the dedicated trees.
The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only.
The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike
G12A only a single version of the SoC is available.
Dependencies:
- patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie,
but is not a strong dependency, it will work without
Neil Armstrong (6):
dt-bindings: clk: meson: add sm1 periph clock controller bindings
clk: meson: g12a: add support for SM1 GP1 PLL
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
clk: meson: g12a: expose SM1 CPU 1, 2 & 3 clocks
arm64: dts: meson-sm1-sei610: enable DVFS
.../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
.../boot/dts/amlogic/meson-sm1-sei610.dts | 59 +-
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++
drivers/clk/meson/g12a.c | 544 ++++++++++++++++++
drivers/clk/meson/g12a.h | 26 +-
include/dt-bindings/clock/g12a-clkc.h | 3 +
6 files changed, 697 insertions(+), 5 deletions(-)
--
2.22.0
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* Re: [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Ivan Mikhaylov @ 2019-08-22 14:24 UTC (permalink / raw)
To: Guenter Roeck
Cc: linux-watchdog, linux-aspeed, Andrew Jeffery, Alexander Amelkin,
linux-kernel, Joel Stanley, Wim Van Sebroeck, linux-arm-kernel
In-Reply-To: <20190822135528.GB8144@roeck-us.net>
On Thu, 2019-08-22 at 06:55 -0700, Guenter Roeck wrote:
> On Thu, Aug 22, 2019 at 12:15:20PM +0300, Ivan Mikhaylov wrote:
> > On Wed, 2019-08-21 at 09:32 -0700, Guenter Roeck wrote:
> > > > + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> > > > + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> > > > + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> > >
> > > The variable reflects the _boot status_. It should not change after
> > > booting.
> >
> > Okay, then perhaps may we set 'status' handler for watchdog device and
> > check
> > 'status' file? Right now 'bootstatus' and 'status' are same because there is
> > no
> > handler for 'status'.
> >
>
> You would still have to redefine one of the status bits to mean something
> driver specific. You would also still have two different flags to read
> and control cs0 - to read the status, you would read an ioctl (or the
> status sysfs attribute), to write it you would write into access_cs0.
>
> I guess I must be missing something. What is the problem with using
> access_cs0 for both ?
>
> Guenter
>
There is no problem, I'll do that way, thanks!
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^ permalink raw reply
* Re: [PATCH] drm: meson: use match data to detect vpu compatibility
From: Julien Masson @ 2019-08-22 14:19 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman
Cc: linux-amlogic, dri-devel, linux-arm-kernel, linux-kernel
In-Reply-To: <87o90hzi3x.fsf@masson.i-did-not-set--mail-host-address--so-tickle-me>
Hi Neil,
On Thu 22 Aug 2019 at 16:14, Julien Masson <jmasson@baylibre.com> wrote:
> On 22/08/2019 11:03, Julien Masson wrote:
>> This patch introduce new enum which contains all VPU family (GXBB,
>> GXL, GXM and G12A).
>> This enum is used to detect the VPU compatible with the device.
>>
>> We only need to set .data to the corresponding enum in the device
>> table, no need to check .compatible string anymore.
>>
>> Signed-off-by: Julien Masson <jmasson@baylibre.com>
>> ---
>> drivers/gpu/drm/meson/meson_crtc.c | 2 +-
>> drivers/gpu/drm/meson/meson_drv.c | 12 +++--
>> drivers/gpu/drm/meson/meson_drv.h | 15 +++++-
>> drivers/gpu/drm/meson/meson_dw_hdmi.c | 2 +-
>> drivers/gpu/drm/meson/meson_overlay.c | 2 +-
>> drivers/gpu/drm/meson/meson_plane.c | 10 ++--
>> drivers/gpu/drm/meson/meson_vclk.c | 64 ++++++++++++-------------
>> drivers/gpu/drm/meson/meson_venc.c | 2 +-
>> drivers/gpu/drm/meson/meson_venc_cvbs.c | 10 ++--
>> drivers/gpu/drm/meson/meson_viu.c | 10 ++--
>> drivers/gpu/drm/meson/meson_vpp.c | 10 ++--
>> 11 files changed, 77 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
>> index bba25325aa9c..57ae1c13d1e6 100644
>> --- a/drivers/gpu/drm/meson/meson_crtc.c
>> +++ b/drivers/gpu/drm/meson/meson_crtc.c
>> @@ -575,7 +575,7 @@ int meson_crtc_create(struct meson_drm *priv)
>> return ret;
>> }
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1;
>> meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1;
>> meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET;
>> diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
>> index ae0166181606..97e9945f66c0 100644
>> --- a/drivers/gpu/drm/meson/meson_drv.c
>> +++ b/drivers/gpu/drm/meson/meson_drv.c
>> @@ -380,10 +380,14 @@ static int compare_of(struct device *dev, void *data)
>>
>> /* Possible connectors nodes to ignore */
>> static const struct of_device_id connectors_match[] = {
>> - { .compatible = "composite-video-connector" },
>> - { .compatible = "svideo-connector" },
>> - { .compatible = "hdmi-connector" },
>> - { .compatible = "dvi-connector" },
>> + { .compatible = "amlogic,meson-gxbb-vpu",
>> + .data = (void *)VPU_COMPATIBLE_GXBB },
>> + { .compatible = "amlogic,meson-gxl-vpu",
>> + .data = (void *)VPU_COMPATIBLE_GXL },
>> + { .compatible = "amlogic,meson-gxm-vpu",
>> + .data = (void *)VPU_COMPATIBLE_GXM },
>> + { .compatible = "amlogic,meson-g12a-vpu",
>> + .data = (void *)VPU_COMPATIBLE_G12A },
>> {}
>> };
Oups I sent the wrong version of this patch, this is wrong.
I must set .data in struct dt_match instead of connectors_match.
Will be done in v2, sorry for that.
>>
>> diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
>> index c9aaec1a846e..eab8c710c4e3 100644
>> --- a/drivers/gpu/drm/meson/meson_drv.h
>> +++ b/drivers/gpu/drm/meson/meson_drv.h
>> @@ -9,6 +9,7 @@
>>
>> #include <linux/device.h>
>> #include <linux/of.h>
>> +#include <linux/of_device.h>
>> #include <linux/regmap.h>
>>
>> struct drm_crtc;
>> @@ -16,6 +17,13 @@ struct drm_device;
>> struct drm_plane;
>> struct meson_drm;
>>
>> +enum vpu_compatible {
>> + VPU_COMPATIBLE_GXBB = 0,
>> + VPU_COMPATIBLE_GXL = 1,
>> + VPU_COMPATIBLE_GXM = 2,
>> + VPU_COMPATIBLE_G12A = 3,
>> +};
>> +
>> struct meson_drm {
>> struct device *dev;
>> void __iomem *io_base;
>> @@ -116,9 +124,12 @@ struct meson_drm {
>> };
>>
>> static inline int meson_vpu_is_compatible(struct meson_drm *priv,
>> - const char *compat)
>> + enum vpu_compatible family)
>> {
>> - return of_device_is_compatible(priv->dev->of_node, compat);
>> + enum vpu_compatible compat =
>> + (enum vpu_compatible)of_device_get_match_data(priv->dev);
>
> Can you store the family into struct meson_drm at probe then check the variable here instead ?
>
> Otherwise the rest looks fine.
>
> Neil
>
Yes sure, I will send you this change in v2 :)
>> +
>> + return compat == family;
>> }
>>
>> #endif /* __MESON_DRV_H */
>> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
>> index f893ebd0b799..68bbd987147b 100644
>> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
>> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
>> @@ -937,7 +937,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
>> reset_control_reset(meson_dw_hdmi->hdmitx_phy);
>>
>> /* Enable APB3 fail on error */
>> - if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> writel_bits_relaxed(BIT(15), BIT(15),
>> meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
>> writel_bits_relaxed(BIT(15), BIT(15),
>> diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c
>> index 5aa9dcb4b35e..2468b0212d52 100644
>> --- a/drivers/gpu/drm/meson/meson_overlay.c
>> +++ b/drivers/gpu/drm/meson/meson_overlay.c
>> @@ -513,7 +513,7 @@ static void meson_overlay_atomic_disable(struct drm_plane *plane,
>> priv->viu.vd1_enabled = false;
>>
>> /* Disable VD1 */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
>> writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
>> writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
>> diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
>> index b9e1e117fb85..ed543227b00d 100644
>> --- a/drivers/gpu/drm/meson/meson_plane.c
>> +++ b/drivers/gpu/drm/meson/meson_plane.c
>> @@ -138,7 +138,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
>> OSD_ENDIANNESS_LE);
>>
>> /* On GXBB, Use the old non-HDR RGB2YUV converter */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
>> priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
>>
>> switch (fb->format->format) {
>> @@ -292,7 +292,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
>> priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
>> priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
>> priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
>> priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
>> @@ -308,8 +308,8 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
>>
>> if (!meson_plane->enabled) {
>> /* Reset OSD1 before enabling it on GXL+ SoCs */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> meson_viu_osd1_reset(priv);
>>
>> meson_plane->enabled = true;
>> @@ -327,7 +327,7 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
>> struct meson_drm *priv = meson_plane->priv;
>>
>> /* Disable OSD1 */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
>> priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
>> else
>> diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
>> index 869231c93617..ac491a781952 100644
>> --- a/drivers/gpu/drm/meson/meson_vclk.c
>> +++ b/drivers/gpu/drm/meson/meson_vclk.c
>> @@ -242,7 +242,7 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
>> unsigned int val;
>>
>> /* Setup PLL to output 1.485GHz */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
>> @@ -254,8 +254,8 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
>> /* Poll for lock bit */
>> regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> (val & HDMI_PLL_LOCK), 10, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
>> @@ -272,7 +272,7 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
>> /* Poll for lock bit */
>> regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> (val & HDMI_PLL_LOCK), 10, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
>> @@ -300,7 +300,7 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
>> VCLK2_DIV_MASK, (55 - 1));
>>
>> /* select vid_pll for vclk2 */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>> VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
>> else
>> @@ -455,7 +455,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
>> {
>> unsigned int val;
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
>> if (frac)
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
>> @@ -475,8 +475,8 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
>> /* Poll for lock bit */
>> regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
>> val, (val & HDMI_PLL_LOCK), 10, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
>> @@ -493,7 +493,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
>> /* Poll for lock bit */
>> regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
>> (val & HDMI_PLL_LOCK), 10, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
>>
>> /* Enable and reset */
>> @@ -545,36 +545,36 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
>> } while(1);
>> }
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
>> 3 << 16, pll_od_to_reg(od1) << 16);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
>> 3 << 21, pll_od_to_reg(od1) << 21);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
>> 3 << 16, pll_od_to_reg(od1) << 16);
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
>> 3 << 22, pll_od_to_reg(od2) << 22);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
>> 3 << 23, pll_od_to_reg(od2) << 23);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
>> 3 << 18, pll_od_to_reg(od2) << 18);
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
>> 3 << 18, pll_od_to_reg(od3) << 18);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
>> 3 << 19, pll_od_to_reg(od3) << 19);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
>> 3 << 20, pll_od_to_reg(od3) << 20);
>> }
>> @@ -585,7 +585,7 @@ static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
>> unsigned int pll_freq)
>> {
>> /* The GXBB PLL has a /2 pre-multiplier */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
>> pll_freq /= 2;
>>
>> return pll_freq / XTAL_FREQ;
>> @@ -605,12 +605,12 @@ static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
>> unsigned int frac;
>>
>> /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> frac_max = HDMI_FRAC_MAX_GXBB;
>> parent_freq *= 2;
>> }
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> frac_max = HDMI_FRAC_MAX_G12A;
>>
>> /* We can have a perfect match !*/
>> @@ -631,15 +631,15 @@ static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
>> unsigned int m,
>> unsigned int frac)
>> {
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> /* Empiric supported min/max dividers */
>> if (m < 53 || m > 123)
>> return false;
>> if (frac >= HDMI_FRAC_MAX_GXBB)
>> return false;
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> /* Empiric supported min/max dividers */
>> if (m < 106 || m > 247)
>> return false;
>> @@ -759,7 +759,7 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
>> /* Set HDMI PLL rate */
>> if (!od1 && !od2 && !od3) {
>> meson_hdmi_pll_generic_set(priv, pll_base_freq);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> switch (pll_base_freq) {
>> case 2970000:
>> m = 0x3d;
>> @@ -776,8 +776,8 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
>> }
>>
>> meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
>> switch (pll_base_freq) {
>> case 2970000:
>> m = 0x7b;
>> @@ -794,7 +794,7 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
>> }
>>
>> meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> switch (pll_base_freq) {
>> case 2970000:
>> m = 0x7b;
>> diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
>> index 679d2274531c..4efd7864d5bf 100644
>> --- a/drivers/gpu/drm/meson/meson_venc.c
>> +++ b/drivers/gpu/drm/meson/meson_venc.c
>> @@ -1759,7 +1759,7 @@ void meson_venc_disable_vsync(struct meson_drm *priv)
>> void meson_venc_init(struct meson_drm *priv)
>> {
>> /* Disable CVBS VDAC */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
>> regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8);
>> } else {
>> diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c
>> index 6dc130a24070..9ab27aecfcf3 100644
>> --- a/drivers/gpu/drm/meson/meson_venc_cvbs.c
>> +++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c
>> @@ -155,7 +155,7 @@ static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder)
>> struct meson_drm *priv = meson_venc_cvbs->priv;
>>
>> /* Disable CVBS VDAC */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
>> regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
>> } else {
>> @@ -174,14 +174,14 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
>> writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
>> priv->io_base + _REG(VENC_VDAC_DACSEL0));
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
>> regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
>> regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
>> regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
>> regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
>> regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
>> }
>> diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
>> index e70cd55d56c9..68cf2c2eca5f 100644
>> --- a/drivers/gpu/drm/meson/meson_viu.c
>> +++ b/drivers/gpu/drm/meson/meson_viu.c
>> @@ -353,10 +353,10 @@ void meson_viu_init(struct meson_drm *priv)
>> priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
>>
>> /* On GXL/GXM, Use the 10bit HDR conversion matrix */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
>> - meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
>> + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> meson_viu_load_matrix(priv);
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
>> true);
>>
>> @@ -367,7 +367,7 @@ void meson_viu_init(struct meson_drm *priv)
>> VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
>> VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> reg |= meson_viu_osd_burst_length_reg(32);
>> else
>> reg |= meson_viu_osd_burst_length_reg(64);
>> @@ -394,7 +394,7 @@ void meson_viu_init(struct meson_drm *priv)
>> writel_relaxed(0x00FF00C0,
>> priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
>>
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
>> writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
>> VIU_OSD_BLEND_REORDER(1, 0) |
>> VIU_OSD_BLEND_REORDER(2, 0) |
>> diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
>> index 1429f3be6028..154837688ab0 100644
>> --- a/drivers/gpu/drm/meson/meson_vpp.c
>> +++ b/drivers/gpu/drm/meson/meson_vpp.c
>> @@ -91,20 +91,20 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
>> void meson_vpp_init(struct meson_drm *priv)
>> {
>> /* set dummy data default YUV black */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>> writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
>> - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
>> + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
>> writel_bits_relaxed(0xff << 16, 0xff << 16,
>> priv->io_base + _REG(VIU_MISC_CTRL1));
>> writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
>> priv->io_base + _REG(VPP_DOLBY_CTRL));
>> writel_relaxed(0x1020080,
>> priv->io_base + _REG(VPP_DUMMY_DATA1));
>> - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
>>
>> /* Initialize vpu fifo control registers */
>> - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
>> + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
>> writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
>> priv->io_base + _REG(VPP_OFIFO_SIZE));
> else
> @@ -113,7 +113,7 @@ void meson_vpp_init(struct meson_drm *priv)
> writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
> priv->io_base + _REG(VPP_HOLD_LINES));
>
> - if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
> + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
> /* Turn off preblend */
> writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
> priv->io_base + _REG(VPP_MISC));
>
--
Julien Masson
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^ permalink raw reply
* Re: [PATCH -next] ASoC: sun4i-i2s: Use PTR_ERR_OR_ZERO in sun4i_i2s_init_regmap_fields()
From: Maxime Ripard @ 2019-08-22 14:18 UTC (permalink / raw)
To: YueHaibing
Cc: alsa-devel, linux-kernel, kernel-janitors, Takashi Iwai,
Liam Girdwood, Marcus Cooper, Chen-Yu Tsai, Mark Brown,
Jaroslav Kysela, linux-arm-kernel
In-Reply-To: <20190822065252.74028-1-yuehaibing@huawei.com>
[-- Attachment #1.1: Type: text/plain, Size: 1023 bytes --]
Hi,
On Thu, Aug 22, 2019 at 06:52:52AM +0000, YueHaibing wrote:
> Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
>
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
> ---
> sound/soc/sunxi/sun4i-i2s.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
> index 9e691baee1e8..2071c54265f3 100644
> --- a/sound/soc/sunxi/sun4i-i2s.c
> +++ b/sound/soc/sunxi/sun4i-i2s.c
> @@ -1095,10 +1095,7 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
> i2s->field_fmt_sr =
> devm_regmap_field_alloc(dev, i2s->regmap,
> i2s->variant->field_fmt_sr);
> - if (IS_ERR(i2s->field_fmt_sr))
> - return PTR_ERR(i2s->field_fmt_sr);
> -
> - return 0;
> + return PTR_ERR_OR_ZERO(i2s->field_fmt_sr);
I'm not really convinced that this more readable or more maintainable
though. Is there a reason for this other than we can do it?
Maxie
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* [PATCH] arm64: Add tagged-address-abi.rst to index.rst
From: Vincenzo Frascino @ 2019-08-22 14:17 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: catalin.marinas, will
In-Reply-To: <20190821164730.47450-3-catalin.marinas@arm.com>
Documentation/arm64/tagged-address-abi.rst introduces the
relaxation of the syscall ABI that allows userspace to pass
certain tagged pointers to kernel syscalls.
Add the document to index.rst for a correct generation of the
table of content.
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
Documentation/arm64/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst
index 96b696ba4e6c..5c0c69dc58aa 100644
--- a/Documentation/arm64/index.rst
+++ b/Documentation/arm64/index.rst
@@ -16,6 +16,7 @@ ARM64 Architecture
pointer-authentication
silicon-errata
sve
+ tagged-address-abi
tagged-pointers
.. only:: subproject and html
--
2.22.1
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^ permalink raw reply related
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell
From: Robin Murphy @ 2019-08-22 14:16 UTC (permalink / raw)
To: Gregory CLEMENT, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
In-Reply-To: <20190711150242.25290-4-gregory.clement@bootlin.com>
On 11/07/2019 16:02, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
Forgive me for repeating myself[1], but:
"Given that, I think something more specific like:
"marvell,ap806-smmu", "arm,mmu-500";
would be most appropriate. Otherwise, if some future Marvell SoC were to
ever come out with a *different* MMU-500 integration problem, you'd
already have painted yourself into a corner."
Robin.
[1]
https://lore.kernel.org/linux-arm-kernel/3ce1d67a-4e3c-e8d8-f7fc-79649f1def68@arm.com/
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..7ed58d51846e 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -16,6 +16,7 @@ conditions.
> "arm,mmu-400"
> "arm,mmu-401"
> "arm,mmu-500"
> + "marvell,mmu-500"
> "cavium,smmu-v2"
> "qcom,smmu-v2"
>
>
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* Re: [PATCH v3 0/2] arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)
From: Maxime Ripard @ 2019-08-22 14:09 UTC (permalink / raw)
To: Sunil Mohan Adapa
Cc: mark.rutland, devicetree, wens, robh+dt, linux-arm-kernel
In-Reply-To: <20190821195217.4166-1-sunil@medhas.org>
[-- Attachment #1.1: Type: text/plain, Size: 748 bytes --]
On Wed, Aug 21, 2019 at 12:52:15PM -0700, Sunil Mohan Adapa wrote:
> A64 OLinuXino board from Olimex has three variants with onboard eMMC:
> A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In
> addition, there are two variants without eMMC. One without eMMC and one with SPI
> flash. This suggests the need for separate device tree for the three eMMC
> variants.
>
> Changes:
>
> v3: Separate dts for eMMC variants
>
> v2: Fix descriptions for VCC and VCCQ
>
> Version 2 of this series already committed in linux-sunxi tree as
> 8d3071f3e85894be35a1b35bcf6fdef970c81018 must be reverted before applying this.
Applied, thanks!
Maxime
--
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Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH v10 23/23] iommu/mediatek: Clean up struct mtk_smi_iommu
From: Matthias Brugger @ 2019-08-22 14:07 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Robin Murphy, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang,
srv_heupstream, chao.hao, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, ming-fan.chen, anan.sun,
Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1566395606-7975-24-git-send-email-yong.wu@mediatek.com>
On 21/08/2019 15:53, Yong Wu wrote:
> Remove the "struct mtk_smi_iommu" to simplify the code since it has only
> one item in it right now.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/iommu/mtk_iommu.c | 4 ++--
> drivers/iommu/mtk_iommu.h | 6 +++---
> drivers/iommu/mtk_iommu_v1.c | 4 ++--
> drivers/memory/mtk-smi.c | 6 +++---
> include/soc/mediatek/smi.h | 4 ----
> 5 files changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index cc81de2..400066d 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -278,7 +278,7 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
> for (i = 0; i < fwspec->num_ids; ++i) {
> larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
> portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
> - larb_mmu = &data->smi_imu.larb_imu[larbid];
> + larb_mmu = &data->larb_imu[larbid];
>
> dev_dbg(dev, "%s iommu port: %d\n",
> enable ? "enable" : "disable", portid);
> @@ -680,7 +680,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> of_node_put(larbnode);
> return -EPROBE_DEFER;
> }
> - data->smi_imu.larb_imu[id].dev = &plarbdev->dev;
> + data->larb_imu[id].dev = &plarbdev->dev;
>
> component_match_add_release(dev, &match, release_of,
> compare_of, larbnode);
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 56b579c..fc0f16e 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -56,7 +56,6 @@ struct mtk_iommu_data {
> struct mtk_iommu_suspend_reg reg;
> struct mtk_iommu_domain *m4u_dom;
> struct iommu_group *m4u_group;
> - struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
> bool enable_4GB;
> bool tlb_flush_active;
>
> @@ -64,6 +63,7 @@ struct mtk_iommu_data {
> const struct mtk_iommu_plat_data *plat_data;
>
> struct list_head list;
> + struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> };
>
> static inline int compare_of(struct device *dev, void *data)
> @@ -80,14 +80,14 @@ static inline int mtk_iommu_bind(struct device *dev)
> {
> struct mtk_iommu_data *data = dev_get_drvdata(dev);
>
> - return component_bind_all(dev, &data->smi_imu);
> + return component_bind_all(dev, &data->larb_imu);
> }
>
> static inline void mtk_iommu_unbind(struct device *dev)
> {
> struct mtk_iommu_data *data = dev_get_drvdata(dev);
>
> - component_unbind_all(dev, &data->smi_imu);
> + component_unbind_all(dev, &data->larb_imu);
> }
>
> #endif
> diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
> index 3922358..860926c 100644
> --- a/drivers/iommu/mtk_iommu_v1.c
> +++ b/drivers/iommu/mtk_iommu_v1.c
> @@ -206,7 +206,7 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
> for (i = 0; i < fwspec->num_ids; ++i) {
> larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
> portid = mt2701_m4u_to_port(fwspec->ids[i]);
> - larb_mmu = &data->smi_imu.larb_imu[larbid];
> + larb_mmu = &data->larb_imu[larbid];
>
> dev_dbg(dev, "%s iommu port: %d\n",
> enable ? "enable" : "disable", portid);
> @@ -610,7 +610,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
> }
> }
>
> - data->smi_imu.larb_imu[larb_nr].dev = &plarbdev->dev;
> + data->larb_imu[larb_nr].dev = &plarbdev->dev;
> component_match_add_release(dev, &match, release_of,
> compare_of, larb_spec.np);
> larb_nr++;
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> index d6dc62f..439d7d8 100644
> --- a/drivers/memory/mtk-smi.c
> +++ b/drivers/memory/mtk-smi.c
> @@ -143,13 +143,13 @@ void mtk_smi_larb_put(struct device *larbdev)
> mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
> {
> struct mtk_smi_larb *larb = dev_get_drvdata(dev);
> - struct mtk_smi_iommu *smi_iommu = data;
> + struct mtk_smi_larb_iommu *larb_mmu = data;
> unsigned int i;
>
> for (i = 0; i < MTK_LARB_NR_MAX; i++) {
> - if (dev == smi_iommu->larb_imu[i].dev) {
> + if (dev == larb_mmu[i].dev) {
> larb->larbid = i;
> - larb->mmu = &smi_iommu->larb_imu[i].mmu;
> + larb->mmu = &larb_mmu[i].mmu;
> return 0;
> }
> }
> diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
> index 6f0b00c..5a34b87 100644
> --- a/include/soc/mediatek/smi.h
> +++ b/include/soc/mediatek/smi.h
> @@ -20,10 +20,6 @@ struct mtk_smi_larb_iommu {
> unsigned int mmu;
> };
>
> -struct mtk_smi_iommu {
> - struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
> -};
> -
> /*
> * mtk_smi_larb_get: Enable the power domain and clocks for this local arbiter.
> * It also initialize some basic setting(like iommu).
>
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* Re: [PATCH 3/3] watchdog/aspeed: add support for dual boot
From: Guenter Roeck @ 2019-08-22 13:55 UTC (permalink / raw)
To: Ivan Mikhaylov
Cc: linux-watchdog, linux-aspeed, Andrew Jeffery, Alexander Amelkin,
linux-kernel, Joel Stanley, Wim Van Sebroeck, linux-arm-kernel
In-Reply-To: <a022c0590f0fbf22cc8476b5ef3f1c22746429ac.camel@yadro.com>
On Thu, Aug 22, 2019 at 12:15:20PM +0300, Ivan Mikhaylov wrote:
> On Wed, 2019-08-21 at 09:32 -0700, Guenter Roeck wrote:
> >
> > > + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
> > > + wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
> > > + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> >
> > The variable reflects the _boot status_. It should not change after booting.
>
> Okay, then perhaps may we set 'status' handler for watchdog device and check
> 'status' file? Right now 'bootstatus' and 'status' are same because there is no
> handler for 'status'.
>
You would still have to redefine one of the status bits to mean something
driver specific. You would also still have two different flags to read
and control cs0 - to read the status, you would read an ioctl (or the
status sysfs attribute), to write it you would write into access_cs0.
I guess I must be missing something. What is the problem with using
access_cs0 for both ?
Guenter
> > > +
> > > + return size;
> > > +}
> > > +static DEVICE_ATTR_WO(access_cs0);
> > > +
> > > +static struct attribute *bswitch_attrs[] = {
> > > + &dev_attr_access_cs0.attr,
> > > + NULL
> > > +};
> > > +ATTRIBUTE_GROUPS(bswitch);
> > > +
> > > static const struct watchdog_ops aspeed_wdt_ops = {
> > > .start = aspeed_wdt_start,
> > > .stop = aspeed_wdt_stop,
> > > @@ -223,6 +248,9 @@ static int aspeed_wdt_probe(struct platform_device
> > > *pdev)
> > >
> > > wdt->ctrl = WDT_CTRL_1MHZ_CLK;
> > >
> > > + if (of_property_read_bool(np, "aspeed,alt-boot"))
> > > + wdt->wdd.groups = bswitch_groups;
> > > +
> > Why does this have to be separate to the existing evaluation of
> > aspeed,alt-boot, and why does the existing code not work ?
> >
> > Also, is it guaranteed that this does not interfer with existing
> > support for alt-boot ?
>
> It doesn't, it just provides for ast2400 switch to cs0 at side 1(cs1). Problem
> is that only one flash chip(side 1/cs1) is accessible on alternate boot, there
> is citation from the documentation in commit body. So if by some reason side 0
> is corrupted, need to switch into alternate boot to cs1, do the load from it,
> drop that bit to make side 0 accessible and do the flash of first side. On
> ast2500/2600 this problem is solved already, in alternate boot there both flash
> chips are present. It's additional requirement for alternate boot on ast2400, to
> make the possibility to access at all side 0 flash chip after we boot to the
> alternate side.
>
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* Re: [PATCH RFC v1 2/2] mmc: host: meson-mx-sdhc: new driver for the Amlogic Meson SDHC host
From: Ulf Hansson @ 2019-08-22 13:52 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: Mark Rutland, DTML, jianxin.pan, linux-mmc@vger.kernel.org,
Linux Kernel Mailing List, Rob Herring,
open list:ARM/Amlogic Meson..., Linux ARM
In-Reply-To: <20190708173330.13217-3-martin.blumenstingl@googlemail.com>
On Mon, 8 Jul 2019 at 19:33, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> WiP - only partially working - see performance numbers.
>
> Odroid-C1 eMMC (HS-200):
> Amlogic's vendor driver @ Linux 3.10:
> 7781351936 bytes (7.8 GB) copied, 134.714 s, 57.8 MB/s
> This driver:
> 7781351936 bytes (7.8 GB, 7.2 GiB) copied, 189.02 s, 41.2 MB/s
>
> EC-100 eMMC (HS MMC):
> Amlogic's vendor driver @ Linux 3.10:
> 15762194432 bytes (16 GB) copied, 422.967 s, 37.3 MB/s
> This driver:
> 15762194432 bytes (16 GB, 15 GiB) copied, 9232.65 s, 1.7 MB/s
>
> 1) Amlogic's vendor driver does some magic with the divider:
> clk_div = input_rate / clk_ios - !(input_rate%clk_ios);
> if (!(clk_div & 0x01)) // if even number, turn it to an odd one
> clk_div++;
> It's not clear to me whether what the reason behind this is, what is
> supposed to be achieved with this?
>
> 2) The hardcoded RX clock phases are taken from the vendor driver. It
> seems that these are only valid when fclk_div3 is used as input
> clock (however, there are four more inputs). It's not clear to me how
> to calculate the RX clock phases in set_ios based on the input clock
> and the ios rate.
>
> 3) The hardware supports a timeout IRQ but the max_busy_timeout is not
> documented anywhere.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Martin, overall this looks good to me. Once you moved from RFC to a
formal patch I will check again, of course.
There are a couple of calls to readl_poll_timeout(), for different
reasons, that I have some questions about, but we can discuss those in
the next step.
[...]
Kind regards
Uffe
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* Re: [v4, 6/8] PM / OPP: Support adjusting OPP voltages at runtime
From: Matthias Brugger @ 2019-08-22 13:51 UTC (permalink / raw)
To: Andrew-sh.Cheng, MyungJoo Ham, Kyungmin Park, Chanwoo Choi,
Rob Herring, Mark Rutland, Rafael J. Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd
Cc: devicetree, srv_heupstream, linux-pm, Roger Lu, Stephen Boyd,
linux-kernel, fan.chen, linux-mediatek, linux-arm-kernel
In-Reply-To: <1565703113-31479-7-git-send-email-andrew-sh.cheng@mediatek.com>
On 13/08/2019 15:31, Andrew-sh.Cheng wrote:
> From: Stephen Boyd <sboyd@codeaurora.org>
>
> On some SoCs the Adaptive Voltage Scaling (AVS) technique is
> employed to optimize the operating voltage of a device. At a
> given frequency, the hardware monitors dynamic factors and either
> makes a suggestion for how much to adjust a voltage for the
> current frequency, or it automatically adjusts the voltage
> without software intervention. Add an API to the OPP library for
> the former case, so that AVS type devices can update the voltages
> for an OPP when the hardware determines the voltage should
> change. The assumption is that drivers like CPUfreq or devfreq
> will register for the OPP notifiers and adjust the voltage
> according to suggestions that AVS makes.
>
> This patch is devired from [1] submitted by Stephen.
> [1] https://lore.kernel.org/patchwork/patch/599279/
>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Nit: your signed-off-by tag is missing.
Regards,
Matthias
> ---
> drivers/opp/core.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++
> include/linux/pm_opp.h | 11 +++++++++
> 2 files changed, 74 insertions(+)
>
> diff --git a/drivers/opp/core.c b/drivers/opp/core.c
> index c094d5d20fd7..407a07f29b12 100644
> --- a/drivers/opp/core.c
> +++ b/drivers/opp/core.c
> @@ -2054,6 +2054,69 @@ static int _opp_set_availability(struct device *dev, unsigned long freq,
> }
>
> /**
> + * dev_pm_opp_adjust_voltage() - helper to change the voltage of an OPP
> + * @dev: device for which we do this operation
> + * @freq: OPP frequency to adjust voltage of
> + * @u_volt: new OPP voltage
> + *
> + * Return: -EINVAL for bad pointers, -ENOMEM if no memory available for the
> + * copy operation, returns 0 if no modifcation was done OR modification was
> + * successful.
> + */
> +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
> + unsigned long u_volt)
> +{
> + struct opp_table *opp_table;
> + struct dev_pm_opp *tmp_opp, *opp = ERR_PTR(-ENODEV);
> + int r = 0;
> +
> + /* Find the opp_table */
> + opp_table = _find_opp_table(dev);
> + if (IS_ERR(opp_table)) {
> + r = PTR_ERR(opp_table);
> + dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r);
> + return r;
> + }
> +
> + mutex_lock(&opp_table->lock);
> +
> + /* Do we have the frequency? */
> + list_for_each_entry(tmp_opp, &opp_table->opp_list, node) {
> + if (tmp_opp->rate == freq) {
> + opp = tmp_opp;
> + break;
> + }
> + }
> +
> + if (IS_ERR(opp)) {
> + r = PTR_ERR(opp);
> + goto adjust_unlock;
> + }
> +
> + /* Is update really needed? */
> + if (opp->supplies->u_volt == u_volt)
> + goto adjust_unlock;
> +
> + opp->supplies->u_volt = u_volt;
> +
> + dev_pm_opp_get(opp);
> + mutex_unlock(&opp_table->lock);
> +
> + /* Notify the voltage change of the OPP */
> + blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_ADJUST_VOLTAGE,
> + opp);
> +
> + dev_pm_opp_put(opp);
> + goto adjust_put_table;
> +
> +adjust_unlock:
> + mutex_unlock(&opp_table->lock);
> +adjust_put_table:
> + dev_pm_opp_put_opp_table(opp_table);
> + return r;
> +}
> +
> +/**
> * dev_pm_opp_enable() - Enable a specific OPP
> * @dev: device for which we do this operation
> * @freq: OPP frequency to enable
> diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
> index af5021f27cb7..86947d53e8c4 100644
> --- a/include/linux/pm_opp.h
> +++ b/include/linux/pm_opp.h
> @@ -22,6 +22,7 @@ struct opp_table;
>
> enum dev_pm_opp_event {
> OPP_EVENT_ADD, OPP_EVENT_REMOVE, OPP_EVENT_ENABLE, OPP_EVENT_DISABLE,
> + OPP_EVENT_ADJUST_VOLTAGE,
> };
>
> /**
> @@ -111,6 +112,9 @@ int dev_pm_opp_add(struct device *dev, unsigned long freq,
> void dev_pm_opp_remove(struct device *dev, unsigned long freq);
> void dev_pm_opp_remove_all_dynamic(struct device *dev);
>
> +int dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
> + unsigned long u_volt);
> +
> int dev_pm_opp_enable(struct device *dev, unsigned long freq);
>
> int dev_pm_opp_disable(struct device *dev, unsigned long freq);
> @@ -234,6 +238,13 @@ static inline void dev_pm_opp_remove_all_dynamic(struct device *dev)
> {
> }
>
> +static inline int
> +dev_pm_opp_adjust_voltage(struct device *dev, unsigned long freq,
> + unsigned long u_volt)
> +{
> + return 0;
> +}
> +
> static inline int dev_pm_opp_enable(struct device *dev, unsigned long freq)
> {
> return 0;
>
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* Re: [RESEND PATCH] KVM: arm: VGIC: properly initialise private IRQ affinity
From: Marc Zyngier @ 2019-08-22 13:48 UTC (permalink / raw)
To: Andre Przywara, Zenghui Yu
Cc: Dave Martin, Julien Grall, kvmarm, linux-arm-kernel,
Christoffer Dall
In-Reply-To: <20190822144224.12d51380@donnerap.cambridge.arm.com>
On 22/08/2019 14:42, Andre Przywara wrote:
> On Thu, 22 Aug 2019 01:13:32 +0800
> Zenghui Yu <yuzenghui@huawei.com> wrote:
>
> Hi,
>
>> On 2019/8/22 1:00, Andre Przywara wrote:
>>> At the moment we initialise the target *mask* of a virtual IRQ to the
>>> VCPU it belongs to, even though this mask is only defined for GICv2 and
>>> quickly runs out of bits for many GICv3 guests.
>>> This behaviour triggers an UBSAN complaint for more than 32 VCPUs:
>>> ------
>>> [ 5659.462377] UBSAN: Undefined behaviour in virt/kvm/arm/vgic/vgic-init.c:223:21
>>> [ 5659.471689] shift exponent 32 is too large for 32-bit type 'unsigned int'
>>> ------
>>> Also for GICv3 guests the reporting of TARGET in the "vgic-state" debugfs
>>> dump is wrong, due to this very same problem.
>>>
>>> Fix both issues by only initialising vgic_irq->targets for a vGICv2 guest,
>>> and by initialising vgic_irq->mpdir for vGICv3 guests instead. We can't
>>> use the actual MPIDR for that, as the VCPU's system register is not
>>> initialised at this point yet. This is not really an issue, as ->mpidr
>>> is just used for the debugfs output and the IROUTER MMIO register, which
>>> does not exist in redistributors (dealing with SGIs and PPIs).
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> Reported-by: Dave Martin <dave.martin@arm.com>
>>> ---
>>> Hi,
>>>
>>> this came up here again, I think it fell through the cracks back in
>>> March:
>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2019-March/637209.html
>>>
>>> Cheers,
>>> Andre.
>>>
>>> virt/kvm/arm/vgic/vgic-init.c | 9 ++++++---
>>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c
>>> index 80127ca9269f..8bce2f75e0c1 100644
>>> --- a/virt/kvm/arm/vgic/vgic-init.c
>>> +++ b/virt/kvm/arm/vgic/vgic-init.c
>>> @@ -210,7 +210,6 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
>>> irq->intid = i;
>>> irq->vcpu = NULL;
>>> irq->target_vcpu = vcpu;
>>> - irq->targets = 1U << vcpu->vcpu_id;
>>> kref_init(&irq->refcount);
>>> if (vgic_irq_is_sgi(i)) {
>>> /* SGIs */
>>> @@ -221,10 +220,14 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
>>> irq->config = VGIC_CONFIG_LEVEL;
>>> }
>>>
>>> - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
>>> + if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
>>
>> I still think that if user-space create VCPUs before vGIC (like what
>> Qemu does), the actual vGIC model will be unknown here. The UBSAN
>> warning will still show up when booting a vGIC-v3 guest (with Qemu).
>
> Yes, you are right. I vaguely remembered this issue, but couldn't
> find anything on the list about it. So thanks for the heads up!
>
> So I think I have a solution, where we drop the initialisation part
> here altogether, instead initialise mpdir/targets together with the
> group in vgic_init(). Unless there is some code which needs
> irq->group before that point?
You may want to check save/restore of a GICv3 guest using a mix of
group-0/1 interrupts. I seem to remember some breakage in that area.
> Will send a patch shortly.
OK. In the meantime, I'll drop your initial patch.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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* Re: [PATCH v6 3/4] dt-bindings: arm: fsl: Add Kontron i.MX6UL N6310 compatibles
From: Krzysztof Kozlowski @ 2019-08-22 13:45 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Shawn Guo, Sascha Hauer,
linux-kernel@vger.kernel.org, Schrempf Frieder, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_Jsq+YZ9KdCCT1grtpf7Z1o=-mFuq3O=o7iVGSAhJYO1-=Ww@mail.gmail.com>
On Thu, 22 Aug 2019 at 14:52, Rob Herring <robh+dt@kernel.org> wrote:
>
> On Wed, Aug 21, 2019 at 12:55 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On Tue, Aug 20, 2019 at 03:27:39PM -0500, Rob Herring wrote:
> > > > I see. If I understand the schema correctly, this should look like:
> > >
> > > Looks correct, but a couple of comments.
> > >
> > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > index 7294ac36f4c0..eb263d1ccf13 100644
> > > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > @@ -161,6 +161,22 @@ properties:
> > > > items:
> > > > - enum:
> > > > - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
> > > > + - kontron,imx6ul-n6310-som # Kontron N6310 SOM
> > >
> > > Is the SOM ever used alone? If not, then no point in listing this here.
> >
> > SoM alone: no, because it requires some type of base board. However it
> > will be used by some customer designs with some amount of
> > changes/addons.
> >
> > Looking at other aproaches, usually SoMs have their own compatible. In
> > such case - I should document it somewhere.
>
> I wasn't suggesting not having the compatible for it, but you don't
> need it in this list because that is not valid. You have to list it
> with the base board compatibles.
The diff against v7 would be like this then:
---
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
b/Documentation/devicetree/bindings/arm/fsl.yaml
index 1f440817fc03..7219c15f6185 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -161,7 +161,6 @@ properties:
items:
- enum:
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- - kontron,imx6ul-n6310-som # Kontron N6310 SOM
- const: fsl,imx6ul
- description: Kontron N6310 S Board
---
This passes the dtbs_check.
I'll send v8
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