* Re: [RFC v4 05/18] objtool: special: Adapt special section handling
From: Julien @ 2019-08-22 20:18 UTC (permalink / raw)
To: Raphael Gault, linux-arm-kernel, linux-kernel, jpoimboe
Cc: peterz, catalin.marinas, will.deacon, raph.gault+kdev
In-Reply-To: <20190816122403.14994-6-raphael.gault@arm.com>
Hi Raphaël,
On 16/08/19 13:23, Raphael Gault wrote:
> This patch abstracts the few architecture dependent tests that are
> perform when handling special section and switch tables. It enables any
> architecture to ignore a particular CPU feature or not to handle switch
> tables.
I think it would be better if this patch only focused on CPU features
and leave dealing with switch table to subsequent patches.
>
> Signed-off-by: Raphael Gault <raphael.gault@arm.com>
> ---
> tools/objtool/arch/arm64/Build | 1 +
> tools/objtool/arch/arm64/arch_special.c | 22 +++++++++++++++
> .../objtool/arch/arm64/include/arch_special.h | 10 +++++--
> tools/objtool/arch/x86/Build | 1 +
> tools/objtool/arch/x86/arch_special.c | 28 +++++++++++++++++++
> tools/objtool/arch/x86/include/arch_special.h | 9 ++++++
> tools/objtool/check.c | 24 ++++++++++++++--
> tools/objtool/special.c | 9 ++----
> tools/objtool/special.h | 3 ++
> 9 files changed, 96 insertions(+), 11 deletions(-)
> create mode 100644 tools/objtool/arch/arm64/arch_special.c
> create mode 100644 tools/objtool/arch/x86/arch_special.c
>
> diff --git a/tools/objtool/arch/arm64/Build b/tools/objtool/arch/arm64/Build
> index bf7a32c2b9e9..3d09be745a84 100644
> --- a/tools/objtool/arch/arm64/Build
> +++ b/tools/objtool/arch/arm64/Build
> @@ -1,3 +1,4 @@
> +objtool-y += arch_special.o
> objtool-y += decode.o
> objtool-y += orc_dump.o
> objtool-y += orc_gen.o
> diff --git a/tools/objtool/arch/arm64/arch_special.c b/tools/objtool/arch/arm64/arch_special.c
> new file mode 100644
> index 000000000000..a21d28876317
> --- /dev/null
> +++ b/tools/objtool/arch/arm64/arch_special.c
> @@ -0,0 +1,22 @@
> +/*
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "../../special.h"
> +#include "arch_special.h"
> +
> +void arch_force_alt_path(unsigned short feature,
> + bool uaccess,
> + struct special_alt *alt)
> +{
> +}
> diff --git a/tools/objtool/arch/arm64/include/arch_special.h b/tools/objtool/arch/arm64/include/arch_special.h
> index 63da775d0581..185103be8a51 100644
> --- a/tools/objtool/arch/arm64/include/arch_special.h
> +++ b/tools/objtool/arch/arm64/include/arch_special.h
> @@ -30,7 +30,13 @@
> #define ALT_ORIG_LEN_OFFSET 10
> #define ALT_NEW_LEN_OFFSET 11
>
> -#define X86_FEATURE_POPCNT (4 * 32 + 23)
> -#define X86_FEATURE_SMAP (9 * 32 + 20)
> +static inline bool arch_should_ignore_feature(unsigned short feature)
> +{
> + return false;
> +}
>
> +static inline bool arch_support_switch_table(void)
> +{
> + return false;
If I understand correctly , this gets later (patch 8) replaced by
arch_find_switch_table() which can return NULL if unable to find a
switch table.
So, is it necessary to introduce this function at this stage of the
patchset? Can't we just have directly arch_find_switch_table() ?
Also, I believe that in the end you keep the two
arch_support_switch_table() implementations (x86 and arm64) despite
getting rid of the only caller (in patch 8).
> +}
> #endif /* _ARM64_ARCH_SPECIAL_H */
> diff --git a/tools/objtool/arch/x86/Build b/tools/objtool/arch/x86/Build
> index 1f11b45999d0..63e167775bc8 100644
> --- a/tools/objtool/arch/x86/Build
> +++ b/tools/objtool/arch/x86/Build
> @@ -1,3 +1,4 @@
> +objtool-y += arch_special.o
> objtool-y += decode.o
> objtool-y += orc_dump.o
> objtool-y += orc_gen.o
> diff --git a/tools/objtool/arch/x86/arch_special.c b/tools/objtool/arch/x86/arch_special.c
> new file mode 100644
> index 000000000000..6583a1770bb2
> --- /dev/null
> +++ b/tools/objtool/arch/x86/arch_special.c
> @@ -0,0 +1,28 @@
> +/*
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "../../special.h"
> +#include "arch_special.h"
> +
> +void arch_force_alt_path(unsigned short feature,
> + bool uaccess,
Maybe you could have something like:
void arch_select_alt_path(unsigned short feature, struct special_alt *alt);
or arch_process_alt_inst(...);
This way you just let the arch decide what to do for alternative
instructions associated with their features, and call it in the "if
(entry->feature)" branch of get_alt_entry().
You don't need to pass the "uaccess" as that info is globally accessible
from builtin.h.
> + struct special_alt *alt)
> +{
> + if (feature == X86_FEATURE_SMAP) {
> + if (uaccess)
> + alt->skip_orig = true;
> + else
> + alt->skip_alt = true;
> + }
> +}
> diff --git a/tools/objtool/arch/x86/include/arch_special.h b/tools/objtool/arch/x86/include/arch_special.h
> index 424ce47013e3..fce2b1193194 100644
> --- a/tools/objtool/arch/x86/include/arch_special.h
> +++ b/tools/objtool/arch/x86/include/arch_special.h
> @@ -33,4 +33,13 @@
> #define X86_FEATURE_POPCNT (4 * 32 + 23)
> #define X86_FEATURE_SMAP (9 * 32 + 20)
>
> +static inline bool arch_should_ignore_feature(unsigned short feature)
> +{
> + return feature == X86_FEATURE_POPCNT;
> +}
With my above suggestion you shouldn't need that and just use the arch
specific alternative handling set the alt->skip_orig.
> +
> +static inline bool arch_support_switch_table(void)
> +{
> + return true;
> +}
> #endif /* _X86_ARCH_SPECIAL_H */
> diff --git a/tools/objtool/check.c b/tools/objtool/check.c
> index 30e147391dcb..4af6422d3428 100644
> --- a/tools/objtool/check.c
> +++ b/tools/objtool/check.c
> @@ -729,7 +729,7 @@ static int handle_group_alt(struct objtool_file *file,
> last_orig_insn = insn;
> }
>
> - if (next_insn_same_sec(file, last_orig_insn)) {
> + if (last_orig_insn && next_insn_same_sec(file, last_orig_insn)) {
> fake_jump = malloc(sizeof(*fake_jump));
> if (!fake_jump) {
> WARN("malloc failed");
> @@ -1061,6 +1061,26 @@ static struct rela *find_jump_table(struct objtool_file *file,
> table_rela = find_rela_by_dest(table_sec, table_offset);
> if (!table_rela)
> continue;
> + /*
> + * If we are on arm64 architecture, we now that we
> + * are in presence of a switch table thanks to
> + * the `br <Xn>` insn. but we can't retrieve it yet.
> + * So we just ignore unreachable for this file.
> + */
> + if (!arch_support_switch_table()) {
> + file->ignore_unreachables = true;
> + return NULL;
> + }
> +
> + rodata_rela = find_rela_by_dest(rodata_sec, table_offset);
> + if (rodata_rela) {
> + /*
> + * Use of RIP-relative switch jumps is quite rare, and
> + * indicates a rare GCC quirk/bug which can leave dead
> + * code behind.
> + */
> + if (text_rela->type == R_X86_64_PC32)
> + file->ignore_unreachables = true;
>
> /*
> * Use of RIP-relative switch jumps is quite rare, and
> @@ -1864,7 +1884,7 @@ static int validate_branch(struct objtool_file *file, struct symbol *func,
> insn = first;
> sec = insn->sec;
>
> - if (insn->alt_group && list_empty(&insn->alts)) {
> + if (!insn->visited && insn->alt_group && list_empty(&insn->alts)) {
> WARN_FUNC("don't know how to handle branch to middle of alternative instruction group",
> sec, insn->offset);
> return 1;
> diff --git a/tools/objtool/special.c b/tools/objtool/special.c
> index b8ccee1b5382..7a0092d6e5b3 100644
> --- a/tools/objtool/special.c
> +++ b/tools/objtool/special.c
> @@ -81,7 +81,7 @@ static int get_alt_entry(struct elf *elf, struct special_entry *entry,
> * feature path which is a "very very small percentage of
> * machines".
> */
> - if (feature == X86_FEATURE_POPCNT)
> + if (arch_should_ignore_feature(feature))
> alt->skip_orig = true;
>
> /*
> @@ -93,12 +93,7 @@ static int get_alt_entry(struct elf *elf, struct special_entry *entry,
> * find paths that see the STAC but take the NOP instead of
> * CLAC and the other way around.
> */
> - if (feature == X86_FEATURE_SMAP) {
> - if (uaccess)
> - alt->skip_orig = true;
> - else
> - alt->skip_alt = true;
> - }
> + arch_force_alt_path(feature, uaccess, alt);
> }
>
> orig_rela = find_rela_by_dest(sec, offset + entry->orig);
> diff --git a/tools/objtool/special.h b/tools/objtool/special.h
> index 35061530e46e..90626a7e41cf 100644
> --- a/tools/objtool/special.h
> +++ b/tools/objtool/special.h
> @@ -27,5 +27,8 @@ struct special_alt {
> };
>
> int special_get_alts(struct elf *elf, struct list_head *alts);
> +void arch_force_alt_path(unsigned short feature,
> + bool uaccess,
> + struct special_alt *alt);
>
> #endif /* _SPECIAL_H */
>
CHeers,
--
Julien Thierry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RFC v4 16/18] arm64: crypto: Add exceptions for crypto object to prevent stack analysis
From: Josh Poimboeuf @ 2019-08-22 20:19 UTC (permalink / raw)
To: Raphael Gault
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
linux-kernel, linux-arm-kernel, julien.thierry.kdev
In-Reply-To: <20190816122403.14994-17-raphael.gault@arm.com>
On Fri, Aug 16, 2019 at 01:24:01PM +0100, Raphael Gault wrote:
> Some crypto modules contain `.word` of data in the .text section.
> Since objtool can't make the distinction between data and incorrect
> instruction, it gives a warning about the instruction beeing unknown
> and stops the analysis of the object file.
>
> The exception can be removed if the data are moved to another section
> or if objtool is tweaked to handle this particular case.
>
> Signed-off-by: Raphael Gault <raphael.gault@arm.com>
If the data can be moved to .rodata then I think that would be a much
better solution.
> ---
> arch/arm64/crypto/Makefile | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
> index 0435f2a0610e..e2a25919ebaa 100644
> --- a/arch/arm64/crypto/Makefile
> +++ b/arch/arm64/crypto/Makefile
> @@ -43,9 +43,11 @@ aes-neon-blk-y := aes-glue-neon.o aes-neon.o
>
> obj-$(CONFIG_CRYPTO_SHA256_ARM64) += sha256-arm64.o
> sha256-arm64-y := sha256-glue.o sha256-core.o
> +OBJECT_FILES_NON_STANDARD_sha256-core.o := y
>
> obj-$(CONFIG_CRYPTO_SHA512_ARM64) += sha512-arm64.o
> sha512-arm64-y := sha512-glue.o sha512-core.o
> +OBJECT_FILES_NON_STANDARD_sha512-core.o := y
>
> obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
> chacha-neon-y := chacha-neon-core.o chacha-neon-glue.o
> @@ -58,6 +60,7 @@ aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
>
> obj-$(CONFIG_CRYPTO_AES_ARM64_BS) += aes-neon-bs.o
> aes-neon-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
> +OBJECT_FILES_NON_STANDARD_aes-neonbs-core.o := y
>
> CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
>
> --
> 2.17.1
>
--
Josh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/5] soc: amlogic: Add support for Everything-Else power domains controller
From: Kevin Hilman @ 2019-08-22 20:32 UTC (permalink / raw)
To: Neil Armstrong, ulf.hansson
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <b6cfb770-76eb-00b1-e088-1a73b7978f33@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> On 22/08/2019 01:16, Kevin Hilman wrote:
>> Neil Armstrong <narmstrong@baylibre.com> writes:
>>
>>> Add support for the General Purpose Amlogic Everything-Else Power controller,
>>> with the first support for G12A and SM1 SoCs dedicated to the VPU, PCIe,
>>> USB, NNA, GE2D and Ethernet Power Domains.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> Nice! Thanks for generalizing this.
>>
>> A few comments/concerns below, but this is mostly ready.
[...]
>>> +#define VPU_PD(__name, __resets, __clks, __top_pd, __mem, __get_power) \
>>> + { \
>>> + .name = __name, \
>>> + .reset_names_count = ARRAY_SIZE(__resets), \
>>> + .reset_names = __resets, \
>>> + .clk_names_count = ARRAY_SIZE(__clks), \
>>> + .clk_names = __clks, \
>>> + .top_pd = __top_pd, \
>>> + .mem_pd_count = ARRAY_SIZE(__mem), \
>>> + .mem_pd = __mem, \
>>> + .get_power = __get_power, \
>>> + }
>>> +
>>> +#define TOP_PD(__name, __top_pd, __mem) \
>>> + { \
>>> + .name = __name, \
>>> + .top_pd = __top_pd, \
>>> + .mem_pd_count = ARRAY_SIZE(__mem), \
>>> + .mem_pd = __mem, \
>>> + }
>>
>> Why can't the TOP_PD domains also have a __get_power(). Shouldn't we
>> just be able to check the sleep_reg/sleep_mask like in the VPU case?
>
> It can, I can add it later, do we need it for this version ?
Yes please. Seems a pretty simple addition, let's have it from the
beginning.
>> Also, for readability, I think the arguments to VPU_PD and TOP_PD to
>> have the same order, at least for the common ones. IOW, __name,
>> __top_pd, __mem should be first.
>
> Sure, will fix
and you can add __get_power to the common list too.
[...]
>>> +static int meson_ee_clk_disable(struct meson_ee_pwrc_domain *pwrc_domain)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0 ; i < pwrc_domain->num_clks ; ++i)
>>> + clk_disable(pwrc_domain->clks[i]);
>>> +
>>> + for (i = 0 ; i < pwrc_domain->num_clks ; ++i)
>>> + clk_unprepare(pwrc_domain->clks[i]);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_ee_clk_enable(struct meson_ee_pwrc_domain *pwrc_domain)
>>> +{
>>> + int i, ret;
>>> +
>>> + for (i = 0 ; i < pwrc_domain->num_clks ; ++i) {
>>> + ret = clk_prepare(pwrc_domain->clks[i]);
>>> + if (ret)
>>> + goto fail_prepare;
>>> + }
>>> +
>>> + for (i = 0 ; i < pwrc_domain->num_clks ; ++i) {
>>> + ret = clk_enable(pwrc_domain->clks[i]);
>>> + if (ret)
>>> + goto fail_enable;
>>> + }
>>> +
>>> + return 0;
>>> +fail_enable:
>>> + while (--i)
>>> + clk_disable(pwrc_domain->clks[i]);
>>> +
>>> + /* Unprepare all clocks */
>>> + i = pwrc_domain->num_clks;
>>> +
>>> +fail_prepare:
>>> + while (--i)
>>> + clk_unprepare(pwrc_domain->clks[i]);
>>> +
>>> + return ret;
>>> +}
>>
>> Both the clk enable and disable functions above are just open-coding of
>> the clk_bulk equivalents. Please use clk_bulk_*, then you don't need
>> these helpers. (c.f. the RFT patch I did to convert the old driver to
>> clk_bulk[1])
>
> Yes, but clk_bulk takes _all_ the clocks from the node, you canot specify
> a list of names, maybe it's overengineered but I wanted to specify the
> exact resets and clocks for each power domain, clk_bulk doesn't provide this.
I've been going on the assumption that there's no reason to list clocks
in the pwrc DT node that you don't want managed by the driver. This
also seems to match the exisiting driver, and this new one.
What is the case where you would list clocks in the DT node for the
power-domain, but not want to manage them in the driver?
If there's no good reason to do that, then clk_bulk greatly simplifies
this code.
>>> +static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
>>> +{
>>> + struct meson_ee_pwrc_domain *pwrc_domain =
>>> + container_of(domain, struct meson_ee_pwrc_domain, base);
>>> + int i;
>>> +
>>> + if (pwrc_domain->desc.top_pd)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
>>> + pwrc_domain->desc.top_pd->sleep_reg,
>>> + pwrc_domain->desc.top_pd->sleep_mask,
>>> + pwrc_domain->desc.top_pd->sleep_mask);
>>> + udelay(20);
>>> +
>>> + for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
>>> + pwrc_domain->desc.mem_pd[i].reg,
>>> + pwrc_domain->desc.mem_pd[i].mask,
>>> + pwrc_domain->desc.mem_pd[i].mask);
>>> +
>>> + udelay(20);
>>> +
>>> + if (pwrc_domain->desc.top_pd)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
>>> + pwrc_domain->desc.top_pd->iso_reg,
>>> + pwrc_domain->desc.top_pd->iso_mask,
>>> + pwrc_domain->desc.top_pd->iso_mask);
>>> +
>>> + if (pwrc_domain->num_clks) {
>>> + msleep(20);
>>> + meson_ee_clk_disable(pwrc_domain);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_ee_pwrc_on(struct generic_pm_domain *domain)
>>> +{
>>> + struct meson_ee_pwrc_domain *pwrc_domain =
>>> + container_of(domain, struct meson_ee_pwrc_domain, base);
>>> + int i, ret;
>>> +
>>> + if (pwrc_domain->desc.top_pd)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
>>> + pwrc_domain->desc.top_pd->sleep_reg,
>>> + pwrc_domain->desc.top_pd->sleep_mask, 0);
>>> + udelay(20);
>>> +
>>> + for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
>>> + pwrc_domain->desc.mem_pd[i].reg,
>>> + pwrc_domain->desc.mem_pd[i].mask, 0);
>>> +
>>> + udelay(20);
>>> +
>>> + ret = meson_ee_reset_assert(pwrc_domain);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + if (pwrc_domain->desc.top_pd)
>>> + regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
>>> + pwrc_domain->desc.top_pd->iso_reg,
>>> + pwrc_domain->desc.top_pd->iso_mask, 0);
>>> +
>>> + ret = meson_ee_reset_deassert(pwrc_domain);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return meson_ee_clk_enable(pwrc_domain);
>>> +}
>>> +
>>> +static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
>>> + struct meson_ee_pwrc *sm1_pwrc,
>>> + struct meson_ee_pwrc_domain *dom)
>>> +{
>>> + dom->pwrc = sm1_pwrc;
>>> + dom->num_rstc = dom->desc.reset_names_count;
>>> + dom->num_clks = dom->desc.clk_names_count;
>>> +
>>> + if (dom->num_rstc) {
>>> + int rst;
>>> +
>>> + dom->rstc = devm_kcalloc(&pdev->dev, dom->num_rstc,
>>> + sizeof(struct reset_control *), GFP_KERNEL);
>>> + if (!dom->rstc)
>>> + return -ENOMEM;
>>> +
>>> + for (rst = 0 ; rst < dom->num_rstc ; ++rst) {
>>> + dom->rstc[rst] = devm_reset_control_get_exclusive(
>>> + &pdev->dev,
>>> + dom->desc.reset_names[rst]);
>>> + if (IS_ERR(dom->rstc[rst]))
>>> + return PTR_ERR(dom->rstc[rst]);
>>> + }
>>
>> Why not simplify and use the helpers that get multiple reset lines (like
>> devm_reset_control_array_get() used in meson-gx-pwrc-vpu.c)?
>
> Same comment as clk_bulk, we cannot be sure we select the right reset lines.
Again, what is the case for listing resets in the power-domain node that
you don't want to be managed by the driver?
>> You could also use reset_control_get_count() and compare to the expected
>> number (dom->num_rstc).
>
> This seems oversimplified
Similar to above, if you're always going to manage all the reset lines
in the DT node, then simple is good.
If there are reasons to list reset lines in the DT node that will not be
managed by the driver, I'm defintiely curious why.
If not, using the reset API helpers is much more readable and
maintainble IMO.
>>
>>> + }
>>> +
>>> + if (dom->num_clks) {
>>> + int clk;
>>> +
>>> + dom->clks = devm_kcalloc(&pdev->dev, dom->num_clks,
>>> + sizeof(struct clk *), GFP_KERNEL);
>>> + if (!dom->clks)
>>> + return -ENOMEM;
>>> +
>>> + for (clk = 0 ; clk < dom->num_clks ; ++clk) {
>>> + dom->clks[clk] = devm_clk_get(&pdev->dev,
>>> + dom->desc.clk_names[clk]);
>>> + if (IS_ERR(dom->clks[clk]))
>>> + return PTR_ERR(dom->clks[clk]);
>>> + }
>>> + }
>>
>> Please use clk_bulk API, and then just double-check that the number of
>> clocks found matches the expected number.
>
> Same, I'll either take all the clks and resets for the vpu power domain,
> or keep this code to make sure we get the right clocks and resets.
Similar to above. IMO, we should be sure to put the "right clocks and
resets" into the DT, and then simplify the code.
>>
>>> + dom->base.name = dom->desc.name;
>>> + dom->base.power_on = meson_ee_pwrc_on;
>>> + dom->base.power_off = meson_ee_pwrc_off;
>>> +
>>> + if (dom->desc.get_power) {
>>> + bool powered_off = dom->desc.get_power(dom);
>>
>> nit: insert blank line here
>>
>> More importantly, we defintely will have problem here in the
>> !powered_off case. TL;DR; the driver's state does not match the actual
>> hardware state.
>>
>> When powered_off = false, you're telling the genpd core that this domain
>> is already turned on. However, you haven't called _pwrc_on() yet for
>> the domain, which means internal state of the driver for this domain
>> (e.g. clock enables, resets, etc.) is not in sync with the HW. On
>> SEI610 this case is happending for the VPU, which seems to be enabled by
>> u-boot, so this driver detects it as already on, which is fine. But...
>>
>> Remember that the ->power_off() function will be called during suspend,
>> and will lead to the clk unprepare/disable calls. However, for domains
>> that are detected as on (!powered_off), clk prepare/enable will never
>> have been called, so that when suspend happens, you'll get "already
>> unprepared" errors from the clock core
>>
>> IOW, I think you need something like this here:
>>
>> if (!powered_off)
>> meson_ee_pwrc_on(&dom->base);
>>
>> so that the internal state of clock fwk etc. matches the detected state
>> of the HW. The problem with that simple fix, at least for the VPU is
>> that it might cause us to lose any existing display or framebuffer
>> console that's on-going. Probably needs some testing.
>
> Yes, I forgot to take the _shutdown() function from gx_pwrc_vpu driver :
>
> 349 static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
> 350 {
> 351 struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
> 352 bool powered_off;
> 353
> 354 powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
> 355 if (!powered_off)
> 356 vpu_pd->genpd.power_off(&vpu_pd->genpd);
> 357 }
OK, yeah, I hadn't noticed that in the original driver. I tested
something simliar with suspend/resume on SEI610 and it gets rid of the
"already unprepared" splats from the clock core.
>>
>> Anyways, to see what I mean, try suspend/resume (you can test this
>> series on my integ branch with "rtcwake -d rtc0 -m mem -s4") and you'll
>> see error splats from the clock core during suspend.
>>
>>
>>
>>> + pm_genpd_init(&dom->base, &pm_domain_always_on_gov,
>>> + powered_off);
>>
>>> + } else
>>> + pm_genpd_init(&dom->base, NULL, true);
>>
>> nit: the else clause should also have {} to match the if
>> (c.f. CodingStyle)
>
> OK
>
>>
>> Why do you force the always-on governor in the case where ->get_power()
>> exists, but not the other?
>>
>> If you force that, then for any devices connected to these domains that
>> use runtime PM, they will never turn off the domain when it's idle.
>> IOW, these domains will only ever be turned off on system-wide
>> suspend/resume.
>>
>> IMO, unless there's a good reason not to, you should pass NULL for the
>> governor.
>
> It's for legacy when VPU is initialized from vendor U-Boot, look at commit :
> 339cd0ea082287ea8e2b7e7159a5a33665a2cbe3 "soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader"
>
> In the case the VPU power domain has been powered on by the bootloader
> and no driver are attached to this power domain, the genpd will power it
> off after a certain amount of time, but the clocks hasn't been enabled
> by the kernel itself and the power-off will trigger some faults.
> This patch enable the clocks to have a coherent state for an eventual
> poweroff and switches to the pm_domain_always_on_gov governor.
The key phrase there being "and no driver is attached". Now that we
have a driver, it claims this domain so I don't think it will be
powered off:
# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
ETH on
/devices/platform/soc/ff3f0000.ethernet unsupported
AUDIO off-0
GE2D off-0
PCI off-0
USB on
/devices/platform/soc/ffe09000.usb active
NNA off-0
VPU on
/devices/platform/soc/ff900000.vpu unsupported
In my tests with a framebuffer console (over HDMI), I don't see the
display being powered off.
> I could set always-on governor only if the domain was already enabled,
> what do you think ?
I don't think that's necessary now that we have a driver. We really
want to be able to power-down this domain when the display is not in
use, and if you use always_on, that will never happen.
> And seems I'm also missing the "This patch enable the clocks".
I'm not sure what patch you're referring to.
Kevin
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* Re: [RFC v4 07/18] objtool: Introduce INSN_UNKNOWN type
From: Julien @ 2019-08-22 20:45 UTC (permalink / raw)
To: Josh Poimboeuf, Raphael Gault
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
linux-kernel, linux-arm-kernel
In-Reply-To: <20190822200406.jc3yf77pomxxwep6@treble>
Hi Josh,
On 22/08/19 21:04, Josh Poimboeuf wrote:
> On Fri, Aug 16, 2019 at 01:23:52PM +0100, Raphael Gault wrote:
>> On arm64 some object files contain data stored in the .text section.
>> This data is interpreted by objtool as instruction but can't be
>> identified as a valid one. In order to keep analysing those files we
>> introduce INSN_UNKNOWN type. The "unknown instruction" warning will thus
>> only be raised if such instructions are uncountered while validating an
>> execution branch.
>>
>> This change doesn't impact the x86 decoding logic since 0 is still used
>> as a way to specify an unknown type, raising the "unknown instruction"
>> warning during the decoding phase still.
>>
>> Signed-off-by: Raphael Gault <raphael.gault@arm.com>
>
> Is there a reason such data can't be moved to .rodata? That would seem
> like the proper fix.
>
Raphaël can confirm, if I remember correctly, that issue was encountered
on assembly files implementing crypto algorithms were some
words/double-words of data were in the middle of the .text. I think it
is done this way to make sure the data can be loaded in a single
instruction. So moving it to another section could impact the crypto
performance depending on the relocations.
That was my understanding at least.
Cheers,
--
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* Re: [PATCH 1/6] dt-bindings: clk: meson: add sm1 periph clock controller bindings
From: Kevin Hilman @ 2019-08-22 20:49 UTC (permalink / raw)
To: Neil Armstrong, jbrunet, devicetree
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-2-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> Update the documentation to support clock driver for the Amlogic SM1 SoC.
>
> SM1 clock tree is very close, the main differences are :
> - each CPU core can achieve a different frequency, albeit a common PLL
> - a similar tree as the clock tree has been added for the DynamIQ Shared Unit
> - has a new GP1 PLL used for the DynamIQ Shared Unit
> - SM1 has additional clocks like for CSI, NanoQ an other components
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
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* Re: [PATCH 6/6] arm64: dts: meson-sm1-sei610: enable DVFS
From: Kevin Hilman @ 2019-08-22 20:49 UTC (permalink / raw)
To: Neil Armstrong, jbrunet
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190822142455.12506-7-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> This enables DVFS for the Amlogic SM1 based SEI610 board by:
> - Adding the SM1 SoC OPPs taken from the vendor tree
> - Selecting the SM1 Clock controller instead of the G12A one
> - Adding the CPU rail regulator, PWM and OPPs for each CPU nodes.
>
> Each power supply can achieve 0.69V to 1.05V using a single PWM
> output clocked at 666KHz with an inverse duty-cycle.
>
> DVFS has been tested by running the arm64 cpuburn at [1] and cycling
> between all the possible cpufreq translations of each cluster and
> checking the final frequency using the clock-measurer, script at [2].
>
> [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
> [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Tested on meson-sm1-sei610 board using the userspace govenor to manually
walk through the available frequencies.
I'll queue this up when there's a stable clock tag I can use for patch
5/6.
Kevin
> ---
> .../boot/dts/amlogic/meson-sm1-sei610.dts | 59 ++++++++++++++--
> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++++++++++++++++++
> 2 files changed, 124 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> index 36ac2e4b970d..69966e2e0611 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
> @@ -19,10 +19,6 @@
> ethernet0 = ðmac;
> };
>
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -
> emmc_pwrseq: emmc-pwrseq {
> compatible = "mmc-pwrseq-emmc";
> reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
> @@ -136,6 +132,25 @@
> regulator-always-on;
> };
>
> + vddcpu: regulator-vddcpu {
> + /*
> + * SY8120B1ABC DC/DC Regulator.
> + */
> + compatible = "pwm-regulator";
> +
> + regulator-name = "VDDCPU";
> + regulator-min-microvolt = <690000>;
> + regulator-max-microvolt = <1050000>;
> +
> + vin-supply = <&dc_in>;
> +
> + pwms = <&pwm_AO_cd 1 1500 0>;
> + pwm-dutycycle-range = <100 0>;
> +
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> vddio_ao1v8: regulator-vddio_ao1v8 {
> compatible = "regulator-fixed";
> regulator-name = "VDDIO_AO1V8";
> @@ -182,6 +197,34 @@
> hdmi-phandle = <&hdmi_tx>;
> };
>
> +&cpu0 {
> + cpu-supply = <&vddcpu>;
> + operating-points-v2 = <&cpu_opp_table>;
> + clocks = <&clkc CLKID_CPU_CLK>;
> + clock-latency = <50000>;
> +};
> +
> +&cpu1 {
> + cpu-supply = <&vddcpu>;
> + operating-points-v2 = <&cpu_opp_table>;
> + clocks = <&clkc CLKID_CPU1_CLK>;
> + clock-latency = <50000>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&vddcpu>;
> + operating-points-v2 = <&cpu_opp_table>;
> + clocks = <&clkc CLKID_CPU2_CLK>;
> + clock-latency = <50000>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&vddcpu>;
> + operating-points-v2 = <&cpu_opp_table>;
> + clocks = <&clkc CLKID_CPU3_CLK>;
> + clock-latency = <50000>;
> +};
> +
> ðmac {
> status = "okay";
> phy-handle = <&internal_ephy>;
> @@ -220,6 +263,14 @@
> clock-names = "clkin0";
> };
>
> +&pwm_AO_cd {
> + pinctrl-0 = <&pwm_ao_d_e_pins>;
> + pinctrl-names = "default";
> + clocks = <&xtal>;
> + clock-names = "clkin1";
> + status = "okay";
> +};
> +
> &pwm_ef {
> status = "okay";
> pinctrl-0 = <&pwm_e_pins>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> index 37064d7f66c1..2b61406b0610 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> @@ -50,6 +50,71 @@
> compatible = "cache";
> };
> };
> +
> + cpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <730000>;
> + };
> +
> + opp-250000000 {
> + opp-hz = /bits/ 64 <250000000>;
> + opp-microvolt = <730000>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <730000>;
> + };
> +
> + opp-667000000 {
> + opp-hz = /bits/ 64 <666666666>;
> + opp-microvolt = <750000>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <770000>;
> + };
> +
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <780000>;
> + };
> +
> + opp-1404000000 {
> + opp-hz = /bits/ 64 <1404000000>;
> + opp-microvolt = <790000>;
> + };
> +
> + opp-1512000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + opp-microvolt = <800000>;
> + };
> +
> + opp-1608000000 {
> + opp-hz = /bits/ 64 <1608000000>;
> + opp-microvolt = <810000>;
> + };
> +
> + opp-1704000000 {
> + opp-hz = /bits/ 64 <1704000000>;
> + opp-microvolt = <850000>;
> + };
> +
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <900000>;
> + };
> +
> + opp-1908000000 {
> + opp-hz = /bits/ 64 <1908000000>;
> + opp-microvolt = <950000>;
> + };
> + };
> };
>
> &cecb_AO {
> @@ -60,6 +125,10 @@
> compatible = "amlogic,meson-sm1-clk-measure";
> };
>
> +&clkc {
> + compatible = "amlogic,sm1-clkc";
> +};
> +
> ðmac {
> power-domains = <&pwrc PWRC_SM1_ETH_ID>;
> };
> --
> 2.22.0
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^ permalink raw reply
* Re: [PATCH v3 0/2] rtc: add new Amlogic Virtual Wake RTC
From: Kevin Hilman @ 2019-08-22 20:52 UTC (permalink / raw)
To: Kevin Hilman, Alexandre Belloni, linux-rtc
Cc: linux-amlogic, devicetree, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190812232850.8016-1-khilman@kernel.org>
Kevin Hilman <khilman@kernel.org> writes:
> From: Kevin Hilman <khilman@baylibre.com>
>
> Add a new driver for the virtual wake RTC on Amlogic SoCs.
>
> The RTC is virtual from the Linux side because it's a hardware timer
> managed by firmware on the secure co-processor (SCP.) The interface
> is 1 register where a wakeup time (in seconds) is written. The SCP then
> uses this value to program an always-on timer.
Just FYI... this was originally tested on G12A and G12B SoCs, but has
now also been tested to work unmodified on the new SM1 SoC as well.
Kevin
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* Re: [PATCH v3 1/2] dt-bindings: rtc: new binding for Amlogic VRTC
From: Alexandre Belloni @ 2019-08-22 21:11 UTC (permalink / raw)
To: Kevin Hilman
Cc: linux-rtc, linux-amlogic, devicetree, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190812232850.8016-2-khilman@kernel.org>
On 12/08/2019 16:28:49-0700, Kevin Hilman wrote:
> From: Kevin Hilman <khilman@baylibre.com>
>
> Add binding fo the new VRTC driver for Amlogic SoCs. The 64-bit
> family of SoCs only has an RTC managed by firmware, and this VRTC
> driver provides the simple, one-register firmware interface.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> .../bindings/rtc/rtc-meson-vrtc.txt | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/rtc-meson-vrtc.txt
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* Re: [PATCH v3 2/2] rtc: Add Amlogic Virtual Wake RTC
From: Alexandre Belloni @ 2019-08-22 21:11 UTC (permalink / raw)
To: Kevin Hilman
Cc: linux-rtc, linux-amlogic, devicetree, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190812232850.8016-3-khilman@kernel.org>
On 12/08/2019 16:28:50-0700, Kevin Hilman wrote:
> From: Neil Armstrong <narmstrong@baylibre.com>
>
> The Amlogic Meson GX SoCs uses a special register to store the
> time in seconds to wakeup after a system suspend.
>
> In order to be able to reuse the RTC wakealarm feature, this
> driver implements a fake RTC device which uses the system time
> to deduce a suspend delay.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> [khilman: rebase to v5.3-rc, rework and modernization]
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> MAINTAINERS | 1 +
> drivers/rtc/Kconfig | 11 +++
> drivers/rtc/Makefile | 1 +
> drivers/rtc/rtc-meson-vrtc.c | 156 +++++++++++++++++++++++++++++++++++
> 4 files changed, 169 insertions(+)
> create mode 100644 drivers/rtc/rtc-meson-vrtc.c
>
Applied, thanks.
--
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* Re: [PATCH net-next v2 2/3] net: ethernet: mediatek: Re-add support SGMII
From: Russell King - ARM Linux admin @ 2019-08-22 21:11 UTC (permalink / raw)
To: René van Dorst
Cc: Nelson Chang, Frank Wunderlich, netdev, Sean Wang, linux-mips,
linux-mediatek, John Crispin, Matthias Brugger, Stefan Roese,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190822195033.Horde.hEW8FBGNfFrugQOCv0gaDfx@www.vdorst.com>
Hi Rene,
On Thu, Aug 22, 2019 at 07:50:33PM +0000, René van Dorst wrote:
> Quoting Russell King - ARM Linux admin <linux@armlinux.org.uk>:
> > Isn't this set for Cisco SGMII as well as for 802.3 1000BASE-X and
> > the up-clocked 2500BASE-X modes?
> >
> > If so, is there a reason why 10Mbps and 100Mbps speeds aren't
> > supported on Cisco SGMII links?
>
> I can only tell a bit about the mt7622 SOC, datasheet tells me that:
>
> The SGMII is the interface between 10/100/1000/2500 Mbps PHY and Ethernet MAC,
> the spec is raised by Cisco in 1999, which is aims for pin reduction compare
> with the GMII. It uses 2 differential data pair for TX and RX with clock
> embedded bit stream to convey frame data and port ability information.
> The core leverages the 1000Base-X PCS and Auto-Negotiation from IEEE 802.3
> specification (clause 36/37). This IP can support up to 3.125G baud for
> 2.5Gbps
> (proprietary 2500Base-X) data rate of MAC by overclocking.
>
> Also features tells me: Support 10/100/1000/2500 Mbps in full duplex mode and
> 10/100 Mbps in half duplex mode.
Yep, that is what I'd expect. Thanks.
--
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* Re: [PATCH v2 1/3] dt-bindings: Add compatible for H6 RTC
From: Alexandre Belloni @ 2019-08-22 21:15 UTC (permalink / raw)
To: megous
Cc: Mark Rutland, Alessandro Zummo, devicetree, Maxime Ripard,
linux-sunxi, linux-kernel, Chen-Yu Tsai, Rob Herring,
linux-arm-kernel, linux-rtc
In-Reply-To: <20190820151934.3860-2-megous@megous.com>
On 20/08/2019 17:19:32+0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> RTC on H6 is similar to the one on H5 SoC, but incompatible in small
> details. See the driver for description of differences. For example
> H6 RTC needs to enable the external low speed oscillator. Add new
> compatible for this RTC.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
> .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
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* Re: [PATCH v2 2/3] rtc: sun6i: Add support for H6 RTC
From: Alexandre Belloni @ 2019-08-22 21:16 UTC (permalink / raw)
To: megous
Cc: Mark Rutland, Alessandro Zummo, devicetree, Maxime Ripard,
linux-sunxi, linux-kernel, Chen-Yu Tsai, Rob Herring,
linux-arm-kernel, linux-rtc
In-Reply-To: <20190820151934.3860-3-megous@megous.com>
On 20/08/2019 17:19:33+0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> mostly in features that are not yet supported by this driver.
>
> Some differences are already stated in the comments in existing code.
> One other difference is that H6 has extra bit in LOSC_CTRL_REG, called
> EXT_LOSC_EN to enable/disable external low speed crystal oscillator.
>
> It also has bit EXT_LOSC_STA in LOSC_AUTO_SWT_STA_REG, to check whether
> external low speed oscillator is working correctly.
>
> This patch adds support for enabling LOSC when necessary:
>
> - during reparenting
> - when probing the clock
>
> H6 also has capacbility to automatically reparent RTC clock from
> external crystal oscillator, to internal RC oscillator, if external
> oscillator fails. This is enabled by default. Disable it during
> probe.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> ---
> drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 38 insertions(+), 2 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* page_alloc.shuffle=1 + CONFIG_PROVE_LOCKING=y = arm64 hang
From: Qian Cai @ 2019-08-22 21:33 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Peter Zijlstra, linux-mm, Dan Williams, linux-kernel,
linux-arm-kernel
https://raw.githubusercontent.com/cailca/linux-mm/master/arm64.config
Booting an arm64 ThunderX2 server with page_alloc.shuffle=1 [1] +
CONFIG_PROVE_LOCKING=y results in hanging.
[1] https://lore.kernel.org/linux-mm/154899811208.3165233.17623209031065121886.s
tgit@dwillia2-desk3.amr.corp.intel.com/
...
[ 125.142689][ T1] arm-smmu-v3 arm-smmu-v3.2.auto: option mask 0x2
[ 125.149687][ T1] arm-smmu-v3 arm-smmu-v3.2.auto: ias 44-bit, oas 44-bit
(features 0x0000170d)
[ 125.165198][ T1] arm-smmu-v3 arm-smmu-v3.2.auto: allocated 524288 entries
for cmdq
[ 125.239425][ [ 125.251484][ T1] arm-smmu-v3 arm-smmu-v3.3.auto: option
mask 0x2
[ 125.258233][ T1] arm-smmu-v3 arm-smmu-v3.3.auto: ias 44-bit, oas 44-bit
(features 0x0000170d)
[ 125.282750][ T1] arm-smmu-v3 arm-smmu-v3.3.auto: allocated 524288 entries
for cmdq
[ 125.320097][ T1] arm-smmu-v3 arm-smmu-v3.3.auto: allocated 524288 entries
for evtq
[ 125.332667][ T1] arm-smmu-v3 arm-smmu-v3.4.auto: option mask 0x2
[ 125.339427][ T1] arm-smmu-v3 arm-smmu-v3.4.auto: ias 44-bit, oas 44-bit
(features 0x0000170d)
[ 125.354846][ T1] arm-smmu-v3 arm-smmu-v3.4.auto: allocated 524288 entries
for cmdq
[ 125.375295][ T1] arm-smmu-v3 arm-smmu-v3.4.auto: allocated 524288 entries
for evtq
[ 125.387371][ T1] arm-smmu-v3 arm-smmu-v3.5.auto: option mask 0x2
[ 125.393955][ T1] arm-smmu-v3 arm-smmu-v3.5.auto: ias 44-bit, oas 44-bit
(features 0x0000170d)
[ 125.522605][ T1] arm-smmu-v3 arm-smmu-v3.5.auto: allocated 524288 entries
for cmdq
[ 125.543338][ T1] arm-smmu-v3 arm-smmu-v3.5.auto: allocated 524288 entries
for evtq
[ 126.694742][ T1] EFI Variables Facility v0.08 2004-May-17
[ 126.799291][ T1] NET: Registered protocol family 17
[ 126.978632][ T1] zswap: loaded using pool lzo/zbud
[ 126.989168][ T1] kmemleak: Kernel memory leak detector initialized
[ 126.989191][ T1577] kmemleak: Automatic memory scanning thread started
[ 127.044079][ T1335] pcieport 0000:0f:00.0: Adding to iommu group 0
[ 127.388074][ T1] Freeing unused kernel memory: 22528K
[ 133.527005][ T1] Checked W+X mappings: passed, no W+X pages found
[ 133.533474][ T1] Run /init as init process
[ 133.727196][ T1] systemd[1]: System time before build time, advancing
clock.
[ 134.576021][ T1587] modprobe (1587) used greatest stack depth: 27056 bytes
left
[ 134.764026][ T1] systemd[1]: systemd 239 running in system mode. (+PAM
+AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT
+GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-
hierarchy=legacy)
[ 134.799044][ T1] systemd[1]: Detected architecture arm64.
[ 134.804818][ T1] systemd[1]: Running in initial RAM disk.
<...hang...>
Fix it by either set page_alloc.shuffle=0 or CONFIG_PROVE_LOCKING=n which allow
it to continue successfully.
[ 121.093846][ T1] systemd[1]: Set hostname to <hpe-apollo-cn99xx>.
[ 123.157524][ T1] random: systemd: uninitialized urandom read (16 bytes
read)
[ 123.168562][ T1] systemd[1]: Listening on Journal Socket.
[ OK ] Listening on Journal Socket.
[ 123.203932][ T1] random: systemd: uninitialized urandom read (16 bytes
read)
[ 123.212813][ T1] systemd[1]: Listening on udev Kernel Socket.
[ OK ] Listening on udev Kernel Socket.
...
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^ permalink raw reply
* [PATCH] ARM: dts: pbab01: correct rtc vendor
From: Alexandre Belloni @ 2019-08-22 21:35 UTC (permalink / raw)
To: Shawn Guo
Cc: Alexandre Belloni, linux-kernel, NXP Linux Team, kernel,
Fabio Estevam, linux-arm-kernel
The rtc8564 is made by Epson but is similar to the NXP pcf8563. Use the
correct vendor name.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 82802f8ce7a0..d434868e870a 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -128,7 +128,7 @@
};
rtc@51 {
- compatible = "nxp,rtc8564";
+ compatible = "epson,rtc8564";
reg = <0x51>;
};
--
2.21.0
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^ permalink raw reply related
* Re: [RFC v4 07/18] objtool: Introduce INSN_UNKNOWN type
From: Josh Poimboeuf @ 2019-08-22 21:51 UTC (permalink / raw)
To: Julien
Cc: raph.gault+kdev, peterz, catalin.marinas, will.deacon,
linux-kernel, Raphael Gault, linux-arm-kernel
In-Reply-To: <3c4e3227-eeb3-371a-d015-a0e0e60e5332@gmail.com>
On Thu, Aug 22, 2019 at 09:45:00PM +0100, Julien wrote:
> Hi Josh,
>
> On 22/08/19 21:04, Josh Poimboeuf wrote:
> > On Fri, Aug 16, 2019 at 01:23:52PM +0100, Raphael Gault wrote:
> > > On arm64 some object files contain data stored in the .text section.
> > > This data is interpreted by objtool as instruction but can't be
> > > identified as a valid one. In order to keep analysing those files we
> > > introduce INSN_UNKNOWN type. The "unknown instruction" warning will thus
> > > only be raised if such instructions are uncountered while validating an
> > > execution branch.
> > >
> > > This change doesn't impact the x86 decoding logic since 0 is still used
> > > as a way to specify an unknown type, raising the "unknown instruction"
> > > warning during the decoding phase still.
> > >
> > > Signed-off-by: Raphael Gault <raphael.gault@arm.com>
> >
> > Is there a reason such data can't be moved to .rodata? That would seem
> > like the proper fix.
> >
>
> Raphaël can confirm, if I remember correctly, that issue was encountered on
> assembly files implementing crypto algorithms were some words/double-words
> of data were in the middle of the .text. I think it is done this way to make
> sure the data can be loaded in a single instruction. So moving it to another
> section could impact the crypto performance depending on the relocations.
>
> That was my understanding at least.
Thanks. If that's the case then that would be useful information to put
in the patch description. A code excerpt of an example code site would
be useful too.
I'm not sure INSN_UNKNOWN is the right name though, since the decoder
does actually know about it. Maybe INSN_DATA or something?
--
Josh
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^ permalink raw reply
* [PATCH 1/2] coresight: tmc: Make memory width mask computation into a function
From: Mathieu Poirier @ 2019-08-22 22:09 UTC (permalink / raw)
To: yabinc, suzuki.poulose, leo.yan
Cc: alexander.shishkin, linux-arm-kernel, mike.leach, linux-kernel
In-Reply-To: <20190822220915.8876-1-mathieu.poirier@linaro.org>
Make the computation of a memory ask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etf.c | 23 ++-------------
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 23b7ff00af5c..807416b75ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
* traces.
*/
if (!buf->snapshot && to_read > handle->size) {
- u32 mask = 0;
-
- /*
- * The value written to RRP must be byte-address aligned to
- * the width of the trace memory databus _and_ to a frame
- * boundary (16 byte), whichever is the biggest. For example,
- * for 32-bit, 64-bit and 128-bit wide trace memory, the four
- * LSBs must be 0s. For 256-bit wide trace memory, the five
- * LSBs must be 0s.
- */
- switch (drvdata->memwidth) {
- case TMC_MEM_INTF_WIDTH_32BITS:
- case TMC_MEM_INTF_WIDTH_64BITS:
- case TMC_MEM_INTF_WIDTH_128BITS:
- mask = GENMASK(31, 4);
- break;
- case TMC_MEM_INTF_WIDTH_256BITS:
- mask = GENMASK(31, 5);
- break;
- }
+ u32 mask = tmc_get_memwidth_mask(drvdata);
/*
* Make sure the new size is aligned in accordance with the
- * requirement explained above.
+ * requirement explained in function tmc_get_memwidth_mask().
*/
to_read = handle->size & mask;
/* Move the RAM read pointer up */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3055bf8e2236..1cf82fa58289 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
+{
+ u32 mask = 0;
+
+ /*
+ * When moving RRP or an offset address forward, the new values must
+ * be byte-address aligned to the width of the trace memory databus
+ * _and_ to a frame boundary (16 byte), whichever is the biggest. For
+ * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
+ * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
+ * be 0s.
+ */
+ switch (drvdata->memwidth) {
+ case TMC_MEM_INTF_WIDTH_32BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_64BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_128BITS:
+ mask = GENMASK(31, 4);
+ break;
+ case TMC_MEM_INTF_WIDTH_256BITS:
+ mask = GENMASK(31, 5);
+ break;
+ }
+
+ return mask;
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 9dbcdf453e22..71de978575f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
--
2.17.1
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^ permalink raw reply related
* [PATCH 0/2] coresight: Add barrier packet when moving offset forward
From: Mathieu Poirier @ 2019-08-22 22:09 UTC (permalink / raw)
To: yabinc, suzuki.poulose, leo.yan
Cc: alexander.shishkin, linux-arm-kernel, mike.leach, linux-kernel
Hi Yabin,
When doing more tests on your patch that adjust the offset to fit the
available space in the perf ring buffer[1], I noticed the decoder wasn't
able to decode the traces that had been collected. The issue was observed
in CPU wide scenarios but I also suspect they would have showed up in
per-thread mode given the right conditions.
I traced the problem to the moving forward of the offset in the trace
buffer. Doing so skips over the barrier packets originally inserted in
function tmc_sync_etr_buf(), which in turn prevents the decoder from
properly synchronising with the trace packets.
I fixed the condition by inserting barrier packets once the offset has been
moved forward, making sure that alignment rules are respected.
I'd be grateful if you could review and test my changes to make sure things
still work on your side.
Applies cleanly on the coresight next branch.
Best regards,
Mathieu
[1]. https://lkml.org/lkml/2019/8/14/1336
Mathieu Poirier (2):
coresight: tmc: Make memory width mask computation into a function
coresight: tmc-etr: Add barrier packet when moving offset forward
.../hwtracing/coresight/coresight-tmc-etf.c | 23 +---------
.../hwtracing/coresight/coresight-tmc-etr.c | 43 ++++++++++++++-----
drivers/hwtracing/coresight/coresight-tmc.c | 28 ++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
4 files changed, 64 insertions(+), 31 deletions(-)
--
2.17.1
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^ permalink raw reply
* [PATCH 2/2] coresight: tmc-etr: Add barrier packet when moving offset forward
From: Mathieu Poirier @ 2019-08-22 22:09 UTC (permalink / raw)
To: yabinc, suzuki.poulose, leo.yan
Cc: alexander.shishkin, linux-arm-kernel, mike.leach, linux-kernel
In-Reply-To: <20190822220915.8876-1-mathieu.poirier@linaro.org>
This patch adds barrier packets in the trace stream when the offset in the
data buffer needs to be moved forward. Otherwise the decoder isn't aware
of the break in the stream and can't synchronise itself with the trace
data.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 43 ++++++++++++++-----
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4f000a03152e..0e4cd6ec5f28 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
etr_buf->ops->sync(etr_buf, rrp, rwp);
-
- /* Insert barrier packets at the beginning, if there was an overflow */
- if (etr_buf->full)
- tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
@@ -1415,10 +1411,11 @@ static void tmc_free_etr_buffer(void *config)
* buffer to the perf ring buffer.
*/
static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long src_offset,
unsigned long to_copy)
{
long bytes;
- long pg_idx, pg_offset, src_offset;
+ long pg_idx, pg_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1427,7 +1424,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1475,7 +1471,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
void *config)
{
bool lost = false;
- unsigned long flags, size = 0;
+ unsigned long flags, offset, size = 0;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etr_perf_buffer *etr_perf = config;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1503,11 +1499,39 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
size = etr_buf->len;
+ offset = etr_buf->offset;
+ lost |= etr_buf->full;
+
+ /*
+ * The ETR buffer may be bigger than the space available in the
+ * perf ring buffer (handle->size). If so advance the offset so that we
+ * get the latest trace data. In snapshot mode none of that matters
+ * since we are expected to clobber stale data in favour of the latest
+ * traces.
+ */
if (!etr_perf->snapshot && size > handle->size) {
- size = handle->size;
+ u32 mask = tmc_get_memwidth_mask(drvdata);
+
+ /*
+ * Make sure the new size is aligned in accordance with the
+ * requirement explained in function tmc_get_memwidth_mask().
+ */
+ size = handle->size & mask;
+ offset = etr_buf->offset + etr_buf->len - size;
+
+ if (offset >= etr_buf->size)
+ offset -= etr_buf->size;
lost = true;
}
- tmc_etr_sync_perf_buffer(etr_perf, size);
+
+ /*
+ * Insert barrier packets at the beginning, if there was an overflow
+ * or if the offset had to be brought forward.
+ */
+ if (lost)
+ tmc_etr_buf_insert_barrier_packet(etr_buf, offset);
+
+ tmc_etr_sync_perf_buffer(etr_perf, offset, size);
/*
* In snapshot mode we simply increment the head by the number of byte
@@ -1518,7 +1542,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
if (etr_perf->snapshot)
handle->head += size;
- lost |= etr_buf->full;
out:
/*
* Don't set the TRUNCATED flag in snapshot mode because 1) the
--
2.17.1
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^ permalink raw reply related
* Re: [PATCH v2 00/14] arm64: dts: meson: fixes following YAML bindings schemas conversion
From: Kevin Hilman @ 2019-08-22 22:26 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-amlogic, Neil Armstrong, linux-kernel, linux-arm-kernel,
devicetree
In-Reply-To: <20190821142043.14649-1-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> This is the first set of DT fixes following the first YAML bindings conversion
> at [1], [2] and [3].
>
> After this set of fixes, the remaining errors are :
> meson-axg-s400.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks'
> meson-g12a-sei510.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks'
> meson-g12b-odroid-n2.dt.yaml: usb-hub: gpios:0:0: 20 is not valid under any of the given schemas
> meson-g12b-odroid-n2.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks'
> meson-g12a-x96-max.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks'
>
> These are only cosmetic changes, and should not break drivers implementation
> following the bindings.
Any chance you can rebase this on top of my v5.4/dt64 branch?
Thanks,
Kevin
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^ permalink raw reply
* Re: [PATCH net-next v4 0/2] dt-bindings: net: meson-dwmac: convert to yaml
From: David Miller @ 2019-08-22 22:42 UTC (permalink / raw)
To: narmstrong
Cc: devicetree, martin.blumenstingl, netdev, linux-kernel, robh+dt,
linux-amlogic, linux-arm-kernel
In-Reply-To: <20190820075742.14857-1-narmstrong@baylibre.com>
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Tue, 20 Aug 2019 09:57:40 +0200
> This patchsets converts the Amlogic Meson DWMAC glue bindings over to
> YAML schemas using the already converted dwmac bindings.
>
> The first patch is needed because the Amlogic glue needs a supplementary
> reg cell to access the DWMAC glue registers.
>
> Changes since v3:
> - Specified net-next target tree
>
> Changes since v2:
> - Added review tags
> - Updated allwinner,sun7i-a20-gmac.yaml reg maxItems
Series applied, thanks.
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^ permalink raw reply
* Re: [PATCH net-next v2 0/3] net: dsa: mt7530: Convert to PHYLINK and add support for port 5
From: David Miller @ 2019-08-22 23:20 UTC (permalink / raw)
To: opensource
Cc: andrew, f.fainelli, frank-w, netdev, sean.wang, linux-mips,
linux-mediatek, john, matthias.bgg, vivien.didelot,
linux-arm-kernel
In-Reply-To: <20190821144547.15113-1-opensource@vdorst.com>
From: René van Dorst <opensource@vdorst.com>
Date: Wed, 21 Aug 2019 16:45:44 +0200
> 1. net: dsa: mt7530: Convert to PHYLINK API
> This patch converts mt7530 to PHYLINK API.
> 2. dt-bindings: net: dsa: mt7530: Add support for port 5
> 3. net: dsa: mt7530: Add support for port 5
> These 2 patches adding support for port 5 of the switch.
>
> v1->v2:
> * Mostly phylink improvements after review.
> rfc -> v1:
> * Mostly phylink improvements after review.
> * Drop phy isolation patches. Adds no value for now.
This definitely needs some review before I'll apply it.
Thanks.
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^ permalink raw reply
* Re: [PATCH] ethernet: Delete unnecessary checks before the macro call “dev_kfree_skb”
From: David Miller @ 2019-08-22 23:23 UTC (permalink / raw)
To: Markus.Elfring
Cc: kstewart, michael.heimpold, kernel-janitors, wsa+renesas,
weiyongjun1, opensource, linux-stm32, stefan.wahren, opendmb,
yuehaibing, joabreu, intel-wired-lan, linux-arm-kernel,
bcm-kernel-feedback-list, ynezz, bryan.whitehead,
jeffrey.t.kirsher, alexandre.torgue, jonathan.lemon, yang.wei9,
alexios.zavras, claudiu.manoil, f.fainelli, swinslow,
shannon.nelson, peppe.cavallaro, tglx, zhongjiang, allison, nico,
gregkh, dougmill, linux-kernel, UNGLinuxDriver, mcgrof,
mcoquelin.stm32, netdev
In-Reply-To: <af1ae1cf-4a01-5e3a-edc2-058668487137@web.de>
From: Markus Elfring <Markus.Elfring@web.de>
Date: Thu, 22 Aug 2019 20:30:15 +0200
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Thu, 22 Aug 2019 20:02:56 +0200
>
> The dev_kfree_skb() function performs also input parameter validation.
> Thus the test around the shown calls is not needed.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Applied.
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^ permalink raw reply
* Re: [PATCH] ARM: imx: Drop imx_anatop_init()
From: Leonard Crestez @ 2019-08-22 23:26 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Aisheng Dong, Peter Chen, Shawn Guo, linux-kernel@vger.kernel.org,
dl-linux-imx, Chris Healy, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAHQ1cqHBzFi80ZCa+jgs0Qy=dMP4yP7am1x-hMTxzb-8Zpok0w@mail.gmail.com>
On 22.08.2019 23:06, Andrey Smirnov wrote:
>> On 31.07.2019 21:01, Andrey Smirnov wrote:
>>> With commit b5bbe2235361 ("usb: phy: mxs: Disable external charger
>>> detect in mxs_phy_hw_init()") in tree all of the necessary charger
>>> setup is done by the USB PHY driver which covers all of the affected
>>> i.MX6 SoCs.
>>>
>>> NOTE: Imx_anatop_init() was also called for i.MX7D, but looking at its
>>> datasheet it appears to have a different USB PHY IP block, so
>>> executing i.MX6 charger disable configuration seems unnecessary.
>>>
>>> -void __init imx_anatop_init(void)
>>> -{
>>> - anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
>>> - if (IS_ERR(anatop)) {
>>> - pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
>>> - return;
>>> - }
>>
>> This patch breaks suspend on imx6 in linux-next because the "anatop"
>> regmap is no longer initialized. This was found via bisect but
>> no_console_suspend prints a helpful stack anyway:
>>
>> (regmap_read) from [<c01226e4>] (imx_anatop_enable_weak2p5+0x28/0x70)
>> (imx_anatop_enable_weak2p5) from [<c0122744>]
>> (imx_anatop_pre_suspend+0x18/0x64)
>> (imx_anatop_pre_suspend) from [<c0124434>] (imx6q_pm_enter+0x60/0x16c)
>> (imx6q_pm_enter) from [<c018c8a4>] (suspend_devices_and_enter+0x7d4/0xcbc)
>> (suspend_devices_and_enter) from [<c018d544>] (pm_suspend+0x7b8/0x904)
>> (pm_suspend) from [<c018b1b4>] (state_store+0x68/0xc8)
>>
>
> My bad, completely missed that fact that anatop was a global variable
> in imx_anatop_init(). Sorry about that.
>
>> Minimal fix looks like this:
>>
>> --- arch/arm/mach-imx/anatop.c
>> +++ arch/arm/mach-imx/anatop.c
>> @@ -111,6 +111,12 @@ void __init imx_init_revision_from_anatop(void)
>> digprog = readl_relaxed(anatop_base + offset);
>> iounmap(anatop_base);
>>
>> + anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
>> + if (IS_ERR(anatop)) {
>> + pr_err("failed to find imx6q-anatop regmap!\n");
>> + return;
>> + }
>>
>> Since all SOCs that called imx_anatop_init also call
>> imx_init_revision_from_anatop this might be an acceptable solution,
>> unless there is some limitation preventing early regmap lookup.
>>
>
> Would making every function that uses anatop explicitly request it via
> syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop") be too much of
> a code duplication? This way we won't need to worry if
> imx_init_revision_from_anatop() was called before any of them are
> used.
It's only used from pre_suspend and post_suspend, everything else in
arch/arm/mach-imx/anatop.c is static. Doing a lookup every time would be
silly, it's fine to let this be global.
I was wondering if maybe imx_init_revision could somehow end up getting
called before syscon/regmap core init.
--
Regards,
Leonard
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* Re: [PATCH v8 1/5] mm: untag user pointers in mmap/munmap/mremap/brk
From: Andrew Morton @ 2019-08-22 23:41 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arch, linux-doc, Szabolcs Nagy, Catalin Marinas,
Kevin Brodsky, Will Deacon, Dave P Martin, linux-mm,
Andrey Konovalov, Vincenzo Frascino, Dave Hansen,
linux-arm-kernel
In-Reply-To: <20190819162851.tncj4wpwf625ofg6@willie-the-truck>
On Mon, 19 Aug 2019 17:28:51 +0100 Will Deacon <will@kernel.org> wrote:
> On Thu, Aug 15, 2019 at 04:43:59PM +0100, Catalin Marinas wrote:
> > There isn't a good reason to differentiate between the user address
> > space layout modification syscalls and the other memory
> > permission/attributes ones (e.g. mprotect, madvise) w.r.t. the tagged
> > address ABI. Untag the user addresses on entry to these functions.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > ---
> > mm/mmap.c | 5 +++++
> > mm/mremap.c | 6 +-----
> > 2 files changed, 6 insertions(+), 5 deletions(-)
>
> Acked-by: Will Deacon <will@kernel.org>
>
> Andrew -- please can you pick this patch up? I'll take the rest of the
> series via arm64 once we've finished discussing the wording details.
>
Sure, I grabbed the patch from the v9 series.
But please feel free to include this in the arm64 tree - I'll autodrop
my copy if this turns up in linux-next.
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^ permalink raw reply
* Re: [PATCH 5/7] media: use the BIT() macro
From: Laurent Pinchart @ 2019-08-23 0:08 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Kate Stewart, Richard Fontana, Lad, Prabhakar, Thierry Reding,
Bluecherry Maintainers, Krzysztof Kozlowski, Sylwester Nawrocki,
devel, linux-samsung-soc, Michael Ellerman, Michal Simek,
Andrey Utkin, Jonathan Hunter, Kukjin Kim, linux-arm-kernel,
Ismael Luceno, Linux Media Mailing List, Mauro Carvalho Chehab,
Benoit Parrot, linux-tegra, Thomas Gleixner, Anton Sviridenko,
Allison Randal, Andy Walls, Hyun Kwon, Greg Kroah-Hartman,
linux-renesas-soc, Kyungmin Park, Kieran Bingham, Sakari Ailus,
Hans Verkuil
In-Reply-To: <c98344166a27f771db7f6379378080b04c06c814.1566502743.git.mchehab+samsung@kernel.org>
Hi Mauro,
Thank you for the patch.
On Thu, Aug 22, 2019 at 04:39:32PM -0300, Mauro Carvalho Chehab wrote:
> As warned by cppcheck:
>
> [drivers/media/dvb-frontends/cx24123.c:434]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
> [drivers/media/pci/bt8xx/bttv-input.c:87]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
> [drivers/media/pci/bt8xx/bttv-input.c:98]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
> ...
> [drivers/media/v4l2-core/v4l2-ioctl.c:1391]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
>
> There are lots of places where we're doing 1 << 31. That's bad,
> as, depending on the architecture, this has an undefined behavior.
>
> The BIT() macro is already prepared to handle this, so, let's
> just switch all "1 << number" macros by BIT(number) at the header files
> with has 1 << 31.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
> ---
> drivers/media/pci/cobalt/cobalt-driver.h | 63 +-
> drivers/media/pci/ivtv/ivtv-irq.h | 28 +-
> drivers/media/pci/mantis/mantis_reg.h | 156 ++---
> drivers/media/pci/solo6x10/solo6x10-regs.h | 290 ++++-----
> .../media/platform/am437x/am437x-vpfe_regs.h | 28 +-
> .../media/platform/davinci/dm644x_ccdc_regs.h | 22 +-
> .../media/platform/exynos4-is/fimc-lite-reg.h | 86 +--
> drivers/media/platform/exynos4-is/fimc-reg.h | 172 ++---
> drivers/media/platform/omap3isp/ispreg.h | 592 +++++++++---------
> drivers/media/platform/s3c-camif/camif-regs.h | 128 ++--
> drivers/media/platform/tegra-cec/tegra_cec.h | 80 +--
> drivers/media/platform/ti-vpe/vpe_regs.h | 94 +--
> drivers/media/platform/vsp1/vsp1_regs.h | 254 ++++----
> drivers/media/platform/xilinx/xilinx-vip.h | 33 +-
> drivers/media/radio/wl128x/fmdrv_common.h | 88 +--
> drivers/staging/media/ipu3/ipu3-tables.h | 4 +-
> 16 files changed, 1065 insertions(+), 1053 deletions(-)
>
> diff --git a/drivers/media/pci/cobalt/cobalt-driver.h b/drivers/media/pci/cobalt/cobalt-driver.h
> index 429bee4ef79c..14b8ca2daa17 100644
> --- a/drivers/media/pci/cobalt/cobalt-driver.h
> +++ b/drivers/media/pci/cobalt/cobalt-driver.h
> @@ -10,6 +10,7 @@
>
> #ifndef COBALT_DRIVER_H
> #define COBALT_DRIVER_H
> +#include <linux/bitops.h>
>
The blank line should go before the header, not after.
> #include <linux/module.h>
> #include <linux/pci.h>
[snip]
> diff --git a/drivers/media/platform/omap3isp/ispreg.h b/drivers/media/platform/omap3isp/ispreg.h
> index 38e2b99b3f10..197f8f43c8fc 100644
> --- a/drivers/media/platform/omap3isp/ispreg.h
> +++ b/drivers/media/platform/omap3isp/ispreg.h
> @@ -45,7 +45,7 @@
>
> #define ISPCCP2_REVISION (0x000)
> #define ISPCCP2_SYSCONFIG (0x004)
> -#define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1)
> +#define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
> #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
> #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
> #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \
> @@ -55,44 +55,44 @@
> #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \
> (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
> #define ISPCCP2_SYSSTATUS (0x008)
> -#define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0)
> +#define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
> #define ISPCCP2_LC01_IRQENABLE (0x00C)
> #define ISPCCP2_LC01_IRQSTATUS (0x010)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1)
> -#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1)
> +#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0)
>
> #define ISPCCP2_LC23_IRQENABLE (0x014)
> #define ISPCCP2_LC23_IRQSTATUS (0x018)
> #define ISPCCP2_LCM_IRQENABLE (0x02C)
> -#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0)
> -#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1)
> +#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0)
> +#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1)
> #define ISPCCP2_LCM_IRQSTATUS (0x030)
> #define ISPCCP2_CTRL (0x040)
> -#define ISPCCP2_CTRL_IF_EN (1 << 0)
> -#define ISPCCP2_CTRL_PHY_SEL (1 << 1)
> +#define ISPCCP2_CTRL_IF_EN BIT(0)
> +#define ISPCCP2_CTRL_PHY_SEL BIT(1)
> #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
> -#define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1)
> +#define ISPCCP2_CTRL_PHY_SEL_STROBE BIT(1)
Please don't replace this one, as it defines the value of a field, not a
bit. Otherwise it will not match ISPCCP2_CTRL_PHY_SEL_CLOCK and will be
confusing.
> #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
> #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
> -#define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2)
> +#define ISPCCP2_CTRL_IO_OUT_SEL BIT(2)
> #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
> #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
> -#define ISPCCP2_CTRL_MODE (1 << 4)
> -#define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9)
> -#define ISPCCP2_CTRL_INV (1 << 10)
> +#define ISPCCP2_CTRL_MODE BIT(4)
> +#define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9)
> +#define ISPCCP2_CTRL_INV BIT(10)
> #define ISPCCP2_CTRL_INV_MASK 0x1
> #define ISPCCP2_CTRL_INV_SHIFT 10
> -#define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11)
> -#define ISPCCP2_CTRL_VP_CLK_POL (1 << 12)
> +#define ISPCCP2_CTRL_VP_ONLY_EN BIT(11)
> +#define ISPCCP2_CTRL_VP_CLK_POL BIT(12)
> #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
> #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
> #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
> @@ -102,12 +102,12 @@
> #define ISPCCP2_DBG (0x044)
> #define ISPCCP2_GNQ (0x048)
> #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
> -#define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0)
> -#define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19)
> +#define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0)
> +#define ISPCCP2_LCx_CTRL_CRC_EN BIT(19)
> #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
> #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2
> #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19
> -#define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1)
> +#define ISPCCP2_LCx_CTRL_REGION_EN BIT(1)
> #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
> #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1
> #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
> @@ -127,8 +127,8 @@
> #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
> #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
> #define ISPCCP2_LCM_CTRL (0x1D0)
> -#define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0)
> -#define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2)
> +#define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0)
> +#define ISPCCP2_LCM_CTRL_DST_PORT BIT(2)
> #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2
> #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3
> #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
> @@ -138,8 +138,8 @@
> #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
> #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20
> #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
> -#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22)
> -#define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23)
> +#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22)
> +#define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23)
> #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24
> #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
> #define ISPCCP2_LCM_VSIZE (0x1D4)
> @@ -201,19 +201,19 @@
>
> /* SBL */
> #define ISPSBL_PCR 0x4
> -#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16)
> -#define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17)
> -#define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18)
> -#define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19)
> -#define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20)
> -#define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21)
> -#define ISPSBL_PCR_PRV_WBL_OVF (1 << 22)
> -#define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23)
> -#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24)
> -#define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25)
> -#define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26)
> +#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16)
> +#define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17)
> +#define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18)
> +#define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19)
> +#define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20)
> +#define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21)
> +#define ISPSBL_PCR_PRV_WBL_OVF BIT(22)
> +#define ISPSBL_PCR_CCDC_WBL_OVF BIT(23)
> +#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24)
> +#define ISPSBL_PCR_CSIA_WBL_OVF BIT(25)
> +#define ISPSBL_PCR_CSIB_WBL_OVF BIT(26)
> #define ISPSBL_CCDC_WR_0 (0x028)
> -#define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21)
> +#define ISPSBL_CCDC_WR_0_DATA_READY BIT(21)
> #define ISPSBL_CCDC_WR_1 (0x02C)
> #define ISPSBL_CCDC_WR_2 (0x030)
> #define ISPSBL_CCDC_WR_3 (0x034)
> @@ -366,40 +366,40 @@
>
> #define ISP_INT_CLR 0xFF113F11
> #define ISPPRV_PCR_EN 1
> -#define ISPPRV_PCR_BUSY (1 << 1)
> -#define ISPPRV_PCR_SOURCE (1 << 2)
> -#define ISPPRV_PCR_ONESHOT (1 << 3)
> -#define ISPPRV_PCR_WIDTH (1 << 4)
> -#define ISPPRV_PCR_INVALAW (1 << 5)
> -#define ISPPRV_PCR_DRKFEN (1 << 6)
> -#define ISPPRV_PCR_DRKFCAP (1 << 7)
> -#define ISPPRV_PCR_HMEDEN (1 << 8)
> -#define ISPPRV_PCR_NFEN (1 << 9)
> -#define ISPPRV_PCR_CFAEN (1 << 10)
> +#define ISPPRV_PCR_BUSY BIT(1)
> +#define ISPPRV_PCR_SOURCE BIT(2)
> +#define ISPPRV_PCR_ONESHOT BIT(3)
> +#define ISPPRV_PCR_WIDTH BIT(4)
> +#define ISPPRV_PCR_INVALAW BIT(5)
> +#define ISPPRV_PCR_DRKFEN BIT(6)
> +#define ISPPRV_PCR_DRKFCAP BIT(7)
> +#define ISPPRV_PCR_HMEDEN BIT(8)
> +#define ISPPRV_PCR_NFEN BIT(9)
> +#define ISPPRV_PCR_CFAEN BIT(10)
> #define ISPPRV_PCR_CFAFMT_SHIFT 11
> #define ISPPRV_PCR_CFAFMT_MASK 0x7800
> #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
> -#define ISPPRV_PCR_CFAFMT_SONYVGA (1 << 11)
> +#define ISPPRV_PCR_CFAFMT_SONYVGA BIT(11)
Same here.
> #define ISPPRV_PCR_CFAFMT_RGBFOVEON (2 << 11)
> #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11)
> #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11)
> #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11)
> -#define ISPPRV_PCR_YNENHEN (1 << 15)
> -#define ISPPRV_PCR_SUPEN (1 << 16)
> +#define ISPPRV_PCR_YNENHEN BIT(15)
> +#define ISPPRV_PCR_SUPEN BIT(16)
> #define ISPPRV_PCR_YCPOS_SHIFT 17
> #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
> -#define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17)
> +#define ISPPRV_PCR_YCPOS_YCbYCr BIT(17)
And here.
> #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17)
> #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17)
> -#define ISPPRV_PCR_RSZPORT (1 << 19)
> -#define ISPPRV_PCR_SDRPORT (1 << 20)
> -#define ISPPRV_PCR_SCOMP_EN (1 << 21)
> +#define ISPPRV_PCR_RSZPORT BIT(19)
> +#define ISPPRV_PCR_SDRPORT BIT(20)
> +#define ISPPRV_PCR_SCOMP_EN BIT(21)
> #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22)
> #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22)
> -#define ISPPRV_PCR_GAMMA_BYPASS (1 << 26)
> -#define ISPPRV_PCR_DCOREN (1 << 27)
> -#define ISPPRV_PCR_DCCOUP (1 << 28)
> -#define ISPPRV_PCR_DRK_FAIL (1 << 31)
> +#define ISPPRV_PCR_GAMMA_BYPASS BIT(26)
> +#define ISPPRV_PCR_DCOREN BIT(27)
> +#define ISPPRV_PCR_DCCOUP BIT(28)
> +#define ISPPRV_PCR_DRK_FAIL BIT(31)
>
> #define ISPPRV_HORZ_INFO_EPH_SHIFT 0
> #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
> @@ -423,8 +423,8 @@
> #define ISPPRV_AVE_ODDDIST_4 0x3
>
> #define ISPPRV_HMED_THRESHOLD_SHIFT 0
> -#define ISPPRV_HMED_EVENDIST (1 << 8)
> -#define ISPPRV_HMED_ODDDIST (1 << 9)
> +#define ISPPRV_HMED_EVENDIST BIT(8)
> +#define ISPPRV_HMED_ODDDIST BIT(9)
>
> #define ISPPRV_WBGAIN_COEF0_SHIFT 0
> #define ISPPRV_WBGAIN_COEF1_SHIFT 8
> @@ -517,8 +517,8 @@
> /* Define bit fields within selected registers */
> #define ISP_REVISION_SHIFT 0
>
> -#define ISP_SYSCONFIG_AUTOIDLE (1 << 0)
> -#define ISP_SYSCONFIG_SOFTRESET (1 << 1)
> +#define ISP_SYSCONFIG_AUTOIDLE BIT(0)
> +#define ISP_SYSCONFIG_SOFTRESET BIT(1)
> #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12
> #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
> #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
> @@ -526,68 +526,68 @@
>
> #define ISP_SYSSTATUS_RESETDONE 0
>
> -#define IRQ0ENABLE_CSIA_IRQ (1 << 0)
> -#define IRQ0ENABLE_CSIC_IRQ (1 << 1)
> -#define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3)
> -#define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4)
> -#define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5)
> -#define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6)
> -#define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7)
> +#define IRQ0ENABLE_CSIA_IRQ BIT(0)
> +#define IRQ0ENABLE_CSIC_IRQ BIT(1)
> +#define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3)
> +#define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4)
> +#define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5)
> +#define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6)
> +#define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7)
> #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \
> IRQ0ENABLE_CCP2_LC0_IRQ | \
> IRQ0ENABLE_CCP2_LC1_IRQ | \
> IRQ0ENABLE_CCP2_LC2_IRQ | \
> IRQ0ENABLE_CCP2_LC3_IRQ)
>
> -#define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8)
> -#define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9)
> -#define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10)
> -#define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11)
> -#define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12)
> -#define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13)
> -#define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16)
> -#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17)
> -#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
> -#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
> -#define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20)
> -#define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24)
> -#define IRQ0ENABLE_OVF_IRQ (1 << 25)
> -#define IRQ0ENABLE_PING_IRQ (1 << 26)
> -#define IRQ0ENABLE_PONG_IRQ (1 << 27)
> -#define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28)
> -#define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29)
> -#define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30)
> -#define IRQ0ENABLE_HS_VS_IRQ (1 << 31)
> +#define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8)
> +#define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9)
> +#define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10)
> +#define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11)
> +#define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12)
> +#define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13)
> +#define IRQ0ENABLE_HIST_DONE_IRQ BIT(16)
> +#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17)
> +#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18)
> +#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19)
> +#define IRQ0ENABLE_PRV_DONE_IRQ BIT(20)
> +#define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24)
> +#define IRQ0ENABLE_OVF_IRQ BIT(25)
> +#define IRQ0ENABLE_PING_IRQ BIT(26)
> +#define IRQ0ENABLE_PONG_IRQ BIT(27)
> +#define IRQ0ENABLE_MMU_ERR_IRQ BIT(28)
> +#define IRQ0ENABLE_OCP_ERR_IRQ BIT(29)
> +#define IRQ0ENABLE_SEC_ERR_IRQ BIT(30)
> +#define IRQ0ENABLE_HS_VS_IRQ BIT(31)
>
> -#define IRQ0STATUS_CSIA_IRQ (1 << 0)
> -#define IRQ0STATUS_CSI2C_IRQ (1 << 1)
> -#define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3)
> -#define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4)
> +#define IRQ0STATUS_CSIA_IRQ BIT(0)
> +#define IRQ0STATUS_CSI2C_IRQ BIT(1)
> +#define IRQ0STATUS_CCP2_LCM_IRQ BIT(3)
> +#define IRQ0STATUS_CCP2_LC0_IRQ BIT(4)
> #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \
> IRQ0STATUS_CCP2_LC0_IRQ)
>
> -#define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5)
> -#define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6)
> -#define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7)
> -#define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8)
> -#define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9)
> -#define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10)
> -#define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11)
> -#define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12)
> -#define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13)
> -#define IRQ0STATUS_HIST_DONE_IRQ (1 << 16)
> -#define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17)
> -#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18)
> -#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19)
> -#define IRQ0STATUS_PRV_DONE_IRQ (1 << 20)
> -#define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24)
> -#define IRQ0STATUS_OVF_IRQ (1 << 25)
> -#define IRQ0STATUS_PING_IRQ (1 << 26)
> -#define IRQ0STATUS_PONG_IRQ (1 << 27)
> -#define IRQ0STATUS_MMU_ERR_IRQ (1 << 28)
> -#define IRQ0STATUS_OCP_ERR_IRQ (1 << 29)
> -#define IRQ0STATUS_SEC_ERR_IRQ (1 << 30)
> -#define IRQ0STATUS_HS_VS_IRQ (1 << 31)
> +#define IRQ0STATUS_CSIB_LC1_IRQ BIT(5)
> +#define IRQ0STATUS_CSIB_LC2_IRQ BIT(6)
> +#define IRQ0STATUS_CSIB_LC3_IRQ BIT(7)
> +#define IRQ0STATUS_CCDC_VD0_IRQ BIT(8)
> +#define IRQ0STATUS_CCDC_VD1_IRQ BIT(9)
> +#define IRQ0STATUS_CCDC_VD2_IRQ BIT(10)
> +#define IRQ0STATUS_CCDC_ERR_IRQ BIT(11)
> +#define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12)
> +#define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13)
> +#define IRQ0STATUS_HIST_DONE_IRQ BIT(16)
> +#define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17)
> +#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18)
> +#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19)
> +#define IRQ0STATUS_PRV_DONE_IRQ BIT(20)
> +#define IRQ0STATUS_RSZ_DONE_IRQ BIT(24)
> +#define IRQ0STATUS_OVF_IRQ BIT(25)
> +#define IRQ0STATUS_PING_IRQ BIT(26)
> +#define IRQ0STATUS_PONG_IRQ BIT(27)
> +#define IRQ0STATUS_MMU_ERR_IRQ BIT(28)
> +#define IRQ0STATUS_OCP_ERR_IRQ BIT(29)
> +#define IRQ0STATUS_SEC_ERR_IRQ BIT(30)
> +#define IRQ0STATUS_HS_VS_IRQ BIT(31)
>
> #define TCTRL_GRESET_LEN 0
>
> @@ -607,20 +607,20 @@
> #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
>
> #define ISPCTRL_PAR_CLK_POL_SHIFT 4
> -#define ISPCTRL_PAR_CLK_POL_INV (1 << 4)
> -#define ISPCTRL_PING_PONG_EN (1 << 5)
> +#define ISPCTRL_PAR_CLK_POL_INV BIT(4)
> +#define ISPCTRL_PING_PONG_EN BIT(5)
> #define ISPCTRL_SHIFT_SHIFT 6
> #define ISPCTRL_SHIFT_0 (0x0 << 6)
> -#define ISPCTRL_SHIFT_2 (0x1 << 6)
> +#define ISPCTRL_SHIFT_2 BIT(6)
And here.
> #define ISPCTRL_SHIFT_4 (0x2 << 6)
> #define ISPCTRL_SHIFT_MASK (0x3 << 6)
>
> -#define ISPCTRL_CCDC_CLK_EN (1 << 8)
> -#define ISPCTRL_SCMP_CLK_EN (1 << 9)
> -#define ISPCTRL_H3A_CLK_EN (1 << 10)
> -#define ISPCTRL_HIST_CLK_EN (1 << 11)
> -#define ISPCTRL_PREV_CLK_EN (1 << 12)
> -#define ISPCTRL_RSZ_CLK_EN (1 << 13)
> +#define ISPCTRL_CCDC_CLK_EN BIT(8)
> +#define ISPCTRL_SCMP_CLK_EN BIT(9)
> +#define ISPCTRL_H3A_CLK_EN BIT(10)
> +#define ISPCTRL_HIST_CLK_EN BIT(11)
> +#define ISPCTRL_PREV_CLK_EN BIT(12)
> +#define ISPCTRL_RSZ_CLK_EN BIT(13)
> #define ISPCTRL_SYNC_DETECT_SHIFT 14
> #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
> #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
> @@ -628,17 +628,17 @@
> #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
> #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
>
> -#define ISPCTRL_CCDC_RAM_EN (1 << 16)
> -#define ISPCTRL_PREV_RAM_EN (1 << 17)
> -#define ISPCTRL_SBL_RD_RAM_EN (1 << 18)
> -#define ISPCTRL_SBL_WR1_RAM_EN (1 << 19)
> -#define ISPCTRL_SBL_WR0_RAM_EN (1 << 20)
> -#define ISPCTRL_SBL_AUTOIDLE (1 << 21)
> -#define ISPCTRL_SBL_SHARED_WPORTC (1 << 26)
> -#define ISPCTRL_SBL_SHARED_RPORTA (1 << 27)
> -#define ISPCTRL_SBL_SHARED_RPORTB (1 << 28)
> -#define ISPCTRL_JPEG_FLUSH (1 << 30)
> -#define ISPCTRL_CCDC_FLUSH (1 << 31)
> +#define ISPCTRL_CCDC_RAM_EN BIT(16)
> +#define ISPCTRL_PREV_RAM_EN BIT(17)
> +#define ISPCTRL_SBL_RD_RAM_EN BIT(18)
> +#define ISPCTRL_SBL_WR1_RAM_EN BIT(19)
> +#define ISPCTRL_SBL_WR0_RAM_EN BIT(20)
> +#define ISPCTRL_SBL_AUTOIDLE BIT(21)
> +#define ISPCTRL_SBL_SHARED_WPORTC BIT(26)
> +#define ISPCTRL_SBL_SHARED_RPORTA BIT(27)
> +#define ISPCTRL_SBL_SHARED_RPORTB BIT(28)
> +#define ISPCTRL_JPEG_FLUSH BIT(30)
> +#define ISPCTRL_CCDC_FLUSH BIT(31)
>
> #define ISPSECURE_SECUREMODE 0
>
> @@ -655,20 +655,20 @@
> #define ISPTCTRL_CTRL_DIVC_SHIFT 10
> #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
>
> -#define ISPTCTRL_CTRL_SHUTEN (1 << 21)
> -#define ISPTCTRL_CTRL_PSTRBEN (1 << 22)
> -#define ISPTCTRL_CTRL_STRBEN (1 << 23)
> -#define ISPTCTRL_CTRL_SHUTPOL (1 << 24)
> -#define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26)
> +#define ISPTCTRL_CTRL_SHUTEN BIT(21)
> +#define ISPTCTRL_CTRL_PSTRBEN BIT(22)
> +#define ISPTCTRL_CTRL_STRBEN BIT(23)
> +#define ISPTCTRL_CTRL_SHUTPOL BIT(24)
> +#define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26)
>
> #define ISPTCTRL_CTRL_INSEL_SHIFT 27
> #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
> -#define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
> +#define ISPTCTRL_CTRL_INSEL_CSIA BIT(27)
And here.
> #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
>
> -#define ISPTCTRL_CTRL_GRESETEn (1 << 29)
> -#define ISPTCTRL_CTRL_GRESETPOL (1 << 30)
> -#define ISPTCTRL_CTRL_GRESETDIR (1 << 31)
> +#define ISPTCTRL_CTRL_GRESETEn BIT(29)
> +#define ISPTCTRL_CTRL_GRESETPOL BIT(30)
> +#define ISPTCTRL_CTRL_GRESETDIR BIT(31)
>
> #define ISPTCTRL_FRAME_SHUT_SHIFT 0
> #define ISPTCTRL_FRAME_PSTRB_SHIFT 6
> @@ -679,33 +679,33 @@
> #define ISPCCDC_PID_TID_SHIFT 16
>
> #define ISPCCDC_PCR_EN 1
> -#define ISPCCDC_PCR_BUSY (1 << 1)
> +#define ISPCCDC_PCR_BUSY BIT(1)
>
> #define ISPCCDC_SYN_MODE_VDHDOUT 0x1
> -#define ISPCCDC_SYN_MODE_FLDOUT (1 << 1)
> -#define ISPCCDC_SYN_MODE_VDPOL (1 << 2)
> -#define ISPCCDC_SYN_MODE_HDPOL (1 << 3)
> -#define ISPCCDC_SYN_MODE_FLDPOL (1 << 4)
> -#define ISPCCDC_SYN_MODE_EXWEN (1 << 5)
> -#define ISPCCDC_SYN_MODE_DATAPOL (1 << 6)
> -#define ISPCCDC_SYN_MODE_FLDMODE (1 << 7)
> +#define ISPCCDC_SYN_MODE_FLDOUT BIT(1)
> +#define ISPCCDC_SYN_MODE_VDPOL BIT(2)
> +#define ISPCCDC_SYN_MODE_HDPOL BIT(3)
> +#define ISPCCDC_SYN_MODE_FLDPOL BIT(4)
> +#define ISPCCDC_SYN_MODE_EXWEN BIT(5)
> +#define ISPCCDC_SYN_MODE_DATAPOL BIT(6)
> +#define ISPCCDC_SYN_MODE_FLDMODE BIT(7)
> #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
> #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
> #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
> #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
> #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
> #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
> -#define ISPCCDC_SYN_MODE_PACK8 (1 << 11)
> +#define ISPCCDC_SYN_MODE_PACK8 BIT(11)
> #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12)
> #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
> -#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12)
> +#define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 BIT(12)
And here.
> #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12)
> -#define ISPCCDC_SYN_MODE_LPF (1 << 14)
> -#define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15)
> -#define ISPCCDC_SYN_MODE_VDHDEN (1 << 16)
> -#define ISPCCDC_SYN_MODE_WEN (1 << 17)
> -#define ISPCCDC_SYN_MODE_VP2SDR (1 << 18)
> -#define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19)
> +#define ISPCCDC_SYN_MODE_LPF BIT(14)
> +#define ISPCCDC_SYN_MODE_FLDSTAT BIT(15)
> +#define ISPCCDC_SYN_MODE_VDHDEN BIT(16)
> +#define ISPCCDC_SYN_MODE_WEN BIT(17)
> +#define ISPCCDC_SYN_MODE_VP2SDR BIT(18)
> +#define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19)
>
> #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
> #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16
> @@ -731,7 +731,7 @@
>
> #define ISPCCDC_HSIZE_OFF_SHIFT 0
>
> -#define ISPCCDC_SDOFST_FIINV (1 << 14)
> +#define ISPCCDC_SDOFST_FIINV BIT(14)
> #define ISPCCDC_SDOFST_FOFST_SHIFT 12
> #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12)
> #define ISPCCDC_SDOFST_LOFST3_SHIFT 0
> @@ -743,7 +743,7 @@
> #define ISPCCDC_CLAMP_OBST_SHIFT 10
> #define ISPCCDC_CLAMP_OBSLN_SHIFT 25
> #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28
> -#define ISPCCDC_CLAMP_CLAMPEN (1 << 31)
> +#define ISPCCDC_CLAMP_CLAMPEN BIT(31)
>
> #define ISPCCDC_COLPTN_R_Ye 0x0
> #define ISPCCDC_COLPTN_Gr_Cy 0x1
> @@ -772,8 +772,8 @@
> #define ISPCCDC_BLKCMP_R_YE_SHIFT 24
>
> #define ISPCCDC_FPC_FPNUM_SHIFT 0
> -#define ISPCCDC_FPC_FPCEN (1 << 15)
> -#define ISPCCDC_FPC_FPERR (1 << 16)
> +#define ISPCCDC_FPC_FPCEN BIT(15)
> +#define ISPCCDC_FPC_FPERR BIT(16)
>
> #define ISPCCDC_VDINT_1_SHIFT 0
> #define ISPCCDC_VDINT_1_MASK 0x00007fff
> @@ -784,23 +784,23 @@
> #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
> #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
> #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
> -#define ISPCCDC_ALAW_CCDTBL (1 << 3)
> +#define ISPCCDC_ALAW_CCDTBL BIT(3)
>
> #define ISPCCDC_REC656IF_R656ON 1
> -#define ISPCCDC_REC656IF_ECCFVH (1 << 1)
> +#define ISPCCDC_REC656IF_ECCFVH BIT(1)
>
> -#define ISPCCDC_CFG_BW656 (1 << 5)
> +#define ISPCCDC_CFG_BW656 BIT(5)
> #define ISPCCDC_CFG_FIDMD_SHIFT 6
> -#define ISPCCDC_CFG_WENLOG (1 << 8)
> +#define ISPCCDC_CFG_WENLOG BIT(8)
> #define ISPCCDC_CFG_WENLOG_AND (0 << 8)
> -#define ISPCCDC_CFG_WENLOG_OR (1 << 8)
> -#define ISPCCDC_CFG_Y8POS (1 << 11)
> -#define ISPCCDC_CFG_BSWD (1 << 12)
> -#define ISPCCDC_CFG_MSBINVI (1 << 13)
> -#define ISPCCDC_CFG_VDLC (1 << 15)
> +#define ISPCCDC_CFG_WENLOG_OR BIT(8)
And here.
> +#define ISPCCDC_CFG_Y8POS BIT(11)
> +#define ISPCCDC_CFG_BSWD BIT(12)
> +#define ISPCCDC_CFG_MSBINVI BIT(13)
> +#define ISPCCDC_CFG_VDLC BIT(15)
>
> #define ISPCCDC_FMTCFG_FMTEN 0x1
> -#define ISPCCDC_FMTCFG_LNALT (1 << 1)
> +#define ISPCCDC_FMTCFG_LNALT BIT(1)
> #define ISPCCDC_FMTCFG_LNUM_SHIFT 2
> #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4
> #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8
> @@ -809,12 +809,12 @@
> #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
> #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
> #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
> -#define ISPCCDC_FMTCFG_VPEN (1 << 15)
> +#define ISPCCDC_FMTCFG_VPEN BIT(15)
>
> #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
> #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16
> #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
> -#define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
> +#define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 BIT(16)
And here.
> #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
> #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
> #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
> @@ -839,9 +839,9 @@
> #define ISPRSZ_PID_CID_SHIFT 8
> #define ISPRSZ_PID_TID_SHIFT 16
>
> -#define ISPRSZ_PCR_ENABLE (1 << 0)
> -#define ISPRSZ_PCR_BUSY (1 << 1)
> -#define ISPRSZ_PCR_ONESHOT (1 << 2)
> +#define ISPRSZ_PCR_ENABLE BIT(0)
> +#define ISPRSZ_PCR_BUSY BIT(1)
> +#define ISPRSZ_PCR_ONESHOT BIT(2)
>
> #define ISPRSZ_CNT_HRSZ_SHIFT 0
> #define ISPRSZ_CNT_HRSZ_MASK \
> @@ -853,10 +853,10 @@
> #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
> #define ISPRSZ_CNT_VSTPH_SHIFT 23
> #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
> -#define ISPRSZ_CNT_YCPOS (1 << 26)
> -#define ISPRSZ_CNT_INPTYP (1 << 27)
> -#define ISPRSZ_CNT_INPSRC (1 << 28)
> -#define ISPRSZ_CNT_CBILIN (1 << 29)
> +#define ISPRSZ_CNT_YCPOS BIT(26)
> +#define ISPRSZ_CNT_INPTYP BIT(27)
> +#define ISPRSZ_CNT_INPSRC BIT(28)
> +#define ISPRSZ_CNT_CBILIN BIT(29)
>
> #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
> #define ISPRSZ_OUT_SIZE_HORZ_MASK \
> @@ -1081,8 +1081,8 @@
> #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11
> #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22
> #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
> -#define ISPH3A_PCR_BUSYAF (1 << 15)
> -#define ISPH3A_PCR_BUSYAEAWB (1 << 18)
> +#define ISPH3A_PCR_BUSYAF BIT(15)
> +#define ISPH3A_PCR_BUSYAEAWB BIT(18)
>
> #define ISPH3A_AEWWIN1_WINHC_SHIFT 0
> #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
> @@ -1167,14 +1167,14 @@
> #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
>
> #define ISPCCDC_LSC_ENABLE 1
> -#define ISPCCDC_LSC_BUSY (1 << 7)
> +#define ISPCCDC_LSC_BUSY BIT(7)
> #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
> #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8
> #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
> #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12
> #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
> #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1
> -#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6)
> +#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6)
>
> #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
> #define ISPCCDC_LSC_INITIAL_X_SHIFT 0
> @@ -1196,43 +1196,43 @@
> (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
> #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \
> (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
> -#define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1)
> -#define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0)
> +#define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1)
> +#define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0)
>
> #define ISPCSI2_SYSSTATUS (0x014)
> -#define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0)
> +#define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0)
>
> #define ISPCSI2_IRQSTATUS (0x018)
> -#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14)
> -#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13)
> -#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12)
> -#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
> -#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10)
> -#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9)
> -#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8)
> +#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14)
> +#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13)
> +#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12)
> +#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11)
> +#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10)
> +#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9)
> +#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8)
> #define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n))
This could be replaced by BIT(n).
>
> #define ISPCSI2_IRQENABLE (0x01c)
> #define ISPCSI2_CTRL (0x040)
> -#define ISPCSI2_CTRL_VP_CLK_EN (1 << 15)
> -#define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11)
> +#define ISPCSI2_CTRL_VP_CLK_EN BIT(15)
> +#define ISPCSI2_CTRL_VP_ONLY_EN BIT(11)
> #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8
> #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \
> (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
> -#define ISPCSI2_CTRL_DBG_EN (1 << 7)
> +#define ISPCSI2_CTRL_DBG_EN BIT(7)
> #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5
> #define ISPCSI2_CTRL_BURST_SIZE_MASK \
> (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
> -#define ISPCSI2_CTRL_FRAME (1 << 3)
> -#define ISPCSI2_CTRL_ECC_EN (1 << 2)
> -#define ISPCSI2_CTRL_SECURE (1 << 1)
> -#define ISPCSI2_CTRL_IF_EN (1 << 0)
> +#define ISPCSI2_CTRL_FRAME BIT(3)
> +#define ISPCSI2_CTRL_ECC_EN BIT(2)
> +#define ISPCSI2_CTRL_SECURE BIT(1)
> +#define ISPCSI2_CTRL_IF_EN BIT(0)
>
> #define ISPCSI2_DBG_H (0x044)
> #define ISPCSI2_GNQ (0x048)
> #define ISPCSI2_PHY_CFG (0x050)
> -#define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30)
> -#define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29)
> +#define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30)
> +#define ISPCSI2_PHY_CFG_RESET_DONE BIT(29)
> #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27
> #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \
> (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
> @@ -1251,7 +1251,7 @@
> (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
> #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \
> (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
> -#define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24)
> +#define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24)
>
> #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4))
> #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \
> @@ -1300,63 +1300,63 @@
> (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
>
> #define ISPCSI2_PHY_IRQSTATUS (0x054)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21)
> -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2)
> -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21)
> +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2)
> +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1)
> #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1
And this could be replace by BIT(0).
>
> #define ISPCSI2_SHORT_PACKET (0x05c)
> #define ISPCSI2_PHY_IRQENABLE (0x060)
> -#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26)
> -#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
> -#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24)
> -#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23)
> -#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22)
> -#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21)
> -#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20)
> -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19)
> -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18)
> -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17)
> -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16)
> -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15)
> -#define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14)
> -#define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13)
> -#define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12)
> -#define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11)
> -#define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1)
> -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0)
> +#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26)
> +#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25)
> +#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24)
> +#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23)
> +#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22)
> +#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21)
> +#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20)
> +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19)
> +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18)
> +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17)
> +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16)
> +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15)
> +#define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14)
> +#define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13)
> +#define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12)
> +#define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11)
> +#define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1)
> +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0)
>
> #define ISPCSI2_DBG_P (0x068)
> #define ISPCSI2_TIMING (0x06c)
> @@ -1371,12 +1371,12 @@
> #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8
> #define ISPCSI2_CTX_CTRL1_COUNT_MASK \
> (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
> -#define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7)
> -#define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6)
> -#define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5)
> -#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4)
> -#define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3)
> -#define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0)
> +#define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7)
> +#define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6)
> +#define ISPCSI2_CTX_CTRL1_CS_EN BIT(5)
> +#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4)
> +#define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3)
> +#define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0)
>
> #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
> #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13
> @@ -1385,7 +1385,7 @@
> #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11
> #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \
> (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
> -#define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10)
> +#define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10)
> #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
> #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \
> (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
> @@ -1401,24 +1401,24 @@
> #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
> #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
> #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
> -#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8)
> -#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7)
> -#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6)
> -#define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5)
> -#define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3)
> -#define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2)
> -#define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1)
> -#define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0)
> +#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8)
> +#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7)
> +#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6)
> +#define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5)
> +#define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3)
> +#define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2)
> +#define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1)
> +#define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0)
>
> #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
> -#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8)
> -#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7)
> -#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6)
> -#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5)
> -#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3)
> -#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2)
> -#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1)
> -#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0)
> +#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8)
> +#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7)
> +#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6)
> +#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5)
> +#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3)
> +#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2)
> +#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1)
> +#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0)
>
> #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
> #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5
> @@ -1454,9 +1454,9 @@
> (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
>
> #define ISPCSIPHY_REG1 (0x004)
> -#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29)
> +#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29)
> /* This field is for OMAP3630 only */
> -#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25)
> +#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25)
> #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18
> #define ISPCSIPHY_REG1_TCLK_TERM_MASK \
> (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
> @@ -1498,11 +1498,11 @@
> */
>
> /* OMAP343X_CONTROL_CSIRXFE */
> -#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV (1 << 7)
> -#define OMAP343X_CONTROL_CSIRXFE_RESENABLE (1 << 8)
> -#define OMAP343X_CONTROL_CSIRXFE_SELFORM (1 << 10)
> -#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ (1 << 12)
> -#define OMAP343X_CONTROL_CSIRXFE_RESET (1 << 13)
> +#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7)
> +#define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8)
> +#define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10)
> +#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12)
> +#define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13)
>
> /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */
> #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2
> @@ -1513,6 +1513,6 @@
> #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
> #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3
> /* CCP2B: set to receive data from PHY2 instead of PHY1 */
> -#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 (1 << 4)
> +#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4)
>
> #endif /* OMAP3_ISP_REG_H */
[snip]
> diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h
> index 1bb1d39c60d9..207c220f42aa 100644
> --- a/drivers/media/platform/vsp1/vsp1_regs.h
> +++ b/drivers/media/platform/vsp1/vsp1_regs.h
> @@ -15,8 +15,8 @@
> */
>
> #define VI6_CMD(n) (0x0000 + (n) * 4)
> -#define VI6_CMD_UPDHDR (1 << 4)
> -#define VI6_CMD_STRCMD (1 << 0)
> +#define VI6_CMD_UPDHDR BIT(4)
> +#define VI6_CMD_STRCMD BIT(0)
>
> #define VI6_CLK_DCSWT 0x0018
> #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
> @@ -32,21 +32,21 @@
> #define VI6_STATUS_SYS_ACT(n) (1 << ((n) + 8))
BIT((n) + 8)
>
> #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
> -#define VI6_WFP_IRQ_ENB_DFEE (1 << 1)
> -#define VI6_WFP_IRQ_ENB_FREE (1 << 0)
> +#define VI6_WFP_IRQ_ENB_DFEE BIT(1)
> +#define VI6_WFP_IRQ_ENB_FREE BIT(0)
>
> #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12)
> -#define VI6_WFP_IRQ_STA_DFE (1 << 1)
> -#define VI6_WFP_IRQ_STA_FRE (1 << 0)
> +#define VI6_WFP_IRQ_STA_DFE BIT(1)
> +#define VI6_WFP_IRQ_STA_FRE BIT(0)
>
> #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60)
> -#define VI6_DISP_IRQ_ENB_DSTE (1 << 8)
> -#define VI6_DISP_IRQ_ENB_MAEE (1 << 5)
> +#define VI6_DISP_IRQ_ENB_DSTE BIT(8)
> +#define VI6_DISP_IRQ_ENB_MAEE BIT(5)
> #define VI6_DISP_IRQ_ENB_LNEE(n) (1 << (n))
BIT(n)
>
> #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60)
> -#define VI6_DISP_IRQ_STA_DST (1 << 8)
> -#define VI6_DISP_IRQ_STA_MAE (1 << 5)
> +#define VI6_DISP_IRQ_STA_DST BIT(8)
> +#define VI6_DISP_IRQ_STA_MAE BIT(5)
> #define VI6_DISP_IRQ_STA_LNE(n) (1 << (n))
Here too.
> #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4)
> @@ -59,32 +59,32 @@
> #define VI6_DL_CTRL 0x0100
> #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16)
> #define VI6_DL_CTRL_AR_WAIT_SHIFT 16
> -#define VI6_DL_CTRL_DC2 (1 << 12)
> -#define VI6_DL_CTRL_DC1 (1 << 8)
> -#define VI6_DL_CTRL_DC0 (1 << 4)
> -#define VI6_DL_CTRL_CFM0 (1 << 2)
> -#define VI6_DL_CTRL_NH0 (1 << 1)
> -#define VI6_DL_CTRL_DLE (1 << 0)
> +#define VI6_DL_CTRL_DC2 BIT(12)
> +#define VI6_DL_CTRL_DC1 BIT(8)
> +#define VI6_DL_CTRL_DC0 BIT(4)
> +#define VI6_DL_CTRL_CFM0 BIT(2)
> +#define VI6_DL_CTRL_NH0 BIT(1)
> +#define VI6_DL_CTRL_DLE BIT(0)
>
> #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4)
>
> #define VI6_DL_SWAP 0x0114
> -#define VI6_DL_SWAP_LWS (1 << 2)
> -#define VI6_DL_SWAP_WDS (1 << 1)
> -#define VI6_DL_SWAP_BTS (1 << 0)
> +#define VI6_DL_SWAP_LWS BIT(2)
> +#define VI6_DL_SWAP_WDS BIT(1)
> +#define VI6_DL_SWAP_BTS BIT(0)
>
> #define VI6_DL_EXT_CTRL(n) (0x011c + (n) * 36)
> -#define VI6_DL_EXT_CTRL_NWE (1 << 16)
> +#define VI6_DL_EXT_CTRL_NWE BIT(16)
> #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8)
> #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8
> -#define VI6_DL_EXT_CTRL_DLPRI (1 << 5)
> -#define VI6_DL_EXT_CTRL_EXPRI (1 << 4)
> -#define VI6_DL_EXT_CTRL_EXT (1 << 0)
> +#define VI6_DL_EXT_CTRL_DLPRI BIT(5)
> +#define VI6_DL_EXT_CTRL_EXPRI BIT(4)
> +#define VI6_DL_EXT_CTRL_EXT BIT(0)
>
> #define VI6_DL_EXT_AUTOFLD_INT BIT(0)
>
> #define VI6_DL_BODY_SIZE 0x0120
> -#define VI6_DL_BODY_SIZE_UPD (1 << 24)
> +#define VI6_DL_BODY_SIZE_UPD BIT(24)
> #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0)
> #define VI6_DL_BODY_SIZE_BS_SHIFT 0
>
> @@ -107,32 +107,32 @@
> #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0
>
> #define VI6_RPF_INFMT 0x0308
> -#define VI6_RPF_INFMT_VIR (1 << 28)
> -#define VI6_RPF_INFMT_CIPM (1 << 16)
> -#define VI6_RPF_INFMT_SPYCS (1 << 15)
> -#define VI6_RPF_INFMT_SPUVS (1 << 14)
> +#define VI6_RPF_INFMT_VIR BIT(28)
> +#define VI6_RPF_INFMT_CIPM BIT(16)
> +#define VI6_RPF_INFMT_SPYCS BIT(15)
> +#define VI6_RPF_INFMT_SPUVS BIT(14)
> #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12)
> -#define VI6_RPF_INFMT_CEXT_EXT (1 << 12)
> +#define VI6_RPF_INFMT_CEXT_EXT BIT(12)
Please don't replace this one.
> #define VI6_RPF_INFMT_CEXT_ONE (2 << 12)
> #define VI6_RPF_INFMT_CEXT_MASK (3 << 12)
> #define VI6_RPF_INFMT_RDTM_BT601 (0 << 9)
> -#define VI6_RPF_INFMT_RDTM_BT601_EXT (1 << 9)
> +#define VI6_RPF_INFMT_RDTM_BT601_EXT BIT(9)
And this one.
> #define VI6_RPF_INFMT_RDTM_BT709 (2 << 9)
> #define VI6_RPF_INFMT_RDTM_BT709_EXT (3 << 9)
> #define VI6_RPF_INFMT_RDTM_MASK (7 << 9)
> -#define VI6_RPF_INFMT_CSC (1 << 8)
> +#define VI6_RPF_INFMT_CSC BIT(8)
> #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0)
> #define VI6_RPF_INFMT_RDFMT_SHIFT 0
>
> #define VI6_RPF_DSWAP 0x030c
> -#define VI6_RPF_DSWAP_A_LLS (1 << 11)
> -#define VI6_RPF_DSWAP_A_LWS (1 << 10)
> -#define VI6_RPF_DSWAP_A_WDS (1 << 9)
> -#define VI6_RPF_DSWAP_A_BTS (1 << 8)
> -#define VI6_RPF_DSWAP_P_LLS (1 << 3)
> -#define VI6_RPF_DSWAP_P_LWS (1 << 2)
> -#define VI6_RPF_DSWAP_P_WDS (1 << 1)
> -#define VI6_RPF_DSWAP_P_BTS (1 << 0)
> +#define VI6_RPF_DSWAP_A_LLS BIT(11)
> +#define VI6_RPF_DSWAP_A_LWS BIT(10)
> +#define VI6_RPF_DSWAP_A_WDS BIT(9)
> +#define VI6_RPF_DSWAP_A_BTS BIT(8)
> +#define VI6_RPF_DSWAP_P_LLS BIT(3)
> +#define VI6_RPF_DSWAP_P_LWS BIT(2)
> +#define VI6_RPF_DSWAP_P_WDS BIT(1)
> +#define VI6_RPF_DSWAP_P_BTS BIT(0)
>
> #define VI6_RPF_LOC 0x0310
> #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16)
> @@ -142,7 +142,7 @@
>
> #define VI6_RPF_ALPH_SEL 0x0314
> #define VI6_RPF_ALPH_SEL_ASEL_PACKED (0 << 28)
> -#define VI6_RPF_ALPH_SEL_ASEL_8B_PLANE (1 << 28)
> +#define VI6_RPF_ALPH_SEL_ASEL_8B_PLANE BIT(28)
And this one.
> #define VI6_RPF_ALPH_SEL_ASEL_SELECT (2 << 28)
> #define VI6_RPF_ALPH_SEL_ASEL_1B_PLANE (3 << 28)
> #define VI6_RPF_ALPH_SEL_ASEL_FIXED (4 << 28)
> @@ -150,9 +150,9 @@
> #define VI6_RPF_ALPH_SEL_ASEL_SHIFT 28
> #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24)
> #define VI6_RPF_ALPH_SEL_IROP_SHIFT 24
> -#define VI6_RPF_ALPH_SEL_BSEL (1 << 23)
> +#define VI6_RPF_ALPH_SEL_BSEL BIT(23)
> #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18)
> -#define VI6_RPF_ALPH_SEL_AEXT_EXT (1 << 18)
> +#define VI6_RPF_ALPH_SEL_AEXT_EXT BIT(18)
And this one.
> #define VI6_RPF_ALPH_SEL_AEXT_ONE (2 << 18)
> #define VI6_RPF_ALPH_SEL_AEXT_MASK (3 << 18)
> #define VI6_RPF_ALPH_SEL_ALPHA1_MASK (0xff << 8)
> @@ -171,7 +171,7 @@
> #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0
>
> #define VI6_RPF_MSK_CTRL 0x031c
> -#define VI6_RPF_MSK_CTRL_MSK_EN (1 << 24)
> +#define VI6_RPF_MSK_CTRL_MSK_EN BIT(24)
> #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16)
> #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16
> #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8)
> @@ -191,9 +191,9 @@
> #define VI6_RPF_MSK_SET_MSB_SHIFT 0
>
> #define VI6_RPF_CKEY_CTRL 0x0328
> -#define VI6_RPF_CKEY_CTRL_CV (1 << 4)
> -#define VI6_RPF_CKEY_CTRL_SAPE1 (1 << 1)
> -#define VI6_RPF_CKEY_CTRL_SAPE0 (1 << 0)
> +#define VI6_RPF_CKEY_CTRL_CV BIT(4)
> +#define VI6_RPF_CKEY_CTRL_SAPE1 BIT(1)
> +#define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0)
>
> #define VI6_RPF_CKEY_SET0 0x032c
> #define VI6_RPF_CKEY_SET1 0x0330
> @@ -220,9 +220,9 @@
>
> #define VI6_RPF_MULT_ALPHA 0x036c
> #define VI6_RPF_MULT_ALPHA_A_MMD_NONE (0 << 12)
> -#define VI6_RPF_MULT_ALPHA_A_MMD_RATIO (1 << 12)
> +#define VI6_RPF_MULT_ALPHA_A_MMD_RATIO BIT(12)
And this one.
> #define VI6_RPF_MULT_ALPHA_P_MMD_NONE (0 << 8)
> -#define VI6_RPF_MULT_ALPHA_P_MMD_RATIO (1 << 8)
> +#define VI6_RPF_MULT_ALPHA_P_MMD_RATIO BIT(8)
And this one.
> #define VI6_RPF_MULT_ALPHA_P_MMD_IMAGE (2 << 8)
> #define VI6_RPF_MULT_ALPHA_P_MMD_BOTH (3 << 8)
> #define VI6_RPF_MULT_ALPHA_RATIO_MASK (0xff << 0)
> @@ -236,11 +236,11 @@
>
> #define VI6_WPF_SRCRPF 0x1000
> #define VI6_WPF_SRCRPF_VIRACT_DIS (0 << 28)
> -#define VI6_WPF_SRCRPF_VIRACT_SUB (1 << 28)
> +#define VI6_WPF_SRCRPF_VIRACT_SUB BIT(28)
And this one.
> #define VI6_WPF_SRCRPF_VIRACT_MST (2 << 28)
> #define VI6_WPF_SRCRPF_VIRACT_MASK (3 << 28)
> #define VI6_WPF_SRCRPF_VIRACT2_DIS (0 << 24)
> -#define VI6_WPF_SRCRPF_VIRACT2_SUB (1 << 24)
> +#define VI6_WPF_SRCRPF_VIRACT2_SUB BIT(24)
And this one.
> #define VI6_WPF_SRCRPF_VIRACT2_MST (2 << 24)
> #define VI6_WPF_SRCRPF_VIRACT2_MASK (3 << 24)
> #define VI6_WPF_SRCRPF_RPF_ACT_DIS(n) (0 << ((n) * 2))
> @@ -250,7 +250,7 @@
>
> #define VI6_WPF_HSZCLIP 0x1004
> #define VI6_WPF_VSZCLIP 0x1008
> -#define VI6_WPF_SZCLIP_EN (1 << 28)
> +#define VI6_WPF_SZCLIP_EN BIT(28)
> #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16)
> #define VI6_WPF_SZCLIP_OFST_SHIFT 16
> #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0)
> @@ -259,45 +259,45 @@
> #define VI6_WPF_OUTFMT 0x100c
> #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24)
> #define VI6_WPF_OUTFMT_PDV_SHIFT 24
> -#define VI6_WPF_OUTFMT_PXA (1 << 23)
> -#define VI6_WPF_OUTFMT_ROT (1 << 18)
> -#define VI6_WPF_OUTFMT_HFLP (1 << 17)
> -#define VI6_WPF_OUTFMT_FLP (1 << 16)
> -#define VI6_WPF_OUTFMT_SPYCS (1 << 15)
> -#define VI6_WPF_OUTFMT_SPUVS (1 << 14)
> +#define VI6_WPF_OUTFMT_PXA BIT(23)
> +#define VI6_WPF_OUTFMT_ROT BIT(18)
> +#define VI6_WPF_OUTFMT_HFLP BIT(17)
> +#define VI6_WPF_OUTFMT_FLP BIT(16)
> +#define VI6_WPF_OUTFMT_SPYCS BIT(15)
> +#define VI6_WPF_OUTFMT_SPUVS BIT(14)
> #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12)
> #define VI6_WPF_OUTFMT_DITH_EN (3 << 12)
> #define VI6_WPF_OUTFMT_DITH_MASK (3 << 12)
> #define VI6_WPF_OUTFMT_WRTM_BT601 (0 << 9)
> -#define VI6_WPF_OUTFMT_WRTM_BT601_EXT (1 << 9)
> +#define VI6_WPF_OUTFMT_WRTM_BT601_EXT BIT(9)
And this one.
> #define VI6_WPF_OUTFMT_WRTM_BT709 (2 << 9)
> #define VI6_WPF_OUTFMT_WRTM_BT709_EXT (3 << 9)
> #define VI6_WPF_OUTFMT_WRTM_MASK (7 << 9)
> -#define VI6_WPF_OUTFMT_CSC (1 << 8)
> +#define VI6_WPF_OUTFMT_CSC BIT(8)
> #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0)
> #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0
>
> #define VI6_WPF_DSWAP 0x1010
> -#define VI6_WPF_DSWAP_P_LLS (1 << 3)
> -#define VI6_WPF_DSWAP_P_LWS (1 << 2)
> -#define VI6_WPF_DSWAP_P_WDS (1 << 1)
> -#define VI6_WPF_DSWAP_P_BTS (1 << 0)
> +#define VI6_WPF_DSWAP_P_LLS BIT(3)
> +#define VI6_WPF_DSWAP_P_LWS BIT(2)
> +#define VI6_WPF_DSWAP_P_WDS BIT(1)
> +#define VI6_WPF_DSWAP_P_BTS BIT(0)
>
> #define VI6_WPF_RNDCTRL 0x1014
> -#define VI6_WPF_RNDCTRL_CBRM (1 << 28)
> +#define VI6_WPF_RNDCTRL_CBRM BIT(28)
> #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24)
> -#define VI6_WPF_RNDCTRL_ABRM_ROUND (1 << 24)
> +#define VI6_WPF_RNDCTRL_ABRM_ROUND BIT(24)
And this one.
> #define VI6_WPF_RNDCTRL_ABRM_THRESH (2 << 24)
> #define VI6_WPF_RNDCTRL_ABRM_MASK (3 << 24)
> #define VI6_WPF_RNDCTRL_ATHRESH_MASK (0xff << 16)
> #define VI6_WPF_RNDCTRL_ATHRESH_SHIFT 16
> #define VI6_WPF_RNDCTRL_CLMD_FULL (0 << 12)
> -#define VI6_WPF_RNDCTRL_CLMD_CLIP (1 << 12)
> +#define VI6_WPF_RNDCTRL_CLMD_CLIP BIT(12)
And this one.
> #define VI6_WPF_RNDCTRL_CLMD_EXT (2 << 12)
> #define VI6_WPF_RNDCTRL_CLMD_MASK (3 << 12)
>
> #define VI6_WPF_ROT_CTRL 0x1018
> -#define VI6_WPF_ROT_CTRL_LN16 (1 << 17)
> +#define VI6_WPF_ROT_CTRL_LN16 BIT(17)
> #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0)
> #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0
>
> @@ -308,7 +308,7 @@
> #define VI6_WPF_DSTM_ADDR_C1 0x102c
>
> #define VI6_WPF_WRBCK_CTRL(n) (0x1034 + (n) * 0x100)
> -#define VI6_WPF_WRBCK_CTRL_WBMD (1 << 0)
> +#define VI6_WPF_WRBCK_CTRL_WBMD BIT(0)
>
> /* -----------------------------------------------------------------------------
> * UIF Control Registers
> @@ -317,20 +317,20 @@
> #define VI6_UIF_OFFSET 0x100
>
> #define VI6_UIF_DISCOM_DOCMCR 0x1c00
> -#define VI6_UIF_DISCOM_DOCMCR_CMPRU (1 << 16)
> -#define VI6_UIF_DISCOM_DOCMCR_CMPR (1 << 0)
> +#define VI6_UIF_DISCOM_DOCMCR_CMPRU BIT(16)
> +#define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0)
>
> #define VI6_UIF_DISCOM_DOCMSTR 0x1c04
> -#define VI6_UIF_DISCOM_DOCMSTR_CMPPRE (1 << 1)
> -#define VI6_UIF_DISCOM_DOCMSTR_CMPST (1 << 0)
> +#define VI6_UIF_DISCOM_DOCMSTR_CMPPRE BIT(1)
> +#define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0)
>
> #define VI6_UIF_DISCOM_DOCMCLSTR 0x1c08
> -#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE (1 << 1)
> -#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST (1 << 0)
> +#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE BIT(1)
> +#define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0)
>
> #define VI6_UIF_DISCOM_DOCMIENR 0x1c0c
> -#define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN (1 << 1)
> -#define VI6_UIF_DISCOM_DOCMIENR_CMPIEN (1 << 0)
> +#define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN BIT(1)
> +#define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0)
>
> #define VI6_UIF_DISCOM_DOCMMDR 0x1c10
> #define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n) ((n) << 16)
> @@ -338,7 +338,7 @@
> #define VI6_UIF_DISCOM_DOCMPMR 0x1c14
> #define VI6_UIF_DISCOM_DOCMPMR_CMPDFF(n) ((n) << 17)
> #define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n) ((n) << 8)
> -#define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF (1 << 7)
> +#define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF BIT(7)
> #define VI6_UIF_DISCOM_DOCMPMR_SEL(n) ((n) << 0)
>
> #define VI6_UIF_DISCOM_DOCMECRCR 0x1c18
> @@ -365,7 +365,7 @@
> #define VI6_DPR_HSI_ROUTE 0x2048
> #define VI6_DPR_BRU_ROUTE 0x204c
> #define VI6_DPR_ILV_BRS_ROUTE 0x2050
> -#define VI6_DPR_ROUTE_BRSSEL (1 << 28)
> +#define VI6_DPR_ROUTE_BRSSEL BIT(28)
> #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16)
> #define VI6_DPR_ROUTE_FXA_SHIFT 16
> #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8)
> @@ -407,10 +407,10 @@
> #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8)
> #define VI6_SRU_CTRL0_PARAM1_SHIFT 8
> #define VI6_SRU_CTRL0_MODE_UPSCALE (4 << 4)
> -#define VI6_SRU_CTRL0_PARAM2 (1 << 3)
> -#define VI6_SRU_CTRL0_PARAM3 (1 << 2)
> -#define VI6_SRU_CTRL0_PARAM4 (1 << 1)
> -#define VI6_SRU_CTRL0_EN (1 << 0)
> +#define VI6_SRU_CTRL0_PARAM2 BIT(3)
> +#define VI6_SRU_CTRL0_PARAM3 BIT(2)
> +#define VI6_SRU_CTRL0_PARAM4 BIT(1)
> +#define VI6_SRU_CTRL0_EN BIT(0)
>
> #define VI6_SRU_CTRL1 0x2204
> #define VI6_SRU_CTRL1_PARAM5 0x7ff
> @@ -427,18 +427,18 @@
> #define VI6_UDS_OFFSET 0x100
>
> #define VI6_UDS_CTRL 0x2300
> -#define VI6_UDS_CTRL_AMD (1 << 30)
> -#define VI6_UDS_CTRL_FMD (1 << 29)
> -#define VI6_UDS_CTRL_BLADV (1 << 28)
> -#define VI6_UDS_CTRL_AON (1 << 25)
> -#define VI6_UDS_CTRL_ATHON (1 << 24)
> -#define VI6_UDS_CTRL_BC (1 << 20)
> -#define VI6_UDS_CTRL_NE_A (1 << 19)
> -#define VI6_UDS_CTRL_NE_RCR (1 << 18)
> -#define VI6_UDS_CTRL_NE_GY (1 << 17)
> -#define VI6_UDS_CTRL_NE_BCB (1 << 16)
> -#define VI6_UDS_CTRL_AMDSLH (1 << 2)
> -#define VI6_UDS_CTRL_TDIPC (1 << 1)
> +#define VI6_UDS_CTRL_AMD BIT(30)
> +#define VI6_UDS_CTRL_FMD BIT(29)
> +#define VI6_UDS_CTRL_BLADV BIT(28)
> +#define VI6_UDS_CTRL_AON BIT(25)
> +#define VI6_UDS_CTRL_ATHON BIT(24)
> +#define VI6_UDS_CTRL_BC BIT(20)
> +#define VI6_UDS_CTRL_NE_A BIT(19)
> +#define VI6_UDS_CTRL_NE_RCR BIT(18)
> +#define VI6_UDS_CTRL_NE_GY BIT(17)
> +#define VI6_UDS_CTRL_NE_BCB BIT(16)
> +#define VI6_UDS_CTRL_AMDSLH BIT(2)
> +#define VI6_UDS_CTRL_TDIPC BIT(1)
>
> #define VI6_UDS_SCALE 0x2304
> #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28)
> @@ -477,12 +477,12 @@
> #define VI6_UDS_HPHASE_HEDP_SHIFT 0
>
> #define VI6_UDS_IPC 0x2318
> -#define VI6_UDS_IPC_FIELD (1 << 27)
> +#define VI6_UDS_IPC_FIELD BIT(27)
> #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0)
> #define VI6_UDS_IPC_VEDP_SHIFT 0
>
> #define VI6_UDS_HSZCLIP 0x231c
> -#define VI6_UDS_HSZCLIP_HCEN (1 << 28)
> +#define VI6_UDS_HSZCLIP_HCEN BIT(28)
> #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16)
> #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT 16
> #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0)
> @@ -507,36 +507,36 @@
> */
>
> #define VI6_LUT_CTRL 0x2800
> -#define VI6_LUT_CTRL_EN (1 << 0)
> +#define VI6_LUT_CTRL_EN BIT(0)
>
> /* -----------------------------------------------------------------------------
> * CLU Control Registers
> */
>
> #define VI6_CLU_CTRL 0x2900
> -#define VI6_CLU_CTRL_AAI (1 << 28)
> -#define VI6_CLU_CTRL_MVS (1 << 24)
> +#define VI6_CLU_CTRL_AAI BIT(28)
> +#define VI6_CLU_CTRL_MVS BIT(24)
> #define VI6_CLU_CTRL_AX1I_2D (3 << 14)
> -#define VI6_CLU_CTRL_AX2I_2D (1 << 12)
> +#define VI6_CLU_CTRL_AX2I_2D BIT(12)
This is a 2-bit field, please don't replace it either.
> #define VI6_CLU_CTRL_OS0_2D (3 << 8)
> -#define VI6_CLU_CTRL_OS1_2D (1 << 6)
> +#define VI6_CLU_CTRL_OS1_2D BIT(6)
Same here.
> #define VI6_CLU_CTRL_OS2_2D (3 << 4)
> -#define VI6_CLU_CTRL_M2D (1 << 1)
> -#define VI6_CLU_CTRL_EN (1 << 0)
> +#define VI6_CLU_CTRL_M2D BIT(1)
> +#define VI6_CLU_CTRL_EN BIT(0)
>
> /* -----------------------------------------------------------------------------
> * HST Control Registers
> */
>
> #define VI6_HST_CTRL 0x2a00
> -#define VI6_HST_CTRL_EN (1 << 0)
> +#define VI6_HST_CTRL_EN BIT(0)
>
> /* -----------------------------------------------------------------------------
> * HSI Control Registers
> */
>
> #define VI6_HSI_CTRL 0x2b00
> -#define VI6_HSI_CTRL_EN (1 << 0)
> +#define VI6_HSI_CTRL_EN BIT(0)
>
> /* -----------------------------------------------------------------------------
> * BRS and BRU Control Registers
> @@ -563,7 +563,7 @@
> #define VI6_BRS_BASE 0x3900
>
> #define VI6_BRU_INCTRL 0x0000
> -#define VI6_BRU_INCTRL_NRM (1 << 28)
> +#define VI6_BRU_INCTRL_NRM BIT(28)
> #define VI6_BRU_INCTRL_DnON (1 << (16 + (n)))
> #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4))
> #define VI6_BRU_INCTRL_DITHn_18BPP (1 << ((n) * 4))
> @@ -597,7 +597,7 @@
> #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0
>
> #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4))
> -#define VI6_BRU_CTRL_RBC (1 << 31)
> +#define VI6_BRU_CTRL_RBC BIT(31)
> #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20)
> #define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20)
> #define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20)
> @@ -610,29 +610,29 @@
> #define VI6_BRU_CTRL_AROP_MASK (0xf << 0)
>
> #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4))
> -#define VI6_BRU_BLD_CBES (1 << 31)
> +#define VI6_BRU_BLD_CBES BIT(31)
> #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28)
> -#define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28)
> +#define VI6_BRU_BLD_CCMDX_255_DST_A BIT(28)
This is a 3-bit field, please don't replace it.
> #define VI6_BRU_BLD_CCMDX_SRC_A (2 << 28)
> #define VI6_BRU_BLD_CCMDX_255_SRC_A (3 << 28)
> #define VI6_BRU_BLD_CCMDX_COEFX (4 << 28)
> #define VI6_BRU_BLD_CCMDX_MASK (7 << 28)
> #define VI6_BRU_BLD_CCMDY_DST_A (0 << 24)
> -#define VI6_BRU_BLD_CCMDY_255_DST_A (1 << 24)
> +#define VI6_BRU_BLD_CCMDY_255_DST_A BIT(24)
And this one.
> #define VI6_BRU_BLD_CCMDY_SRC_A (2 << 24)
> #define VI6_BRU_BLD_CCMDY_255_SRC_A (3 << 24)
> #define VI6_BRU_BLD_CCMDY_COEFY (4 << 24)
> #define VI6_BRU_BLD_CCMDY_MASK (7 << 24)
> #define VI6_BRU_BLD_CCMDY_SHIFT 24
> -#define VI6_BRU_BLD_ABES (1 << 23)
> +#define VI6_BRU_BLD_ABES BIT(23)
> #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20)
> -#define VI6_BRU_BLD_ACMDX_255_DST_A (1 << 20)
> +#define VI6_BRU_BLD_ACMDX_255_DST_A BIT(20)
And this one.
> #define VI6_BRU_BLD_ACMDX_SRC_A (2 << 20)
> #define VI6_BRU_BLD_ACMDX_255_SRC_A (3 << 20)
> #define VI6_BRU_BLD_ACMDX_COEFX (4 << 20)
> #define VI6_BRU_BLD_ACMDX_MASK (7 << 20)
> #define VI6_BRU_BLD_ACMDY_DST_A (0 << 16)
> -#define VI6_BRU_BLD_ACMDY_255_DST_A (1 << 16)
> +#define VI6_BRU_BLD_ACMDY_255_DST_A BIT(16)
And this one.
> #define VI6_BRU_BLD_ACMDY_SRC_A (2 << 16)
> #define VI6_BRU_BLD_ACMDY_255_SRC_A (3 << 16)
> #define VI6_BRU_BLD_ACMDY_COEFY (4 << 16)
> @@ -662,11 +662,11 @@
> #define VI6_HGO_SIZE_HSIZE_SHIFT 16
> #define VI6_HGO_SIZE_VSIZE_SHIFT 0
> #define VI6_HGO_MODE 0x3008
> -#define VI6_HGO_MODE_STEP (1 << 10)
> -#define VI6_HGO_MODE_MAXRGB (1 << 7)
> -#define VI6_HGO_MODE_OFSB_R (1 << 6)
> -#define VI6_HGO_MODE_OFSB_G (1 << 5)
> -#define VI6_HGO_MODE_OFSB_B (1 << 4)
> +#define VI6_HGO_MODE_STEP BIT(10)
> +#define VI6_HGO_MODE_MAXRGB BIT(7)
> +#define VI6_HGO_MODE_OFSB_R BIT(6)
> +#define VI6_HGO_MODE_OFSB_G BIT(5)
> +#define VI6_HGO_MODE_OFSB_B BIT(4)
> #define VI6_HGO_MODE_HRATIO_SHIFT 2
> #define VI6_HGO_MODE_VRATIO_SHIFT 0
> #define VI6_HGO_LB_TH 0x300c
> @@ -687,7 +687,7 @@
> #define VI6_HGO_EXT_HIST_ADDR 0x335c
> #define VI6_HGO_EXT_HIST_DATA 0x3360
> #define VI6_HGO_REGRST 0x33fc
> -#define VI6_HGO_REGRST_RCLEA (1 << 0)
> +#define VI6_HGO_REGRST_RCLEA BIT(0)
>
> /* -----------------------------------------------------------------------------
> * HGT Control Registers
> @@ -713,7 +713,7 @@
> #define VI6_HGT_SUM 0x3754
> #define VI6_HGT_LB_DET 0x3758
> #define VI6_HGT_REGRST 0x37fc
> -#define VI6_HGT_REGRST_RCLEA (1 << 0)
> +#define VI6_HGT_REGRST_RCLEA BIT(0)
>
> /* -----------------------------------------------------------------------------
> * LIF Control Registers
> @@ -724,9 +724,9 @@
> #define VI6_LIF_CTRL 0x3b00
> #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16)
> #define VI6_LIF_CTRL_OBTH_SHIFT 16
> -#define VI6_LIF_CTRL_CFMT (1 << 4)
> -#define VI6_LIF_CTRL_REQSEL (1 << 1)
> -#define VI6_LIF_CTRL_LIF_EN (1 << 0)
> +#define VI6_LIF_CTRL_CFMT BIT(4)
> +#define VI6_LIF_CTRL_REQSEL BIT(1)
> +#define VI6_LIF_CTRL_LIF_EN BIT(0)
>
> #define VI6_LIF_CSBTH 0x3b04
> #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16)
> @@ -735,7 +735,7 @@
> #define VI6_LIF_CSBTH_LBTH_SHIFT 0
>
> #define VI6_LIF_LBA 0x3b0c
> -#define VI6_LIF_LBA_LBA0 (1 << 31)
> +#define VI6_LIF_LBA_LBA0 BIT(31)
> #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16)
> #define VI6_LIF_LBA_LBA1_SHIFT 16
>
> @@ -767,9 +767,9 @@
> #define VI6_IP_VERSION_MODEL_VSPDL_GEN3 (0x19 << 8)
> #define VI6_IP_VERSION_MODEL_VSPBS_GEN3 (0x1a << 8)
> #define VI6_IP_VERSION_SOC_MASK (0xff << 0)
> -#define VI6_IP_VERSION_SOC_H2 (0x01 << 0)
> -#define VI6_IP_VERSION_SOC_V2H (0x01 << 0)
> -#define VI6_IP_VERSION_SOC_V3M (0x01 << 0)
> +#define VI6_IP_VERSION_SOC_H2 BIT(0)
> +#define VI6_IP_VERSION_SOC_V2H BIT(0)
> +#define VI6_IP_VERSION_SOC_V3M BIT(0)
These three are multi-bit fields, please don't replace them.
> #define VI6_IP_VERSION_SOC_M2 (0x02 << 0)
> #define VI6_IP_VERSION_SOC_M3W (0x02 << 0)
> #define VI6_IP_VERSION_SOC_V3H (0x02 << 0)
> diff --git a/drivers/media/platform/xilinx/xilinx-vip.h b/drivers/media/platform/xilinx/xilinx-vip.h
> index 47da39211ae4..9ca2c36c84cf 100644
> --- a/drivers/media/platform/xilinx/xilinx-vip.h
> +++ b/drivers/media/platform/xilinx/xilinx-vip.h
> @@ -11,6 +11,7 @@
>
> #ifndef __XILINX_VIP_H__
> #define __XILINX_VIP_H__
> +#include <linux/bitops.h>
>
The blank line should go above.
> #include <linux/io.h>
> #include <media/v4l2-subdev.h>
> @@ -35,23 +36,23 @@ struct clk;
>
> /* Xilinx Video IP Control Registers */
> #define XVIP_CTRL_CONTROL 0x0000
> -#define XVIP_CTRL_CONTROL_SW_ENABLE (1 << 0)
> -#define XVIP_CTRL_CONTROL_REG_UPDATE (1 << 1)
> -#define XVIP_CTRL_CONTROL_BYPASS (1 << 4)
> -#define XVIP_CTRL_CONTROL_TEST_PATTERN (1 << 5)
> -#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET (1 << 30)
> -#define XVIP_CTRL_CONTROL_SW_RESET (1 << 31)
> +#define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0)
> +#define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1)
> +#define XVIP_CTRL_CONTROL_BYPASS BIT(4)
> +#define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5)
> +#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30)
> +#define XVIP_CTRL_CONTROL_SW_RESET BIT(31)
> #define XVIP_CTRL_STATUS 0x0004
> -#define XVIP_CTRL_STATUS_PROC_STARTED (1 << 0)
> -#define XVIP_CTRL_STATUS_EOF (1 << 1)
> +#define XVIP_CTRL_STATUS_PROC_STARTED BIT(0)
> +#define XVIP_CTRL_STATUS_EOF BIT(1)
> #define XVIP_CTRL_ERROR 0x0008
> -#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY (1 << 0)
> -#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE (1 << 1)
> -#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY (1 << 2)
> -#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE (1 << 3)
> +#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0)
> +#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1)
> +#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2)
> +#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3)
> #define XVIP_CTRL_IRQ_ENABLE 0x000c
> -#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED (1 << 0)
> -#define XVIP_CTRL_IRQ_EOF (1 << 1)
> +#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0)
> +#define XVIP_CTRL_IRQ_EOF BIT(1)
> #define XVIP_CTRL_VERSION 0x0010
> #define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24)
> #define XVIP_CTRL_VERSION_MAJOR_SHIFT 24
> @@ -72,13 +73,13 @@ struct clk;
> #define XVIP_ACTIVE_HSIZE_SHIFT 0
> #define XVIP_ENCODING 0x0028
> #define XVIP_ENCODING_NBITS_8 (0 << 4)
> -#define XVIP_ENCODING_NBITS_10 (1 << 4)
> +#define XVIP_ENCODING_NBITS_10 BIT(4)
Please don't replace this one either.
> #define XVIP_ENCODING_NBITS_12 (2 << 4)
> #define XVIP_ENCODING_NBITS_16 (3 << 4)
> #define XVIP_ENCODING_NBITS_MASK (3 << 4)
> #define XVIP_ENCODING_NBITS_SHIFT 4
> #define XVIP_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0)
> -#define XVIP_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0)
> +#define XVIP_ENCODING_VIDEO_FORMAT_YUV444 BIT(0)
And same here.
> #define XVIP_ENCODING_VIDEO_FORMAT_RGB (2 << 0)
> #define XVIP_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0)
> #define XVIP_ENCODING_VIDEO_FORMAT_MASK (3 << 0)
> diff --git a/drivers/media/radio/wl128x/fmdrv_common.h b/drivers/media/radio/wl128x/fmdrv_common.h
> index 7d7a2b17aa76..699f328f3e52 100644
> --- a/drivers/media/radio/wl128x/fmdrv_common.h
> +++ b/drivers/media/radio/wl128x/fmdrv_common.h
> @@ -159,18 +159,18 @@ struct fm_event_msg_hdr {
> #define FM_DISABLE 0
>
> /* FLAG_GET register bits */
> -#define FM_FR_EVENT (1 << 0)
> -#define FM_BL_EVENT (1 << 1)
> -#define FM_RDS_EVENT (1 << 2)
> -#define FM_BBLK_EVENT (1 << 3)
> -#define FM_LSYNC_EVENT (1 << 4)
> -#define FM_LEV_EVENT (1 << 5)
> -#define FM_IFFR_EVENT (1 << 6)
> -#define FM_PI_EVENT (1 << 7)
> -#define FM_PD_EVENT (1 << 8)
> -#define FM_STIC_EVENT (1 << 9)
> -#define FM_MAL_EVENT (1 << 10)
> -#define FM_POW_ENB_EVENT (1 << 11)
> +#define FM_FR_EVENT BIT(0)
> +#define FM_BL_EVENT BIT(1)
> +#define FM_RDS_EVENT BIT(2)
> +#define FM_BBLK_EVENT BIT(3)
> +#define FM_LSYNC_EVENT BIT(4)
> +#define FM_LEV_EVENT BIT(5)
> +#define FM_IFFR_EVENT BIT(6)
> +#define FM_PI_EVENT BIT(7)
> +#define FM_PD_EVENT BIT(8)
> +#define FM_STIC_EVENT BIT(9)
> +#define FM_MAL_EVENT BIT(10)
> +#define FM_POW_ENB_EVENT BIT(11)
>
> /*
> * Firmware files of FM. ASIC ID and ASIC version will be appened to this,
> @@ -268,38 +268,38 @@ struct fm_event_msg_hdr {
> * Represents an RDS group type & version.
> * There are 15 groups, each group has 2 versions: A and B.
> */
> -#define FM_RDS_GROUP_TYPE_MASK_0A ((unsigned long)1<<0)
> -#define FM_RDS_GROUP_TYPE_MASK_0B ((unsigned long)1<<1)
> -#define FM_RDS_GROUP_TYPE_MASK_1A ((unsigned long)1<<2)
> -#define FM_RDS_GROUP_TYPE_MASK_1B ((unsigned long)1<<3)
> -#define FM_RDS_GROUP_TYPE_MASK_2A ((unsigned long)1<<4)
> -#define FM_RDS_GROUP_TYPE_MASK_2B ((unsigned long)1<<5)
> -#define FM_RDS_GROUP_TYPE_MASK_3A ((unsigned long)1<<6)
> -#define FM_RDS_GROUP_TYPE_MASK_3B ((unsigned long)1<<7)
> -#define FM_RDS_GROUP_TYPE_MASK_4A ((unsigned long)1<<8)
> -#define FM_RDS_GROUP_TYPE_MASK_4B ((unsigned long)1<<9)
> -#define FM_RDS_GROUP_TYPE_MASK_5A ((unsigned long)1<<10)
> -#define FM_RDS_GROUP_TYPE_MASK_5B ((unsigned long)1<<11)
> -#define FM_RDS_GROUP_TYPE_MASK_6A ((unsigned long)1<<12)
> -#define FM_RDS_GROUP_TYPE_MASK_6B ((unsigned long)1<<13)
> -#define FM_RDS_GROUP_TYPE_MASK_7A ((unsigned long)1<<14)
> -#define FM_RDS_GROUP_TYPE_MASK_7B ((unsigned long)1<<15)
> -#define FM_RDS_GROUP_TYPE_MASK_8A ((unsigned long)1<<16)
> -#define FM_RDS_GROUP_TYPE_MASK_8B ((unsigned long)1<<17)
> -#define FM_RDS_GROUP_TYPE_MASK_9A ((unsigned long)1<<18)
> -#define FM_RDS_GROUP_TYPE_MASK_9B ((unsigned long)1<<19)
> -#define FM_RDS_GROUP_TYPE_MASK_10A ((unsigned long)1<<20)
> -#define FM_RDS_GROUP_TYPE_MASK_10B ((unsigned long)1<<21)
> -#define FM_RDS_GROUP_TYPE_MASK_11A ((unsigned long)1<<22)
> -#define FM_RDS_GROUP_TYPE_MASK_11B ((unsigned long)1<<23)
> -#define FM_RDS_GROUP_TYPE_MASK_12A ((unsigned long)1<<24)
> -#define FM_RDS_GROUP_TYPE_MASK_12B ((unsigned long)1<<25)
> -#define FM_RDS_GROUP_TYPE_MASK_13A ((unsigned long)1<<26)
> -#define FM_RDS_GROUP_TYPE_MASK_13B ((unsigned long)1<<27)
> -#define FM_RDS_GROUP_TYPE_MASK_14A ((unsigned long)1<<28)
> -#define FM_RDS_GROUP_TYPE_MASK_14B ((unsigned long)1<<29)
> -#define FM_RDS_GROUP_TYPE_MASK_15A ((unsigned long)1<<30)
> -#define FM_RDS_GROUP_TYPE_MASK_15B ((unsigned long)1<<31)
> +#define FM_RDS_GROUP_TYPE_MASK_0A ((unsigned long)BIT(0))
> +#define FM_RDS_GROUP_TYPE_MASK_0B ((unsigned long)BIT(1))
> +#define FM_RDS_GROUP_TYPE_MASK_1A ((unsigned long)BIT(2))
> +#define FM_RDS_GROUP_TYPE_MASK_1B ((unsigned long)BIT(3))
> +#define FM_RDS_GROUP_TYPE_MASK_2A ((unsigned long)BIT(4))
> +#define FM_RDS_GROUP_TYPE_MASK_2B ((unsigned long)BIT(5))
> +#define FM_RDS_GROUP_TYPE_MASK_3A ((unsigned long)BIT(6))
> +#define FM_RDS_GROUP_TYPE_MASK_3B ((unsigned long)BIT(7))
> +#define FM_RDS_GROUP_TYPE_MASK_4A ((unsigned long)BIT(8))
> +#define FM_RDS_GROUP_TYPE_MASK_4B ((unsigned long)BIT(9))
> +#define FM_RDS_GROUP_TYPE_MASK_5A ((unsigned long)BIT(10))
> +#define FM_RDS_GROUP_TYPE_MASK_5B ((unsigned long)BIT(11))
> +#define FM_RDS_GROUP_TYPE_MASK_6A ((unsigned long)BIT(12))
> +#define FM_RDS_GROUP_TYPE_MASK_6B ((unsigned long)BIT(13))
> +#define FM_RDS_GROUP_TYPE_MASK_7A ((unsigned long)BIT(14))
> +#define FM_RDS_GROUP_TYPE_MASK_7B ((unsigned long)BIT(15))
> +#define FM_RDS_GROUP_TYPE_MASK_8A ((unsigned long)BIT(16))
> +#define FM_RDS_GROUP_TYPE_MASK_8B ((unsigned long)BIT(17))
> +#define FM_RDS_GROUP_TYPE_MASK_9A ((unsigned long)BIT(18))
> +#define FM_RDS_GROUP_TYPE_MASK_9B ((unsigned long)BIT(19))
> +#define FM_RDS_GROUP_TYPE_MASK_10A ((unsigned long)BIT(20))
> +#define FM_RDS_GROUP_TYPE_MASK_10B ((unsigned long)BIT(21))
> +#define FM_RDS_GROUP_TYPE_MASK_11A ((unsigned long)BIT(22))
> +#define FM_RDS_GROUP_TYPE_MASK_11B ((unsigned long)BIT(23))
> +#define FM_RDS_GROUP_TYPE_MASK_12A ((unsigned long)BIT(24))
> +#define FM_RDS_GROUP_TYPE_MASK_12B ((unsigned long)BIT(25))
> +#define FM_RDS_GROUP_TYPE_MASK_13A ((unsigned long)BIT(26))
> +#define FM_RDS_GROUP_TYPE_MASK_13B ((unsigned long)BIT(27))
> +#define FM_RDS_GROUP_TYPE_MASK_14A ((unsigned long)BIT(28))
> +#define FM_RDS_GROUP_TYPE_MASK_14B ((unsigned long)BIT(29))
> +#define FM_RDS_GROUP_TYPE_MASK_15A ((unsigned long)BIT(30))
> +#define FM_RDS_GROUP_TYPE_MASK_15B ((unsigned long)BIT(31))
BIT() includes a UL suffix, I think you can drop the unsigned long cast.
>
> /* RX Alternate Frequency info */
> #define FM_RDS_MIN_AF 1
> diff --git a/drivers/staging/media/ipu3/ipu3-tables.h b/drivers/staging/media/ipu3/ipu3-tables.h
> index a1bf3286f380..aefd9966a3ad 100644
> --- a/drivers/staging/media/ipu3/ipu3-tables.h
> +++ b/drivers/staging/media/ipu3/ipu3-tables.h
> @@ -4,6 +4,8 @@
> #ifndef __IPU3_TABLES_H
> #define __IPU3_TABLES_H
>
> +#include <linux/bitops.h>
> +
> #include "ipu3-abi.h"
>
> #define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */
> @@ -12,7 +14,7 @@
>
> #define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128
> #define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64
> -#define IMGU_SCALER_FP ((u32)1 << 31) /* 1.0 in fixed point */
> +#define IMGU_SCALER_FP ((u32)BIT(31)) /* 1.0 in fixed point */
Can't we drop the (u32) ?
>
> #define IMGU_XNR3_VMEM_LUT_LEN 16
--
Regards,
Laurent Pinchart
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