* Re: [PATCH 05/11] ftrace: create memcache for hash entries
From: Changbin Du @ 2019-08-26 22:35 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-arch, linux-s390, linux-parisc, Jonathan Corbet, linux-sh,
x86, linux-doc, linux-kernel, Steven Rostedt, linux-mips,
Ingo Molnar, Jessica Yu, sparclinux, linux-kbuild,
Thomas Gleixner, linuxppc-dev, linux-riscv, linux-arm-kernel,
Changbin Du
In-Reply-To: <20190826074437.GM2369@hirez.programming.kicks-ass.net>
On Mon, Aug 26, 2019 at 09:44:37AM +0200, Peter Zijlstra wrote:
> On Sun, Aug 25, 2019 at 09:23:24PM +0800, Changbin Du wrote:
> > When CONFIG_FTRACE_FUNC_PROTOTYPE is enabled, thousands of
> > ftrace_func_entry instances are created. So create a dedicated
> > memcache to enhance performance.
> >
> > Signed-off-by: Changbin Du <changbin.du@gmail.com>
> > ---
> > kernel/trace/ftrace.c | 17 ++++++++++++++++-
> > 1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
> > index a314f0768b2c..cfcb8dad93ea 100644
> > --- a/kernel/trace/ftrace.c
> > +++ b/kernel/trace/ftrace.c
> > @@ -94,6 +94,8 @@ struct ftrace_ops *function_trace_op __read_mostly = &ftrace_list_end;
> > /* What to set function_trace_op to */
> > static struct ftrace_ops *set_function_trace_op;
> >
> > +struct kmem_cache *hash_entry_cache;
> > +
> > static bool ftrace_pids_enabled(struct ftrace_ops *ops)
> > {
> > struct trace_array *tr;
> > @@ -1169,7 +1171,7 @@ static int add_hash_entry(struct ftrace_hash *hash, unsigned long ip,
> > {
> > struct ftrace_func_entry *entry;
> >
> > - entry = kmalloc(sizeof(*entry), GFP_KERNEL);
> > + entry = kmem_cache_alloc(hash_entry_cache, GFP_KERNEL);
> > if (!entry)
> > return -ENOMEM;
> >
> > @@ -6153,6 +6155,15 @@ void __init ftrace_init(void)
> > if (ret)
> > goto failed;
> >
> > + hash_entry_cache = kmem_cache_create("ftrace-hash",
> > + sizeof(struct ftrace_func_entry),
> > + sizeof(struct ftrace_func_entry),
> > + 0, NULL);
> > + if (!hash_entry_cache) {
> > + pr_err("failed to create ftrace hash entry cache\n");
> > + goto failed;
> > + }
>
> Wait what; you already have then in the binary image, now you're
> allocating extra memory for each of them?
>
No, here we only allocate ftrace hash entries. The prototype data is not copied.
The entry->priv points to prototype data in binary.
> Did you look at what ORC does? Is the binary search really not fast
> enough?
For ftrace, binary search is not enough. Just like the hash tables
(ftrace_graph_notrace_hash, ftrace_graph_hash) we already have which is used to
filter traced functions.
--
Cheers,
Changbin Du
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* Re: [PATCH 2/8] coresight: etm4x: Fix input validation for sysfs.
From: Mathieu Poirier @ 2019-08-26 22:29 UTC (permalink / raw)
To: Mike Leach; +Cc: coresight, linux-arm-kernel, suzuki.poulose
In-Reply-To: <20190819205720.24457-3-mike.leach@linaro.org>
On Mon, Aug 19, 2019 at 09:57:14PM +0100, Mike Leach wrote:
> A number of issues are fixed relating to sysfs input validation:-
>
> 1) bb_ctrl_store() - incorrect compare of bit select field to absolute
> value. Reworked per ETMv4 specification.
> 2) seq_event_store() - incorrect mask value - register has two
> event values.
> 3) cyc_threshold_store() - must mask with max before checking min
> otherwise wrapped values can set illegal value below min.
> 4) res_ctrl_store() - update to mask off all res0 bits.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 21 ++++++++++++-------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index b6984be0c515..fa1d6a938f6c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -652,10 +652,13 @@ static ssize_t cyc_threshold_store(struct device *dev,
>
> if (kstrtoul(buf, 16, &val))
> return -EINVAL;
> +
> + /* mask off max threshold before checking min value */
> + val &= ETM_CYC_THRESHOLD_MASK;
> if (val < drvdata->ccitmin)
> return -EINVAL;
>
> - config->ccctlr = val & ETM_CYC_THRESHOLD_MASK;
> + config->ccctlr = val;
> return size;
> }
> static DEVICE_ATTR_RW(cyc_threshold);
> @@ -686,14 +689,16 @@ static ssize_t bb_ctrl_store(struct device *dev,
> return -EINVAL;
> if (!drvdata->nr_addr_cmp)
> return -EINVAL;
> +
> /*
> - * Bit[7:0] selects which address range comparator is used for
> - * branch broadcast control.
> + * Bit[8] controls include(1) / exclude(0), bits[0-7] select
> + * individual range comparators. If include then at least 1
> + * range must be selected.
s/"must be selected"/"must be selected"
> */
> - if (BMVAL(val, 0, 7) > drvdata->nr_addr_cmp)
> + if ((val & BIT(8)) && (BMVAL(val, 0, 7) == 0))
> return -EINVAL;
>
> - config->bb_ctrl = val;
> + config->bb_ctrl = val & GENMASK(8, 0);
> return size;
> }
> static DEVICE_ATTR_RW(bb_ctrl);
> @@ -1324,8 +1329,8 @@ static ssize_t seq_event_store(struct device *dev,
>
> spin_lock(&drvdata->spinlock);
> idx = config->seq_idx;
> - /* RST, bits[7:0] */
> - config->seq_ctrl[idx] = val & 0xFF;
> + /* Seq control has two masks B[15:5] F[7:0] */
> + config->seq_ctrl[idx] = val & 0xFFFF;
> spin_unlock(&drvdata->spinlock);
> return size;
> }
> @@ -1580,7 +1585,7 @@ static ssize_t res_ctrl_store(struct device *dev,
> if (idx % 2 != 0)
> /* PAIRINV, bit[21] */
> val &= ~BIT(21);
> - config->res_ctrl[idx] = val;
> + config->res_ctrl[idx] = val & GENMASK(21, 0);
> spin_unlock(&drvdata->spinlock);
> return size;
> }
With the above:
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> --
> 2.17.1
>
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* Re: [RFC PATCH 5/7] arm64: smp: use generic SMP stop common code
From: Thomas Gleixner @ 2019-08-26 22:26 UTC (permalink / raw)
To: Cristian Marussi
Cc: linux-arch, mark.rutland, peterz, catalin.marinas, linux-kernel,
Christoph Hellwig, takahiro.akashi, james.morse,
hidehiro.kawai.ez, will, dave.martin, linux-arm-kernel
In-Reply-To: <c6a86709-6faf-bf84-08aa-c41dab61c58f@arm.com>
On Mon, 26 Aug 2019, Cristian Marussi wrote:
> On 8/26/19 4:32 PM, Christoph Hellwig wrote:
> > > +config ARCH_USE_COMMON_SMP_STOP
> > > + def_bool y if SMP
> >
> > The option belongs into common code and the arch code shoud only
> > select it.
> >
>
> In fact that was my first approach, but then I noticed that in kernel/ topdir
> there was no generic Kconfig but only subsystem specific ones:
>
> Kconfig.freezer Kconfig.hz Kconfig.locks Kconfig.preempt
arch/Kconfig
Thanks,
tglx
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* Re: [PATCH 03/11] asm-generic: add generic dwarf definition
From: Changbin Du @ 2019-08-26 22:25 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-arch, linux-s390, linux-parisc, Jonathan Corbet, linux-sh,
x86, linux-doc, linux-kernel, Steven Rostedt, linux-mips,
Ingo Molnar, Jessica Yu, sparclinux, linux-kbuild,
Thomas Gleixner, linuxppc-dev, linux-riscv, linux-arm-kernel,
Changbin Du
In-Reply-To: <20190826074215.GL2369@hirez.programming.kicks-ass.net>
Hi, Peter,
On Mon, Aug 26, 2019 at 09:42:15AM +0200, Peter Zijlstra wrote:
> On Sun, Aug 25, 2019 at 09:23:22PM +0800, Changbin Du wrote:
> > Add generic DWARF constant definitions. We will use it later.
> >
> > Signed-off-by: Changbin Du <changbin.du@gmail.com>
> > ---
> > include/asm-generic/dwarf.h | 199 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 199 insertions(+)
> > create mode 100644 include/asm-generic/dwarf.h
> >
> > diff --git a/include/asm-generic/dwarf.h b/include/asm-generic/dwarf.h
> > new file mode 100644
> > index 000000000000..c705633c2a8f
> > --- /dev/null
> > +++ b/include/asm-generic/dwarf.h
> > @@ -0,0 +1,199 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Architecture independent definitions of DWARF.
> > + *
> > + * Copyright (C) 2019 Changbin Du <changbin.du@gmail.com>
>
> You're claiming copyright on dwarf definitions? ;-)
>
> I'm thinking only Oracle was daft enough to think stuff like that was
> copyrightable.
>
ok, let me remove copyright line. I think SPDX claim is okay, right?
> Also; I think it would be very good to not use/depend on DWARF for this.
>
It only includes the DWARF expersion opcodes, not all of dwarf stuffs.
> You really don't need all of DWARF; I'm thikning you only need a few
> types; for location we already have regs_get_kernel_argument() which
> has all the logic to find the n-th argument.
>
regs_get_kernel_argument() can handle most cases, but if the size of one paramater
exceeds 64bit (it is rare in kernel), we must recalculate the locations. So I think
dwarf location descriptor is the most accurate one.
--
Cheers,
Changbin Du
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* Re: [PATCH RESEND 05/14] drm: rockchip: Provide ddc symlink in rk3066_hdmi sysfs directory
From: Heiko Stuebner @ 2019-08-26 22:15 UTC (permalink / raw)
To: Andrzej Pietrasiewicz, amd-gfx
Cc: Neil Armstrong, David Airlie, dri-devel, linux-kernel,
Andrzej Hajda, kernel, David (ChunMing) Zhou, linux-samsung-soc,
linux-rockchip, Harry Wentland, Leo Li, linux-arm-msm, intel-gfx,
linux-mediatek, linux-tegra, Sean Paul, linux-arm-kernel,
Sandy Huang, Daniel Vetter, Alex Deucher, freedreno,
Christian König
In-Reply-To: <4cad24dde4508cec17483f983da08226ba7e48b0.1566845537.git.andrzej.p@collabora.com>
Am Montag, 26. August 2019, 21:25:47 CEST schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
> Acked-by: Sam Ravnborg <sam@ravnborg.org>
> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
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* Re: [PATCH RESEND 06/14] drm: rockchip: Provide ddc symlink in inno_hdmi sysfs directory
From: Heiko Stuebner @ 2019-08-26 22:14 UTC (permalink / raw)
To: Andrzej Pietrasiewicz, linux-kernel, Sam Ravnborg, Daniel Vetter,
Sean Paul
Cc: freedreno, linux-samsung-soc, linux-tegra, linux-rockchip, Leo Li,
linux-arm-msm, intel-gfx, Sandy Huang, dri-devel, Jonathan Hunter,
Eric Anholt, Thierry Reding, linux-mediatek, Alex Deucher, kernel,
Harry Wentland, linux-arm-kernel
In-Reply-To: <a1f778d328328f15300338600bb2400850717300.1566845537.git.andrzej.p@collabora.com>
Am Montag, 26. August 2019, 21:25:48 CEST schrieb Andrzej Pietrasiewicz:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
> Acked-by: Sam Ravnborg <sam@ravnborg.org>
> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
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* Re: [PATCH 1/8] coresight: etm4x: Fixes for ETM v4.4 architecture updates.
From: Mathieu Poirier @ 2019-08-26 21:47 UTC (permalink / raw)
To: Mike Leach; +Cc: coresight, linux-arm-kernel, suzuki.poulose
In-Reply-To: <20190819205720.24457-2-mike.leach@linaro.org>
Hi Mike,
On Mon, Aug 19, 2019 at 09:57:13PM +0100, Mike Leach wrote:
> ETMv4.4 adds in support for tracing secure EL2 (per arch 8.x updates).
What is the name of the ETMv4.4 document? I can only find up to 4.2 on line.
> Patch accounts for this new capability.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../hwtracing/coresight/coresight-etm4x-sysfs.c | 12 ++++++------
> drivers/hwtracing/coresight/coresight-etm4x.c | 5 ++++-
> drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++++++++++----
> 3 files changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 219c10eb752c..b6984be0c515 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -738,7 +738,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev,
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
>
> - val = BMVAL(config->vinst_ctrl, 16, 19);
> + val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
>
> @@ -754,8 +754,8 @@ static ssize_t s_exlevel_vinst_store(struct device *dev,
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
> - /* clear all EXLEVEL_S bits (bit[18] is never implemented) */
> - config->vinst_ctrl &= ~(BIT(16) | BIT(17) | BIT(19));
> + /* clear all EXLEVEL_S bits */
> + config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK);
> /* enable instruction tracing for corresponding exception level */
> val &= drvdata->s_ex_level;
> config->vinst_ctrl |= (val << 16);
> @@ -773,7 +773,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev,
> struct etmv4_config *config = &drvdata->config;
>
> /* EXLEVEL_NS, bits[23:20] */
> - val = BMVAL(config->vinst_ctrl, 20, 23);
> + val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20;
> return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> }
>
> @@ -789,8 +789,8 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev,
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
> - /* clear EXLEVEL_NS bits (bit[23] is never implemented */
> - config->vinst_ctrl &= ~(BIT(20) | BIT(21) | BIT(22));
> + /* clear EXLEVEL_NS bits */
> + config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK);
> /* enable instruction tracing for corresponding exception level */
> val &= drvdata->ns_ex_level;
> config->vinst_ctrl |= (val << 20);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index a128b5063f46..52b8876de157 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -629,6 +629,7 @@ static void etm4_init_arch_data(void *info)
> * TRCARCHMAJ, bits[11:8] architecture major versin number
> */
> drvdata->arch = BMVAL(etmidr1, 4, 11);
> + drvdata->config.arch = drvdata->arch;
>
> /* maximum size of resources */
> etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
> @@ -780,6 +781,7 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
> static u64 etm4_get_access_type(struct etmv4_config *config)
> {
> u64 access_type = etm4_get_ns_access_type(config);
> + u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
>
> /*
> * EXLEVEL_S, bits[11:8], don't trace anything happening
> @@ -787,7 +789,8 @@ static u64 etm4_get_access_type(struct etmv4_config *config)
> */
> access_type |= (ETM_EXLEVEL_S_APP |
> ETM_EXLEVEL_S_OS |
> - ETM_EXLEVEL_S_HYP);
> + s_hyp |
> + ETM_EXLEVEL_S_MON);
>
> return access_type;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4523f10ddd0f..60bc2fb5159b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -180,17 +180,22 @@
> /* PowerDown Control Register bits */
> #define TRCPDCR_PU BIT(3)
>
> -/* secure state access levels */
> +/* secure state access levels - TRCACATRn */
> #define ETM_EXLEVEL_S_APP BIT(8)
> #define ETM_EXLEVEL_S_OS BIT(9)
> -#define ETM_EXLEVEL_S_NA BIT(10)
> -#define ETM_EXLEVEL_S_HYP BIT(11)
> -/* non-secure state access levels */
> +#define ETM_EXLEVEL_S_HYP BIT(10)
> +#define ETM_EXLEVEL_S_MON BIT(11)
> +/* non-secure state access levels - TRCACATRn */
> #define ETM_EXLEVEL_NS_APP BIT(12)
> #define ETM_EXLEVEL_NS_OS BIT(13)
> #define ETM_EXLEVEL_NS_HYP BIT(14)
> #define ETM_EXLEVEL_NS_NA BIT(15)
>
> +/* secure / non secure masks - TRCVICTLR, IDR3 */
> +#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16)
> +/* NS MON (EL3) mode never implemented */
> +#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20)
It is hard to say without documentation but shouldn't this be GENMASK(23, 20)?
> +
> /**
> * struct etmv4_config - configuration information related to an ETMv4
> * @mode: Controls various modes supported by this ETM.
> @@ -237,6 +242,7 @@
> * @vmid_mask0: VM ID comparator mask for comparator 0-3.
> * @vmid_mask1: VM ID comparator mask for comparator 4-7.
> * @ext_inp: External input selection.
> + * @arch: ETM architecture version (for arch dependent config).
> */
> struct etmv4_config {
> u32 mode;
> @@ -279,6 +285,7 @@ struct etmv4_config {
> u32 vmid_mask0;
> u32 vmid_mask1;
> u32 ext_inp;
> + u8 arch;
> };
>
> /**
> --
> 2.17.1
>
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* Re: [PATCH v1 5/6] rqchip/gic-v3-its: move reset pending table outside of allocator
From: Pavel Tatashin @ 2019-08-26 21:29 UTC (permalink / raw)
To: Pavel Tatashin, James Morris, Sasha Levin, kexec mailing list,
LKML, Linux ARM, Marc Zyngier, James Morse, Vladimir Murzin,
Mark Rutland
In-Reply-To: <20190826190056.27854-6-pasha.tatashin@soleen.com>
This patch requires a small fix (which I will do in later revisions):
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 2ffdb3927549..c9faeac4b3a8 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2182,7 +2182,8 @@ static void its_cpu_init_lpis(void)
paddr &= GENMASK_ULL(51, 16);
WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
- its_free_pending_table(gic_data_rdist()->pend_page);
+ if (efi_enabled(EFI_CONFIG_TABLES))
+ its_free_pending_table(gic_data_rdist()->pend_page);
gic_data_rdist()->pend_page = NULL;
goto out;
reserved-memory does not need to be freed. However, I am confused why
it is needed to be freed in EFI case. Marc, can you please explain
this to me?
Thank you,
Pasha
On Mon, Aug 26, 2019 at 3:01 PM Pavel Tatashin
<pasha.tatashin@soleen.com> wrote:
>
> Allow to use reserved memory for interrupt controller tables.
>
> Currently, it is not possible to do kexec reboots without possible memory
> corruption using device tree and GICv3 interrupt controller.
>
> GICv3 can be configured once during boot, and location of tables cannot
> be changed thereafter.
>
> The fix is to allow to reserve memory region in interrupt controller device
> property, and use it to do allocations.
>
> Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 82 ++++++++++++++++++++++++++++----
> 1 file changed, 72 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index d5f3508ca11f..aeda8760cc4e 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -47,6 +47,54 @@
>
> static u32 lpi_id_bits;
>
> +/*
> + * Describes reserved memory region in interrupt controller.
> + * The memory reserved: [pa_start, pa_end)
> + */
> +struct of_resv {
> + unsigned long pa_start;
> + unsigned long pa_end;
> +};
> +
> +static struct page __init *get_of_page(struct of_resv *resv, unsigned long size)
> +{
> + unsigned long pa = ALIGN(resv->pa_start, size);
> + unsigned long pa_next = pa + size;
> +
> + /* Check if there is enough memory reserved to do another allocation */
> + if (pa_next > resv->pa_end)
> + return NULL;
> +
> + resv->pa_start = pa_next;
> + memset(phys_to_virt(pa), 0, size);
> +
> + return phys_to_page(pa);
> +}
> +
> +/*
> + * Memory controller might have a reserved memory region to be used for table
> + * allocations. This is a requirement for kexec reboots.
> + */
> +static void __init its_of_mem_region(struct device_node *node,
> + struct of_resv **resv,
> + struct of_resv *resv_buf)
> +{
> + struct device_node *np = of_parse_phandle(node, "memory-region", 0);
> + struct resource mem_res;
> +
> + if (!np)
> + return;
> +
> + if (of_address_to_resource(np, 0, &mem_res)) {
> + pr_warn("%pOF: address to resource failed\n", np);
> + return;
> + }
> +
> + resv_buf->pa_start = mem_res.start;
> + resv_buf->pa_end = mem_res.start + resource_size(&mem_res);
> + *resv = resv_buf;
> +}
> +
> /*
> * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
> * deal with (one configuration byte per interrupt). PENDBASE has to
> @@ -1665,7 +1713,7 @@ static int gic_reserve_range(phys_addr_t addr, unsigned long size)
> return 0;
> }
>
> -static int __init its_setup_lpi_prop_table(void)
> +static int __init its_setup_lpi_prop_table(struct of_resv *resv)
> {
> if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
> unsigned long pa;
> @@ -1676,7 +1724,10 @@ static int __init its_setup_lpi_prop_table(void)
> lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
>
> pa = val & GENMASK_ULL(51, 12);
> - va = memremap(pa, LPI_PROPBASE_SZ, MEMREMAP_WB);
> + if (resv)
> + va = phys_to_virt(pa);
> + else
> + va = memremap(pa, LPI_PROPBASE_SZ, MEMREMAP_WB);
> gic_rdists->prop_table_pa = pa;
> gic_rdists->prop_table_va = va;
> } else {
> @@ -1685,7 +1736,10 @@ static int __init its_setup_lpi_prop_table(void)
> lpi_id_bits = min_t(u32,
> GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
> ITS_MAX_LPI_NRBITS);
> - page = its_allocate_prop_table(GFP_NOWAIT);
> + if (resv)
> + page = get_of_page(resv, LPI_PROPBASE_SZ);
> + else
> + page = its_allocate_prop_table(GFP_NOWAIT);
> if (!page) {
> pr_err("Failed to allocate PROPBASE\n");
> return -ENOMEM;
> @@ -2009,7 +2063,8 @@ static void its_free_pending_table(struct page *pt)
>
> /*
> * Booting with kdump and LPIs enabled is generally fine. Any other
> - * case is wrong in the absence of firmware/EFI support.
> + * case is wrong in the absence of firmware/EFI support or reserve-memory
> + * in device tree for interrupt controller.
> */
> static bool enabled_lpis_allowed(void)
> {
> @@ -2023,7 +2078,7 @@ static bool enabled_lpis_allowed(void)
> return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
> }
>
> -static int __init allocate_lpi_tables(void)
> +static int __init allocate_lpi_tables(struct of_resv *resv)
> {
> u64 val;
> int err, cpu;
> @@ -2039,7 +2094,7 @@ static int __init allocate_lpi_tables(void)
> pr_info("GICv3: Using preallocated redistributor tables\n");
> }
>
> - err = its_setup_lpi_prop_table();
> + err = its_setup_lpi_prop_table(resv);
> if (err)
> return err;
>
> @@ -2051,7 +2106,10 @@ static int __init allocate_lpi_tables(void)
> for_each_possible_cpu(cpu) {
> struct page *pend_page;
>
> - pend_page = its_allocate_pending_table(GFP_NOWAIT);
> + if (resv)
> + pend_page = get_of_page(resv, LPI_PENDBASE_SZ);
> + else
> + pend_page = its_allocate_pending_table(GFP_NOWAIT);
> if (!pend_page) {
> pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
> return -ENOMEM;
> @@ -3957,16 +4015,20 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
> struct irq_domain *parent_domain)
> {
> struct device_node *of_node;
> + struct of_resv resv_buf;
> + struct of_resv *resv = NULL;
> struct its_node *its;
> bool has_v4 = false;
> int err;
>
> its_parent = parent_domain;
> of_node = to_of_node(handle);
> - if (of_node)
> + if (of_node) {
> its_of_probe(of_node);
> - else
> + its_of_mem_region(of_node, &resv, &resv_buf);
> + } else {
> its_acpi_probe();
> + }
>
> if (list_empty(&its_nodes)) {
> pr_warn("ITS: No ITS available, not enabling LPIs\n");
> @@ -3975,7 +4037,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
>
> gic_rdists = rdists;
>
> - err = allocate_lpi_tables();
> + err = allocate_lpi_tables(resv);
> if (err)
> return err;
>
> --
> 2.23.0
>
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^ permalink raw reply related
* Re: [PATCH v1 0/6] Allow kexec reboot for GICv3 and device tree
From: Pavel Tatashin @ 2019-08-26 21:25 UTC (permalink / raw)
To: Marc Zyngier
Cc: Sasha Levin, Mark Rutland, Vladimir Murzin, kexec mailing list,
James Morris, LKML, James Morse, Linux ARM
In-Reply-To: <20190826201313.246208e9@why>
On Mon, Aug 26, 2019 at 3:13 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Mon, 26 Aug 2019 15:00:50 -0400
> Pavel Tatashin <pasha.tatashin@soleen.com> wrote:
>
> > Marc Zyngier added the support for kexec and GICv3 for EFI based systems.
> > However, it is still not possible todo on systems with device trees.
> >
> > Here is EFI fixes from Marc:
> > https://lore.kernel.org/lkml/20180921195954.21574-1-marc.zyngier@arm.com
> >
> > For Device Tree variant: lets allow reserve a memory region in interrupt
> > controller node, and use this property to allocate interrupt tables.
>
> There is no such thing as a "device tree variant". As long as your
> bootloader implements EFI, everything will work correctly, whether
> you're using DT, ACPI, or the anything else.
>
> This already works today, without any need to add anything to the
> kernel (I have systems using EDK II and u-boot, both implementing EFI,
> and I'm able to kexec without any issue). If your bootloader doesn't
> support EFI, here's a good opportunity to implement it!
Hi Marc,
Thank you very much for looking at this work.
Running Linux without EFI is common, and there are scenarios which
make it appropriate. As I understand most of embedded linux do not
have EFI enabled, and thus I do not see a reason why we would not
support a first class feature of Linux (kexec) on non-EFI bootloaders.
We (Microsoft) have a small highly secure device with a high uptime
requirement. The device also has PCIe and thus GICv3. The update for
this device relies on kexec. For a number of reasons, it was decided
to use U-Boot and Linux without EFI enabled. One of those reasons is
to improve boot performance, enabling EFI in U-Boot alone reduces the
boot performance by half a second. Our total reboot budget is under a
second which makes that half a second unacceptable. Also, adding EFI
support to kernel increases its size and there are security
implications from enabling more code both in U-Boot and Linux.
> --
> Without deviation from the norm, progress is not possible.
Totally agreed.
Thank you,
Pasha
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^ permalink raw reply
* [PATCH v2] ARM: dts: imx7d: sbc-iot-imx7: add basic board support
From: André Draszik @ 2019-08-26 20:51 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arm-kernel, devicetree, shawnguo, s.hauer, robh+dt,
grinberg, kernel, André Draszik, mark.rutland, festevam,
ilya, linux-imx
In-Reply-To: <20190826153800.35400-12-git@andred.net>
This is a forward-port of Compulab's downstream commit
against linux 4.9.11.
Original commit message:
The SB-IOT-iMX7 base board together with CL-SOM-iMX7
SoM forms SBC-IOT-iMX7 single board computer.
SBC-IOT-iMX7 is a single board computer optimized for
industrial control and monitoring, extensive wireless
and wired connectivity, ideal solution for
cost-sensitive systems. It is based on the Freescale
i.MX7 system-on-chip. SBC-IOT-iMX7 is implemented with
the CL-SOM-iMX7 System-on-Module providing most of the
functions,and SB-IOT-iMX7 carrier board providing
additional peripheral functions and connectors.
https://www.compulab.com/products/computer-on-modules/cl-som-imx7-freescale-i-mx-7-system-on-module/
https://www.compulab.com/products/sbcs/sbc-iot-imx7-nxp-i-mx-7-internet-of-things-single-board-computer/
This commit adds basic board support, including:
* SD-card (note that write-protect is not connected
on this carrier board)
* SPI (available on expansion header)
* i2c3 & i2c4 (including bus recovery information)
* additional UARTs
* all USB ports
Compared to the downtream commit, this commit doesn't
add / enable the PCIe and LCD interface, as PCIe
support needs an additional patch to the PCI controller
first, and I can't test the LCD.
Signed-off-by: André Draszik <git@andred.net>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
v2:
* use standard uart-has-rtscts instead of fsl,uart-has-rtscts
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts | 198 +++++++++++++++++++++++
2 files changed, 199 insertions(+)
create mode 100644 arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..78d51f2f9930 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -591,6 +591,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-pico-hobbit.dtb \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
+ imx7d-sbc-iot-imx7.dtb \
imx7d-sdb.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
diff --git a/arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts b/arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts
new file mode 100644
index 000000000000..5e72927b05be
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-sbc-iot-imx7.dts
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2017 CompuLab Ltd. - http://www.compulab.co.il/
+/*
+ * Support for CompuLab SBC-IOT-iMX7 Single Board Computer
+ */
+
+#include "imx7d-cl-som-imx7.dts"
+
+/ {
+ model = "CompuLab,SBC-IOT-iMX7";
+ compatible = "compulab,sbc-iot-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
+
+ reg_usb_vbus: regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ sda-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio1 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_recovery>;
+ sda-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ eeprom_iot@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+};
+
+&iomuxc {
+ pinctrl-1 = <&pinctrl_xpen>;
+
+ /* SB-IOT-iMX7 Xpension Header P7 */
+ pinctrl_xpen: xpengrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x34 /* P7-4 - gpio82 */
+ MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x34 /* P7-5 - gpio81 */
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0xf /* P7-7 */
+ MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0xf /* P7-8 */
+ MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0xf /* P7-6 */
+ >;
+ };
+
+ pinctrl_ecspi3_cs: ecspi3_cs_grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x34 /* P7-9 */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x4000000f /* P7-3 */
+ MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x4000000f /* P7-2 */
+ >;
+ };
+
+ pinctrl_i2c3_recovery: i2c3recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x4000000f /* P7-3 */
+ MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x4000000f /* P7-2 */
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x4000000f
+ MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x4000000f
+ >;
+ };
+
+ pinctrl_i2c4_recovery: i2c4recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x4000000f
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x4000000f
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x79 /* P7-12 */
+ MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x79 /* P7-13 */
+ MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x79 /* P7-11 */
+ MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x79 /* P7-10 */
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 /* RS232-TX */
+ MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 /* RS232-RX */
+ MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x79 /* RS232-RTS */
+ MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x79 /* RS232-CTS */
+ >;
+ };
+
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 /* R485-TX */
+ MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 /* R485-RX */
+ MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 /* R485-CTS */
+ MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 /* R485-TTS */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usbh {
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ status = "okay";
+};
--
2.23.0.rc1
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* [PATCH 10/20] clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Alexandre Torgue, Geert Uytterhoeven, linux-kernel,
Maxime Coquelin, moderated list:ARM/STM32 ARCHITECTURE,
moderated list:ARM/STM32 ARCHITECTURE
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Use the DIV_ROUND_CLOSEST() helper instead of open-coding the same
operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/renesas-ostm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
index 61d5f3b539ce..37c39b901bb1 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -221,7 +221,7 @@ static int __init ostm_init(struct device_node *np)
}
rate = clk_get_rate(ostm_clk);
- ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
+ ostm->ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
/*
* First probed device will be used as system clocksource. Any
--
2.17.1
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* [PATCH 09/20] arm64: dts: imx8mq: Add system counter node
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Abel Vesa, Anson Huang, Carlo Caione, Andrey Smirnov,
Fabio Estevam, Sascha Hauer, Angus Ainslie (Purism), linux-kernel,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Shawn Guo,
Guido Günther,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Lucas Stach
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..b4529773af51 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -635,6 +635,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_25m>;
+ clock-names = "per";
+ };
};
bus@30800000 { /* AIPS3 */
--
2.17.1
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* [PATCH 08/20] arm64: dts: imx8mm: Add system counter node
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jacky Bai, Anson Huang, Fabio Estevam, Sascha Hauer, linux-kernel,
Daniel Baluta, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Leonard Crestez, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 232a7412755a..89ef22a8f81e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -510,6 +510,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
};
aips3: bus@30800000 {
--
2.17.1
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^ permalink raw reply related
* [PATCH 07/20] clocksource/drivers/imx-sysctr: Add internal clock divider handle
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Anson Huang, Shawn Guo, Sascha Hauer, linux-kernel,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-imx-sysctr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d68066efb..b7c80a368a1b 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
+#define SYS_CTR_CLK_DIV 0x3
+
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
+ /* system counter clock is divided by 3 internally */
+ to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;
--
2.17.1
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^ permalink raw reply related
* [PATCH 06/20] clocksource/drivers/tcb_clksrc: Register delay timer
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches, linux-kernel,
moderated list:ARM/Microchip AT91 SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Implement and register delay timer to allow get_cycles() to work properly.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-atmel-tcb.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5e9317dc3d39..a642c23b2fba 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -429,7 +429,7 @@ config ATMEL_ST
config ATMEL_TCB_CLKSRC
bool "Atmel TC Block timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
+ depends on ARM && HAS_IOMEM
select TIMER_OF if OF
help
Support for Timer Counter Blocks on Atmel SoCs.
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 6ed31f9def7e..7427b07495a8 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -6,6 +6,7 @@
#include <linux/irq.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
@@ -125,6 +126,18 @@ static u64 notrace tc_sched_clock_read32(void)
return tc_get_cycles32(&clksrc);
}
+static struct delay_timer tc_delay_timer;
+
+static unsigned long tc_delay_timer_read(void)
+{
+ return tc_get_cycles(&clksrc);
+}
+
+static unsigned long notrace tc_delay_timer_read32(void)
+{
+ return tc_get_cycles32(&clksrc);
+}
+
#ifdef CONFIG_GENERIC_CLOCKEVENTS
struct tc_clkevt_device {
@@ -432,6 +445,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup ony channel 0 */
tcb_setup_single_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read32;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read32;
} else {
/* we have three clocks no matter what the
* underlying platform supports.
@@ -444,6 +458,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read;
}
/* and away we go! */
@@ -458,6 +473,9 @@ static int __init tcb_clksrc_init(struct device_node *node)
sched_clock_register(tc_sched_clock, 32, divided_rate);
+ tc_delay_timer.freq = divided_rate;
+ register_current_timer_delay(&tc_delay_timer);
+
return 0;
err_unregister_clksrc:
--
2.17.1
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* [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The newer Allwinner SoCs have a High Speed Timer supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun5i-a13-hstimer.txt | 26 ------
.../timer/allwinner,sun5i-a13-hstimer.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
deleted file mode 100644
index 2c5c1be78360..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Allwinner SoCs High Speed Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sun5i-a13-hstimer" or
- "allwinner,sun7i-a20-hstimer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
- one)
-- clocks: phandle to the source clock (usually the AHB clock)
-
-Optional properties:
-- resets: phandle to a reset controller asserting the timer
-
-Example:
-
-timer@1c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <0 51 1>,
- <0 52 1>,
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
- resets = <&ahb1rst 19>;
-};
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
new file mode 100644
index 000000000000..dfa0c41fd261
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A13 High-Speed Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun5i-a13-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+ - items:
+ - const: allwinner,sun6i-a31-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Timer 0 Interrupt
+ - description: Timer 1 Interrupt
+ - description: Timer 2 Interrupt
+ - description: Timer 3 Interrupt
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun5i-a13-hstimer
+
+then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@1c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1rst 19>;
+ };
+
+...
--
2.17.1
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* [PATCH 04/20] clocksource: sun4i: Add missing compatibles
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Maxime Ripard, Chen-Yu Tsai, linux-kernel,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-sun4i.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 65f38f6ca714..0ba8155b8287 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
+ sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
+ sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
sun4i_timer_init);
--
2.17.1
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* [PATCH 03/20] dt-bindings: timer: Add missing compatibles
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 7292a424092c..20adc1c8e9cc 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -14,6 +14,8 @@ properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
reg:
@@ -39,6 +41,30 @@ allOf:
minItems: 6
maxItems: 6
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-a23-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-v3s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
- if:
properties:
compatible:
--
2.17.1
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* [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The older Allwinner SoCs have a Timer supported in Linux, with a matching
Device Tree binding.
While the original binding only mentions one interrupt, the timer actually
has 6 of them.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 76 +++++++++++++++++++
.../bindings/timer/allwinner,sun4i-timer.txt | 19 -----
2 files changed, 76 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
new file mode 100644
index 000000000000..7292a424092c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-timer
+ - allwinner,suniv-f1c100s-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ List of timers interrupts
+
+ clocks:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun4i-a10-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,suniv-f1c100s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ timer {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
+ clocks = <&osc>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
deleted file mode 100644
index 3da9d515c03a..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be one of the following:
- "allwinner,sun4i-a10-timer"
- "allwinner,suniv-f1c100s-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x400>;
- interrupts = <22>;
- clocks = <&osc>;
-};
--
2.17.1
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* Re: [PATCH RESEND v11 7/8] open: openat2(2) syscall
From: sbaugh @ 2019-08-26 19:50 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-arch, sparclinux, linux-ia64, linux-parisc, linux-sh,
linux-api, linux-kernel, linux-mips, linuxppc-dev, linux-alpha,
linux-fsdevel, linux-arm-kernel
In-Reply-To: <20190820033406.29796-8-cyphar@cyphar.com>
Aleksa Sarai <cyphar@cyphar.com> writes:
> To this end, we introduce the openat2(2) syscall. It provides all of the
> features of openat(2) through the @how->flags argument, but also
> also provides a new @how->resolve argument which exposes RESOLVE_* flags
> that map to our new LOOKUP_* flags. It also eliminates the long-standing
> ugliness of variadic-open(2) by embedding it in a struct.
I don't like this usage of a structure in memory to pass arguments that
would fit in registers. This would be quite inconvenient for me as a
userspace developer.
Others have brought up issues with this: the issue of seccomp, and the
issue of mismatch between the userspace interface and the kernel
interface, are the most important for me. I want to add another,
admittedly somewhat niche, concern.
This interfaces requires a program to allocate memory (even on the
stack) just to pass arguments to the kernel which could be passed
without allocating that memory. That makes it more difficult and less
efficient to use this syscall in any case where memory is not so easily
allocatable: such as early program startup or assembly, where the stack
may be limited in size or not even available yet, or when injecting a
syscall while ptracing.
A struct-passing interface was needed for clone, since we ran out of
registers; but we have not run out of registers yet for openat, so it
would be nice to avoid this if we can. We can always expand later...
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^ permalink raw reply
* [PATCH v2] soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain
From: Jolly Shah @ 2019-08-26 20:30 UTC (permalink / raw)
To: matthias.bgg, andy.gross, shawnguo, geert+renesas,
bjorn.andersson, sean.wang, m.szyprowski, michal.simek
Cc: Tejas Patel, Jolly Shah, rajanv, linux-kernel, linux-arm-kernel
From: Tejas Patel <tejas.patel@xilinx.com>
For "0" requirement which is used to inform firmware that device is
not required currently by master, Versal PLM (Platform Loader and
Manager) which runs on Platform Management Controller and is responsible
platform management of devices that disables clock, power it down
and reset the device. genpd_power_off() is being called during runtime
suspend also. So, if any device goes to runtime suspend state during
resumes it needs to be re-initialized again. It is possible that
drivers do not reinitialize device upon resume from runtime suspend
every time ans so dont want it to be powered down or get reset
during runtime suspend.
In Versal PLM new PM_CAP_UNUSABLE capability is added, which disables
clock only and avoids power down and reset during runtime suspend. Power
and reset will be gated with core suspend.So, this patch sets
CAPABILITY_UNUSABLE requirement during gpd_power_off()
if platform is other than zynqmp.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
---
drivers/soc/xilinx/zynqmp_pm_domains.c | 10 ++++++++--
include/linux/firmware/xlnx-zynqmp.h | 3 ++-
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c
index 600f57c..23d90cb 100644
--- a/drivers/soc/xilinx/zynqmp_pm_domains.c
+++ b/drivers/soc/xilinx/zynqmp_pm_domains.c
@@ -2,7 +2,7 @@
/*
* ZynqMP Generic PM domain support
*
- * Copyright (C) 2015-2018 Xilinx, Inc.
+ * Copyright (C) 2015-2019 Xilinx, Inc.
*
* Davorin Mista <davorin.mista@aggios.com>
* Jolly Shah <jollys@xilinx.com>
@@ -25,6 +25,8 @@
static const struct zynqmp_eemi_ops *eemi_ops;
+static int min_capability;
+
/**
* struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
* @gpd: Generic power domain
@@ -106,7 +108,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain)
int ret;
struct pm_domain_data *pdd, *tmp;
struct zynqmp_pm_domain *pd;
- u32 capabilities = 0;
+ u32 capabilities = min_capability;
bool may_wakeup;
if (!eemi_ops->set_requirement)
@@ -283,6 +285,10 @@ static int zynqmp_gpd_probe(struct platform_device *pdev)
if (!domains)
return -ENOMEM;
+ if (!of_device_is_compatible(dev->parent->of_node,
+ "xlnx,zynqmp-firmware"))
+ min_capability = ZYNQMP_PM_CAPABILITY_UNUSABLE;
+
for (i = 0; i < ZYNQMP_NUM_DOMAINS; i++, pd++) {
pd->node_id = 0;
pd->gpd.name = kasprintf(GFP_KERNEL, "domain%d", i);
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 778abbb..b8a7c22 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -2,7 +2,7 @@
/*
* Xilinx Zynq MPSoC Firmware layer
*
- * Copyright (C) 2014-2018 Xilinx
+ * Copyright (C) 2014-2019 Xilinx
*
* Michal Simek <michal.simek@xilinx.com>
* Davorin Mista <davorin.mista@aggios.com>
@@ -46,6 +46,7 @@
#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
+#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
/*
* Firmware FPGA Manager flags
--
2.7.4
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^ permalink raw reply related
* Re: [RFC PATCH 5/7] arm64: smp: use generic SMP stop common code
From: Cristian Marussi @ 2019-08-26 19:58 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, mark.rutland, peterz, catalin.marinas, linux-kernel,
takahiro.akashi, james.morse, hidehiro.kawai.ez, tglx, will,
dave.martin, linux-arm-kernel
In-Reply-To: <20190826153236.GA9591@infradead.org>
Hi
On 8/26/19 4:32 PM, Christoph Hellwig wrote:
>> +config ARCH_USE_COMMON_SMP_STOP
>> + def_bool y if SMP
>
> The option belongs into common code and the arch code shoud only
> select it.
>
In fact that was my first approach, but then I noticed that in kernel/ topdir
there was no generic Kconfig but only subsystem specific ones:
Kconfig.freezer Kconfig.hz Kconfig.locks Kconfig.preempt
while instead looking into archs top level Kconfig, beside the usual arch/Kconfig selects,
I could find this similar sort of "reversed" approach in which the arch defined and
selected a CONFIG which was indeed then used only in common code like in:
20:37 $ egrep -R ARCH_HAS_CACHE_LINE_SIZE .
./arch/arc/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./arch/x86/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./arch/arm64/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./include/linux/cache.h:#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
20:39 $ egrep -R ARCH_HAS_KEXEC_PURGATORY .
./arch/powerpc/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/x86/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/s390/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/s390/purgatory/Makefile:obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += kexec-purgatory.o
./arch/s390/Kbuild:obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += purgatory/
./kernel/kexec_file.c: if (!IS_ENABLED(CONFIG_ARCH_HAS_KEXEC_PURGATORY))
so I thought it was an acceptable option and I went for it, not to introduce a new kernel/Kconfig.smp
just for this new config option; but in fact I could have missed the real reason underlying these two
different choices.
Thanks
Cristian
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^ permalink raw reply
* [PATCH v2 3/3] coresight: tmc-etr: Add barrier packets when moving offset forward
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
This patch adds barrier packets in the trace stream when the offset in the
data buffer needs to be moved forward. Otherwise the decoder isn't aware
of the break in the stream and can't synchronise itself with the trace
data.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Yabin Cui <yabinc@google.com>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 29 +++++++++++++++----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index bae47272de98..625882bc8b08 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1418,10 +1418,11 @@ static void tmc_free_etr_buffer(void *config)
* buffer to the perf ring buffer.
*/
static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long src_offset,
unsigned long to_copy)
{
long bytes;
- long pg_idx, pg_offset, src_offset;
+ long pg_idx, pg_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1430,7 +1431,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1478,7 +1478,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
void *config)
{
bool lost = false;
- unsigned long flags, size = 0;
+ unsigned long flags, offset, size = 0;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etr_perf_buffer *etr_perf = config;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1506,16 +1506,35 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
lost = etr_buf->full;
+ offset = etr_buf->offset;
size = etr_buf->len;
+
+ /*
+ * The ETR buffer may be bigger than the space available in the
+ * perf ring buffer (handle->size). If so advance the offset so that we
+ * get the latest trace data. In snapshot mode none of that matters
+ * since we are expected to clobber stale data in favour of the latest
+ * traces.
+ */
if (!etr_perf->snapshot && size > handle->size) {
- size = handle->size;
+ u32 mask = tmc_get_memwidth_mask(drvdata);
+
+ /*
+ * Make sure the new size is aligned in accordance with the
+ * requirement explained in function tmc_get_memwidth_mask().
+ */
+ size = handle->size & mask;
+ offset = etr_buf->offset + etr_buf->len - size;
+
+ if (offset >= etr_buf->size)
+ offset -= etr_buf->size;
lost = true;
}
/* Insert barrier packets at the beginning, if there was an overflow */
if (lost)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
- tmc_etr_sync_perf_buffer(etr_perf, size);
+ tmc_etr_sync_perf_buffer(etr_perf, offset, size);
/*
* In snapshot mode we simply increment the head by the number of byte
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 2/3] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
If less space is available in the perf ring buffer than the ETR buffer,
barrier packets inserted in the trace stream by tmc_sync_etr_buf() are
skipped over when the head of the buffer is moved forward, resulting in
traces that can't be decoded.
This patch decouples the process of syncing ETR buffers and the addition
of barrier packets in order to perform the latter once the offset in the
trace buffer has been properly computed.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4f000a03152e..bae47272de98 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
etr_buf->ops->sync(etr_buf, rrp, rwp);
-
- /* Insert barrier packets at the beginning, if there was an overflow */
- if (etr_buf->full)
- tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
@@ -1086,6 +1082,13 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
drvdata->sysfs_buf = NULL;
} else {
tmc_sync_etr_buf(drvdata);
+ /*
+ * Insert barrier packets at the beginning, if there was
+ * an overflow.
+ */
+ if (etr_buf->full)
+ tmc_etr_buf_insert_barrier_packet(etr_buf,
+ etr_buf->offset);
}
}
@@ -1502,11 +1505,16 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
CS_LOCK(drvdata->base);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ lost = etr_buf->full;
size = etr_buf->len;
if (!etr_perf->snapshot && size > handle->size) {
size = handle->size;
lost = true;
}
+
+ /* Insert barrier packets at the beginning, if there was an overflow */
+ if (lost)
+ tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
tmc_etr_sync_perf_buffer(etr_perf, size);
/*
@@ -1517,8 +1525,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
*/
if (etr_perf->snapshot)
handle->head += size;
-
- lost |= etr_buf->full;
out:
/*
* Don't set the TRUNCATED flag in snapshot mode because 1) the
--
2.17.1
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* [PATCH v2 1/3] coresight: tmc: Make memory width mask computation into a function
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
Make the computation of a memory mask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etf.c | 23 ++-------------
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 23b7ff00af5c..807416b75ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
* traces.
*/
if (!buf->snapshot && to_read > handle->size) {
- u32 mask = 0;
-
- /*
- * The value written to RRP must be byte-address aligned to
- * the width of the trace memory databus _and_ to a frame
- * boundary (16 byte), whichever is the biggest. For example,
- * for 32-bit, 64-bit and 128-bit wide trace memory, the four
- * LSBs must be 0s. For 256-bit wide trace memory, the five
- * LSBs must be 0s.
- */
- switch (drvdata->memwidth) {
- case TMC_MEM_INTF_WIDTH_32BITS:
- case TMC_MEM_INTF_WIDTH_64BITS:
- case TMC_MEM_INTF_WIDTH_128BITS:
- mask = GENMASK(31, 4);
- break;
- case TMC_MEM_INTF_WIDTH_256BITS:
- mask = GENMASK(31, 5);
- break;
- }
+ u32 mask = tmc_get_memwidth_mask(drvdata);
/*
* Make sure the new size is aligned in accordance with the
- * requirement explained above.
+ * requirement explained in function tmc_get_memwidth_mask().
*/
to_read = handle->size & mask;
/* Move the RAM read pointer up */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3055bf8e2236..1cf82fa58289 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
+{
+ u32 mask = 0;
+
+ /*
+ * When moving RRP or an offset address forward, the new values must
+ * be byte-address aligned to the width of the trace memory databus
+ * _and_ to a frame boundary (16 byte), whichever is the biggest. For
+ * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
+ * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
+ * be 0s.
+ */
+ switch (drvdata->memwidth) {
+ case TMC_MEM_INTF_WIDTH_32BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_64BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_128BITS:
+ mask = GENMASK(31, 4);
+ break;
+ case TMC_MEM_INTF_WIDTH_256BITS:
+ mask = GENMASK(31, 5);
+ break;
+ }
+
+ return mask;
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 9dbcdf453e22..71de978575f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
--
2.17.1
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