* [PATCH v2 7/7] arm64: dts: mt8183: tune disconnect threshold of u2phy
From: Chunfeng Yun @ 2019-08-28 7:34 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566977671-22191-1-git-send-email-chunfeng.yun@mediatek.com>
Set DISCTH to max-15, replace the default value 8, due to
default disconnect threshold is lower than USB SPEC define
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: new patch
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c20cc0e8c2b4..4f4d4a5ed422 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -435,6 +435,7 @@
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
+ mediatek,discth = <15>;
status = "okay";
};
--
2.23.0
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* [PATCH v2 6/7] arm64: dts: mt8183: enable USB remote wakeup
From: Chunfeng Yun @ 2019-08-28 7:34 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566977671-22191-1-git-send-email-chunfeng.yun@mediatek.com>
Enable USB remote wakeup for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 142ff52f0f42..077256f3397b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -150,6 +150,7 @@
&ssusb {
vusb33-supply = <&mt6358_vusb_reg>;
dr_mode = "host";
+ wakeup-source;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 28da334237c6..c20cc0e8c2b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -215,6 +215,13 @@
#clock-cells = <1>;
};
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8183-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -384,6 +391,7 @@
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.23.0
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* [RESEND PATCH] ARM: multi_v7_defconfig: enable MMP2 platform
From: Lubomir Rintel @ 2019-08-28 7:42 UTC (permalink / raw)
To: Olof Johansson
Cc: Lubomir Rintel, Russell King, linux-arm-kernel, linux-kernel
Marvell MMP/PXA/MMP2 platforms seem to be excluded from the defconfig
for no good reasons. Enable the DT-based boards and the modules for
their peripherals.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
arch/arm/configs/multi_v7_defconfig | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 6a40bc2ef2718..091693797ce98 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -51,6 +51,8 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MILBEAUT=y
CONFIG_ARCH_MILBEAUT_M10V=y
+CONFIG_ARCH_MMP=y
+CONFIG_MACH_MMP2_DT=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -278,6 +280,7 @@ CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_PXA27x=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_ST_KEYSCAN=y
CONFIG_KEYBOARD_SPEAR=y
@@ -312,6 +315,7 @@ CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_8250_OMAP=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250_PXA=m
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -590,6 +594,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MMP_CAMERA=m
CONFIG_VIDEO_STM32_DCMI=m
CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
CONFIG_VIDEO_S5P_FIMC=m
@@ -684,6 +689,9 @@ CONFIG_SND_ATMEL_SOC_PDMIC=m
CONFIG_SND_ATMEL_SOC_I2S=m
CONFIG_SND_BCM2835_SOC_I2S=m
CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_MMP_SOC=y
+CONFIG_SND_PXA_SOC_SSP=m
+CONFIG_SND_PXA910_SOC=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
@@ -722,6 +730,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_EHCI_MV=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_STI=y
CONFIG_USB_OHCI_EXYNOS=m
@@ -791,6 +800,7 @@ CONFIG_MMC_SDHCI_DOVE=y
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_S3C=y
CONFIG_MMC_SDHCI_PXAV3=y
+CONFIG_MMC_SDHCI_PXAV2=m
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_MMC_SDHCI_S3C_DMA=y
CONFIG_MMC_SDHCI_BCM_KONA=y
@@ -856,6 +866,7 @@ CONFIG_RTC_DRV_DA9063=m
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_DIGICOLOR=m
CONFIG_RTC_DRV_S3C=m
+CONFIG_RTC_DRV_SA1100=m
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_AT91RM9200=m
CONFIG_RTC_DRV_AT91SAM9=m
--
2.21.0
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* Re: [PATCH v2 0/5] ARM: make DaVinci part of the ARM v5 multiplatform build
From: Sekhar Nori @ 2019-08-28 7:44 UTC (permalink / raw)
To: Bartosz Golaszewski, Arnd Bergmann
Cc: David Lechner, Kevin Hilman, Linux Kernel Mailing List,
Bartosz Golaszewski, Hans Verkuil, Mauro Carvalho Chehab,
Linux ARM, Linux Media Mailing List
In-Reply-To: <CAMRc=MdCviMA4gakqFS3+F-nU2XkdmmZbCb-m1mBJdGRHufKGg@mail.gmail.com>
On 28/08/19 1:03 PM, Bartosz Golaszewski wrote:
> pon., 5 sie 2019 o 10:31 Bartosz Golaszewski <brgl@bgdev.pl> napisał(a):
>>
>> czw., 25 lip 2019 o 16:57 Arnd Bergmann <arnd@arndb.de> napisał(a):
>>>
>>> On Thu, Jul 25, 2019 at 3:13 PM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>>>>
>>>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>>
>>>> This series makes DaVinci part of the multiplatform build for ARM v5.
>>>>
>>>> First three patches fix build errors spotted and fixed by Arnd with v1.
>>>>
>>>> The fourth patch adds necessary bits and pieces for davinci to support
>>>> multiplatform build and the last one actually adds all davinci boards
>>>> to multi_v5_defconfig.
>>>>
>>>> Tested on da850-lcdk with both multi_v5 as well as davinci_all defconfigs.
>>>>
>>>> v1 -> v2:
>>>> - added patches from Arnd that fix build errors spotted when building
>>>> random configurations (much appreciated)
>>>> - rebased on top of v5.3-rc1
>>>
>>>> Arnd Bergmann (3):
>>>> staging: media/davinci_vpfe: fix pinmux setup compilation
>>>> media: davinci-vpbe: remove obsolete includes
>>>> davinci: fix sleep.S build error on ARMv4
>>>>
>>>> Bartosz Golaszewski (2):
>>>> ARM: davinci: support multiplatform build for ARM v5
>>>> ARM: multi_v5_defconfig: make DaVinci part of the ARM v5 multiplatform build
>>>
>>>
>>> Thanks a lot for reposting the series!
>>>
>>> I wonder how we shoud deal with the dependencies now that the two media
>>> patches got merged in the linux-media tree.
>>>
>>> It would be tempting to just merge the arch/arm/ changes, but that creates
>>> a bisection problem when the vpbe driver is enabled. I don't care
>>> about the staging driver really as that one is broken anyway, but including
>>> the "media: davinci-vpbe: remove obsolete includes" fix would be better
>>> here.
>>>
>>> Mauro, any idea for how to handle that? Should we apply an identical
>>> patch to the davinci tree, or maybe only have it the ARM tree and you
>>> drop it from your tree (I don't know if you have a rule against rebasing).
>>> Sorry for not coordinating with Bartosz before I sent the patch again
>>> earlier this week.
>>>
>>>
>>> Arnd
>>
>> Hi Arnd,
>>
>> is there any action required from me for this series?
>>
>> Bart
>
> Ping.
I dont think the multi-platform parts can be merged in v5.4 since we
dont have DM365 converted successfully to use clocksource driver yet.
But other parts of the series can be merged and hopefully we resolve
that pending issue for v5.5
Thanks,
Sekhar
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* Re: [PATCH 2/2] clk: mediatek: add pericfg clocks for MT8183
From: Chunfeng Yun @ 2019-08-28 7:47 UTC (permalink / raw)
To: Weiyi Lu
Cc: Mark Rutland, Nicolas Boichat, Ryder Lee, devicetree,
Stephen Boyd, Michael Turquette, linux-kernel, linux-clk,
Rob Herring, linux-mediatek, Matthias Brugger, Erin Lo,
linux-arm-kernel
In-Reply-To: <1566975333.24969.2.camel@mtksdaap41>
Hi Weiyi,
On Wed, 2019-08-28 at 14:55 +0800, Weiyi Lu wrote:
> On Wed, 2019-08-28 at 13:55 +0800, Chunfeng Yun wrote:
> > Add pericfg clocks for MT8183, it's used when support USB
> > remote wakeup
> >
> > Cc: Weiyi Lu <weiyi.lu@mediatek.com>
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > drivers/clk/mediatek/clk-mt8183.c | 35 ++++++++++++++++++++++++++
> > include/dt-bindings/clock/mt8183-clk.h | 4 +++
> > 2 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
> > index 1aa5f4059251..b19221bad0c9 100644
> > --- a/drivers/clk/mediatek/clk-mt8183.c
> > +++ b/drivers/clk/mediatek/clk-mt8183.c
> > @@ -999,6 +999,25 @@ static const struct mtk_gate infra_clks[] = {
> > "msdc50_0_sel", 24),
> > };
> >
> > +static const struct mtk_gate_regs peri_cg_regs = {
> > + .set_ofs = 0x20c,
> > + .clr_ofs = 0x20c,
> > + .sta_ofs = 0x20c,
> > +};
> > +
> > +#define GATE_PERI(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &peri_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> > +}
>
> Hi Chunfeng,
>
> I suggest
>
> #define GATE_PERI(_id, _name, _parent, _shift) \
> GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
> &mtk_clk_gate_ops_no_setclr_inv)
>
Good point, thanks
> > +
> > +static const struct mtk_gate peri_clks[] = {
> > + GATE_PERI(CLK_PERI_AXI, "periaxi", "axi_sel", 31),
> > +};
> > +
> > static const struct mtk_gate_regs apmixed_cg_regs = {
> > .set_ofs = 0x20,
> > .clr_ofs = 0x20,
> > @@ -1194,6 +1213,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
> > return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > }
> >
> > +static int clk_mt8183_peri_probe(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
> > +
> > + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
> > + clk_data);
> > +
> > + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +}
> > +
> > static int clk_mt8183_mcu_probe(struct platform_device *pdev)
> > {
> > struct clk_onecell_data *clk_data;
> > @@ -1223,6 +1255,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
> > }, {
> > .compatible = "mediatek,mt8183-infracfg",
> > .data = clk_mt8183_infra_probe,
> > + }, {
> > + .compatible = "mediatek,mt8183-pericfg",
> > + .data = clk_mt8183_peri_probe,
> > }, {
> > .compatible = "mediatek,mt8183-mcucfg",
> > .data = clk_mt8183_mcu_probe,
> > diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
> > index 0046506eb24c..a7b470b0ec8a 100644
> > --- a/include/dt-bindings/clock/mt8183-clk.h
> > +++ b/include/dt-bindings/clock/mt8183-clk.h
> > @@ -284,6 +284,10 @@
> > #define CLK_INFRA_FBIST2FPC 100
> > #define CLK_INFRA_NR_CLK 101
> >
> > +/* PERICFG */
> > +#define CLK_PERI_AXI 0
> > +#define CLK_PERI_NR_CLK 1
> > +
> > /* MFGCFG */
> > #define CLK_MFG_BG3D 0
> > #define CLK_MFG_NR_CLK 1
>
>
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* Re: [PATCH v2 0/5] ARM: make DaVinci part of the ARM v5 multiplatform build
From: Bartosz Golaszewski @ 2019-08-28 7:55 UTC (permalink / raw)
To: Sekhar Nori
Cc: David Lechner, Arnd Bergmann, Kevin Hilman, Bartosz Golaszewski,
Linux Kernel Mailing List, Hans Verkuil, Mauro Carvalho Chehab,
Linux ARM, Linux Media Mailing List
In-Reply-To: <27eb964a-bc6c-3a0d-c2c4-48e908465986@ti.com>
śr., 28 sie 2019 o 09:44 Sekhar Nori <nsekhar@ti.com> napisał(a):
>
> On 28/08/19 1:03 PM, Bartosz Golaszewski wrote:
> > pon., 5 sie 2019 o 10:31 Bartosz Golaszewski <brgl@bgdev.pl> napisał(a):
> >>
> >> czw., 25 lip 2019 o 16:57 Arnd Bergmann <arnd@arndb.de> napisał(a):
> >>>
> >>> On Thu, Jul 25, 2019 at 3:13 PM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> >>>>
> >>>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >>>>
> >>>> This series makes DaVinci part of the multiplatform build for ARM v5.
> >>>>
> >>>> First three patches fix build errors spotted and fixed by Arnd with v1.
> >>>>
> >>>> The fourth patch adds necessary bits and pieces for davinci to support
> >>>> multiplatform build and the last one actually adds all davinci boards
> >>>> to multi_v5_defconfig.
> >>>>
> >>>> Tested on da850-lcdk with both multi_v5 as well as davinci_all defconfigs.
> >>>>
> >>>> v1 -> v2:
> >>>> - added patches from Arnd that fix build errors spotted when building
> >>>> random configurations (much appreciated)
> >>>> - rebased on top of v5.3-rc1
> >>>
> >>>> Arnd Bergmann (3):
> >>>> staging: media/davinci_vpfe: fix pinmux setup compilation
> >>>> media: davinci-vpbe: remove obsolete includes
> >>>> davinci: fix sleep.S build error on ARMv4
> >>>>
> >>>> Bartosz Golaszewski (2):
> >>>> ARM: davinci: support multiplatform build for ARM v5
> >>>> ARM: multi_v5_defconfig: make DaVinci part of the ARM v5 multiplatform build
> >>>
> >>>
> >>> Thanks a lot for reposting the series!
> >>>
> >>> I wonder how we shoud deal with the dependencies now that the two media
> >>> patches got merged in the linux-media tree.
> >>>
> >>> It would be tempting to just merge the arch/arm/ changes, but that creates
> >>> a bisection problem when the vpbe driver is enabled. I don't care
> >>> about the staging driver really as that one is broken anyway, but including
> >>> the "media: davinci-vpbe: remove obsolete includes" fix would be better
> >>> here.
> >>>
> >>> Mauro, any idea for how to handle that? Should we apply an identical
> >>> patch to the davinci tree, or maybe only have it the ARM tree and you
> >>> drop it from your tree (I don't know if you have a rule against rebasing).
> >>> Sorry for not coordinating with Bartosz before I sent the patch again
> >>> earlier this week.
> >>>
> >>>
> >>> Arnd
> >>
> >> Hi Arnd,
> >>
> >> is there any action required from me for this series?
> >>
> >> Bart
> >
> > Ping.
>
> I dont think the multi-platform parts can be merged in v5.4 since we
> dont have DM365 converted successfully to use clocksource driver yet.
>
> But other parts of the series can be merged and hopefully we resolve
> that pending issue for v5.5
>
> Thanks,
> Sekhar
Actually I tested this without the clocksource conversion and it works
- the previous driver still selects relevant config options. But I
think you're right - it's worth picking up all the bug fixes from this
series and then merging the rest once dm365 issue is fixed.
Bart
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* [PATCH 00/10] ARM: dts: omap changes for IOMMU / reset support
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
Hi,
This series adds reset nodes for OMAP4+ family of SoCs, and fixes the
IOMMUs to support these also.
This series depends on the earlier posted clock series [1], PRM support
series [2], and the pdata quirks [3] and [4].
-Tero
[1] https://marc.info/?l=linux-clk&m=156697558331203&w=2
[2] https://marc.info/?l=linux-omap&m=156697680731569&w=2
[3] https://marc.info/?l=linux-omap&m=156517109506492&w=2
[4] https://marc.info/?l=linux-omap&m=156697839332083
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* [PATCH 01/10] ARM: dts: omap5: add IVA clkctrl nodes
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add clkctrtl nodes for Image and Video Accelerator subsystem for omap5.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 33e8dd905bff..f1ab2777e33e 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -1132,6 +1132,20 @@
};
};
+ iva_cm: iva_cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ iva_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
dss_cm: dss_cm@1400 {
compatible = "ti,omap4-cm";
reg = <0x1400 0x100>;
--
2.17.1
--
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* [PATCH 02/10] ARM: dts: dra7: add PRM nodes
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add PRM nodes for dra7 series of SoCs. These are initially used to
support reset control for some of the nodes, but will be extended
later to add powerdomain control and support for PRCM irqs among
other things.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 55 +++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 953f0ffce2a9..95147289be9c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -763,3 +763,58 @@
#include "dra7-l4.dtsi"
#include "dra7xx-clocks.dtsi"
+
+&prm {
+ prm_dsp1: prm@400 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ };
+
+ prm_ipu: prm@500 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x500 0x100>;
+ #reset-cells = <1>;
+ clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
+ };
+
+ prm_iva: prm@f00 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0xf00 0x100>;
+ };
+
+ prm_dsp2: prm@1b00 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ };
+
+ prm_eve1: prm@1b40 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1b40 0x40>;
+ };
+
+ prm_eve2: prm@1b80 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1b80 0x40>;
+ };
+
+ prm_eve3: prm@1bc0 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1bc0 0x40>;
+ };
+
+ prm_eve4: prm@1c00 {
+ compatible = "ti,dra7-prm-inst";
+ reg = <0x1c00 0x60>;
+ };
+};
--
2.17.1
--
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^ permalink raw reply related
* [PATCH 03/10] ARM: dts: omap4: add PRM nodes
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add PRM nodes for omap4 series of SoCs. These are initially used to
support reset control for some of the nodes, but will be extended
later to add powerdomain control and support for PRCM irqs among
other things.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap4-l4.dtsi | 2 +-
arch/arm/boot/dts/omap4.dtsi | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index bea05dc4ef0f..0977bc39955b 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -981,7 +981,7 @@
ranges = <0x0 0x6000 0x2000>;
prm: prm@0 {
- compatible = "ti,omap4-prm";
+ compatible = "ti,omap4-prm", "simple-bus";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index c43e52fd5f65..e377f66fc322 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -443,3 +443,32 @@
#include "omap4-l4.dtsi"
#include "omap4-l4-abe.dtsi"
#include "omap44xx-clocks.dtsi"
+
+&prm {
+ prm_tesla: prm@400 {
+ compatible = "ti,omap4-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap4-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ };
+
+ prm_ivahd: prm@f00 {
+ compatible = "ti,omap4-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
+ };
+
+ prm_device: prm@1b00 {
+ compatible = "ti,omap4-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+};
--
2.17.1
--
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^ permalink raw reply related
* [PATCH 04/10] ARM: dts: am33xx: Add PRM data
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add PRM data for AM33xx SoC. Initially this is used to provide reset
support, but will be expanded later to support also powerdomain control.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am33xx.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index e5c2f71a7c77..7448400a119e 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -445,3 +445,32 @@
#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"
+
+&prcm {
+ prm_per: prm@c00 {
+ compatible = "ti,am3-prm-inst";
+ reg = <0xc00 0x100>;
+ #reset-cells = <1>;
+ clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
+ };
+
+ prm_wkup: prm@d00 {
+ compatible = "ti,am3-prm-inst";
+ reg = <0xd00 0x100>;
+ #reset-cells = <1>;
+ clocks = <&l4_wkup_clkctrl AM3_WKUP_M3_CLKCTRL 0>;
+ };
+
+ prm_device: prm@f00 {
+ compatible = "ti,am3-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_gfx: prm@1100 {
+ compatible = "ti,am3-prm-inst";
+ reg = <0x1100 0x100>;
+ #reset-cells = <1>;
+ clocks = <&gfx_l3_clkctrl AM3_GFX_CLKCTRL 0>;
+ };
+};
--
2.17.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 05/10] ARM: dts: am43xx: Add PRM data
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add PRM data for AM43xx SoC. Initially this is used to provide reset
support, but will be expanded later to support also powerdomain control.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 55aff4db9c7c..4bd22c6ba3ff 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -353,3 +353,32 @@
#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"
+
+&prcm {
+ prm_gfx: prm@400 {
+ compatible = "ti,am4-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
+ };
+
+ prm_per: prm@800 {
+ compatible = "ti,am4-prm-inst";
+ reg = <0x800 0x100>;
+ #reset-cells = <1>;
+ clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
+ };
+
+ prm_wkup: prm@2000 {
+ compatible = "ti,am4-prm-inst";
+ reg = <0x2000 0x100>;
+ #reset-cells = <1>;
+ clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
+ };
+
+ prm_device: prm@4000 {
+ compatible = "ti,am4-prm-inst";
+ reg = <0x4000 0x100>;
+ #reset-cells = <1>;
+ };
+};
--
2.17.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
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^ permalink raw reply related
* [PATCH 06/10] ARM: dts: omap5: Add PRM data
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Add PRM data for OMAP54xx SoC. Initially this is used to provide reset
support, but will be expanded later to support also powerdomain control.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index edfd26c03462..c8bde171a949 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -412,3 +412,33 @@
#include "omap5-l4-abe.dtsi"
#include "omap54xx-clocks.dtsi"
+
+&prm {
+ prm_dsp: prm@400 {
+ compatible = "ti,omap5-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
+
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap5-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ };
+
+ prm_iva: prm@1200 {
+ compatible = "ti,omap5-prm-inst";
+ reg = <0x1200 0x100>;
+ #reset-cells = <1>;
+ clocks = <&iva_clkctrl OMAP5_IVA_CLKCTRL 0>;
+ };
+
+ prm_device: prm@1c00 {
+ compatible = "ti,omap5-prm-inst";
+ reg = <0x1c00 0x100>;
+ #reset-cells = <1>;
+ };
+};
--
2.17.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 08/10] ARM: dts: dra74x: convert IOMMUs to use ti-sysc
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Convert dra74x IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra74x.dtsi | 71 +++++++++++++++++++++++++++--------
1 file changed, 55 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index d1b5b76bc5a8..c5abc436ca1f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -66,24 +66,63 @@
};
};
- mmu0_dsp2: mmu@41501000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41501000 0x100>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x0>;
- status = "disabled";
+ target-module@41501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41501000 0x4>,
+ <0x41501010 0x4>,
+ <0x41501014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41501000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu0_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x0>;
+ };
};
- mmu1_dsp2: mmu@41502000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41502000 0x100>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x1>;
- status = "disabled";
+ target-module@41502000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41502000 0x4>,
+ <0x41502010 0x4>,
+ <0x41502014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41502000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ };
};
};
};
--
2.17.1
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply related
* [PATCH 07/10] ARM: dts: dra7: convert IOMMUs to use ti-sysc
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Convert dra7 IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 140 +++++++++++++++++++++++++++---------
1 file changed, 108 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 95147289be9c..98c01f204a1a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -377,44 +377,120 @@
ti,hwmods = "dmm";
};
- mmu0_dsp1: mmu@40d01000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d01000 0x100>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x0>;
- status = "disabled";
+ target-module@40d01000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d01000 0x4>,
+ <0x40d01010 0x4>,
+ <0x40d01014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d01000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu0_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ };
};
- mmu1_dsp1: mmu@40d02000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d02000 0x100>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x1>;
- status = "disabled";
+ target-module@40d02000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d02000 0x4>,
+ <0x40d02010 0x4>,
+ <0x40d02014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d02000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ };
};
- mmu_ipu1: mmu@58882000 {
- compatible = "ti,dra7-iommu";
- reg = <0x58882000 0x100>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu1";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- status = "disabled";
+ target-module@58882000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58882000 0x4>,
+ <0x58882010 0x4>,
+ <0x58882014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_ipu 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x58882000 0x100>;
+
+ mmu_ipu1: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
- mmu_ipu2: mmu@55082000 {
- compatible = "ti,dra7-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu2";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- status = "disabled";
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55082000 0x100>;
+
+ mmu_ipu2: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
abb_mpu: regulator-abb-mpu {
--
2.17.1
--
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^ permalink raw reply related
* [PATCH 09/10] ARM: dts: omap4: convert IOMMUs to use ti-sysc
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Convert omap4 IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap4-l4.dtsi | 11 ++++++---
arch/arm/boot/dts/omap4.dtsi | 43 +++++++++++++++++++++------------
2 files changed, 36 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index 0977bc39955b..7eca6cdbbdd9 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -321,7 +321,6 @@
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -335,12 +334,18 @@
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_tesla 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e377f66fc322..f28fe1c36b0c 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -173,14 +173,6 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
- };
-
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
@@ -206,14 +198,35 @@
/* No child device binding, driver in staging */
};
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
+
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus1";
--
2.17.1
--
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^ permalink raw reply related
* [PATCH 10/10] ARM: dts: omap5: convert IOMMUs to use ti-sysc
From: Tero Kristo @ 2019-08-28 7:56 UTC (permalink / raw)
To: linux-omap, tony; +Cc: linux-arm-kernel
In-Reply-To: <20190828075644.4493-1-t-kristo@ti.com>
Convert omap5 IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
arch/arm/boot/dts/omap5-l4.dtsi | 11 ++++++---
arch/arm/boot/dts/omap5.dtsi | 40 +++++++++++++++++++++------------
2 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index 0960348002ad..80c2d2fcc03b 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -349,7 +349,6 @@
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -364,12 +363,18 @@
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_dsp 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index c8bde171a949..05929d59b0af 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -186,21 +186,33 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
- };
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
dmm@4e000000 {
--
2.17.1
--
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^ permalink raw reply related
* Re: [PATCH 0/2] drm/meson: add resume/suspend hooks
From: Neil Armstrong @ 2019-08-28 8:05 UTC (permalink / raw)
To: Kevin Hilman, dri-devel; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel
In-Reply-To: <7h5zmixvrz.fsf@baylibre.com>
On 27/08/2019 21:17, Kevin Hilman wrote:
> Neil Armstrong <narmstrong@baylibre.com> writes:
>
>> This serie adds the resume/suspend hooks in the Amlogic Meson VPU main driver
>> and the DW-HDMI Glue driver to correctly save state and disable HW before
>> suspend, and succesfully re-init the HW to recover functionnal display
>> after resume.
>>
>> This serie has been tested on Amlogic G12A based SEI510 board, using
>> the newly accepted VRTC driver and the rtcwake utility.
>
> Tested-by: Kevin Hilman <khilman@baylibre.com>
>
> Tested on my G12A SEI510 board, and I verified that it fixes
> suspend/resume issues previously seen.
>
> Kevin
>
Thanks,
Applying to drm-misc-next (for v5.5), with a typo fix in the first patch commit log:
s/suspens/suspend
Neil
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^ permalink raw reply
* Re: [PATCH] arm64: KVM: Device mappings should be execute-never
From: Marc Zyngier @ 2019-08-28 8:10 UTC (permalink / raw)
To: James Morse, linux-arm-kernel, kvmarm
Cc: Catalin Marinas, Will Deacon, Julien Thierry, Suzuki K Poulose
In-Reply-To: <20190827170646.17105-1-james.morse@arm.com>
On 27/08/2019 18:06, James Morse wrote:
> Since commit 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in
> Stage-2 if CTR_EL0.DIC is set"), KVM has stopped marking normal memory
> as execute-never at stage2 when the system supports D->I Coherency at
> the PoU. This avoids KVM taking a trap when the page is first executed,
> in order to clean it to PoU.
>
> The patch that added this change also wrapped PAGE_S2_DEVICE mappings
> up in this too. The upshot is, if your CPU caches support DIC ...
> you can execute devices.
Amazing. And we all missed that, while it should have been obvious. Oh
well...
>
> Revert the PAGE_S2_DEVICE change so PTE_S2_XN is always used
> directly.
>
> Fixes: 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set")
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> arch/arm64/include/asm/pgtable-prot.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index 92d2e9f28f28..9a21b84536f2 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -77,7 +77,7 @@
> })
>
> #define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
> -#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
> +#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
>
> #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
> #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
>
Applied to -next.
Thanks,
M.
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^ permalink raw reply
* Re: [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS
From: Jerome Brunet @ 2019-08-28 8:11 UTC (permalink / raw)
To: Kevin Hilman, Neil Armstrong
Cc: linux-amlogic, linux-kernel, linux-clk, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <7h1rx6uti8.fsf@baylibre.com>
On Tue 27 Aug 2019 at 15:35, Kevin Hilman <khilman@baylibre.com> wrote:
> Kevin Hilman <khilman@baylibre.com> writes:
>
>> Jerome Brunet <jbrunet@baylibre.com> writes:
>>
>>> On Mon 26 Aug 2019 at 09:25, Neil Armstrong <narmstrong@baylibre.com> wrote:
>>>
>>>> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
>>>> enables DVFS on the SM1 SoC for the SEI610 board.
>>>>
>>>> The SM1 Clock structure is slightly different because of the Cortex-A55
>>>> core used, having the capability for each core of a same cluster to run
>>>> at a different frequency thanks to the newly used DynamIQ Shared Unit.
>>>>
>>>> This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit,
>>>> with a bypass mux to use the CPU0 instead of the dedicated trees.
>>>>
>>>> The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only.
>>>>
>>>> The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike
>>>> G12A only a single version of the SoC is available.
>>>>
>>>> Dependencies:
>>>> - patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie,
>>>> but is not a strong dependency, it will work without
>>>>
>>>> Changes since v1:
>>>> - exposed GP1, DSU and CPU 1,2,3 clock in patch 1
>>>>
>>>> Neil Armstrong (5):
>>>> dt-bindings: clk: meson: add sm1 periph clock controller bindings
>>>> clk: meson: g12a: add support for SM1 GP1 PLL
>>>> clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
>>>> clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
>>>> arm64: dts: meson-sm1-sei610: enable DVFS
>>>>
>>>> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
>>>> .../boot/dts/amlogic/meson-sm1-sei610.dts | 59 +-
>>>> arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++
>>>> drivers/clk/meson/g12a.c | 544 ++++++++++++++++++
>>>> drivers/clk/meson/g12a.h | 24 +-
>>>> include/dt-bindings/clock/g12a-clkc.h | 5 +
>>>> 6 files changed, 697 insertions(+), 5 deletions(-)
>>>
>>> Applied 1 to 4
>>
>> Will there be a stable tag I can use for that so I can apply patch 5?
>
> Ah, I should've finished reading the list before asking. I now see your
> clock PR. I'll use this tag[1] unless there's a different one I should
> use.
I just pushed clk-meson-dt-v5.4-3 for you, with dt changes only.
>
> Kevin
>
> [1] git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.4-2
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* Re: [PATCH 2/2] dt-bindings: imx6q-pcie: add "fsl,pcie-phy-refclk-internal" for i.MX7D
From: André Draszik @ 2019-08-28 8:17 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Richard Zhu, Fabio Estevam,
Sascha Hauer, linux-kernel, NXP Linux Team,
Pengutronix Kernel Team, linux-pci, Bjorn Helgaas, Shawn Guo,
linux-arm-kernel, Lucas Stach
In-Reply-To: <20190827155626.GA29948@bogus>
Hi Rob,
On Tue, 2019-08-27 at 10:56 -0500, Rob Herring wrote:
> On Tue, Aug 13, 2019 at 11:37:59AM +0100, André Draszik wrote:
> > The i.MX7D variant of the IP can use either an external
> > crystal oscillator input or an internal clock input as
> > a reference clock input for the PCIe PHY.
> >
> > Document the optional property 'fsl,pcie-phy-refclk-internal'
> >
> > Signed-off-by: André Draszik <git@andred.net>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: NXP Linux Team <linux-imx@nxp.com>
> > Cc: linux-pci@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > index a7f5f5afa0e6..985d7083df9f 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > @@ -56,6 +56,11 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
> > - "turnoff"
> > - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
>
> Not sure how this got in, but why is the phy binding not used here?
>
> >
> > +Additional optional properties for imx7d-pcie:
> > +- fsl,pcie-phy-refclk-internal: If present then an internal PLL input is used
> > + as PCIe PHY reference clock source. By default an external ocsillator input
> > + is used.
>
> Can't the clock binding and maybe 'assigned-clocks' be used here?
>
> Also, this is a property of the PHY, so it belongs in the PHY's node.
Thanks for pointing this out. I'll have a look.
Andre'
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* Re: [PATCH RESEND v2 1/6] dt-bindings: watchdog: Add YAML schemas for the generic watchdog bindings
From: Maxime Ripard @ 2019-08-28 8:18 UTC (permalink / raw)
To: linux, wim
Cc: Mark Rutland, devicetree, linux-watchdog, linux-kernel,
Chen-Yu Tsai, Rob Herring, Frank Rowand, linux-arm-kernel
In-Reply-To: <20190821143835.7294-1-mripard@kernel.org>
[-- Attachment #1.1: Type: text/plain, Size: 439 bytes --]
On Wed, Aug 21, 2019 at 04:38:30PM +0200, Maxime Ripard wrote:
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The watchdogs have a bunch of generic properties that are needed in a
> device tree. Add a YAML schemas for those.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Ping?
Maxime
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Embedded Linux and Kernel engineering
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* Re: [PATCH v2 2/2] ARM: exynos: Enable support for ARM architected timers
From: Marek Szyprowski @ 2019-08-28 8:22 UTC (permalink / raw)
To: Marc Zyngier
Cc: Chanwoo Choi, linux-samsung-soc, Krzysztof Kozlowski,
linux-arm-kernel, Bartlomiej Zolnierkiewicz
In-Reply-To: <d286053b6f4b4783d0638dc2dbd5858e@www.loen.fr>
Hi Marc,
On 2019-08-26 12:49, Marc Zyngier wrote:
> On 2019-08-26 11:31, Marek Szyprowski wrote:
>> ARM architected timer can be used together with Exynos MultiCore Timer
>> driver, so enable support for it. Support for ARM architected timers is
>> essential for enabling proper KVM support.
>
> How can you say that this is to "enable KVM support", while in the
> previous
> patch, you set "arm,cpu-registers-not-fw-configured" which implies
> that you're
> booting in secure mode with the timer's CP15 registers left to
> undefined values?
Thanks for asking a good question!
I've did my KVM research mainly on Exynos5422-based OdroidXU3/XU4 boards
family. After some recently merged patches they all now boot correctly
in HYP mode.
On all of those boards arch timers are indeed partially not configured
(CNTFRQ is zero). I was convinced that this also requires adding
"arm,cpu-registers-not-fw-configured" property to make timers fully
operational, but it looks that this only disables VDSO on arm32 and
switches to phys timers if booted in SVC mode.
I've checked and KVM works fine on the mentioned boards regardless of
the "arm,cpu-registers-not-fw-configured" property. The only issue is
the lack of proper value in CNTFRQ register, what requires patching
timer node by adding "clock-frequency = <24000000>" property also to the
guest dtb.
I've did my test of KVM with QEMU emulator version 3.1.0 (Debian
1:3.1+dfsg-8) virtualizing vexpress-a15 machine, with patched
vexpress-v2p-ca15-tc1.dtb and the following command line on OdroidXU3:
taskset 0x30 qemu-system-arm -M vexpress-a15 -smp 2 -cpu host
-enable-kvm -m 512 -kernel zImage -dtb vexpress-v2p-ca15-tc1.dtb -append
"console=ttyAMA0 root=/dev/vda rw rootwait" -serial stdio -display none
-monitor null -device virtio-blk-device,drive=virtio-blk -drive
file=rootfs.raw,id=virtio-blk,if=none,format=raw -netdev user,id=user
-device virtio-net-device,netdev=user
Then I've checked other boards that are capable of running in HYP mode.
Exynos5250 Arndale board with mainline uboot boots to HYP fine.
Exynos5250-based Snow Chromebook with stock bootloader boots only to SVC
mode. There exists a way to upgrade uboot to enable HYP, but this
requires HW fix to enable write access to nvram. Both boards however
also don't configure CNTFRQ register, but otherwise the arch timer
registers seems to be configured fine (virt counters are in sync between
CPUs).
The last group of boards are Exynos5420-based Pit and Exynos5800-based
Pi Chromebooks. In theory they are capable in running HYP mode with a
patched bootloader, but stock bootloader boots only to SVC. They also
truly don't have arch timer registers correctly configured, as virt
timers are out of sync between CPUs.
I will send v3 with "arm,cpu-registers-not-fw-configured" property moved
from the timer nodes in dtsi files to respective effected boards.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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* [PATCH v2 2/2] clk: mediatek: add pericfg clocks for MT8183
From: Chunfeng Yun @ 2019-08-28 8:22 UTC (permalink / raw)
To: Rob Herring, Stephen Boyd
Cc: Mark Rutland, devicetree, Ryder Lee, Weiyi Lu, Michael Turquette,
linux-kernel, linux-clk, Chunfeng Yun, Nicolas Boichat,
linux-mediatek, Matthias Brugger, Erin Lo, linux-arm-kernel
In-Reply-To: <1566980533-28282-1-git-send-email-chunfeng.yun@mediatek.com>
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2:
use GATE_MTK to define GATE_PERI suggested by Weiyi
---
drivers/clk/mediatek/clk-mt8183.c | 30 ++++++++++++++++++++++++++
include/dt-bindings/clock/mt8183-clk.h | 4 ++++
2 files changed, 34 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 1aa5f4059251..f3765bbdbe85 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -999,6 +999,20 @@ static const struct mtk_gate infra_clks[] = {
"msdc50_0_sel", 24),
};
+static const struct mtk_gate_regs peri_cg_regs = {
+ .set_ofs = 0x20c,
+ .clr_ofs = 0x20c,
+ .sta_ofs = 0x20c,
+};
+
+#define GATE_PERI(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate peri_clks[] = {
+ GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
+};
+
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x20,
.clr_ofs = 0x20,
@@ -1194,6 +1208,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
+static int clk_mt8183_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
static int clk_mt8183_mcu_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
@@ -1223,6 +1250,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
}, {
.compatible = "mediatek,mt8183-infracfg",
.data = clk_mt8183_infra_probe,
+ }, {
+ .compatible = "mediatek,mt8183-pericfg",
+ .data = clk_mt8183_peri_probe,
}, {
.compatible = "mediatek,mt8183-mcucfg",
.data = clk_mt8183_mcu_probe,
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
index 0046506eb24c..a7b470b0ec8a 100644
--- a/include/dt-bindings/clock/mt8183-clk.h
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -284,6 +284,10 @@
#define CLK_INFRA_FBIST2FPC 100
#define CLK_INFRA_NR_CLK 101
+/* PERICFG */
+#define CLK_PERI_AXI 0
+#define CLK_PERI_NR_CLK 1
+
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1
--
2.23.0
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* [PATCH v2 1/2] dt-bindings: clock: mediatek: add pericfg for MT8183
From: Chunfeng Yun @ 2019-08-28 8:22 UTC (permalink / raw)
To: Rob Herring, Stephen Boyd
Cc: Mark Rutland, devicetree, Ryder Lee, Weiyi Lu, Michael Turquette,
linux-kernel, linux-clk, Chunfeng Yun, Nicolas Boichat,
linux-mediatek, Matthias Brugger, Erin Lo, linux-arm-kernel
This patch adds binding of pericfg for MT8183.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
.../devicetree/bindings/arm/mediatek/mediatek,pericfg.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 4c7e478117a0..ecf027a9003a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7629-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
+ - "mediatek,mt8183-pericfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
--
2.23.0
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