* [PATCH v7 01/13] dt-bindings: mediatek: Add property to mt8183 smi-common
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..01744ec 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -20,7 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
+ "mediatek,mt8183-smi-common", "syscon"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
--
1.8.1.1.dirty
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* [PATCH v7 07/13] soc: mediatek: Refactor bus protection control
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Put bus protection enable and disable control in separate functions.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 44 ++++++++++++++++++++++++++-------------
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index ad0f619..fb2b027 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -274,6 +274,30 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
+static int scpsys_bus_protect_enable(struct scp_domain *scpd)
+{
+ struct scp *scp = scpd->scp;
+
+ if (!scpd->data->bus_prot_mask)
+ return 0;
+
+ return mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+}
+
+static int scpsys_bus_protect_disable(struct scp_domain *scpd)
+{
+ struct scp *scp = scpd->scp;
+
+ if (!scpd->data->bus_prot_mask)
+ return 0;
+
+ return mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
@@ -316,13 +340,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_pwr_ack;
- if (scpd->data->bus_prot_mask) {
- ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- if (ret)
- goto err_pwr_ack;
- }
+ ret = scpsys_bus_protect_disable(scpd);
+ if (ret < 0)
+ goto err_pwr_ack;
return 0;
@@ -344,13 +364,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
u32 val;
int ret, tmp;
- if (scpd->data->bus_prot_mask) {
- ret = mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- if (ret)
- goto out;
- }
+ ret = scpsys_bus_protect_enable(scpd);
+ if (ret < 0)
+ goto out;
ret = scpsys_sram_disable(scpd, ctl_addr);
if (ret < 0)
--
1.8.1.1.dirty
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* [PATCH v7 12/13] soc: mediatek: Add MT8183 scpsys support
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 226 ++++++++++++++++++++++++++++++++++++++
1 file changed, 226 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 85c6bf4..e072810 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -1129,6 +1130,217 @@ static void mtk_register_power_domains(struct platform_device *pdev,
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
};
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .basic_clk_id = {"audio", "audio1", "audio2"},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(13) | BIT(14), BIT(13) | BIT(14)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_id = {"mfg"},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(19) | BIT(20) | BIT(21),
+ BIT(19) | BIT(20) | BIT(21)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(21) | BIT(22), BIT(21) | BIT(22)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_id = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(16) | BIT(17), BIT(16) | BIT(17)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ GENMASK(7, 0), GENMASK(7, 0)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"cam"},
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(4) | BIT(5) | BIT(9) | BIT(13),
+ BIT(4) | BIT(5) | BIT(9) | BIT(13)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(28), BIT(28)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(11), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(3) | BIT(4), BIT(3) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"isp"},
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(3) | BIT(8), BIT(3) | BIT(8)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(2), BIT(2)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(7), BIT(7)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(1), BIT(1)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_id = {"vpu", "vpu1"},
+ .subsys_clk_prefix = "vpu",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ GENMASK(9, 6) | BIT(12),
+ GENMASK(9, 6) | BIT(12)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(27), BIT(27)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(5) | BIT(6), BIT(5) | BIT(6)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"vpu2"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(6), BIT(6)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(0) | BIT(2) | BIT(4),
+ BIT(0) | BIT(2) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"vpu3"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(7), BIT(7)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(1) | BIT(3) | BIT(5),
+ BIT(1) | BIT(3) | BIT(5)),
+ },
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
static const struct scp_soc_data mt2701_data = {
.domains = scp_domain_data_mt2701,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
@@ -1195,6 +1407,17 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.bus_prot_reg_update = true,
};
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184
+ }
+};
+
/*
* scpsys driver init
*/
@@ -1219,6 +1442,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt8173-scpsys",
.data = &mt8173_data,
}, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
/* sentinel */
}
};
--
1.8.1.1.dirty
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* [PATCH v7 03/13] soc: mediatek: Refactor polling timeout and documentation
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 503222d..e97fc0e 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,7 +21,7 @@
#include <dt-bindings/power/mt8173-power.h>
#define MTK_POLL_DELAY_US 10
-#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
@@ -108,6 +108,17 @@ enum clk_id {
#define MAX_CLKS 3
+/**
+ * struct scp_domain_data - scp domain data for power on/off flow
+ * @name: The domain name.
+ * @sta_mask: The mask for power on/off status bit.
+ * @ctl_offs: The offset for main power control register.
+ * @sram_pdn_bits: The mask for sram power control bits.
+ * @sram_pdn_ack_bits: The mask for sram power control acked bits.
+ * @bus_prot_mask: The mask for single step bus protection.
+ * @clk_id: The basic clocks required by this power domain.
+ * @caps: The flag for active wake-up action.
+ */
struct scp_domain_data {
const char *name;
u32 sta_mask;
--
1.8.1.1.dirty
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* [PATCH v7 00/13] Mediatek MT8183 scpsys support
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
This series is based on v5.3-rc1 with MT8183 SMI dt-binding patch v11[1].
[1] [v11,01/23] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
(https://patchwork.kernel.org/patch/11112769/)
changes since v6:
- remove the patch of SPDX license identifier because it's already fixed
changes since v5:
- fix documentation in [PATCH 04/14]
- remove useless variable checking and reuse API of clock control in [PATCH 06/14]
- coding style fix of bus protection control in [PATCH 08/14]
- fix naming of new added data in [PATCH 09/14]
- small refactor of multiple step bus protection control in [PATCH 10/14]
changes since v4:
- add property to mt8183 smi-common
- seperate refactor patches and new add function
- add power controller device node
Weiyi Lu (13):
dt-bindings: mediatek: Add property to mt8183 smi-common
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Refactor polling timeout and documentation
soc: mediatek: Refactor regulator control
soc: mediatek: Refactor clock control
soc: mediatek: Refactor sram control
soc: mediatek: Refactor bus protection control
soc: mediatek: Add basic_clk_id to scp_power_data
soc: mediatek: Add multiple step bus protection control
soc: mediatek: Add subsys clock control for bus protection
soc: mediatek: Add extra sram control
soc: mediatek: Add MT8183 scpsys support
arm64: dts: Add power controller device node of MT8183
.../mediatek,smi-common.txt | 2 +-
.../bindings/soc/mediatek/scpsys.txt | 14 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 +++
drivers/soc/mediatek/mtk-scpsys.c | 575 +++++++++++++++---
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/scpsys-ext.h | 39 ++
8 files changed, 741 insertions(+), 78 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/dt-bindings/power/mt8183-power.h
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
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* [PATCH v7 09/13] soc: mediatek: Add multiple step bus protection control
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common. Also add new APIs for multiple
step bus protection control with more customized arguments.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-scpsys.c | 39 +++++++++----
include/linux/soc/mediatek/scpsys-ext.h | 39 +++++++++++++
4 files changed, 168 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b017330..b442be9 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
new file mode 100644
index 0000000..b24321e
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <Owen.Chen@mediatek.com>
+ */
+#include <linux/ktime.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
+
+static int set_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_set, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_set)
+ regmap_write(map, reg_set, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, mask);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, (val & ack_mask) == ack_mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int clear_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_clr, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_clr)
+ regmap_write(map, reg_clr, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, 0);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, !(val & ack_mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = 0; i < MAX_STEPS; i++) {
+ struct regmap *map;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = set_bus_protection(map,
+ bp_table[i].mask, bp_table[i].mask,
+ bp_table[i].set_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = MAX_STEPS - 1; i >= 0; i--) {
+ struct regmap *map;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = clear_bus_protection(map,
+ bp_table[i].mask, bp_table[i].clr_ack_mask,
+ bp_table[i].clr_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index d31e1a4..f25101f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -12,6 +12,7 @@
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
@@ -120,6 +121,7 @@ enum clk_id {
* @basic_clk_id: provide the same purpose with field "clk_id"
* by declaring basic clock prefix name rather than clk_id.
* @caps: The flag for active wake-up action.
+ * @bp_table: The mask table for multiple step bus protection.
*/
struct scp_domain_data {
const char *name;
@@ -131,6 +133,7 @@ struct scp_domain_data {
enum clk_id clk_id[MAX_CLKS];
const char *basic_clk_id[MAX_CLKS];
u8 caps;
+ struct bus_prot bp_table[MAX_STEPS];
};
struct scp;
@@ -154,6 +157,7 @@ struct scp {
struct device *dev;
void __iomem *base;
struct regmap *infracfg;
+ struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
bool bus_prot_reg_update;
};
@@ -281,24 +285,28 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
@@ -466,6 +474,17 @@ static struct scp *init_scp(struct platform_device *pdev,
return ERR_CAST(scp->infracfg);
}
+ scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "smi_comm");
+
+ if (scp->smi_common == ERR_PTR(-ENODEV)) {
+ scp->smi_common = NULL;
+ } else if (IS_ERR(scp->smi_common)) {
+ dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
+ PTR_ERR(scp->smi_common));
+ return ERR_CAST(scp->smi_common);
+ }
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
new file mode 100644
index 0000000..3e5b84d
--- /dev/null
+++ b/include/linux/soc/mediatek/scpsys-ext.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
+#define __SOC_MEDIATEK_SCPSYS_EXT_H
+
+#define MAX_STEPS 4
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, _clr_ack_mask) { \
+ .type = _type, \
+ .set_ofs = _set_ofs, \
+ .clr_ofs = _clr_ofs, \
+ .en_ofs = _en_ofs, \
+ .sta_ofs = _sta_ofs, \
+ .mask = _mask, \
+ .clr_ack_mask = _clr_ack_mask, \
+ }
+
+enum regmap_type {
+ INVALID_TYPE = 0,
+ IFR_TYPE,
+ SMI_TYPE,
+};
+
+struct bus_prot {
+ enum regmap_type type;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 en_ofs;
+ u32 sta_ofs;
+ u32 mask;
+ u32 clr_ack_mask;
+};
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+
+#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
--
1.8.1.1.dirty
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* [PATCH v7 05/13] soc: mediatek: Refactor clock control
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Put clock enable and disable control in separate function.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 45 ++++++++++++++++++++++++---------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index aed540d..73e4a1a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -207,6 +207,29 @@ static int scpsys_regulator_disable(struct scp_domain *scpd)
return regulator_disable(scpd->supply);
}
+static void scpsys_clk_disable(struct clk *clk[], int max_num)
+{
+ int i;
+
+ for (i = max_num - 1; i >= 0; i--)
+ clk_disable_unprepare(clk[i]);
+}
+
+static int scpsys_clk_enable(struct clk *clk[], int max_num)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < max_num && clk[i]; i++) {
+ ret = clk_prepare_enable(clk[i]);
+ if (ret) {
+ scpsys_clk_disable(clk, i);
+ break;
+ }
+ }
+
+ return ret;
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
@@ -215,21 +238,14 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
- int i;
ret = scpsys_regulator_enable(scpd);
if (ret < 0)
return ret;
- for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
- ret = clk_prepare_enable(scpd->clk[i]);
- if (ret) {
- for (--i; i >= 0; i--)
- clk_disable_unprepare(scpd->clk[i]);
-
- goto err_clk;
- }
- }
+ ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
+ if (ret)
+ goto err_clk;
val = readl(ctl_addr);
val |= PWR_ON_BIT;
@@ -282,10 +298,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
return 0;
err_pwr_ack:
- for (i = MAX_CLKS - 1; i >= 0; i--) {
- if (scpd->clk[i])
- clk_disable_unprepare(scpd->clk[i]);
- }
+ scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
scpsys_regulator_disable(scpd);
@@ -302,7 +315,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
- int i;
if (scpd->data->bus_prot_mask) {
ret = mtk_infracfg_set_bus_protection(scp->infracfg,
@@ -343,8 +355,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
- for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
- clk_disable_unprepare(scpd->clk[i]);
+ scpsys_clk_disable(scpd->clk, MAX_CLKS);
ret = scpsys_regulator_disable(scpd);
if (ret < 0)
--
1.8.1.1.dirty
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* [PATCH v7 02/13] dt-bindings: soc: Add MT8183 power dt-bindings
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 14 ++++++++++++
include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 876693a..00eab7e 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
Required properties:
- compatible: Should be one of:
@@ -25,18 +26,31 @@ Required properties:
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
+ The new clock type "BASIC" belongs to the type above.
+ As to the new clock type "SUBSYS" needs to be
+ enabled before releasing bus protection.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+ "vpu", "vpu1", "vpu2", "vpu3"
+ SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6", "mm-7",
+ "mm-8", "mm-9", "isp-0", "isp-1",
+ "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6", "vpu-0",
+ "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+ "vpu-5"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..5c0c8c7
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
1.8.1.1.dirty
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* [PATCH v7 11/13] soc: mediatek: Add extra sram control
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 33c4034..85c6bf4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -57,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -115,6 +117,8 @@ enum clk_id {
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
@@ -130,6 +134,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
@@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr);
+ val |= PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
--
1.8.1.1.dirty
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* [PATCH v7 13/13] arm64: dts: Add power controller device node of MT8183
From: Weiyi Lu @ 2019-08-28 9:11 UTC (permalink / raw)
To: Nicolas Boichat, Matthias Brugger, Rob Herring
Cc: James Liao, Weiyi Lu, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-1-git-send-email-weiyi.lu@mediatek.com>
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4..66aaa07 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mt8183-power.h>
#include "mt8183-pinfunc.h"
/ {
@@ -238,6 +239,62 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_CAM>,
+ <&topckgen CLK_TOP_MUX_IMG>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>,
+ <&imgsys CLK_IMG_LARB5>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&camsys CLK_CAM_LARB6>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_SENINF>,
+ <&camsys CLK_CAM_CAMSV0>,
+ <&camsys CLK_CAM_CAMSV1>,
+ <&camsys CLK_CAM_CAMSV2>,
+ <&camsys CLK_CAM_CCU>,
+ <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ clock-names = "audio", "audio1", "audio2",
+ "mfg", "mm", "cam",
+ "isp", "vpu", "vpu1",
+ "vpu2", "vpu3", "mm-0",
+ "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6",
+ "mm-7", "mm-8", "mm-9",
+ "isp-0", "isp-1", "cam-0",
+ "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6",
+ "vpu-0", "vpu-1", "vpu-2",
+ "vpu-3", "vpu-4", "vpu-5";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
@@ -396,6 +453,11 @@
#clock-cells = <1>;
};
+ smi_common: smi@14019000 {
+ compatible = "mediatek,mt8183-smi-common", "syscon";
+ reg = <0 0x14019000 0 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
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^ permalink raw reply related
* Re: [PATCH V15 1/5] dt-bindings: fsl: scu: add thermal binding
From: Zhang Rui @ 2019-08-28 9:14 UTC (permalink / raw)
To: Anson Huang, robh+dt@kernel.org, mark.rutland@arm.com,
corbet@lwn.net, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will.deacon@arm.com, edubezval@gmail.com,
daniel.lezcano@linaro.org, Aisheng Dong, ulf.hansson@linaro.org,
Peng Fan, mchehab+samsung@kernel.org, linux@roeck-us.net,
Daniel Baluta, maxime.ripard@bootlin.com,
horms+renesas@verge.net.au, olof@lixom.net,
jagan@amarulasolutions.com, bjorn.andersson@linaro.org,
Leonard Crestez, dinguyen@kernel.org,
enric.balletbo@collabora.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <DB3PR0402MB39162EB555CD7AE75D58C582F5C60@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Hi, Anson,
We're missing ACK from the maintainers for patch 4/5 and 5/5, if we
want to shipped the patch via thermal tree.
For patch 2/5, as it introduces a new API for OF_THERMAL, I'd like to
get Eduardo' feedback before taking them.
thanks,
rui
On Wed, 2019-07-24 at 03:16 +0000, Anson Huang wrote:
> Ping...
>
> > Hi, Daniel/Rui/Eduardo
> > Could you please take a look at this patch series?
> >
> > Anson
> >
> > > From: Anson Huang <Anson.Huang@nxp.com>
> > >
> > > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
> > > system
> > > controller, the system controller is in charge of system power,
> > > clock
> > > and thermal sensors etc. management, Linux kernel has to
> > > communicate
> > > with system controller via MU (message unit) IPC to get
> > > temperature
> > > from thermal sensors, this patch adds binding doc for i.MX system
> > > controller thermal driver.
> > >
> > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> > > ---
> > > No change.
> > > ---
> > > .../devicetree/bindings/arm/freescale/fsl,scu.txt | 16
> >
> > ++++++++++++++++
> > > 1 file changed, 16 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > index a575e42..fc3844e 100644
> > > --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > @@ -155,6 +155,17 @@ Required properties:
> > > Optional properties:
> > > - timeout-sec: contains the watchdog timeout in seconds.
> > >
> > > +Thermal bindings based on SCU Message Protocol
> > > +------------------------------------------------------------
> > > +
> > > +Required properties:
> > > +- compatible: Should be :
> > > + "fsl,imx8qxp-sc-thermal"
> > > + followed by "fsl,imx-sc-thermal";
> > > +
> > > +- #thermal-sensor-cells: See
> > > Documentation/devicetree/bindings/thermal/thermal.txt
> > > + for a description.
> > > +
> > > Example (imx8qxp):
> > > -------------
> > > aliases {
> > > @@ -222,6 +233,11 @@ firmware {
> > > compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-
> > > wdt";
> > > timeout-sec = <60>;
> > > };
> > > +
> > > + tsens: thermal-sensor {
> > > + compatible = "fsl,imx8qxp-sc-thermal",
> > > "fsl,imx-sc-
> > > thermal";
> > > + #thermal-sensor-cells = <1>;
> > > + };
> > > };
> > > };
> > >
> > > --
> > > 2.7.4
>
>
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^ permalink raw reply
* Re: [PATCH v2 1/2] input: keyboard: snvs_pwrkey: Send key events for i.MX6 S, DL and Q
From: Marco Felsch @ 2019-08-28 9:15 UTC (permalink / raw)
To: Robin van der Gracht
Cc: Mark Rutland, devicetree @ vger . kernel . org, Fabio Estevam,
Adam Ford, Sascha Hauer, Dmitry Torokhov,
linux-kernel @ vger . kernel . org, Rob Herring, dl-linux-imx,
Pengutronix Kernel Team, linux-input @ vger . kernel . org,
Robin Gong, Shawn Guo, linux-arm-kernel @ lists . infradead . org
In-Reply-To: <20190827123216.32728-1-robin@protonic.nl>
Hi Robin,
thanks for the patch.
On 19-08-27 14:32, Robin van der Gracht wrote:
> The first generation i.MX6 processors does not send an interrupt when the
> power key is pressed. It sends a power down request interrupt if the key is
> released before a hard shutdown (5 second press). This should allow
> software to bring down the SoC safely.
>
> For this driver to work as a regular power key with the older SoCs, we need
> to send a keypress AND release when we get the power down request irq.
>
> Signed-off-by: Robin van der Gracht <robin@protonic.nl>
> ---
> .../devicetree/bindings/crypto/fsl-sec4.txt | 16 ++++--
> drivers/input/keyboard/Kconfig | 2 +-
> drivers/input/keyboard/snvs_pwrkey.c | 52 ++++++++++++++++---
Can we split this so the dt-bindings are a standalone patch? IMHO this
is the usual way because the maintainer can squash them on there needs.
Also it would be cool to document the changes. A common place for
changes is after the '---' or on the cover-letter.
> 3 files changed, 57 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> index 2fe245ca816a..e4fbb9797082 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> @@ -420,14 +420,22 @@ EXAMPLE
> =====================================================================
> System ON/OFF key driver
>
> - The snvs-pwrkey is designed to enable POWER key function which controlled
> - by SNVS ONOFF, the driver can report the status of POWER key and wakeup
> - system if pressed after system suspend.
> + The snvs-pwrkey is designed to enable POWER key function which is controlled
> + by SNVS ONOFF. It can wakeup the system if pressed after system suspend.
> +
> + There are two generations of SVNS pwrkey hardware. The first generation is
> + included in i.MX6 Solo, DualLite and Quad processors. The second generation
> + is included in i.MX6 SoloX and newer SoCs.
> +
> + Second generation SNVS can detect and report the status of POWER key, but the
> + first generation can only detect a key release and so emits an instantaneous
> + press and release event when the key is released.
>
> - compatible:
> Usage: required
> Value type: <string>
> - Definition: Mush include "fsl,sec-v4.0-pwrkey".
> + Definition: Must include "fsl,sec-v4.0-pwrkey" for i.MX6 SoloX and newer
> + or "fsl,imx6qdl-snvs-pwrkey" for older SoCs.
>
> - interrupts:
> Usage: required
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index 7c4f19dab34f..937e58da5ce1 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -436,7 +436,7 @@ config KEYBOARD_SNVS_PWRKEY
> depends on OF
> help
> This is the snvs powerkey driver for the Freescale i.MX application
> - processors that are newer than i.MX6 SX.
> + processors.
>
> To compile this driver as a module, choose M here; the
> module will be called snvs_pwrkey.
> diff --git a/drivers/input/keyboard/snvs_pwrkey.c b/drivers/input/keyboard/snvs_pwrkey.c
> index 5342d8d45f81..d71c44733103 100644
> --- a/drivers/input/keyboard/snvs_pwrkey.c
> +++ b/drivers/input/keyboard/snvs_pwrkey.c
> @@ -29,6 +29,11 @@
> #define DEBOUNCE_TIME 30
> #define REPEAT_INTERVAL 60
>
> +enum imx_snvs_hwtype {
> + IMX6SX_SNVS, /* i.MX6 SoloX and newer */
> + IMX6QDL_SNVS, /* i.MX6 Solo, DualLite and Quad */
> +};
> +
> struct pwrkey_drv_data {
> struct regmap *snvs;
> int irq;
> @@ -37,14 +42,41 @@ struct pwrkey_drv_data {
> int wakeup;
> struct timer_list check_timer;
> struct input_dev *input;
> + enum imx_snvs_hwtype hwtype;
> };
>
> +static const struct of_device_id imx_snvs_pwrkey_ids[] = {
> + {
> + .compatible = "fsl,sec-v4.0-pwrkey",
> + .data = (const void *)IMX6SX_SNVS,
> + },
> + {
> + .compatible = "fsl,imx6qdl-snvs-pwrkey",
> + .data = (const void *)IMX6QDL_SNVS,
> + },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, imx_snvs_pwrkey_ids);
Can we keep this on the original place if you are using ...
> +
> static void imx_imx_snvs_check_for_events(struct timer_list *t)
> {
> struct pwrkey_drv_data *pdata = from_timer(pdata, t, check_timer);
> struct input_dev *input = pdata->input;
> u32 state;
>
> + if (pdata->hwtype == IMX6QDL_SNVS) {
> + /*
> + * The first generation i.MX6 SoCs only sends an interrupt on
> + * button release. To mimic power-key usage, we'll prepend a
> + * press event.
> + */
> + input_report_key(input, pdata->keycode, 1);
Missing input_sync() here?
> + input_report_key(input, pdata->keycode, 0);
> + input_sync(input);
> + pm_relax(input->dev.parent);
> + return;
> + }
> +
> regmap_read(pdata->snvs, SNVS_HPSR_REG, &state);
> state = state & SNVS_HPSR_BTN ? 1 : 0;
>
> @@ -67,13 +99,17 @@ static irqreturn_t imx_snvs_pwrkey_interrupt(int irq, void *dev_id)
> {
> struct platform_device *pdev = dev_id;
> struct pwrkey_drv_data *pdata = platform_get_drvdata(pdev);
> + unsigned long expire = jiffies;
> u32 lp_status;
>
> pm_wakeup_event(pdata->input->dev.parent, 0);
>
> regmap_read(pdata->snvs, SNVS_LPSR_REG, &lp_status);
> - if (lp_status & SNVS_LPSR_SPO)
> - mod_timer(&pdata->check_timer, jiffies + msecs_to_jiffies(DEBOUNCE_TIME));
> + if (lp_status & SNVS_LPSR_SPO) {
> + if (pdata->hwtype == IMX6SX_SNVS)
> + expire += msecs_to_jiffies(DEBOUNCE_TIME);
> + mod_timer(&pdata->check_timer, expire);
Is this desired because the timer gets triggered earlier.
> + }
>
> /* clear SPO status */
> regmap_write(pdata->snvs, SNVS_LPSR_REG, SNVS_LPSR_SPO);
> @@ -93,6 +129,7 @@ static int imx_snvs_pwrkey_probe(struct platform_device *pdev)
> struct pwrkey_drv_data *pdata = NULL;
> struct input_dev *input = NULL;
> struct device_node *np;
> + const struct of_device_id *match;
> int error;
>
> /* Get SNVS register Page */
> @@ -100,6 +137,10 @@ static int imx_snvs_pwrkey_probe(struct platform_device *pdev)
> if (!np)
> return -ENODEV;
>
> + match = of_match_node(imx_snvs_pwrkey_ids, np);
> + if (!match)
> + return -ENODEV;
... of_device_get_match_data() here. While reading the rm it seems that
the snvs block has a dedicated version register. IMHO this could be a
better way to apply the change also to existing devices with old
firmware.
Regards,
Marco
> +
> pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> if (!pdata)
> return -ENOMEM;
> @@ -115,6 +156,7 @@ static int imx_snvs_pwrkey_probe(struct platform_device *pdev)
> dev_warn(&pdev->dev, "KEY_POWER without setting in dts\n");
> }
>
> + pdata->hwtype = (enum imx_snvs_hwtype)match->data;
> pdata->wakeup = of_property_read_bool(np, "wakeup-source");
>
> pdata->irq = platform_get_irq(pdev, 0);
> @@ -175,12 +217,6 @@ static int imx_snvs_pwrkey_probe(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id imx_snvs_pwrkey_ids[] = {
> - { .compatible = "fsl,sec-v4.0-pwrkey" },
> - { /* sentinel */ }
> -};
> -MODULE_DEVICE_TABLE(of, imx_snvs_pwrkey_ids);
> -
> static struct platform_driver imx_snvs_pwrkey_driver = {
> .driver = {
> .name = "snvs_pwrkey",
> --
> 2.20.1
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* RE: [PATCH V15 1/5] dt-bindings: fsl: scu: add thermal binding
From: Anson Huang @ 2019-08-28 9:20 UTC (permalink / raw)
To: Zhang Rui, robh+dt@kernel.org, mark.rutland@arm.com,
corbet@lwn.net, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
catalin.marinas@arm.com, will.deacon@arm.com, edubezval@gmail.com,
daniel.lezcano@linaro.org, Aisheng Dong, ulf.hansson@linaro.org,
Peng Fan, mchehab+samsung@kernel.org, linux@roeck-us.net,
Daniel Baluta, maxime.ripard@bootlin.com,
horms+renesas@verge.net.au, olof@lixom.net,
jagan@amarulasolutions.com, bjorn.andersson@linaro.org,
Leonard Crestez, dinguyen@kernel.org,
enric.balletbo@collabora.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <ff3fd0ab2ba659e98070760be8e7c0f223e921f9.camel@intel.com>
Hi, Rui
> Subject: Re: [PATCH V15 1/5] dt-bindings: fsl: scu: add thermal binding
>
> Hi, Anson,
>
> We're missing ACK from the maintainers for patch 4/5 and 5/5, if we want to
> shipped the patch via thermal tree.
I think 4/5 and 5/5 can be taken by Shawn Guo once the driver part is taken, he
normally do it in this way, once driver and dt-binding are taken, I will notify him.
>
> For patch 2/5, as it introduces a new API for OF_THERMAL, I'd like to get
> Eduardo' feedback before taking them.
OK, NOT sure when he can take a look at it, we are kind of pending on this for some
time, let's wait. If you have chance to talk to him, please help ask for help from him about
this patch series, thanks a lot!
thanks,
Anson
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^ permalink raw reply
* Re: [RFC V2 0/1] mm/debug: Add tests for architecture exported page table helpers
From: Anshuman Khandual @ 2019-08-28 9:22 UTC (permalink / raw)
To: Matthew Wilcox
Cc: Mark Rutland, linux-ia64, linux-sh, Peter Zijlstra, James Hogan,
Tetsuo Handa, Heiko Carstens, Michal Hocko, linux-mm, Dave Hansen,
Paul Mackerras, sparclinux, Thomas Gleixner, linux-s390,
Michael Ellerman, x86, Russell King - ARM Linux, Steven Price,
Jason Gunthorpe, linux-arm-kernel, linux-snps-arc, Kees Cook,
Masahiro Yamada, Mark Brown, Dan Williams, Vlastimil Babka,
Sri Krishna chowdary, Ard Biesheuvel, Greg Kroah-Hartman,
linux-mips, Ralf Baechle, linux-kernel, Paul Burton,
Mike Rapoport, Vineet Gupta, Martin Schwidefsky, Andrew Morton,
linuxppc-dev, David S. Miller
In-Reply-To: <20190826131308.GA15933@bombadil.infradead.org>
On 08/26/2019 06:43 PM, Matthew Wilcox wrote:
> On Mon, Aug 26, 2019 at 08:07:13AM +0530, Anshuman Khandual wrote:
>> On 08/09/2019 07:22 PM, Matthew Wilcox wrote:
>>> On Fri, Aug 09, 2019 at 04:05:07PM +0530, Anshuman Khandual wrote:
>>>> On 08/09/2019 03:46 PM, Matthew Wilcox wrote:
>>>>> On Fri, Aug 09, 2019 at 01:03:17PM +0530, Anshuman Khandual wrote:
>>>>>> Should alloc_gigantic_page() be made available as an interface for general
>>>>>> use in the kernel. The test module here uses very similar implementation from
>>>>>> HugeTLB to allocate a PUD aligned memory block. Similar for mm_alloc() which
>>>>>> needs to be exported through a header.
>>>>>
>>>>> Why are you allocating memory at all instead of just using some
>>>>> known-to-exist PFNs like I suggested?
>>>>
>>>> We needed PFN to be PUD aligned for pfn_pud() and PMD aligned for mk_pmd().
>>>> Now walking the kernel page table for a known symbol like kernel_init()
>>>
>>> I didn't say to walk the kernel page table. I said to call virt_to_pfn()
>>> for a known symbol like kernel_init().
>>>
>>>> as you had suggested earlier we might encounter page table page entries at PMD
>>>> and PUD which might not be PMD or PUD aligned respectively. It seemed to me
>>>> that alignment requirement is applicable only for mk_pmd() and pfn_pud()
>>>> which create large mappings at those levels but that requirement does not
>>>> exist for page table pages pointing to next level. Is not that correct ? Or
>>>> I am missing something here ?
>>>
>>> Just clear the bottom bits off the PFN until you get a PMD or PUD aligned
>>> PFN. It's really not hard.
>>
>> As Mark pointed out earlier that might end up being just a synthetic PFN
>> which might not even exist on a given system.
>
> And why would that matter?
>
To start with the test uses struct page with mk_pte() and mk_pmd() while
pfn gets used in pfn_pud() during pXX_basic_tests(). So we will not be able
to derive a valid struct page from a synthetic pfn. Also if synthetic pfn is
going to be used anyway then why derive it from a real kernel symbol like
kernel_init(). Could not one be just made up with right alignment ?
Currently the test allocates 'mm_struct' and other page table pages from real
memory then why should it use synthetic pfn while creating actual page table
entries ? Couple of benefits going with synthetic pfn will be..
- It simplifies the test a bit removing PUD_SIZE allocation helpers
- It might enable the test to be run on systems without adequate memory
In the current proposal the allocation happens during boot making it much more
likely to succeed than not and when it fails, respective tests will be skipped.
I am just wondering if being able to run complete set of tests on smaller
systems with less memory weighs lot more in favor of going with synthetic
pfn instead.
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* Re: FYI: imx-sdma firmware is not compatible with SLUB slab allocator
From: Jurgen Lambrecht @ 2019-08-28 9:26 UTC (permalink / raw)
To: Leonard Crestez
Cc: Aisheng Dong, Robin Gong, dl-linux-imx,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <VI1PR04MB7023FB06F79F31334905D34EEEA00@VI1PR04MB7023.eurprd04.prod.outlook.com>
On 8/27/19 5:04 PM, Leonard Crestez wrote:
> CAUTION: This Email originated from outside Televic. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 27.08.2019 16:35, Jurgen Lambrecht wrote:
>> We are updating our kernel on our custom board with an iMX6UL from 3.14
>> to 4.19, and when loading linux-firmware/imx/sdma/sdma-imx6q.bin v3.5
>> the kernel hangs when booting, only "Starting kernel ..." is printed (by
>> uBoot I think).
> If you enable "earlycon" you should be able to see an useful error
> message from crashes in early boot.
>
> Enabling earlycon is board-specific: if you have a correct
> /chosen/stdout-path reference in dts just adding "earlycon" to kernel
> cmdline should work otherwise you can specify
> earlycon=ec_imx6q,0x202000,115200 with the exact address depending on
> which uart is console on your board.
OK, thanks. First time I hear of earlycon.
But as I thought (because of logs with other kernel versions) the kernel
just hangs when loading the sdma driver.
Now it is v3.5, but I also tried v3.3 a few weeks ago.
This is the last kernel log (below the full log):
[ 2.312336] imx-sdma 20ec000.sdma: loaded firmware 3.5
About the DT config, I enabled sdma on all that I found: standard dtsi
only has sdma enabled for SAI. But the freescale 4.1 kernel has more: I
also enabled sdma for ecspi1 to ecspi4, uart1 to uart8.
But as a test I have also removed all sdma entries from DT, and still it
hangs.
With enabling I mean add 2 lines, e.g. for sai1 in imx6ul.dtsi:
dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
dma-names = "rx", "tx";
>
>> When I remove the sdma bin (built-in the kernel via EXTRA_FIRMWARE),
>> then it boots.
>>
>> I found that the slab allocator (menu config -> General setup -> Choose
>> SLAB allocator) is the culprit: when using imx_v6_v7_defconfig the
>> kernel boots, but not with our config (based on a tiny config I think).
>> And the config that makes the difference is the slab allocator: with
>> SLUB or SLAB the kernel (with sdma bin) boots, but not with SLOB.
>>
>> I don't know how to force selecting SLUB in Kconfig when selecting
>> IMX_SDMA, but anyhow first this issue must be confirmed on other
>> processors from the iMX family.
> If there's an incompatibility between SLOB and sdma then it's sounds
> like a bug which should be fixed, not worked around via kconfig.
I agree, but it is closed source, so nothing to do about it (except
mailing nxp).
That is why I posted this, to hope to get tips like yours.
>
> I tried to enable EXTRA_FIRMWARE on v4.19.68 and imx6ul-14x14-evk booted
> worked fine for me with these changes:
> diff --git arch/arm/configs/imx_v6_v7_defconfig
> arch/arm/configs/imx_v6_v7_defconfig
> index 7f524cee1357..cedd4d2e0e02 100644
> --- arch/arm/configs/imx_v6_v7_defconfig
> +++ arch/arm/configs/imx_v6_v7_defconfig
> @@ -11,8 +11,8 @@ CONFIG_RELAY=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_PERF_EVENTS=y
> -# CONFIG_SLUB_DEBUG is not set
> # CONFIG_COMPAT_BRK is not set
> +CONFIG_SLOB=y
> CONFIG_ARCH_MULTI_V6=y
> CONFIG_ARCH_MXC=y
> CONFIG_MACH_MX31LILLY=y
> @@ -90,6 +90,10 @@ CONFIG_RFKILL_INPUT=y
> CONFIG_DEVTMPFS=y
> CONFIG_DEVTMPFS_MOUNT=y
> # CONFIG_STANDALONE is not set
> +CONFIG_EXTRA_FIRMWARE="imx/sdma/sdma-imx6q.bin"
> +CONFIG_EXTRA_FIRMWARE_DIR="../linux-firmware"
Can you please check your boot log if you see that line "imx-sdma
20ec000.sdma: loaded firmware 3.5" ? Else it is not loaded.
If you load the imx-sdma driver as a module I believe you have to put
the firmware sdma-imx6q.bin in the RFS on /lib/firmware/imx/sdma/
instead of building it into the kernel image.
> +CONFIG_FW_LOADER_USER_HELPER=y
> +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
those are not really needed
> CONFIG_CMA_SIZE_MBYTES=64
> CONFIG_IMX_WEIM=y
> CONFIG_CONNECTOR=y
>
> Please try to get a stack dump with earlycon.
So no stack dump, it just hangs:
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.56-00374-gcda746ffc0d9-dirty
(lambrecht@jl-lx-tra) (gcc version 4.9.3 (GCC)) #25 Wed Aug 28 10:49:44
CEST 2019
[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7),
cr=10c53c7d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
instruction cache
[ 0.000000] OF: fdt: Machine model: iMX6ul 33.96.7949 (PEI-SP)
[ 0.000000] earlycon: ec_imx6q0 at MMIO 0x02020000 (options '')
[ 0.000000] bootconsole [ec_imx6q0] enabled
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] cma: Reserved 64 MiB at 0x9b400000
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] random: get_random_bytes called from
start_kernel+0x8c/0x47c with crng_init=0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130048
[ 0.000000] Kernel command line: version=DEV_33967972_1-04-01
console=ttymxc0,115200 ubi.mtd=0 root=ubi0:rootfsB rootfstype=ubifs
mtdparts=gpmi-nand:-(nandflash) earlycon
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144
bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072
bytes)
[ 0.000000] Memory: 434544K/524288K available (7168K kernel code,
558K rwdata, 2068K rodata, 1024K init, 7590K bss, 24208K reserved,
65536K cma-reserved, 0K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xff800000 ( 496 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (8160 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 559 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) (7591 kB)
[ 0.000000] Running RCU self tests
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] Switching to timer-based delay loop, resolution 41ns
[ 0.000020] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
every 89478484971ns
[ 0.007848] clocksource: mxc_timer1: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 79635851949 ns
[ 0.019941] Console: colour dummy device 80x30
[ 0.021842] Lock dependency validator: Copyright (c) 2006 Red Hat,
Inc., Ingo Molnar
[ 0.029870] ... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.033667] ... MAX_LOCK_DEPTH: 48
[ 0.037840] ... MAX_LOCKDEP_KEYS: 8191
[ 0.042288] ... CLASSHASH_SIZE: 4096
[ 0.046538] ... MAX_LOCKDEP_ENTRIES: 32768
[ 0.050975] ... MAX_LOCKDEP_CHAINS: 65536
[ 0.055500] ... CHAINHASH_SIZE: 32768
[ 0.059851] memory used by lock dependency info: 4655 kB
[ 0.065244] per task-struct memory footprint: 1536 bytes
[ 0.070822] Calibrating delay loop (skipped), value calculated using
timer frequency.. 48.00 BogoMIPS (lpj=240000)
[ 0.081099] pid_max: default: 32768 minimum: 301
[ 0.086321] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.092363] Mountpoint-cache hash table entries: 1024 (order: 0, 4096
bytes)
[ 0.104414] CPU: Testing write buffer coherency: ok
[ 0.112690] Setting up static identity map for 0x80100000 - 0x80100078
[ 0.123963] devtmpfs: initialized
[ 0.272880] VFP support v0.3: implementor 41 architecture 2 part 30
variant 7 rev 5
[ 0.281104] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.288416] futex hash table entries: 256 (order: 1, 11264 bytes)
[ 0.300366] pinctrl core: initialized pinctrl subsystem
[ 0.319160] NET: Registered protocol family 16
[ 0.333165] DMA: preallocated 256 KiB pool for atomic coherent
allocations
[ 0.355397] cpuidle: using governor menu
[ 0.436775] vdd3p0: supplied by regulator-dummy
[ 0.446444] cpu: supplied by regulator-dummy
[ 0.455657] vddsoc: supplied by regulator-dummy
[ 0.556952] No ATAGs?
[ 0.572146] imx6ul-pinctrl 20e0000.iomuxc: initialized IMX pinctrl driver
[ 0.908280] mxs-dma 1804000.dma-apbh: initialized
[ 0.945421] i2c i2c-2: IMX I2C adapter registered
[ 0.949403] i2c i2c-2: can't use DMA, using PIO instead.
[ 0.970338] i2c i2c-1: IMX I2C adapter registered
[ 0.972345] i2c i2c-1: can't use DMA, using PIO instead.
[ 0.991751] i2c i2c-0: IMX I2C adapter registered
[ 0.993758] i2c i2c-0: can't use DMA, using PIO instead.
[ 1.006680] i2c i2c-3: IMX I2C adapter registered
[ 1.008683] i2c i2c-3: can't use DMA, using PIO instead.
[ 1.015674] pps_core: LinuxPPS API ver. 1 registered
[ 1.018866] pps_core: Software ver. 5.3.6 - Copyright 2005-2007
Rodolfo Giometti <giometti@linux.it>
[ 1.028470] PTP clock support registered
[ 1.038288] Advanced Linux Sound Architecture Driver Initialized.
[ 1.058453] clocksource: Switched to clocksource mxc_timer1
[ 2.111494] NET: Registered protocol family 2
[ 2.120322] tcp_listen_portaddr_hash hash table entries: 256 (order:
1, 10240 bytes)
[ 2.125441] TCP established hash table entries: 4096 (order: 2, 16384
bytes)
[ 2.132796] TCP bind hash table entries: 4096 (order: 5, 147456 bytes)
[ 2.140593] TCP: Hash tables configured (established 4096 bind 4096)
[ 2.148435] UDP hash table entries: 256 (order: 2, 20480 bytes)
[ 2.152078] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes)
[ 2.161791] NET: Registered protocol family 1
[ 2.173419] RPC: Registered named UNIX socket transport module.
[ 2.176626] RPC: Registered udp transport module.
[ 2.181521] RPC: Registered tcp transport module.
[ 2.186009] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.214905] workingset: timestamp_bits=30 max_order=17 bucket_order=0
[ 2.234013] NFS: Registering the id_resolver key type
[ 2.236776] Key type id_resolver registered
[ 2.240861] Key type id_legacy registered
[ 2.246822] fuse init (API version 7.27)
[ 2.289930] io scheduler noop registered (default)
[ 2.312336] imx-sdma 20ec000.sdma: loaded firmware 3.5
Kind regards,
Jürgen
>
> --
> Regards,
> Leonard
>
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^ permalink raw reply
* Re: [PATCH net-next v4 3/3] dt-bindings: net: ethernet: Update mt7622 docs and dts to reflect the new phylink API
From: Matthias Brugger @ 2019-08-28 9:29 UTC (permalink / raw)
To: René van Dorst, John Crispin, Sean Wang, Nelson Chang,
David S . Miller
Cc: Frank Wunderlich, netdev, linux-mips, Russell King,
linux-mediatek, Stefan Roese, linux-arm-kernel
In-Reply-To: <20190825174341.20750-4-opensource@vdorst.com>
Hi David,
On 25/08/2019 19:43, René van Dorst wrote:
> This patch the removes the recently added mediatek,physpeed property.
> Use the fixed-link property speed = <2500> to set the phy in 2.5Gbit.
> See mt7622-bananapi-bpi-r64.dts for a working example.
>
> Signed-off-by: René van Dorst <opensource@vdorst.com>
> --
> v3->v4:
> * no change
> v2->v3:
> * no change
> v1->v2:
> * SGMII port only support BASE-X at 2.5Gbit.
> ---
> .../arm/mediatek/mediatek,sgmiisys.txt | 2 --
> .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 28 +++++++++++++------
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 -
> 3 files changed, 19 insertions(+), 12 deletions(-)
Thanks for taking this patch. For the next time, please make sure that dts[i]
patches are independent from the binding description, as dts[i] should go
through my tree. No problem for this round, just saying for the future.
Regards,
Matthias
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> index f5518f26a914..30cb645c0e54 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> @@ -9,8 +9,6 @@ Required Properties:
> - "mediatek,mt7622-sgmiisys", "syscon"
> - "mediatek,mt7629-sgmiisys", "syscon"
> - #clock-cells: Must be 1
> -- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up
> - the capability of the target PHY.
>
> The SGMIISYS controller uses the common clk binding from
> Documentation/devicetree/bindings/clock/clock-bindings.txt
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
> index 710c5c3d87d3..83e10591e0e5 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
> @@ -115,24 +115,34 @@
> };
>
> ð {
> - pinctrl-names = "default";
> - pinctrl-0 = <ð_pins>;
> status = "okay";
> + gmac0: mac@0 {
> + compatible = "mediatek,eth-mac";
> + reg = <0>;
> + phy-mode = "2500base-x";
> +
> + fixed-link {
> + speed = <2500>;
> + full-duplex;
> + pause;
> + };
> + };
>
> gmac1: mac@1 {
> compatible = "mediatek,eth-mac";
> reg = <1>;
> - phy-handle = <&phy5>;
> + phy-mode = "rgmii";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + pause;
> + };
> };
>
> - mdio-bus {
> + mdio: mdio-bus {
> #address-cells = <1>;
> #size-cells = <0>;
> -
> - phy5: ethernet-phy@5 {
> - reg = <5>;
> - phy-mode = "sgmii";
> - };
> };
> };
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index d1e13d340e26..dac51e98204c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -931,6 +931,5 @@
> "syscon";
> reg = <0 0x1b128000 0 0x3000>;
> #clock-cells = <1>;
> - mediatek,physpeed = "2500";
> };
> };
>
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^ permalink raw reply
* Re: [PATCH] thermal: mediatek: add suspend/resume callback
From: Zhang Rui @ 2019-08-28 9:36 UTC (permalink / raw)
To: michael.kao, Eduardo Valentin, Daniel Lezcano, Rob Herring,
Mark Rutland, Matthias Brugger, hsinyi
Cc: devicetree, linux-pm, Louis Yu, linux-kernel, linux-mediatek,
linux-arm-kernel
In-Reply-To: <1562058985-27538-1-git-send-email-michael.kao@mediatek.com>
On Tue, 2019-07-02 at 17:16 +0800, michael.kao@mediatek.com wrote:
> From: Louis Yu <louis.yu@mediatek.com>
>
> Add suspend/resume callback to disable/enable Mediatek thermal sensor
> respectively. Since thermal power domain is off in suspend, thermal
> driver
> needs re-initialization during resume.
>
> Signed-off-by: Louis Yu <louis.yu@mediatek.com>
> Signed-off-by: Michael Kao <michael.kao@mediatek.com>
> ---
> This patch series base on these patches [1][2][3].
>
> [1]thermal: mediatek: mt8183: fix bank number settings (
> https://patchwork.kernel.org/patch/10938817/)
> [2]thermal: mediatek: add another get_temp ops for thermal sensors (
> https://patchwork.kernel.org/patch/10938829/)
> [3]thermal: mediatek: use spinlock to protect PTPCORESEL (
> https://patchwork.kernel.org/patch/10938841/)
>
all these patches are not sent to linux-pm mailing list, thus they
never got chance to get merged. please resend them to linux-pm.
I don't know what the first part of the patch set do, so I'm wondering
if there is any dependency?
thanks,
rui
> drivers/thermal/mtk_thermal.c | 134
> +++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 125 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/thermal/mtk_thermal.c
> b/drivers/thermal/mtk_thermal.c
> index 3d01153..61d4114 100644
> --- a/drivers/thermal/mtk_thermal.c
> +++ b/drivers/thermal/mtk_thermal.c
> @@ -30,6 +30,7 @@
> #include <linux/thermal.h>
> #include <linux/reset.h>
> #include <linux/types.h>
> +#include <linux/iopoll.h>
>
> /* AUXADC Registers */
> #define AUXADC_CON1_SET_V 0x008
> @@ -39,6 +40,8 @@
>
> #define APMIXED_SYS_TS_CON1 0x604
>
> +#define APMIXED_SYS_TS_CON1_BUFFER_OFF 0x30
> +
> /* Thermal Controller Registers */
> #define TEMP_MONCTL0 0x000
> #define TEMP_MONCTL1 0x004
> @@ -46,6 +49,7 @@
> #define TEMP_MONIDET0 0x014
> #define TEMP_MONIDET1 0x018
> #define TEMP_MSRCTL0 0x038
> +#define TEMP_MSRCTL1 0x03c
> #define TEMP_AHBPOLL 0x040
> #define TEMP_AHBTO 0x044
> #define TEMP_ADCPNP0 0x048
> @@ -95,6 +99,9 @@
> #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
> #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
>
> +#define TEMP_MSRCTL1_BUS_STA (BIT(0) | BIT(7))
> +#define TEMP_MSRCTL1_SENSING_POINTS_PAUSE 0x10E
> +
> /* MT8173 thermal sensors */
> #define MT8173_TS1 0
> #define MT8173_TS2 1
> @@ -266,6 +273,10 @@ struct mtk_thermal_data {
> struct mtk_thermal {
> struct device *dev;
> void __iomem *thermal_base;
> + void __iomem *apmixed_base;
> + void __iomem *auxadc_base;
> + u64 apmixed_phys_base;
> + u64 auxadc_phys_base;
>
> struct clk *clk_peri_therm;
> struct clk *clk_auxadc;
> @@ -795,6 +806,42 @@ static void mtk_thermal_init_bank(struct
> mtk_thermal *mt, int num,
> mtk_thermal_put_bank(bank);
> }
>
> +static int mtk_thermal_disable_sensing(struct mtk_thermal *mt, int
> num)
> +{
> + struct mtk_thermal_bank *bank = &mt->banks[num];
> + u32 val;
> + unsigned long timeout;
> + void __iomem *addr;
> + int ret = 0;
> +
> + bank->id = num;
> + bank->mt = mt;
> +
> + mtk_thermal_get_bank(bank);
> +
> + val = readl(mt->thermal_base + TEMP_MSRCTL1);
> + /* pause periodic temperature measurement for sensing points */
> + writel(val | TEMP_MSRCTL1_SENSING_POINTS_PAUSE,
> + mt->thermal_base + TEMP_MSRCTL1);
> +
> + /* wait until temperature measurement bus idle */
> + timeout = jiffies + HZ;
> + addr = mt->thermal_base + TEMP_MSRCTL1;
> +
> + ret = readl_poll_timeout(addr, val, (val &
> TEMP_MSRCTL1_BUS_STA) == 0x0,
> + 0, timeout);
> + if (ret < 0)
> + goto out;
> +
> + /* disable periodic temperature meausrement on sensing points
> */
> + writel(0x0, mt->thermal_base + TEMP_MONCTL0);
> +
> +out:
> + mtk_thermal_put_bank(bank);
> +
> + return ret;
> +}
> +
> static u64 of_get_phys_base(struct device_node *np)
> {
> u64 size64;
> @@ -917,7 +964,6 @@ static int mtk_thermal_probe(struct
> platform_device *pdev)
> struct device_node *auxadc, *apmixedsys, *np = pdev-
> >dev.of_node;
> struct mtk_thermal *mt;
> struct resource *res;
> - u64 auxadc_phys_base, apmixed_phys_base;
> struct thermal_zone_device *tzdev;
> struct mtk_thermal_zone *tz;
>
> @@ -954,11 +1000,11 @@ static int mtk_thermal_probe(struct
> platform_device *pdev)
> return -ENODEV;
> }
>
> - auxadc_phys_base = of_get_phys_base(auxadc);
> + mt->auxadc_phys_base = of_get_phys_base(auxadc);
>
> of_node_put(auxadc);
>
> - if (auxadc_phys_base == OF_BAD_ADDR) {
> + if (mt->auxadc_phys_base == OF_BAD_ADDR) {
> dev_err(&pdev->dev, "Can't get auxadc phys address\n");
> return -EINVAL;
> }
> @@ -969,11 +1015,12 @@ static int mtk_thermal_probe(struct
> platform_device *pdev)
> return -ENODEV;
> }
>
> - apmixed_phys_base = of_get_phys_base(apmixedsys);
> + mt->apmixed_phys_base = of_get_phys_base(apmixedsys);
> + mt->apmixed_base = of_iomap(apmixedsys, 0);
>
> of_node_put(apmixedsys);
>
> - if (apmixed_phys_base == OF_BAD_ADDR) {
> + if (mt->apmixed_phys_base == OF_BAD_ADDR) {
> dev_err(&pdev->dev, "Can't get auxadc phys address\n");
> return -EINVAL;
> }
> @@ -985,19 +1032,19 @@ static int mtk_thermal_probe(struct
> platform_device *pdev)
> ret = clk_prepare_enable(mt->clk_auxadc);
> if (ret) {
> dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n",
> ret);
> - return ret;
> + goto err_disable_clk_auxadc;
> }
>
> ret = clk_prepare_enable(mt->clk_peri_therm);
> if (ret) {
> dev_err(&pdev->dev, "Can't enable peri clk: %d\n",
> ret);
> - goto err_disable_clk_auxadc;
> + goto err_disable_clk_peri_therm;
> }
>
> for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ;
> ctrl_id++)
> for (i = 0; i < mt->conf->num_banks; i++)
> - mtk_thermal_init_bank(mt, i, apmixed_phys_base,
> - auxadc_phys_base,
> ctrl_id);
> + mtk_thermal_init_bank(mt, i, mt-
> >apmixed_phys_base,
> + mt->auxadc_phys_base,
> ctrl_id);
>
> platform_set_drvdata(pdev, mt);
>
> @@ -1041,11 +1088,80 @@ static int mtk_thermal_remove(struct
> platform_device *pdev)
> return 0;
> }
>
> +static int __maybe_unused mtk_thermal_suspend(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct mtk_thermal *mt = platform_get_drvdata(pdev);
> + int i, ret;
> +
> + for (i = 0; i < mt->conf->num_banks; i++) {
> + ret = mtk_thermal_disable_sensing(mt, i);
> + if (ret)
> + goto out;
> + }
> +
> + /* disable buffer */
> + writel(readl(mt->apmixed_base + APMIXED_SYS_TS_CON1) |
> + APMIXED_SYS_TS_CON1_BUFFER_OFF,
> + mt->apmixed_base + APMIXED_SYS_TS_CON1);
> +
> + clk_disable_unprepare(mt->clk_peri_therm);
> + clk_disable_unprepare(mt->clk_auxadc);
> +
> + return 0;
> +
> +out:
> + dev_err(&pdev->dev, "Failed to wait until bus idle\n");
> +
> + return ret;
> +}
> +
> +static int __maybe_unused mtk_thermal_resume(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct mtk_thermal *mt = platform_get_drvdata(pdev);
> + int i, ret, ctrl_id;
> +
> + ret = device_reset(&pdev->dev);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(mt->clk_auxadc);
> + if (ret) {
> + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n",
> ret);
> + goto err_disable_clk_auxadc;
> + }
> +
> + ret = clk_prepare_enable(mt->clk_peri_therm);
> + if (ret) {
> + dev_err(&pdev->dev, "Can't enable peri clk: %d\n",
> ret);
> + goto err_disable_clk_peri_therm;
> + }
> +
> + for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ;
> ctrl_id++)
> + for (i = 0; i < mt->conf->num_banks; i++)
> + mtk_thermal_init_bank(mt, i, mt-
> >apmixed_phys_base,
> + mt->auxadc_phys_base,
> ctrl_id);
> +
> + return 0;
> +
> +err_disable_clk_peri_therm:
> + clk_disable_unprepare(mt->clk_peri_therm);
> +err_disable_clk_auxadc:
> + clk_disable_unprepare(mt->clk_auxadc);
> +
> + return ret;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(mtk_thermal_pm_ops,
> + mtk_thermal_suspend, mtk_thermal_resume);
> +
> static struct platform_driver mtk_thermal_driver = {
> .probe = mtk_thermal_probe,
> .remove = mtk_thermal_remove,
> .driver = {
> .name = "mtk-thermal",
> + .pm = &mtk_thermal_pm_ops,
> .of_match_table = mtk_thermal_of_match,
> },
> };
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^ permalink raw reply
* Re: [PATCH 6/6] PCI: tegra: Add support to enable slot regulators
From: Andrew Murray @ 2019-08-28 9:37 UTC (permalink / raw)
To: Thierry Reding
Cc: devicetree, lorenzo.pieralisi, mperttunen, mmaddireddy, kthota,
gustavo.pimentel, Vidya Sagar, linux-kernel, kishon, linux-tegra,
robh+dt, linux-pci, bhelgaas, digetx, jonathanh, linux-arm-kernel,
sagar.tv
In-Reply-To: <20190828090757.GA2917@ulmo>
On Wed, Aug 28, 2019 at 11:07:57AM +0200, Thierry Reding wrote:
> On Tue, Aug 27, 2019 at 06:13:34PM +0100, Andrew Murray wrote:
> > On Tue, Aug 27, 2019 at 09:54:17PM +0530, Vidya Sagar wrote:
> > > On 8/27/2019 9:17 PM, Andrew Murray wrote:
> > > > On Mon, Aug 26, 2019 at 01:01:43PM +0530, Vidya Sagar wrote:
> > > > > Add support to get regulator information of 3.3V and 12V supplies of a PCIe
> > > > > slot from the respective controller's device-tree node and enable those
> > > > > supplies. This is required in platforms like p2972-0000 where the supplies
> > > > > to x16 slot owned by C5 controller need to be enabled before attempting to
> > > > > enumerate the devices.
> > > > >
> > > > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > > > ---
> > > > > drivers/pci/controller/dwc/pcie-tegra194.c | 65 ++++++++++++++++++++++
> > > > > 1 file changed, 65 insertions(+)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > > > index 8a27b25893c9..97de2151a738 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > > > @@ -278,6 +278,8 @@ struct tegra_pcie_dw {
> > > > > u32 aspm_l0s_enter_lat;
> > > > > struct regulator *pex_ctl_supply;
> > > > > + struct regulator *slot_ctl_3v3;
> > > > > + struct regulator *slot_ctl_12v;
> > > > > unsigned int phy_count;
> > > > > struct phy **phys;
> > > > > @@ -1047,6 +1049,59 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
> > > > > }
> > > > > }
> > > > > +static void tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
> > > > > +{
> > > > > + pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
> > > > > + if (IS_ERR(pcie->slot_ctl_3v3))
> > > > > + pcie->slot_ctl_3v3 = NULL;
> > > > > +
> > > > > + pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
> > > > > + if (IS_ERR(pcie->slot_ctl_12v))
> > > > > + pcie->slot_ctl_12v = NULL;
> > > >
> > > > Do these need to take into consideration -EPROBE_DEFER?
> > > Since these are devm_* APIs, isn't it taken care of automatically?
> >
> > devm_regulator_get_optional can still return -EPROBE_DEFER - for times when
> > "lookup could succeed in the future".
> >
> > It's probably helpful here for your driver to distinguish between there not
> > being a regulator specified in the DT, and there being a regulator but there
> > is no device for it yet. For the latter case - your driver would probe but
> > nothing would enumerate.
> >
> > See pcie-rockchip-host.c for an example of where this is handled.
> >
> > Of course if, for whatever reason it is unlikely you'll ever get -EPROBE_DEFER
> > then maybe it's OK as it is.
>
> Let's not assume that. We've just recently encountered a case where we
> did not handle -EPROBE_DEFER because we had assumed too much, and that
> turned into a bit of a hassle to fix.
>
> Vidya, I think what Andrew is saying is that you need to propagate the
> -EPROBE_DEFER error to the caller (i.e. the ->probe() callback) so that
> the PCI controller driver can be properly added to the defer queue in
> case the regulator isn't ready yet.
Indeed.
>
> I think what we want here is something like:
>
> pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
> if (IS_ERR(pcie->slot_ctl_3v3)) {
> if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
> return PTR_ERR(pcie->slot_ctl_3v3);
>
> pcie->slot_ctl_3v3 = NULL;
> }
>
> Andrew, I'm not sure the handling in rockchip_pcie_parse_host_dt() is
> correct. It singles out -EPROBE_DEFER, which I think is the wrong way
> around. We should be special-casing -ENODEV, because regulator_get()
> can return a wide array of error cases, not all of which we actually
> want to consider successes. For example we could be getting -ENOMEM,
> which, I would argue, is something that we should propagate.
Yes I completely agree, given that the regulator is optional: we only want
to proceed if we find the regulator or if a regulator wasn't specified in the
DT. We should fail upon any other error, in case a regulator was specified
but the error prevented it from being returned.
> I think
> it'd be very confusing to take that as meaning "optional regulator
> wasn't specified", because in that case the DTS file would've had the
> regulator hooked up (we have to assume that it is needed in that case)
> but we won't be enabling it, so it's unlikely that devices will
> enumerate.
Thanks,
Andrew Murray
>
> Thierry
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^ permalink raw reply
* Re: [PATCH v7 02/13] dt-bindings: soc: Add MT8183 power dt-bindings
From: Matthias Brugger @ 2019-08-28 9:39 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring
Cc: James Liao, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-3-git-send-email-weiyi.lu@mediatek.com>
On 28/08/2019 11:11, Weiyi Lu wrote:
> Add power dt-bindings of MT8183 and introduces "BASIC" and
> "SUBSYS" clock types in binding document.
> The "BASIC" type is compatible to the original power control with
> clock name [a-z]+[0-9]*, e.g. mm, vpu1.
> The "SUBSYS" type is used for bus protection control with clock
> name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 14 ++++++++++++
> include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
> create mode 100644 include/dt-bindings/power/mt8183-power.h
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> index 876693a..00eab7e 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
> @@ -14,6 +14,7 @@ power/power_domain.txt. It provides the power domains defined in
> - include/dt-bindings/power/mt2701-power.h
> - include/dt-bindings/power/mt2712-power.h
> - include/dt-bindings/power/mt7622-power.h
> +- include/dt-bindings/power/mt8183-power.h
>
> Required properties:
> - compatible: Should be one of:
> @@ -25,18 +26,31 @@ Required properties:
> - "mediatek,mt7623a-scpsys": For MT7623A SoC
> - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
> - "mediatek,mt8173-scpsys"
> + - "mediatek,mt8183-scpsys"
> - #power-domain-cells: Must be 1
> - reg: Address range of the SCPSYS unit
> - infracfg: must contain a phandle to the infracfg controller
> - clock, clock-names: clocks according to the common clock binding.
> These are clocks which hardware needs to be
> enabled before enabling certain power domains.
> + The new clock type "BASIC" belongs to the type above.
> + As to the new clock type "SUBSYS" needs to be
> + enabled before releasing bus protection.
The new clock type won't be new in a couple of month, better reword this. E.g.:
Some SoCs have to groups of clocks. BASIC clocks need to be enabled before
enabling the corresponding power domain. SUBSYS clocks need to be enabled before
releasing the bus protection.
> Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
> Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
> Required clocks for MT6797: "mm", "mfg", "vdec"
> Required clocks for MT7622 or MT7629: "hif_sel"
> Required clocks for MT7623A: "ethif"
> Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
> + Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
> + "vpu", "vpu1", "vpu2", "vpu3"
> + SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
> + "mm-4", "mm-5", "mm-6", "mm-7",
> + "mm-8", "mm-9", "isp-0", "isp-1",
> + "cam-0", "cam-1", "cam-2", "cam-3",
> + "cam-4", "cam-5", "cam-6", "vpu-0",
> + "vpu-1", "vpu-2", "vpu-3", "vpu-4",
> + "vpu-5"
>
> Optional properties:
> - vdec-supply: Power supply for the vdec power domain
> diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
> new file mode 100644
> index 0000000..5c0c8c7
> --- /dev/null
> +++ b/include/dt-bindings/power/mt8183-power.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
> +#define _DT_BINDINGS_POWER_MT8183_POWER_H
> +
> +#define MT8183_POWER_DOMAIN_AUDIO 0
> +#define MT8183_POWER_DOMAIN_CONN 1
> +#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
> +#define MT8183_POWER_DOMAIN_MFG 3
> +#define MT8183_POWER_DOMAIN_MFG_CORE0 4
> +#define MT8183_POWER_DOMAIN_MFG_CORE1 5
> +#define MT8183_POWER_DOMAIN_MFG_2D 6
> +#define MT8183_POWER_DOMAIN_DISP 7
> +#define MT8183_POWER_DOMAIN_CAM 8
> +#define MT8183_POWER_DOMAIN_ISP 9
> +#define MT8183_POWER_DOMAIN_VDEC 10
> +#define MT8183_POWER_DOMAIN_VENC 11
> +#define MT8183_POWER_DOMAIN_VPU_TOP 12
> +#define MT8183_POWER_DOMAIN_VPU_CORE0 13
> +#define MT8183_POWER_DOMAIN_VPU_CORE1 14
> +
> +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
>
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^ permalink raw reply
* Re: [PATCH v7 03/13] soc: mediatek: Refactor polling timeout and documentation
From: Matthias Brugger @ 2019-08-28 9:43 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring
Cc: James Liao, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-4-git-send-email-weiyi.lu@mediatek.com>
On 28/08/2019 11:11, Weiyi Lu wrote:
> Use USEC_PER_SEC to indicate the polling timeout directly.
> And add documentation of scp_domain_data.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
Queued for v5.4-next/soc
Thanks!
> drivers/soc/mediatek/mtk-scpsys.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index 503222d..e97fc0e 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -21,7 +21,7 @@
> #include <dt-bindings/power/mt8173-power.h>
>
> #define MTK_POLL_DELAY_US 10
> -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
> +#define MTK_POLL_TIMEOUT USEC_PER_SEC
>
> #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
> #define MTK_SCPD_FWAIT_SRAM BIT(1)
> @@ -108,6 +108,17 @@ enum clk_id {
>
> #define MAX_CLKS 3
>
> +/**
> + * struct scp_domain_data - scp domain data for power on/off flow
> + * @name: The domain name.
> + * @sta_mask: The mask for power on/off status bit.
> + * @ctl_offs: The offset for main power control register.
> + * @sram_pdn_bits: The mask for sram power control bits.
> + * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> + * @bus_prot_mask: The mask for single step bus protection.
> + * @clk_id: The basic clocks required by this power domain.
> + * @caps: The flag for active wake-up action.
> + */
> struct scp_domain_data {
> const char *name;
> u32 sta_mask;
>
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^ permalink raw reply
* Re: [PATCH v2 01/11] asm-generic: add dma_zone_size
From: Nicolas Saenz Julienne @ 2019-08-28 9:44 UTC (permalink / raw)
To: Christoph Hellwig
Cc: catalin.marinas, eric, linux-riscv, frowand.list, m.szyprowski,
linux-arch, f.fainelli, will, devicetree, Arnd Bergmann,
marc.zyngier, robh+dt, linux-rpi-kernel, linux-arm-kernel, phill,
mbrugger, linux-mm, linux-kernel, iommu, wahrenst, akpm,
Robin Murphy
In-Reply-To: <027272c27398b950f207101a2c5dbc07a30a36bc.camel@suse.de>
[-- Attachment #1.1: Type: text/plain, Size: 2255 bytes --]
On Mon, 2019-08-26 at 15:46 +0200, Nicolas Saenz Julienne wrote:
> On Mon, 2019-08-26 at 09:09 +0200, Christoph Hellwig wrote:
> > On Tue, Aug 20, 2019 at 04:58:09PM +0200, Nicolas Saenz Julienne wrote:
> > > Some architectures have platform specific DMA addressing limitations.
> > > This will allow for hardware description code to provide the constraints
> > > in a generic manner, so as for arch code to properly setup it's memory
> > > zones and DMA mask.
> >
> > I know this just spreads the arm code, but I still kinda hate it.
>
> Rob's main concern was finding a way to pass the constraint from HW definition
> to arch without widening fdt's architecture specific function surface. I'd say
> it's fair to argue that having a generic mechanism makes sense as it'll now
> traverse multiple archs and subsystems.
>
> I get adding globals like this is not very appealing, yet I went with it as it
> was the easier to integrate with arm's code. Any alternative suggestions?
>
> > MAX_DMA_ADDRESS is such an oddly defined concepts. We have the mm
> > code that uses it to start allocating after the dma zones, but
> > I think that would better be done using a function returning
> > 1 << max(zone_dma_bits, 32) or so. Then we have about a handful
> > of drivers using it that all seem rather bogus, and one of which
> > I think are usable on arm64.
>
> Is it safe to assume DMA limitations will always be a power of 2? I ask as
> RPi4
> kinda isn't: ZONE_DMA is 0x3c000000 bytes big, I'm approximating the zone mask
> to 30 as [0x3c000000 0x3fffffff] isn't defined as memory so it's unlikely that
> we´ll encounter buffers there. But I don't know how it could affect mm
> initialization code.
>
> This also rules out 'zone_dma_bits' as a mechanism to pass ZONE_DMA's size
> from
> HW definition code to arch's.
Hi Christoph,
I gave it a thought and think this whole MAX_DMA_ADDRESS topic falls out of the
scope of the series. I agree it's something that we should get rid of, but
fixing it isn't going to affect the overall enhancement intended here. I'd
rather focus on how are we going to pass the DMA zone data into the arch code
and fix MAX_DMA_ADDRESS on another series.
Regards,
Nicolas
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^ permalink raw reply
* Re: [PATCH v7 04/13] soc: mediatek: Refactor regulator control
From: Matthias Brugger @ 2019-08-28 9:44 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring
Cc: James Liao, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-5-git-send-email-weiyi.lu@mediatek.com>
On 28/08/2019 11:11, Weiyi Lu wrote:
> Put regulator enable and disable control in separate functions.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Applied to v5.4-next/soc
Thanks!
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 32 +++++++++++++++++++++++---------
> 1 file changed, 23 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index e97fc0e..aed540d 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -191,6 +191,22 @@ static int scpsys_domain_is_on(struct scp_domain *scpd)
> return -EINVAL;
> }
>
> +static int scpsys_regulator_enable(struct scp_domain *scpd)
> +{
> + if (!scpd->supply)
> + return 0;
> +
> + return regulator_enable(scpd->supply);
> +}
> +
> +static int scpsys_regulator_disable(struct scp_domain *scpd)
> +{
> + if (!scpd->supply)
> + return 0;
> +
> + return regulator_disable(scpd->supply);
> +}
> +
> static int scpsys_power_on(struct generic_pm_domain *genpd)
> {
> struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> @@ -201,11 +217,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> int ret, tmp;
> int i;
>
> - if (scpd->supply) {
> - ret = regulator_enable(scpd->supply);
> - if (ret)
> - return ret;
> - }
> + ret = scpsys_regulator_enable(scpd);
> + if (ret < 0)
> + return ret;
>
> for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
> ret = clk_prepare_enable(scpd->clk[i]);
> @@ -273,8 +287,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> clk_disable_unprepare(scpd->clk[i]);
> }
> err_clk:
> - if (scpd->supply)
> - regulator_disable(scpd->supply);
> + scpsys_regulator_disable(scpd);
>
> dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
>
> @@ -333,8 +346,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
> clk_disable_unprepare(scpd->clk[i]);
>
> - if (scpd->supply)
> - regulator_disable(scpd->supply);
> + ret = scpsys_regulator_disable(scpd);
> + if (ret < 0)
> + goto out;
>
> return 0;
>
>
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* [PATCH v2] mmc: mediatek: enable SDIO IRQ low level trigger function
From: Yong Mao @ 2019-08-28 9:45 UTC (permalink / raw)
To: Ulf Hansson
Cc: srv_heupstream, linux-mmc, linux-kernel, linux-mediatek,
Chaotian Jing, Matthias Brugger, linux-arm-kernel
In-Reply-To:
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* [PATCH v2] mmc: mediatek: enable SDIO IRQ low level trigger function
From: Yong Mao @ 2019-08-28 9:45 UTC (permalink / raw)
To: Ulf Hansson
Cc: srv_heupstream, linux-mmc, linux-kernel, yong mao, linux-mediatek,
Chaotian Jing, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566985524-22749-1-git-send-email-yong.mao@mediatek.com>
From: yong mao <yong.mao@mediatek.com>
SDIO IRQ is not defaultly triggered by low level,
but by falling edge. It needs to set related register
to enable SDIO IRQ low level trigger function.
Otherwise the SDIO IRQ may be lost in some specail condition.
Signed-off-by: Yong Mao <yong.mao@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 33f4b63..585f0c7 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -192,6 +192,7 @@
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
+#define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
/* SDC_ADV_CFG0 mask */
#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
@@ -1568,6 +1569,7 @@ static void msdc_init_hw(struct msdc_host *host)
/* Config SDIO device detect interrupt function */
sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
+ sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
/* Configure to default data timeout */
sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
--
1.9.1
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* Re: [PATCH v7 05/13] soc: mediatek: Refactor clock control
From: Matthias Brugger @ 2019-08-28 9:46 UTC (permalink / raw)
To: Weiyi Lu, Nicolas Boichat, Rob Herring
Cc: James Liao, srv_heupstream, linux-kernel, Fan Chen,
linux-mediatek, Yong Wu, linux-arm-kernel
In-Reply-To: <1566983506-26598-6-git-send-email-weiyi.lu@mediatek.com>
On 28/08/2019 11:11, Weiyi Lu wrote:
> Put clock enable and disable control in separate function.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 45 ++++++++++++++++++++++++---------------
> 1 file changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index aed540d..73e4a1a 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -207,6 +207,29 @@ static int scpsys_regulator_disable(struct scp_domain *scpd)
> return regulator_disable(scpd->supply);
> }
>
> +static void scpsys_clk_disable(struct clk *clk[], int max_num)
> +{
> + int i;
> +
> + for (i = max_num - 1; i >= 0; i--)
> + clk_disable_unprepare(clk[i]);
> +}
> +
> +static int scpsys_clk_enable(struct clk *clk[], int max_num)
> +{
> + int i, ret = 0;
> +
> + for (i = 0; i < max_num && clk[i]; i++) {
> + ret = clk_prepare_enable(clk[i]);
> + if (ret) {
> + scpsys_clk_disable(clk, i);
> + break;
> + }
> + }
> +
> + return ret;
> +}
> +
> static int scpsys_power_on(struct generic_pm_domain *genpd)
> {
> struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> @@ -215,21 +238,14 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> u32 val;
> int ret, tmp;
> - int i;
>
> ret = scpsys_regulator_enable(scpd);
> if (ret < 0)
> return ret;
>
> - for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
> - ret = clk_prepare_enable(scpd->clk[i]);
> - if (ret) {
> - for (--i; i >= 0; i--)
> - clk_disable_unprepare(scpd->clk[i]);
> -
> - goto err_clk;
> - }
> - }
> + ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
> + if (ret)
> + goto err_clk;
>
> val = readl(ctl_addr);
> val |= PWR_ON_BIT;
> @@ -282,10 +298,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
> return 0;
>
> err_pwr_ack:
> - for (i = MAX_CLKS - 1; i >= 0; i--) {
> - if (scpd->clk[i])
> - clk_disable_unprepare(scpd->clk[i]);
> - }
> + scpsys_clk_disable(scpd->clk, MAX_CLKS);
> err_clk:
> scpsys_regulator_disable(scpd);
>
> @@ -302,7 +315,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
> u32 val;
> int ret, tmp;
> - int i;
>
> if (scpd->data->bus_prot_mask) {
> ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> @@ -343,8 +355,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> if (ret < 0)
> goto out;
>
> - for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
> - clk_disable_unprepare(scpd->clk[i]);
> + scpsys_clk_disable(scpd->clk, MAX_CLKS);
>
> ret = scpsys_regulator_disable(scpd);
> if (ret < 0)
>
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