* Re: [PATCH V9 1/3] perf: imx8_ddr_perf: add AXI ID filter support
From: Will Deacon @ 2019-08-28 13:44 UTC (permalink / raw)
To: Joakim Zhang
Cc: mark.rutland@arm.com, Frank Li, robin.murphy@arm.com,
dl-linux-imx, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190828120524.9038-1-qiangqing.zhang@nxp.com>
On Wed, Aug 28, 2019 at 12:07:52PM +0000, Joakim Zhang wrote:
> AXI filtering is used by CSV modes 0x41 and 0x42 to count reads or
> writes with an ARID or AWID matching filter setting. Granularity is at
> subsystem level. Implementation does not allow filtring between masters
> within a subsystem. Filter is defined with 2 configuration parameters.
>
> --AXI_ID defines AxID matching value
> --AXI_MASKING defines which bits of AxID are meaningful for the matching
> 0：corresponding bit is masked
> 1: corresponding bit is not masked, i.e. used to do the matching
>
> When non-masked bits are matching corresponding AXI_ID bits then counter
> is incremented. This filter allows counting read or write access from a
> subsystem or multiple subsystems.
>
> Perf counter is incremented if AxID && AXI_MASKING == AXI_ID && AXI_MASKING
>
> AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
>
> Read and write AXI ID filter should write same value to DPCR1 if want to
> specify at the same time as this filter is shared between counters.
>
> e.g.
> perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
> perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
>
> NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
> it will be reverted in driver automatically. so that the user can just specify
> axi_id to monitor a specific id, rather than having to specify axi_mask.
> e.g.
> perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Thanks, I've pushed this series out to:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-next/perf
and plan to send it for 5.4. I did rewrite the commit messages, so please
take a look. I also folded the other two patches together.
Thanks,
Will
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* Re: [linux-sunxi] Re: [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling DDR
From: Chen-Yu Tsai @ 2019-08-28 13:46 UTC (permalink / raw)
To: Maxime Ripard
Cc: Ulf Hansson, Alejandro González, Greg KH, Linus Walleij,
linux-mmc, linux-kernel@vger.kernel.org, linux-sunxi,
Thomas Gleixner, Linux ARM
In-Reply-To: <20190828134334.qzuwodoxmw7ov5yg@flea>
On Wed, Aug 28, 2019 at 9:43 PM Maxime Ripard <mripard@kernel.org> wrote:
>
> On Wed, Aug 28, 2019 at 09:29:32PM +0800, Chen-Yu Tsai wrote:
> > On Wed, Aug 28, 2019 at 8:52 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > >
> > > On Sun, Aug 25, 2019 at 5:06 PM Alejandro González
> > > <alejandro.gonzalez.correo@gmail.com> wrote:
> > >
> > > > Jernej Skrabec compared the BSP driver with this
> > > > driver, and found that the BSP driver configures pinctrl to operate at
> > > > 1.8 V when entering DDR mode (although 3.3 V operation is supported), while
> > > > the mainline kernel lacks any mechanism to switch voltages dynamically.
> >
> > AFAIK The Pine H64 does not have the ability to switch I/O voltages. It is
> > fixed to either 1.8V (the default based on the schematics) or 3.3V.
>
> Should that be handled at the board level then maybe?
Yeah. You'd specify which one using vqmmc-supply in the mmc node and
vcc-pc-supply
in the pinctrl node.
ChenYu
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* Re: [PATCHv5] drivers/amba: add reset control to amba bus probe
From: Valdis Klētnieks @ 2019-08-28 13:46 UTC (permalink / raw)
To: Dinh Nguyen
Cc: devicetree, daniel.thompson, tony.luck, manivannan.sadhasivam,
keescook, robh, linus.walleij, anton, linux, linux-kernel,
p.zabel, ccross, frowand.list, linux-arm-kernel
In-Reply-To: <46bcf493-9dd6-bf5b-089a-be158739a13f@kernel.org>
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On Wed, 28 Aug 2019 08:34:20 -0500, Dinh Nguyen said:
> > Does this DTRT for both old and new U-Boots? My naive reading of
> > this patch
>
> What is a DTRT?
Do The Right Thing, sorry...
> > says on an old U-Boot, we end up attempting to bring it out of
> > reset even though they had already been brought out.
> >
>
> If the peripheral is already out of reset, de-asserting the reset has
> no affect.
OK, thanks. There's been hardware where doing that sort of thing twice will
confuse the device and cause issues.
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* Re: [PATCH v3 01/10] KVM: arm64: Document PV-time interface
From: Christoffer Dall @ 2019-08-28 13:49 UTC (permalink / raw)
To: Steven Price
Cc: kvm, linux-doc, Marc Zyngier, Russell King, linux-kernel,
Catalin Marinas, Paolo Bonzini, Will Deacon, kvmarm,
linux-arm-kernel
In-Reply-To: <20190827085706.GB6541@e113682-lin.lund.arm.com>
On Tue, Aug 27, 2019 at 10:57:06AM +0200, Christoffer Dall wrote:
> On Wed, Aug 21, 2019 at 04:36:47PM +0100, Steven Price wrote:
> > Introduce a paravirtualization interface for KVM/arm64 based on the
> > "Arm Paravirtualized Time for Arm-Base Systems" specification DEN 0057A.
> >
> > This only adds the details about "Stolen Time" as the details of "Live
> > Physical Time" have not been fully agreed.
> >
> > User space can specify a reserved area of memory for the guest and
> > inform KVM to populate the memory with information on time that the host
> > kernel has stolen from the guest.
> >
> > A hypercall interface is provided for the guest to interrogate the
> > hypervisor's support for this interface and the location of the shared
> > memory structures.
> >
> > Signed-off-by: Steven Price <steven.price@arm.com>
> > ---
> > Documentation/virt/kvm/arm/pvtime.txt | 100 ++++++++++++++++++++++++++
> > 1 file changed, 100 insertions(+)
> > create mode 100644 Documentation/virt/kvm/arm/pvtime.txt
> >
> > diff --git a/Documentation/virt/kvm/arm/pvtime.txt b/Documentation/virt/kvm/arm/pvtime.txt
> > new file mode 100644
> > index 000000000000..1ceb118694e7
> > --- /dev/null
> > +++ b/Documentation/virt/kvm/arm/pvtime.txt
> > @@ -0,0 +1,100 @@
> > +Paravirtualized time support for arm64
> > +======================================
> > +
> > +Arm specification DEN0057/A defined a standard for paravirtualised time
> > +support for AArch64 guests:
> > +
> > +https://developer.arm.com/docs/den0057/a
> > +
> > +KVM/arm64 implements the stolen time part of this specification by providing
> > +some hypervisor service calls to support a paravirtualized guest obtaining a
> > +view of the amount of time stolen from its execution.
> > +
> > +Two new SMCCC compatible hypercalls are defined:
> > +
> > +PV_FEATURES 0xC5000020
> > +PV_TIME_ST 0xC5000022
> > +
> > +These are only available in the SMC64/HVC64 calling convention as
> > +paravirtualized time is not available to 32 bit Arm guests. The existence of
> > +the PV_FEATURES hypercall should be probed using the SMCCC 1.1 ARCH_FEATURES
> > +mechanism before calling it.
> > +
> > +PV_FEATURES
> > + Function ID: (uint32) : 0xC5000020
> > + PV_func_id: (uint32) : Either PV_TIME_LPT or PV_TIME_ST
> > + Return value: (int32) : NOT_SUPPORTED (-1) or SUCCESS (0) if the relevant
> > + PV-time feature is supported by the hypervisor.
> > +
> > +PV_TIME_ST
> > + Function ID: (uint32) : 0xC5000022
> > + Return value: (int64) : IPA of the stolen time data structure for this
> > + (V)CPU. On failure:
> > + NOT_SUPPORTED (-1)
> > +
> > +The IPA returned by PV_TIME_ST should be mapped by the guest as normal memory
> > +with inner and outer write back caching attributes, in the inner shareable
> > +domain. A total of 16 bytes from the IPA returned are guaranteed to be
> > +meaningfully filled by the hypervisor (see structure below).
> > +
> > +PV_TIME_ST returns the structure for the calling VCPU.
> > +
> > +Stolen Time
> > +-----------
> > +
> > +The structure pointed to by the PV_TIME_ST hypercall is as follows:
> > +
> > + Field | Byte Length | Byte Offset | Description
> > + ----------- | ----------- | ----------- | --------------------------
> > + Revision | 4 | 0 | Must be 0 for version 0.1
> > + Attributes | 4 | 4 | Must be 0
> > + Stolen time | 8 | 8 | Stolen time in unsigned
> > + | | | nanoseconds indicating how
> > + | | | much time this VCPU thread
> > + | | | was involuntarily not
> > + | | | running on a physical CPU.
> > +
> > +The structure will be updated by the hypervisor prior to scheduling a VCPU. It
> > +will be present within a reserved region of the normal memory given to the
> > +guest. The guest should not attempt to write into this memory. There is a
> > +structure per VCPU of the guest.
> > +
> > +User space interface
> > +====================
> > +
> > +User space can request that KVM provide the paravirtualized time interface to
> > +a guest by creating a KVM_DEV_TYPE_ARM_PV_TIME device, for example:
> > +
> > + struct kvm_create_device pvtime_device = {
> > + .type = KVM_DEV_TYPE_ARM_PV_TIME,
> > + .attr = 0,
> > + .flags = 0,
> > + };
> > +
> > + pvtime_fd = ioctl(vm_fd, KVM_CREATE_DEVICE, &pvtime_device);
> > +
> > +Creation of the device should be done after creating the vCPUs of the virtual
> > +machine.
> > +
> > +The IPA of the structures must be given to KVM. This is the base address
> > +of an array of stolen time structures (one for each VCPU). The base address
> > +must be page aligned. The size must be at least 64 * number of VCPUs and be a
> > +multiple of PAGE_SIZE.
> > +
> > +The memory for these structures should be added to the guest in the usual
> > +manner (e.g. using KVM_SET_USER_MEMORY_REGION).
> > +
> > +For example:
> > +
> > + struct kvm_dev_arm_st_region region = {
> > + .gpa = <IPA of guest base address>,
> > + .size = <size in bytes>
> > + };
>
> This feel fragile; how are you handling userspace creating VCPUs after
> setting this up, the GPA overlapping guest memory, etc. Is the
> philosophy here that the VMM can mess up the VM if it wants, but that
> this should never lead attacks on the host (we better hope not) and so
> we don't care?
>
> It seems to me setting the IPA per vcpu throught the VCPU device would
> avoid a lot of these issues. See
> Documentation/virt/kvm/devices/vcpu.txt.
>
>
I discussed this with Marc the other day, and we realized that if we
make the configuration of the IPA per-PE, then a VMM can construct a VM
where these data structures are distributed within the IPA space of a
VM, which could lead to a lower TLB pressure for some
configurations/workloads.
Thanks,
Christoffer
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* [PATCH 1/2] ARM: dts: ux500: Fix up the thermal nodes
From: Linus Walleij @ 2019-08-28 13:52 UTC (permalink / raw)
To: linux-arm-kernel, Ulf Hansson; +Cc: Linus Walleij, Daniel Lezcano
The thermal driver for the DB8500 was never properly converted
to device tree, the node should definitely be activated for
all board variants so move this down into the main SoC
DTSI, and default on.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-dbx5x0.dtsi | 22 +++++++++++++++++++++-
arch/arm/boot/dts/ste-snowball.dts | 29 -----------------------------
2 files changed, 21 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index b1a31134f860..7953eea7c486 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -505,10 +505,30 @@
thermal@801573c0 {
compatible = "stericsson,db8500-thermal";
reg = <0x801573c0 0x40>;
+ interrupt-parent = <&prcmu>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
<22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
- status = "disabled";
+ num-trips = <4>;
+
+ trip0-temp = <70000>;
+ trip0-type = "active";
+ trip0-cdev-num = <1>;
+ trip0-cdev-name0 = "thermal-cpufreq-0";
+
+ trip1-temp = <75000>;
+ trip1-type = "active";
+ trip1-cdev-num = <1>;
+ trip1-cdev-name0 = "thermal-cpufreq-0";
+
+ trip2-temp = <80000>;
+ trip2-type = "active";
+ trip2-cdev-num = <1>;
+ trip2-cdev-name0 = "thermal-cpufreq-0";
+
+ trip3-temp = <85000>;
+ trip3-type = "critical";
+ trip3-cdev-num = <0>;
};
db8500-prcmu-regulators {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 3428290644ba..064e8abec954 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -376,40 +376,11 @@
pinctrl-0 = <&ssp0_snowball_mode>;
};
- cpufreq-cooling {
- status = "okay";
- };
-
prcmu@80157000 {
cpufreq {
status = "okay";
};
- thermal@801573c0 {
- num-trips = <4>;
-
- trip0-temp = <70000>;
- trip0-type = "active";
- trip0-cdev-num = <1>;
- trip0-cdev-name0 = "thermal-cpufreq-0";
-
- trip1-temp = <75000>;
- trip1-type = "active";
- trip1-cdev-num = <1>;
- trip1-cdev-name0 = "thermal-cpufreq-0";
-
- trip2-temp = <80000>;
- trip2-type = "active";
- trip2-cdev-num = <1>;
- trip2-cdev-name0 = "thermal-cpufreq-0";
-
- trip3-temp = <85000>;
- trip3-type = "critical";
- trip3-cdev-num = <0>;
-
- status = "okay";
- };
-
ab8500 {
ab8500-gpio {
/*
--
2.21.0
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* [PATCH 2/2] ARM: dts: ux500: Update thermal zone
From: Linus Walleij @ 2019-08-28 13:52 UTC (permalink / raw)
To: linux-arm-kernel, Ulf Hansson; +Cc: Linus Walleij, Daniel Lezcano
In-Reply-To: <20190828135218.7307-1-linus.walleij@linaro.org>
After moving the DB8500 thermal driver to use device tree
we define the default thermal zone for the Ux500 in the
device tree replacing the oldstyle hardcoded trigger
points.
This default thermal zone utilizes the cpufreq driver
(using the generic OF cpufreq back-end) as a passive
cooling device, and defines a critical trip point when
the temperature goes above 85 degrees celsius which will
(hopefully) make the system shut down if the temperature
cannot be controlled.
This default policy can later be augmented for specific
subdevices if these have tighter temperature conditions.
After this patch we get:
/sys/class/thermal/thermal_zone0 (CPU thermal zone)
This reports the rough temperature and trip points
from the thermal zone in the device tree.
By executing two yes > /dev/null & jobs fully utilizing
the two CPU cores we can notice the temperature climbing
in the thermal zone in response and falling when we kill
the jobs.
/syc/class/thermal/cooling_device0 (cpufreq cooling)
this reports all 4 available cpufreq frequencies as
states.
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-dbx5x0.dtsi | 57 +++++++++++++++++++------------
1 file changed, 36 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 7953eea7c486..9ee50f339e7a 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -44,6 +44,7 @@
clocks = <&prcmu_clk PRCMU_ARMSS>;
clock-names = "cpu";
clock-latency = <20000>;
+ #cooling-cells = <2>;
};
CPU1: cpu@301 {
device_type = "cpu";
@@ -52,6 +53,39 @@
};
};
+ thermal-zones {
+ /*
+ * Thermal zone for the SoC, using the thermal sensor in the
+ * PRCMU for temperature and the cpufreq driver for passive
+ * cooling.
+ */
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu-crit {
+ temperature = <85000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ trip = <&cpu_alert>;
+ cooling-device = <&CPU0 0 2>;
+ contribution = <100>;
+ };
+ };
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -502,33 +536,14 @@
reg = <0x80157450 0xC>;
};
- thermal@801573c0 {
+ thermal: thermal@801573c0 {
compatible = "stericsson,db8500-thermal";
reg = <0x801573c0 0x40>;
interrupt-parent = <&prcmu>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
<22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
- num-trips = <4>;
-
- trip0-temp = <70000>;
- trip0-type = "active";
- trip0-cdev-num = <1>;
- trip0-cdev-name0 = "thermal-cpufreq-0";
-
- trip1-temp = <75000>;
- trip1-type = "active";
- trip1-cdev-num = <1>;
- trip1-cdev-name0 = "thermal-cpufreq-0";
-
- trip2-temp = <80000>;
- trip2-type = "active";
- trip2-cdev-num = <1>;
- trip2-cdev-name0 = "thermal-cpufreq-0";
-
- trip3-temp = <85000>;
- trip3-type = "critical";
- trip3-cdev-num = <0>;
+ #thermal-sensor-cells = <0>;
};
db8500-prcmu-regulators {
--
2.21.0
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* Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox
From: Sudeep Holla @ 2019-08-28 13:58 UTC (permalink / raw)
To: Peng Fan
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
f.fainelli@gmail.com, andre.przywara@arm.com,
jassisinghbrar@gmail.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, dl-linux-imx, Sudeep Holla,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1567004515-3567-2-git-send-email-peng.fan@nxp.com>
On Wed, Aug 28, 2019 at 03:02:58AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
> actions in software layers running in the EL2 or EL3 exception levels.
> The term "ARM" here relates to the SMC instruction as part of the ARM
> instruction set, not as a standard endorsed by ARM Ltd.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> .../devicetree/bindings/mailbox/arm-smc.yaml | 125 +++++++++++++++++++++
> 1 file changed, 125 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml
> new file mode 100644
> index 000000000000..f8eb28d5e307
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM SMC Mailbox Interface
> +
> +maintainers:
> + - Peng Fan <peng.fan@nxp.com>
> +
> +description: |
> + This mailbox uses the ARM smc (secure monitor call) and hvc (hypervisor
> + call) instruction to trigger a mailbox-connected activity in firmware,
> + executing on the very same core as the caller. By nature this operation
> + is synchronous and this mailbox provides no way for asynchronous messages
> + to be delivered the other way round, from firmware to the OS, but
> + asynchronous notification could also be supported.
What do you mean by that ? I would prefer to drop the above line unless
I am missing something. IMO it contradicts the previous statement less
you elaborate more on this.
> However the value of
> + r0/w0/x0 the firmware returns after the smc call is delivered as a received
> + message to the mailbox framework, so a synchronous communication can be
> + established, for a asynchronous notification, no value will be returned.
I assume you refer to asynchronous communication from OS to firmware in the
above statement and "not asynchronous notification" from firmware to OS.
> + The exact meaning of both the action the mailbox triggers as well as the
> + return value is defined by their users and is not subject to this binding.
> +
> + One use case of this mailbox is the SCMI interface, which uses shared memory
> + to transfer commands and parameters, and a mailbox to trigger a function
> + call. This allows SoCs without a separate management processor (or when
> + such a processor is not available or used) to use this standardized
> + interface anyway.
> +
Not sure if reference to SCMI is needed at all but I don't have any
objections to it, just thought worth mentioning.
> + This binding describes no hardware, but establishes a firmware interface.
> + Upon receiving an SMC using one of the described SMC function identifiers,
> + the firmware is expected to trigger some mailbox connected functionality.
> + The communication follows the ARM SMC calling convention.
> + Firmware expects an SMC function identifier in r0 or w0. The supported
> + identifiers are passed from consumers, or listed in the the arm,func-ids
> + properties as described below. The firmware can return one value in
> + the first SMC result register, it is expected to be an error value,
> + which shall be propagated to the mailbox client.
> +
> + Any core which supports the SMC or HVC instruction can be used, as long as
> + a firmware component running in EL3 or EL2 is handling these calls.
> +
Other than the above points, I am fine with it. Once fixed,
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Note I haven't reviewed the yaml scheme, but just binding in general.
--
Regards,
Sudeep
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^ permalink raw reply
* Re: [PATCH v5 2/2] mailbox: introduce ARM SMC based mailbox
From: Sudeep Holla @ 2019-08-28 14:02 UTC (permalink / raw)
To: Peng Fan
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
f.fainelli@gmail.com, andre.przywara@arm.com,
jassisinghbrar@gmail.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, dl-linux-imx, Sudeep Holla,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1567004515-3567-3-git-send-email-peng.fan@nxp.com>
On Wed, Aug 28, 2019 at 03:03:02AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> This mailbox driver implements a mailbox which signals transmitted data
> via an ARM smc (secure monitor call) instruction. The mailbox receiver
> is implemented in firmware and can synchronously return data when it
> returns execution to the non-secure world again.
> An asynchronous receive path is not implemented.
> This allows the usage of a mailbox to trigger firmware actions on SoCs
> which either don't have a separate management processor or on which such
> a core is not available. A user of this mailbox could be the SCP
> interface.
>
> Modified from Andre Przywara's v2 patch
> https://lore.kernel.org/patchwork/patch/812999/
>
> Cc: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/mailbox/Kconfig | 7 ++
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm-smc-mailbox.c | 215 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 224 insertions(+)
> create mode 100644 drivers/mailbox/arm-smc-mailbox.c
>
[...]
> +static int arm_smc_mbox_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mbox_controller *mbox;
> + struct arm_smc_chan_data *chan_data;
> + const char *method;
> + bool mem_trans = false;
> + int ret, i;
> + u32 val;
> +
> + if (!of_property_read_u32(dev->of_node, "arm,num-chans", &val)) {
> + if (!val) {
> + dev_err(dev, "invalid arm,num-chans value %u\n", val);
> + return -EINVAL;
> + }
> + } else {
> + return -EINVAL;
> + }
> +
> + if (!of_property_read_string(dev->of_node, "transports", &method)) {
> + if (!strcmp("mem", method)) {
> + mem_trans = true;
> + } else if (!strcmp("reg", method)) {
> + mem_trans = false;
> + } else {
> + dev_warn(dev, "invalid \"transports\" property: %s\n",
> + method);
> +
> + return -EINVAL;
> + }
> + } else {
> + return -EINVAL;
> + }
> +
> + if (!of_property_read_string(dev->of_node, "method", &method)) {
> + if (!strcmp("hvc", method)) {
> + invoke_smc_mbox_fn = __invoke_fn_hvc;
> + } else if (!strcmp("smc", method)) {
> + invoke_smc_mbox_fn = __invoke_fn_smc;
> + } else {
> + dev_warn(dev, "invalid \"method\" property: %s\n",
> + method);
> +
> + return -EINVAL;
> + }
> + } else {
> + return -EINVAL;
> + }
> +
> + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
> + if (!mbox)
> + return -ENOMEM;
> +
> + mbox->num_chans = val;
> + mbox->chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*mbox->chans),
> + GFP_KERNEL);
> + if (!mbox->chans)
> + return -ENOMEM;
> +
> + chan_data = devm_kcalloc(dev, mbox->num_chans, sizeof(*chan_data),
> + GFP_KERNEL);
> + if (!chan_data)
> + return -ENOMEM;
> +
> + for (i = 0; i < mbox->num_chans; i++) {
> + u32 function_id;
> +
> + ret = of_property_read_u32_index(dev->of_node,
> + "arm,func-ids", i,
> + &function_id);
I missed it in binding but I thought we agreed to make this "arm,func-ids"
a required property and not optional ?
--
Regards,
Sudeep
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^ permalink raw reply
* [PATCH v8] thermal: cpu_cooling: Migrate to using the EM framework
From: Quentin Perret @ 2019-08-28 14:02 UTC (permalink / raw)
To: edubezval, rui.zhang, javi.merino, viresh.kumar, amit.kachhap,
rjw, catalin.marinas, will, daniel.lezcano
Cc: linux-pm, linux-kernel, quentin.perret, mka, ionela.voinescu,
dietmar.eggemann, linux-arm-kernel
In-Reply-To: <20190812084235.21440-5-quentin.perret@arm.com>
The newly introduced Energy Model framework manages power cost tables in
a generic way. Moreover, it supports several types of models since the
tables can come from DT or firmware (through SCMI) for example. On the
other hand, the cpu_cooling subsystem manages its own power cost tables
using only DT data.
In order to avoid the duplication of data in the kernel, and in order to
enable IPA with EMs coming from more than just DT, remove the private
tables from cpu_cooling.c and migrate it to using the centralized EM
framework. Doing so should have no visible functional impact for
existing users of IPA since:
- recent extenstions to the the PM_OPP infrastructure enable the
registration of EMs in PM_EM using the DT property used by IPA;
- the existing upstream cpufreq drivers marked with the
'CPUFREQ_IS_COOLING_DEV' flag all use the aforementioned PM_OPP
infrastructure, which means they all support PM_EM. The only two
exceptions are qoriq-cpufreq which doesn't in fact use an EM and
scmi-cpufreq which doesn't use DT for power costs.
For existing users of cpu_cooling, PM_EM tables will contain the exact
same power values that IPA used to compute on its own until now. The
only new dependency for them is to compile in CONFIG_ENERGY_MODEL.
The case where the thermal subsystem is used without an Energy Model
(cpufreq_cooling_ops) is handled by looking directly at CPUFreq's
frequency table which is already a dependency for cpu_cooling.c anyway.
Since the thermal framework expects the cooling states in a particular
order, bail out whenever the CPUFreq table is unsorted, since that is
fairly uncommon in general, and there are currently no users of
cpu_cooling for this use-case.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Quentin Perret <quentin.perret@arm.com>
---
In v8 I fixed the checkpatch.pl errors reported by Rui (thanks for
pointing them out) due to whitespaces instead of tabs. There is no
actual code change. The one warning left is intentional, but do let me
know if you have better ideas to make it go away.
Thanks,
Quentin
---
drivers/thermal/Kconfig | 1 +
drivers/thermal/cpu_cooling.c | 249 ++++++++++++----------------------
2 files changed, 90 insertions(+), 160 deletions(-)
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 9966364a6deb..340853a3ca48 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -144,6 +144,7 @@ config THERMAL_GOV_USER_SPACE
config THERMAL_GOV_POWER_ALLOCATOR
bool "Power allocator thermal governor"
+ depends on ENERGY_MODEL
help
Enable this to manage platform thermals by dynamically
allocating and limiting power to devices.
diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index 498f59ab64b2..89be25210ed4 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -19,6 +19,7 @@
#include <linux/slab.h>
#include <linux/cpu.h>
#include <linux/cpu_cooling.h>
+#include <linux/energy_model.h>
#include <trace/events/thermal.h>
@@ -36,21 +37,6 @@
* ...
*/
-/**
- * struct freq_table - frequency table along with power entries
- * @frequency: frequency in KHz
- * @power: power in mW
- *
- * This structure is built when the cooling device registers and helps
- * in translating frequency to power and vice versa.
- */
-struct freq_table {
- u32 frequency;
-#ifdef CONFIG_THERMAL_GOV_POWER_ALLOCATOR
- u32 power;
-#endif
-};
-
/**
* struct time_in_idle - Idle time stats
* @time: previous reading of the absolute time that this cpu was idle
@@ -72,7 +58,7 @@ struct time_in_idle {
* frequency.
* @max_level: maximum cooling level. One less than total number of valid
* cpufreq frequencies.
- * @freq_table: Freq table in descending order of frequencies
+ * @em: Reference on the Energy Model of the device
* @cdev: thermal_cooling_device pointer to keep track of the
* registered cooling device.
* @policy: cpufreq policy.
@@ -88,7 +74,7 @@ struct cpufreq_cooling_device {
unsigned int cpufreq_state;
unsigned int clipped_freq;
unsigned int max_level;
- struct freq_table *freq_table; /* In descending order */
+ struct em_perf_domain *em;
struct cpufreq_policy *policy;
struct list_head node;
struct time_in_idle *idle_time;
@@ -162,114 +148,40 @@ static int cpufreq_thermal_notifier(struct notifier_block *nb,
static unsigned long get_level(struct cpufreq_cooling_device *cpufreq_cdev,
unsigned int freq)
{
- struct freq_table *freq_table = cpufreq_cdev->freq_table;
- unsigned long level;
+ int i;
- for (level = 1; level <= cpufreq_cdev->max_level; level++)
- if (freq > freq_table[level].frequency)
+ for (i = cpufreq_cdev->max_level - 1; i >= 0; i--) {
+ if (freq > cpufreq_cdev->em->table[i].frequency)
break;
-
- return level - 1;
-}
-
-/**
- * update_freq_table() - Update the freq table with power numbers
- * @cpufreq_cdev: the cpufreq cooling device in which to update the table
- * @capacitance: dynamic power coefficient for these cpus
- *
- * Update the freq table with power numbers. This table will be used in
- * cpu_power_to_freq() and cpu_freq_to_power() to convert between power and
- * frequency efficiently. Power is stored in mW, frequency in KHz. The
- * resulting table is in descending order.
- *
- * Return: 0 on success, -EINVAL if there are no OPPs for any CPUs,
- * or -ENOMEM if we run out of memory.
- */
-static int update_freq_table(struct cpufreq_cooling_device *cpufreq_cdev,
- u32 capacitance)
-{
- struct freq_table *freq_table = cpufreq_cdev->freq_table;
- struct dev_pm_opp *opp;
- struct device *dev = NULL;
- int num_opps = 0, cpu = cpufreq_cdev->policy->cpu, i;
-
- dev = get_cpu_device(cpu);
- if (unlikely(!dev)) {
- pr_warn("No cpu device for cpu %d\n", cpu);
- return -ENODEV;
}
- num_opps = dev_pm_opp_get_opp_count(dev);
- if (num_opps < 0)
- return num_opps;
-
- /*
- * The cpufreq table is also built from the OPP table and so the count
- * should match.
- */
- if (num_opps != cpufreq_cdev->max_level + 1) {
- dev_warn(dev, "Number of OPPs not matching with max_levels\n");
- return -EINVAL;
- }
-
- for (i = 0; i <= cpufreq_cdev->max_level; i++) {
- unsigned long freq = freq_table[i].frequency * 1000;
- u32 freq_mhz = freq_table[i].frequency / 1000;
- u64 power;
- u32 voltage_mv;
-
- /*
- * Find ceil frequency as 'freq' may be slightly lower than OPP
- * freq due to truncation while converting to kHz.
- */
- opp = dev_pm_opp_find_freq_ceil(dev, &freq);
- if (IS_ERR(opp)) {
- dev_err(dev, "failed to get opp for %lu frequency\n",
- freq);
- return -EINVAL;
- }
-
- voltage_mv = dev_pm_opp_get_voltage(opp) / 1000;
- dev_pm_opp_put(opp);
-
- /*
- * Do the multiplication with MHz and millivolt so as
- * to not overflow.
- */
- power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv;
- do_div(power, 1000000000);
-
- /* power is stored in mW */
- freq_table[i].power = power;
- }
-
- return 0;
+ return cpufreq_cdev->max_level - i - 1;
}
static u32 cpu_freq_to_power(struct cpufreq_cooling_device *cpufreq_cdev,
u32 freq)
{
int i;
- struct freq_table *freq_table = cpufreq_cdev->freq_table;
- for (i = 1; i <= cpufreq_cdev->max_level; i++)
- if (freq > freq_table[i].frequency)
+ for (i = cpufreq_cdev->max_level - 1; i >= 0; i--) {
+ if (freq > cpufreq_cdev->em->table[i].frequency)
break;
+ }
- return freq_table[i - 1].power;
+ return cpufreq_cdev->em->table[i + 1].power;
}
static u32 cpu_power_to_freq(struct cpufreq_cooling_device *cpufreq_cdev,
u32 power)
{
int i;
- struct freq_table *freq_table = cpufreq_cdev->freq_table;
- for (i = 1; i <= cpufreq_cdev->max_level; i++)
- if (power > freq_table[i].power)
+ for (i = cpufreq_cdev->max_level - 1; i >= 0; i--) {
+ if (power > cpufreq_cdev->em->table[i].power)
break;
+ }
- return freq_table[i - 1].frequency;
+ return cpufreq_cdev->em->table[i + 1].frequency;
}
/**
@@ -410,7 +322,7 @@ static int cpufreq_state2power(struct thermal_cooling_device *cdev,
struct thermal_zone_device *tz,
unsigned long state, u32 *power)
{
- unsigned int freq, num_cpus;
+ unsigned int freq, num_cpus, idx;
struct cpufreq_cooling_device *cpufreq_cdev = cdev->devdata;
/* Request state should be less than max_level */
@@ -419,7 +331,8 @@ static int cpufreq_state2power(struct thermal_cooling_device *cdev,
num_cpus = cpumask_weight(cpufreq_cdev->policy->cpus);
- freq = cpufreq_cdev->freq_table[state].frequency;
+ idx = cpufreq_cdev->max_level - state;
+ freq = cpufreq_cdev->em->table[idx].frequency;
*power = cpu_freq_to_power(cpufreq_cdev, freq) * num_cpus;
return 0;
@@ -463,8 +376,59 @@ static int cpufreq_power2state(struct thermal_cooling_device *cdev,
power);
return 0;
}
+
+static inline bool em_is_sane(struct cpufreq_cooling_device *cpufreq_cdev,
+ struct em_perf_domain *em) {
+ struct cpufreq_policy *policy;
+ unsigned int nr_levels;
+
+ if (!em)
+ return false;
+
+ policy = cpufreq_cdev->policy;
+ if (!cpumask_equal(policy->related_cpus, to_cpumask(em->cpus))) {
+ pr_err("The span of pd %*pbl is misaligned with cpufreq policy %*pbl\n",
+ cpumask_pr_args(to_cpumask(em->cpus)),
+ cpumask_pr_args(policy->related_cpus));
+ return false;
+ }
+
+ nr_levels = cpufreq_cdev->max_level + 1;
+ if (em->nr_cap_states != nr_levels) {
+ pr_err("The number of cap states in pd %*pbl (%u) doesn't match the number of cooling levels (%u)\n",
+ cpumask_pr_args(to_cpumask(em->cpus)),
+ em->nr_cap_states, nr_levels);
+ return false;
+ }
+
+ return true;
+}
#endif /* CONFIG_THERMAL_GOV_POWER_ALLOCATOR */
+static unsigned int get_state_freq(struct cpufreq_cooling_device *cpufreq_cdev,
+ unsigned long state)
+{
+ struct cpufreq_policy *policy;
+ unsigned long idx;
+
+#ifdef CONFIG_THERMAL_GOV_POWER_ALLOCATOR
+ /* Use the Energy Model table if available */
+ if (cpufreq_cdev->em) {
+ idx = cpufreq_cdev->max_level - state;
+ return cpufreq_cdev->em->table[idx].frequency;
+ }
+#endif
+
+ /* Otherwise, fallback on the CPUFreq table */
+ policy = cpufreq_cdev->policy;
+ if (policy->freq_table_sorted == CPUFREQ_TABLE_SORTED_ASCENDING)
+ idx = cpufreq_cdev->max_level - state;
+ else
+ idx = state;
+
+ return policy->freq_table[idx].frequency;
+}
+
/* cpufreq cooling device callback functions are defined below */
/**
@@ -530,7 +494,7 @@ static int cpufreq_set_cur_state(struct thermal_cooling_device *cdev,
if (cpufreq_cdev->cpufreq_state == state)
return 0;
- clip_freq = cpufreq_cdev->freq_table[state].frequency;
+ clip_freq = get_state_freq(cpufreq_cdev, state);
cpufreq_cdev->cpufreq_state = state;
cpufreq_cdev->clipped_freq = clip_freq;
@@ -552,26 +516,12 @@ static struct notifier_block thermal_cpufreq_notifier_block = {
.notifier_call = cpufreq_thermal_notifier,
};
-static unsigned int find_next_max(struct cpufreq_frequency_table *table,
- unsigned int prev_max)
-{
- struct cpufreq_frequency_table *pos;
- unsigned int max = 0;
-
- cpufreq_for_each_valid_entry(pos, table) {
- if (pos->frequency > max && pos->frequency < prev_max)
- max = pos->frequency;
- }
-
- return max;
-}
-
/**
* __cpufreq_cooling_register - helper function to create cpufreq cooling device
* @np: a valid struct device_node to the cooling device device tree node
* @policy: cpufreq policy
* Normally this should be same as cpufreq policy->related_cpus.
- * @capacitance: dynamic power coefficient for these cpus
+ * @em: Energy Model of the cpufreq policy
*
* This interface function registers the cpufreq cooling device with the name
* "thermal-cpufreq-%x". This api can support multiple instances of cpufreq
@@ -583,12 +533,13 @@ static unsigned int find_next_max(struct cpufreq_frequency_table *table,
*/
static struct thermal_cooling_device *
__cpufreq_cooling_register(struct device_node *np,
- struct cpufreq_policy *policy, u32 capacitance)
+ struct cpufreq_policy *policy,
+ struct em_perf_domain *em)
{
struct thermal_cooling_device *cdev;
struct cpufreq_cooling_device *cpufreq_cdev;
char dev_name[THERMAL_NAME_LENGTH];
- unsigned int freq, i, num_cpus;
+ unsigned int i, num_cpus;
int ret;
struct thermal_cooling_device_ops *cooling_ops;
bool first;
@@ -622,55 +573,38 @@ __cpufreq_cooling_register(struct device_node *np,
/* max_level is an index, not a counter */
cpufreq_cdev->max_level = i - 1;
- cpufreq_cdev->freq_table = kmalloc_array(i,
- sizeof(*cpufreq_cdev->freq_table),
- GFP_KERNEL);
- if (!cpufreq_cdev->freq_table) {
- cdev = ERR_PTR(-ENOMEM);
- goto free_idle_time;
- }
-
ret = ida_simple_get(&cpufreq_ida, 0, 0, GFP_KERNEL);
if (ret < 0) {
cdev = ERR_PTR(ret);
- goto free_table;
+ goto free_idle_time;
}
cpufreq_cdev->id = ret;
snprintf(dev_name, sizeof(dev_name), "thermal-cpufreq-%d",
cpufreq_cdev->id);
- /* Fill freq-table in descending order of frequencies */
- for (i = 0, freq = -1; i <= cpufreq_cdev->max_level; i++) {
- freq = find_next_max(policy->freq_table, freq);
- cpufreq_cdev->freq_table[i].frequency = freq;
-
- /* Warn for duplicate entries */
- if (!freq)
- pr_warn("%s: table has duplicate entries\n", __func__);
- else
- pr_debug("%s: freq:%u KHz\n", __func__, freq);
- }
-
cooling_ops = &cpufreq_cooling_ops;
#ifdef CONFIG_THERMAL_GOV_POWER_ALLOCATOR
- if (capacitance) {
- ret = update_freq_table(cpufreq_cdev, capacitance);
- if (ret) {
- cdev = ERR_PTR(ret);
- goto remove_ida;
- }
+ if (em_is_sane(cpufreq_cdev, em)) {
+ cpufreq_cdev->em = em;
cooling_ops->get_requested_power = cpufreq_get_requested_power;
cooling_ops->state2power = cpufreq_state2power;
cooling_ops->power2state = cpufreq_power2state;
- }
+ } else
#endif
+ if (policy->freq_table_sorted == CPUFREQ_TABLE_UNSORTED) {
+ pr_err("%s: unsorted frequency tables are not supported\n",
+ __func__);
+ cdev = ERR_PTR(-EINVAL);
+ goto remove_ida;
+ }
+
cdev = thermal_of_cooling_device_register(np, dev_name, cpufreq_cdev,
cooling_ops);
if (IS_ERR(cdev))
goto remove_ida;
- cpufreq_cdev->clipped_freq = cpufreq_cdev->freq_table[0].frequency;
+ cpufreq_cdev->clipped_freq = get_state_freq(cpufreq_cdev, 0);
mutex_lock(&cooling_list_lock);
/* Register the notifier for first cpufreq cooling device */
@@ -686,8 +620,6 @@ __cpufreq_cooling_register(struct device_node *np,
remove_ida:
ida_simple_remove(&cpufreq_ida, cpufreq_cdev->id);
-free_table:
- kfree(cpufreq_cdev->freq_table);
free_idle_time:
kfree(cpufreq_cdev->idle_time);
free_cdev:
@@ -709,7 +641,7 @@ __cpufreq_cooling_register(struct device_node *np,
struct thermal_cooling_device *
cpufreq_cooling_register(struct cpufreq_policy *policy)
{
- return __cpufreq_cooling_register(NULL, policy, 0);
+ return __cpufreq_cooling_register(NULL, policy, NULL);
}
EXPORT_SYMBOL_GPL(cpufreq_cooling_register);
@@ -737,7 +669,6 @@ of_cpufreq_cooling_register(struct cpufreq_policy *policy)
{
struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
struct thermal_cooling_device *cdev = NULL;
- u32 capacitance = 0;
if (!np) {
pr_err("cpu_cooling: OF node not available for cpu%d\n",
@@ -746,10 +677,9 @@ of_cpufreq_cooling_register(struct cpufreq_policy *policy)
}
if (of_find_property(np, "#cooling-cells", NULL)) {
- of_property_read_u32(np, "dynamic-power-coefficient",
- &capacitance);
+ struct em_perf_domain *em = em_cpu_get(policy->cpu);
- cdev = __cpufreq_cooling_register(np, policy, capacitance);
+ cdev = __cpufreq_cooling_register(np, policy, em);
if (IS_ERR(cdev)) {
pr_err("cpu_cooling: cpu%d failed to register as cooling device: %ld\n",
policy->cpu, PTR_ERR(cdev));
@@ -791,7 +721,6 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
thermal_cooling_device_unregister(cdev);
ida_simple_remove(&cpufreq_ida, cpufreq_cdev->id);
kfree(cpufreq_cdev->idle_time);
- kfree(cpufreq_cdev->freq_table);
kfree(cpufreq_cdev);
}
EXPORT_SYMBOL_GPL(cpufreq_cooling_unregister);
--
2.22.1
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^ permalink raw reply related
* RE: FYI: imx-sdma firmware is not compatible with SLUB slab allocator
From: Robin Gong @ 2019-08-28 14:05 UTC (permalink / raw)
To: Jurgen Lambrecht, Leonard Crestez
Cc: Aisheng Dong, dl-linux-imx, linux-arm-kernel@lists.infradead.org
In-Reply-To: <7282882c-1c79-9685-4bfe-80195976c8d6@televic.com>
On 8/28/19 17:27, Jurgen Lambrecht wrote:
>
> On 8/27/19 5:04 PM, Leonard Crestez wrote:
> > CAUTION: This Email originated from outside Televic. Do not click links or
> open attachments unless you recognize the sender and know the content is
> safe.
> >
> >
> > On 27.08.2019 16:35, Jurgen Lambrecht wrote:
> >> We are updating our kernel on our custom board with an iMX6UL from
> >> 3.14 to 4.19, and when loading linux-firmware/imx/sdma/sdma-imx6q.bin
> >> v3.5 the kernel hangs when booting, only "Starting kernel ..." is
> >> printed (by uBoot I think).
> > If you enable "earlycon" you should be able to see an useful error
> > message from crashes in early boot.
> >
> > Enabling earlycon is board-specific: if you have a correct
> > /chosen/stdout-path reference in dts just adding "earlycon" to kernel
> > cmdline should work otherwise you can specify
> > earlycon=ec_imx6q,0x202000,115200 with the exact address depending on
> > which uart is console on your board.
>
> OK, thanks. First time I hear of earlycon.
>
> But as I thought (because of logs with other kernel versions) the kernel just
> hangs when loading the sdma driver.
> Now it is v3.5, but I also tried v3.3 a few weeks ago.
>
> This is the last kernel log (below the full log):
>
> [ 2.312336] imx-sdma 20ec000.sdma: loaded firmware 3.5
>
> About the DT config, I enabled sdma on all that I found: standard dtsi only
> has sdma enabled for SAI. But the freescale 4.1 kernel has more: I also
> enabled sdma for ecspi1 to ecspi4, uart1 to uart8.
> But as a test I have also removed all sdma entries from DT, and still it hangs.
Could you help check if below commit in your side?
commit ebb853b1bd5f659b92c71dc6a9de44cfc37c78c0
Author: Lucas Stach <l.stach@pengutronix.de>
Date: Tue Nov 6 03:40:28 2018 +0000
Revert "dmaengine: imx-sdma: alloclate bd memory from dma pool"
This reverts commit fe5b85c656bc. The SDMA engine needs the descriptors to
be contiguous in memory. As the dma pool API is only able to provide a
single descriptor per alloc invocation there is no guarantee that multiple
descriptors satisfy this requirement. Also the code in question is broken
as it only allocates memory for a single descriptor, without looking at the
number of descriptors required for the transfer, leading to out-of-bounds
accesses when the descriptors are written.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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^ permalink raw reply
* [PATCH v2 0/3] arm64: meson-sm1: add support for the SM1 based VIM3L
From: Neil Armstrong @ 2019-08-28 14:11 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
This patchset adds support for the Amlogic SM1 based Khadas VIM3L variant.
The S903D3 package variant of SM1 is pin-to-pin compatible with the
S922X and A311d, so only internal DT changes are needed :
- DVFS support is different
- Audio support not yet available for SM1
This patchset moved all the non-g12b nodes to meson-khadas-vim3.dtsi
and add the sm1 specific nodes into meson-sm1-khadas-vim3l.dts.
Display has a color conversion bug on SM1 by using a more recent vendor
bootloader on the SM1 based VIM3, this is out of scope of this patchset
and will be fixed in the drm/meson driver.
Dependencies:
- patch 1,2: None
- patch 3: Depends on the "arm64: meson-sm1: add support for DVFS" patchset at [1]
Changes since v1:
- renamed compatible to khadas,vim3l
- renamed DT file to meson-sm1-khadas-vim3l.dts
[1] https://patchwork.kernel.org/cover/11109411/
Neil Armstrong (3):
arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
amlogic: arm: add Amlogic SM1 based Khadas VIM3L bindings
arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
.../devicetree/bindings/arm/amlogic.yaml | 3 +-
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../amlogic/meson-g12b-a311d-khadas-vim3.dts | 1 +
.../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 355 -----------------
.../amlogic/meson-g12b-s922x-khadas-vim3.dts | 1 +
.../boot/dts/amlogic/meson-khadas-vim3.dtsi | 360 ++++++++++++++++++
.../dts/amlogic/meson-sm1-khadas-vim3l.dts | 70 ++++
7 files changed, 435 insertions(+), 356 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
--
2.22.0
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^ permalink raw reply
* [PATCH v2 2/3] amlogic: arm: add Amlogic SM1 based Khadas VIM3L bindings
From: Neil Armstrong @ 2019-08-28 14:11 UTC (permalink / raw)
To: khilman, devicetree
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141157.15503-1-narmstrong@baylibre.com>
The Khadas VIM3 is also available as VIM3L with the Pin-to-pin compatible
Amlogic SM1 SoC in the S905D3 variant package.
Change the description to match the S905X3/D3/Y3 variants like the G12A
description, and add the khadas,vim3l compatible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index b48ea1e4913a..99015cef8bb1 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -150,9 +150,10 @@ properties:
- const: amlogic,s922x
- const: amlogic,g12b
- - description: Boards with the Amlogic Meson SM1 S905X3 SoC
+ - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
- seirobotics,sei610
+ - khadas,vim3l
- const: amlogic,sm1
...
--
2.22.0
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^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
From: Neil Armstrong @ 2019-08-28 14:11 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141157.15503-1-narmstrong@baylibre.com>
To prepare support of the Amlogic SM1 based Khadas VIM3, move the non-G12B
specific nodes (all except DVFS and Audio) to a new meson-khadas-vim3.dtsi
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../amlogic/meson-g12b-a311d-khadas-vim3.dts | 1 +
.../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 355 -----------------
.../amlogic/meson-g12b-s922x-khadas-vim3.dts | 1 +
.../boot/dts/amlogic/meson-khadas-vim3.dtsi | 360 ++++++++++++++++++
4 files changed, 362 insertions(+), 355 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
index 73128ed24361..3a6a1e0c1e32 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "meson-g12b-a311d.dtsi"
+#include "meson-khadas-vim3.dtsi"
#include "meson-g12b-khadas-vim3.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
index 9c3ca2edc725..554863429aa6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
@@ -5,116 +5,9 @@
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
*/
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- model = "Khadas VIM3";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- white {
- label = "vim3:white:sys";
- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- red {
- label = "vim3:red";
- gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
vddcpu_a: regulator-vddcpu-a {
/*
* MP8756GD Regulator.
@@ -153,62 +46,6 @@
regulator-always-on;
};
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vsys_3v3: regulator-vsys_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VSYS_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb_pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-KHADAS-VIM3";
@@ -269,20 +106,6 @@
status = "okay";
};
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
&clkc_audio {
status = "okay";
};
@@ -329,31 +152,6 @@
clock-latency = <50000>;
};
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
&frddr_b {
status = "okay";
};
@@ -362,46 +160,6 @@
status = "okay";
};
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
- pinctrl-names = "default";
-
- gpio_expander: gpio-controller@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- vcc-supply = <&vcc_3v3>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-khadas";
-};
-
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
@@ -418,81 +176,6 @@
status = "okay";
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vsys_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
&tdmif_b {
status = "okay";
};
@@ -504,41 +187,3 @@
&tohdmitx {
status = "okay";
};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb_pwr>;
-};
-
-&usb3_pcie_phy {
- phy-supply = <&usb_pwr>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
-};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
index 6bcf972b8bfa..b73deb282120 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "meson-g12b-s922x.dtsi"
+#include "meson-khadas-vim3.dtsi"
#include "meson-g12b-khadas-vim3.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
new file mode 100644
index 000000000000..8647da7d6609
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ model = "Khadas VIM3";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Function";
+ linux,code = <KEY_FN>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ white {
+ label = "vim3:white:sys";
+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ red {
+ label = "vim3:red";
+ gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vsys_3v3: regulator-vsys_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSYS_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+ pinctrl-names = "default";
+
+ gpio_expander: gpio-controller@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ vcc-supply = <&vcc_3v3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+ linux,rc-map-name = "rc-khadas";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vsys_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+};
--
2.22.0
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^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
From: Neil Armstrong @ 2019-08-28 14:11 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141157.15503-1-narmstrong@baylibre.com>
Add the Amlogic SM1 based Khadas VIM3L, sharing all the same features
as the G12B based VIM3, but:
- a different DVFS support since only a single cluster is available
- audio is still not available on SM1
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../dts/amlogic/meson-sm1-khadas-vim3l.dts | 70 +++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index edbf128e7707..84afecba9ec0 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
new file mode 100644
index 000000000000..5233bd7cacfb
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include "meson-khadas-vim3.dtsi"
+
+/ {
+ compatible = "khadas,vim3l", "amlogic,sm1";
+ model = "Khadas VIM3L";
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * Silergy SY8030DEC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&vsys_3v3>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
--
2.22.0
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^ permalink raw reply related
* Re: [PATCH v2 2/3] amlogic: arm: add Amlogic SM1 based Khadas VIM3L bindings
From: Neil Armstrong @ 2019-08-28 14:15 UTC (permalink / raw)
To: khilman, devicetree; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel
In-Reply-To: <20190828141157.15503-3-narmstrong@baylibre.com>
Damn wrong subject.. please ignore this one.
Neil
On 28/08/2019 16:11, Neil Armstrong wrote:
> The Khadas VIM3 is also available as VIM3L with the Pin-to-pin compatible
> Amlogic SM1 SoC in the S905D3 variant package.
>
> Change the description to match the S905X3/D3/Y3 variants like the G12A
> description, and add the khadas,vim3l compatible.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/arm/amlogic.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
> index b48ea1e4913a..99015cef8bb1 100644
> --- a/Documentation/devicetree/bindings/arm/amlogic.yaml
> +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
> @@ -150,9 +150,10 @@ properties:
> - const: amlogic,s922x
> - const: amlogic,g12b
>
> - - description: Boards with the Amlogic Meson SM1 S905X3 SoC
> + - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
> items:
> - enum:
> - seirobotics,sei610
> + - khadas,vim3l
> - const: amlogic,sm1
> ...
>
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^ permalink raw reply
* Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs
From: Mike Leach @ 2019-08-28 14:15 UTC (permalink / raw)
To: Leo Yan; +Cc: Coresight ML, linux-arm-kernel, Mathieu Poirier
In-Reply-To: <20190828051847.GG26133@leoy-ThinkPad-X240s>
HI Leo,
On Wed, 28 Aug 2019 at 06:18, Leo Yan <leo.yan@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> > An API to control single-shot comparator operation was missing from sysfs.
> > This adds the parameters to sysfs to allow programming of this feature.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> > .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++
> > drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++-
> > drivers/hwtracing/coresight/coresight-etm4x.h | 3 +
> > 3 files changed, 150 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 483976074779..7c019dda1236 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
> > for (i = 0; i < drvdata->nr_resource; i++)
> > config->res_ctrl[i] = 0x0;
> >
> > + config->ss_idx = 0x0;
> > for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > config->ss_ctrl[i] = 0x0;
> > config->ss_pe_cmp[i] = 0x0;
> > @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
> > }
> > static DEVICE_ATTR_RW(res_ctrl);
> >
> > +static ssize_t sshot_idx_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + val = config->ss_idx;
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_idx_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > + if (val >= drvdata->nr_ss_cmp)
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + config->ss_idx = val;
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_idx);
> > +
> > +static ssize_t sshot_ctrl_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_ctrl[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_ctrl_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + u8 idx;
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + idx = config->ss_idx;
> > + config->ss_ctrl[idx] = val & GENMASK(24, 0);
> > + /* must clear bit 31 in related status register on programming */
> > + config->ss_status[idx] &= ~BIT(31);
>
> Since function etm4_enable_hw() will clear ss_status's bit 31 when
> program TRCSSCSRn, so is here redundant to clear bit 31?
>
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_ctrl);
> > +
> > +static ssize_t sshot_status_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_status[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +static DEVICE_ATTR_RO(sshot_status);
> > +
> > +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_pe_cmp[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + u8 idx;
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + idx = config->ss_idx;
> > + config->ss_ctrl[idx] = val & GENMASK(7, 0);
> > + /* must clear bit 31 in related status register on programming */
> > + config->ss_status[idx] &= ~BIT(31);
>
> Same question for if it's redundant to clear bit 31?
>
> Thanks,
> Leo Yan
>
The sysfs representation is not the current state of these registers,
but the values that will be programmed on enabling the hardware. We do
not write anything to hardware immediately.
So from a sysfs perspective, the bit clear is reflected in the status
register here to recognise that it will be programmed as cleared.
Should the same registers be set from a different path - e.g. perf,
then the status will automatically be cleared each time the hw is
enabled.
Regards
Mike
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> > +
> > static ssize_t ctxid_idx_show(struct device *dev,
> > struct device_attribute *attr,
> > char *buf)
> > @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
> > &dev_attr_addr_exlevel_s_ns.attr,
> > &dev_attr_addr_cmp_view.attr,
> > &dev_attr_vinst_pe_cmp_start_stop.attr,
> > + &dev_attr_sshot_idx.attr,
> > + &dev_attr_sshot_ctrl.attr,
> > + &dev_attr_sshot_pe_ctrl.attr,
> > + &dev_attr_sshot_status.attr,
> > &dev_attr_seq_idx.attr,
> > &dev_attr_seq_state.attr,
> > &dev_attr_seq_event.attr,
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index d8b078d0cc7f..fb7083218410 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > drvdata->base + TRCRSCTLRn(i));
> >
> > for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + /* always clear status bit on restart if using single-shot */
> > + if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > + config->ss_status[i] &= ~BIT(31);
> > writel_relaxed(config->ss_ctrl[i],
> > drvdata->base + TRCSSCCRn(i));
> > writel_relaxed(config->ss_status[i],
> > @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
> > {
> > u32 control;
> > struct etmv4_drvdata *drvdata = info;
> > + struct etmv4_config *config = &drvdata->config;
> > + struct device *etm_dev = &drvdata->csdev->dev;
> > + int i;
> >
> > CS_UNLOCK(drvdata->base);
> >
> > @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
> > isb();
> > writel_relaxed(control, drvdata->base + TRCPRGCTLR);
> >
> > + /* wait for TRCSTATR.PMSTABLE to go to '1' */
> > + if (coresight_timeout(drvdata->base, TRCSTATR,
> > + TRCSTATR_PMSTABLE_BIT, 1))
> > + dev_err(etm_dev,
> > + "timeout while waiting for PM stable Trace Status\n");
> > +
> > + /* read the status of the single shot comparators */
> > + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + config->ss_status[i] =
> > + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > + }
> > +
> > coresight_disclaim_device_unlocked(drvdata->base);
> >
> > CS_LOCK(drvdata->base);
> > @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
> > u32 etmidr4;
> > u32 etmidr5;
> > struct etmv4_drvdata *drvdata = info;
> > + int i;
> >
> > /* Make sure all registers are accessible */
> > etm4_os_unlock(drvdata);
> > @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
> > drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
> > /*
> > * NUMSSCC, bits[23:20] the number of single-shot
> > - * comparator control for tracing
> > + * comparator control for tracing. Read any status regs as these
> > + * also contain RO capability data.
> > */
> > drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> > + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + drvdata->config.ss_status[i] =
> > + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > + }
> > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> > drvdata->numcidc = BMVAL(etmidr4, 24, 27);
> > /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 60bc2fb5159b..be8b32ea1654 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -175,6 +175,7 @@
> > ETM_MODE_EXCL_USER)
> >
> > #define TRCSTATR_IDLE_BIT 0
> > +#define TRCSTATR_PMSTABLE_BIT 1
> > #define ETM_DEFAULT_ADDR_COMP 0
> >
> > /* PowerDown Control Register bits */
> > @@ -226,6 +227,7 @@
> > * @cntr_val: Sets or returns the value for a counter.
> > * @res_idx: Resource index selector.
> > * @res_ctrl: Controls the selection of the resources in the trace unit.
> > + * @ss_idx: Single-shot index selector.
> > * @ss_ctrl: Controls the corresponding single-shot comparator resource.
> > * @ss_status: The status of the corresponding single-shot comparator.
> > * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
> > @@ -269,6 +271,7 @@ struct etmv4_config {
> > u32 cntr_val[ETMv4_MAX_CNTR];
> > u8 res_idx;
> > u32 res_ctrl[ETM_MAX_RES_SEL];
> > + u8 ss_idx;
> > u32 ss_ctrl[ETM_MAX_SS_CMP];
> > u32 ss_status[ETM_MAX_SS_CMP];
> > u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> > --
> > 2.17.1
> >
> > _______________________________________________
> > CoreSight mailing list
> > CoreSight@lists.linaro.org
> > https://lists.linaro.org/mailman/listinfo/coresight
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs
From: Mike Leach @ 2019-08-28 14:15 UTC (permalink / raw)
To: Mathieu Poirier; +Cc: Coresight ML, linux-arm-kernel, Suzuki K. Poulose
In-Reply-To: <20190827222718.GC14958@xps15>
Hi,
On Tue, 27 Aug 2019 at 23:27, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> > An API to control single-shot comparator operation was missing from sysfs.
> > This adds the parameters to sysfs to allow programming of this feature.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> > .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++
> > drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++-
> > drivers/hwtracing/coresight/coresight-etm4x.h | 3 +
> > 3 files changed, 150 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 483976074779..7c019dda1236 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
> > for (i = 0; i < drvdata->nr_resource; i++)
> > config->res_ctrl[i] = 0x0;
> >
> > + config->ss_idx = 0x0;
> > for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > config->ss_ctrl[i] = 0x0;
> > config->ss_pe_cmp[i] = 0x0;
> > @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
> > }
> > static DEVICE_ATTR_RW(res_ctrl);
> >
> > +static ssize_t sshot_idx_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + val = config->ss_idx;
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_idx_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > + if (val >= drvdata->nr_ss_cmp)
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + config->ss_idx = val;
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_idx);
> > +
> > +static ssize_t sshot_ctrl_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_ctrl[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_ctrl_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + u8 idx;
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + idx = config->ss_idx;
> > + config->ss_ctrl[idx] = val & GENMASK(24, 0);
> > + /* must clear bit 31 in related status register on programming */
> > + config->ss_status[idx] &= ~BIT(31);
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_ctrl);
> > +
> > +static ssize_t sshot_status_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_status[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +static DEVICE_ATTR_RO(sshot_status);
> > +
> > +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> > + struct device_attribute *attr,
> > + char *buf)
> > +{
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + val = config->ss_pe_cmp[config->ss_idx];
> > + spin_unlock(&drvdata->spinlock);
> > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > +}
> > +
> > +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + u8 idx;
> > + unsigned long val;
> > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct etmv4_config *config = &drvdata->config;
> > +
> > + if (kstrtoul(buf, 16, &val))
> > + return -EINVAL;
> > +
> > + spin_lock(&drvdata->spinlock);
> > + idx = config->ss_idx;
> > + config->ss_ctrl[idx] = val & GENMASK(7, 0);
>
> config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
>
Good spot, Thanks
Mike
> > + /* must clear bit 31 in related status register on programming */
> > + config->ss_status[idx] &= ~BIT(31);
> > + spin_unlock(&drvdata->spinlock);
> > + return size;
> > +}
> > +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> > +
> > static ssize_t ctxid_idx_show(struct device *dev,
> > struct device_attribute *attr,
> > char *buf)
> > @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
> > &dev_attr_addr_exlevel_s_ns.attr,
> > &dev_attr_addr_cmp_view.attr,
> > &dev_attr_vinst_pe_cmp_start_stop.attr,
> > + &dev_attr_sshot_idx.attr,
> > + &dev_attr_sshot_ctrl.attr,
> > + &dev_attr_sshot_pe_ctrl.attr,
> > + &dev_attr_sshot_status.attr,
> > &dev_attr_seq_idx.attr,
> > &dev_attr_seq_state.attr,
> > &dev_attr_seq_event.attr,
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> > index d8b078d0cc7f..fb7083218410 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> > @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > drvdata->base + TRCRSCTLRn(i));
> >
> > for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + /* always clear status bit on restart if using single-shot */
> > + if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > + config->ss_status[i] &= ~BIT(31);
> > writel_relaxed(config->ss_ctrl[i],
> > drvdata->base + TRCSSCCRn(i));
> > writel_relaxed(config->ss_status[i],
> > @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
> > {
> > u32 control;
> > struct etmv4_drvdata *drvdata = info;
> > + struct etmv4_config *config = &drvdata->config;
> > + struct device *etm_dev = &drvdata->csdev->dev;
> > + int i;
> >
> > CS_UNLOCK(drvdata->base);
> >
> > @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
> > isb();
> > writel_relaxed(control, drvdata->base + TRCPRGCTLR);
> >
> > + /* wait for TRCSTATR.PMSTABLE to go to '1' */
> > + if (coresight_timeout(drvdata->base, TRCSTATR,
> > + TRCSTATR_PMSTABLE_BIT, 1))
> > + dev_err(etm_dev,
> > + "timeout while waiting for PM stable Trace Status\n");
> > +
> > + /* read the status of the single shot comparators */
> > + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + config->ss_status[i] =
> > + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > + }
> > +
> > coresight_disclaim_device_unlocked(drvdata->base);
> >
> > CS_LOCK(drvdata->base);
> > @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
> > u32 etmidr4;
> > u32 etmidr5;
> > struct etmv4_drvdata *drvdata = info;
> > + int i;
> >
> > /* Make sure all registers are accessible */
> > etm4_os_unlock(drvdata);
> > @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
> > drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
> > /*
> > * NUMSSCC, bits[23:20] the number of single-shot
> > - * comparator control for tracing
> > + * comparator control for tracing. Read any status regs as these
> > + * also contain RO capability data.
> > */
> > drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> > + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> > + drvdata->config.ss_status[i] =
> > + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> > + }
> > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> > drvdata->numcidc = BMVAL(etmidr4, 24, 27);
> > /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 60bc2fb5159b..be8b32ea1654 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -175,6 +175,7 @@
> > ETM_MODE_EXCL_USER)
> >
> > #define TRCSTATR_IDLE_BIT 0
> > +#define TRCSTATR_PMSTABLE_BIT 1
> > #define ETM_DEFAULT_ADDR_COMP 0
> >
> > /* PowerDown Control Register bits */
> > @@ -226,6 +227,7 @@
> > * @cntr_val: Sets or returns the value for a counter.
> > * @res_idx: Resource index selector.
> > * @res_ctrl: Controls the selection of the resources in the trace unit.
> > + * @ss_idx: Single-shot index selector.
> > * @ss_ctrl: Controls the corresponding single-shot comparator resource.
> > * @ss_status: The status of the corresponding single-shot comparator.
> > * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
> > @@ -269,6 +271,7 @@ struct etmv4_config {
> > u32 cntr_val[ETMv4_MAX_CNTR];
> > u8 res_idx;
> > u32 res_ctrl[ETM_MAX_RES_SEL];
> > + u8 ss_idx;
> > u32 ss_ctrl[ETM_MAX_SS_CMP];
> > u32 ss_status[ETM_MAX_SS_CMP];
> > u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> > --
> > 2.17.1
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v3 0/3] arm64: meson-sm1: add support for the SM1 based VIM3L
From: Neil Armstrong @ 2019-08-28 14:18 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
This patchset adds support for the Amlogic SM1 based Khadas VIM3L variant.
The S903D3 package variant of SM1 is pin-to-pin compatible with the
S922X and A311d, so only internal DT changes are needed :
- DVFS support is different
- Audio support not yet available for SM1
This patchset moved all the non-g12b nodes to meson-khadas-vim3.dtsi
and add the sm1 specific nodes into meson-sm1-khadas-vim3l.dts.
Display has a color conversion bug on SM1 by using a more recent vendor
bootloader on the SM1 based VIM3, this is out of scope of this patchset
and will be fixed in the drm/meson driver.
Dependencies:
- patch 1,2: None
- patch 3: Depends on the "arm64: meson-sm1: add support for DVFS" patchset at [1]
Changes since v2:
- fixed patch 2 subject
Changes since v1:
- renamed compatible to khadas,vim3l
- renamed DT file to meson-sm1-khadas-vim3l.dts
[1] https://patchwork.kernel.org/cover/11109411/
Neil Armstrong (3):
arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
.../devicetree/bindings/arm/amlogic.yaml | 3 +-
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../amlogic/meson-g12b-a311d-khadas-vim3.dts | 1 +
.../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 355 -----------------
.../amlogic/meson-g12b-s922x-khadas-vim3.dts | 1 +
.../boot/dts/amlogic/meson-khadas-vim3.dtsi | 360 ++++++++++++++++++
.../dts/amlogic/meson-sm1-khadas-vim3l.dts | 70 ++++
7 files changed, 435 insertions(+), 356 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
--
2.22.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v3 2/3] dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
From: Neil Armstrong @ 2019-08-28 14:18 UTC (permalink / raw)
To: khilman, devicetree
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141816.16328-1-narmstrong@baylibre.com>
The Khadas VIM3 is also available as VIM3L with the Pin-to-pin compatible
Amlogic SM1 SoC in the S905D3 variant package.
Change the description to match the S905X3/D3/Y3 variants like the G12A
description, and add the khadas,vim3l compatible.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index b48ea1e4913a..99015cef8bb1 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -150,9 +150,10 @@ properties:
- const: amlogic,s922x
- const: amlogic,g12b
- - description: Boards with the Amlogic Meson SM1 S905X3 SoC
+ - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
- seirobotics,sei610
+ - khadas,vim3l
- const: amlogic,sm1
...
--
2.22.0
_______________________________________________
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^ permalink raw reply related
* [PATCH v3 1/3] arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
From: Neil Armstrong @ 2019-08-28 14:18 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141816.16328-1-narmstrong@baylibre.com>
To prepare support of the Amlogic SM1 based Khadas VIM3, move the non-G12B
specific nodes (all except DVFS and Audio) to a new meson-khadas-vim3.dtsi
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../amlogic/meson-g12b-a311d-khadas-vim3.dts | 1 +
.../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 355 -----------------
.../amlogic/meson-g12b-s922x-khadas-vim3.dts | 1 +
.../boot/dts/amlogic/meson-khadas-vim3.dtsi | 360 ++++++++++++++++++
4 files changed, 362 insertions(+), 355 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
index 73128ed24361..3a6a1e0c1e32 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "meson-g12b-a311d.dtsi"
+#include "meson-khadas-vim3.dtsi"
#include "meson-g12b-khadas-vim3.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
index 9c3ca2edc725..554863429aa6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
@@ -5,116 +5,9 @@
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
*/
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
- model = "Khadas VIM3";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- white {
- label = "vim3:white:sys";
- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- red {
- label = "vim3:red";
- gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
vddcpu_a: regulator-vddcpu-a {
/*
* MP8756GD Regulator.
@@ -153,62 +46,6 @@
regulator-always-on;
};
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vsys_3v3: regulator-vsys_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VSYS_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb_pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-KHADAS-VIM3";
@@ -269,20 +106,6 @@
status = "okay";
};
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
&clkc_audio {
status = "okay";
};
@@ -329,31 +152,6 @@
clock-latency = <50000>;
};
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
&frddr_b {
status = "okay";
};
@@ -362,46 +160,6 @@
status = "okay";
};
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
- pinctrl-names = "default";
-
- gpio_expander: gpio-controller@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- vcc-supply = <&vcc_3v3>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-khadas";
-};
-
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
@@ -418,81 +176,6 @@
status = "okay";
};
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vsys_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
&tdmif_b {
status = "okay";
};
@@ -504,41 +187,3 @@
&tohdmitx {
status = "okay";
};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb_pwr>;
-};
-
-&usb3_pcie_phy {
- phy-supply = <&usb_pwr>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
-};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
index 6bcf972b8bfa..b73deb282120 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "meson-g12b-s922x.dtsi"
+#include "meson-khadas-vim3.dtsi"
#include "meson-g12b-khadas-vim3.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
new file mode 100644
index 000000000000..8647da7d6609
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ model = "Khadas VIM3";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Function";
+ linux,code = <KEY_FN>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ white {
+ label = "vim3:white:sys";
+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ red {
+ label = "vim3:red";
+ gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vsys_3v3: regulator-vsys_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSYS_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+ pinctrl-names = "default";
+
+ gpio_expander: gpio-controller@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ vcc-supply = <&vcc_3v3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+ linux,rc-map-name = "rc-khadas";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vsys_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+};
--
2.22.0
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* [PATCH v3 3/3] arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
From: Neil Armstrong @ 2019-08-28 14:18 UTC (permalink / raw)
To: khilman; +Cc: linux-amlogic, linux-kernel, linux-arm-kernel, Neil Armstrong
In-Reply-To: <20190828141816.16328-1-narmstrong@baylibre.com>
Add the Amlogic SM1 based Khadas VIM3L, sharing all the same features
as the G12B based VIM3, but:
- a different DVFS support since only a single cluster is available
- audio is still not available on SM1
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../dts/amlogic/meson-sm1-khadas-vim3l.dts | 70 +++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index edbf128e7707..84afecba9ec0 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
new file mode 100644
index 000000000000..5233bd7cacfb
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include "meson-khadas-vim3.dtsi"
+
+/ {
+ compatible = "khadas,vim3l", "amlogic,sm1";
+ model = "Khadas VIM3L";
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * Silergy SY8030DEC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&vsys_3v3>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
--
2.22.0
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* Re: [PATCH 8/8] coresight: etm4x: docs: Additional documentation for ETM4x.
From: Mike Leach @ 2019-08-28 14:20 UTC (permalink / raw)
To: Mathieu Poirier; +Cc: Coresight ML, linux-arm-kernel, Suzuki K. Poulose
In-Reply-To: <20190827223438.GA20203@xps15>
Hi Mathieu,
I assume you want the split to be ? :-
1. the update in Documentation/ARM/testing/sysfs-bus-coresight-devices-etm4x
2. the moving of coresight docs to their new common directory.
3. the addition of the new etm4x doc
On Tue, 27 Aug 2019 at 23:34, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote:
> > Update existing docs for new sysfs API features.
> > Add new ETMv4 reference document for sysfs programming.
> > Move coresight documentation to common directory.
> >
>
> I also get the following warnings when adding the patch:
>
> $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch
> Applying: coresight: etm4x: docs: Additional documentation for ETM4x.
> .git/rebase-apply/patch:620: space before tab in indent.
> bitfield up to 32 bits setting trace features.
> .git/rebase-apply/patch:950: space before tab in indent.
> ; range comparator
> .git/rebase-apply/patch:954: space before tab in indent.
> ; address comparator
> .git/rebase-apply/patch:1057: new blank line at EOF.
> +
> warning: 4 lines add whitespace errors.
>
OK - I'll re-look at this, but don't recall seeing any errors myself
& al cleared by checkpatch.
Regards
Mike
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> > .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++---
> > .../{ => coresight}/coresight-cpu-debug.txt | 0
> > .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++
> > .../trace/{ => coresight}/coresight.txt | 0
> > MAINTAINERS | 3 +-
> > 5 files changed, 575 insertions(+), 70 deletions(-)
> > rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%)
> > create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt
> > rename Documentation/trace/{ => coresight}/coresight.txt (100%)
> >
> > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > index 36258bc1b473..112c50ae9986 100644
> > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> > @@ -1,4 +1,4 @@
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
> > +What: /sys/bus/coresight/devices/etm<N>/enable_source
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry.
> > of coresight components linking the source to the sink is
> > configured and managed automatically by the coresight framework.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
> > +What: /sys/bus/coresight/devices/etm<N>/cpu
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) The CPU this tracing entity is associated with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp
> > +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of PE comparator inputs that are
> > available for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp
> > +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of address comparator pairs that are
> > available for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr
> > +What: /sys/bus/coresight/devices/etm<N>/nr_cntr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of counters that are available for
> > tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp
> > +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates how many external inputs are implemented.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc
> > +What: /sys/bus/coresight/devices/etm<N>/numcidc
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of Context ID comparators that are
> > available for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc
> > +What: /sys/bus/coresight/devices/etm<N>/numvmidc
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of VMID comparators that are available
> > for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate
> > +What: /sys/bus/coresight/devices/etm<N>/nrseqstate
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of sequencer states that are
> > implemented.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource
> > +What: /sys/bus/coresight/devices/etm<N>/nr_resource
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of resource selection pairs that are
> > available for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp
> > +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Indicates the number of single-shot comparator controls that
> > are available for tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/reset
> > +What: /sys/bus/coresight/devices/etm<N>/reset
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (W) Cancels all configuration on a trace unit and set it back
> > to its boot configuration.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mode
> > +What: /sys/bus/coresight/devices/etm<N>/mode
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example
> > P0 instruction tracing, branch broadcast, cycle counting and
> > context ID tracing.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/pe
> > +What: /sys/bus/coresight/devices/etm<N>/pe
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls which PE to trace.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/event
> > +What: /sys/bus/coresight/devices/etm<N>/event
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
> > +What: /sys/bus/coresight/devices/etm<N>/event_instren
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls the behavior of the events in bank 0 to 3.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts
> > +What: /sys/bus/coresight/devices/etm<N>/event_ts
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls the insertion of global timestamps in the trace
> > streams.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq
> > +What: /sys/bus/coresight/devices/etm<N>/syncfreq
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls how often trace synchronization requests occur.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold
> > +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Sets the threshold value for cycle counting.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl
> > +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls which regions in the memory map are enabled to
> > use branch broadcasting.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst
> > +What: /sys/bus/coresight/devices/etm<N>/event_vinst
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls instruction trace filtering.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst
> > +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) In Secure state, each bit controls whether instruction
> > tracing is enabled for the corresponding exception level.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst
> > +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) In non-secure state, each bit controls whether instruction
> > tracing is enabled for the corresponding exception level.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx
> > +What: /sys/bus/coresight/devices/etm<N>/addr_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which address comparator or pair (of comparators) to
> > work with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype
> > +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls what type of comparison the trace unit performs.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single
> > +What: /sys/bus/coresight/devices/etm<N>/addr_single
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Used to setup single address comparator values.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range
> > +What: /sys/bus/coresight/devices/etm<N>/addr_range
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Used to setup address range comparator values.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx
> > +What: /sys/bus/coresight/devices/etm<N>/seq_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which sequensor.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state
> > +What: /sys/bus/coresight/devices/etm<N>/seq_state
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Use this to set, or read, the sequencer state.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event
> > +What: /sys/bus/coresight/devices/etm<N>/seq_event
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Moves the sequencer state to a specific state.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event
> > +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Moves the sequencer to state 0 when a programmed event
> > occurs.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx
> > +What: /sys/bus/coresight/devices/etm<N>/cntr_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which counter unit to work with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr
> > +What: /sys/bus/coresight/devices/etm<N>/cntrldvr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) This sets or returns the reload count value of the
> > specific counter.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val
> > +What: /sys/bus/coresight/devices/etm<N>/cntr_val
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) This sets or returns the current count value of the
> > specific counter.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl
> > +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls the operation of the selected counter.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx
> > +What: /sys/bus/coresight/devices/etm<N>/res_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which resource selection unit to work with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl
> > +What: /sys/bus/coresight/devices/etm<N>/res_ctrl
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Controls the selection of the resources in the trace unit.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx
> > +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which context ID comparator to work with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid
> > +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Get/Set the context ID comparator value to trigger on.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks
> > +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Mask for all 8 context ID comparator value
> > registers (if implemented).
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx
> > +What: /sys/bus/coresight/devices/etm<N>/vmid_idx
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Select which virtual machine ID comparator to work with.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val
> > +What: /sys/bus/coresight/devices/etm<N>/vmid_val
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Get/Set the virtual machine ID comparator value to
> > trigger on.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks
> > +What: /sys/bus/coresight/devices/etm<N>/vmid_masks
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (RW) Mask for all 8 virtual machine ID comparator value
> > registers (if implemented).
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr
> > +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Set the Exception Level matching bits for secure and
> > + non-secure exception levels.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the start stop control register for PE input
> > + comparators.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (R) Print the current settings for the selected address
> > + comparator.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/sshot_idx
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Select the single shot control register to access.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the selected single shot control register.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/sshot_status
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (R) Print the current value of the selected single shot
> > + status register.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
> > +Date: August 2019
> > +KernelVersion: 5.4
> > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > +Description: (RW) Access the selected single show PE comparator control
> > + register.
> > +
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the OS Lock Status Register (0x304).
> > The value it taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Power Down Control Register
> > (0x310). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Power Down Status Register
> > (0x314). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the SW Lock Status Register
> > (0xFB4). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Authentication Status Register
> > (0xFB8). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Device ID Register
> > (0xFC8). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Device Type Register
> > (0xFCC). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Peripheral ID0 Register
> > (0xFE0). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Peripheral ID1 Register
> > (0xFE4). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Peripheral ID2 Register
> > (0xFE8). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the Peripheral ID3 Register
> > (0xFEC). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
> > Date: February 2016
> > KernelVersion: 4.07
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the trace configuration register
> > (0x010) as currently set by SW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
> > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
> > Date: February 2016
> > KernelVersion: 4.07
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Print the content of the trace ID register (0x040).
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E0).
> > The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E4).
> > The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address,
> > VMID, context ID and instuction address in the trace unit
> > (0x1E8). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources
> > architecture specification for more details (0x1E8).
> > The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns how many resources the trace unit supports (0x1F0).
> > The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns how many resources the trace unit supports (0x1F4).
> > The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns the maximum speculation depth of the instruction
> > trace stream. (0x180). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns the number of P0 right-hand keys that the trace unit
> > can use (0x184). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Description: (R) Returns the number of P1 right-hand keys that the trace unit
> > can use (0x188). The value is taken directly from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the
> > trace unit can use (0x18C). The value is taken directly from
> > the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that
> > the trace unit can use (0x190). The value is taken directly
> > from the HW.
> >
> > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
> > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
> > Date: April 2015
> > KernelVersion: 4.01
> > Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
> > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt
> > similarity index 100%
> > rename from Documentation/trace/coresight-cpu-debug.txt
> > rename to Documentation/trace/coresight/coresight-cpu-debug.txt
> > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > new file mode 100644
> > index 000000000000..72e81bbbef43
> > --- /dev/null
> > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt
> > @@ -0,0 +1,459 @@
> > +ETMv4 sysfs linux driver programming reference - v2.
> > +====================================================
> > +
> > +Supplement to existing ETMv4 driver documentation.
> > +
> > +Sysfs files and directories
> > +---------------------------
> > +
> > +Root: /sys/bus/coresight/devices/etm<N>
> > +
> > +
> > +The following paragraphs explain the association between sysfs files and the
> > +ETMv4 registers that they effect. Note the register names are given without
> > +the ‘TRC’ prefix.
> > +
> > +File : mode (rw)
> > +Trace Registers : {CONFIGR + others}
> > +Notes : Bit select trace features. See ‘mode’ section below. Bits
> > + in this will cause equivalent programming of trace config and
> > + other registers to enable the features requested.
> > +Syntax & eg : 'echo bitfield > mode'
> > + bitfield up to 32 bits setting trace features.
> > +Example : $> echo 0x > mode
> > +
> > +File : reset (wo)
> > +Trace Registers : All
> > +Notes : Reset all programming to trace nothing / no logic programmed.
> > +Syntax : 'echo 1 > reset'
> > +
> > +File : enable_source (wo)
> > +Trace Registers : PRGCTLR, All hardware regs.
> > +Notes : >0: Programs up the hardware with the current values held in
> > + the driver and enables trace.
> > + 0: disable trace hardware.
> > +Syntax : 'echo 1 > enable_source'
> > +
> > +File : cpu (ro)
> > +Trace Registers : None.
> > +Notes : CPU ID that this ETM is attached to.
> > +Example :$> cat cpu
> > + $> 0
> > +
> > +File : addr_idx (rw)
> > +Trace Registers : None.
> > +Notes : Virtual register to index address comparator and range
> > + features. Set index for first of the pair in a range.
> > +Syntax : 'echo idx > addr_idx'
> > + Where idx < nr_addr_cmp x 2
> > +
> > +File : addr_range (rw)
> > +Trace Registers : ACVR[idx, idx+1], VIIECTLR
> > +Notes : Pair of addresses for a range selected by addr_idx. Include
> > + / exclude according to the optional parameter, or if omitted
> > + uses the current ‘mode’ setting. Select comparator range in
> > + control register. Error if index is odd value.
> > +Depends : mode, addr_idx
> > +Syntax : 'echo addr1 addr2 [exclude] > addr_range'
> > + Where addr1 and addr2 define the range and addr1 < addr2.
> > + Optional exclude value - 0 for include, 1 for exclude.
> > +Example : $> echo 0x0000 0x2000 0 > addr_range
> > +
> > +File : addr_single (rw)
> > +Trace Registers : ACVR[idx]
> > +Notes : Set a single address comparator according to addr_idx. This
> > + is used if the address comparator is used as part of event
> > + generation logic etc.
> > +Depends : addr_idx
> > +Syntax : 'echo addr1 > addr_single'
> > +
> > +File : addr_start (rw)
> > +Trace Registers : ACVR[idx], VISSCTLR
> > +Notes : Set a trace start address comparator according to addr_idx.
> > + Select comparator in control register.
> > +Depends : addr_idx
> > +Syntax : 'echo addr1 > addr_start'
> > +
> > +File : addr_stop (rw)
> > +Trace Registers : ACVR[idx], VISSCTLR
> > +Notes : Set a trace stop address comparator according to addr_idx.
> > + Select comparator in control register.
> > +Depends : addr_idx
> > +Syntax : 'echo addr1 > addr_stop'
> > +
> > +File : addr_context (rw)
> > +Trace Registers : ACATR[idx,{6:4}]
> > +Notes : Link context ID comparator to address comparator addr_idx
> > +Depends : addr_idx.
> > +Syntax : 'echo ctxt_idx > addr_context'
> > + Where ctxt_idx is the index of the linked context id / vmid
> > + comparator.
> > +
> > +File : addr_ctxtype (rw)
> > +Trace Registers : ACATR[idx,{3:2}]
> > +Notes : Input value string. Set type for linked context ID comparator
> > +Depends : addr_idx
> > +Syntax : 'echo type > addr_ctxtype'
> > + Type one of {all, vmid, ctxid, none}
> > +Example : $> echo ctxid > addr_ctxtype
> > +
> > +File : addr_exlevel_s_ns (rw)
> > +Trace Registers : ACATR[idx,{14:8}]
> > +Notes : Set the ELx secure and non-secure matching bits for the
> > + selected address comparator
> > +Depends : addr_idx
> > +Syntax : 'echo val > addr_exlevel_s_ns'
> > + val is a 7 bit value for exception levels to exclude. Input
> > + value shifted to correct bits in register.
> > +Example : $> echo 0x4F > addr_exlevel_s_ns
> > +
> > +File : addr_instdatatype (rw)
> > +Trace Registers : ACATR[idx,{1:0}]
> > +Notes : Set the comparator address type for matching. Driver only
> > + supports setting instruction address type.
> > +Depends : addr_idx
> > +
> > +File : addr_cmp_view (ro)
> > +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR
> > +Notes : Read the currently selected address comparator. If part of
> > + address range then display both addresses.
> > +Depends : addr_idx
> > +Syntax : 'cat addr_cmp_view'
> > +Example : $> cat addr_cmp_view
> > + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)
> > +
> > +File : nr_addr_cmp (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of address comparator pairs
> > +
> > +File : sshot_idx (rw)
> > +Trace Registers : None
> > +Notes : Select single shot register set.
> > +
> > +File : sshot_ctrl (rw)
> > +Trace Registers : SSCCR[idx]
> > +Notes : Access a single shot comparator control register.
> > +Depends : sshot_idx
> > +Syntax : 'echo val > sshot_ctrl'
> > + Writes val into the selected control register.
> > +
> > +File : sshot_status (ro)
> > +Trace Registers : SSCSR[idx]
> > +Notes : Read a single shot comparator status register
> > +Depends : sshot_idx
> > +Syntax : 'cat sshot_status'
> > + Read status.
> > +Example : $> cat sshot_status
> > + 0x1
> > +
> > +File : sshot_pe_ctrl (rw)
> > +Trace Registers : SSPCICR[idx]
> > +Notes : Access a single shot PE comparator input control register.
> > +Depends : sshot_idx
> > +Syntax : echo val > sshot_pe_ctrl
> > + Writes val into the selected control register.
> > +
> > +File : ns_exlevel_vinst (rw)
> > +Trace Registers : VICTLR{23:20}
> > +Notes : Program non-secure exception level filters. Set / clear NS
> > + exception filter bits. Setting ‘1’ excludes trace from the
> > + exception level.
> > +Syntax : 'echo bitfield > ns_exlevel_viinst'
> > + Where bitfield contains bits to set clear for EL0 to EL2
> > +Example : %> echo 0x4 > ns_exlevel_viinst
> > + ; Exclude EL2 NS trace.
> > +
> > +File : vinst_pe_cmp_start_stop (rw)
> > +Trace Registers : VIPCSSCTLR
> > +Notes : Access PE start stop comparator input control registers
> > +
> > +File : bb_ctrl (rw)
> > +Trace Registers : BBCTLR
> > +Notes : Define ranges that Branch Broadcast will operate in.
> > + Default (0x0) is all addresses.
> > +Depends : BB enabled.
> > +
> > +File : cyc_threshold (rw)
> > +Trace Registers : CCCTLR
> > +Notes : Set the threshold for which cycle counts will be emitted.
> > + Error if attempt to set below minimum defined in IDR3, masked
> > + to width of valid bits.
> > +Depends : CC enabled.
> > +
> > +File : syncfreq (rw)
> > +Trace Registers : SYNCPR
> > +Notes : Set trace synchronisation period. Power of 2 value, 0 (off)
> > + or 8-20. Driver defaults to 12 (every 4096 bytes).
> > +
> > +File : cntr_idx (rw)
> > +Trace Registers : none
> > +Notes : Select the counter to access
> > +Syntax : 'echo idx > cntr_idx'
> > + Where idx < nr_cntr
> > +
> > +File : cntr_ctrl (rw)
> > +Trace Registers : CNTCTLR[idx]
> > +Notes : Set counter control value
> > +Depends : cntr_idx
> > +Syntax : 'echo val > cntr_ctrl'
> > + Where val is per ETMv4 spec.
> > +
> > +File : cntrldvr (rw)
> > +Trace Registers : CNTRLDVR[idx]
> > +Notes : Set counter reload value
> > +Depends : cntr_idx
> > +Syntax : 'echo val > cntrldvr'
> > + Where val is per ETMv4 spec.
> > +
> > +File : nr_cntr (ro)
> > +Trace Registers : From IDR5
> > +Notes : Number of counters implemented.
> > +
> > +File : ctxid_idx (rw)
> > +Trace Registers : None
> > +Notes : Select the context ID comparator to access
> > +Syntax : 'echo idx > ctxid_idx'
> > + Where idx < numcidc
> > +
> > +File : ctxid_pid (rw)
> > +Trace Registers : CIDCVR[idx]
> > +Notes : Set the context ID comparator value
> > +Depends : ctxid_idx
> > +
> > +File : ctxid_masks (rw)
> > +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
> > +Notes : Pair of values to set the byte masks for 1-8 context ID
> > + comparators. Automatically clears masked bytes to 0 in CID
> > + value registers.
> > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks'
> > + 32 bit values made up of mask bytes, where mN represents a
> > + byte mask value for Ctxt ID comparator N.
> > + Second value not required on systems that have fewer than 4
> > + context ID comparators
> > +
> > +File : numcidc (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of Context ID comparators
> > +
> > +File : vmid_idx (rw)
> > +Trace Registers : None
> > +Notes : Select the VM ID comparator to access.
> > +Syntax : 'echo idx > vmid_idx'
> > + Where idx < numvmidc
> > +
> > +File : vmid_val (rw)
> > +Trace Registers : VMIDCVR[idx]
> > +Notes : Set the VM ID comparator value
> > +Depends : vmid_idx
> > +
> > +File : vmid_masks (rw)
> > +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
> > +Notes : Pair of values to set the byte masks for 1-8 VM ID
> > + comparators. Automatically clears masked bytes to 0 in VMID
> > + value registers.
> > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks'
> > + Where mN represents a byte mask value for VMID comparator N.
> > + Second value not required on systems that have fewer than
> > + 4 VMID comparators.
> > +
> > +File : numvmidc (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of VMID comparators
> > +
> > +File : res_idx (rw)
> > +Trace Registers : None.
> > +Notes : Select the resource selector control to access. Must be 2 or
> > + higher as selectors 0 and 1 are hardwired.
> > +Syntax : 'echo idx > res_idx'
> > + Where 2 <= idx < nr_resource x 2
> > +
> > +File : res_ctrl (rw)
> > +Trace Registers : RSCTLR[idx]
> > +Notes : Set resource selector control value. Value per ETMv4 spec.
> > +Depends : res_idx
> > +Syntax : 'echo val > res_cntr'
> > + Where val is per ETMv4 spec.
> > +
> > +File : nr_resource (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of resource selector pairs
> > +
> > +File : event (rw)
> > +Trace Registers : EVENTCTRL0R
> > +Notes : Set up to 4 implemented event fields.
> > +Syntax : 'echo ev3ev2ev1ev0 > event'
> > + Where evN is an 8 bit event field. Up to 4 event fields make up
> > + the 32bit input value. Number of valid fields implementation
> > + dependent defined in IDR0.
> > +
> > +File : event_instren (rw)
> > +Trace Registers : EVENTCTRL1R
> > +Notes : Choose events which insert event packets into trace stream.
> > +Depends : EVENTCTRL0R
> > +Syntax : 'echo bitfield > event_instren'
> > + Where bitfield is up to 4 bits according to number of event
> > + fields.
> > +
> > +File : event_ts (rw)
> > +Trace Registers : TSCTLR
> > +Notes : Set the event that will generate timestamp requests.
> > +Depends : TS activated
> > +Syntax : 'echo evfield > event_ts'
> > + Where evfield is an 8 bit event selector.
> > +
> > +File : seq_idx (rw)
> > +Trace Registers : None
> > +Notes : Sequencer event register select - 0 to 2
> > +
> > +
> > +File : seq_state (rw)
> > +Trace Registers : SEQSTR
> > +Notes : Sequencer current state - 0 to 3.
> > +
> > +File : seq_event (rw)
> > +Trace Registers : SEQEVR[idx]
> > +Notes : State transition event registers
> > +Depends : seq_idx
> > +Syntax : 'echo evBevF > seq_event'
> > + Where evBevF is a 16 bit value made up of two event selectors,
> > + evB - back, evF - forwards.
> > +
> > +File : seq_reset_event (rw)
> > +Trace Registers : SEQRSTEVR
> > +Notes : Sequencer reset event
> > +Syntax : 'echo evfield > seq_reset_event'
> > + Where evfield is an 8 bit event selector.
> > +
> > +File : nrseqstate (ro)
> > +Trace Registers : From IDR5
> > +Notes : Number of sequencer states (0 or 4)
> > +
> > +File : nr_pe_cmp (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of PE comparator inputs
> > +
> > +File : nr_ext_inp (ro)
> > +Trace Registers : From IDR5
> > +Notes : Number of external inputs
> > +
> > +File : nr_ss_cmp (ro)
> > +Trace Registers : From IDR4
> > +Notes : Number of Single Shot control registers
> > +
> > +Note: When programming any address comparator the driver will tag the
> > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag
> > +is set, then only the values can be changed using the same sysfs file / type
> > +used to program it.
> > +
> > +Thus:-
> > +% echo 0 > addr_idx ; select address comparator 0
> > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1.
> > +% echo 0x2000 > addr_start ; this will error as comparator 0 is a
> > + ; range comparator
> > +% echo 2 > addr_idx ; select address comparator 2
> > +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused,
> > +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start
> > + ; address comparator
> > +% echo 2 > addr_idx ; select address comparator 3
> > +% echo 0x3000 > addr_stop ; this is OK
> > +
> > +To remove programming on all the comparators (and all the other hardware) use
> > +the reset parameter:
> > +
> > +% echo 1 > reset
> > +
> > +The ‘mode’ sysfs parameter.
> > +---------------------------
> > +
> > +This is a bitfield selection parameter that sets the overall trace mode for the
> > +ETM. The table below describes the bits, using the defines from the driver
> > +source file, along with a description of the feature these represent. Many
> > +features are optional and therefore dependent on implementation in the
> > +hardware.
> > +
> > +Bit assignements shown below:-
> > +
> > +bit (0) : #define ETM_MODE_EXCLUDE
> > +description : This is the default value for the include / exclude function when
> > + setting address ranges. Set 1 for exclude range. When the mode
> > + parameter is set this value is applied to the currently indexed
> > + address range.
> > +
> > +bit (4) : #define ETM_MODE_BB
> > +description : Set to enable branch broadcast if supported in hardware [IDR0].
> > +
> > +bit (5) : #define ETMv4_MODE_CYCACC
> > +description : Set to enable cycle accurate trace if supported [IDR0].
> > +
> > +bit (6) : ETMv4_MODE_CTXID
> > +description : Set to enable context ID tracing if supported in hardware [IDR2].
> > +
> > +bit (7) : ETM_MODE_VMID
> > +description : Set to enable virtual machine ID tracing if supported [IDR2].
> > +
> > +bit (11) : ETMv4_MODE_TIMESTAMP
> > +description : Set to enable timestamp generation if supported [IDR0].
> > +
> > +bit (12) : ETM_MODE_RETURNSTACK
> > +description : Set to enable trace return stack use if supported [IDR0].
> > +
> > +bit (13-14) : ETM_MODE_QELEM(val)
> > +description : ‘val’ determines level of Q element support enabled if
> > + implemented by the ETM [IDR0]
> > +
> > +bit (19) : ETM_MODE_ATB_TRIGGER
> > +description : Set to enable the ATBTRIGGER bit in the event control register
> > + [EVENTCTLR1] if supported [IDR5].
> > +
> > +bit (20) : ETM_MODE_LPOVERRIDE
> > +description : Set to enable the LPOVERRIDE bit in the event control register
> > + [EVENTCTLR1], if supported [IDR5].
> > +
> > +bit (21) : ETM_MODE_ISTALL_EN
> > +description : Set to enable the ISTALL bit in the stall control register
> > + [STALLCTLR]
> > +
> > +bit (23) : ETM_MODE_INSTPRIO
> > +description : Set to enable the INSTPRIORITY bit in the stall control register
> > + [STALLCTLR] , if supported [IDR0].
> > +
> > +bit (24) : ETM_MODE_NOOVERFLOW
> > +description : Set to enable the NOOVERFLOW bit in the stall control register
> > + [STALLCTLR], if supported [IDR3].
> > +
> > +bit (25) : ETM_MODE_TRACE_RESET
> > +description : Set to enable the TRCRESET bit in the viewinst control register
> > + [VICTLR] , if supported [IDR3].
> > +
> > +bit (26) : ETM_MODE_TRACE_ERR
> > +description : Set to enable the TRCCTRL bit in the viewinst control register
> > + [VICTLR].
> > +
> > +bit (27) : ETM_MODE_VIEWINST_STARTSTOP
> > +description : Set the initial state value of the ViewInst start / stop logic
> > + in the viewinst control register [VICTLR]
> > +
> > +bit (30) : ETM_MODE_EXCL_KERN
> > +description : Set default trace setup to exclude kernel mode trace (see note a)
> > +
> > +bit (31) : ETM_MODE_EXCL_USER
> > +description : Set default trace setup to exclude user space trace (see note a)
> > +
> > +Note a) On startup the ETM is programmed to trace the complete address space
> > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to
> > +set EL exclude bits for NS state in either user space (EL0) or kernel space
> > +(EL1) in the address range comparator. (the default setting excludes all
> > +secure EL, and NS EL2)
> > +
> > +Once the reset parameter has been used, and/or custom programming has been
> > +implemented - using these bits will result in the EL bits for address
> > +comparator 0 being set in the same way.
> > +
> > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with
> > +data trace. As A profile data trace is architecturally prohibited in ETMv4,
> > +these have been omitted here. Possible uses could be where a kernel has
> > +support for control of R or M profile infrastructure as part of a heterogeneous
> > +system.
> > +
> > +Bits 17, 28-29 are unused.
> > +
> > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt
> > similarity index 100%
> > rename from Documentation/trace/coresight.txt
> > rename to Documentation/trace/coresight/coresight.txt
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 783569e3c4b4..777b77fde29b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com>
> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > S: Maintained
> > F: drivers/hwtracing/coresight/*
> > -F: Documentation/trace/coresight.txt
> > -F: Documentation/trace/coresight-cpu-debug.txt
> > +F: Documentation/trace/coresight/*
> > F: Documentation/devicetree/bindings/arm/coresight.txt
> > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> > --
> > 2.17.1
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [EXT] [PATCH v3 0/2] drm: bridge: Add NWL MIPI DSI host controller support
From: Robert Chiras @ 2019-08-28 14:29 UTC (permalink / raw)
To: dl-linux-imx, narmstrong@baylibre.com, robh+dt@kernel.org,
linux-kernel@vger.kernel.org, lee.jones@linaro.org,
devicetree@vger.kernel.org, agx@sigxcpu.org, festevam@gmail.com,
jernej.skrabec@siol.net, daniel@ffwll.ch, mark.rutland@arm.com,
a.hajda@samsung.com, dri-devel@lists.freedesktop.org,
jonas@kwiboo.se, shawnguo@kernel.org,
linux-arm-kernel@lists.infradead.org, sam@ravnborg.org,
airlied@linux.ie, Laurent.pinchart@ideasonboard.com,
kernel@pengutronix.de, arnd@arndb.de, s.hauer@pengutronix.de
In-Reply-To: <cover.1566470526.git.agx@sigxcpu.org>
Hi Guido,
I tested this on my setup and it works. My DSI panel is a little bit
different and it doesn't work with this as-is, but I added some
improvements on top of this, in order to be able to setup the clocks.
The changes I made can arrive on top of this as improvements, of
course, since it will allow this driver to dinamically set the
video_pll clock for any kind of mode.
So, for the whole patch-set, you can add:
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Best regards,
Robert
On Jo, 2019-08-22 at 12:44 +0200, Guido Günther wrote:
> This adds initial support for the NWL MIPI DSI Host controller found
> on i.MX8
> SoCs.
>
> It adds support for the i.MX8MQ but the same IP core can also be
> found on e.g.
> i.MX8QXP. I added the necessary hooks to support other imx8 variants
> but since
> I only have imx8mq boards to test I omitted the platform data for
> other SoCs.
>
> The code is based on NXPs BSP so I added Robert Chiras as
> Co-authored-by. Robert, if this looks sane could you add your
> Signed-off-by:?
>
> The most notable changes over the BSP driver are
> - Calculate HS mode timing from phy_configure_opts_mipi_dphy
> - Perform all clock setup via DT
> - Merge nwl-imx and nwl drivers
> - Add B0 silion revision quirk
> - become a bridge driver to hook into mxsfb (from what I read[0]
> DCSS, which
> also can drive the nwl on the imx8mq will likely not become part
> of
> imx-display-subsystem so it makes sense to make it drive a bridge
> for dsi as
> well).
> - Use panel_bridge to attach the panel
> - Use multiplex framework instead of accessing syscon directly
>
> This has been tested on a Librem 5 devkit using mxsfb with Robert's
> patches[1]
> and the rocktech-jh057n00900 panel driver on next-20190821. The DCSS
> can later
> on also act as input source too.
>
> Changes from v2:
> - Per review comments by Rob Herring
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> August%2F230448.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C757
> 201f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C0%7C637020674654566414&sdata=JdvAdCPGq2CTsW%2BgXgnAVltWMIfdCDQn
> dXSLYpnjEH8%3D&reserved=0
> - bindings:
> - Simplify by restricting to fsl,imx8mq-nwl-dsi
> - document reset lines
> - add port@{0,1}
> - use a real compatible string for the panel
> - resets are required
> - Per review comments by Arnd Bergmann
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> August%2F230868.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C757
> 201f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C0%7C637020674654566414&sdata=LyJpZjQjMCe5zUdvK8CD8ETucLPxx621gW
> xtpAr8DM4%3D&reserved=0
> - Don't access iomuxc_gpr regs directly. This allows us to drop the
> first patch in the series with the iomuxc_gpr field defines.
> - Per review comments by Laurent Pinchart
> - Fix wording in bindings
> - Add mux-controls to bindings
> - Don't print error message on dphy probe deferal
>
> Changes from v1:
> - Per review comments by Sam Ravnborg
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> July%2F228130.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C75720
> 1f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637020674654566414&sdata=AU2gzIwrbCdIBZenPWWYYX%2BgdX53zc2%2B
> SQhZbuN%2FWpU%3D&reserved=0
> - Change binding docs to YAML
> - build: Don't always visit imx-nwl/
> - build: Add header-test-y
> - Sort headers according to DRM convention
> - Use drm_display_mode instead of videmode
> - Per review comments by Fabio Estevam
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> July%2F228299.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C75720
> 1f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637020674654566414&sdata=6kpIZ6iNAQ13fMXU6sqENLwy%2FdIWL6ef8j
> gyas7I0CQ%3D&reserved=0
> - Don't restrict build to ARCH_MXC
> - Drop unused includes
> - Drop unreachable code in imx_nwl_dsi_bridge_mode_fixup()
> - Drop remaining calls of dev_err() and use DRM_DEV_ERR()
> consistently.
> - Use devm_platform_ioremap_resource()
> - Drop devm_free_irq() in probe() error path
> - Use single line comments where sufficient
> - Use <linux/time64.h> instead of defining USEC_PER_SEC
> - Make input source select imx8 specific
> - Drop <asm/unaligned.h> inclusion (after removal of
> get_unaligned_le32)
> - Drop all EXPORT_SYMBOL_GPL() for functions used in the same
> module
> but different source files.
> - Drop nwl_dsi_enable_{rx,tx}_clock() by invoking
> clk_prepare_enable()
> directly
> - Remove pointless comment
> - Laurent Pinchart
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> July%2F228313.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C75720
> 1f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637020674654566414&sdata=tDlVGeET1CPMH9W%2FqmnePNR51vNaTKD%2F
> iFOoR9%2FmESc%3D&reserved=0
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> ists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> July%2F228308.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C75720
> 1f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637020674654566414&sdata=NsLGAL8%2BcOC0ZZxxeoGe7VxQCgqSBEN4G3
> WVGOeZpCo%3D&reserved=0
> - Drop (on iMX8MQ) unused csr regmap
> - Use NWL_MAX_PLATFORM_CLOCKS everywhere
> - Drop get_unaligned_le32() usage
> - remove duplicate 'for the' in binding docs
> - Don't include unused <linux/clk-provider.h>
> - Don't include unused <linux/component.h>
> - Drop dpms_mode for tracking state, trust the drm layer on that
> - Use pm_runtime_put() instead of pm_runtime_put_sync()
> - Don't overwrite encoder type
> - Make imx_nwl_platform_data const
> - Use the reset controller API instead of open coding that platform
> specific
> part
> - Use <linux/bitfield.h> intead of making up our own defines
> - name mipi_dsi_transfer less generic: nwl_dsi_transfer
> - ensure clean in .remove by calling mipi_dsi_host_unregister.
> - prefix constants by NWL_DSI_
> - properly format transfer_direction enum
> - simplify platform clock handling
> - Don't modify state in mode_fixup() and use mode_set() instead
> - Drop bridge detach(), already handle by nwl_dsi_host_detach()
> - Drop USE_*_QUIRK() macros
> - Drop (for now) unused clock defnitions. 'pixel' and 'bypass' clock
> will be
> used for i.MX8 SoCs but since they're unused atm drop the
> definitions - but
> keep the logic to enable/disable several clocks in place since we
> know we'll
> need it in the future.
>
> Changes from v0:
> - Add quirk for IMQ8MQ silicon B0 revision to not mess with the
> system reset controller on power down since enable() won't work
> otherwise.
> - Drop devm_free_irq() handled by the device driver core
> - Disable tx esc clock after the phy power down to unbreak
> disable/enable (unblank/blank)
> - Add ports to dt binding docs
> - Select GENERIC_PHY_MIPI_DPHY instead of GENERIC_PHY for
> phy_mipi_dphy_get_default_config
> - Select DRM_MIPI_DSI
> - Include drm_print.h to fix build on next-20190408
> - Drop some debugging messages
> - Newline terminate all DRM_ printouts
> - Turn component driver into a drm bridge
>
> [0]: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%
> 2Flists.freedesktop.org%2Farchives%2Fdri-devel%2F2019-
> May%2F219484.html&data=02%7C01%7Crobert.chiras%40nxp.com%7C757201
> f9aaa54653580e08d726edb290%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637020674654566414&sdata=4IVjhLy3a2XxZ4jYwDFD23D%2BvwAVAEj44hY
> fvvp8OpQ%3D&reserved=0
> [1]: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%
> 2Fpatchwork.freedesktop.org%2Fseries%2F62822%2F&data=02%7C01%7Cro
> bert.chiras%40nxp.com%7C757201f9aaa54653580e08d726edb290%7C686ea1d3bc
> 2b4c6fa92cd99c5c301635%7C0%7C0%7C637020674654566414&sdata=GueUBOc
> baGjWtWcMYBplL6ki2UbgaFPkQHg%2F6eReiYg%3D&reserved=0
>
> To: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
> Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>
> , Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.
> de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <
> festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Andrzej
> Hajda <a.hajda@samsung.com>, Neil Armstrong <narmstrong@baylibre.com>
> , Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman
> <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@siol.net>, Lee
> Jones <lee.jones@linaro.org>, Guido Günther <agx@sigxcpu.org>, dri-de
> vel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kern
> el@lists.infradead.org, linux-kernel@vger.kernel.org, Robert Chiras <
> robert.chiras@nxp.com>, Sam Ravnborg <sam@ravnborg.org>, Fabio
> Estevam <festevam@gmail.com>, Arnd Bergmann <arnd@arndb.de>
>
>
> Guido Günther (2):
> dt-bindings: display/bridge: Add binding for NWL mipi dsi host
> controller
> drm/bridge: Add NWL MIPI DSI host controller support
>
> .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/nwl-dsi/Kconfig | 16 +
> drivers/gpu/drm/bridge/nwl-dsi/Makefile | 4 +
> drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c | 501 +++++++++++++
> drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h | 65 ++
> drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c | 700
> ++++++++++++++++++
> drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h | 112 +++
> 9 files changed, 1556 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Kconfig
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/Makefile
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c
> create mode 100644 drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h
>
> --
> 2.20.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [RFC] ARM: omap3: Enable HWMODS for HW Random Number Generator
From: Adam Ford @ 2019-08-28 15:00 UTC (permalink / raw)
To: linux-omap
Cc: Mark Rutland, devicetree, Paul Walmsley, aaro.koskinen,
Tony Lindgren, adam.ford, Russell King, linux-kernel, t-kristo,
Rob Herring, Benoît Cousson, pali.rohar, Adam Ford,
linux-arm-kernel
The datasheet for the AM3517 shows the RNG is connected to L4.
It shows the module address for the RNG is 0x480A0000, and it
matches the omap2.dtsi description. Since the driver can support
omap2 and omap4, it seems reasonable to assume the omap3 would
use the same core for the RNG.
This RFC, mimics much of the omap2 hwmods on the OMAP3. It
also adds the necessary clock for driving the RNG. Unfortunately,
it appears non-functional. If anyone has any suggestions on how
to finish the hwmod (or port it to the newer l4 device tree
format), feedback is requested.
Currently the hwmods repond as follows:
[ 0.245697] omap_hwmod: rng: _wait_target_ready failed: -22
[ 0.245727] omap_hwmod: rng: cannot be enabled for reset (3)
[ 6.780792] omap_hwmod: rng: _wait_target_ready failed: -22
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 945537aee3ca..05891dff7fa1 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -189,7 +189,7 @@
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
- <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&rng_ick>,
<&ssi_ick>;
};
};
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 037529a9e969..82330a66e35c 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -17,6 +17,7 @@
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
#define OMAP3430_ST_AES2_SHIFT 28
+#define OMAP34XX_ST_RNG_SHIFT 2
#define OMAP3430_ST_SHA12_SHIFT 27
#define AM35XX_ST_UART4_SHIFT 23
#define OMAP3430_ST_HDQ_SHIFT 22
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f52438bdfc14..bae4487383b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1627,6 +1627,42 @@ static struct omap_hwmod omap3xxx_gpmc_hwmod = {
.flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
};
+/* RNG */
+
+static struct omap_hwmod_class_sysconfig omap3_rng_sysc = {
+ .rev_offs = 0x3c,
+ .sysc_offs = 0x40,
+ .syss_offs = 0x44,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3_rng_hwmod_class = {
+ .name = "rng",
+ .sysc = &omap3_rng_sysc,
+};
+
+struct omap_hwmod omap3xxx_rng_hwmod = {
+ .name = "rng",
+ .main_clk = "rng_ick",
+ .prcm = {
+ .omap2 = {
+ .module_offs = CORE_MOD,
+ .idlest_reg_id = 4,
+ .idlest_idle_bit = OMAP34XX_ST_RNG_SHIFT,
+ },
+ },
+ /*
+ * XXX The first read from the SYSSTATUS register of the RNG
+ * after the SYSCONFIG SOFTRESET bit is set triggers an
+ * imprecise external abort. It's unclear why this happens.
+ * Until this is analyzed, skip the IP block reset.
+ */
+ .flags = HWMOD_INIT_NO_RESET,
+ .class = &omap3_rng_hwmod_class,
+};
+
/*
* interfaces
*/
@@ -2508,6 +2544,13 @@ static struct omap_hwmod omap3xxx_sham_hwmod = {
.class = &omap3xxx_sham_class,
};
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap3xxx_l4_core__rng = {
+ .master = &omap3xxx_l4_core_hwmod,
+ .slave = &omap3xxx_rng_hwmod,
+ .clk = "rng_ick",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
.master = &omap3xxx_l4_core_hwmod,
@@ -2769,6 +2812,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva,
&omap3xxx_l4_core__ssi,
+ &omap3xxx_l4_core__rng,
NULL,
};
@@ -2788,6 +2832,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
&am35xx_l4_core__mdio,
&am35xx_emac__l3,
&am35xx_l4_core__emac,
+ &omap3xxx_l4_core__rng,
NULL,
};
--
2.17.1
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* [PATCH] PCI: rockchip: Properly handle optional regulators
From: Thierry Reding @ 2019-08-28 15:07 UTC (permalink / raw)
To: Lorenzo Pieralisi, Bjorn Helgaas, Shawn Lin
Cc: Heiko Stuebner, linux-pci, Vidya Sagar, linux-rockchip,
Andrew Murray, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
regulator_get_optional() can fail for a number of reasons besides probe
deferral. It can for example return -ENOMEM if it runs out of memory as
it tries to allocate data structures. Propagating only -EPROBE_DEFER is
problematic because it results in these legitimately fatal errors being
treated as "regulator not specified in DT".
What we really want is to ignore the optional regulators only if they
have not been specified in DT. regulator_get_optional() returns -ENODEV
in this case, so that's the special case that we need to handle. So we
propagate all errors, except -ENODEV, so that real failures will still
cause the driver to fail probe.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/pci/controller/pcie-rockchip-host.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index 8d20f1793a61..ef8e677ce9d1 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -608,29 +608,29 @@ static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
if (IS_ERR(rockchip->vpcie12v)) {
- if (PTR_ERR(rockchip->vpcie12v) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
+ if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
+ return PTR_ERR(rockchip->vpcie12v);
dev_info(dev, "no vpcie12v regulator found\n");
}
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
if (IS_ERR(rockchip->vpcie3v3)) {
- if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
+ if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
+ return PTR_ERR(rockchip->vpcie3v3);
dev_info(dev, "no vpcie3v3 regulator found\n");
}
rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
if (IS_ERR(rockchip->vpcie1v8)) {
- if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
+ if (PTR_ERR(rockchip->vpcie1v8) != -ENODEV)
+ return PTR_ERR(rockchip->vpcie1v8);
dev_info(dev, "no vpcie1v8 regulator found\n");
}
rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
if (IS_ERR(rockchip->vpcie0v9)) {
- if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
+ if (PTR_ERR(rockchip->vpcie0v9) != -ENODEV)
+ return PTR_ERR(rockchip->vpcie0v9);
dev_info(dev, "no vpcie0v9 regulator found\n");
}
--
2.22.0
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