* [PATCH RFC bpf-next 09/10] arm: include: asm: swab: mask rev16 instruction for clang
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
The samples/bpf with clang -emit-llvm reuses linux headers to build
bpf samples, and this w/a only for samples (samples/bpf/Makefile
CLANG-bpf).
It allows to build samples/bpf for arm bpf using clang.
In another way clang -emit-llvm generates errors like:
CLANG-bpf samples/bpf/tc_l2_redirect_kern.o
<inline asm>:1:2: error: invalid register/token name
rev16 r3, r0
This decision is arguable, probably there is another way, but
it doesn't have impact on samples/bpf, so it's easier just ignore
it for clang, at least for now.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
arch/arm/include/asm/swab.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h
index c6051823048b..a9fd9cd33d5e 100644
--- a/arch/arm/include/asm/swab.h
+++ b/arch/arm/include/asm/swab.h
@@ -25,8 +25,11 @@ static inline __attribute_const__ __u32 __arch_swahb32(__u32 x)
__asm__ ("rev16 %0, %1" : "=r" (x) : "r" (x));
return x;
}
+
+#ifndef __clang__
#define __arch_swahb32 __arch_swahb32
#define __arch_swab16(x) ((__u16)__arch_swahb32(x))
+#endif
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
{
--
2.17.1
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* [PATCH RFC bpf-next 08/10] samples: bpf: Makefile: base progs build on Makefile.progs
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
The main reason for that - HOSTCC and CC have different aims.
It was tested for arm cross compilation, based on linaro toolchain,
but should work for others.
In order to split cross compilation with host build, base bpf samples
on Makefile.progs. I've verified it on arm with adding SYSROOT.
It's also convenient when debug is with NFC.
To cross-compile I've used:
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
make -j4 samples/bpf/ SYSROOT="path/to/sysroot"
Sysroot contains correct headers installed ofc.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile | 164 ++++++++++++++++++++++++-----------------
samples/bpf/README.rst | 7 ++
2 files changed, 102 insertions(+), 69 deletions(-)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 043f9cc14cdd..ed7131851172 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -4,55 +4,53 @@ BPF_SAMPLES_PATH ?= $(abspath $(srctree)/$(src))
TOOLS_PATH := $(BPF_SAMPLES_PATH)/../../tools
# List of programs to build
-hostprogs-y := test_lru_dist
-hostprogs-y += sock_example
-hostprogs-y += fds_example
-hostprogs-y += sockex1
-hostprogs-y += sockex2
-hostprogs-y += sockex3
-hostprogs-y += tracex1
-hostprogs-y += tracex2
-hostprogs-y += tracex3
-hostprogs-y += tracex4
-hostprogs-y += tracex5
-hostprogs-y += tracex6
-hostprogs-y += tracex7
-hostprogs-y += test_probe_write_user
-hostprogs-y += trace_output
-hostprogs-y += lathist
-hostprogs-y += offwaketime
-hostprogs-y += spintest
-hostprogs-y += map_perf_test
-hostprogs-y += test_overhead
-hostprogs-y += test_cgrp2_array_pin
-hostprogs-y += test_cgrp2_attach
-hostprogs-y += test_cgrp2_sock
-hostprogs-y += test_cgrp2_sock2
-hostprogs-y += xdp1
-hostprogs-y += xdp2
-hostprogs-y += xdp_router_ipv4
-hostprogs-y += test_current_task_under_cgroup
-hostprogs-y += trace_event
-hostprogs-y += sampleip
-hostprogs-y += tc_l2_redirect
-hostprogs-y += lwt_len_hist
-hostprogs-y += xdp_tx_iptunnel
-hostprogs-y += test_map_in_map
-hostprogs-y += per_socket_stats_example
-hostprogs-y += xdp_redirect
-hostprogs-y += xdp_redirect_map
-hostprogs-y += xdp_redirect_cpu
-hostprogs-y += xdp_monitor
-hostprogs-y += xdp_rxq_info
-hostprogs-y += syscall_tp
-hostprogs-y += cpustat
-hostprogs-y += xdp_adjust_tail
-hostprogs-y += xdpsock
-hostprogs-y += xdp_fwd
-hostprogs-y += task_fd_query
-hostprogs-y += xdp_sample_pkts
-hostprogs-y += ibumad
-hostprogs-y += hbm
+progs-y := test_lru_dist
+progs-y += sock_example
+progs-y += fds_example
+progs-y += sockex1
+progs-y += sockex2
+progs-y += sockex3
+progs-y += tracex1
+progs-y += tracex2
+progs-y += tracex3
+progs-y += tracex4
+progs-y += tracex5
+progs-y += tracex6
+progs-y += tracex7
+progs-y += test_probe_write_user
+progs-y += trace_output
+progs-y += lathist
+progs-y += offwaketime
+progs-y += spintest
+progs-y += map_perf_test
+progs-y += test_overhead
+progs-y += test_cgrp2_array_pin
+progs-y += test_cgrp2_attach
+progs-y += test_cgrp2_sock
+progs-y += test_cgrp2_sock2
+progs-y += xdp1
+progs-y += xdp2
+progs-y += xdp_router_ipv4
+progs-y += test_current_task_under_cgroup
+progs-y += trace_event
+progs-y += sampleip
+progs-y += tc_l2_redirect
+progs-y += lwt_len_hist
+progs-y += xdp_tx_iptunnel
+progs-y += test_map_in_map
+progs-y += xdp_redirect_map
+progs-y += xdp_redirect_cpu
+progs-y += xdp_monitor
+progs-y += xdp_rxq_info
+progs-y += syscall_tp
+progs-y += cpustat
+progs-y += xdp_adjust_tail
+progs-y += xdpsock
+progs-y += xdp_fwd
+progs-y += task_fd_query
+progs-y += xdp_sample_pkts
+progs-y += ibumad
+progs-y += hbm
# Libbpf dependencies
LIBBPF = $(TOOLS_PATH)/lib/bpf/libbpf.a
@@ -111,7 +109,7 @@ ibumad-objs := bpf_load.o ibumad_user.o $(TRACE_HELPERS)
hbm-objs := bpf_load.o hbm.o $(CGROUP_HELPERS)
# Tell kbuild to always build the programs
-always := $(hostprogs-y)
+always := $(progs-y)
always += sockex1_kern.o
always += sockex2_kern.o
always += sockex3_kern.o
@@ -171,26 +169,51 @@ always += ibumad_kern.o
always += hbm_out_kern.o
always += hbm_edt_kern.o
-KBUILD_HOSTCFLAGS += -I$(objtree)/usr/include
-KBUILD_HOSTCFLAGS += -I$(srctree)/tools/lib/bpf/
-KBUILD_HOSTCFLAGS += -I$(srctree)/tools/testing/selftests/bpf/
-KBUILD_HOSTCFLAGS += -I$(srctree)/tools/lib/ -I$(srctree)/tools/include
-KBUILD_HOSTCFLAGS += -I$(srctree)/tools/perf
-
-HOSTCFLAGS_bpf_load.o += -I$(objtree)/usr/include -Wno-unused-variable
-
-KBUILD_HOSTLDLIBS += $(LIBBPF) -lelf
-HOSTLDLIBS_tracex4 += -lrt
-HOSTLDLIBS_trace_output += -lrt
-HOSTLDLIBS_map_perf_test += -lrt
-HOSTLDLIBS_test_overhead += -lrt
-HOSTLDLIBS_xdpsock += -pthread
-
# Strip all expet -D options needed to handle linux headers
# for arm it's __LINUX_ARM_ARCH__ and potentially others fork vars
D_OPTIONS = $(shell echo "$(KBUILD_CFLAGS) " | sed 's/[[:blank:]]/\n/g' | \
sed '/^-D/!d' | tr '\n' ' ')
+ifdef SYSROOT
+ccflags-y += --sysroot=${SYSROOT}
+ccflags-y += -I${SYSROOT}/usr/include
+CLANG_EXTRA_CFLAGS := $(ccflags-y)
+PROGS_LDFLAGS := -L${SYSROOT}/usr/lib
+endif
+
+ccflags-y += -I$(srctree)/tools/lib/bpf/
+ccflags-y += -I$(srctree)/tools/testing/selftests/bpf/
+ccflags-y += -I$(srctree)/tools/lib/
+ccflags-y += -I$(srctree)/tools/perf
+
+ccflags-y += $(D_OPTIONS)
+ccflags-y += -Wall
+ccflags-y += -Wmissing-prototypes
+ccflags-y += -Wstrict-prototypes
+ccflags-y += -fomit-frame-pointer
+
+PROGS_CFLAGS := $(ccflags-y)
+
+ccflags-y += -I$(objtree)/usr/include
+ccflags-y += -I$(srctree)/tools/include
+
+PROGCFLAGS_bpf_load.o += -I$(objtree)/usr/include -I$(srctree)/tools/include \
+ -Wno-unused-variable
+PROGCFLAGS_sampleip_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_task_fd_query_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_trace_event_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_trace_output_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_tracex6_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_xdp_sample_pkts_user.o += -I$(srctree)/tools/include
+PROGCFLAGS_xdpsock_user.o += -I$(srctree)/tools/include
+
+PROGS_LDLIBS := $(LIBBPF) -lelf
+PROGLDLIBS_tracex4 += -lrt
+PROGLDLIBS_trace_output += -lrt
+PROGLDLIBS_map_perf_test += -lrt
+PROGLDLIBS_test_overhead += -lrt
+PROGLDLIBS_xdpsock += -pthread
+
CLANG_EXTRA_CFLAGS += $(D_OPTIONS)
# Allows pointing LLC/CLANG to a LLVM backend with bpf support, redefine on cmdline:
@@ -202,15 +225,14 @@ BTF_PAHOLE ?= pahole
# Detect that we're cross compiling and use the cross compiler
ifdef CROSS_COMPILE
-HOSTCC = $(CROSS_COMPILE)gcc
CLANG_ARCH_ARGS = --target=$(notdir $(CROSS_COMPILE:%-=%))
endif
# Don't evaluate probes and warnings if we need to run make recursively
ifneq ($(src),)
HDR_PROBE := $(shell printf "\#include <linux/types.h>\n struct list_head { int a; }; int main() { return 0; }" | \
- $(HOSTCC) $(KBUILD_HOSTCFLAGS) -x c - -o /dev/null 2>/dev/null && \
- echo okay)
+ $(CC) $(PROGS_CFLAGS) $(PROGS_LDFLAGS) -x c - -o /dev/null \
+ 2>/dev/null && echo okay)
ifeq ($(HDR_PROBE),)
$(warning WARNING: Detected possible issues with include path.)
@@ -246,7 +268,9 @@ clean:
$(LIBBPF): FORCE
# Fix up variables inherited from Kbuild that tools/ build system won't like
- $(MAKE) -C $(dir $@) RM='rm -rf' LDFLAGS= srctree=$(BPF_SAMPLES_PATH)/../../ O=
+ $(MAKE) -C $(dir $@) RM='rm -rf' EXTRA_CFLAGS="$(ccflags-y)" \
+ EXTRA_CXXFLAGS="$(ccflags-y)" LDFLAGS=$(PROGS_LDFLAGS) \
+ srctree=$(BPF_SAMPLES_PATH)/../../ O=
$(obj)/syscall_nrs.h: $(obj)/syscall_nrs.s FORCE
$(call filechk,offsets,__SYSCALL_NRS_H__)
@@ -283,6 +307,8 @@ $(obj)/hbm_out_kern.o: $(src)/hbm.h $(src)/hbm_kern.h
$(obj)/hbm.o: $(src)/hbm.h
$(obj)/hbm_edt_kern.o: $(src)/hbm.h $(src)/hbm_kern.h
+-include $(BPF_SAMPLES_PATH)/Makefile.prog
+
# asm/sysreg.h - inline assembly used by it is incompatible with llvm.
# But, there is no easy way to fix it, so just exclude it since it is
# useless for BPF samples.
diff --git a/samples/bpf/README.rst b/samples/bpf/README.rst
index 5f27e4faca50..6b5e4eace977 100644
--- a/samples/bpf/README.rst
+++ b/samples/bpf/README.rst
@@ -74,3 +74,10 @@ samples for the cross target.
export ARCH=arm64
export CROSS_COMPILE="aarch64-linux-gnu-"
make samples/bpf/ LLC=~/git/llvm/build/bin/llc CLANG=~/git/llvm/build/bin/clang
+
+If need to use environment of target board, the SYSROOT also can be set,
+pointing on FS of target board:
+
+make samples/bpf/ LLC=~/git/llvm/build/bin/llc \
+ CLANG=~/git/llvm/build/bin/clang \
+ SYSROOT=~/some_sdk/linux-devkit/sysroots/aarch64-linux-gnu
--
2.17.1
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* [PATCH RFC bpf-next 07/10] samples: bpf: add makefile.prog for separate CC build
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
The HOSTCC is supposed to build binaries and tools running on the host
afterwards, in order to simplify build or so, like "fixdep" or else.
In case of cross compiling "fixdep" is executed on host when the rest
samples should run on target arch. In order to build binaries for
target arch with CC and tools running on host with HOSTCC, lets add
Makefile.prog for simplicity, having definition and routines similar
to ones, used in script/Makefile.host. That allows later add
cross-compilation to samples/bpf with minimum changes.
Makefile.prog contains only stuff needed for samples/bpf, potentially
can be reused and sophisticated for other prog sets later and now
needed only for unblocking tricky samples/bpf cross compilation.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile.prog | 77 +++++++++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 samples/bpf/Makefile.prog
diff --git a/samples/bpf/Makefile.prog b/samples/bpf/Makefile.prog
new file mode 100644
index 000000000000..d5d02fbb5e6e
--- /dev/null
+++ b/samples/bpf/Makefile.prog
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0
+# ==========================================================================
+# Building binaries on the host system
+# Binaries are not used during the compilation of the kernel, and intendent to
+# be build for target board, target board can be host ofc. Added to build
+# binaries to run not on host system.
+#
+# Both C and C++ are supported, but preferred language is C for such utilities.
+#
+# Sample syntax (see Documentation/kbuild/makefiles.rst for reference)
+# progs-y := xdpsock_example
+# Will compile xdpsock_example.c and create an executable named xdpsock_example
+#
+# progs-y := xdpsock
+# xdpsock-objs := xdpsock_user.o xdpsock_user2.o
+# Will compile xdpsock.c and xdpsock.c, and then link the executable
+# xdpsock, based on xdpsock_user.o and xdpsock_user2.o
+#
+# Inherited from scripts/Makefile.host
+#
+__progs := $(sort $(progs-y))
+
+# C code
+# Executables compiled from a single .c file
+prog-csingle := $(foreach m,$(__progs), \
+ $(if $($(m)-objs)$($(m)-cxxobjs),,$(m)))
+
+# C executables linked based on several .o files
+prog-cmulti := $(foreach m,$(__progs),\
+ $(if $($(m)-cxxobjs),,$(if $($(m)-objs),$(m))))
+
+# Object (.o) files compiled from .c files
+prog-cobjs := $(sort $(foreach m,$(__progs),$($(m)-objs)))
+
+prog-csingle := $(addprefix $(obj)/,$(prog-csingle))
+prog-cmulti := $(addprefix $(obj)/,$(prog-cmulti))
+prog-cobjs := $(addprefix $(obj)/,$(prog-cobjs))
+
+#####
+# Handle options to gcc. Support building with separate output directory
+
+_progc_flags = $(PROGS_CFLAGS) \
+ $(PROGCFLAGS_$(basetarget).o)
+
+# $(objtree)/$(obj) for including generated headers from checkin source files
+ifeq ($(KBUILD_EXTMOD),)
+ifdef building_out_of_srctree
+_progc_flags += -I $(objtree)/$(obj)
+endif
+endif
+
+progc_flags = -Wp,-MD,$(depfile) $(_progc_flags)
+
+# Create executable from a single .c file
+# prog-csingle -> Executable
+quiet_cmd_prog-csingle = CC $@
+ cmd_prog-csingle = $(CC) $(progc_flags) $(PROGS_LDFLAGS) -o $@ $< \
+ $(PROGS_LDLIBS) $(PROGLDLIBS_$(@F))
+$(prog-csingle): $(obj)/%: $(src)/%.c FORCE
+ $(call if_changed_dep,prog-csingle)
+
+# Link an executable based on list of .o files, all plain c
+# prog-cmulti -> executable
+quiet_cmd_prog-cmulti = LD $@
+ cmd_prog-cmulti = $(CC) $(progc_flags) $(PROGS_LDFLAGS) -o $@ \
+ $(addprefix $(obj)/,$($(@F)-objs)) \
+ $(PROGS_LDLIBS) $(PROGLDLIBS_$(@F))
+$(prog-cmulti): $(prog-cobjs) FORCE
+ $(call if_changed,prog-cmulti)
+$(call multi_depend, $(prog-cmulti), , -objs)
+
+# Create .o file from a single .c file
+# prog-cobjs -> .o
+quiet_cmd_prog-cobjs = CC $@
+ cmd_prog-cobjs = $(CC) $(progc_flags) -c -o $@ $<
+$(prog-cobjs): $(obj)/%.o: $(src)/%.c FORCE
+ $(call if_changed_dep,prog-cobjs)
--
2.17.1
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* [PATCH RFC bpf-next 06/10] samples: bpf: makefile: fix HDR_PROBE
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
echo should be replace on echo -e to handle \n correctly, but instead,
replace it on printf as some systems can't handle echo -e.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 9232efa2b1b3..043f9cc14cdd 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -208,7 +208,7 @@ endif
# Don't evaluate probes and warnings if we need to run make recursively
ifneq ($(src),)
-HDR_PROBE := $(shell echo "\#include <linux/types.h>\n struct list_head { int a; }; int main() { return 0; }" | \
+HDR_PROBE := $(shell printf "\#include <linux/types.h>\n struct list_head { int a; }; int main() { return 0; }" | \
$(HOSTCC) $(KBUILD_HOSTCFLAGS) -x c - -o /dev/null 2>/dev/null && \
echo okay)
--
2.17.1
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* [PATCH RFC bpf-next 05/10] samples: bpf: Makefile: use vars from KBUILD_CFLAGS to handle linux headers
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
The kernel headers are reused from samples bpf, and autoconf.h is not
enough to reflect complete configuration for clang. One of such
configurations is __LINUX_ARM_ARCH__ min version used as instruction
set selector. In another case an error like "SMP is not
supported" for arm and others errors are issued and final object is
not correct.
---
samples/bpf/Makefile | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index cdd742c05200..9232efa2b1b3 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -186,6 +186,13 @@ HOSTLDLIBS_map_perf_test += -lrt
HOSTLDLIBS_test_overhead += -lrt
HOSTLDLIBS_xdpsock += -pthread
+# Strip all expet -D options needed to handle linux headers
+# for arm it's __LINUX_ARM_ARCH__ and potentially others fork vars
+D_OPTIONS = $(shell echo "$(KBUILD_CFLAGS) " | sed 's/[[:blank:]]/\n/g' | \
+ sed '/^-D/!d' | tr '\n' ' ')
+
+CLANG_EXTRA_CFLAGS += $(D_OPTIONS)
+
# Allows pointing LLC/CLANG to a LLVM backend with bpf support, redefine on cmdline:
# make samples/bpf/ LLC=~/git/llvm/build/bin/llc CLANG=~/git/llvm/build/bin/clang
LLC ?= llc
--
2.17.1
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* [PATCH RFC bpf-next 04/10] samples: bpf: use own EXTRA_CFLAGS for clang commands
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
It can overlap with CFLAGS used for libraries built with gcc if
not now then in following patches. Correct it here for simplicity.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index a2953357927e..cdd742c05200 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -219,10 +219,10 @@ BTF_LLVM_PROBE := $(shell echo "int main() { return 0; }" | \
/bin/rm -f ./llvm_btf_verify.o)
ifneq ($(BTF_LLVM_PROBE),)
- EXTRA_CFLAGS += -g
+ CLANG_EXTRA_CFLAGS += -g
else
ifneq ($(and $(BTF_LLC_PROBE),$(BTF_PAHOLE_PROBE),$(BTF_OBJCOPY_PROBE)),)
- EXTRA_CFLAGS += -g
+ CLANG_EXTRA_CFLAGS += -g
LLC_FLAGS += -mattr=dwarfris
DWARF2BTF = y
endif
@@ -281,8 +281,8 @@ $(obj)/hbm_edt_kern.o: $(src)/hbm.h $(src)/hbm_kern.h
# useless for BPF samples.
$(obj)/%.o: $(src)/%.c
@echo " CLANG-bpf " $@
- $(Q)$(CLANG) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) $(EXTRA_CFLAGS) -I$(obj) \
- -I$(srctree)/tools/testing/selftests/bpf/ \
+ $(Q)$(CLANG) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) $(CLANG_EXTRA_CFLAGS) \
+ -I$(obj) -I$(srctree)/tools/testing/selftests/bpf/ \
-D__KERNEL__ -D__BPF_TRACING__ -Wno-unused-value -Wno-pointer-sign \
-D__TARGET_ARCH_$(SRCARCH) -Wno-compare-distinct-pointer-types \
-Wno-gnu-variable-sized-type-not-at-end \
--
2.17.1
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* [PATCH RFC bpf-next 03/10] libbpf: Makefile: add C/CXX/LDFLAGS to libbpf.so and test_libpf targets
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
In case of LDFLAGS and EXTRA_CC flags there is no way to pass them
correctly to build command, for instance when --sysroot is used or
external libraries are used, like -lelf. In follow patches this is
used for samples/bpf cross-compiling.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
tools/lib/bpf/Makefile | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/tools/lib/bpf/Makefile b/tools/lib/bpf/Makefile
index 844f6cd79c03..d606d249e334 100644
--- a/tools/lib/bpf/Makefile
+++ b/tools/lib/bpf/Makefile
@@ -99,6 +99,10 @@ else
CFLAGS := -g -Wall
endif
+ifdef EXTRA_CXXFLAGS
+ CXXFLAGS := $(EXTRA_CXXFLAGS)
+endif
+
ifeq ($(feature-libelf-mmap), 1)
override CFLAGS += -DHAVE_LIBELF_MMAP_SUPPORT
endif
@@ -179,8 +183,9 @@ $(BPF_IN): force elfdep bpfdep
$(OUTPUT)libbpf.so: $(OUTPUT)libbpf.so.$(LIBBPF_VERSION)
$(OUTPUT)libbpf.so.$(LIBBPF_VERSION): $(BPF_IN)
- $(QUIET_LINK)$(CC) --shared -Wl,-soname,libbpf.so.$(VERSION) \
- -Wl,--version-script=$(VERSION_SCRIPT) $^ -lelf -o $@
+ $(QUIET_LINK)$(CC) $(LDFLAGS) \
+ --shared -Wl,-soname,libbpf.so.$(VERSION) \
+ -Wl,--version-script=$(VERSION_SCRIPT) $^ -lelf -o $@
@ln -sf $(@F) $(OUTPUT)libbpf.so
@ln -sf $(@F) $(OUTPUT)libbpf.so.$(VERSION)
@@ -188,7 +193,7 @@ $(OUTPUT)libbpf.a: $(BPF_IN)
$(QUIET_LINK)$(RM) $@; $(AR) rcs $@ $^
$(OUTPUT)test_libbpf: test_libbpf.cpp $(OUTPUT)libbpf.a
- $(QUIET_LINK)$(CXX) $(INCLUDES) $^ -lelf -o $@
+ $(QUIET_LINK)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(INCLUDES) $^ -lelf -o $@
$(OUTPUT)libbpf.pc:
$(QUIET_GEN)sed -e "s|@PREFIX@|$(prefix)|" \
--
2.17.1
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* [PATCH RFC bpf-next 02/10] samples: bpf: Makefile: remove target for native build
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
No need to set --target for native build, at least for arm, the
default target will be used anyway. In case of arm, for at least
clang 5 - 10 it causes error like:
clang: warning: unknown platform, assuming -mfloat-abi=soft
LLVM ERROR: Unsupported calling convention
make[2]: *** [/home/root/snapshot/samples/bpf/Makefile:299:
/home/root/snapshot/samples/bpf/sockex1_kern.o] Error 1
To make the platform to be known, only set to real triple helps:
--target=arm-linux-gnueabihf
or just drop the target key to use default one. Decision to just drop
it and thus default target will be used, looks better.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile | 2 --
1 file changed, 2 deletions(-)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 61b7394b811e..a2953357927e 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -197,8 +197,6 @@ BTF_PAHOLE ?= pahole
ifdef CROSS_COMPILE
HOSTCC = $(CROSS_COMPILE)gcc
CLANG_ARCH_ARGS = --target=$(notdir $(CROSS_COMPILE:%-=%))
-else
-CLANG_ARCH_ARGS = -target $(ARCH)
endif
# Don't evaluate probes and warnings if we need to run make recursively
--
2.17.1
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* [PATCH RFC bpf-next 01/10] samples: bpf: Makefile: use --target from cross-compile
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
In-Reply-To: <20190830005037.24004-1-ivan.khoronzhuk@linaro.org>
For cross compiling the target triple can be inherited from
cross-compile prefix as it's done in CLANG_FLAGS from kernel makefile.
So copy-paste this decision from kernel Makefile.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
---
samples/bpf/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/samples/bpf/Makefile b/samples/bpf/Makefile
index 1d9be26b4edd..61b7394b811e 100644
--- a/samples/bpf/Makefile
+++ b/samples/bpf/Makefile
@@ -196,6 +196,8 @@ BTF_PAHOLE ?= pahole
# Detect that we're cross compiling and use the cross compiler
ifdef CROSS_COMPILE
HOSTCC = $(CROSS_COMPILE)gcc
+CLANG_ARCH_ARGS = --target=$(notdir $(CROSS_COMPILE:%-=%))
+else
CLANG_ARCH_ARGS = -target $(ARCH)
endif
--
2.17.1
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* [PATCH RFC bpf-next 00/10] improve/fix cross-compilation for bpf samples
From: Ivan Khoronzhuk @ 2019-08-30 0:50 UTC (permalink / raw)
To: linux, ast, daniel, yhs, davem, jakub.kicinski, hawk,
john.fastabend
Cc: Ivan Khoronzhuk, netdev, linux-kernel, clang-built-linux, bpf,
linux-arm-kernel
This series contains mainly fixes/improvements for cross-compilation
(also verified on native platform build), tested on arm, but intended
for any arch.
The several patches are related to llvm clang and should be out of this
series or even fixed in another way, and here just to get comments:
arm: include: asm: swab: mask rev16 instruction for clang
arm: include: asm: unified: mask .syntax unified for clang
Also, only for armv7, there is one more problem related to long and
void type sizes for 32 bits, while the BPF LLVM back end still
operates in 64 bit, but that's another story.
Smth related not only for cross-compilation and can have impact on other
archs and build environments, so might be good idea to verify it in order
to add appropriate changes, some warn options can be tuned, so comment.
Ivan Khoronzhuk (10):
samples: bpf: Makefile: use --target from cross-compile
samples: bpf: Makefile: remove target for native build
libbpf: Makefile: add C/CXX/LDFLAGS to libbpf.so and test_libpf
targets
samples: bpf: use own EXTRA_CFLAGS for clang commands
samples: bpf: Makefile: use vars from KBUILD_CFLAGS to handle linux
headers
samples: bpf: makefile: fix HDR_PROBE
samples: bpf: add makefile.prog for separate CC build
samples: bpf: Makefile: base progs build on Makefile.progs
arm: include: asm: swab: mask rev16 instruction for clang
arm: include: asm: unified: mask .syntax unified for clang
arch/arm/include/asm/swab.h | 3 +
arch/arm/include/asm/unified.h | 6 +-
samples/bpf/Makefile | 177 +++++++++++++++++++--------------
samples/bpf/Makefile.prog | 77 ++++++++++++++
samples/bpf/README.rst | 7 ++
tools/lib/bpf/Makefile | 11 +-
6 files changed, 205 insertions(+), 76 deletions(-)
create mode 100644 samples/bpf/Makefile.prog
--
2.17.1
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* Re: [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it
From: Andrew Murray @ 2019-08-30 0:08 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829165457.grindfmgpdpsbt4i@willie-the-truck>
On Thu, Aug 29, 2019 at 05:54:58PM +0100, Will Deacon wrote:
> On Thu, Aug 29, 2019 at 04:48:34PM +0100, Will Deacon wrote:
> > diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> > index 95091f72228b..7fa042f5444e 100644
> > --- a/arch/arm64/include/asm/atomic_ll_sc.h
> > +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> > @@ -23,6 +23,10 @@ asm_ops "\n" \
> > #define __LL_SC_FALLBACK(asm_ops) asm_ops
> > #endif
> >
> > +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> > +#define K
> > +#endif
>
> Bah, I need to use something like __stringify when the constraint is used
> in order for this to get expanded properly. Updated diff below.
I don't think the changes in your updated diff are required. We successfully
combine 'asm_op' with the remainder of the assembly string without using
__stringify, and this is no different to how the original patch combined
'constraint' with "r".
You can verify this by looking at the preprocessed .i files generated with
something like:
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- drivers/spi/spi-rockchip.i
I see no difference (with GCC 7.3.1) between the original approach and your
use of __stringify. Incidentally you end up with "K" "r" instead of "Kr" but
it seems to have the desired effect (e.g. supress/emit out of range errors).
I have a couple of macros that resolves this to "Kr" but I don't think it's
necessary.
Did you find that it didn't work without your changes? I found it hard to
reproduce the out-of-range errors until I made the following change, I could
then easily see the effect of changing the constraint:
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
- : #constraint "r" (i)); \
+ : #constraint) "r" (4294967295)); \
}
Thanks,
Andrew Murray
>
> Will
>
> --->8
>
> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
> index 61de992bbea3..0cef056b5fb1 100644
> --- a/arch/arm64/Makefile
> +++ b/arch/arm64/Makefile
> @@ -39,6 +39,12 @@ $(warning LSE atomics not supported by binutils)
> endif
> endif
>
> +cc_has_k_constraint := $(call try-run,echo \
> + 'int main(void) { \
> + asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \
> + return 0; \
> + }' | $(CC) -S -x c -o "$$TMP" -,,-DCONFIG_CC_HAS_K_CONSTRAINT=1)
> +
> ifeq ($(CONFIG_ARM64), y)
> brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)
>
> @@ -63,7 +69,8 @@ ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y)
> endif
> endif
>
> -KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) $(compat_vdso)
> +KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) \
> + $(compat_vdso) $(cc_has_k_constraint)
> KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
> KBUILD_CFLAGS += $(call cc-disable-warning, psabi)
> KBUILD_AFLAGS += $(lseinstr) $(brokengasinst) $(compat_vdso)
> diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> index 95091f72228b..7b012148bfd6 100644
> --- a/arch/arm64/include/asm/atomic_ll_sc.h
> +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> @@ -10,6 +10,8 @@
> #ifndef __ASM_ATOMIC_LL_SC_H
> #define __ASM_ATOMIC_LL_SC_H
>
> +#include <linux/stringify.h>
> +
> #if IS_ENABLED(CONFIG_ARM64_LSE_ATOMICS) && IS_ENABLED(CONFIG_AS_LSE)
> #define __LL_SC_FALLBACK(asm_ops) \
> " b 3f\n" \
> @@ -23,6 +25,10 @@ asm_ops "\n" \
> #define __LL_SC_FALLBACK(asm_ops) asm_ops
> #endif
>
> +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> +#define K
> +#endif
> +
> /*
> * AArch64 UP and SMP safe atomic ops. We use load exclusive and
> * store exclusive to ensure that these are atomic. We may loop
> @@ -44,7 +50,7 @@ __ll_sc_atomic_##op(int i, atomic_t *v) \
> " stxr %w1, %w0, %2\n" \
> " cbnz %w1, 1b\n") \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i)); \
> + : __stringify(constraint) "r" (i)); \
> }
>
> #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
> @@ -63,7 +69,7 @@ __ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \
> " cbnz %w1, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -85,7 +91,7 @@ __ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \
> " cbnz %w2, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -113,10 +119,15 @@ ATOMIC_OPS(sub, sub, J)
> ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
> ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
>
> -ATOMIC_OPS(and, and, )
> +ATOMIC_OPS(and, and, K)
> +ATOMIC_OPS(or, orr, K)
> +ATOMIC_OPS(xor, eor, K)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> ATOMIC_OPS(andnot, bic, )
> -ATOMIC_OPS(or, orr, )
> -ATOMIC_OPS(xor, eor, )
>
> #undef ATOMIC_OPS
> #undef ATOMIC_FETCH_OP
> @@ -138,7 +149,7 @@ __ll_sc_atomic64_##op(s64 i, atomic64_t *v) \
> " stxr %w1, %0, %2\n" \
> " cbnz %w1, 1b") \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i)); \
> + : __stringify(constraint) "r" (i)); \
> }
>
> #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\
> @@ -157,7 +168,7 @@ __ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \
> " cbnz %w1, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -179,7 +190,7 @@ __ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
> " cbnz %w2, 1b\n" \
> " " #mb ) \
> : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i) \
> + : __stringify(constraint) "r" (i) \
> : cl); \
> \
> return result; \
> @@ -208,9 +219,14 @@ ATOMIC64_OPS(sub, sub, J)
> ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
>
> ATOMIC64_OPS(and, and, L)
> -ATOMIC64_OPS(andnot, bic, )
> ATOMIC64_OPS(or, orr, L)
> ATOMIC64_OPS(xor, eor, L)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> +ATOMIC64_OPS(andnot, bic, )
>
> #undef ATOMIC64_OPS
> #undef ATOMIC64_FETCH_OP
> @@ -269,7 +285,7 @@ __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
> "2:") \
> : [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
> [v] "+Q" (*(u##sz *)ptr) \
> - : [old] #constraint "r" (old), [new] "r" (new) \
> + : [old] __stringify(constraint) "r" (old), [new] "r" (new) \
> : cl); \
> \
> return oldval; \
> @@ -280,21 +296,21 @@ __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
> * handle the 'K' constraint for the value 4294967295 - thus we use no
> * constraint for 32 bit operations.
> */
> -__CMPXCHG_CASE(w, b, , 8, , , , , )
> -__CMPXCHG_CASE(w, h, , 16, , , , , )
> -__CMPXCHG_CASE(w, , , 32, , , , , )
> +__CMPXCHG_CASE(w, b, , 8, , , , , K)
> +__CMPXCHG_CASE(w, h, , 16, , , , , K)
> +__CMPXCHG_CASE(w, , , 32, , , , , K)
> __CMPXCHG_CASE( , , , 64, , , , , L)
> -__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", )
> -__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", )
> -__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", )
> +__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", K)
> +__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", K)
> +__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", K)
> __CMPXCHG_CASE( , , acq_, 64, , a, , "memory", L)
> -__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", )
> -__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", )
> -__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", )
> +__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", K)
> +__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", K)
> +__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", K)
> __CMPXCHG_CASE( , , rel_, 64, , , l, "memory", L)
> -__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", )
> +__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
> __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
>
> #undef __CMPXCHG_CASE
> @@ -332,5 +348,6 @@ __CMPXCHG_DBL( , , , )
> __CMPXCHG_DBL(_mb, dmb ish, l, "memory")
>
> #undef __CMPXCHG_DBL
> +#undef K
>
> #endif /* __ASM_ATOMIC_LL_SC_H */
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* Re: [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it
From: Andrew Murray @ 2019-08-29 23:49 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829154834.26547-11-will@kernel.org>
On Thu, Aug 29, 2019 at 04:48:34PM +0100, Will Deacon wrote:
> The 'K' constraint is a documented AArch64 machine constraint supported
> by GCC for matching integer constants that can be used with a 32-bit
> logical instruction. Unfortunately, some released compilers erroneously
> accept the immediate '4294967295' for this constraint, which is later
> refused by GAS at assembly time. This had led us to avoid the use of
> the 'K' constraint altogether.
>
> Instead, detect whether the compiler is up to the job when building the
> kernel and pass the 'K' constraint to our 32-bit atomic macros when it
> appears to be supported.
>
> Signed-off-by: Will Deacon <will@kernel.org>
See my comments within this email thread, but for this patch as it is:
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> ---
> arch/arm64/Makefile | 9 ++++++-
> arch/arm64/include/asm/atomic_ll_sc.h | 47 +++++++++++++++++++++++------------
> 2 files changed, 39 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
> index 61de992bbea3..0cef056b5fb1 100644
> --- a/arch/arm64/Makefile
> +++ b/arch/arm64/Makefile
> @@ -39,6 +39,12 @@ $(warning LSE atomics not supported by binutils)
> endif
> endif
>
> +cc_has_k_constraint := $(call try-run,echo \
> + 'int main(void) { \
> + asm volatile("and w0, w0, %w0" :: "K" (4294967295)); \
> + return 0; \
> + }' | $(CC) -S -x c -o "$$TMP" -,,-DCONFIG_CC_HAS_K_CONSTRAINT=1)
> +
> ifeq ($(CONFIG_ARM64), y)
> brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)
>
> @@ -63,7 +69,8 @@ ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y)
> endif
> endif
>
> -KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) $(compat_vdso)
> +KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst) \
> + $(compat_vdso) $(cc_has_k_constraint)
> KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
> KBUILD_CFLAGS += $(call cc-disable-warning, psabi)
> KBUILD_AFLAGS += $(lseinstr) $(brokengasinst) $(compat_vdso)
> diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> index 95091f72228b..7fa042f5444e 100644
> --- a/arch/arm64/include/asm/atomic_ll_sc.h
> +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> @@ -23,6 +23,10 @@ asm_ops "\n" \
> #define __LL_SC_FALLBACK(asm_ops) asm_ops
> #endif
>
> +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> +#define K
> +#endif
> +
> /*
> * AArch64 UP and SMP safe atomic ops. We use load exclusive and
> * store exclusive to ensure that these are atomic. We may loop
> @@ -113,10 +117,15 @@ ATOMIC_OPS(sub, sub, J)
> ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
> ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
>
> -ATOMIC_OPS(and, and, )
> +ATOMIC_OPS(and, and, K)
> +ATOMIC_OPS(or, orr, K)
> +ATOMIC_OPS(xor, eor, K)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> ATOMIC_OPS(andnot, bic, )
> -ATOMIC_OPS(or, orr, )
> -ATOMIC_OPS(xor, eor, )
>
> #undef ATOMIC_OPS
> #undef ATOMIC_FETCH_OP
> @@ -208,9 +217,14 @@ ATOMIC64_OPS(sub, sub, J)
> ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
>
> ATOMIC64_OPS(and, and, L)
> -ATOMIC64_OPS(andnot, bic, )
> ATOMIC64_OPS(or, orr, L)
> ATOMIC64_OPS(xor, eor, L)
> +/*
> + * GAS converts the mysterious and undocumented BIC (immediate) alias to
> + * an AND (immediate) instruction with the immediate inverted. We don't
> + * have a constraint for this, so fall back to register.
> + */
> +ATOMIC64_OPS(andnot, bic, )
>
> #undef ATOMIC64_OPS
> #undef ATOMIC64_FETCH_OP
> @@ -280,21 +294,21 @@ __ll_sc__cmpxchg_case_##name##sz(volatile void *ptr, \
> * handle the 'K' constraint for the value 4294967295 - thus we use no
> * constraint for 32 bit operations.
> */
> -__CMPXCHG_CASE(w, b, , 8, , , , , )
> -__CMPXCHG_CASE(w, h, , 16, , , , , )
> -__CMPXCHG_CASE(w, , , 32, , , , , )
> +__CMPXCHG_CASE(w, b, , 8, , , , , K)
> +__CMPXCHG_CASE(w, h, , 16, , , , , K)
> +__CMPXCHG_CASE(w, , , 32, , , , , K)
> __CMPXCHG_CASE( , , , 64, , , , , L)
> -__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", )
> -__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", )
> -__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", )
> +__CMPXCHG_CASE(w, b, acq_, 8, , a, , "memory", K)
> +__CMPXCHG_CASE(w, h, acq_, 16, , a, , "memory", K)
> +__CMPXCHG_CASE(w, , acq_, 32, , a, , "memory", K)
> __CMPXCHG_CASE( , , acq_, 64, , a, , "memory", L)
> -__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", )
> -__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", )
> -__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", )
> +__CMPXCHG_CASE(w, b, rel_, 8, , , l, "memory", K)
> +__CMPXCHG_CASE(w, h, rel_, 16, , , l, "memory", K)
> +__CMPXCHG_CASE(w, , rel_, 32, , , l, "memory", K)
> __CMPXCHG_CASE( , , rel_, 64, , , l, "memory", L)
> -__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", )
> -__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", )
> +__CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
> +__CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
> __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
>
> #undef __CMPXCHG_CASE
> @@ -332,5 +346,6 @@ __CMPXCHG_DBL( , , , )
> __CMPXCHG_DBL(_mb, dmb ish, l, "memory")
>
> #undef __CMPXCHG_DBL
> +#undef K
>
> #endif /* __ASM_ATOMIC_LL_SC_H */
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [PATCH v5 09/10] arm64: atomics: Undefine internal macros after use
From: Andrew Murray @ 2019-08-29 23:44 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829154834.26547-10-will@kernel.org>
On Thu, Aug 29, 2019 at 04:48:33PM +0100, Will Deacon wrote:
> We use a bunch of internal macros when constructing our atomic and
> cmpxchg routines in order to save on boilerplate. Avoid exposing these
> directly to users of the header files.
>
> Signed-off-by: Will Deacon <will@kernel.org>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> ---
> arch/arm64/include/asm/atomic.h | 7 +++++++
> arch/arm64/include/asm/cmpxchg.h | 4 ++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
> index 7c334337674d..916e5a6d5454 100644
> --- a/arch/arm64/include/asm/atomic.h
> +++ b/arch/arm64/include/asm/atomic.h
> @@ -32,6 +32,7 @@ ATOMIC_OP(atomic_add)
> ATOMIC_OP(atomic_and)
> ATOMIC_OP(atomic_sub)
>
> +#undef ATOMIC_OP
>
> #define ATOMIC_FETCH_OP(name, op) \
> static inline int arch_##op##name(int i, atomic_t *v) \
> @@ -54,6 +55,8 @@ ATOMIC_FETCH_OPS(atomic_fetch_sub)
> ATOMIC_FETCH_OPS(atomic_add_return)
> ATOMIC_FETCH_OPS(atomic_sub_return)
>
> +#undef ATOMIC_FETCH_OP
> +#undef ATOMIC_FETCH_OPS
>
> #define ATOMIC64_OP(op) \
> static inline void arch_##op(long i, atomic64_t *v) \
> @@ -68,6 +71,7 @@ ATOMIC64_OP(atomic64_add)
> ATOMIC64_OP(atomic64_and)
> ATOMIC64_OP(atomic64_sub)
>
> +#undef ATOMIC64_OP
>
> #define ATOMIC64_FETCH_OP(name, op) \
> static inline long arch_##op##name(long i, atomic64_t *v) \
> @@ -90,6 +94,9 @@ ATOMIC64_FETCH_OPS(atomic64_fetch_sub)
> ATOMIC64_FETCH_OPS(atomic64_add_return)
> ATOMIC64_FETCH_OPS(atomic64_sub_return)
>
> +#undef ATOMIC64_FETCH_OP
> +#undef ATOMIC64_FETCH_OPS
> +
> static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
> {
> return __lse_ll_sc_body(atomic64_dec_if_positive, v);
> diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
> index afaba73e0b2c..a1398f2f9994 100644
> --- a/arch/arm64/include/asm/cmpxchg.h
> +++ b/arch/arm64/include/asm/cmpxchg.h
> @@ -129,6 +129,8 @@ __CMPXCHG_CASE(mb_, 16)
> __CMPXCHG_CASE(mb_, 32)
> __CMPXCHG_CASE(mb_, 64)
>
> +#undef __CMPXCHG_CASE
> +
> #define __CMPXCHG_DBL(name) \
> static inline long __cmpxchg_double##name(unsigned long old1, \
> unsigned long old2, \
> @@ -143,6 +145,8 @@ static inline long __cmpxchg_double##name(unsigned long old1, \
> __CMPXCHG_DBL( )
> __CMPXCHG_DBL(_mb)
>
> +#undef __CMPXCHG_DBL
> +
> #define __CMPXCHG_GEN(sfx) \
> static inline unsigned long __cmpxchg##sfx(volatile void *ptr, \
> unsigned long old, \
> --
> 2.11.0
>
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* Re: [PATCH v5 08/10] arm64: lse: Make ARM64_LSE_ATOMICS depend on JUMP_LABEL
From: Andrew Murray @ 2019-08-29 23:44 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829154834.26547-9-will@kernel.org>
On Thu, Aug 29, 2019 at 04:48:32PM +0100, Will Deacon wrote:
> Support for LSE atomic instructions (CONFIG_ARM64_LSE_ATOMICS) relies on
> a static key to select between the legacy LL/SC implementation which is
> available on all arm64 CPUs and the super-duper LSE implementation which
> is available on CPUs implementing v8.1 and later.
>
> Unfortunately, when building a kernel with CONFIG_JUMP_LABEL disabled
> (e.g. because the toolchain doesn't support 'asm goto'), the static key
> inside the atomics code tries to use atomics itself. This results in a
> mess of circular includes and a build failure:
>
> In file included from ./arch/arm64/include/asm/lse.h:11,
> from ./arch/arm64/include/asm/atomic.h:16,
> from ./include/linux/atomic.h:7,
> from ./include/asm-generic/bitops/atomic.h:5,
> from ./arch/arm64/include/asm/bitops.h:26,
> from ./include/linux/bitops.h:19,
> from ./include/linux/kernel.h:12,
> from ./include/asm-generic/bug.h:18,
> from ./arch/arm64/include/asm/bug.h:26,
> from ./include/linux/bug.h:5,
> from ./include/linux/page-flags.h:10,
> from kernel/bounds.c:10:
> ./include/linux/jump_label.h: In function ‘static_key_count’:
> ./include/linux/jump_label.h:254:9: error: implicit declaration of function ‘atomic_read’ [-Werror=implicit-function-declaration]
> return atomic_read(&key->enabled);
> ^~~~~~~~~~~
>
> [ ... more of the same ... ]
>
> Since LSE atomic instructions are not critical to the operation of the
> kernel, make them depend on JUMP_LABEL at compile time.
>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> arch/arm64/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 3adcec05b1f6..27405ac94228 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1263,6 +1263,7 @@ config ARM64_PAN
>
> config ARM64_LSE_ATOMICS
> bool "Atomic instructions"
> + depends on JUMP_LABEL
> default y
> help
> As part of the Large System Extensions, ARMv8.1 introduces new
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [PATCH v5 07/10] arm64: asm: Kill 'asm/atomic_arch.h'
From: Andrew Murray @ 2019-08-29 23:43 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829154834.26547-8-will@kernel.org>
On Thu, Aug 29, 2019 at 04:48:31PM +0100, Will Deacon wrote:
> The contents of 'asm/atomic_arch.h' can be split across some of our
> other 'asm/' headers. Remove it.
>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> arch/arm64/include/asm/atomic.h | 77 ++++++++++++++++-
> arch/arm64/include/asm/atomic_arch.h | 155 -----------------------------------
> arch/arm64/include/asm/cmpxchg.h | 41 ++++++++-
> arch/arm64/include/asm/lse.h | 24 ++++++
> 4 files changed, 140 insertions(+), 157 deletions(-)
> delete mode 100644 arch/arm64/include/asm/atomic_arch.h
>
> diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
> index c70d3f389d29..7c334337674d 100644
> --- a/arch/arm64/include/asm/atomic.h
> +++ b/arch/arm64/include/asm/atomic.h
> @@ -17,9 +17,84 @@
>
> #ifdef __KERNEL__
>
> -#include <asm/atomic_arch.h>
> #include <asm/cmpxchg.h>
>
> +#define ATOMIC_OP(op) \
> +static inline void arch_##op(int i, atomic_t *v) \
> +{ \
> + __lse_ll_sc_body(op, i, v); \
> +}
> +
> +ATOMIC_OP(atomic_andnot)
> +ATOMIC_OP(atomic_or)
> +ATOMIC_OP(atomic_xor)
> +ATOMIC_OP(atomic_add)
> +ATOMIC_OP(atomic_and)
> +ATOMIC_OP(atomic_sub)
> +
> +
> +#define ATOMIC_FETCH_OP(name, op) \
> +static inline int arch_##op##name(int i, atomic_t *v) \
> +{ \
> + return __lse_ll_sc_body(op##name, i, v); \
> +}
> +
> +#define ATOMIC_FETCH_OPS(op) \
> + ATOMIC_FETCH_OP(_relaxed, op) \
> + ATOMIC_FETCH_OP(_acquire, op) \
> + ATOMIC_FETCH_OP(_release, op) \
> + ATOMIC_FETCH_OP( , op)
> +
> +ATOMIC_FETCH_OPS(atomic_fetch_andnot)
> +ATOMIC_FETCH_OPS(atomic_fetch_or)
> +ATOMIC_FETCH_OPS(atomic_fetch_xor)
> +ATOMIC_FETCH_OPS(atomic_fetch_add)
> +ATOMIC_FETCH_OPS(atomic_fetch_and)
> +ATOMIC_FETCH_OPS(atomic_fetch_sub)
> +ATOMIC_FETCH_OPS(atomic_add_return)
> +ATOMIC_FETCH_OPS(atomic_sub_return)
> +
> +
> +#define ATOMIC64_OP(op) \
> +static inline void arch_##op(long i, atomic64_t *v) \
> +{ \
> + __lse_ll_sc_body(op, i, v); \
> +}
> +
> +ATOMIC64_OP(atomic64_andnot)
> +ATOMIC64_OP(atomic64_or)
> +ATOMIC64_OP(atomic64_xor)
> +ATOMIC64_OP(atomic64_add)
> +ATOMIC64_OP(atomic64_and)
> +ATOMIC64_OP(atomic64_sub)
> +
> +
> +#define ATOMIC64_FETCH_OP(name, op) \
> +static inline long arch_##op##name(long i, atomic64_t *v) \
> +{ \
> + return __lse_ll_sc_body(op##name, i, v); \
> +}
> +
> +#define ATOMIC64_FETCH_OPS(op) \
> + ATOMIC64_FETCH_OP(_relaxed, op) \
> + ATOMIC64_FETCH_OP(_acquire, op) \
> + ATOMIC64_FETCH_OP(_release, op) \
> + ATOMIC64_FETCH_OP( , op)
> +
> +ATOMIC64_FETCH_OPS(atomic64_fetch_andnot)
> +ATOMIC64_FETCH_OPS(atomic64_fetch_or)
> +ATOMIC64_FETCH_OPS(atomic64_fetch_xor)
> +ATOMIC64_FETCH_OPS(atomic64_fetch_add)
> +ATOMIC64_FETCH_OPS(atomic64_fetch_and)
> +ATOMIC64_FETCH_OPS(atomic64_fetch_sub)
> +ATOMIC64_FETCH_OPS(atomic64_add_return)
> +ATOMIC64_FETCH_OPS(atomic64_sub_return)
> +
> +static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
> +{
> + return __lse_ll_sc_body(atomic64_dec_if_positive, v);
> +}
> +
> #define ATOMIC_INIT(i) { (i) }
>
> #define arch_atomic_read(v) READ_ONCE((v)->counter)
> diff --git a/arch/arm64/include/asm/atomic_arch.h b/arch/arm64/include/asm/atomic_arch.h
> deleted file mode 100644
> index 1aac7fc65084..000000000000
> --- a/arch/arm64/include/asm/atomic_arch.h
> +++ /dev/null
> @@ -1,155 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * Selection between LSE and LL/SC atomics.
> - *
> - * Copyright (C) 2018 ARM Ltd.
> - * Author: Andrew Murray <andrew.murray@arm.com>
> - */
> -
> -#ifndef __ASM_ATOMIC_ARCH_H
> -#define __ASM_ATOMIC_ARCH_H
> -
> -
> -#include <linux/jump_label.h>
> -
> -#include <asm/cpucaps.h>
> -#include <asm/atomic_ll_sc.h>
> -#include <asm/atomic_lse.h>
> -
> -extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
> -extern struct static_key_false arm64_const_caps_ready;
> -
> -static inline bool system_uses_lse_atomics(void)
> -{
> - return (IS_ENABLED(CONFIG_ARM64_LSE_ATOMICS) &&
> - IS_ENABLED(CONFIG_AS_LSE) &&
> - static_branch_likely(&arm64_const_caps_ready)) &&
> - static_branch_likely(&cpu_hwcap_keys[ARM64_HAS_LSE_ATOMICS]);
> -}
> -
> -#define __lse_ll_sc_body(op, ...) \
> -({ \
> - system_uses_lse_atomics() ? \
> - __lse_##op(__VA_ARGS__) : \
> - __ll_sc_##op(__VA_ARGS__); \
> -})
> -
> -#define ATOMIC_OP(op) \
> -static inline void arch_##op(int i, atomic_t *v) \
> -{ \
> - __lse_ll_sc_body(op, i, v); \
> -}
> -
> -ATOMIC_OP(atomic_andnot)
> -ATOMIC_OP(atomic_or)
> -ATOMIC_OP(atomic_xor)
> -ATOMIC_OP(atomic_add)
> -ATOMIC_OP(atomic_and)
> -ATOMIC_OP(atomic_sub)
> -
> -
> -#define ATOMIC_FETCH_OP(name, op) \
> -static inline int arch_##op##name(int i, atomic_t *v) \
> -{ \
> - return __lse_ll_sc_body(op##name, i, v); \
> -}
> -
> -#define ATOMIC_FETCH_OPS(op) \
> - ATOMIC_FETCH_OP(_relaxed, op) \
> - ATOMIC_FETCH_OP(_acquire, op) \
> - ATOMIC_FETCH_OP(_release, op) \
> - ATOMIC_FETCH_OP( , op)
> -
> -ATOMIC_FETCH_OPS(atomic_fetch_andnot)
> -ATOMIC_FETCH_OPS(atomic_fetch_or)
> -ATOMIC_FETCH_OPS(atomic_fetch_xor)
> -ATOMIC_FETCH_OPS(atomic_fetch_add)
> -ATOMIC_FETCH_OPS(atomic_fetch_and)
> -ATOMIC_FETCH_OPS(atomic_fetch_sub)
> -ATOMIC_FETCH_OPS(atomic_add_return)
> -ATOMIC_FETCH_OPS(atomic_sub_return)
> -
> -
> -#define ATOMIC64_OP(op) \
> -static inline void arch_##op(long i, atomic64_t *v) \
> -{ \
> - __lse_ll_sc_body(op, i, v); \
> -}
> -
> -ATOMIC64_OP(atomic64_andnot)
> -ATOMIC64_OP(atomic64_or)
> -ATOMIC64_OP(atomic64_xor)
> -ATOMIC64_OP(atomic64_add)
> -ATOMIC64_OP(atomic64_and)
> -ATOMIC64_OP(atomic64_sub)
> -
> -
> -#define ATOMIC64_FETCH_OP(name, op) \
> -static inline long arch_##op##name(long i, atomic64_t *v) \
> -{ \
> - return __lse_ll_sc_body(op##name, i, v); \
> -}
> -
> -#define ATOMIC64_FETCH_OPS(op) \
> - ATOMIC64_FETCH_OP(_relaxed, op) \
> - ATOMIC64_FETCH_OP(_acquire, op) \
> - ATOMIC64_FETCH_OP(_release, op) \
> - ATOMIC64_FETCH_OP( , op)
> -
> -ATOMIC64_FETCH_OPS(atomic64_fetch_andnot)
> -ATOMIC64_FETCH_OPS(atomic64_fetch_or)
> -ATOMIC64_FETCH_OPS(atomic64_fetch_xor)
> -ATOMIC64_FETCH_OPS(atomic64_fetch_add)
> -ATOMIC64_FETCH_OPS(atomic64_fetch_and)
> -ATOMIC64_FETCH_OPS(atomic64_fetch_sub)
> -ATOMIC64_FETCH_OPS(atomic64_add_return)
> -ATOMIC64_FETCH_OPS(atomic64_sub_return)
> -
> -
> -static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
> -{
> - return __lse_ll_sc_body(atomic64_dec_if_positive, v);
> -}
> -
> -#define __CMPXCHG_CASE(name, sz) \
> -static inline u##sz __cmpxchg_case_##name##sz(volatile void *ptr, \
> - u##sz old, \
> - u##sz new) \
> -{ \
> - return __lse_ll_sc_body(_cmpxchg_case_##name##sz, \
> - ptr, old, new); \
> -}
> -
> -__CMPXCHG_CASE( , 8)
> -__CMPXCHG_CASE( , 16)
> -__CMPXCHG_CASE( , 32)
> -__CMPXCHG_CASE( , 64)
> -__CMPXCHG_CASE(acq_, 8)
> -__CMPXCHG_CASE(acq_, 16)
> -__CMPXCHG_CASE(acq_, 32)
> -__CMPXCHG_CASE(acq_, 64)
> -__CMPXCHG_CASE(rel_, 8)
> -__CMPXCHG_CASE(rel_, 16)
> -__CMPXCHG_CASE(rel_, 32)
> -__CMPXCHG_CASE(rel_, 64)
> -__CMPXCHG_CASE(mb_, 8)
> -__CMPXCHG_CASE(mb_, 16)
> -__CMPXCHG_CASE(mb_, 32)
> -__CMPXCHG_CASE(mb_, 64)
> -
> -
> -#define __CMPXCHG_DBL(name) \
> -static inline long __cmpxchg_double##name(unsigned long old1, \
> - unsigned long old2, \
> - unsigned long new1, \
> - unsigned long new2, \
> - volatile void *ptr) \
> -{ \
> - return __lse_ll_sc_body(_cmpxchg_double##name, \
> - old1, old2, new1, new2, ptr); \
> -}
> -
> -__CMPXCHG_DBL( )
> -__CMPXCHG_DBL(_mb)
> -
> -#endif /* __ASM_ATOMIC_LSE_H */
> diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
> index e5fff8cd4904..afaba73e0b2c 100644
> --- a/arch/arm64/include/asm/cmpxchg.h
> +++ b/arch/arm64/include/asm/cmpxchg.h
> @@ -10,7 +10,6 @@
> #include <linux/build_bug.h>
> #include <linux/compiler.h>
>
> -#include <asm/atomic_arch.h>
> #include <asm/barrier.h>
> #include <asm/lse.h>
>
> @@ -104,6 +103,46 @@ __XCHG_GEN(_mb)
> #define arch_xchg_release(...) __xchg_wrapper(_rel, __VA_ARGS__)
> #define arch_xchg(...) __xchg_wrapper( _mb, __VA_ARGS__)
>
> +#define __CMPXCHG_CASE(name, sz) \
> +static inline u##sz __cmpxchg_case_##name##sz(volatile void *ptr, \
> + u##sz old, \
> + u##sz new) \
> +{ \
> + return __lse_ll_sc_body(_cmpxchg_case_##name##sz, \
> + ptr, old, new); \
> +}
> +
> +__CMPXCHG_CASE( , 8)
> +__CMPXCHG_CASE( , 16)
> +__CMPXCHG_CASE( , 32)
> +__CMPXCHG_CASE( , 64)
> +__CMPXCHG_CASE(acq_, 8)
> +__CMPXCHG_CASE(acq_, 16)
> +__CMPXCHG_CASE(acq_, 32)
> +__CMPXCHG_CASE(acq_, 64)
> +__CMPXCHG_CASE(rel_, 8)
> +__CMPXCHG_CASE(rel_, 16)
> +__CMPXCHG_CASE(rel_, 32)
> +__CMPXCHG_CASE(rel_, 64)
> +__CMPXCHG_CASE(mb_, 8)
> +__CMPXCHG_CASE(mb_, 16)
> +__CMPXCHG_CASE(mb_, 32)
> +__CMPXCHG_CASE(mb_, 64)
> +
> +#define __CMPXCHG_DBL(name) \
> +static inline long __cmpxchg_double##name(unsigned long old1, \
> + unsigned long old2, \
> + unsigned long new1, \
> + unsigned long new2, \
> + volatile void *ptr) \
> +{ \
> + return __lse_ll_sc_body(_cmpxchg_double##name, \
> + old1, old2, new1, new2, ptr); \
> +}
> +
> +__CMPXCHG_DBL( )
> +__CMPXCHG_DBL(_mb)
> +
> #define __CMPXCHG_GEN(sfx) \
> static inline unsigned long __cmpxchg##sfx(volatile void *ptr, \
> unsigned long old, \
> diff --git a/arch/arm64/include/asm/lse.h b/arch/arm64/include/asm/lse.h
> index 08e818e53ed7..80b388278149 100644
> --- a/arch/arm64/include/asm/lse.h
> +++ b/arch/arm64/include/asm/lse.h
> @@ -2,22 +2,46 @@
> #ifndef __ASM_LSE_H
> #define __ASM_LSE_H
>
> +#include <asm/atomic_ll_sc.h>
> +
> #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
>
> #include <linux/compiler_types.h>
> #include <linux/export.h>
> +#include <linux/jump_label.h>
> #include <linux/stringify.h>
> #include <asm/alternative.h>
> +#include <asm/atomic_lse.h>
> #include <asm/cpucaps.h>
>
> __asm__(".arch_extension lse");
>
> +extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
> +extern struct static_key_false arm64_const_caps_ready;
> +
> +static inline bool system_uses_lse_atomics(void)
> +{
> + return (static_branch_likely(&arm64_const_caps_ready)) &&
> + static_branch_likely(&cpu_hwcap_keys[ARM64_HAS_LSE_ATOMICS]);
> +}
> +
> +#define __lse_ll_sc_body(op, ...) \
> +({ \
> + system_uses_lse_atomics() ? \
> + __lse_##op(__VA_ARGS__) : \
> + __ll_sc_##op(__VA_ARGS__); \
> +})
> +
> /* In-line patching at runtime */
> #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
> ALTERNATIVE(llsc, lse, ARM64_HAS_LSE_ATOMICS)
>
> #else /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
>
> +static inline bool system_uses_lse_atomics(void) { return false; }
> +
> +#define __lse_ll_sc_body(op, ...) __ll_sc_##op(__VA_ARGS__)
> +
> #define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc
>
> #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [GIT PULL] arm64: dts: Amlogic updates for v5.4 (round 2)
From: Kevin Hilman @ 2019-08-29 23:39 UTC (permalink / raw)
To: arm, soc; +Cc: linux-amlogic, linux-arm-kernel
In-Reply-To: <7h4l1zrf84.fsf@baylibre.com>
Arnd, Olof,
Kevin Hilman <khilman@baylibre.com> writes:
> Another (final) round of 64-bit DT updates for Amlogic SoCs for v5.4.
> Highlights are in the tag description, but of note is a tag pulled in
> from the clock tree due to a handful of new clocks used for DVFS and
> power domains.
Here's the promised respin (round 2.1):
In addition to the clock dependency listed above, this branch adds a
bunch of DT users of a new PM domain driver, which has new bindings and
DT headers added in my drivers PR. That drivers branch is also merged
here to ensure this branch builds standlone also.
Sorry for the noise on the first attempt.
Please pull,
Kevin
The following changes since commit e9a12e14322d7ddafeed6aec0d3fb02c0b5dc03c:
arm64: dts: add support for SM1 based SEI Robotics SEI610 (2019-08-20 13:31:11 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt64-2.1
for you to fetch changes up to b09d116b787a4ee2587a631baf2532738a5ce833:
arm64: dts: meson-sm1-sei610: add stdout-path property back (2019-08-29 16:18:38 -0700)
----------------------------------------------------------------
arm64: dts: Amlogic updates for v5.4 (round 2)
- new board: Khadas VIM3L (SM1/S905D3 SoC)
- support power domains on G12[AB] and SM1 SoCs
- DT binding fixups based on YAML schema
- add a bunch of remote control keymap
- enable DVFS on SM1/SEI610 board
----------------------------------------------------------------
Christian Hewitt (8):
soc: amlogic: meson-gx-socinfo: add A311D id
arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap
arm64: dts: meson-g12a-x96-max: add rc-x96max keymap
arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap
arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap
arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap
arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap
arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap
Jerome Brunet (3):
dt-bindings: clock: meson: add resets to the audio clock controller
arm64: dts: meson: g12a: audio clock controller provides resets
arm64: dts: meson: g12a: add reset to tdm formatters
Kevin Hilman (3):
Merge tag 'amlogic-drivers-2.1' of https://git.kernel.org/.../khilman/linux-amlogic into v5.4/dt64-2
Merge tag 'clk-meson-dt-v5.4-3' of git://github.com/BayLibre/clk-meson into v5.4/dt64-2
arm64: dts: meson: g12a-common: add VRTC
Neil Armstrong (31):
soc: amlogic: meson-clk-measure: protect measure with a mutex
soc: amlogic: meson-clk-measure: add G12B second cluster cpu clk
soc: amlogic: meson-gx-socinfo: Add SM1 and S905X3 IDs
dt-bindings: soc: amlogic: clk-measure: Add SM1 compatible
soc: amlogic: clk-measure: Add support for SM1
dt-bindings: clk: meson: add sm1 periph clock controller bindings
soc: amlogic: Add support for Everything-Else power domains controller
dt-bindings: power: add Amlogic Everything-Else power domains bindings
arm64: dts: meson: fix ethernet mac reg format
arm64: dts: meson-gx: drop the vpu dmc memory cell
arm64: dts: meson-gx: fix reset controller compatible
arm64: dts: meson-gx: fix spifc compatible
arm64: dts: meson-gx: fix watchdog compatible
arm64: dts: meson-gx: fix mhu compatible
arm64: dts: meson-gx: fix periphs bus node name
arm64: dts: meson-gxl: fix internal phy compatible
arm64: dts: meson-axg: fix MHU compatible
arm64: dts: meson-g12a: fix reset controller compatible
arm64: dts: meson-g12a-x96-max: fix compatible
arm64: dts: meson-gxbb-nanopi-k2: add missing model
arm64: dts: meson-gxbb-p201: fix snps, reset-delays-us format
arm64: dts: meson: fix boards regulators states format
arm64: dts: meson-g12: add Everything-Else power domain controller
arm64: dts: meson-sm1-sei610: add HDMI display support
arm64: dts: meson-sm1-sei610: add USB support
arm64: dts: meson-sm1-sei610: enable DVFS
arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
arm64: dts: meson-sm1-sei610: enable DVFS
arm64: dts: meson-sm1-sei610: add stdout-path property back
Nishka Dasgupta (1):
soc: amlogic: meson-gx-socinfo: Add of_node_put() before return
Documentation/devicetree/bindings/arm/amlogic.yaml | 3 +-
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt | 1 +
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 +
Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml | 93 +++++++++++++++++++
Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 1 +
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 +-
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 113 +++++++++++++----------
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 3 +-
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 9 ++
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 355 ----------------------------------------------------------------------
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 5 +-
arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 9 ++
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 19 ++--
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 1 +
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 4 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 4 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts | 4 +-
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts | 4 +-
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +-
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 360 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 70 ++++++++++++++
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 83 +++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 85 ++++++++++++++++-
drivers/soc/amlogic/Kconfig | 11 +++
drivers/soc/amlogic/Makefile | 1 +
drivers/soc/amlogic/meson-clk-measure.c | 148 ++++++++++++++++++++++++++++-
drivers/soc/amlogic/meson-ee-pwrc.c | 492 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/soc/amlogic/meson-gx-socinfo.c | 7 +-
include/dt-bindings/clock/g12a-clkc.h | 5 +
include/dt-bindings/power/meson-g12a-power.h | 13 +++
include/dt-bindings/power/meson-sm1-power.h | 18 ++++
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h | 38 ++++++++
42 files changed, 1553 insertions(+), 443 deletions(-)
create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
create mode 100644 arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
create mode 100644 drivers/soc/amlogic/meson-ee-pwrc.c
create mode 100644 include/dt-bindings/power/meson-g12a-power.h
create mode 100644 include/dt-bindings/power/meson-sm1-power.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
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^ permalink raw reply
* Re: [PATCH v5 06/10] arm64: lse: Remove unused 'alt_lse' assembly macro
From: Andrew Murray @ 2019-08-29 23:39 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190829154834.26547-7-will@kernel.org>
On Thu, Aug 29, 2019 at 04:48:30PM +0100, Will Deacon wrote:
> The 'alt_lse' assembly macro has been unused since 7c8fc35dfc32
> ("locking/atomics/arm64: Replace our atomic/lock bitop implementations
> with asm-generic").
>
> Remove it.
>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> arch/arm64/include/asm/lse.h | 22 ----------------------
> 1 file changed, 22 deletions(-)
>
> diff --git a/arch/arm64/include/asm/lse.h b/arch/arm64/include/asm/lse.h
> index 52b80846d1b7..08e818e53ed7 100644
> --- a/arch/arm64/include/asm/lse.h
> +++ b/arch/arm64/include/asm/lse.h
> @@ -10,37 +10,15 @@
> #include <asm/alternative.h>
> #include <asm/cpucaps.h>
>
> -#ifdef __ASSEMBLER__
> -
> -.arch_extension lse
> -
> -.macro alt_lse, llsc, lse
> - alternative_insn "\llsc", "\lse", ARM64_HAS_LSE_ATOMICS
> -.endm
> -
> -#else /* __ASSEMBLER__ */
> -
> __asm__(".arch_extension lse");
>
> -
> /* In-line patching at runtime */
> #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
> ALTERNATIVE(llsc, lse, ARM64_HAS_LSE_ATOMICS)
>
> -#endif /* __ASSEMBLER__ */
> #else /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
>
> -#ifdef __ASSEMBLER__
> -
> -.macro alt_lse, llsc, lse
> - \llsc
> -.endm
> -
> -#else /* __ASSEMBLER__ */
> -
> -
> #define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc
>
> -#endif /* __ASSEMBLER__ */
> #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
> #endif /* __ASM_LSE_H */
> --
> 2.11.0
>
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^ permalink raw reply
* Re: [GIT PULL] soc: amlogic: updates for v5.4 (round 2)
From: Kevin Hilman @ 2019-08-29 23:34 UTC (permalink / raw)
To: arm, soc; +Cc: linux-amlogic, linux-arm-kernel
In-Reply-To: <7ho907rfsf.fsf@baylibre.com>
OK, here's the respin (round 2.1)
The previous version was missing the bindings for the new driver, which
I had mistakenly put in the DT branch instead of here. Without the
bindings and associated headers, this branch did not build stanalone
(found by kbuild robot.)
All that is fixed by this branch.
As a result, I also needed to respin the DT64 pull. Since I moved the
bindings/header patche here, the respin of the DT64 pull will now have a
dependency merge of this branch.
Kevin
The following changes since commit 49ed86f503be80aac158a567c4cfd31cf1cd181e:
soc: amlogic: meson-gx-socinfo: Add of_node_put() before return (2019-08-20 14:53:33 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-drivers-2.1
for you to fetch changes up to bd9eccf14008732f8ea4a7efc7839911e56053a1:
dt-bindings: power: add Amlogic Everything-Else power domains bindings (2019-08-29 16:05:01 -0700)
----------------------------------------------------------------
soc: amlogic: updates for v5.4 (round 2)
- add power domain controller
----------------------------------------------------------------
Neil Armstrong (2):
soc: amlogic: Add support for Everything-Else power domains controller
dt-bindings: power: add Amlogic Everything-Else power domains bindings
Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml | 93 +++++++++++++++++++
drivers/soc/amlogic/Kconfig | 11 +++
drivers/soc/amlogic/Makefile | 1 +
drivers/soc/amlogic/meson-ee-pwrc.c | 492 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
include/dt-bindings/power/meson-g12a-power.h | 13 +++
include/dt-bindings/power/meson-sm1-power.h | 18 ++++
6 files changed, 628 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
create mode 100644 drivers/soc/amlogic/meson-ee-pwrc.c
create mode 100644 include/dt-bindings/power/meson-g12a-power.h
create mode 100644 include/dt-bindings/power/meson-sm1-power.h
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^ permalink raw reply
* linux-next: manual merge of the arm-soc tree with the arm tree
From: Stephen Rothwell @ 2019-08-29 23:27 UTC (permalink / raw)
To: Olof Johansson, Arnd Bergmann, ARM, Russell King
Cc: Nathan Chancellor, Linux Next Mailing List,
Linux Kernel Mailing List
[-- Attachment #1.1: Type: text/plain, Size: 786 bytes --]
Hi all,
Today's linux-next merge of the arm-soc tree got a conflict in:
arch/arm/mach-iop13xx/pci.c
between commit:
4af014984273 ("ARM: 8871/1: iop13xx: Simplify iop13xx_atu{e,x}_pci_status checks")
from the arm tree and commit:
59d3ae9a5bf6 ("ARM: remove Intel iop33x and iop13xx support")
from the arm-soc tree.
I fixed it up (the latter removed the file, so I did that) and can
carry the fix as necessary. This is now fixed as far as linux-next is
concerned, but any non trivial conflicts should be mentioned to your
upstream maintainer when your tree is submitted for merging. You may
also want to consider cooperating with the maintainer of the conflicting
tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* Re: [GIT PULL] arm64: dts: Amlogic updates for v5.4 (round 2)
From: Kevin Hilman @ 2019-08-29 23:04 UTC (permalink / raw)
To: arm, soc; +Cc: linux-amlogic, linux-arm-kernel
In-Reply-To: <7h4l1zrf84.fsf@baylibre.com>
Kevin Hilman <khilman@baylibre.com> writes:
> Hello Arnd, Olof,
>
> Another (final) round of 64-bit DT updates for Amlogic SoCs for v5.4.
> Highlights are in the tag description, but of note is a tag pulled in
> from the clock tree due to a handful of new clocks used for DVFS and
> power domains.
>
> Please pull.
Actually, please ignore. I messed up some dependencies between this an
the drivers PR. Will respin/resend.
Thanks,
Kevin
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^ permalink raw reply
* Re: [GIT PULL] soc: amlogic: updates for v5.4 (round 2)
From: Kevin Hilman @ 2019-08-29 23:03 UTC (permalink / raw)
To: arm, soc; +Cc: linux-amlogic, linux-arm-kernel
In-Reply-To: <7ho907rfsf.fsf@baylibre.com>
Kevin Hilman <khilman@baylibre.com> writes:
> The following changes since commit 49ed86f503be80aac158a567c4cfd31cf1cd181e:
>
> soc: amlogic: meson-gx-socinfo: Add of_node_put() before return (2019-08-20 14:53:33 -0700)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-drivers-2
>
> for you to fetch changes up to eef3c2ba0a42a6aa709828e968b64bd11f4aeb19:
>
> soc: amlogic: Add support for Everything-Else power domains controller (2019-08-28 14:29:37 -0700)
>
> ----------------------------------------------------------------
> soc: amlogic: updates for v5.4 (round 2)
> - add power domain controller
>
> ----------------------------------------------------------------
Please ignore. I messed up some dependencies. I'll respin/resend.
Kevin
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: remoteproc: stm32: add wakeup-source
From: Rob Herring @ 2019-08-29 22:57 UTC (permalink / raw)
To: Fabien Dessenne
Cc: Mark Rutland, Ohad Ben-Cohen, Alexandre Torgue, Loic Pallardy,
devicetree, Arnaud Pouliquen, linux-remoteproc, linux-kernel,
Fabien Dessenne, Bjorn Andersson, Maxime Coquelin, linux-stm32,
linux-arm-kernel
In-Reply-To: <1566833923-16718-2-git-send-email-fabien.dessenne@st.com>
On Mon, 26 Aug 2019 17:38:42 +0200, Fabien Dessenne wrote:
> Add the "wakeup-source" property: if the optional wdg interrupt is
> defined, then this property may be defined too.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
> ---
> Documentation/devicetree/bindings/remoteproc/stm32-rproc.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
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* Re: swiotlb-xen cleanups v2
From: Stefano Stabellini @ 2019-08-29 22:55 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Stefano Stabellini, Konrad Rzeszutek Wilk, x86, linux-kernel,
iommu, xen-devel, linux-arm-kernel
In-Reply-To: <20190826121944.515-1-hch@lst.de>
On Mon, 26 Aug 2019, Christoph Hellwig wrote:
> Hi Xen maintainers and friends,
>
> please take a look at this series that cleans up the parts of swiotlb-xen
> that deal with non-coherent caches.
>
> Changes since v1:
> - rewrite dma_cache_maint to be much simpler
> - improve various comments and commit logs
> - remove page-coherent.h entirely
Thanks for your work on this, it really makes the code better. I tested
it on ARM64 with a non-coherent network device and verified it works as
intended (Cadence GEM on ZynqMP).
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* Re: [PATCH v2 4/4] dt-bindings/watchdog: Add access_cs0 option for alt-boot
From: Rob Herring @ 2019-08-29 22:56 UTC (permalink / raw)
To: Ivan Mikhaylov
Cc: Mark Rutland, devicetree, Alexander Amelkin, linux-watchdog,
linux-aspeed, Andrew Jeffery, openbmc, Guenter Roeck,
linux-kernel, Joel Stanley, Wim Van Sebroeck, linux-arm-kernel
In-Reply-To: <20190826104636.19324-5-i.mikhaylov@yadro.com>
On Mon, Aug 26, 2019 at 01:46:36PM +0300, Ivan Mikhaylov wrote:
> The option for the ast2400/2500 to get access to CS0 at runtime.
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
> ---
> Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> index c5077a1f5cb3..023a9b578df6 100644
> --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> @@ -34,6 +34,13 @@ Optional properties:
> engine is responsible for this.
>
> - aspeed,alt-boot: If property is present then boot from alternate block.
> + At alternate side 'access_cs0' sysfs file provides:
What's sysfs?
Don't put Linux stuff in bindings.
> + ast2400: a way to get access to the primary SPI flash
> + chip at CS0 after booting from the alternate
> + chip at CS1.
> + ast2500: a way to restore the normal address mapping from
> + (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
> +
> - aspeed,external-signal: If property is present then signal is sent to
> external reset counter (only WDT1 and WDT2). If not
> specified no external signal is sent.
> --
> 2.20.1
>
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* Re: [PATCH 03/11] xen/arm: simplify dma_cache_maint
From: Stefano Stabellini @ 2019-08-29 22:49 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Stefano Stabellini, Konrad Rzeszutek Wilk, x86, linux-kernel,
iommu, xen-devel, linux-arm-kernel
In-Reply-To: <20190827063754.GA32045@lst.de>
On Tue, 27 Aug 2019, Christoph Hellwig wrote:
> And this was still buggy I think, it really needs some real Xen/Arm
> testing which I can't do. Hopefully better version below:
>
> --
> >From 5ad4b6e291dbb49f65480c9b769414931cbd485a Mon Sep 17 00:00:00 2001
> From: Christoph Hellwig <hch@lst.de>
> Date: Wed, 24 Jul 2019 15:26:08 +0200
> Subject: xen/arm: simplify dma_cache_maint
>
> Calculate the required operation in the caller, and pass it directly
> instead of recalculating it for each page, and use simple arithmetics
> to get from the physical address to Xen page size aligned chunks.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/arm/xen/mm.c | 61 ++++++++++++++++-------------------------------
> 1 file changed, 21 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c
> index 90574d89d0d4..2fde161733b0 100644
> --- a/arch/arm/xen/mm.c
> +++ b/arch/arm/xen/mm.c
> @@ -35,64 +35,45 @@ unsigned long xen_get_swiotlb_free_pages(unsigned int order)
> return __get_free_pages(flags, order);
> }
>
> -enum dma_cache_op {
> - DMA_UNMAP,
> - DMA_MAP,
> -};
> static bool hypercall_cflush = false;
>
> -/* functions called by SWIOTLB */
> -
> -static void dma_cache_maint(dma_addr_t handle, unsigned long offset,
> - size_t size, enum dma_data_direction dir, enum dma_cache_op op)
> +/* buffers in highmem or foreign pages cannot cross page boundaries */
> +static void dma_cache_maint(dma_addr_t handle, size_t size, u32 op)
> {
> struct gnttab_cache_flush cflush;
> - unsigned long xen_pfn;
> - size_t left = size;
>
> - xen_pfn = (handle >> XEN_PAGE_SHIFT) + offset / XEN_PAGE_SIZE;
> - offset %= XEN_PAGE_SIZE;
> + cflush.a.dev_bus_addr = handle & XEN_PAGE_MASK;
> + cflush.offset = xen_offset_in_page(handle);
> + cflush.op = op;
>
> do {
> - size_t len = left;
> -
> - /* buffers in highmem or foreign pages cannot cross page
> - * boundaries */
> - if (len + offset > XEN_PAGE_SIZE)
> - len = XEN_PAGE_SIZE - offset;
> -
> - cflush.op = 0;
> - cflush.a.dev_bus_addr = xen_pfn << XEN_PAGE_SHIFT;
> - cflush.offset = offset;
> - cflush.length = len;
> -
> - if (op == DMA_UNMAP && dir != DMA_TO_DEVICE)
> - cflush.op = GNTTAB_CACHE_INVAL;
> - if (op == DMA_MAP) {
> - if (dir == DMA_FROM_DEVICE)
> - cflush.op = GNTTAB_CACHE_INVAL;
> - else
> - cflush.op = GNTTAB_CACHE_CLEAN;
> - }
> - if (cflush.op)
> - HYPERVISOR_grant_table_op(GNTTABOP_cache_flush, &cflush, 1);
> + if (size + cflush.offset > XEN_PAGE_SIZE)
> + cflush.length = XEN_PAGE_SIZE - cflush.offset;
> + else
> + cflush.length = size;
> +
> + HYPERVISOR_grant_table_op(GNTTABOP_cache_flush, &cflush, 1);
>
> - offset = 0;
> - xen_pfn++;
> - left -= len;
> - } while (left);
> + cflush.offset = 0;
> + cflush.a.dev_bus_addr += cflush.length;
> + size -= cflush.length;
Yes that's better
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> + } while (size);
> }
>
> static void __xen_dma_page_dev_to_cpu(struct device *hwdev, dma_addr_t handle,
> size_t size, enum dma_data_direction dir)
> {
> - dma_cache_maint(handle & PAGE_MASK, handle & ~PAGE_MASK, size, dir, DMA_UNMAP);
> + if (dir != DMA_TO_DEVICE)
> + dma_cache_maint(handle, size, GNTTAB_CACHE_INVAL);
> }
>
> static void __xen_dma_page_cpu_to_dev(struct device *hwdev, dma_addr_t handle,
> size_t size, enum dma_data_direction dir)
> {
> - dma_cache_maint(handle & PAGE_MASK, handle & ~PAGE_MASK, size, dir, DMA_MAP);
> + if (dir == DMA_FROM_DEVICE)
> + dma_cache_maint(handle, size, GNTTAB_CACHE_INVAL);
> + else
> + dma_cache_maint(handle, size, GNTTAB_CACHE_CLEAN);
> }
>
> void __xen_dma_map_page(struct device *hwdev, struct page *page,
> --
> 2.20.1
>
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