* [PATCH v3 07/16] ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
MMP3 has a PJ4B with a Tauros 3 cache controller that uses CACHE_L2X0
instead, while CACHE_TAUROS2 is present on PJ4 and PJ1 (Mohawk) based
platforms only.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
arch/arm/mm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c1222c0e9fd3b..5255aa64618b5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1041,7 +1041,7 @@ endif
config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller"
- depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
+ depends on (CPU_MOHAWK || CPU_PJ4)
default y
select OUTER_CACHE
help
--
2.21.0
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* [PATCH v3 05/16] dt-bindings: phy-mmp3-usb: Add bindings
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Rob Herring, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
This is the PHY chip for USB OTG on MMP3 platform.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- Add Rob's Reviewed-by tag
Changes since v1:
- s/usbphy@/usb-phy@/
- Dropped a reference to Documentation/phy.txt
.../devicetree/bindings/phy/phy-mmp3-usb.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
new file mode 100644
index 0000000000000..7183b9102f917
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
@@ -0,0 +1,13 @@
+Marvell MMP3 USB PHY
+--------------------
+
+Required properties:
+- compatible: must be "marvell,mmp3-usb-phy"
+- #phy-cells: must be 0
+
+Example:
+ usb-phy: usb-phy@d4207000 {
+ compatible = "marvell,mmp3-usb-phy";
+ reg = <0xd4207000 0x40>;
+ #phy-cells = <0>;
+ };
--
2.21.0
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* [PATCH v3 06/16] ARM: l2c: add definition for FWA in PL310 aux register
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
The PL310 also has a "Force write allocate" bits in the Auxiliary
Control Register.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 32edfadb15935..a6d4ee86ba543 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -118,6 +118,8 @@
#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
+#define L310_AUX_CTRL_FWA_SHIFT 23
+#define L310_AUX_CTRL_FWA_MASK (3 << 23)
#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
--
2.21.0
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* [PATCH v3 03/16] dt-bindings: arm: mrvl: Document MMP3 compatible string
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Rob Herring, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
Marvel MMP3 is a successor to MMP2, containing similar peripherals with two
PJ4B cores.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- s/MMP3 SoC/MMP3 based boards/, for consistency with MMP2
- Rob's review
Changes since v1:
- Rebased on top of mrvl.txt->mrvl.yaml conversion
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index ef59d6e35bb66..818dfe6de5120 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -29,4 +29,7 @@ properties:
- enum:
- mrvl,mmp2-brownstone
- const: mrvl,mmp2
+ - description: MMP3 based boards
+ items:
+ - const: mrvl,mmp3
...
--
2.21.0
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* [PATCH v3 04/16] dt-bindings: mrvl, intc: Add a MMP3 interrupt controller
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Rob Herring, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
Similar to MMP2 one, but has an extra range for the other core. The
muxes stay the same.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- Add Rob's Reviewed-by tag
Changes since v1:
- Reformat the compatible property documentation to higlight the valid
combinations
- Drop an unneeded mmp3-intc example
.../bindings/interrupt-controller/mrvl,intc.txt | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
index 608fee15a4cfc..a0ed02725a9d7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
@@ -1,13 +1,17 @@
* Marvell MMP Interrupt controller
Required properties:
-- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
- "mrvl,mmp2-mux-intc"
+- compatible : Should be
+ "mrvl,mmp-intc" on Marvel MMP,
+ "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
+ "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
- reg : Address and length of the register set of the interrupt controller.
If the interrupt controller is intc, address and length means the range
- of the whole interrupt controller. If the interrupt controller is mux-intc,
- address and length means one register. Since address of mux-intc is in the
- range of intc. mux-intc is secondary interrupt controller.
+ of the whole interrupt controller. The "marvell,mmp3-intc" controller
+ also has a secondary range for the second CPU core. If the interrupt
+ controller is mux-intc, address and length means one register. Since
+ address of mux-intc is in the range of intc. mux-intc is secondary
+ interrupt controller.
- reg-names : Name of the register set of the interrupt controller. It's
only required in mux-intc interrupt controller.
- interrupts : Should be the port interrupt shared by mux interrupts. It's
--
2.21.0
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* [PATCH v3 01/16] dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Rob Herring, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
Add the enable method for the second PJ4B core of the Marvell MMP3 SoC.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v1:
- Add Rob's Reviewed-by tag
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index aa40b074b8648..fcba84e32e68a 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -186,6 +186,7 @@ properties:
- marvell,armada-390-smp
- marvell,armada-xp-smp
- marvell,98dx3236-smp
+ - marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
- qcom,gcc-msm8660
--
2.21.0
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* [PATCH v3 02/16] dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Lubomir Rintel, Cc : Rob Herring,
Thomas Gleixner, linux-clk, linux-arm-kernel
In-Reply-To: <20190830220743.439670-1-lkundrak@v3.sk>
Convert Marvell MMP SoC bindings to DT schema format using json-schema.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v2:
- Add mrvl,pxa910
- s/MMP2 Brownstone Board/MMP2 based boards/
Changes since v1:
- Added this patch
.../devicetree/bindings/arm/mrvl/mrvl.txt | 14 --------
.../devicetree/bindings/arm/mrvl/mrvl.yaml | 32 +++++++++++++++++++
2 files changed, 32 insertions(+), 14 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
create mode 100644 Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
deleted file mode 100644
index 951687528efb0..0000000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Marvell Platforms Device Tree Bindings
-----------------------------------------------------
-
-PXA168 Aspenite Board
-Required root node properties:
- - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
-
-PXA910 DKB Board
-Required root node properties:
- - compatible = "mrvl,pxa910-dkb";
-
-MMP2 Brownstone Board
-Required root node properties:
- - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
new file mode 100644
index 0000000000000..ef59d6e35bb66
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Platforms Device Tree Bindings
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: PXA168 Aspenite Board
+ items:
+ - enum:
+ - mrvl,pxa168-aspenite
+ - const: mrvl,pxa168
+ - description: PXA910 DKB Board
+ items:
+ - enum:
+ - mrvl,pxa910-dkb
+ - const: mrvl,pxa910
+ - description: MMP2 based boards
+ items:
+ - enum:
+ - mrvl,mmp2-brownstone
+ - const: mrvl,mmp2
+...
--
2.21.0
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* [PATCH v3 00/16] Initial support for Marvell MMP3 SoC
From: Lubomir Rintel @ 2019-08-30 22:07 UTC (permalink / raw)
To: To : Olof Johansson
Cc: Mark Rutland, devicetree, Jason Cooper, Stephen Boyd,
linux-kernel, Michael Turquette, Russell King,
Kishon Vijay Abraham I, Cc : Rob Herring, Thomas Gleixner,
linux-clk, linux-arm-kernel
Hi,
this is the third spin of a patch set that adds support for the Marvell
MMP3 processor, that I'd eventually love to see land in the Arm SoC
tree. MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet
and Dell Wyse 3020/Tx0D thin clients.
Compared to v2, there's a handful of fixes in response to reviews. Four
irqchip patches have been removed because they've been applied to the
irqchip-next tree. Details in individual patches.
Thank you
Lubo
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* Re: [PATCH 05/26] openrisc: map as uncached in ioremap
From: Stafford Horne @ 2019-08-30 21:45 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-ia64, linux-sh, linux-kernel, Guo Ren, sparclinux,
linux-riscv, Vincent Chen, linux-arch, linux-s390, linux-hexagon,
x86, linux-snps-arc, linux-xtensa, Arnd Bergmann, linux-m68k,
openrisc, Greentime Hu, linux-mtd, Guan Xuetao, linux-arm-kernel,
Michal Simek, linux-parisc, linux-mips, linux-alpha, nios2-dev
In-Reply-To: <20190830160705.GF26887@lst.de>
On Fri, Aug 30, 2019 at 06:07:05PM +0200, Christoph Hellwig wrote:
> On Fri, Aug 23, 2019 at 10:55:39PM +0900, Stafford Horne wrote:
> > On Sat, Aug 17, 2019 at 09:32:32AM +0200, Christoph Hellwig wrote:
> > > Openrisc is the only architecture not mapping ioremap as uncached,
> > > which has been the default since the Linux 2.6.x days. Switch it
> > > over to implement uncached semantics by default.
> > >
> > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > ---
> > > arch/openrisc/include/asm/io.h | 20 +++-----------------
> > > arch/openrisc/include/asm/pgtable.h | 2 +-
> > > arch/openrisc/mm/ioremap.c | 8 ++++----
> > > 3 files changed, 8 insertions(+), 22 deletions(-)
> >
> > Acked-by: Stafford Horne <shorne@gmail.com>
>
> Can you send this one to Linus for 5.4? That would help with the
> possibility to remove ioremap_nocache after that.
Sure, I will pick this up.
-Stafford
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* Re: [PATCH netdev] net: stmmac: dwmac-rk: Don't fail if phy regulator is absent
From: David Miller @ 2019-08-30 21:17 UTC (permalink / raw)
To: wens
Cc: alexandre.torgue, netdev, linux-kernel, linux-rockchip, wens,
joabreu, peppe.cavallaro, linux-arm-kernel, heiko
In-Reply-To: <20190829031724.20865-1-wens@kernel.org>
From: Chen-Yu Tsai <wens@kernel.org>
Date: Thu, 29 Aug 2019 11:17:24 +0800
> From: Chen-Yu Tsai <wens@csie.org>
>
> The devicetree binding lists the phy phy as optional. As such, the
> driver should not bail out if it can't find a regulator. Instead it
> should just skip the remaining regulator related code and continue
> on normally.
>
> Skip the remainder of phy_power_on() if a regulator supply isn't
> available. This also gets rid of the bogus return code.
>
> Fixes: 2e12f536635f ("net: stmmac: dwmac-rk: Use standard devicetree property for phy regulator")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied and queued up for -stable.
> On a separate note, maybe we should add this file to the Rockchip
> entry in MAINTAINERS?
Yes, probably.
Thanks.
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* Re: [PATCH] ARM: Emit __gnu_mcount_nc when using Clang 10.0.0 or newer
From: Nick Desaulniers @ 2019-08-30 21:15 UTC (permalink / raw)
To: Nathan Chancellor
Cc: Arnd Bergmann, Russell King, Stefan Agner, LKML,
clang-built-linux, Matthias Kaehlcke, Linux ARM
In-Reply-To: <CAKwvOdksu_L+e52awkd=ffkaasCZeBjKcFU4nvU7q7reEzF2WA@mail.gmail.com>
On Fri, Aug 30, 2019 at 2:13 PM Nick Desaulniers
<ndesaulniers@google.com> wrote:
>
> On Fri, Aug 30, 2019 at 10:28 AM Nathan Chancellor
> <natechancellor@gmail.com> wrote:
> > diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> > index a43fc753aa53..23c2bf0fbd30 100644
> > --- a/arch/arm/Makefile
> > +++ b/arch/arm/Makefile
> > @@ -115,6 +115,10 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
> > CFLAGS_ABI +=-funwind-tables
> > endif
> >
> > +ifeq ($(CONFIG_CC_IS_CLANG),y)
> > +CFLAGS_ABI +=-meabi gnu
Needs a space. `+=-`.
--
Thanks,
~Nick Desaulniers
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* Re: [PATCH] ARM: Emit __gnu_mcount_nc when using Clang 10.0.0 or newer
From: Nick Desaulniers @ 2019-08-30 21:13 UTC (permalink / raw)
To: Nathan Chancellor
Cc: Arnd Bergmann, Russell King, Stefan Agner, LKML,
clang-built-linux, Matthias Kaehlcke, Linux ARM
In-Reply-To: <20190830172824.GA119107@archlinux-threadripper>
On Fri, Aug 30, 2019 at 10:28 AM Nathan Chancellor
<natechancellor@gmail.com> wrote:
>
> On Thu, Aug 29, 2019 at 01:57:35PM -0700, Nick Desaulniers wrote:
> > On Thu, Aug 29, 2019 at 1:21 PM Stefan Agner <stefan@agner.ch> wrote:
> > >
> > > On 2019-08-29 21:34, Nathan Chancellor wrote:
> > > > On Thu, Aug 29, 2019 at 10:55:28AM -0700, Nick Desaulniers wrote:
> > > >> On Wed, Aug 28, 2019 at 11:27 PM Nathan Chancellor
> > > > I will test with or without CONFIG_AEABI like Matthias asked and I will
> > > > implement your Kconfig suggestion if it passes all of my tests. The
> > > > reason that I did it this way is because I didn't want a user to end up
> > > > with a non-booting kernel since -meabi gnu works with older versions of
> > > > clang at build time, the issue happens at boot time but the Kconfig
> > > > suggestion + cc-option should fix that.
> Disabling CONFIG_AEABI does not work with clang, I get a ton of failures
> around undefined references to __aeabi_idivmod and __aeabi_uidivmod. I
> don't think this is worth looking into given that CONFIG_AEABI is not
> selectable when CONFIG_CPU_V6 or CONFIG_CPU_V7 is selected, which is
> what we primarily care about.. We currently build and boot
> multi_v5_defconfig but it has CONFIG_AEABI set in it. As a result, I
> don't think we need to care about it with this patch.
The plan of record is to never support !CONFIG_AEBI (ie OABI) w/
Clang. See also my commit currently in linux-next:
ARM: 8875/1: Kconfig: default to AEABI w/ Clang
https://github.com/ClangBuiltLinux/linux/issues/482
so !AEABI is a moot point. If we ever changed our minds, then yes we
should additionally guard on !CONFIG_AEABI, but I feel like that's a
highly unlikely scenario at this point.
>
> This diff would also solve the issue without the need for the version
> check in the Makefile, as it is the combination of -meabi gnu and -pg
> that causes the boot issue and -pg gets added when
> CONFIG_FUNCTION_TRACER is enabled. Would that be preferred? I do not
> think adding cc-option is necessary given that we know GCC universally
> does not support this flag; there is no point in adding a small penalty
> with cc-option to either compiler.
>
> Cheers,
> Nathan
>
> ================================================
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a98c7af50bf0..440ad41e77e4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -83,7 +83,7 @@ config ARM
> select HAVE_FAST_GUP if ARM_LPAE
> select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> - select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> + select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
> select HAVE_GCC_PLUGINS
> select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
> select HAVE_IDE if PCI || ISA || PCMCIA
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index a43fc753aa53..23c2bf0fbd30 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -115,6 +115,10 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
> CFLAGS_ABI +=-funwind-tables
> endif
>
> +ifeq ($(CONFIG_CC_IS_CLANG),y)
> +CFLAGS_ABI +=-meabi gnu
> +endif
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
> +
> # Accept old syntax despite ".syntax unified"
> AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
>
--
Thanks,
~Nick Desaulniers
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 3/3] MAINTAINERS: Add an entry for the Xilinx logicPD-I2S block
From: Miquel Raynal @ 2019-08-30 21:06 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai
Cc: Mark Rutland, devicetree, alsa-devel, Michal Simek, Rob Herring,
Thomas Petazzoni, Miquel Raynal, alexandre, linux-arm-kernel
In-Reply-To: <20190830210607.22644-1-miquel.raynal@bootlin.com>
Reference the driver and and the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5bf8f340e6a8..382c33a1adef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17136,6 +17136,12 @@ L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial/uartlite.c
+XILINX LOGICPD I2S SOUND DRIVER
+M: Miquel Raynal <miquel.raynal@bootlin.com>
+S: Maintained
+F: sound/soc/xilinx/xlnx-logicpd-i2s.c
+F: Documentation/devicetree/bindings/sound/xlnx,logicpd-i2s.yaml
+
XILINX VIDEO IP CORES
M: Hyun Kwon <hyun.kwon@xilinx.com>
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 1/3] ASoC: xlnx: add Xilinx logicPD-I2S FPGA IP support
From: Miquel Raynal @ 2019-08-30 21:06 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai
Cc: Mark Rutland, devicetree, alsa-devel, Michal Simek, Rob Herring,
Thomas Petazzoni, Miquel Raynal, alexandre, linux-arm-kernel
This IP is very simple so this driver manage both the DAI and the PCM
streams, hence the presence of both components in this driver.
There are plenty available interruptions when capturing or playing
back audio that can be triggered but the only one that fits the ALSA
sound system is the XFER_DONE which is used to bound sound
periods. Other interrupts are masked. Please note that capture and
playback are not possible at the same time though.
Capture seems to work (at least it creates a file with something
inside) but I have no capture mechanism on the board to actually test
that it works correctly.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Hello,
This is my first contribution in the sound subsystem, I hope I've
understood the core but I might be entirely wrong as well, so please
do not hesitate to be critical on my choices.
Thanks,
Miquèl
sound/soc/xilinx/Kconfig | 7 +
sound/soc/xilinx/Makefile | 2 +
sound/soc/xilinx/xlnx-logicpd-i2s.c | 468 ++++++++++++++++++++++++++++
3 files changed, 477 insertions(+)
create mode 100644 sound/soc/xilinx/xlnx-logicpd-i2s.c
diff --git a/sound/soc/xilinx/Kconfig b/sound/soc/xilinx/Kconfig
index 47f606b924e4..b62cae6750b9 100644
--- a/sound/soc/xilinx/Kconfig
+++ b/sound/soc/xilinx/Kconfig
@@ -7,6 +7,13 @@ config SND_SOC_XILINX_I2S
PCM data. In receiver mode, IP receives PCM audio and
encapsulates PCM in AES format and sends AES data.
+config SND_SOC_XILINX_LOGICPD_I2S
+ tristate "Audio support for the Xilinx logicPD I2S"
+ help
+ Select this option to enable Xilinx logicPD I2S slave
+ transceiver. This enables I2S playback and capture using
+ Xilinx/logicPD IP.
+
config SND_SOC_XILINX_AUDIO_FORMATTER
tristate "Audio support for the the Xilinx audio formatter"
help
diff --git a/sound/soc/xilinx/Makefile b/sound/soc/xilinx/Makefile
index d79fd38b094b..d127c30f8fe2 100644
--- a/sound/soc/xilinx/Makefile
+++ b/sound/soc/xilinx/Makefile
@@ -1,5 +1,7 @@
snd-soc-xlnx-i2s-objs := xlnx_i2s.o
obj-$(CONFIG_SND_SOC_XILINX_I2S) += snd-soc-xlnx-i2s.o
+snd-soc-xlnx-logicpd-i2s-objs := xlnx-logicpd-i2s.o
+obj-$(CONFIG_SND_SOC_XILINX_LOGICPD_I2S) += snd-soc-xlnx-logicpd-i2s.o
snd-soc-xlnx-formatter-pcm-objs := xlnx_formatter_pcm.o
obj-$(CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER) += snd-soc-xlnx-formatter-pcm.o
snd-soc-xlnx-spdif-objs := xlnx_spdif.o
diff --git a/sound/soc/xilinx/xlnx-logicpd-i2s.c b/sound/soc/xilinx/xlnx-logicpd-i2s.c
new file mode 100644
index 000000000000..325a5bb6978a
--- /dev/null
+++ b/sound/soc/xilinx/xlnx-logicpd-i2s.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx logicPD logiI2S - I2S slave transceiver v2 support
+ *
+ * Copyright (C) 2019 Bootlin
+ *
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#define DRV_NAME "xlnx_logicpd_i2s"
+
+#define IP_VERSION 0x0
+#define PATCH_LEVEL(reg) (((reg) & GENMASK(4, 0)) + 'a')
+#define MINOR_REV(reg) (((reg) & GENMASK(10, 5)) >> 5)
+#define MAJOR_REV(reg) (((reg) & GENMASK(16, 11)) >> 11)
+#define LICENSE_TYPE(reg) (((reg) & GENMASK(18, 17)) >> 17)
+#define CONTROL_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x4 : 0x24)
+#define ENGINE_EN BIT(0)
+#define XFER_DONE BIT(1)
+#define BUFF_BASE_ADDR_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x8 : 0x28)
+#define BUFF_LEN_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0xC : 0x2C)
+#define FIFO_STAT_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x10 : 0x30)
+#define INTR_MASK_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x14 : 0x34)
+#define XFER_DONE_INTR BIT(31)
+#define INTR_STAT_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x18 : 0x38)
+#define FIFO_COUNT(reg) ((reg) >> 20)
+
+#define BYTES_TO_WORDS(n) ((n) / 4)
+
+/* Arbitrarily chosen period size */
+#define PCM_PERIOD_WORDS SZ_8K
+#define PCM_PERIOD_BYTES (PCM_PERIOD_WORDS * 4)
+/* This is the actual maximum size that can actually be moved in one chunk */
+#define PCM_BUF_WORDS (SZ_64K - 1)
+#define PCM_BUF_BYTES (PCM_BUF_WORDS * 4)
+
+struct xlnx_logicpd_i2s;
+
+/**
+ * struct xlnx_logicpd_stream - Internal stream representation
+ *
+ * @i2s: Chip data
+ * @substream: Core substream structure
+ * @period_idx: Index of the period within the circular buffer
+ */
+struct xlnx_logicpd_stream {
+ struct xlnx_logicpd_i2s *i2s;
+ struct snd_pcm_substream *substream;
+ unsigned int period_idx;
+};
+
+/**
+ * struct xlnx_logicpd_i2s - Chip structure
+ *
+ * @base: Registers base address
+ * @streams: Playback and capture streams in an array
+ */
+struct xlnx_logicpd_i2s {
+ void __iomem *base;
+ struct xlnx_logicpd_stream streams[2];
+};
+
+static struct xlnx_logicpd_i2s *substream_to_cpu_dai_chip(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+
+ return snd_soc_dai_get_drvdata(rtd->cpu_dai);
+}
+
+/* PCM methods */
+
+static const struct snd_pcm_hardware xlnx_logicpd_pcm_hardware = {
+ .info = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_HALF_DUPLEX,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .channels_min = 2,
+ .channels_max = 2,
+ .period_bytes_min = 0,
+ .period_bytes_max = PCM_PERIOD_BYTES,
+ .periods_min = 0,
+ .periods_max = -1,
+ .buffer_bytes_max = PCM_BUF_BYTES,
+};
+
+static int xlnx_logicpd_pcm_open(struct snd_pcm_substream *substream)
+{
+ struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
+ unsigned int dir = substream->stream;
+
+ snd_soc_set_runtime_hwparams(substream, &xlnx_logicpd_pcm_hardware);
+
+ i2s->streams[dir].substream = substream;
+
+ return 0;
+}
+
+static int xlnx_logicpd_pcm_close(struct snd_pcm_substream *substream)
+{
+ struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
+ unsigned int dir = substream->stream;
+
+ i2s->streams[dir].substream = NULL;
+
+ return 0;
+}
+
+static int xlnx_logicpd_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+ runtime->dma_bytes = params_buffer_bytes(params);
+
+ return 0;
+}
+
+static snd_pcm_uframes_t xlnx_logicpd_pcm_pointer(struct snd_pcm_substream *substream)
+{
+ struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
+ unsigned int dir = substream->stream;
+
+ return bytes_to_frames(runtime,
+ i2s->streams[dir].period_idx * period_sz);
+}
+
+static int xlnx_logicpd_pcm_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ return remap_pfn_range(vma, vma->vm_start,
+ substream->dma_buffer.addr >> PAGE_SHIFT,
+ vma->vm_end - vma->vm_start, vma->vm_page_prot);
+}
+
+static const struct snd_pcm_ops xlnx_logicpd_pcm_ops = {
+ .open = xlnx_logicpd_pcm_open,
+ .close = xlnx_logicpd_pcm_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = xlnx_logicpd_pcm_hw_params,
+ .pointer = xlnx_logicpd_pcm_pointer,
+ .mmap = xlnx_logicpd_pcm_mmap,
+};
+
+static int xlnx_logicpd_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_pcm *pcm = rtd->pcm;
+ struct snd_pcm_substream *substream;
+ struct snd_dma_buffer *buf;
+ int dir;
+
+ for (dir = SNDRV_PCM_STREAM_PLAYBACK;
+ dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
+ substream = pcm->streams[dir].substream;
+ if (!substream)
+ continue;
+
+ buf = &substream->dma_buffer;
+ buf->area = dma_alloc_coherent(pcm->card->dev, PCM_BUF_BYTES,
+ &buf->addr, GFP_KERNEL);
+ buf->bytes = PCM_BUF_BYTES;
+ if (!buf->area)
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void xlnx_logicpd_pcm_free(struct snd_pcm *pcm)
+{
+ struct snd_pcm_substream *substream;
+ struct snd_dma_buffer *buf;
+ int dir;
+
+ for (dir = SNDRV_PCM_STREAM_PLAYBACK;
+ dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
+ substream = pcm->streams[dir].substream;
+ if (!substream)
+ continue;
+
+ buf = &substream->dma_buffer;
+ if (!buf->area)
+ continue;
+
+ dma_free_coherent(pcm->card->dev, buf->bytes,
+ buf->area, buf->addr);
+ buf->area = NULL;
+ }
+}
+
+static const struct snd_soc_component_driver xlnx_logicpd_pcm_component = {
+ .name = "xlnx-logicp-pcm",
+ .ops = &xlnx_logicpd_pcm_ops,
+ .pcm_new = xlnx_logicpd_pcm_new,
+ .pcm_free = xlnx_logicpd_pcm_free,
+};
+
+/* DAI methods */
+
+static void xlnx_logicpd_dai_int_en(struct xlnx_logicpd_i2s *i2s, int dir)
+{
+ u32 reg;
+
+ reg = readl_relaxed(i2s->base + INTR_MASK_REG(dir));
+ reg &= ~XFER_DONE_INTR;
+ writel(reg, i2s->base + INTR_MASK_REG(dir));
+}
+
+static void xlnx_logicpd_dai_int_dis(struct xlnx_logicpd_i2s *i2s, int dir)
+{
+ u32 reg;
+
+ reg = readl_relaxed(i2s->base + INTR_MASK_REG(dir));
+ reg |= XFER_DONE_INTR;
+ writel_relaxed(reg, i2s->base + INTR_MASK_REG(dir));
+}
+
+static irqreturn_t xlnx_logicpd_dai_isr(int irq, void *dev_id)
+{
+ struct xlnx_logicpd_stream *stream = dev_id;
+ struct xlnx_logicpd_i2s *i2s = stream->i2s;
+ struct snd_pcm_substream *substream = stream->substream;
+ unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
+ unsigned int buf_sz = snd_pcm_lib_buffer_bytes(substream);
+ dma_addr_t buf_addr = substream->dma_buffer.addr;
+ unsigned int dir = substream->stream;
+ u32 reg;
+
+ /* Reading INTR_STAT deasserts the host interrupt */
+ reg = readl_relaxed(i2s->base + INTR_STAT_REG(dir));
+
+ /*
+ * When the XFER_DONE interrupt is triggered, it means the period has
+ * been entirely shifted into the FIFO. At this point, we can move the
+ * buffer pointer to the next period and ask to transfer another chunk
+ * of data. Whenever the FIFO will be at its "almost full" state (4096
+ * words minus the threshold of 100 words) the internal DMA engine will
+ * automatically restart shifting data to the FIFO until its full state.
+ * Hence, the host has up to 3996 words (in our case, 3996 frames) to
+ * serve the interrupt before an underrun that would happen, at eg.
+ * 44100Hz, after 90ms.
+ */
+ if (reg & XFER_DONE_INTR) {
+ unsigned int offset_in_buf = ++stream->period_idx * period_sz;
+
+ if (offset_in_buf >= buf_sz) {
+ stream->period_idx = 0;
+ offset_in_buf = stream->period_idx * period_sz;
+ }
+
+ /* Move on to the next period in the overall buffer */
+ writel_relaxed(buf_addr + offset_in_buf,
+ i2s->base + BUFF_BASE_ADDR_REG(dir));
+ /* The last period might be smaller, update length if needed */
+ period_sz = min(period_sz, buf_sz - offset_in_buf);
+ writel_relaxed(BYTES_TO_WORDS(period_sz),
+ i2s->base + BUFF_LEN_REG(dir));
+
+ /* Inform the PCM middle-layer */
+ snd_pcm_period_elapsed(substream);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int xlnx_logicpd_dai_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct xlnx_logicpd_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
+ dma_addr_t buf_addr = substream->dma_buffer.addr;
+ unsigned int dir = substream->stream;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ i2s->streams[dir].period_idx = 0;
+ /* Disable the other engine if enabled */
+ if (readl(i2s->base + CONTROL_REG(!dir)) & ENGINE_EN)
+ writel(0, i2s->base + CONTROL_REG(!dir));
+ /* Enable the desired engine */
+ writel_relaxed(ENGINE_EN, i2s->base + CONTROL_REG(dir));
+ /* Set the buffer start address */
+ writel_relaxed(buf_addr, i2s->base + BUFF_BASE_ADDR_REG(dir));
+ /* Enable the XFER_DONE IRQ, signaling the end of the period */
+ xlnx_logicpd_dai_int_en(i2s, dir);
+ /* Actually start the internal DMA engine */
+ writel(BYTES_TO_WORDS(period_sz),
+ i2s->base + BUFF_LEN_REG(dir));
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ /* Disable the interrupts */
+ xlnx_logicpd_dai_int_dis(i2s, dir);
+ /* Ensure the host IRQ is deasserted */
+ readl_relaxed(i2s->base + INTR_STAT_REG(dir));
+ break;
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_dai_ops xlnx_logicpd_dai_ops = {
+ .trigger = xlnx_logicpd_dai_trigger,
+};
+
+static int xlnx_logicpd_dai_probe(struct snd_soc_dai *dai)
+{
+ struct xlnx_logicpd_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+ unsigned int dir;
+
+ for (dir = SNDRV_PCM_STREAM_PLAYBACK;
+ dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
+ i2s->streams[dir].i2s = i2s;
+
+ /* Reset the transmitter/receiver engine */
+ writel_relaxed(0, i2s->base + CONTROL_REG(dir));
+ /* Mask all interrupts */
+ writel_relaxed(GENMASK(31, 0), i2s->base + INTR_MASK_REG(dir));
+ }
+
+ return 0;
+}
+
+struct snd_soc_dai_driver xlnx_logicpd_dai = {
+ .name = "xylinx-logicpd-dai",
+ .probe = xlnx_logicpd_dai_probe,
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_192000,
+ .rate_min = 8000,
+ .rate_max = 192000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ },
+ .symmetric_rates = 1,
+ .ops = &xlnx_logicpd_dai_ops,
+};
+
+static const struct snd_soc_component_driver xlnx_logicpd_i2s_component = {
+ .name = DRV_NAME,
+ .ops = &xlnx_logicpd_pcm_ops,
+};
+
+static const struct of_device_id xlnx_logicpd_i2s_of_match[] = {
+ {
+ .compatible = "xlnx,logicpd-i2s-dai",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xlnx_logicpd_i2s_of_match);
+
+static int xlnx_logicpd_i2s_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct xlnx_logicpd_i2s *i2s;
+ struct xlnx_logicpd_stream *stream;
+ int tx_irq, rx_irq, ret;
+ u32 reg;
+
+ i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
+ if (!i2s)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, i2s);
+
+ i2s->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(i2s->base))
+ return PTR_ERR(i2s->base);
+
+ stream = &i2s->streams[SNDRV_PCM_STREAM_PLAYBACK];
+ tx_irq = platform_get_irq_byname(pdev, "tx");
+ if (tx_irq > 0) {
+ ret = devm_request_irq(dev, tx_irq, xlnx_logicpd_dai_isr,
+ 0, "logicpd-i2s-tx", stream);
+ if (ret)
+ return ret;
+ } else {
+ dev_err(dev, "TX IRQ not available (%d), disabling playback\n",
+ tx_irq);
+ tx_irq = 0;
+ }
+
+ stream = &i2s->streams[SNDRV_PCM_STREAM_CAPTURE];
+ rx_irq = platform_get_irq_byname(pdev, "rx");
+ if (rx_irq > 0) {
+ ret = devm_request_irq(dev, rx_irq, xlnx_logicpd_dai_isr,
+ 0, "logicpd-i2s-rx", stream);
+ if (ret)
+ return ret;
+ } else {
+ dev_err(dev, "RX IRQ not available (%d), disabling capture\n",
+ rx_irq);
+ rx_irq = 0;
+ }
+
+ if (!tx_irq && !rx_irq)
+ return -EINVAL;
+
+ ret = devm_snd_soc_register_component(dev, &xlnx_logicpd_pcm_component,
+ NULL, 0);
+ if (ret) {
+ dev_err(dev, "cannot register PCM component (%d)\n", ret);
+ return ret;
+ }
+
+ ret = devm_snd_soc_register_component(dev, &xlnx_logicpd_i2s_component,
+ &xlnx_logicpd_dai, 1);
+ if (ret) {
+ dev_err(dev, "cannot register I2S component (%d)\n", ret);
+ return ret;
+ }
+
+ reg = readl_relaxed(i2s->base + IP_VERSION);
+ dev_info(dev, "%s DAI version %u.%u.%c (license: %s) registered\n",
+ xlnx_logicpd_dai.name,
+ (unsigned int)MAJOR_REV(reg),
+ (unsigned int)MINOR_REV(reg),
+ (char)PATCH_LEVEL(reg),
+ LICENSE_TYPE(reg) == 0 ? "source" :
+ (LICENSE_TYPE(reg) == 1 ? "eval" : "release"));
+
+ return ret;
+}
+
+static struct platform_driver xlnx_logicpd_i2s_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = xlnx_logicpd_i2s_of_match,
+ },
+ .probe = xlnx_logicpd_i2s_probe,
+};
+
+module_platform_driver(xlnx_logicpd_i2s_driver);
+
+MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
+MODULE_DESCRIPTION("Xilinx logicPD I2S module");
+MODULE_LICENSE("GPL v2");
--
2.20.1
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^ permalink raw reply related
* [PATCH 2/3] dt-bindings: sound: Add Xilinx logicPD-I2S FPGA IP bindings
From: Miquel Raynal @ 2019-08-30 21:06 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai
Cc: Mark Rutland, devicetree, alsa-devel, Michal Simek, Rob Herring,
Thomas Petazzoni, Miquel Raynal, alexandre, linux-arm-kernel
In-Reply-To: <20190830210607.22644-1-miquel.raynal@bootlin.com>
Document the logicPD I2S FPGA block bindings in yaml.
Syntax verified with dt-doc-validate.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/sound/xlnx,logicpd-i2s.yaml | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/xlnx,logicpd-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/xlnx,logicpd-i2s.yaml b/Documentation/devicetree/bindings/sound/xlnx,logicpd-i2s.yaml
new file mode 100644
index 000000000000..cbff641af199
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/xlnx,logicpd-i2s.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/xlnx,logicpd-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Device-Tree bindings for Xilinx logicPD I2S FPGA block
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+
+description: |
+ The IP supports I2S playback/capture audio. It acts as a slave and
+ clocks should come from the codec. It only supports two channels and
+ S16_LE format.
+
+properties:
+ compatible:
+ items:
+ - const: xlnx,logicpd-i2s
+
+ reg:
+ maxItems: 1
+ description:
+ Base address and size of the IP core instance.
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: tx interrupt
+ - description: rx interrupt
+ description:
+ Either the Tx interruption or the Rx interruption or both.
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupts-controller
+
+examples:
+ - |
+ logii2s_dai: logii2s-dai@43c10000 {
+ reg = <0x43c10000 0x1000>;
+ compatible = "xlnx,logicpd-i2s-dai";
+ interrupt-parent = <&intc>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx", "tx";
+ };
--
2.20.1
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^ permalink raw reply related
* Re: [PATCH] arm: fix page faults in do_alignment
From: Eric W. Biederman @ 2019-08-30 21:02 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: kstewart, gustavo, gregkh, linux-kernel, Jing Xiangfeng, linux-mm,
sakari.ailus, bhelgaas, tglx, linux-arm-kernel
In-Reply-To: <20190830203052.GG13294@shell.armlinux.org.uk>
Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
> On Fri, Aug 30, 2019 at 02:45:36PM -0500, Eric W. Biederman wrote:
>> Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
>>
>> > On Fri, Aug 30, 2019 at 09:31:17PM +0800, Jing Xiangfeng wrote:
>> >> The function do_alignment can handle misaligned address for user and
>> >> kernel space. If it is a userspace access, do_alignment may fail on
>> >> a low-memory situation, because page faults are disabled in
>> >> probe_kernel_address.
>> >>
>> >> Fix this by using __copy_from_user stead of probe_kernel_address.
>> >>
>> >> Fixes: b255188 ("ARM: fix scheduling while atomic warning in alignment handling code")
>> >> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>> >
>> > NAK.
>> >
>> > The "scheduling while atomic warning in alignment handling code" is
>> > caused by fixing up the page fault while trying to handle the
>> > mis-alignment fault generated from an instruction in atomic context.
>> >
>> > Your patch re-introduces that bug.
>>
>> And the patch that fixed scheduling while atomic apparently introduced a
>> regression. Admittedly a regression that took 6 years to track down but
>> still.
>
> Right, and given the number of years, we are trading one regression for
> a different regression. If we revert to the original code where we
> fix up, we will end up with people complaining about a "new" regression
> caused by reverting the previous fix. Follow this policy and we just
> end up constantly reverting the previous revert.
>
> The window is very small - the page in question will have had to have
> instructions read from it immediately prior to the handler being entered,
> and would have had to be made "old" before subsequently being unmapped.
> Rather than excessively complicating the code and making it even more
> inefficient (as in your patch), we could instead retry executing the
> instruction when we discover that the page is unavailable, which should
> cause the page to be paged back in.
My patch does not introduce any inefficiencies. It onlys moves the
check for user_mode up a bit. My patch did duplicate the code.
> If the page really is unavailable, the prefetch abort should cause a
> SEGV to be raised, otherwise the re-execution should replace the page.
>
> The danger to that approach is we page it back in, and it gets paged
> back out before we're able to read the instruction indefinitely.
I would think either a little code duplication or a function that looks
at user_mode(regs) and picks the appropriate kind of copy to do would be
the best way to go. Because what needs to happen in the two cases for
reading the instruction are almost completely different.
> However, as it's impossible for me to contact the submitter, anything
> I do will be poking about in the dark and without any way to validate
> that it does fix the problem, so I think apart from reviewing of any
> patches, there's not much I can do.
I didn't realize your emails to him were bouncing. That is odd. Mine
don't appear to be.
Eric
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^ permalink raw reply
* Re: [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it
From: Nick Desaulniers @ 2019-08-30 20:57 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Ard.Biesheuvel,
andrew.murray, Nathan Chancellor, Robin Murphy, Linux ARM
In-Reply-To: <20190829215347.GB2404@brain-police>
On Thu, Aug 29, 2019 at 2:53 PM Will Deacon <will@kernel.org> wrote:
>
> On Thu, Aug 29, 2019 at 10:45:57AM -0700, Nick Desaulniers wrote:
> > On Thu, Aug 29, 2019 at 9:55 AM Will Deacon <will@kernel.org> wrote:
> > >
> > > On Thu, Aug 29, 2019 at 04:48:34PM +0100, Will Deacon wrote:
> > > > diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> > > > index 95091f72228b..7fa042f5444e 100644
> > > > --- a/arch/arm64/include/asm/atomic_ll_sc.h
> > > > +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> > > > @@ -23,6 +23,10 @@ asm_ops "\n" \
> > > > #define __LL_SC_FALLBACK(asm_ops) asm_ops
> > > > #endif
> > > >
> > > > +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> > > > +#define K
> > > > +#endif
> > >
> > > Bah, I need to use something like __stringify when the constraint is used
> > > in order for this to get expanded properly. Updated diff below.
> > >
> > > Will
> >
> > Hi Will, thanks for cc'ing me on the patch set. I'd be happy to help
> > test w/ Clang. Would you mind pushing this set with the below diff to
> > a publicly available tree+branch I can pull from? (I haven't yet
> > figured out how to download multiple diff's from gmail rather than 1
> > by 1, and TBH I'd rather just use git).
>
> Sorry, of course. I should've mentioned this in the cover letter:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/atomics
>
> FWIW, I did test (defconfig + boot) with clang, but this does mean that LSE
> atomics are disabled for that configuration when asm goto is not supported.
>
> Will
Thanks, just curious if you (or anyone else on the list) has the QEMU
recipe handy to test on a virtual machine that has ll/sc instructions,
and one that does not? I'm guessing testing the default machine would
not exercise the code path where these instructions have been added?
--
Thanks,
~Nick Desaulniers
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^ permalink raw reply
* Re: [PATCH] Revert "asm-generic: Remove unneeded __ARCH_WANT_SYS_LLSEEK macro"
From: Arnd Bergmann @ 2019-08-30 20:37 UTC (permalink / raw)
To: Michal Suchánek
Cc: Rich Felker, Linux-sh list, Benjamin Herrenschmidt,
Heiko Carstens, linux-mips, James E.J. Bottomley, Max Filippov,
Guo Ren, H. Peter Anvin, sparclinux, Vincenzo Frascino,
Will Deacon, linux-arch, linux-s390, Yoshinori Sato,
Michael Ellerman, Helge Deller, the arch/x86 maintainers,
Russell King, Christian Borntraeger, Ingo Molnar,
Geert Uytterhoeven, Linux ARM, Catalin Marinas, James Hogan,
Firoz Khan, linux-xtensa, Vasily Gorbik, linux-m68k,
Borislav Petkov, Alexander Viro, David Howells, Thomas Gleixner,
Christian Brauner, Chris Zankel, Michal Simek, Parisc List,
Greg Kroah-Hartman, Linux Kernel Mailing List, Ralf Baechle,
Paul Burton, Linux FS-devel Mailing List, Paul Mackerras,
linuxppc-dev, David S. Miller
In-Reply-To: <20190830221315.4b3b8a74@kitsune.suse.cz>
On Fri, Aug 30, 2019 at 10:13 PM Michal Suchánek <msuchanek@suse.de> wrote:
> On Fri, 30 Aug 2019 21:54:43 +0200
> Arnd Bergmann <arnd@arndb.de> wrote:
> > > index 5bbf587f5bc1..2f3c4bb138c4 100644
> > > --- a/fs/read_write.c
> > > +++ b/fs/read_write.c
> > > @@ -331,7 +331,7 @@ COMPAT_SYSCALL_DEFINE3(lseek, unsigned int, fd, compat_off_t, offset, unsigned i
> > > }
> > > #endif
> > >
> > > -#if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT)
> > > +#ifdef __ARCH_WANT_SYS_LLSEEK
> > > SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned long, offset_high,
> > > unsigned long, offset_low, loff_t __user *, result,
> > > unsigned int, whence)
> >
> > However, only reverting the patch will now break all newly added
> > 32-bit architectures that don't define __ARCH_WANT_SYS_LLSEEK:
> > at least nds32 and riscv32 come to mind, not sure if there is another.
>
> AFAICT nds32 never had the syscall. Its headers were added without
> __ARCH_WANT_SYS_LLSEEK before the define was removed.
nds32 got it from include/asm-generic/unistd.h
Arnd
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^ permalink raw reply
* Re: [PATCH] arm: fix page faults in do_alignment
From: Russell King - ARM Linux admin @ 2019-08-30 20:30 UTC (permalink / raw)
To: Eric W. Biederman
Cc: kstewart, gustavo, gregkh, linux-kernel, Jing Xiangfeng, linux-mm,
sakari.ailus, bhelgaas, tglx, linux-arm-kernel
In-Reply-To: <87d0gmwi73.fsf@x220.int.ebiederm.org>
On Fri, Aug 30, 2019 at 02:45:36PM -0500, Eric W. Biederman wrote:
> Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
>
> > On Fri, Aug 30, 2019 at 09:31:17PM +0800, Jing Xiangfeng wrote:
> >> The function do_alignment can handle misaligned address for user and
> >> kernel space. If it is a userspace access, do_alignment may fail on
> >> a low-memory situation, because page faults are disabled in
> >> probe_kernel_address.
> >>
> >> Fix this by using __copy_from_user stead of probe_kernel_address.
> >>
> >> Fixes: b255188 ("ARM: fix scheduling while atomic warning in alignment handling code")
> >> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
> >
> > NAK.
> >
> > The "scheduling while atomic warning in alignment handling code" is
> > caused by fixing up the page fault while trying to handle the
> > mis-alignment fault generated from an instruction in atomic context.
> >
> > Your patch re-introduces that bug.
>
> And the patch that fixed scheduling while atomic apparently introduced a
> regression. Admittedly a regression that took 6 years to track down but
> still.
Right, and given the number of years, we are trading one regression for
a different regression. If we revert to the original code where we
fix up, we will end up with people complaining about a "new" regression
caused by reverting the previous fix. Follow this policy and we just
end up constantly reverting the previous revert.
The window is very small - the page in question will have had to have
instructions read from it immediately prior to the handler being entered,
and would have had to be made "old" before subsequently being unmapped.
Rather than excessively complicating the code and making it even more
inefficient (as in your patch), we could instead retry executing the
instruction when we discover that the page is unavailable, which should
cause the page to be paged back in.
If the page really is unavailable, the prefetch abort should cause a
SEGV to be raised, otherwise the re-execution should replace the page.
The danger to that approach is we page it back in, and it gets paged
back out before we're able to read the instruction indefinitely.
However, as it's impossible for me to contact the submitter, anything
I do will be poking about in the dark and without any way to validate
that it does fix the problem, so I think apart from reviewing of any
patches, there's not much I can do.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
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^ permalink raw reply
* Re: [PATCH] Revert "asm-generic: Remove unneeded __ARCH_WANT_SYS_LLSEEK macro"
From: Michal Suchánek @ 2019-08-30 20:13 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rich Felker, Linux-sh list, Benjamin Herrenschmidt,
Heiko Carstens, linux-mips, James E.J. Bottomley, Max Filippov,
Guo Ren, H. Peter Anvin, sparclinux, Vincenzo Frascino,
Will Deacon, linux-arch, linux-s390, Yoshinori Sato,
Michael Ellerman, Helge Deller, the arch/x86 maintainers,
Russell King, Christian Borntraeger, Ingo Molnar,
Geert Uytterhoeven, Linux ARM, Catalin Marinas, James Hogan,
Firoz Khan, linux-xtensa, Vasily Gorbik, linux-m68k,
Borislav Petkov, Alexander Viro, David Howells, Thomas Gleixner,
Christian Brauner, Chris Zankel, Michal Simek, Parisc List,
Greg Kroah-Hartman, Linux Kernel Mailing List, Ralf Baechle,
Paul Burton, Linux FS-devel Mailing List, Paul Mackerras,
linuxppc-dev, David S. Miller
In-Reply-To: <CAK8P3a16=ktJm5B3c5-XS7SqVuHBY5+E2FwVUqbdOdWK-AUgSA@mail.gmail.com>
On Fri, 30 Aug 2019 21:54:43 +0200
Arnd Bergmann <arnd@arndb.de> wrote:
> On Fri, Aug 30, 2019 at 9:46 PM Michal Suchanek <msuchanek@suse.de> wrote:
> >
> > This reverts commit caf6f9c8a326cffd1d4b3ff3f1cfba75d159d70b.
> >
> > Maybe it was needed after all.
> >
> > When CONFIG_COMPAT is disabled on ppc64 the kernel does not build.
> >
> > There is resistance to both removing the llseek syscall from the 64bit
> > syscall tables and building the llseek interface unconditionally.
> >
> > Link: https://lore.kernel.org/lkml/20190828151552.GA16855@infradead.org/
> > Link: https://lore.kernel.org/lkml/20190829214319.498c7de2@naga/
> >
> > Signed-off-by: Michal Suchanek <msuchanek@suse.de>
>
> This seems like the right idea in principle.
>
> > index 5bbf587f5bc1..2f3c4bb138c4 100644
> > --- a/fs/read_write.c
> > +++ b/fs/read_write.c
> > @@ -331,7 +331,7 @@ COMPAT_SYSCALL_DEFINE3(lseek, unsigned int, fd, compat_off_t, offset, unsigned i
> > }
> > #endif
> >
> > -#if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT)
> > +#ifdef __ARCH_WANT_SYS_LLSEEK
> > SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned long, offset_high,
> > unsigned long, offset_low, loff_t __user *, result,
> > unsigned int, whence)
>
> However, only reverting the patch will now break all newly added
> 32-bit architectures that don't define __ARCH_WANT_SYS_LLSEEK:
> at least nds32 and riscv32 come to mind, not sure if there is another.
AFAICT nds32 never had the syscall. Its headers were added without
__ARCH_WANT_SYS_LLSEEK before the define was removed.
The new architecture csky should be handled.
>
> I think the easiest way however would be to combine the two checks
> above and make it
>
> #if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT) ||
> defined(__ARCH_WANT_SYS_LLSEEK)
>
> and then only set __ARCH_WANT_SYS_LLSEEK for powerpc.
Yes, that limits the use of __ARCH_WANT_SYS_LLSEEK, does not require
resurrecting the old headers, and may fix some architectures like nds32
that forgot to add it.
Thanks
Michal
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^ permalink raw reply
* Re: [PATCH] Revert "asm-generic: Remove unneeded __ARCH_WANT_SYS_LLSEEK macro"
From: Arnd Bergmann @ 2019-08-30 19:54 UTC (permalink / raw)
To: Michal Suchanek
Cc: Rich Felker, Linux-sh list, Benjamin Herrenschmidt,
Heiko Carstens, linux-mips, James E.J. Bottomley, Max Filippov,
Guo Ren, H. Peter Anvin, sparclinux, Vincenzo Frascino,
Will Deacon, linux-arch, linux-s390, Yoshinori Sato,
Michael Ellerman, Helge Deller, the arch/x86 maintainers,
Russell King, Christian Borntraeger, Ingo Molnar,
Geert Uytterhoeven, Linux ARM, Catalin Marinas, James Hogan,
Firoz Khan, linux-xtensa, Vasily Gorbik, linux-m68k,
Borislav Petkov, Alexander Viro, David Howells, Thomas Gleixner,
Christian Brauner, Chris Zankel, Michal Simek, Parisc List,
Greg Kroah-Hartman, Linux Kernel Mailing List, Ralf Baechle,
Paul Burton, Linux FS-devel Mailing List, Paul Mackerras,
linuxppc-dev, David S. Miller
In-Reply-To: <20190830194651.31043-1-msuchanek@suse.de>
On Fri, Aug 30, 2019 at 9:46 PM Michal Suchanek <msuchanek@suse.de> wrote:
>
> This reverts commit caf6f9c8a326cffd1d4b3ff3f1cfba75d159d70b.
>
> Maybe it was needed after all.
>
> When CONFIG_COMPAT is disabled on ppc64 the kernel does not build.
>
> There is resistance to both removing the llseek syscall from the 64bit
> syscall tables and building the llseek interface unconditionally.
>
> Link: https://lore.kernel.org/lkml/20190828151552.GA16855@infradead.org/
> Link: https://lore.kernel.org/lkml/20190829214319.498c7de2@naga/
>
> Signed-off-by: Michal Suchanek <msuchanek@suse.de>
This seems like the right idea in principle.
> index 5bbf587f5bc1..2f3c4bb138c4 100644
> --- a/fs/read_write.c
> +++ b/fs/read_write.c
> @@ -331,7 +331,7 @@ COMPAT_SYSCALL_DEFINE3(lseek, unsigned int, fd, compat_off_t, offset, unsigned i
> }
> #endif
>
> -#if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT)
> +#ifdef __ARCH_WANT_SYS_LLSEEK
> SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned long, offset_high,
> unsigned long, offset_low, loff_t __user *, result,
> unsigned int, whence)
However, only reverting the patch will now break all newly added
32-bit architectures that don't define __ARCH_WANT_SYS_LLSEEK:
at least nds32 and riscv32 come to mind, not sure if there is another.
I think the easiest way however would be to combine the two checks
above and make it
#if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT) ||
defined(__ARCH_WANT_SYS_LLSEEK)
and then only set __ARCH_WANT_SYS_LLSEEK for powerpc.
Arnd
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^ permalink raw reply
* Re: [PATCH 14/26] asm-generic: don't provide __ioremap
From: Arnd Bergmann @ 2019-08-30 19:47 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Cc@lst.de:Paul Walmsley <paul.walmsley@sifive.com>, Guo Ren <guoren@kernel.org>, Michal Simek <monstr@monstr.eu>, Greentime Hu <green.hu@gmail.com>, Vincent Chen <deanbo422@gmail.com>, Guan Xuetao <gxt@pku.edu.cn>, x86@kernel.org, linux-arch@vger.kernel.org, linux-s390@vger.kernel.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-xtensa@linux-xtensa.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, linux-mtd@lists.infradead.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, nios2-dev@lists.rocketboards.org, linux-riscv@lists.infradead.org, linux-snps-arc@lists.infradead.org,
In-Reply-To: <20190830160404.GA26887@lst.de>
On Fri, Aug 30, 2019 at 6:04 PM Christoph Hellwig <hch@lst.de> wrote:
>
> Arnd, can you consider this patch for asm-generic for 5.4? I don't
> think I'll be able to feed the actual generic ioremap implementation
> to Linus this merge window, but if we can get as many patches as
> possible in through their maintainer trees that would make my life
> much easier.
Applied now, I missed it earlier when I was on vacation.
Arnd
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^ permalink raw reply
* [PATCH] Revert "asm-generic: Remove unneeded __ARCH_WANT_SYS_LLSEEK macro"
From: Michal Suchanek @ 2019-08-30 19:46 UTC (permalink / raw)
To: linux-arch
Cc: Rich Felker, linux-sh, Benjamin Herrenschmidt, Heiko Carstens,
linux-mips, James E.J. Bottomley, Max Filippov, Guo Ren,
H. Peter Anvin, sparclinux, Vincenzo Frascino, Will Deacon,
linux-s390, Arnd Bergmann, Yoshinori Sato, Michael Ellerman,
Helge Deller, x86, Russell King, Christian Borntraeger,
Ingo Molnar, Geert Uytterhoeven, linux-arm-kernel,
Catalin Marinas, James Hogan, Firoz Khan, Michal Suchanek,
linux-xtensa, Vasily Gorbik, linux-m68k, Borislav Petkov,
Alexander Viro, David Howells, Thomas Gleixner, Christian Brauner,
Chris Zankel, Michal Simek, linux-parisc, Greg Kroah-Hartman,
linux-kernel, Ralf Baechle, Paul Burton, linux-fsdevel,
Paul Mackerras, linuxppc-dev, David S. Miller
In-Reply-To: <bb6d25c6baae315d05b571d8c508f0e8fa90027c.1567188299.git.msuchanek@suse.de>
This reverts commit caf6f9c8a326cffd1d4b3ff3f1cfba75d159d70b.
Maybe it was needed after all.
When CONFIG_COMPAT is disabled on ppc64 the kernel does not build.
There is resistance to both removing the llseek syscall from the 64bit
syscall tables and building the llseek interface unconditionally.
Link: https://lore.kernel.org/lkml/20190828151552.GA16855@infradead.org/
Link: https://lore.kernel.org/lkml/20190829214319.498c7de2@naga/
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
---
arch/arm/include/asm/unistd.h | 1 +
arch/arm64/include/asm/unistd.h | 1 +
arch/csky/include/asm/unistd.h | 2 +-
arch/m68k/include/asm/unistd.h | 1 +
arch/microblaze/include/asm/unistd.h | 1 +
arch/mips/include/asm/unistd.h | 1 +
arch/parisc/include/asm/unistd.h | 1 +
arch/powerpc/include/asm/unistd.h | 1 +
arch/s390/include/asm/unistd.h | 1 +
arch/sh/include/asm/unistd.h | 1 +
arch/sparc/include/asm/unistd.h | 1 +
arch/x86/include/asm/unistd.h | 1 +
arch/xtensa/include/asm/unistd.h | 1 +
fs/read_write.c | 2 +-
include/asm-generic/unistd.h | 12 ++++++++++++
15 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 include/asm-generic/unistd.h
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 3676e82cf95c..e35ec8100a21 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -18,6 +18,7 @@
#define __ARCH_WANT_SYS_GETHOSTNAME
#define __ARCH_WANT_SYS_PAUSE
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_SIGPENDING
#define __ARCH_WANT_SYS_SIGPROCMASK
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index 2629a68b8724..2c9d8d91e347 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -7,6 +7,7 @@
#define __ARCH_WANT_SYS_GETHOSTNAME
#define __ARCH_WANT_SYS_PAUSE
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_SIGPENDING
#define __ARCH_WANT_SYS_SIGPROCMASK
diff --git a/arch/csky/include/asm/unistd.h b/arch/csky/include/asm/unistd.h
index da7a18295615..bee8ba8309e7 100644
--- a/arch/csky/include/asm/unistd.h
+++ b/arch/csky/include/asm/unistd.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
-#include <uapi/asm/unistd.h>
+#include <asm-generic/unistd.h>
#define NR_syscalls (__NR_syscalls)
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 2e0047cf86f8..54c04eb4495a 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -21,6 +21,7 @@
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLD_GETRLIMIT
#define __ARCH_WANT_SYS_OLD_MMAP
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index d79d35ac6253..c5fcbce1f997 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -27,6 +27,7 @@
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
/* #define __ARCH_WANT_SYS_OLD_GETRLIMIT */
#define __ARCH_WANT_SYS_OLDUMOUNT
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 071053ece677..8e8c7cab95ca 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -38,6 +38,7 @@
#define __ARCH_WANT_SYS_WAITPID
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLD_UNAME
#define __ARCH_WANT_SYS_OLDUMOUNT
diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h
index cd438e4150f6..29bd46381f2e 100644
--- a/arch/parisc/include/asm/unistd.h
+++ b/arch/parisc/include/asm/unistd.h
@@ -159,6 +159,7 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLDUMOUNT
#define __ARCH_WANT_SYS_SIGPENDING
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index b0720c7c3fcf..700fcdac2e3c 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -31,6 +31,7 @@
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLD_GETRLIMIT
#define __ARCH_WANT_SYS_OLD_UNAME
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index 9e9f75ef046a..52e9e2fe3768 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -21,6 +21,7 @@
#define __ARCH_WANT_SYS_IPC
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLD_GETRLIMIT
#define __ARCH_WANT_SYS_OLD_MMAP
diff --git a/arch/sh/include/asm/unistd.h b/arch/sh/include/asm/unistd.h
index 9c7d9d9999c6..4899b6b72f1a 100644
--- a/arch/sh/include/asm/unistd.h
+++ b/arch/sh/include/asm/unistd.h
@@ -22,6 +22,7 @@
# define __ARCH_WANT_SYS_SOCKETCALL
# define __ARCH_WANT_SYS_FADVISE64
# define __ARCH_WANT_SYS_GETPGRP
+# define __ARCH_WANT_SYS_LLSEEK
# define __ARCH_WANT_SYS_NICE
# define __ARCH_WANT_SYS_OLD_GETRLIMIT
# define __ARCH_WANT_SYS_OLD_UNAME
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index 1e66278ba4a5..7edfc208e2af 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -36,6 +36,7 @@
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLDUMOUNT
#define __ARCH_WANT_SYS_SIGPENDING
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 097589753fec..9e5a1748b4ce 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -39,6 +39,7 @@
# define __ARCH_WANT_SYS_FADVISE64
# define __ARCH_WANT_SYS_GETHOSTNAME
# define __ARCH_WANT_SYS_GETPGRP
+# define __ARCH_WANT_SYS_LLSEEK
# define __ARCH_WANT_SYS_NICE
# define __ARCH_WANT_SYS_OLDUMOUNT
# define __ARCH_WANT_SYS_OLD_GETRLIMIT
diff --git a/arch/xtensa/include/asm/unistd.h b/arch/xtensa/include/asm/unistd.h
index b52236245e51..9fd236a7825e 100644
--- a/arch/xtensa/include/asm/unistd.h
+++ b/arch/xtensa/include/asm/unistd.h
@@ -9,6 +9,7 @@
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_STAT64
#define __ARCH_WANT_SYS_UTIME32
+#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_GETPGRP
#define NR_syscalls __NR_syscalls
diff --git a/fs/read_write.c b/fs/read_write.c
index 5bbf587f5bc1..2f3c4bb138c4 100644
--- a/fs/read_write.c
+++ b/fs/read_write.c
@@ -331,7 +331,7 @@ COMPAT_SYSCALL_DEFINE3(lseek, unsigned int, fd, compat_off_t, offset, unsigned i
}
#endif
-#if !defined(CONFIG_64BIT) || defined(CONFIG_COMPAT)
+#ifdef __ARCH_WANT_SYS_LLSEEK
SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned long, offset_high,
unsigned long, offset_low, loff_t __user *, result,
unsigned int, whence)
diff --git a/include/asm-generic/unistd.h b/include/asm-generic/unistd.h
new file mode 100644
index 000000000000..ea74eca8463f
--- /dev/null
+++ b/include/asm-generic/unistd.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <uapi/asm-generic/unistd.h>
+#include <linux/export.h>
+
+/*
+ * These are required system calls, we should
+ * invert the logic eventually and let them
+ * be selected by default.
+ */
+#if __BITS_PER_LONG == 32
+#define __ARCH_WANT_SYS_LLSEEK
+#endif
--
2.22.0
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^ permalink raw reply related
* Re: [PATCH] arm: fix page faults in do_alignment
From: Eric W. Biederman @ 2019-08-30 19:45 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: kstewart, gustavo, gregkh, linux-kernel, Jing Xiangfeng, linux-mm,
sakari.ailus, bhelgaas, tglx, linux-arm-kernel
In-Reply-To: <20190830133522.GZ13294@shell.armlinux.org.uk>
Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
> On Fri, Aug 30, 2019 at 09:31:17PM +0800, Jing Xiangfeng wrote:
>> The function do_alignment can handle misaligned address for user and
>> kernel space. If it is a userspace access, do_alignment may fail on
>> a low-memory situation, because page faults are disabled in
>> probe_kernel_address.
>>
>> Fix this by using __copy_from_user stead of probe_kernel_address.
>>
>> Fixes: b255188 ("ARM: fix scheduling while atomic warning in alignment handling code")
>> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
>
> NAK.
>
> The "scheduling while atomic warning in alignment handling code" is
> caused by fixing up the page fault while trying to handle the
> mis-alignment fault generated from an instruction in atomic context.
>
> Your patch re-introduces that bug.
And the patch that fixed scheduling while atomic apparently introduced a
regression. Admittedly a regression that took 6 years to track down but
still.
So it looks like the code needs to do something like:
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 04b36436cbc0..5e2b8623851e 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -784,6 +784,9 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
instrptr = instruction_pointer(regs);
+ if (user_mode(regs))
+ goto user;
+
if (thumb_mode(regs)) {
u16 *ptr = (u16 *)(instrptr & ~1);
fault = probe_kernel_address(ptr, tinstr);
@@ -933,6 +936,34 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
return 1;
user:
+ if (thumb_mode(regs)) {
+ u16 *ptr = (u16 *)(instrptr & ~1);
+ fault = get_user(tinstr, ptr);
+ tinstr = __mem_to_opcode_thumb16(tinstr);
+ if (!fault) {
+ if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
+ IS_T32(tinstr)) {
+ /* Thumb-2 32-bit */
+ u16 tinst2 = 0;
+ fault = get_user(ptr + 1, tinst2);
+ tinst2 = __mem_to_opcode_thumb16(tinst2);
+ instr = __opcode_thumb32_compose(tinstr, tinst2);
+ thumb2_32b = 1;
+ } else {
+ isize = 2;
+ instr = thumb2arm(tinstr);
+ }
+ }
+ } else {
+ fault = get_user(instr, (u32*)instrptr);
+ instr = __mem_to_opcode_arm(instr);
+ }
+
+ if (fault) {
+ type = TYPE_FAULT;
+ goto bad_or_fault;
+ }
+
ai_user += 1;
if (ai_usermode & UM_WARN)
Eric
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^ permalink raw reply related
* Re: [PATCH] arm64: use x22 to save boot exception level
From: Andrew F. Davis @ 2019-08-30 19:23 UTC (permalink / raw)
To: Mark Rutland
Cc: Nishanth Menon, Matthew Leach, Catalin Marinas, linux-kernel,
Tero Kristo, Will Deacon, linux-arm-kernel
In-Reply-To: <20190829094720.GA44575@lakrids.cambridge.arm.com>
On 8/29/19 5:47 AM, Mark Rutland wrote:
> Hi Andrew,
>
> On Wed, Aug 28, 2019 at 01:33:18PM -0400, Andrew F. Davis wrote:
>> The exception level in which the kernel was entered needs to be saved for
>> later. We do this by writing the exception level to memory. As this data
>> is written with the MMU/cache off it will bypass any cache, after this we
>> invalidate the address so that later reads from cacheable mappings do not
>> read a stale cache line. The side effect of this invalidate is any
>> existing cache line for this address in the same coherency domain will be
>> cleaned and written into memory, possibly overwriting the data we just
>> wrote. As this memory is treated as cacheable by already running cores it
>> on not architecturally safe to perform any non-caching accesses to this
>> memory anyway.
>
> Are you seeing an issue in practice here, or is this something that
> you've found by inspection?
>
We are seeing an actual issue. And I do have a good idea what is causing
it, let me answer your questions on the system then I'll explain below.
> If this is an issue in practice, can you tell me more about the system,
> i.e.
>
> - Which CPU models do you see this with?
A53s
> - Do you see this with the boot CPU, secondaries, or both?
Both
> - Do you have a system-level cache? If so, which model?
Yes, Custom design, Datasheet has some more details if needed:
http://www.ti.com/product/AM6548
> - Do you see this on bare-metal?
Not tested
> - Do you see this under a hypervisor? If so, which hypervisor?
>
Not tested
> We place __boot_cpu_mode in the .mmuoff.data.write section, which is
> only written with the MMU off (i.e. with non-cacheable accesses), such
> that the cached copy should always be clean and shouldn't be written
> back. Your description sounds like you're seeing a write-back, which is
> surprising and may indicate a bug elsewhere.
>
> Depending on what exactly you're seeing, this could also be an issue for
> __early_cpu_boot_status and the early page table creation, so I'd like
> to understand that better.
>
We are seeing is a write-back from L3 cache. Our bootloader writes the
kernel image with caches on, then after turning off caching but before
handing off to Linux it clean/invalidates all cache lines by set/way.
This cleans out the L1/L2 but leaves dirty lines in L3. Our platform
doesn't really have a good way to clean L3 as it only provides cache
maintenance operations by VA, not by line, so we would need to clean
every VA address manually..
Also want to point out, although this isn't a problem for most platforms
what this code does here, with writing to a location as non-cacheable,
is not architecturally safe as the running cores that do the reads have
this section marked as cacheable when they read, therefor you have
mismatched attributes. When this happens like this according to the ARM
ARM we should do a cache invalidate after the write *and* before the
read, which we do not do.
I would like to work this fix from the U-Boot side also, but in parallel
I would like to reduce the mismatched attributes as much as possible on
the kernel side like done here. So yes, we still will have issue with
__early_cpu_boot_status, but that only seems to be needed in the failure
to boot case, I'd like to fix that up as well at some later point.
As for early page table, since U-Boot doesn't write anything to those
addresses (__boot_cpu_mode is in the data section and so written by the
loader), they seem to be safe for now (I can break them by writing to
all memory locations to dirty up the caches).
Thanks,
Andrew
> Thanks,
> Mark.
>
>> Lets avoid these issues altogether by moving the writing of the boot
>> exception level to after MMU/caching has been enabled. Saving the boot
>> state in unused register x22 until we can safely and coherently write out
>> this data.
>>
>> As the data is not written with the MMU off anymore we move the variable
>> definition out of this section and into a regular C code data section.
>>
>> Signed-off-by: Andrew F. Davis <afd@ti.com>
>> ---
>> arch/arm64/kernel/head.S | 31 +++++++++++--------------------
>> arch/arm64/kernel/smp.c | 10 ++++++++++
>> 2 files changed, 21 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
>> index 2cdacd1c141b..4c71493742c5 100644
>> --- a/arch/arm64/kernel/head.S
>> +++ b/arch/arm64/kernel/head.S
>> @@ -99,6 +99,7 @@ pe_header:
>> *
>> * Register Scope Purpose
>> * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
>> + * x22 stext() .. start_kernel() exception level core was booted
>> * x23 stext() .. start_kernel() physical misalignment/KASLR offset
>> * x28 __create_page_tables() callee preserved temp register
>> * x19/x20 __primary_switch() callee preserved temp registers
>> @@ -108,7 +109,6 @@ ENTRY(stext)
>> bl el2_setup // Drop to EL1, w0=cpu_boot_mode
>> adrp x23, __PHYS_OFFSET
>> and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
>> - bl set_cpu_boot_mode_flag
>> bl __create_page_tables
>> /*
>> * The following calls CPU setup code, see arch/arm64/mm/proc.S for
>> @@ -428,6 +428,8 @@ __primary_switched:
>> sub x4, x4, x0 // the kernel virtual and
>> str_l x4, kimage_voffset, x5 // physical mappings
>>
>> + bl set_cpu_boot_mode_flag
>> +
>> // Clear BSS
>> adr_l x0, __bss_start
>> mov x1, xzr
>> @@ -470,7 +472,7 @@ EXPORT_SYMBOL(kimage_vaddr)
>> * If we're fortunate enough to boot at EL2, ensure that the world is
>> * sane before dropping to EL1.
>> *
>> - * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
>> + * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w22 if
>> * booted in EL1 or EL2 respectively.
>> */
>> ENTRY(el2_setup)
>> @@ -480,7 +482,7 @@ ENTRY(el2_setup)
>> b.eq 1f
>> mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
>> msr sctlr_el1, x0
>> - mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
>> + mov w22, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
>> isb
>> ret
>>
>> @@ -593,7 +595,7 @@ set_hcr:
>>
>> cbz x2, install_el2_stub
>>
>> - mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
>> + mov w22, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
>> isb
>> ret
>>
>> @@ -632,7 +634,7 @@ install_el2_stub:
>> PSR_MODE_EL1h)
>> msr spsr_el2, x0
>> msr elr_el2, lr
>> - mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
>> + mov w22, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
>> eret
>> ENDPROC(el2_setup)
>>
>> @@ -642,12 +644,10 @@ ENDPROC(el2_setup)
>> */
>> set_cpu_boot_mode_flag:
>> adr_l x1, __boot_cpu_mode
>> - cmp w0, #BOOT_CPU_MODE_EL2
>> + cmp w22, #BOOT_CPU_MODE_EL2
>> b.ne 1f
>> - add x1, x1, #4
>> -1: str w0, [x1] // This CPU has booted in EL1
>> - dmb sy
>> - dc ivac, x1 // Invalidate potentially stale cache line
>> + add x1, x1, #4 // This CPU has booted in EL2
>> +1: str w22, [x1]
>> ret
>> ENDPROC(set_cpu_boot_mode_flag)
>>
>> @@ -658,16 +658,7 @@ ENDPROC(set_cpu_boot_mode_flag)
>> * sufficient alignment that the CWG doesn't overlap another section.
>> */
>> .pushsection ".mmuoff.data.write", "aw"
>> -/*
>> - * We need to find out the CPU boot mode long after boot, so we need to
>> - * store it in a writable variable.
>> - *
>> - * This is not in .bss, because we set it sufficiently early that the boot-time
>> - * zeroing of .bss would clobber it.
>> - */
>> -ENTRY(__boot_cpu_mode)
>> - .long BOOT_CPU_MODE_EL2
>> - .long BOOT_CPU_MODE_EL1
>> +
>> /*
>> * The booting CPU updates the failed status @__early_cpu_boot_status,
>> * with MMU turned off.
>> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
>> index 018a33e01b0e..66bdcaf61a46 100644
>> --- a/arch/arm64/kernel/smp.c
>> +++ b/arch/arm64/kernel/smp.c
>> @@ -65,6 +65,16 @@ struct secondary_data secondary_data;
>> /* Number of CPUs which aren't online, but looping in kernel text. */
>> int cpus_stuck_in_kernel;
>>
>> +/*
>> + * We need to find out the CPU boot mode long after boot, so we need to
>> + * store it in a writable variable in early boot. Any core started in
>> + * EL1 will write that to the first location, EL2 to the second. After
>> + * all cores are started this allows us to check that all cores started
>> + * in the same mode.
>> + */
>> +u32 __boot_cpu_mode[2] = { BOOT_CPU_MODE_EL2, BOOT_CPU_MODE_EL1 };
>> +EXPORT_SYMBOL(__boot_cpu_mode);
>> +
>> enum ipi_msg_type {
>> IPI_RESCHEDULE,
>> IPI_CALL_FUNC,
>> --
>> 2.17.1
>>
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