* Re: [PATCH v2 8/9] mips: numa: check the node id consistently for mips ip27
From: Yunsheng Lin @ 2019-09-02 6:11 UTC (permalink / raw)
To: Paul Burton
Cc: dalias@libc.org, linux-sh@vger.kernel.org, peterz@infradead.org,
catalin.marinas@arm.com, dave.hansen@linux.intel.com,
heiko.carstens@de.ibm.com, linuxarm@huawei.com,
jiaxun.yang@flygoat.com, linux-mips@vger.kernel.org,
mwb@linux.vnet.ibm.com, paulus@samba.org, hpa@zytor.com,
sparclinux@vger.kernel.org, chenhc@lemote.com, will@kernel.org,
cai@lca.pw, linux-s390@vger.kernel.org,
ysato@users.sourceforge.jp, mpe@ellerman.id.au, x86@kernel.org,
rppt@linux.ibm.com, borntraeger@de.ibm.com, dledford@redhat.com,
mingo@redhat.com, jeffrey.t.kirsher@intel.com,
benh@kernel.crashing.org, jhogan@kernel.org,
nfont@linux.vnet.ibm.com, mattst88@gmail.com, len.brown@intel.com,
gor@linux.ibm.com, anshuman.khandual@arm.com, bp@alien8.de,
luto@kernel.org, tglx@linutronix.de,
naveen.n.rao@linux.vnet.ibm.com,
linux-arm-kernel@lists.infradead.org, rth@twiddle.net,
axboe@kernel.dk, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, ralf@linux-mips.org,
tbogendoerfer@suse.de, linux-alpha@vger.kernel.org,
ink@jurassic.park.msu.ru, akpm@linux-foundation.org,
robin.murphy@arm.com, davem@davemloft.net
In-Reply-To: <20190831154547.qzh6j4jwg5o5y4db@pburton-laptop>
On 2019/8/31 23:45, Paul Burton wrote:
> Hi Yunsheng,
>
> On Sat, Aug 31, 2019 at 01:58:22PM +0800, Yunsheng Lin wrote:
>> According to Section 6.2.14 from ACPI spec 6.3 [1], the setting
>> of proximity domain is optional, as below:
>>
>> This optional object is used to describe proximity domain
>> associations within a machine. _PXM evaluates to an integer
>> that identifies a device as belonging to a Proximity Domain
>> defined in the System Resource Affinity Table (SRAT).
>>
>> Since mips ip27 uses hub_data instead of node_to_cpumask_map,
>> this patch checks node id with the below case before returning
>> &hub_data(node)->h_cpus:
>> 1. if node_id >= MAX_COMPACT_NODES, return cpu_none_mask
>> 2. if node_id < 0, return cpu_online_mask
>> 3. if hub_data(node) is NULL, return cpu_online_mask
>>
>> [1] https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
>
> Similar to David's comment on the sparc patch, these systems don't use
> ACPI so I don't see from your commit message why this change would be
> relevant.
>
> This same comment applies to patch 9 too.
Thanks for pointing out.
MIPS's NUMA node id is also defined by DT?
>
> Thanks,
> Paul
>
>>
>> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
>> ---
>> arch/mips/include/asm/mach-ip27/topology.h | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
>> index 965f079..914a55a 100644
>> --- a/arch/mips/include/asm/mach-ip27/topology.h
>> +++ b/arch/mips/include/asm/mach-ip27/topology.h
>> @@ -15,9 +15,18 @@ struct cpuinfo_ip27 {
>> extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
>>
>> #define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
>> -#define cpumask_of_node(node) ((node) == -1 ? \
>> - cpu_all_mask : \
>> - &hub_data(node)->h_cpus)
>> +
>> +static inline const struct cpumask *cpumask_of_node(int node)
>> +{
>> + if (node >= MAX_COMPACT_NODES)
>> + return cpu_none_mask;
>> +
>> + if (node < 0 || !hub_data(node))
>> + return cpu_online_mask;
>> +
>> + return &hub_data(node)->h_cpus;
>> +}
>> +
>> struct pci_bus;
>> extern int pcibus_to_node(struct pci_bus *);
>>
>> --
>> 2.8.1
>>
>
> .
>
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^ permalink raw reply
* [PATCH bpf-next] arm64: bpf: optimize modulo operation
From: jerinj @ 2019-09-02 6:14 UTC (permalink / raw)
To: netdev, Daniel Borkmann, Alexei Starovoitov, Zi Shen Lim,
Catalin Marinas, Will Deacon, Martin KaFai Lau, Song Liu,
Yonghong Song, open list:BPF JIT for ARM64,
moderated list:ARM64 PORT (AARCH64 ARCHITECTURE), open list
Cc: Jerin Jacob
From: Jerin Jacob <jerinj@marvell.com>
Optimize modulo operation instruction generation by
using single MSUB instruction vs MUL followed by SUB
instruction scheme.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
arch/arm64/net/bpf_jit.h | 3 +++
arch/arm64/net/bpf_jit_comp.c | 6 ++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index cb7ab50b7657..eb73f9f72c46 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -171,6 +171,9 @@
/* Rd = Ra + Rn * Rm */
#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
+/* Rd = Ra - Rn * Rm */
+#define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
+ A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB)
/* Rd = Rn * Rm */
#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index f5b437f8a22b..cdc79de0c794 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -409,8 +409,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
break;
case BPF_MOD:
emit(A64_UDIV(is64, tmp, dst, src), ctx);
- emit(A64_MUL(is64, tmp, tmp, src), ctx);
- emit(A64_SUB(is64, dst, dst, tmp), ctx);
+ emit(A64_MSUB(is64, dst, dst, tmp, src), ctx);
break;
}
break;
@@ -516,8 +515,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
case BPF_ALU64 | BPF_MOD | BPF_K:
emit_a64_mov_i(is64, tmp2, imm, ctx);
emit(A64_UDIV(is64, tmp, dst, tmp2), ctx);
- emit(A64_MUL(is64, tmp, tmp, tmp2), ctx);
- emit(A64_SUB(is64, dst, dst, tmp), ctx);
+ emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx);
break;
case BPF_ALU | BPF_LSH | BPF_K:
case BPF_ALU64 | BPF_LSH | BPF_K:
--
2.23.0
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^ permalink raw reply related
* Re: [PATCH v4 3/4] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
From: Jorge Ramirez @ 2019-09-02 6:23 UTC (permalink / raw)
To: Stephen Boyd, Bjorn Andersson
Cc: mark.rutland, robh, jackp, devicetree, gregkh, linux-usb,
khasim.mohammed, linux-kernel, kishon, linux-arm-msm, andy.gross,
shawn.guo, linux-arm-kernel
In-Reply-To: <5d696ad2.1c69fb81.977ea.39e5@mx.google.com>
On 8/30/19 20:28, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2019-08-30 09:45:20)
>> On Fri 30 Aug 09:01 PDT 2019, Stephen Boyd wrote:
>>
>>> Quoting Jorge Ramirez (2019-08-29 00:03:48)
>>>> On 2/23/19 17:52, Bjorn Andersson wrote:
>>>>> On Thu 07 Feb 03:17 PST 2019, Jorge Ramirez-Ortiz wrote:
>>>>>> +
>>>>>> +Required child nodes:
>>>>>> +
>>>>>> +- usb connector node as defined in bindings/connector/usb-connector.txt
>>>>>> + containing the property vbus-supply.
>>>>>> +
>>>>>> +Example:
>>>>>> +
>>>>>> +usb3_phy: usb3-phy@78000 {
>>>>>> + compatible = "qcom,snps-usb-ssphy";
>>>>>> + reg = <0x78000 0x400>;
>>>>>> + #phy-cells = <0>;
>>>>>> + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
>>>>>> + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
>>>>>> + <&gcc GCC_USB3_PHY_PIPE_CLK>;
>>>>>> + clock-names = "ref", "phy", "pipe";
>>>>>> + resets = <&gcc GCC_USB3_PHY_BCR>,
>>>>>> + <&gcc GCC_USB3PHY_PHY_BCR>;
>>>>>> + reset-names = "com", "phy";
>>>>>> + vdd-supply = <&vreg_l3_1p05>;
>>>>>> + vdda1p8-supply = <&vreg_l5_1p8>;
>>>>>> + usb3_c_connector: usb3-c-connector {
>>>
>>> Node name should be 'connector', not usb3-c-connector.
>>>
>>
>> It probably has to be usb-c-connector, because we have a
>> micro-usb-connector on the same board.
>
> Ok. Or connector@1 and connector@2? Our toplevel node container story is
> sort of sad because we have to play tricks with node names. But in the
> example, just connector I presume?
>
>>
>>>>>
>>>>> The USB-C connector is attached both to the HS and SS PHYs, so I think
>>>>> you should represent this external to this node and use of_graph to
>>>>> query it.
>>>>
>>>> but AFAICS we wont be able to retrieve the vbux-supply from an external
>>>> node (that interface does not exist).
>>>>
>>>> rob, do you have a suggestion?
>>>
>>> Shouldn't the vbus supply be in the phy? Or is this a situation where
>>> the phy itself doesn't have the vbus supply going to it because the PMIC
>>> gets in the way and handles the vbus for the connector by having the SoC
>>> communicate with the PMIC about when to turn the vbus on and off, etc?
>>>
>>
>> That's correct, the VBUS comes out of the PMIC and goes directly to the
>> connector.
>>
>> The additional complicating factor here is that the connector is wired
>> to a USB2 phy as well, so we need to wire up detection and vbus control
>> to both of them - but I think this will be fine, if we can only figure
>> out a sane way of getting hold of the vbus-supply.
>>
>
> Does it really matter to describe this situation though? Maybe it's
> simpler to throw the vbus supply into the phy and control it from the
> phy driver, even if it never really goes there. Or put it into the
> toplevel usb controller?
>
that would work for me - the connector definition seemed a better way to
explain the connectivity but since we cant retrieve the supply from the
external node is not of much functional use.
but please let me know how to proceed. shall I add the supply back to
the phy?
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^ permalink raw reply
* Re: [PATCH] PCI: Remove unused includes and superfluous struct declaration
From: kbuild test robot @ 2019-09-02 6:31 UTC (permalink / raw)
To: Krzysztof Wilczynski
Cc: devicetree, Lorenzo Pieralisi, Jingoo Han, Joerg Roedel,
linux-pci, linux-kernel, iommu, Rob Herring, Bjorn Helgaas,
kbuild-all, Thomas Petazzoni, Gustavo Pimentel, Frank Rowand,
linux-arm-kernel
In-Reply-To: <20190901112506.8469-1-kw@linux.com>
[-- Attachment #1: Type: text/plain, Size: 18112 bytes --]
Hi Krzysztof,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Krzysztof-Wilczynski/PCI-Remove-unused-includes-and-superfluous-struct-declaration/20190902-040019
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
In file included from include/linux/list.h:9:0,
from include/linux/kobject.h:19,
from include/linux/of.h:17,
from include/linux/irqdomain.h:35,
from include/linux/acpi.h:13,
from include/linux/acpi_iort.h:10,
from drivers/irqchip/irq-gic-v3-its-pci-msi.c:7:
drivers/irqchip/irq-gic-v3-its-pci-msi.c: In function 'its_pci_msi_vec_count':
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:37:12: error: implicit declaration of function 'pci_msi_vec_count'; did you mean 'its_pci_msi_vec_count'? [-Werror=implicit-function-declaration]
msi = max(pci_msi_vec_count(pdev), 0);
^
include/linux/kernel.h:821:22: note: in definition of macro '__typecheck'
(!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
^
include/linux/kernel.h:845:24: note: in expansion of macro '__safe_cmp'
__builtin_choose_expr(__safe_cmp(x, y), \
^~~~~~~~~~
include/linux/kernel.h:861:19: note: in expansion of macro '__careful_cmp'
#define max(x, y) __careful_cmp(x, y, >)
^~~~~~~~~~~~~
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:37:8: note: in expansion of macro 'max'
msi = max(pci_msi_vec_count(pdev), 0);
^~~
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:38:13: error: implicit declaration of function 'pci_msix_vec_count'; did you mean 'its_pci_msi_vec_count'? [-Werror=implicit-function-declaration]
msix = max(pci_msix_vec_count(pdev), 0);
^
include/linux/kernel.h:821:22: note: in definition of macro '__typecheck'
(!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
^
include/linux/kernel.h:845:24: note: in expansion of macro '__safe_cmp'
__builtin_choose_expr(__safe_cmp(x, y), \
^~~~~~~~~~
include/linux/kernel.h:861:19: note: in expansion of macro '__careful_cmp'
#define max(x, y) __careful_cmp(x, y, >)
^~~~~~~~~~~~~
drivers/irqchip/irq-gic-v3-its-pci-msi.c:38:9: note: in expansion of macro 'max'
msix = max(pci_msix_vec_count(pdev), 0);
^~~
drivers/irqchip/irq-gic-v3-its-pci-msi.c: In function 'its_pci_msi_prepare':
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:60:7: error: implicit declaration of function 'dev_is_pci'; did you mean 'dev_to_psd'? [-Werror=implicit-function-declaration]
if (!dev_is_pci(dev))
^~~~~~~~~~
dev_to_psd
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:65:9: error: implicit declaration of function 'to_pci_dev'; did you mean 'atomic_dec'? [-Werror=implicit-function-declaration]
pdev = to_pci_dev(dev);
^~~~~~~~~~
atomic_dec
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:65:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
pdev = to_pci_dev(dev);
^
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:70:2: error: implicit declaration of function 'pci_for_each_dma_alias'; did you mean 'xas_for_each_conflict'? [-Werror=implicit-function-declaration]
pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev);
^~~~~~~~~~~~~~~~~~~~~~
xas_for_each_conflict
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:71:36: error: dereferencing pointer to incomplete type 'struct pci_dev'
if (alias_dev != pdev && alias_dev->subordinate)
^~
>> drivers/irqchip/irq-gic-v3-its-pci-msi.c:72:3: error: implicit declaration of function 'pci_walk_bus' [-Werror=implicit-function-declaration]
pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count,
^~~~~~~~~~~~
cc1: some warnings being treated as errors
--
drivers/irqchip/irq-gic-v2m.c: In function 'gicv2m_acpi_init':
>> drivers/irqchip/irq-gic-v2m.c:558:2: error: implicit declaration of function 'pci_msi_register_fwnode_provider'; did you mean 'acpi_bus_register_driver'? [-Werror=implicit-function-declaration]
pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
acpi_bus_register_driver
cc1: some warnings being treated as errors
--
In file included from drivers/pci/controller/pci-thunder-pem.c:11:0:
include/linux/pci-acpi.h: In function 'acpi_find_root_bridge_handle':
>> include/linux/pci-acpi.h:34:29: error: dereferencing pointer to incomplete type 'struct pci_dev'
struct pci_bus *pbus = pdev->bus;
^~
>> include/linux/pci-acpi.h:37:10: error: implicit declaration of function 'pci_is_root_bus'; did you mean 'acpi_is_root_bridge'? [-Werror=implicit-function-declaration]
while (!pci_is_root_bus(pbus))
^~~~~~~~~~~~~~~
acpi_is_root_bridge
>> include/linux/pci-acpi.h:38:14: error: dereferencing pointer to incomplete type 'struct pci_bus'
pbus = pbus->parent;
^~
In file included from include/linux/acpi.h:32:0,
from include/linux/pci-acpi.h:12,
from drivers/pci/controller/pci-thunder-pem.c:11:
>> include/acpi/acpi_bus.h:411:23: warning: passing argument 1 of 'is_acpi_device_node' makes pointer from integer without a cast [-Wint-conversion]
is_acpi_device_node(__to_acpi_device_node_fwnode) ? \
^
>> include/linux/acpi.h:43:30: note: in expansion of macro 'to_acpi_device_node'
#define ACPI_COMPANION(dev) to_acpi_device_node((dev)->fwnode)
^~~~~~~~~~~~~~~~~~~
>> include/linux/acpi.h:46:46: note: in expansion of macro 'ACPI_COMPANION'
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
^~~~~~~~~~~~~~
>> include/linux/pci-acpi.h:40:9: note: in expansion of macro 'ACPI_HANDLE'
return ACPI_HANDLE(pbus->bridge);
^~~~~~~~~~~
include/acpi/acpi_bus.h:399:6: note: expected 'const struct fwnode_handle *' but argument is of type 'int'
bool is_acpi_device_node(const struct fwnode_handle *fwnode);
^~~~~~~~~~~~~~~~~~~
In file included from drivers/pci/controller/pci-thunder-pem.c:7:0:
>> include/linux/kernel.h:972:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
void *__mptr = (void *)(ptr); \
^
>> include/acpi/acpi_bus.h:412:4: note: in expansion of macro 'container_of'
container_of(__to_acpi_device_node_fwnode, \
^~~~~~~~~~~~
>> include/linux/acpi.h:43:30: note: in expansion of macro 'to_acpi_device_node'
#define ACPI_COMPANION(dev) to_acpi_device_node((dev)->fwnode)
^~~~~~~~~~~~~~~~~~~
>> include/linux/acpi.h:46:46: note: in expansion of macro 'ACPI_COMPANION'
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
^~~~~~~~~~~~~~
>> include/linux/pci-acpi.h:40:9: note: in expansion of macro 'ACPI_HANDLE'
return ACPI_HANDLE(pbus->bridge);
^~~~~~~~~~~
In file included from include/linux/build_bug.h:5:0,
from include/linux/bitfield.h:10,
from drivers/pci/controller/pci-thunder-pem.c:6:
>> include/linux/kernel.h:973:32: error: invalid type argument of unary '*' (have 'int')
BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~~~~~
include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
include/linux/kernel.h:973:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~~~~~~~~~~~~~~~
include/linux/kernel.h:973:20: note: in expansion of macro '__same_type'
BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~~~~~~~~~~
>> include/acpi/acpi_bus.h:412:4: note: in expansion of macro 'container_of'
container_of(__to_acpi_device_node_fwnode, \
^~~~~~~~~~~~
>> include/linux/acpi.h:43:30: note: in expansion of macro 'to_acpi_device_node'
#define ACPI_COMPANION(dev) to_acpi_device_node((dev)->fwnode)
^~~~~~~~~~~~~~~~~~~
>> include/linux/acpi.h:46:46: note: in expansion of macro 'ACPI_COMPANION'
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
^~~~~~~~~~~~~~
>> include/linux/pci-acpi.h:40:9: note: in expansion of macro 'ACPI_HANDLE'
return ACPI_HANDLE(pbus->bridge);
^~~~~~~~~~~
include/linux/kernel.h:974:18: error: invalid type argument of unary '*' (have 'int')
!__same_type(*(ptr), void), \
^~~~~~
include/linux/compiler.h:330:9: note: in definition of macro '__compiletime_assert'
if (!(condition)) \
^~~~~~~~~
include/linux/compiler.h:350:2: note: in expansion of macro '_compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
include/linux/kernel.h:973:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~~~~~~~~~~~~~~~
include/linux/kernel.h:974:6: note: in expansion of macro '__same_type'
!__same_type(*(ptr), void), \
^~~~~~~~~~~
>> include/acpi/acpi_bus.h:412:4: note: in expansion of macro 'container_of'
container_of(__to_acpi_device_node_fwnode, \
^~~~~~~~~~~~
>> include/linux/acpi.h:43:30: note: in expansion of macro 'to_acpi_device_node'
#define ACPI_COMPANION(dev) to_acpi_device_node((dev)->fwnode)
^~~~~~~~~~~~~~~~~~~
>> include/linux/acpi.h:46:46: note: in expansion of macro 'ACPI_COMPANION'
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
^~~~~~~~~~~~~~
vim +71 drivers/irqchip/irq-gic-v3-its-pci-msi.c
723344dd0b2aa1 Tomasz Nowicki 2016-09-12 @7 #include <linux/acpi_iort.h>
f130420e51df30 Marc Zyngier 2015-07-28 8 #include <linux/msi.h>
f130420e51df30 Marc Zyngier 2015-07-28 9 #include <linux/of.h>
f130420e51df30 Marc Zyngier 2015-07-28 10 #include <linux/of_irq.h>
f130420e51df30 Marc Zyngier 2015-07-28 11 #include <linux/of_pci.h>
f130420e51df30 Marc Zyngier 2015-07-28 12
f130420e51df30 Marc Zyngier 2015-07-28 13 static void its_mask_msi_irq(struct irq_data *d)
f130420e51df30 Marc Zyngier 2015-07-28 14 {
f130420e51df30 Marc Zyngier 2015-07-28 15 pci_msi_mask_irq(d);
f130420e51df30 Marc Zyngier 2015-07-28 16 irq_chip_mask_parent(d);
f130420e51df30 Marc Zyngier 2015-07-28 17 }
f130420e51df30 Marc Zyngier 2015-07-28 18
f130420e51df30 Marc Zyngier 2015-07-28 19 static void its_unmask_msi_irq(struct irq_data *d)
f130420e51df30 Marc Zyngier 2015-07-28 20 {
f130420e51df30 Marc Zyngier 2015-07-28 21 pci_msi_unmask_irq(d);
f130420e51df30 Marc Zyngier 2015-07-28 22 irq_chip_unmask_parent(d);
f130420e51df30 Marc Zyngier 2015-07-28 23 }
f130420e51df30 Marc Zyngier 2015-07-28 24
f130420e51df30 Marc Zyngier 2015-07-28 25 static struct irq_chip its_msi_irq_chip = {
f130420e51df30 Marc Zyngier 2015-07-28 26 .name = "ITS-MSI",
f130420e51df30 Marc Zyngier 2015-07-28 27 .irq_unmask = its_unmask_msi_irq,
f130420e51df30 Marc Zyngier 2015-07-28 28 .irq_mask = its_mask_msi_irq,
f130420e51df30 Marc Zyngier 2015-07-28 29 .irq_eoi = irq_chip_eoi_parent,
f130420e51df30 Marc Zyngier 2015-07-28 30 .irq_write_msi_msg = pci_msi_domain_write_msg,
f130420e51df30 Marc Zyngier 2015-07-28 31 };
f130420e51df30 Marc Zyngier 2015-07-28 32
3403b0259d152c Robin Murphy 2017-05-31 33 static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data)
f130420e51df30 Marc Zyngier 2015-07-28 34 {
3403b0259d152c Robin Murphy 2017-05-31 35 int msi, msix, *count = data;
f130420e51df30 Marc Zyngier 2015-07-28 36
f130420e51df30 Marc Zyngier 2015-07-28 @37 msi = max(pci_msi_vec_count(pdev), 0);
f130420e51df30 Marc Zyngier 2015-07-28 @38 msix = max(pci_msix_vec_count(pdev), 0);
3403b0259d152c Robin Murphy 2017-05-31 39 *count += max(msi, msix);
f130420e51df30 Marc Zyngier 2015-07-28 40
3403b0259d152c Robin Murphy 2017-05-31 41 return 0;
f130420e51df30 Marc Zyngier 2015-07-28 42 }
f130420e51df30 Marc Zyngier 2015-07-28 43
f130420e51df30 Marc Zyngier 2015-07-28 44 static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data)
f130420e51df30 Marc Zyngier 2015-07-28 45 {
3403b0259d152c Robin Murphy 2017-05-31 46 struct pci_dev **alias_dev = data;
f130420e51df30 Marc Zyngier 2015-07-28 47
3403b0259d152c Robin Murphy 2017-05-31 48 *alias_dev = pdev;
f130420e51df30 Marc Zyngier 2015-07-28 49
f130420e51df30 Marc Zyngier 2015-07-28 50 return 0;
f130420e51df30 Marc Zyngier 2015-07-28 51 }
f130420e51df30 Marc Zyngier 2015-07-28 52
f130420e51df30 Marc Zyngier 2015-07-28 53 static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
f130420e51df30 Marc Zyngier 2015-07-28 54 int nvec, msi_alloc_info_t *info)
f130420e51df30 Marc Zyngier 2015-07-28 55 {
3403b0259d152c Robin Murphy 2017-05-31 56 struct pci_dev *pdev, *alias_dev;
54456db9a23753 Marc Zyngier 2015-07-28 57 struct msi_domain_info *msi_info;
30800b3a1fb14c Marc Zyngier 2018-05-31 58 int alias_count = 0, minnvec = 1;
f130420e51df30 Marc Zyngier 2015-07-28 59
f130420e51df30 Marc Zyngier 2015-07-28 @60 if (!dev_is_pci(dev))
f130420e51df30 Marc Zyngier 2015-07-28 61 return -EINVAL;
f130420e51df30 Marc Zyngier 2015-07-28 62
54456db9a23753 Marc Zyngier 2015-07-28 63 msi_info = msi_get_domain_info(domain->parent);
54456db9a23753 Marc Zyngier 2015-07-28 64
f130420e51df30 Marc Zyngier 2015-07-28 @65 pdev = to_pci_dev(dev);
3403b0259d152c Robin Murphy 2017-05-31 66 /*
3403b0259d152c Robin Murphy 2017-05-31 67 * If pdev is downstream of any aliasing bridges, take an upper
3403b0259d152c Robin Murphy 2017-05-31 68 * bound of how many other vectors could map to the same DevID.
3403b0259d152c Robin Murphy 2017-05-31 69 */
3403b0259d152c Robin Murphy 2017-05-31 @70 pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev);
3403b0259d152c Robin Murphy 2017-05-31 @71 if (alias_dev != pdev && alias_dev->subordinate)
3403b0259d152c Robin Murphy 2017-05-31 @72 pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count,
3403b0259d152c Robin Murphy 2017-05-31 73 &alias_count);
f130420e51df30 Marc Zyngier 2015-07-28 74
54456db9a23753 Marc Zyngier 2015-07-28 75 /* ITS specific DeviceID, as the core ITS ignores dev. */
ccf91e68a4357e David Daney 2015-10-08 76 info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
54456db9a23753 Marc Zyngier 2015-07-28 77
30800b3a1fb14c Marc Zyngier 2018-05-31 78 /*
30800b3a1fb14c Marc Zyngier 2018-05-31 79 * Always allocate a power of 2, and special case device 0 for
30800b3a1fb14c Marc Zyngier 2018-05-31 80 * broken systems where the DevID is not wired (and all devices
30800b3a1fb14c Marc Zyngier 2018-05-31 81 * appear as DevID 0). For that reason, we generously allocate a
30800b3a1fb14c Marc Zyngier 2018-05-31 82 * minimum of 32 MSIs for DevID 0. If you want more because all
30800b3a1fb14c Marc Zyngier 2018-05-31 83 * your devices are aliasing to DevID 0, consider fixing your HW.
30800b3a1fb14c Marc Zyngier 2018-05-31 84 */
147c8f376e5526 Marc Zyngier 2018-05-27 85 nvec = max(nvec, alias_count);
30800b3a1fb14c Marc Zyngier 2018-05-31 86 if (!info->scratchpad[0].ul)
30800b3a1fb14c Marc Zyngier 2018-05-31 87 minnvec = 32;
30800b3a1fb14c Marc Zyngier 2018-05-31 88 nvec = max_t(int, minnvec, roundup_pow_of_two(nvec));
147c8f376e5526 Marc Zyngier 2018-05-27 89 return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
f130420e51df30 Marc Zyngier 2015-07-28 90 }
f130420e51df30 Marc Zyngier 2015-07-28 91
:::::: The code at line 71 was first introduced by commit
:::::: 3403b0259d152c3ca67b32bb710f826bc17c0d16 irqchip/gic-v3-its: Fix MSI alias accounting
:::::: TO: Robin Murphy <robin.murphy@arm.com>
:::::: CC: Marc Zyngier <marc.zyngier@arm.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
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^ permalink raw reply
* Re: [PATCHv3 00/10] soc: ti: add OMAP PRM driver (for reset)
From: Tero Kristo @ 2019-09-02 6:50 UTC (permalink / raw)
To: santosh.shilimkar, ssantosh, linux-omap, tony, s-anna, p.zabel
Cc: devicetree, linux-arm-kernel
In-Reply-To: <f7d6a2fb-175c-361b-00ff-ddde67700daa@oracle.com>
On 30/08/2019 19:50, santosh.shilimkar@oracle.com wrote:
> On 8/30/19 5:18 AM, Tero Kristo wrote:
>> Hi,
>>
>> V3 of the series, ended up re-sending the whole series as I squashed one
>> patch from v2 and because of that the ordering has changed a bit. Changes
>> in v3 contain fixes for the comments from Philipp Zabel.
>>
>> - added spinlock to protect register writes
>> - added own xlate function to prevent bad reset IDs to be registered
>> - use mask for the valid reset detection instead of parsing reset map
>> - fixed reset status bit handling
>> - used iopoll macro instead of handwritten poll loop for timeouts
>> - squashed patch #6 into #4 from v2 of the series
>> - some other minor fixes.
>>
>> This series still depends on the clk driver changes for the reset<->clk
>> syncing [1].
>>
> This has to wait for another merge window. It will also take care of
> dependencies landing in mainline. Will push this to linux-next as
> soon as v5.4-rc1 is out. Please remind me in case you don't see it
> in next after 5.4-rc1.
Yep it is very late so did not expect it getting in, just wanted to get
the patches rolling. I still hope to see the clock patches getting in
this cycle due to dependency, lets keep fingers crossed.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: allwinner: h6: Introduce Tanix TX6 board
From: Rong Chen @ 2019-09-02 7:05 UTC (permalink / raw)
To: Jernej Škrabec, kbuild test robot
Cc: mark.rutland, devicetree, linux-kernel, mripard, wens, robh+dt,
kbuild-all, linux-arm-kernel
In-Reply-To: <7640522.c0V0aH5rf2@jernej-laptop>
Hi,
On 8/19/19 2:59 AM, Jernej Škrabec wrote:
> Dne nedelja, 18. avgust 2019 ob 20:42:49 CEST je kbuild test robot napisal(a):
>> Hi Jernej,
>>
>> Thank you for the patch! Yet something to improve:
>>
>> [auto build test ERROR on linus/master]
>> [cannot apply to v5.3-rc4 next-20190816]
>> [if your patch is applied to the wrong git tree, please drop us a note to
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Jernej-Skrabec/dt-bindings-arm-sun
>> xi-Add-compatible-for-Tanix-TX6-board/20190819-002034 config:
>> arm64-defconfig (attached as .config)
>> compiler: aarch64-linux-gcc (GCC) 7.4.0
>> reproduce:
>> wget
>> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
>> ~/bin/make.cross chmod +x ~/bin/make.cross
>> # save the attached .config to linux build tree
>> GCC_VERSION=7.4.0 make.cross ARCH=arm64
>>
>> If you fix the issue, kindly add following tag
>> Reported-by: kbuild test robot <lkp@intel.com>
>>
>> All errors (new ones prefixed by >>):
>>>> Error: arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts:83.1-6 Label
>>>> or path r_ir not found FATAL ERROR: Syntax error parsing input tree
> Strange, Allwinner tree has commit, which introduces r_ir node:
> https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/commit/?
> h=sunxi/dt-for-5.4&id=9267811aad3524c857cf2e16bbadd8c569e15ab9
>
> Maybe kbuild test robot tree doesn't have it?
The tree is in our list.
https://github.com/intel/lkp-tests/blob/master/repo/linux/sunxi
Robot also tries to apply patches to a git tree to test. Maybe your
patch was applied to a wrong git tree.
Best Regards,
Rong Chen
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^ permalink raw reply
* Re: [PATCH v4 02/10] KVM: arm/arm64: Factor out hypercall handling from PSCI code
From: kbuild test robot @ 2019-09-02 7:06 UTC (permalink / raw)
To: Steven Price
Cc: Mark Rutland, Christoffer Dall, linux-kernel, kvm,
Radim =?unknown-8bit?B?S3LEjW3DocWZ?=, Marc Zyngier,
Suzuki K Pouloze, linux-doc, Russell King, Steven Price,
James Morse, kbuild-all, Catalin Marinas, Paolo Bonzini,
Julien Thierry, Will Deacon, kvmarm, linux-arm-kernel
In-Reply-To: <20190830084255.55113-3-steven.price@arm.com>
[-- Attachment #1: Type: text/plain, Size: 11454 bytes --]
Hi Steven,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc6 next-20190830]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Steven-Price/arm64-Stolen-time-support/20190901-185152
config: i386-randconfig-a002-201935 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
In file included from include/kvm/arm_hypercalls.h:7:0,
from <command-line>:0:
>> arch/x86/include/asm/kvm_emulate.h:349:22: error: 'NR_VCPU_REGS' undeclared here (not in a function)
unsigned long _regs[NR_VCPU_REGS];
^~~~~~~~~~~~
In file included from <command-line>:0:0:
>> include/kvm/arm_hypercalls.h:9:33: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
int kvm_hvc_call_handler(struct kvm_vcpu *vcpu);
^~~~~~~~
include/kvm/arm_hypercalls.h:11:45: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
static inline u32 smccc_get_function(struct kvm_vcpu *vcpu)
^~~~~~~~
include/kvm/arm_hypercalls.h: In function 'smccc_get_function':
>> include/kvm/arm_hypercalls.h:13:9: error: implicit declaration of function 'vcpu_get_reg' [-Werror=implicit-function-declaration]
return vcpu_get_reg(vcpu, 0);
^~~~~~~~~~~~
include/kvm/arm_hypercalls.h: At top level:
include/kvm/arm_hypercalls.h:16:51: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
static inline unsigned long smccc_get_arg1(struct kvm_vcpu *vcpu)
^~~~~~~~
include/kvm/arm_hypercalls.h:21:51: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
static inline unsigned long smccc_get_arg2(struct kvm_vcpu *vcpu)
^~~~~~~~
include/kvm/arm_hypercalls.h:26:51: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
static inline unsigned long smccc_get_arg3(struct kvm_vcpu *vcpu)
^~~~~~~~
include/kvm/arm_hypercalls.h:31:44: warning: 'struct kvm_vcpu' declared inside parameter list will not be visible outside of this definition or declaration
static inline void smccc_set_retval(struct kvm_vcpu *vcpu,
^~~~~~~~
include/kvm/arm_hypercalls.h: In function 'smccc_set_retval':
>> include/kvm/arm_hypercalls.h:37:2: error: implicit declaration of function 'vcpu_set_reg'; did you mean 'smccc_set_retval'? [-Werror=implicit-function-declaration]
vcpu_set_reg(vcpu, 0, a0);
^~~~~~~~~~~~
smccc_set_retval
cc1: some warnings being treated as errors
vim +/NR_VCPU_REGS +349 arch/x86/include/asm/kvm_emulate.h
a584539b24b87d arch/x86/include/asm/kvm_emulate.h Paolo Bonzini 2015-04-01 290
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 291 struct x86_emulate_ctxt {
0225fb509d51fc arch/x86/include/asm/kvm_emulate.h Mathias Krause 2012-08-30 292 const struct x86_emulate_ops *ops;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 293
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 294 /* Register state before/after emulation. */
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 295 unsigned long eflags;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 296 unsigned long eip; /* eip before instruction emulation */
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 297 /* Emulated execution mode, represented by an X86EMUL_MODE value. */
9d1b39a967871b arch/x86/include/asm/kvm_emulate.h Gleb Natapov 2012-09-03 298 enum x86emul_mode mode;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 299
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 300 /* interruptibility state, as a result of execution of STI or MOV SS */
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 301 int interruptibility;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 302
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 303 bool perm_ok; /* do not check permissions if true */
b51e974fcdabd0 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 304 bool ud; /* inject an #UD if host doesn't support insn */
c8401dda2f0a00 arch/x86/include/asm/kvm_emulate.h Paolo Bonzini 2017-06-07 305 bool tf; /* TF value before instruction (after for syscall/sysret) */
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 306
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 307 bool have_exception;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 308 struct x86_exception exception;
9dac77fa4011bd arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 309
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 310 /*
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 311 * decode cache
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 312 */
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 313
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 314 /* current opcode length in bytes */
1ce19dc16ce913 arch/x86/include/asm/kvm_emulate.h Borislav Petkov 2013-09-22 315 u8 opcode_len;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 316 u8 b;
c4f035c60dad45 arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-04-04 317 u8 intercept;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 318 u8 op_bytes;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 319 u8 ad_bytes;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 320 struct operand src;
0dc8d10f7d848b arch/x86/include/asm/kvm_x86_emulate.h Guillaume Thouvenin 2008-12-04 321 struct operand src2;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 322 struct operand dst;
ef65c88912cafe arch/x86/include/asm/kvm_emulate.h Avi Kivity 2010-07-29 323 int (*execute)(struct x86_emulate_ctxt *ctxt);
d09beabd7cd4cf arch/x86/include/asm/kvm_emulate.h Joerg Roedel 2011-04-04 324 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
41061cdb98a0be arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 325 /*
41061cdb98a0be arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 326 * The following six fields are cleared together,
41061cdb98a0be arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 327 * the rest are initialized unconditionally in x86_decode_insn
41061cdb98a0be arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 328 * or elsewhere
41061cdb98a0be arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 329 */
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 330 bool rip_relative;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 331 u8 rex_prefix;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 332 u8 lock_prefix;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 333 u8 rep_prefix;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 334 /* bitmaps of registers in _regs[] that can be read */
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 335 u32 regs_valid;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 336 /* bitmaps of registers in _regs[] that have been written */
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 337 u32 regs_dirty;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 338 /* modrm */
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 339 u8 modrm;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 340 u8 modrm_mod;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 341 u8 modrm_reg;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 342 u8 modrm_rm;
09ee57cdae3156 arch/x86/include/asm/kvm_emulate.h Avi Kivity 2010-08-01 343 u8 modrm_seg;
573e80fe04db1a arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 344 u8 seg_override;
c44b4c6ab80eef arch/x86/include/asm/kvm_emulate.h Bandan Das 2014-04-16 345 u64 d;
36dd9bb5ce32bc arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-06-01 346 unsigned long _eip;
cbd27ee783f1e5 arch/x86/include/asm/kvm_emulate.h Avi Kivity 2012-06-10 347 struct operand memop;
b5c9ff731f3cee arch/x86/include/asm/kvm_emulate.h Takuya Yoshikawa 2011-05-25 348 /* Fields above regs are cleared together. */
dd856efafe6097 arch/x86/include/asm/kvm_emulate.h Avi Kivity 2012-08-27 @349 unsigned long _regs[NR_VCPU_REGS];
f09ed83e211d25 arch/x86/include/asm/kvm_emulate.h Avi Kivity 2011-09-13 350 struct operand *memopp;
6226686954c4cc drivers/kvm/x86_emulate.h Avi Kivity 2007-11-20 351 struct fetch_cache fetch;
7b262e90fc20a4 arch/x86/include/asm/kvm_emulate.h Gleb Natapov 2010-03-18 352 struct read_cache io_read;
9de41573675cba arch/x86/include/asm/kvm_emulate.h Gleb Natapov 2010-04-28 353 struct read_cache mem_read;
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 354 };
e4e03deda83b1f drivers/kvm/x86_emulate.h Laurent Vivier 2007-09-18 355
:::::: The code at line 349 was first introduced by commit
:::::: dd856efafe6097a5c9104725c2bca74430423db8 KVM: x86 emulator: access GPRs on demand
:::::: TO: Avi Kivity <avi@redhat.com>
:::::: CC: Marcelo Tosatti <mtosatti@redhat.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH] drm/mcde: Some fixes to handling video mode
From: Linus Walleij @ 2019-09-02 7:17 UTC (permalink / raw)
To: dri-devel, Maarten Lankhorst, Maxime Ripard, Sean Paul
Cc: Linus Walleij, Stephan Gerhold, linux-arm-kernel
The video DSI mode had not really been tested. These fixes makes
it more likely to work on real hardware:
- Set the HS clock to something the video mode reported by the
panel can handle rather than the max HS rate.
- Put the active width (x width) in the right bits and the VSA
(vertical sync active) in the right bits (those were swapped).
- Calculate the packet sizes in bytes as in the vendor driver,
rather than in bits.
- Handle negative result in front/back/sync packages and fall
back to zero like in the vendor driver.
Cc: Stephan Gerhold <stephan@gerhold.net>
Fixes: 5fc537bfd000 ("drm/mcde: Add new driver for ST-Ericsson MCDE")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpu/drm/mcde/mcde_dsi.c | 60 ++++++++++++++++++++++-----------
1 file changed, 41 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c
index 90659d190d78..f5079f0e24ca 100644
--- a/drivers/gpu/drm/mcde/mcde_dsi.c
+++ b/drivers/gpu/drm/mcde/mcde_dsi.c
@@ -365,11 +365,12 @@ void mcde_dsi_te_request(struct mipi_dsi_device *mdsi)
static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
const struct drm_display_mode *mode)
{
- u8 bpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format);
+ /* cpp, characters per pixel, number of bytes per pixel */
+ u8 cpp = mipi_dsi_pixel_format_to_bpp(d->mdsi->format) / 8;
u64 bpl;
- u32 hfp;
- u32 hbp;
- u32 hsa;
+ int hfp;
+ int hbp;
+ int hsa;
u32 blkline_pck, line_duration;
u32 blkeol_pck, blkeol_duration;
u32 val;
@@ -420,13 +421,13 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
writel(val, d->regs + DSI_VID_MAIN_CTL);
/* Vertical frame parameters are pretty straight-forward */
- val = mode->vdisplay << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;
+ val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
/* vertical front porch */
val |= (mode->vsync_start - mode->vdisplay)
<< DSI_VID_VSIZE_VFP_LENGTH_SHIFT;
/* vertical sync active */
val |= (mode->vsync_end - mode->vsync_start)
- << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
+ << DSI_VID_VSIZE_VSA_LENGTH_SHIFT;
/* vertical back porch */
val |= (mode->vtotal - mode->vsync_end)
<< DSI_VID_VSIZE_VBP_LENGTH_SHIFT;
@@ -437,21 +438,25 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
* horizontal resolution is given in pixels and must be re-calculated
* into bytes since this is what the hardware expects.
*
+ * hfp = horizontal front porch in bytes
+ * hbp = horizontal back porch in bytes
+ * hsa = horizontal sync active in bytes
+ *
* 6 + 2 is HFP header + checksum
*/
- hfp = (mode->hsync_start - mode->hdisplay) * bpp - 6 - 2;
+ hfp = (mode->hsync_start - mode->hdisplay) * cpp - 6 - 2;
if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
/*
* 6 is HBP header + checksum
* 4 is RGB header + checksum
*/
- hbp = (mode->htotal - mode->hsync_end) * bpp - 4 - 6;
+ hbp = (mode->htotal - mode->hsync_end) * cpp - 4 - 6;
/*
* 6 is HBP header + checksum
* 4 is HSW packet bytes
* 4 is RGB header + checksum
*/
- hsa = (mode->hsync_end - mode->hsync_start) * bpp - 4 - 4 - 6;
+ hsa = (mode->hsync_end - mode->hsync_start) * cpp - 4 - 4 - 6;
} else {
/*
* HBP includes both back porch and sync
@@ -459,11 +464,23 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
* 4 is HSW packet bytes
* 4 is RGB header + checksum
*/
- hbp = (mode->htotal - mode->hsync_start) * bpp - 4 - 4 - 6;
- /* HSA is not considered in this mode and set to 0 */
+ hbp = (mode->htotal - mode->hsync_start) * cpp - 4 - 4 - 6;
+ /* HSA is not present in this mode and set to 0 */
+ hsa = 0;
+ }
+ if (hfp < 0) {
+ dev_info(d->dev, "hfp negative, set to 0\n");
+ hfp = 0;
+ }
+ if (hbp < 0) {
+ dev_info(d->dev, "hbp negative, set to 0\n");
+ hbp = 0;
+ }
+ if (hsa < 0) {
+ dev_info(d->dev, "hsa negative, set to 0\n");
hsa = 0;
}
- dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u\n",
+ dev_dbg(d->dev, "hfp: %u, hbp: %u, hsa: %u bytes\n",
hfp, hbp, hsa);
/* Frame parameters: horizontal sync active */
@@ -475,7 +492,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
writel(val, d->regs + DSI_VID_HSIZE1);
/* RGB data length (bytes on one scanline) */
- val = mode->hdisplay * (bpp / 8);
+ val = mode->hdisplay * cpp;
writel(val, d->regs + DSI_VID_HSIZE2);
/* TODO: further adjustments for TVG mode here */
@@ -507,7 +524,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
}
line_duration = (blkline_pck + 6) / d->mdsi->lanes;
- dev_dbg(d->dev, "line duration %u\n", line_duration);
+ dev_dbg(d->dev, "line duration %u bytes\n", line_duration);
val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;
/*
* This is the time to perform LP->HS on D-PHY
@@ -517,17 +534,18 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
writel(val, d->regs + DSI_VID_DPHY_TIME);
/* Calculate block end of line */
- blkeol_pck = bpl - mode->hdisplay * bpp - 6;
+ blkeol_pck = bpl - mode->hdisplay * cpp - 6;
blkeol_duration = (blkeol_pck + 6) / d->mdsi->lanes;
- dev_dbg(d->dev, "blkeol pck: %u, duration: %u\n",
- blkeol_pck, blkeol_duration);
+ dev_dbg(d->dev, "blkeol pck: %u bytes, duration: %u bytes\n",
+ blkeol_pck, blkeol_duration);
if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
/* Set up EOL clock for burst mode */
val = readl(d->regs + DSI_VID_BLKSIZE1);
val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;
writel(val, d->regs + DSI_VID_BLKSIZE1);
- writel(blkeol_pck, d->regs + DSI_VID_VCA_SETTING2);
+ writel(blkeol_pck & DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK,
+ d->regs + DSI_VID_VCA_SETTING2);
writel(blkeol_duration, d->regs + DSI_VID_PCK_TIME);
writel(blkeol_duration - 6, d->regs + DSI_VID_VCA_SETTING1);
@@ -535,9 +553,11 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
/* Maximum line limit */
val = readl(d->regs + DSI_VID_VCA_SETTING2);
+ val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK;
val |= blkline_pck <<
DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT;
writel(val, d->regs + DSI_VID_VCA_SETTING2);
+ dev_dbg(d->dev, "blkline pck: %u bytes\n", blkline_pck);
/* Put IF1 into video mode */
val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
@@ -699,7 +719,9 @@ static void mcde_dsi_bridge_mode_set(struct drm_bridge *bridge,
lp_freq = d->mdsi->lp_rate;
else
lp_freq = DSI_DEFAULT_LP_FREQ_HZ;
- if (d->mdsi->hs_rate)
+ if (pixel_clock_hz)
+ hs_freq = pixel_clock_hz;
+ else if (d->mdsi->hs_rate)
hs_freq = d->mdsi->hs_rate;
else
hs_freq = DSI_DEFAULT_HS_FREQ_HZ;
--
2.21.0
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^ permalink raw reply related
* Re: [PATCH] spi: ep93xx: Repair SPI CS lookup tables
From: Lukasz Majewski @ 2019-09-02 7:18 UTC (permalink / raw)
To: Alexander Sverdlin
Cc: Hartley Sweeten, Linus Walleij, Russell King, stable, linux-spi,
linux-gpio, Mark Brown, linux-arm-kernel
In-Reply-To: <20190831180402.10008-1-alexander.sverdlin@gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 3660 bytes --]
On Sat, 31 Aug 2019 20:04:02 +0200
Alexander Sverdlin <alexander.sverdlin@gmail.com> wrote:
> The actual device name of the SPI controller being registered on
> EP93xx is "spi0" (as seen by gpiod_find_lookup_table()). This patch
> fixes all relevant lookup tables and the following failure (seen on
> EDB9302):
>
> ep93xx-spi ep93xx-spi.0: failed to register SPI master
> ep93xx-spi: probe of ep93xx-spi.0 failed with error -22
>
> Fixes: 1dfbf334f1236 ("spi: ep93xx: Convert to use CS GPIO
> descriptors") Cc: stable@vger.kernel.org
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
> arch/arm/mach-ep93xx/edb93xx.c | 2 +-
> arch/arm/mach-ep93xx/simone.c | 2 +-
> arch/arm/mach-ep93xx/ts72xx.c | 4 ++--
> arch/arm/mach-ep93xx/vision_ep9307.c | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-ep93xx/edb93xx.c
> b/arch/arm/mach-ep93xx/edb93xx.c index 1f0da76a39de..7b7280c21ee0
> 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c
> +++ b/arch/arm/mach-ep93xx/edb93xx.c
> @@ -103,7 +103,7 @@ static struct spi_board_info
> edb93xx_spi_board_info[] __initdata = { };
>
> static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = {
> - .dev_id = "ep93xx-spi.0",
> + .dev_id = "spi0",
> .table = {
> GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW),
> { },
> diff --git a/arch/arm/mach-ep93xx/simone.c
> b/arch/arm/mach-ep93xx/simone.c index e2658e22bba1..8a53b74dc4b2
> 100644 --- a/arch/arm/mach-ep93xx/simone.c
> +++ b/arch/arm/mach-ep93xx/simone.c
> @@ -73,7 +73,7 @@ static struct spi_board_info simone_spi_devices[]
> __initdata = {
> * v1.3 parts will still work, since the signal on SFRMOUT is
> automatic. */
> static struct gpiod_lookup_table simone_spi_cs_gpio_table = {
> - .dev_id = "ep93xx-spi.0",
> + .dev_id = "spi0",
> .table = {
> GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW),
> { },
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c
> b/arch/arm/mach-ep93xx/ts72xx.c index 582e06e104fd..e0e1b11032f1
> 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -267,7 +267,7 @@ static struct spi_board_info bk3_spi_board_info[]
> __initdata = {
> * goes through CPLD
> */
> static struct gpiod_lookup_table bk3_spi_cs_gpio_table = {
> - .dev_id = "ep93xx-spi.0",
> + .dev_id = "spi0",
> .table = {
> GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW),
> { },
> @@ -316,7 +316,7 @@ static struct spi_board_info ts72xx_spi_devices[]
> __initdata = { };
>
> static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table = {
> - .dev_id = "ep93xx-spi.0",
> + .dev_id = "spi0",
> .table = {
> /* DIO_17 */
> GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW),
> diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c
> b/arch/arm/mach-ep93xx/vision_ep9307.c index
> a88a1d807b32..cbcba3136d74 100644 ---
> a/arch/arm/mach-ep93xx/vision_ep9307.c +++
> b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -242,7 +242,7 @@ static
> struct spi_board_info vision_spi_board_info[] __initdata = { };
>
> static struct gpiod_lookup_table vision_spi_cs_gpio_table = {
> - .dev_id = "ep93xx-spi.0",
> + .dev_id = "spi0",
> .table = {
> GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW),
> GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW),
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
[-- Attachment #1.2: OpenPGP digital signature --]
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^ permalink raw reply
* Re: [PATCH v2 2/9] x86: numa: check the node id consistently for x86
From: Peter Zijlstra @ 2019-09-02 7:25 UTC (permalink / raw)
To: Yunsheng Lin
Cc: dalias, linux-sh, catalin.marinas, dave.hansen, heiko.carstens,
linuxarm, jiaxun.yang, linux-kernel, mwb, paulus, hpa, sparclinux,
chenhc, will, linux-s390, ysato, mpe, x86, rppt, borntraeger,
dledford, mingo, jeffrey.t.kirsher, benh, jhogan, nfont, mattst88,
len.brown, gor, anshuman.khandual, ink, cai, luto, tglx,
naveen.n.rao, linux-arm-kernel, rth, axboe, robin.murphy,
linux-mips, ralf, tbogendoerfer, paul.burton, linux-alpha, bp,
akpm, linuxppc-dev, davem
In-Reply-To: <ae64285f-5134-4147-7b02-34bb5d519e8c@huawei.com>
On Mon, Sep 02, 2019 at 01:46:51PM +0800, Yunsheng Lin wrote:
> On 2019/9/1 0:12, Peter Zijlstra wrote:
> > 1) because even it is not set, the device really does belong to a node.
> > It is impossible a device will have magic uniform access to memory when
> > CPUs cannot.
>
> So it means dev_to_node() will return either NUMA_NO_NODE or a
> valid node id?
NUMA_NO_NODE := -1, which is not a valid node number. It is also, like I
said, not a valid device location on a NUMA system.
Just because ACPI/BIOS is shit, doesn't mean the device doesn't have a
node association. It just means we don't know and might have to guess.
> > 2) is already true today, cpumask_of_node() requires a valid node_id.
>
> Ok, most of the user does check node_id before calling
> cpumask_of_node(), but does a little different type of checking:
>
> 1) some does " < 0" check;
> 2) some does "== NUMA_NO_NODE" check;
> 3) some does ">= MAX_NUMNODES" check;
> 4) some does "< 0 || >= MAX_NUMNODES || !node_online(node)" check.
The one true way is:
'(unsigned)node_id >= nr_node_ids'
> > 3) is just wrong and increases overhead for everyone.
>
> Ok, cpumask_of_node() is also used in some critical path such
> as scheduling, which may not need those checking, the overhead
> is unnecessary.
>
> But for non-critical path such as setup or configuration path,
> it better to have consistent checking, and also simplify the
> user code that calls cpumask_of_node().
>
> Do you think it is worth the trouble to add a new function
> such as cpumask_of_node_check(maybe some other name) to do
> consistent checking?
>
> Or caller just simply check if dev_to_node()'s return value is
> NUMA_NO_NODE before calling cpumask_of_node()?
It is not a matter of convenience. The function is called
cpumask_of_node(), when node < 0 || node >= nr_node_ids, it is not a
valid node, therefore the function shouldn't return anything except an
error.
Also note that the CONFIG_DEBUG_PER_CPU_MAPS version of
cpumask_of_node() already does this (although it wants the below fix).
---
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index e6dad600614c..5f49c10201c7 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -861,7 +861,7 @@ void numa_remove_cpu(int cpu)
*/
const struct cpumask *cpumask_of_node(int node)
{
- if (node >= nr_node_ids) {
+ if ((unsigned)node >= nr_node_ids) {
printk(KERN_WARNING
"cpumask_of_node(%d): node > nr_node_ids(%u)\n",
node, nr_node_ids);
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^ permalink raw reply related
* Re: [PATCH v5 00/18] add thermal driver for h6
From: Maxime Ripard @ 2019-09-02 7:27 UTC (permalink / raw)
To: Yangtao Li, rui.zhang, edubezval, daniel.lezcano, robh+dt,
mark.rutland, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre, devicetree, linux-kernel,
linux-arm-kernel, linux-pm
In-Reply-To: <20190901215214.f4vbxemdd7mf3gun@core.my.home>
Hi,
On Sun, Sep 01, 2019 at 11:52:14PM +0200, Ondřej Jirman wrote:
> Hello Yangtao,
>
> On Sat, Aug 10, 2019 at 05:28:11AM +0000, Yangtao Li wrote:
> > This patchset add support for A64, H3, H5, H6 and R40 thermal sensor.
> >
> > Thx to Icenowy and Vasily.
> >
> > BTY, do a cleanup in thermal makfile.
>
> I've added support for A83T and also some cleanups, according to my
> feedback:
>
> https://megous.com/git/linux/log/?h=ths-5.3
>
> Feel free to pick up whatever you like from that tree.
>
> For others, there are also DTS patches in that tree for H3, H5, A83T, and H6, so
> that shoul make testing of this driver easier.
I'm not convinced that always expanding the number of SoC supported is
the best strategy to get this merged. Usually, keeping the same
feature set across version, consolidating that, and then once it's in
sending the new SoC support works best.
Maxime
--
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Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [RFC 1/9] dt-bindings: arm: samsung: Convert Samsung board/soc bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-02 7:32 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, Alessandro Zummo, Alexandre Belloni,
Lars-Peter Clausen, Arnd Bergmann, devicetree,
open list:IIO SUBSYSTEM AND DRIVERS, Marek Szyprowski,
linux-kernel@vger.kernel.org, Tomasz Figa, linux-samsung-soc,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Peter Meerwald-Stadler, Hartmut Knaack, Olof Johansson,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM, notify,
Jonathan Cameron, Paweł Chmiel
In-Reply-To: <CAL_Jsq+5MpPSjRtFp-xf8P0rBuArMFbum7yadcHNBQz_N=Ergg@mail.gmail.com>
On Mon, 26 Aug 2019 at 13:38, Rob Herring <robh+dt@kernel.org> wrote:
>
> On Fri, Aug 23, 2019 at 9:54 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > Convert Samsung S5P and Exynos SoC bindings to DT schema format using
> > json-schema. This is purely conversion of already documented bindings
> > so it does not cover all of DTS in the Linux kernel (few S5P/Exynos and
> > all S3C are missing).
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > ---
> >
> > If the schema looks sensible, I will continue on converting other
> > SoC and driver bindings and later adding missing schemas (S3C
> > SoCs).
>
> Looks pretty good.
>
> > ---
> > .../bindings/arm/samsung/samsung-boards.txt | 83 --------
> > .../bindings/arm/samsung/samsung-boards.yaml | 188 ++++++++++++++++++
> > 2 files changed, 188 insertions(+), 83 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> > create mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
>
>
> > diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> > new file mode 100644
> > index 000000000000..e963fd70c436
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> > @@ -0,0 +1,188 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung Exynos and S5P SoC based boards
> > +
> > +maintainers:
> > + - Krzysztof Kozlowski <krzk@kernel.org>
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: S5PV210 based Aries boards
> > + items:
> > + - enum:
> > + - samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P)
> > + - samsung,galaxys # Samsung Galaxy S (i9000)
> > + - const: samsung,aries
> > + - const: samsung,s5pv210
> > +
> > + - description: Exynos3250 based boards
> > + items:
> > + - enum:
> > + - samsung,monk # Samsung Simband
> > + - samsung,rinato # Samsung Gear2
> > + - const: samsung,exynos3250
> > + - const: samsung,exynos3
> > +
> > + - description: Samsung ARTIK5 boards
> > + items:
> > + - enum:
> > + - samsung,artik5-eval # Samsung ARTIK5 eval board
> > + - const: samsung,artik5 # Samsung ARTIK5 module
> > + - const: samsung,exynos3250
> > + - const: samsung,exynos3
> > +
> > + - description: Exynos4210 based boards
> > + items:
> > + - enum:
> > + - insignal,origen # Insignal Origen
> > + - samsung,smdkv310 # Samsung SMDKV310 eval
> > + - samsung,trats # Samsung Tizen Reference
> > + - samsung,universal_c210 # Samsung C210
> > + - const: samsung,exynos4210
> > + - const: samsung,exynos4
> > +
> > + - description: Exynos4412 based boards
> > + items:
> > + - enum:
> > + - friendlyarm,tiny4412 # FriendlyARM TINY4412
> > + - hardkernel,odroid-u3 # Hardkernel Odroid U3
> > + - hardkernel,odroid-x # Hardkernel Odroid X
> > + - hardkernel,odroid-x2 # Hardkernel Odroid X2
> > + - insignal,origen4412 # Insignal Origen
> > + - samsung,smdk4412 # Samsung SMDK4412 eval
> > + - topeet,itop4412-elite # TOPEET Elite base
> > + - const: samsung,exynos4412
> > + - const: samsung,exynos4
> > +
> > + - description: Samsung Midas family boards
> > + items:
> > + - enum:
> > + - samsung,i9300 # Samsung GT-I9300
> > + - samsung,i9305 # Samsung GT-I9305
> > + - samsung,n710x # Samsung GT-N7100/GT-N7105
> > + - samsung,trats2 # Samsung Tizen Reference
> > + - const: samsung,midas
> > + - const: samsung,exynos4412
> > + - const: samsung,exynos4
> > +
> > + - description: Exynos5250 based boards
> > + items:
> > + - enum:
> > + - google,snow-rev5 # Google Snow Rev 5+
> > + - google,spring # Google Spring
> > + - insignal,arndale # Insignal Arndale
> > + - samsung,smdk5250 # Samsung SMDK5250 eval
> > + - const: samsung,exynos5250
> > + - const: samsung,exynos5
> > +
> > + - description: Google Snow Boards (Rev 4+)
> > + items:
> > + - enum:
> > + - google,snow-rev4
>
> const here as I wouldn't expect this list to grow.
OK
>
> > + - const: google,snow
> > + - const: samsung,exynos5250
> > + - const: samsung,exynos5
> > +
> > + - description: Exynos5260 based boards
> > + items:
> > + - enum:
> > + - samsung,xyref5260 # Samsung Xyref5260 eval
> > + - const: samsung,exynos5260
> > + - const: samsung,exynos5
> > +
> > + - description: Exynos5410 based boards
> > + items:
> > + - enum:
> > + - hardkernel,odroid-xu # Hardkernel Odroid XU
> > + - samsung,smdk5410 # Samsung SMDK5410 eval
> > + - const: samsung,exynos5410
> > + - const: samsung,exynos5
> > +
> > + - description: Exynos5420 based boards
> > + items:
> > + - enum:
> > + - insignal,arndale-octa # Insignal Arndale Octa
> > + - samsung,smdk5420 # Samsung SMDK5420 eval
> > + - const: samsung,exynos5420
> > + - const: samsung,exynos5
> > +
> > + - description: Google Peach Pit Boards (Rev 6+)
> > + items:
> > + - enum:
> > + - google,pit-rev16
>
> const
OK
>
> > + - const: google,pit-rev15
> > + - const: google,pit-rev14
> > + - const: google,pit-rev13
> > + - const: google,pit-rev12
> > + - const: google,pit-rev11
> > + - const: google,pit-rev10
> > + - const: google,pit-rev9
> > + - const: google,pit-rev8
> > + - const: google,pit-rev7
> > + - const: google,pit-rev6
> > + - const: google,pit
> > + - const: google,peach
> > + - const: samsung,exynos5420
> > + - const: samsung,exynos5
> > +
> > + - description: Exynos5800 based boards
> > + items:
> > + - enum:
> > + - hardkernel,odroid-xu3 # Hardkernel Odroid XU3
> > + - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
> > + - hardkernel,odroid-xu4 # Hardkernel Odroid XU4
> > + - hardkernel,odroid-hc1 # Hardkernel Odroid HC1
> > + - const: samsung,exynos5800
> > + - const: samsung,exynos5
> > +
> > + - description: Google Peach Pi Boards (Rev 10+)
> > + items:
> > + - enum:
> > + - google,pi-rev16
> > + - const: google,pi-rev15
> > + - const: google,pi-rev14
> > + - const: google,pi-rev13
> > + - const: google,pi-rev12
> > + - const: google,pi-rev11
> > + - const: google,pi-rev10
> > + - const: google,pi
> > + - const: google,peach
> > + - const: samsung,exynos5800
> > + - const: samsung,exynos5
> > +
> > + - description: Exynos5433 based boards
> > + items:
> > + - enum:
> > + - samsung,tm2 # Samsung TM2
> > + - samsung,tm2e # Samsung TM2E
> > + - const: samsung,exynos5433
> > +
> > + firmware:
>
> This should be moved to its own file.
Indeed, thanks for the review.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia, smmu-v2
From: Thierry Reding @ 2019-09-02 7:38 UTC (permalink / raw)
To: Krishna Reddy
Cc: Timo Alho, Thierry Reding, Mikko Perttunen,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
Pritesh Raithatha, Thomas Zeng (SW-TEGRA), Sachin Nikam,
linux-tegra@vger.kernel.org, Yu-Huan Hsu, Juha Tukkinen,
Robin Murphy, Alexander Van Brunt,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <BYAPR12MB271012F225E35C1459E58D07B3BD0@BYAPR12MB2710.namprd12.prod.outlook.com>
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On Fri, Aug 30, 2019 at 06:12:08PM +0000, Krishna Reddy wrote:
> >> + "nidia,smmu-v2"
> >> "qcom,smmu-v2"
>
> >I agree with Mikko that the compatible must be at least SoC-specific, but potentially even instance-specific (e.g. "nvidia,tegra194-gpu-smmu")
> > depending on how many of these parallel-SMMU configurations might be hiding in current and future SoCs.
>
> I am correcting the spelling mistake pointed by Mikko. The NVIDIA SMMUv2 implementation is getting used beyond Tegra194 SOC.
> To be able to use the smmu compatible string across multiple SOC's, "nvidia,smmu-v2" compatible string is chosen.
> Are you suggesting to make it soc specific and add another one in future?
Yeah, I think that's the safest thing to do. Even if we're using the
same implementation in future SoCs, chances are there will be some
changes. Even if the changes are just fixes, having a SoC-specific
compatible string will ensure we can apply workarounds only to the
implementations that are missing the fixes.
So I think "nvidia,tegra194-smmu" is a good candidate. It uniquely
identifies the instantiation of the IP in Tegra194. Also, if it ever
turns out that the instantiation of the SMMU in the next Tegra
generation is *exactly* the same (even if highly unlikely), there's
nothing wrong with reusing the "nvidia,tegra194-smmu".
We've done similar things in the past, where some new IP was mostly
compatible with old IP. Typically we still include a new compatible
string in case any errata are discovered subsequently. It's not uncommon
to see things like:
compatible = "nvidia,tegra124-xyz", "nvidia,tegra20-xyz";
Basically this means that this is the IP that was also used in Tegra20
and the same Tegra20 driver can be used to drive this hardware on
Tegra124. The Tegra124-specific compatible string may enable newer
features if there's a driver that supports it.
Thierry
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^ permalink raw reply
* Re: [PATCH 1/3] ASoC: xlnx: add Xilinx logicPD-I2S FPGA IP support
From: Michal Simek @ 2019-09-02 7:39 UTC (permalink / raw)
To: Miquel Raynal, Liam Girdwood, Mark Brown, Jaroslav Kysela,
Takashi Iwai
Cc: Mark Rutland, devicetree, alsa-devel,
Maruthi Srinivas Bayyavarapu, Michal Simek, Rob Herring,
Thomas Petazzoni, praveenv, alexandre, linux-arm-kernel
In-Reply-To: <20190830210607.22644-1-miquel.raynal@bootlin.com>
Hi Miquel
On 30. 08. 19 23:06, Miquel Raynal wrote:
> This IP is very simple so this driver manage both the DAI and the PCM
> streams, hence the presence of both components in this driver.
>
> There are plenty available interruptions when capturing or playing
> back audio that can be triggered but the only one that fits the ALSA
> sound system is the XFER_DONE which is used to bound sound
> periods. Other interrupts are masked. Please note that capture and
> playback are not possible at the same time though.
>
> Capture seems to work (at least it creates a file with something
> inside) but I have no capture mechanism on the board to actually test
> that it works correctly.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>
> Hello,
>
> This is my first contribution in the sound subsystem, I hope I've
> understood the core but I might be entirely wrong as well, so please
> do not hesitate to be critical on my choices.
>
> Thanks,
> Miquèl
>
> sound/soc/xilinx/Kconfig | 7 +
> sound/soc/xilinx/Makefile | 2 +
> sound/soc/xilinx/xlnx-logicpd-i2s.c | 468 ++++++++++++++++++++++++++++
What IP is this?
https://www.xilinx.com/products/intellectual-property/audio-i2s.html
https://github.com/Xilinx/linux-xlnx/blob/master/sound/soc/xilinx/xlnx_i2s.c
Anyway I am adding Praveen and Maruthi to take a look.
Thanks,
Michal
> 3 files changed, 477 insertions(+)
> create mode 100644 sound/soc/xilinx/xlnx-logicpd-i2s.c
>
> diff --git a/sound/soc/xilinx/Kconfig b/sound/soc/xilinx/Kconfig
> index 47f606b924e4..b62cae6750b9 100644
> --- a/sound/soc/xilinx/Kconfig
> +++ b/sound/soc/xilinx/Kconfig
> @@ -7,6 +7,13 @@ config SND_SOC_XILINX_I2S
> PCM data. In receiver mode, IP receives PCM audio and
> encapsulates PCM in AES format and sends AES data.
>
> +config SND_SOC_XILINX_LOGICPD_I2S
> + tristate "Audio support for the Xilinx logicPD I2S"
> + help
> + Select this option to enable Xilinx logicPD I2S slave
> + transceiver. This enables I2S playback and capture using
> + Xilinx/logicPD IP.
> +
> config SND_SOC_XILINX_AUDIO_FORMATTER
> tristate "Audio support for the the Xilinx audio formatter"
> help
> diff --git a/sound/soc/xilinx/Makefile b/sound/soc/xilinx/Makefile
> index d79fd38b094b..d127c30f8fe2 100644
> --- a/sound/soc/xilinx/Makefile
> +++ b/sound/soc/xilinx/Makefile
> @@ -1,5 +1,7 @@
> snd-soc-xlnx-i2s-objs := xlnx_i2s.o
> obj-$(CONFIG_SND_SOC_XILINX_I2S) += snd-soc-xlnx-i2s.o
> +snd-soc-xlnx-logicpd-i2s-objs := xlnx-logicpd-i2s.o
> +obj-$(CONFIG_SND_SOC_XILINX_LOGICPD_I2S) += snd-soc-xlnx-logicpd-i2s.o
> snd-soc-xlnx-formatter-pcm-objs := xlnx_formatter_pcm.o
> obj-$(CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER) += snd-soc-xlnx-formatter-pcm.o
> snd-soc-xlnx-spdif-objs := xlnx_spdif.o
> diff --git a/sound/soc/xilinx/xlnx-logicpd-i2s.c b/sound/soc/xilinx/xlnx-logicpd-i2s.c
> new file mode 100644
> index 000000000000..325a5bb6978a
> --- /dev/null
> +++ b/sound/soc/xilinx/xlnx-logicpd-i2s.c
> @@ -0,0 +1,468 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx logicPD logiI2S - I2S slave transceiver v2 support
> + *
> + * Copyright (C) 2019 Bootlin
> + *
> + * Author: Miquel Raynal <miquel.raynal@bootlin.com>
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <sound/dmaengine_pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +
> +#define DRV_NAME "xlnx_logicpd_i2s"
> +
> +#define IP_VERSION 0x0
> +#define PATCH_LEVEL(reg) (((reg) & GENMASK(4, 0)) + 'a')
> +#define MINOR_REV(reg) (((reg) & GENMASK(10, 5)) >> 5)
> +#define MAJOR_REV(reg) (((reg) & GENMASK(16, 11)) >> 11)
> +#define LICENSE_TYPE(reg) (((reg) & GENMASK(18, 17)) >> 17)
> +#define CONTROL_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x4 : 0x24)
> +#define ENGINE_EN BIT(0)
> +#define XFER_DONE BIT(1)
> +#define BUFF_BASE_ADDR_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x8 : 0x28)
> +#define BUFF_LEN_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0xC : 0x2C)
> +#define FIFO_STAT_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x10 : 0x30)
> +#define INTR_MASK_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x14 : 0x34)
> +#define XFER_DONE_INTR BIT(31)
> +#define INTR_STAT_REG(s) ((s) == SNDRV_PCM_STREAM_PLAYBACK ? 0x18 : 0x38)
> +#define FIFO_COUNT(reg) ((reg) >> 20)
> +
> +#define BYTES_TO_WORDS(n) ((n) / 4)
> +
> +/* Arbitrarily chosen period size */
> +#define PCM_PERIOD_WORDS SZ_8K
> +#define PCM_PERIOD_BYTES (PCM_PERIOD_WORDS * 4)
> +/* This is the actual maximum size that can actually be moved in one chunk */
> +#define PCM_BUF_WORDS (SZ_64K - 1)
> +#define PCM_BUF_BYTES (PCM_BUF_WORDS * 4)
> +
> +struct xlnx_logicpd_i2s;
> +
> +/**
> + * struct xlnx_logicpd_stream - Internal stream representation
> + *
> + * @i2s: Chip data
> + * @substream: Core substream structure
> + * @period_idx: Index of the period within the circular buffer
> + */
> +struct xlnx_logicpd_stream {
> + struct xlnx_logicpd_i2s *i2s;
> + struct snd_pcm_substream *substream;
> + unsigned int period_idx;
> +};
> +
> +/**
> + * struct xlnx_logicpd_i2s - Chip structure
> + *
> + * @base: Registers base address
> + * @streams: Playback and capture streams in an array
> + */
> +struct xlnx_logicpd_i2s {
> + void __iomem *base;
> + struct xlnx_logicpd_stream streams[2];
> +};
> +
> +static struct xlnx_logicpd_i2s *substream_to_cpu_dai_chip(struct snd_pcm_substream *substream)
> +{
> + struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
> +
> + return snd_soc_dai_get_drvdata(rtd->cpu_dai);
> +}
> +
> +/* PCM methods */
> +
> +static const struct snd_pcm_hardware xlnx_logicpd_pcm_hardware = {
> + .info = SNDRV_PCM_INFO_MMAP |
> + SNDRV_PCM_INFO_MMAP_VALID |
> + SNDRV_PCM_INFO_INTERLEAVED |
> + SNDRV_PCM_INFO_HALF_DUPLEX,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .rate_min = 8000,
> + .rate_max = 192000,
> + .channels_min = 2,
> + .channels_max = 2,
> + .period_bytes_min = 0,
> + .period_bytes_max = PCM_PERIOD_BYTES,
> + .periods_min = 0,
> + .periods_max = -1,
> + .buffer_bytes_max = PCM_BUF_BYTES,
> +};
> +
> +static int xlnx_logicpd_pcm_open(struct snd_pcm_substream *substream)
> +{
> + struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
> + unsigned int dir = substream->stream;
> +
> + snd_soc_set_runtime_hwparams(substream, &xlnx_logicpd_pcm_hardware);
> +
> + i2s->streams[dir].substream = substream;
> +
> + return 0;
> +}
> +
> +static int xlnx_logicpd_pcm_close(struct snd_pcm_substream *substream)
> +{
> + struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
> + unsigned int dir = substream->stream;
> +
> + i2s->streams[dir].substream = NULL;
> +
> + return 0;
> +}
> +
> +static int xlnx_logicpd_pcm_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params)
> +{
> + struct snd_pcm_runtime *runtime = substream->runtime;
> +
> + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
> + runtime->dma_bytes = params_buffer_bytes(params);
> +
> + return 0;
> +}
> +
> +static snd_pcm_uframes_t xlnx_logicpd_pcm_pointer(struct snd_pcm_substream *substream)
> +{
> + struct xlnx_logicpd_i2s *i2s = substream_to_cpu_dai_chip(substream);
> + struct snd_pcm_runtime *runtime = substream->runtime;
> + unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
> + unsigned int dir = substream->stream;
> +
> + return bytes_to_frames(runtime,
> + i2s->streams[dir].period_idx * period_sz);
> +}
> +
> +static int xlnx_logicpd_pcm_mmap(struct snd_pcm_substream *substream,
> + struct vm_area_struct *vma)
> +{
> + return remap_pfn_range(vma, vma->vm_start,
> + substream->dma_buffer.addr >> PAGE_SHIFT,
> + vma->vm_end - vma->vm_start, vma->vm_page_prot);
> +}
> +
> +static const struct snd_pcm_ops xlnx_logicpd_pcm_ops = {
> + .open = xlnx_logicpd_pcm_open,
> + .close = xlnx_logicpd_pcm_close,
> + .ioctl = snd_pcm_lib_ioctl,
> + .hw_params = xlnx_logicpd_pcm_hw_params,
> + .pointer = xlnx_logicpd_pcm_pointer,
> + .mmap = xlnx_logicpd_pcm_mmap,
> +};
> +
> +static int xlnx_logicpd_pcm_new(struct snd_soc_pcm_runtime *rtd)
> +{
> + struct snd_pcm *pcm = rtd->pcm;
> + struct snd_pcm_substream *substream;
> + struct snd_dma_buffer *buf;
> + int dir;
> +
> + for (dir = SNDRV_PCM_STREAM_PLAYBACK;
> + dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
> + substream = pcm->streams[dir].substream;
> + if (!substream)
> + continue;
> +
> + buf = &substream->dma_buffer;
> + buf->area = dma_alloc_coherent(pcm->card->dev, PCM_BUF_BYTES,
> + &buf->addr, GFP_KERNEL);
> + buf->bytes = PCM_BUF_BYTES;
> + if (!buf->area)
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static void xlnx_logicpd_pcm_free(struct snd_pcm *pcm)
> +{
> + struct snd_pcm_substream *substream;
> + struct snd_dma_buffer *buf;
> + int dir;
> +
> + for (dir = SNDRV_PCM_STREAM_PLAYBACK;
> + dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
> + substream = pcm->streams[dir].substream;
> + if (!substream)
> + continue;
> +
> + buf = &substream->dma_buffer;
> + if (!buf->area)
> + continue;
> +
> + dma_free_coherent(pcm->card->dev, buf->bytes,
> + buf->area, buf->addr);
> + buf->area = NULL;
> + }
> +}
> +
> +static const struct snd_soc_component_driver xlnx_logicpd_pcm_component = {
> + .name = "xlnx-logicp-pcm",
> + .ops = &xlnx_logicpd_pcm_ops,
> + .pcm_new = xlnx_logicpd_pcm_new,
> + .pcm_free = xlnx_logicpd_pcm_free,
> +};
> +
> +/* DAI methods */
> +
> +static void xlnx_logicpd_dai_int_en(struct xlnx_logicpd_i2s *i2s, int dir)
> +{
> + u32 reg;
> +
> + reg = readl_relaxed(i2s->base + INTR_MASK_REG(dir));
> + reg &= ~XFER_DONE_INTR;
> + writel(reg, i2s->base + INTR_MASK_REG(dir));
> +}
> +
> +static void xlnx_logicpd_dai_int_dis(struct xlnx_logicpd_i2s *i2s, int dir)
> +{
> + u32 reg;
> +
> + reg = readl_relaxed(i2s->base + INTR_MASK_REG(dir));
> + reg |= XFER_DONE_INTR;
> + writel_relaxed(reg, i2s->base + INTR_MASK_REG(dir));
> +}
> +
> +static irqreturn_t xlnx_logicpd_dai_isr(int irq, void *dev_id)
> +{
> + struct xlnx_logicpd_stream *stream = dev_id;
> + struct xlnx_logicpd_i2s *i2s = stream->i2s;
> + struct snd_pcm_substream *substream = stream->substream;
> + unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
> + unsigned int buf_sz = snd_pcm_lib_buffer_bytes(substream);
> + dma_addr_t buf_addr = substream->dma_buffer.addr;
> + unsigned int dir = substream->stream;
> + u32 reg;
> +
> + /* Reading INTR_STAT deasserts the host interrupt */
> + reg = readl_relaxed(i2s->base + INTR_STAT_REG(dir));
> +
> + /*
> + * When the XFER_DONE interrupt is triggered, it means the period has
> + * been entirely shifted into the FIFO. At this point, we can move the
> + * buffer pointer to the next period and ask to transfer another chunk
> + * of data. Whenever the FIFO will be at its "almost full" state (4096
> + * words minus the threshold of 100 words) the internal DMA engine will
> + * automatically restart shifting data to the FIFO until its full state.
> + * Hence, the host has up to 3996 words (in our case, 3996 frames) to
> + * serve the interrupt before an underrun that would happen, at eg.
> + * 44100Hz, after 90ms.
> + */
> + if (reg & XFER_DONE_INTR) {
> + unsigned int offset_in_buf = ++stream->period_idx * period_sz;
> +
> + if (offset_in_buf >= buf_sz) {
> + stream->period_idx = 0;
> + offset_in_buf = stream->period_idx * period_sz;
> + }
> +
> + /* Move on to the next period in the overall buffer */
> + writel_relaxed(buf_addr + offset_in_buf,
> + i2s->base + BUFF_BASE_ADDR_REG(dir));
> + /* The last period might be smaller, update length if needed */
> + period_sz = min(period_sz, buf_sz - offset_in_buf);
> + writel_relaxed(BYTES_TO_WORDS(period_sz),
> + i2s->base + BUFF_LEN_REG(dir));
> +
> + /* Inform the PCM middle-layer */
> + snd_pcm_period_elapsed(substream);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int xlnx_logicpd_dai_trigger(struct snd_pcm_substream *substream,
> + int cmd, struct snd_soc_dai *dai)
> +{
> + struct xlnx_logicpd_i2s *i2s = snd_soc_dai_get_drvdata(dai);
> + unsigned int period_sz = snd_pcm_lib_period_bytes(substream);
> + dma_addr_t buf_addr = substream->dma_buffer.addr;
> + unsigned int dir = substream->stream;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + i2s->streams[dir].period_idx = 0;
> + /* Disable the other engine if enabled */
> + if (readl(i2s->base + CONTROL_REG(!dir)) & ENGINE_EN)
> + writel(0, i2s->base + CONTROL_REG(!dir));
> + /* Enable the desired engine */
> + writel_relaxed(ENGINE_EN, i2s->base + CONTROL_REG(dir));
> + /* Set the buffer start address */
> + writel_relaxed(buf_addr, i2s->base + BUFF_BASE_ADDR_REG(dir));
> + /* Enable the XFER_DONE IRQ, signaling the end of the period */
> + xlnx_logicpd_dai_int_en(i2s, dir);
> + /* Actually start the internal DMA engine */
> + writel(BYTES_TO_WORDS(period_sz),
> + i2s->base + BUFF_LEN_REG(dir));
> + break;
> + case SNDRV_PCM_TRIGGER_STOP:
> + /* Disable the interrupts */
> + xlnx_logicpd_dai_int_dis(i2s, dir);
> + /* Ensure the host IRQ is deasserted */
> + readl_relaxed(i2s->base + INTR_STAT_REG(dir));
> + break;
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static const struct snd_soc_dai_ops xlnx_logicpd_dai_ops = {
> + .trigger = xlnx_logicpd_dai_trigger,
> +};
> +
> +static int xlnx_logicpd_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct xlnx_logicpd_i2s *i2s = snd_soc_dai_get_drvdata(dai);
> + unsigned int dir;
> +
> + for (dir = SNDRV_PCM_STREAM_PLAYBACK;
> + dir <= SNDRV_PCM_STREAM_CAPTURE; dir++) {
> + i2s->streams[dir].i2s = i2s;
> +
> + /* Reset the transmitter/receiver engine */
> + writel_relaxed(0, i2s->base + CONTROL_REG(dir));
> + /* Mask all interrupts */
> + writel_relaxed(GENMASK(31, 0), i2s->base + INTR_MASK_REG(dir));
> + }
> +
> + return 0;
> +}
> +
> +struct snd_soc_dai_driver xlnx_logicpd_dai = {
> + .name = "xylinx-logicpd-dai",
> + .probe = xlnx_logicpd_dai_probe,
> + .capture = {
> + .stream_name = "Capture",
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .rate_min = 8000,
> + .rate_max = 192000,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + },
> + .playback = {
> + .stream_name = "Playback",
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = SNDRV_PCM_RATE_8000_192000,
> + .rate_min = 8000,
> + .rate_max = 192000,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + },
> + .symmetric_rates = 1,
> + .ops = &xlnx_logicpd_dai_ops,
> +};
> +
> +static const struct snd_soc_component_driver xlnx_logicpd_i2s_component = {
> + .name = DRV_NAME,
> + .ops = &xlnx_logicpd_pcm_ops,
> +};
> +
> +static const struct of_device_id xlnx_logicpd_i2s_of_match[] = {
> + {
> + .compatible = "xlnx,logicpd-i2s-dai",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, xlnx_logicpd_i2s_of_match);
> +
> +static int xlnx_logicpd_i2s_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct xlnx_logicpd_i2s *i2s;
> + struct xlnx_logicpd_stream *stream;
> + int tx_irq, rx_irq, ret;
> + u32 reg;
> +
> + i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
> + if (!i2s)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, i2s);
> +
> + i2s->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(i2s->base))
> + return PTR_ERR(i2s->base);
> +
> + stream = &i2s->streams[SNDRV_PCM_STREAM_PLAYBACK];
> + tx_irq = platform_get_irq_byname(pdev, "tx");
> + if (tx_irq > 0) {
> + ret = devm_request_irq(dev, tx_irq, xlnx_logicpd_dai_isr,
> + 0, "logicpd-i2s-tx", stream);
> + if (ret)
> + return ret;
> + } else {
> + dev_err(dev, "TX IRQ not available (%d), disabling playback\n",
> + tx_irq);
> + tx_irq = 0;
> + }
> +
> + stream = &i2s->streams[SNDRV_PCM_STREAM_CAPTURE];
> + rx_irq = platform_get_irq_byname(pdev, "rx");
> + if (rx_irq > 0) {
> + ret = devm_request_irq(dev, rx_irq, xlnx_logicpd_dai_isr,
> + 0, "logicpd-i2s-rx", stream);
> + if (ret)
> + return ret;
> + } else {
> + dev_err(dev, "RX IRQ not available (%d), disabling capture\n",
> + rx_irq);
> + rx_irq = 0;
> + }
> +
> + if (!tx_irq && !rx_irq)
> + return -EINVAL;
> +
> + ret = devm_snd_soc_register_component(dev, &xlnx_logicpd_pcm_component,
> + NULL, 0);
> + if (ret) {
> + dev_err(dev, "cannot register PCM component (%d)\n", ret);
> + return ret;
> + }
> +
> + ret = devm_snd_soc_register_component(dev, &xlnx_logicpd_i2s_component,
> + &xlnx_logicpd_dai, 1);
> + if (ret) {
> + dev_err(dev, "cannot register I2S component (%d)\n", ret);
> + return ret;
> + }
> +
> + reg = readl_relaxed(i2s->base + IP_VERSION);
> + dev_info(dev, "%s DAI version %u.%u.%c (license: %s) registered\n",
> + xlnx_logicpd_dai.name,
> + (unsigned int)MAJOR_REV(reg),
> + (unsigned int)MINOR_REV(reg),
> + (char)PATCH_LEVEL(reg),
> + LICENSE_TYPE(reg) == 0 ? "source" :
> + (LICENSE_TYPE(reg) == 1 ? "eval" : "release"));
> +
> + return ret;
> +}
> +
> +static struct platform_driver xlnx_logicpd_i2s_driver = {
> + .driver = {
> + .name = DRV_NAME,
> + .of_match_table = xlnx_logicpd_i2s_of_match,
> + },
> + .probe = xlnx_logicpd_i2s_probe,
> +};
> +
> +module_platform_driver(xlnx_logicpd_i2s_driver);
> +
> +MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
> +MODULE_DESCRIPTION("Xilinx logicPD I2S module");
> +MODULE_LICENSE("GPL v2");
>
_______________________________________________
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^ permalink raw reply
* Re: [PATCH 1/2] drm/mediatek: Support CMDQ interface in ddp component
From: Nicolas Boichat @ 2019-09-02 7:44 UTC (permalink / raw)
To: Bibby Hsieh
Cc: Yongqiang Niu, David Airlie, Daniel Vetter, lkml, dri-devel,
Tomasz Figa, YT Shen, CK Hu, Thierry Reding,
moderated list:ARM/Mediatek SoC support, Philipp Zabel,
Matthias Brugger, linux-arm Mailing List
In-Reply-To: <20190830074103.16671-2-bibby.hsieh@mediatek.com>
On Fri, Aug 30, 2019 at 3:41 PM Bibby Hsieh <bibby.hsieh@mediatek.com> wrote:
>
> The CMDQ (Command Queue) in MT8183 is used to help
> update all relevant display controller registers
> with critical time limation.
> This patch add cmdq interface in ddp_comp interface,
> let all ddp_comp interface can support cpu/cmdq function
> at the same time.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> Signed-off-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 78 +++++++-------
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 66 ++++++------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 110 ++++++++++++++------
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 53 ++++++----
> 5 files changed, 187 insertions(+), 127 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> index f33d98b356d6..c5d3e3cf8ad5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> @@ -9,6 +9,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
>
> static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_color *color = comp_to_color(comp);
>
> - writel(w, comp->regs + DISP_COLOR_WIDTH(color));
> - writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
> + mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));
> + mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));
> }
>
> static void mtk_color_start(struct mtk_ddp_comp *comp)
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 94c80c215c6e..f11c785199d3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -9,6 +9,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -120,14 +121,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
>
> static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> if (w != 0 && h != 0)
> - writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
> - writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
> + mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
> + DISP_REG_OVL_ROI_SIZE);
> + mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
>
> - writel(0x1, comp->regs + DISP_REG_OVL_RST);
> - writel(0x0, comp->regs + DISP_REG_OVL_RST);
> + mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
> + mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
> }
>
> static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
> @@ -137,7 +139,8 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
> return ovl->data->layer_nr;
> }
>
> -static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
> +static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> {
> unsigned int reg;
> unsigned int gmc_thrshd_l;
> @@ -145,8 +148,8 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
> unsigned int gmc_value;
> struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
>
> - writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
> -
> + mtk_ddp_write(cmdq_pkt, 0x1, comp,
> + DISP_REG_OVL_RDMA_CTRL(idx));
> gmc_thrshd_l = GMC_THRESHOLD_LOW >>
> (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
> gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
> @@ -156,22 +159,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
> else
> gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
> gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
> - writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
> -
> - reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
> - reg = reg | BIT(idx);
> - writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
You get rid of all uses of the "reg" variable, so please drop the
declaration too.
> + mtk_ddp_write(cmdq_pkt, gmc_value,
> + comp, DISP_REG_OVL_RDMA_GMC(idx));
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
> + DISP_REG_OVL_SRC_CON, BIT(idx));
> }
>
> -static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
> +static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> {
> - unsigned int reg;
> -
> - reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
> - reg = reg & ~BIT(idx);
> - writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
> -
> - writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
> + mtk_ddp_write_mask(cmdq_pkt, 0, comp,
> + DISP_REG_OVL_SRC_CON, BIT(idx));
> + mtk_ddp_write(cmdq_pkt, 0, comp,
> + DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
> @@ -211,7 +211,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
> }
>
> static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> - struct mtk_plane_state *state)
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> struct mtk_plane_pending_state *pending = &state->pending;
> @@ -223,38 +224,37 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> unsigned int con;
>
> if (!pending->enable)
> - mtk_ovl_layer_off(comp, idx);
> + mtk_ovl_layer_off(comp, idx, cmdq_pkt);
>
> con = ovl_fmt_convert(ovl, fmt);
> if (idx != 0)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> - writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
> - writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
> - writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
> - writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
> - writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
> + DISP_REG_OVL_CON(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
> + DISP_REG_OVL_PITCH(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
> + DISP_REG_OVL_SRC_SIZE(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
> + DISP_REG_OVL_OFFSET(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
> + DISP_REG_OVL_ADDR(ovl, idx));
>
> if (pending->enable)
> - mtk_ovl_layer_on(comp, idx);
> + mtk_ovl_layer_on(comp, idx, cmdq_pkt);
> }
>
> static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
> {
> - unsigned int reg;
> -
> - reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> - reg = reg | OVL_BGCLR_SEL_IN;
> - writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + mtk_ddp_write_mask(NULL, OVL_BGCLR_SEL_IN, comp,
> + DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN);
> }
>
> static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
> {
> - unsigned int reg;
> -
> - reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> - reg = reg & ~OVL_BGCLR_SEL_IN;
> - writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + mtk_ddp_write_mask(NULL, 0, comp,
> + DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN);
> }
>
> static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 24945fec00b1..6df372dac3e3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -9,6 +9,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -86,23 +87,14 @@ static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> -static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg,
> - unsigned int mask, unsigned int val)
> -{
> - unsigned int tmp = readl(comp->regs + reg);
> -
> - tmp = (tmp & ~mask) | (val & mask);
> - writel(tmp, comp->regs + reg);
> -}
> -
> static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
> struct drm_crtc *crtc)
> {
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
>
> rdma->crtc = crtc;
> - rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
> - RDMA_FRAME_END_INT);
> + mtk_ddp_write_mask(NULL, RDMA_FRAME_END_INT, comp,
> + DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT);
> }
>
> static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
> @@ -110,31 +102,35 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
>
> rdma->crtc = NULL;
> - rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
> + mtk_ddp_write_mask(NULL, 0, comp,
> + DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT);
> }
>
> static void mtk_rdma_start(struct mtk_ddp_comp *comp)
> {
> - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
> - RDMA_ENGINE_EN);
> + mtk_ddp_write_mask(NULL, RDMA_ENGINE_EN, comp,
> + DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN);
> }
>
> static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
> {
> - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
> + mtk_ddp_write_mask(NULL, 0, comp,
> + DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN);
> }
>
> static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> unsigned int height, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> unsigned int threshold;
> unsigned int reg;
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> u32 rdma_fifo_size;
>
> - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
> + mtk_ddp_write_mask(cmdq_pkt, width, comp,
> + DISP_REG_RDMA_SIZE_CON_0, 0xfff);
> + mtk_ddp_write_mask(cmdq_pkt, height, comp,
> + DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
>
> if (rdma->fifo_size)
> rdma_fifo_size = rdma->fifo_size;
> @@ -151,7 +147,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> reg = RDMA_FIFO_UNDERFLOW_EN |
> RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> - writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> + mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
> }
>
> static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
> @@ -197,7 +193,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
> }
>
> static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> - struct mtk_plane_state *state)
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> struct mtk_plane_pending_state *pending = &state->pending;
> @@ -207,24 +204,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> unsigned int con;
>
> con = rdma_fmt_convert(rdma, fmt);
> - writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
> + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
>
> if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
> - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
> - RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
> - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
> - RDMA_MATRIX_INT_MTX_SEL,
> - RDMA_MATRIX_INT_MTX_BT601_to_RGB);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,
> + DISP_REG_RDMA_SIZE_CON_0,
> + RDMA_MATRIX_ENABLE);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
> + comp, DISP_REG_RDMA_SIZE_CON_0,
> + RDMA_MATRIX_INT_MTX_SEL);
> } else {
> - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
> - RDMA_MATRIX_ENABLE, 0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, comp,
> + DISP_REG_RDMA_SIZE_CON_0,
> + RDMA_MATRIX_ENABLE);
> }
> + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
> + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
> + mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
> + DISP_RDMA_MEM_GMC_SETTING_0);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
> + DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
>
> - writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
> - writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
> - writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
> - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
> - RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
> }
>
> static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8fea98578bc8..76416c1cbb28 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -13,6 +13,7 @@
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <drm/drmP.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> #include "mtk_drm_drv.h"
> #include "mtk_drm_plane.h"
> #include "mtk_drm_ddp_comp.h"
> @@ -76,36 +77,76 @@
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
>
> +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> + struct mtk_ddp_comp *comp, unsigned int offset)
> +{
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt)
> + cmdq_pkt_write(cmdq_pkt, comp->subsys,
> + comp->regs_pa + offset, value);
> + else
> + writel(value, comp->regs + offset);
> +}
> +
> +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> + struct mtk_ddp_comp *comp,
> + unsigned int offset)
> +{
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt)
> + cmdq_pkt_write(cmdq_pkt, comp->subsys,
> + comp->regs_pa + offset, value);
> + else
> + writel_relaxed(value, comp->regs + offset);
> +}
> +
> +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
> + unsigned int value,
> + struct mtk_ddp_comp *comp,
> + unsigned int offset,
> + unsigned int mask)
> +{
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt) {
> + cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,
> + comp->regs_pa + offset, value, mask);
> + } else {
> + u32 tmp = readl(comp->regs + offset);
> +
> + tmp = (tmp & ~mask) | (value & mask);
> + writel(tmp, comp->regs + offset);
> + }
> +}
> +
> void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
> - unsigned int CFG)
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> {
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - writel(0, comp->regs + DISP_DITHER_5);
> - writel(0, comp->regs + DISP_DITHER_7);
> - writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> - DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> - DITHER_NEW_BIT_MODE,
> - comp->regs + DISP_DITHER_15);
> - writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> - DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> - DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> - DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - comp->regs + DISP_DITHER_16);
> - writel(DISP_DITHERING, comp->regs + CFG);
> + mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_NEW_BIT_MODE,
> + comp, DISP_DITHER_15);
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> + comp, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
> }
> }
>
> static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
> - writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
> - mtk_dither_set(comp, bpc, DISP_OD_CFG);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
> + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
> + mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
> }
>
> static void mtk_od_start(struct mtk_ddp_comp *comp)
> @@ -120,9 +161,9 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
>
> static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> }
>
> static void mtk_aal_start(struct mtk_ddp_comp *comp)
> @@ -137,10 +178,10 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
>
> static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE);
> - writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG);
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> + mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
> }
>
> static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> @@ -155,10 +196,10 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
>
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE);
> - writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG);
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct mtk_ddp_comp *comp)
> @@ -173,10 +214,10 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
>
> static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> - unsigned int bpc)
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
> - mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
> + mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
> }
>
> static void mtk_gamma_start(struct mtk_ddp_comp *comp)
> @@ -190,24 +231,25 @@ static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
> }
>
> static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> - struct drm_crtc_state *state)
> + struct drm_crtc_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> {
> - unsigned int i, reg;
> + unsigned int i;
> struct drm_color_lut *lut;
> void __iomem *lut_base;
> u32 word;
>
> if (state->gamma_lut) {
> - reg = readl(comp->regs + DISP_GAMMA_CFG);
> - reg = reg | GAMMA_LUT_EN;
> - writel(reg, comp->regs + DISP_GAMMA_CFG);
> + mtk_ddp_write_mask(cmdq_pkt, GAMMA_LUT_EN, comp,
> + DISP_GAMMA_CFG, GAMMA_LUT_EN);
> lut_base = comp->regs + DISP_GAMMA_LUT;
> lut = (struct drm_color_lut *)state->gamma_lut->data;
> for (i = 0; i < MTK_LUT_SIZE; i++) {
> word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
> (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
> ((lut[i].blue >> 6) & LUT_10BIT_MASK);
> - writel(word, (lut_base + i * 4));
> + mtk_ddp_write(cmdq_pkt, word, comp,
> + (unsigned int)(lut_base + i * 4));
> }
> }
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 268d416081da..6bbc35f92815 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -69,21 +69,26 @@ enum mtk_ddp_comp_id {
> };
>
> struct mtk_ddp_comp;
> -
> +struct cmdq_pkt;
> struct mtk_ddp_comp_funcs {
> void (*config)(struct mtk_ddp_comp *comp, unsigned int w,
> - unsigned int h, unsigned int vrefresh, unsigned int bpc);
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void (*start)(struct mtk_ddp_comp *comp);
> void (*stop)(struct mtk_ddp_comp *comp);
> void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
> void (*disable_vblank)(struct mtk_ddp_comp *comp);
> unsigned int (*layer_nr)(struct mtk_ddp_comp *comp);
> - void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx);
> - void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx);
> + void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> + void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
> - struct mtk_plane_state *state);
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> void (*gamma_set)(struct mtk_ddp_comp *comp,
> - struct drm_crtc_state *state);
> + struct drm_crtc_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
> void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> };
> @@ -98,10 +103,11 @@ struct mtk_ddp_comp {
>
> static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
> unsigned int w, unsigned int h,
> - unsigned int vrefresh, unsigned int bpc)
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> {
> if (comp->funcs && comp->funcs->config)
> - comp->funcs->config(comp, w, h, vrefresh, bpc);
> + comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt);
> }
>
> static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp)
> @@ -138,32 +144,36 @@ static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp)
> }
>
> static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp,
> - unsigned int idx)
> + unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> {
> if (comp->funcs && comp->funcs->layer_on)
> - comp->funcs->layer_on(comp, idx);
> + comp->funcs->layer_on(comp, idx, cmdq_pkt);
> }
>
> static inline void mtk_ddp_comp_layer_off(struct mtk_ddp_comp *comp,
> - unsigned int idx)
> + unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> {
> if (comp->funcs && comp->funcs->layer_off)
> - comp->funcs->layer_off(comp, idx);
> + comp->funcs->layer_off(comp, idx, cmdq_pkt);
> }
>
> static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp,
> unsigned int idx,
> - struct mtk_plane_state *state)
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> {
> if (comp->funcs && comp->funcs->layer_config)
> - comp->funcs->layer_config(comp, idx, state);
> + comp->funcs->layer_config(comp, idx, state, cmdq_pkt);
> }
>
> static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp,
> - struct drm_crtc_state *state)
> + struct drm_crtc_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> {
> if (comp->funcs && comp->funcs->gamma_set)
> - comp->funcs->gamma_set(comp, state);
> + comp->funcs->gamma_set(comp, state, cmdq_pkt);
> }
>
> static inline void mtk_ddp_comp_bgclr_in_on(struct mtk_ddp_comp *comp)
> @@ -186,6 +196,13 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
> int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp);
> void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp);
> void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
> - unsigned int CFG);
> -
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt);
> +enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
> +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> + struct mtk_ddp_comp *comp, unsigned int offset);
> +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> + struct mtk_ddp_comp *comp, unsigned int offset);
> +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
> + struct mtk_ddp_comp *comp, unsigned int offset,
> + unsigned int mask);
> #endif /* MTK_DRM_DDP_COMP_H */
> --
> 2.18.0
>
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^ permalink raw reply
* Re: [PATCH] phy: tegra: xusb: remove unused variable
From: Thierry Reding @ 2019-09-02 7:48 UTC (permalink / raw)
To: Chunfeng Yun
Cc: JC Kuo, linux-kernel, Jonathan Hunter, linux-tegra,
linux-mediatek, Matthias Brugger, Kishon Vijay Abraham I,
linux-arm-kernel
In-Reply-To: <1567394159-22572-1-git-send-email-chunfeng.yun@mediatek.com>
[-- Attachment #1.1: Type: text/plain, Size: 327 bytes --]
On Mon, Sep 02, 2019 at 11:15:59AM +0800, Chunfeng Yun wrote:
> The local variable @priv is set but not used, can be removed
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> drivers/phy/tegra/xusb-tegra210.c | 3 ---
> 1 file changed, 3 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* [RFC,v5, 2/5] dts: arm64: mt8183: Add ISP Pass 1 nodes
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <20190902075135.1332-1-jungo.lin@mediatek.com>
Add nodes for Pass 1 unit of Mediatek's camera ISP system.
Pass 1 unit embedded in Mediatek SoCs, works with the
co-processor to process image signal from the image sensor
and output RAW image data.
Signed-off-by: Jungo Lin <jungo.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 66aaa07f6cec..0d607342d4f1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -505,5 +505,35 @@
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ camisp: camisp@1a000000 {
+ compatible = "mediatek,mt8183-camisp";
+ reg = <0 0x1a000000 0 0x1000>,
+ <0 0x1a003000 0 0x1000>,
+ <0 0x1a004000 0 0x2000>,
+ <0 0x1a006000 0 0x2000>,
+ <0 0x1a008000 0 0x2000>;
+ reg-names = "cam_sys",
+ "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ iommus = <&iommu M4U_PORT_CAM_IMGO>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_CAMTG>;
+ clock-names = "camsys_cam_cgpdn",
+ "camsys_camtg_cgpdn";
+ mediatek,larb = <&larb3>,
+ <&larb6>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
+ mediatek,scp = <&scp>;
+ };
};
};
--
2.18.0
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^ permalink raw reply related
* [RFC,v5, 3/5] media: videodev2.h: Add new boottime timestamp type
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <20190902075135.1332-1-jungo.lin@mediatek.com>
For Camera AR(Augmented Reality) application requires camera timestamps
to be reported with CLOCK_BOOTTIME to sync timestamp with other sensor
sources.
The boottime timestamp is identical to monotonic timestamp,
except it also includes any time that the system is suspended.
Signed-off-by: Jungo Lin <jungo.lin@mediatek.com>
---
Documentation/media/uapi/v4l/buffer.rst | 11 ++++++++++-
include/uapi/linux/videodev2.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/media/uapi/v4l/buffer.rst b/Documentation/media/uapi/v4l/buffer.rst
index 1cbd9cde57f3..9e636f4118f5 100644
--- a/Documentation/media/uapi/v4l/buffer.rst
+++ b/Documentation/media/uapi/v4l/buffer.rst
@@ -649,13 +649,22 @@ Buffer Flags
- 0x00002000
- The buffer timestamp has been taken from the ``CLOCK_MONOTONIC``
clock. To access the same clock outside V4L2, use
- :c:func:`clock_gettime`.
+ :c:func:`clock_gettime` using clock IDs ``CLOCK_MONOTONIC``.
* .. _`V4L2-BUF-FLAG-TIMESTAMP-COPY`:
- ``V4L2_BUF_FLAG_TIMESTAMP_COPY``
- 0x00004000
- The CAPTURE buffer timestamp has been taken from the corresponding
OUTPUT buffer. This flag applies only to mem2mem devices.
+ * .. _`V4L2_BUF_FLAG_TIMESTAMP_BOOTIME`:
+
+ - ``V4L2_BUF_FLAG_TIMESTAMP_BOOTIME``
+ - 0x00008000
+ - The buffer timestamp has been taken from the ``CLOCK_BOOTTIME``
+ clock. To access the same clock outside V4L2, use
+ :c:func:`clock_gettime` using clock IDs ``CLOCK_BOOTTIME``.
+ Identical to CLOCK_MONOTONIC, except it also includes any time that
+ the system is suspended.
* .. _`V4L2-BUF-FLAG-TSTAMP-SRC-MASK`:
- ``V4L2_BUF_FLAG_TSTAMP_SRC_MASK``
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 9d9705ceda76..a4fd271348e7 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1043,6 +1043,8 @@ static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv)
#define V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN 0x00000000
#define V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC 0x00002000
#define V4L2_BUF_FLAG_TIMESTAMP_COPY 0x00004000
+#define V4L2_BUF_FLAG_TIMESTAMP_BOOTIME 0x00008000
+
/* Timestamp sources. */
#define V4L2_BUF_FLAG_TSTAMP_SRC_MASK 0x00070000
#define V4L2_BUF_FLAG_TSTAMP_SRC_EOF 0x00000000
--
2.18.0
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^ permalink raw reply related
* [RFC, v5, 0/5] media: platform: mtk-isp: Add Mediatek ISP Pass 1 driver
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <Jungo Lin <jungo.lin@mediatek.com>
Hello,
This RFC patch series adding the driver for Pass 1 (P1) unit in
Mediatek's camera ISP system on mt8183 SoC, which will be used in
camera features of CrOS. It's the first time Mediatek develops
ISP kernel drivers based on V4L2 and media controller framework.
I posted the main part of the ISP Pass 1 driver as RFC to discuss
first and would like some review comments on the overall architecture
of the driver.
Pass 1 unit processes image signal from sensor devices and accepts the
tuning parameters to adjust the image quality. It performs optical
black correction, defect pixel correction, W/IR imbalance correction
and lens shading correction for RAW processing.
The driver is implemented with V4L2 and media controller framework so
we have the following entities to describe the ISP pass 1 path.
(The current metadata interface used in meta input and partial meta
nodes is only a temporary solution to kick off the driver development
and is not ready to be reviewed yet.)
1. meta input (output video device): connect to ISP P1 sub device.
It accepts the tuning buffer from user.
2. ISP P1 (sub device): connect to partial meta 0/1/2/3,
main stream and packed out video devices. When processing an image,
Pass 1 hardware supports multiple output images with different sizes
and formats so it needs two capture video devices ("main stream" and
"packed out") to return the image data to the user.
3. main stream (capture video device): return the processed image data
which is used in capture scenario.
4. packed out (capture video device): return the processed image data
which is used in preview scenario.
5. partial meta 0 (capture video device): return the AE/AWB statistics.
6. partial meta 1 (capture video device): return the AF statistics.
7. partial meta 2 (capture video device): return the local contrast
enhanced statistics.
8. partial meta 3 (capture video device): return the local motion
vector statistics.
The overall patches of the series is:
* Patch 1 & 2 are dt-bindings & dts information related to ISP P1 driver.
* Patch 3 extends the original V4L2 image & meta formats for ISP P1 driver.
* Patch 4 is the heart of ISP P1 driver. It handles the ISP
HW configuration. Moreover, implement standard V4L2 video driver that utilizes
V4L2 and media framework APIs. Communicate with co-process via SCP communication
to compose ISP registers in the firmware.
Here is ISP P1 media topology:
It is included the main/sub sensor & sen-inf sub-devices which are implemented
in below patch[1][2][3]:
For Mediatek ISP P1 driver, it also depends on MT8183 SCP[6] & IOMMU[7] patchsets
/usr/bin/media-ctl -p -d /dev/media1
Media controller API version 4.19.59
Media device information
------------------------
driver mtk-cam-p1
model mtk-cam-p1
serial
bus info platform:1a000000.camisp
hw revision 0x0
driver version 4.19.67
Device topology
- entity 1: mtk-cam-p1 (12 pads, 8 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev5
pad0: Sink
<- "mtk-cam-p1 meta input":0 []
pad1: Source
-> "mtk-cam-p1 main stream":0 [ENABLED,IMMUTABLE]
pad2: Source
-> "mtk-cam-p1 packed out":0 []
pad3: Source
-> "mtk-cam-p1 partial meta 0":0 []
pad4: Source
-> "mtk-cam-p1 partial meta 1":0 []
pad5: Source
-> "mtk-cam-p1 partial meta 2":0 []
pad6: Source
-> "mtk-cam-p1 partial meta 3":0 []
pad7: Source
pad8: Source
pad9: Source
pad10: Source
pad11: Sink
<- "1a040000.seninf.mipi-csi":4 [ENABLED,IMMUTABLE]
- entity 14: mtk-cam-p1 meta input (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video25
pad0: Source
-> "mtk-cam-p1":0 []
- entity 20: mtk-cam-p1 main stream (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video26
pad0: Sink
<- "mtk-cam-p1":1 [ENABLED,IMMUTABLE]
- entity 26: mtk-cam-p1 packed out (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video27
pad0: Sink
<- "mtk-cam-p1":2 []
- entity 32: mtk-cam-p1 partial meta 0 (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video28
pad0: Sink
<- "mtk-cam-p1":3 []
- entity 38: mtk-cam-p1 partial meta 1 (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video29
pad0: Sink
<- "mtk-cam-p1":4 []
- entity 44: mtk-cam-p1 partial meta 2 (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video30
pad0: Sink
<- "mtk-cam-p1":5 []
- entity 50: mtk-cam-p1 partial meta 3 (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video31
pad0: Sink
<- "mtk-cam-p1":6 []
- entity 56: 1a040000.seninf.mipi-csi (12 pads, 3 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev6
pad0: Sink
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
<- "ov5695 2-0036":0 []
pad1: Sink
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
<- "ov2685 4-003c":0 []
pad2: Sink
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad3: Sink
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad4: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
-> "mtk-cam-p1":11 [ENABLED,IMMUTABLE]
pad5: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad6: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad7: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad8: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad9: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad10: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
pad11: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
- entity 69: ov5695 2-0036 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev7
pad0: Source
[fmt:SBGGR10_1X10/2592x1944 field:none colorspace:srgb]
-> "1a040000.seninf.mipi-csi":0 []
- entity 73: ov2685 4-003c (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev8
pad0: Source
[fmt:SBGGR10_1X10/1600x1200 field:none colorspace:srgb]
-> "1a040000.seninf.mipi-csi":1 []
===========
= history =
===========
version 5:
- Fixed Rob's comment on dt-binding format
- Fix Tomasz's comment in mtk_isp_pm_suspend function
- Support V4L2_BUF_FLAG_TIMESTAMP_BOOTTIME timestamp flag
and new timestamp type in driver
- Fix buffer en-queue timing issue in v4
- Remove default link_notify callback function in mtk_cam_media_ops
Todo:
- vb2_ops's buf_request_complete callback function implementation
- Add rst documents for Mediatek meta formats
- New meta buffer structure design & re-factoring
- Align and pack IPI comamnd structures for EC ROM size shrink
version 4:
- Fix Tomasz's comments which are addressed in MTK ISP P1 driver v3 patch[4]
- Fix some Tomasz comments which are addressed in DIP's v2 patch[5]
- Extend MTK proprietary image formats to support bayer order
- Support V4L2_BUF_FLAG_TSTAMP_SRC_SOE for capture devices
Todo:
- vb2_ops's buf_request_complete callback function implementation
- Add rst documents for Mediatek meta formats
- New meta buffer structure design & re-factoring
- Support V4L2_BUF_FLAG_TIMESTAMP_BOOTTIME timestamp flag
- Align and pack IPI comamnd structures for EC ROM size shrink
version 3:
- Remove ISP Pass 1 reserved memory device node and change to use SCP's
reserved memory region. (Rob Herring)
- Fix comments of ISP Pass 1 device node & dt-bindings document (Rob Herring)
- Revise ISP Pass1 Kconfig
- Add rst documents for Mediatek image formats (Hans Verkuil)
- Fix kernel warning messages when running v4l2_compliance test
- Move AFO buffer enqueue & de-queue from request API to non-request
- mtk_cam-ctrl.h/mtk_cam-ctrl.c
Revise Mediatek ISP Pass1 specific V4L2 control naming & file licence declaration (Hans Verkuil)
Split GET_BIN_INFO control into two controls to get width & height in-dependently (Hans Verkuil)
- mtk_cam-v4l2-util.h/mtk_cam-v4l2-util.c
Merging mtk_cam-dev.c and mtk_cam-v4l2-util.c. (Drew Davenport)
Remove the pix_mode argument in related functions and unreachable code. (Drew Davenport)
Fix Drew's comments which are addressed in v2 patch
Fix some Tomasz comments which are addressed in DIP's v1 patch[3]
- mtk_cam-regs.h / mtk_cam.h / mtk_cam.c
Fix Drew's comments which are addressed in v2 patch
Fix some Tomasz comments which are addressed in DIP's v1 patch[3]
Refactoring mtk_isp_config & mtk_isp_req_enqueue functions
- mtk_cam-scp.h / mtk_cam-scp.c
Move function declarations from mtk_cam.h to mtk_cam-scp.h (Drew Davenport)
Fix some Tomasz comments which are addressed in DIP's v1 patch[3]
Fix ISP de-initialize timing KE issue
- mtk_cam-smem.h / mtk_cam-smem-dev.c
Get the reserved shared memory via SCP driver (Tomasz Figa)
Todo:
- Add rst documents for Mediatek meta formats
- New meta buffer structure design & re-factoring
version 2:
- Add 3A enhancement feature which includes:
Separates 3A pipeline out of frame basis to improve
AE/AWB (exposure and white balance) performance.
Add 2 SCP sub-commands for 3A meta buffers.
- Add new child device to manage P1 shared memory between P1 HW unit
and co-processor.
- Remove mediatek,cam_smem.txt & cam_smem dts node in mt8183.dtsi.
- Revised document wording for dt-bindings documents & dts information.
- Remove mtk_cam-ctx.h & mtk_cam-dev-ctx-core.c and move these
source codes to mtk_cam-dev.h & mtk_cam-dev.c.
- mtk_cam-dev.h / mtk_cam-dev.c
Revised mtk_cam_video_device & mtk_cam_dev to remove unused structure fields
or add comments.
Revised buffer size for LMVO & LCSO.
Fix pixel format utility function.
Add vb2_dma_contig_set_max_seg_size to configure DMA max segment size.
- mtk_cam-v4l2-util.c
Refactoring V4L2 async mechanism with seninf driver only
Refactoring CIO (Connection IO) implementation with active sensor
Revised stream on function for 3A enhancement feature
Add new V4L2 en-queue/de-queue utility functions for 3A enhancement feature
- mtk_cam-regs.h / mtk_cam.h / mtk_cam.c
Add meta buffer index register definitions
Add meta DMA configuration function.
Separate with frame-base and non-frame-base en-queue/de-queue functions
Add isp_setup_scp_rproc function to get RPC handle
Add mtk_cam_reserved_memory_init for shared memory management
- mtk_cam-scp.h / mtk_cam-scp.c
Add new meta strictures for 3A enhancement feature
Add new IPI command utility function for 3A enhancement feature
Enhance isp_composer_dma_sg_init function flow
Shorten overall IPI command structure size
Remove scp_state state checking
Improve code readability
- mtk_cam-smem.h / mtk_cam-smem-dev.c
Add mtk_cam_alloc_smem_dev to allocate one new child device of ISP driver.
Handling P1 driver 's reserved memory & allocate DMA buffers based on this
memory region.
TODOs:
- 3A enhancement feature bug fixing
version 1:
- Revised driver sources based on Tomasz's comments including
part1/2/3/4 in RFC V0 patch.
- Remove DMA cache mechanism.
Support two new video devices (LCSO/LMVO) for advance camera
features.
- Fixed v4l2-compliance test failure items.
- Add private controls for Mediatek camera middle-ware.
- Replace VPU driver's APIs with new SCP driver interface for
co-processor communication.
- Refactoring mtk_cam_scp.c to use ring-buffers mechanism for IPI
commands RX handling.
- Fix internal bugs.
TODOs:
- Remove mtk_cam_smem_drv.c & mtk_cam_smem.h and implement DMA pool
for shared memory management.
- Revised file names.
- Support non frame-sync AFO/AAO DMA buffers
version 0:
- Initial submission
==================
Dependent patch
==================
Camera ISP P1 driver depends on seninf driver, SCP driver.
The patches are listed as following:
[1]. BACKPORT: FROMLIST: platform: mtk-isp: Add Mediatek sensor interface driver
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1482517
[2]. WIP: media: ov5695: support ov5695 sensor in mt8183
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1614887
[3]. WIP: media: ov2685: support ov2685 sensor in mt8183
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1614885
[4]. media: platform: mtk-isp: Add Mediatek ISP Pass 1 driver
https://patchwork.linuxtv.org/cover/56778/
[5]. [RFC,V2,4/6] platform: mtk-isp: Add Mediatek DIP driver
https://patchwork.linuxtv.org/patch/57472/
[6]. Add support for mt8183 SCP
https://patchwork.kernel.org/cover/11076543/
[7]. MT8183 IOMMU SUPPORT
https://patchwork.kernel.org/cover/10984739/
==================
Compliance test
==================
The v4l2-compliance is built with the below lastest patch.
https://git.linuxtv.org/v4l-utils.git/commit/?id=28be49b4e9d72c5866188cf5ba408541c665c921
Note 1.
This testing depends on the above seninf & sensors patches[1][2][3].
Note 2.
The current failure items are related to Mediatek seninf driver which
is under developing in other patchset.[1]
/usr/bin/v4l2-compliance -m /dev/media1
v4l2-compliance SHA: not available, 32 bits
Compliance test for mtk-cam-p1 device /dev/media1:
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Required ioctls:
test MEDIA_IOC_DEVICE_INFO: OK
Allow for multiple opens:
test second /dev/media1 open: OK
test MEDIA_IOC_DEVICE_INFO: OK
test for unlimited opens: OK
Media Controller ioctls:
test MEDIA_IOC_G_TOPOLOGY: OK
Entities: 11 Interfaces: 11 Pads: 33 Links: 21
test MEDIA_IOC_ENUM_ENTITIES/LINKS: OK
test MEDIA_IOC_SETUP_LINK: OK
Total for mtk-cam-p1 device /dev/media1: 7, Succeeded: 7, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video25:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x8c200000
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x0c200000
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000010
Type : V4L Video
Entity Info:
ID : 0x0000000e (14)
Name : mtk-cam-p1 meta input
Function : V4L2 I/O
Pad 0x0100000f : 0: Source
Link 0x02000012: to remote pad 0x1000002 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video25 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video25: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video26:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000016
Type : V4L Video
Entity Info:
ID : 0x00000014 (20)
Name : mtk-cam-p1 main stream
Function : V4L2 I/O
Pad 0x01000015 : 0: Sink
Link 0x02000018: from remote pad 0x1000003 of entity 'mtk-cam-p1': Data, Enabled, Immutable
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video26 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video26: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video27:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04201000
Video Capture Multiplanar
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x0300001c
Type : V4L Video
Entity Info:
ID : 0x0000001a (26)
Name : mtk-cam-p1 packed out
Function : V4L2 I/O
Pad 0x0100001b : 0: Sink
Link 0x0200001e: from remote pad 0x1000004 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video27 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video27: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video28:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84a00000
Metadata Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04a00000
Metadata Capture
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000022
Type : V4L Video
Entity Info:
ID : 0x00000020 (32)
Name : mtk-cam-p1 partial meta 0
Function : V4L2 I/O
Pad 0x01000021 : 0: Sink
Link 0x02000024: from remote pad 0x1000005 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video28 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video28: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video29:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84a00000
Metadata Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04a00000
Metadata Capture
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000028
Type : V4L Video
Entity Info:
ID : 0x00000026 (38)
Name : mtk-cam-p1 partial meta 1
Function : V4L2 I/O
Pad 0x01000027 : 0: Sink
Link 0x0200002a: from remote pad 0x1000006 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video29 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video29: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video30:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84a00000
Metadata Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04a00000
Metadata Capture
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x0300002e
Type : V4L Video
Entity Info:
ID : 0x0000002c (44)
Name : mtk-cam-p1 partial meta 2
Function : V4L2 I/O
Pad 0x0100002d : 0: Sink
Link 0x02000030: from remote pad 0x1000007 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video30 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video30: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/video31:
Driver Info:
Driver name : mtk-cam-p1
Card type : mtk-cam-p1
Bus info : platform:1a000000.camisp
Driver version : 4.19.67
Capabilities : 0x84a00000
Metadata Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04a00000
Metadata Capture
Streaming
Extended Pix Format
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000034
Type : V4L Video
Entity Info:
ID : 0x00000032 (50)
Name : mtk-cam-p1 partial meta 3
Function : V4L2 I/O
Pad 0x01000033 : 0: Sink
Link 0x02000036: from remote pad 0x1000008 of entity 'mtk-cam-p1': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video31 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK
Total for mtk-cam-p1 device /dev/video31: 45, Succeeded: 45, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/v4l-subdev5:
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x0300004f
Type : V4L Sub-Device
Entity Info:
ID : 0x00000001 (1)
Name : mtk-cam-p1
Function : Video Pixel Formatter
Pad 0x01000002 : 0: Sink
Link 0x02000012: from remote pad 0x100000f of entity 'mtk-cam-p1 meta input': Data
Pad 0x01000003 : 1: Source
Link 0x02000018: to remote pad 0x1000015 of entity 'mtk-cam-p1 main stream': Data, Enabled, Immutable
Pad 0x01000004 : 2: Source
Link 0x0200001e: to remote pad 0x100001b of entity 'mtk-cam-p1 packed out': Data
Pad 0x01000005 : 3: Source
Link 0x02000024: to remote pad 0x1000021 of entity 'mtk-cam-p1 partial meta 0': Data
Pad 0x01000006 : 4: Source
Link 0x0200002a: to remote pad 0x1000027 of entity 'mtk-cam-p1 partial meta 1': Data
Pad 0x01000007 : 5: Source
Link 0x02000030: to remote pad 0x100002d of entity 'mtk-cam-p1 partial meta 2': Data
Pad 0x01000008 : 6: Source
Link 0x02000036: to remote pad 0x1000033 of entity 'mtk-cam-p1 partial meta 3': Data
Pad 0x01000009 : 7: Source
Pad 0x0100000a : 8: Source
Pad 0x0100000b : 9: Source
Pad 0x0100000c : 10: Source
Pad 0x0100000d : 11: Sink
Link 0x0200004d: from remote pad 0x100003d of entity '1a040000.seninf.mipi-csi': Data, Enabled, Immutable
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
Allow for multiple opens:
test second /dev/v4l-subdev5 open: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Sub-Device ioctls (Sink Pad 0):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 1):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 2):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 3):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 4):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 5):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 6):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 7):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 8):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 9):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 10):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Sink Pad 11):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_FMT: OK (Not Supported)
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
test VIDIOC_QUERYCTRL: OK (Not Supported)
test VIDIOC_G/S_CTRL: OK (Not Supported)
test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK (Not Supported)
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
test VIDIOC_EXPBUF: OK (Not Supported)
test Requests: OK (Not Supported)
Total for mtk-cam-p1 device /dev/v4l-subdev5: 125, Succeeded: 125, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/v4l-subdev6:
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000051
Type : V4L Sub-Device
Entity Info:
ID : 0x00000038 (56)
Name : 1a040000.seninf.mipi-csi
Function : Video Interface Bridge
Pad 0x01000039 : 0: Sink
Link 0x02000047: from remote pad 0x1000046 of entity 'ov5695 2-0036': Data
Pad 0x0100003a : 1: Sink
Link 0x0200004b: from remote pad 0x100004a of entity 'ov2685 4-003c': Data
Pad 0x0100003b : 2: Sink
Pad 0x0100003c : 3: Sink
Pad 0x0100003d : 4: Source
Link 0x0200004d: to remote pad 0x100000d of entity 'mtk-cam-p1': Data, Enabled, Immutable
Pad 0x0100003e : 5: Source
Pad 0x0100003f : 6: Source
Pad 0x01000040 : 7: Source
Pad 0x01000041 : 8: Source
Pad 0x01000042 : 9: Source
Pad 0x01000043 : 10: Source
Pad 0x01000044 : 11: Source
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
Allow for multiple opens:
test second /dev/v4l-subdev6 open: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Sub-Device ioctls (Sink Pad 0):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Sink Pad 1):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Sink Pad 2):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Sink Pad 3):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 4):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 5):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 6):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 7):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 8):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 9):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 10):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Sub-Device ioctls (Source Pad 11):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(381): s_fmt.format.code == ~0U
test Try VIDIOC_SUBDEV_G/S_FMT: FAIL
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK (Not Supported)
fail: v4l2-test-subdevs.cpp(313): fmt.code == 0 || fmt.code == ~0U
fail: v4l2-test-subdevs.cpp(356): checkMBusFrameFmt(node, fmt.format)
test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 2 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK (Not Supported)
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
test VIDIOC_EXPBUF: OK (Not Supported)
test Requests: OK (Not Supported)
Total for mtk-cam-p1 device /dev/v4l-subdev6: 125, Succeeded: 101, Failed: 24, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/v4l-subdev7:
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000053
Type : V4L Sub-Device
Entity Info:
ID : 0x00000045 (69)
Name : ov5695 2-0036
Function : Camera Sensor
Pad 0x01000046 : 0: Source
Link 0x02000047: to remote pad 0x1000039 of entity '1a040000.seninf.mipi-csi': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
Allow for multiple opens:
test second /dev/v4l-subdev7 open: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Sub-Device ioctls (Source Pad 0):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
test Try VIDIOC_SUBDEV_G/S_FMT: OK
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
test Active VIDIOC_SUBDEV_G/S_FMT: OK
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 11 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK (Not Supported)
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
test VIDIOC_EXPBUF: OK (Not Supported)
test Requests: OK (Not Supported)
Total for mtk-cam-p1 device /dev/v4l-subdev7: 48, Succeeded: 48, Failed: 0, Warnings: 0
--------------------------------------------------------------------------------
Compliance test for mtk-cam-p1 device /dev/v4l-subdev8:
Media Driver Info:
Driver name : mtk-cam-p1
Model : mtk-cam-p1
Serial :
Bus info : platform:1a000000.camisp
Media version : 4.19.67
Hardware revision: 0x00000000 (0)
Driver version : 4.19.67
Interface Info:
ID : 0x03000055
Type : V4L Sub-Device
Entity Info:
ID : 0x00000049 (73)
Name : ov2685 4-003c
Function : Camera Sensor
Pad 0x0100004a : 0: Source
Link 0x0200004b: to remote pad 0x100003a of entity '1a040000.seninf.mipi-csi': Data
Required ioctls:
test MC information (see 'Media Driver Info' above): OK
Allow for multiple opens:
test second /dev/v4l-subdev8 open: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Sub-Device ioctls (Source Pad 0):
test Try VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
test Try VIDIOC_SUBDEV_G/S_FMT: OK
test Try VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test Active VIDIOC_SUBDEV_ENUM_MBUS_CODE/FRAME_SIZE/FRAME_INTERVAL: OK
test Active VIDIOC_SUBDEV_G/S_FMT: OK
test Active VIDIOC_SUBDEV_G/S_SELECTION/CROP: OK (Not Supported)
test VIDIOC_SUBDEV_G/S_FRAME_INTERVAL: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 10 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK (Not Supported)
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
test VIDIOC_EXPBUF: OK (Not Supported)
test Requests: OK (Not Supported)
Total for mtk-cam-p1 device /dev/v4l-subdev8: 48, Succeeded: 48, Failed: 0, Warnings: 0
Grand Total for mtk-cam-p1 device /dev/media1: 668, Succeeded: 644, Failed: 24, Warnings: 0
=========================================================================================
Jungo Lin (5):
media: dt-bindings: mt8183: Added camera ISP Pass 1
dts: arm64: mt8183: Add ISP Pass 1 nodes
media: videodev2.h: Add new boottime timestamp type
media: pixfmt: Add Mediatek ISP P1 image & meta formats
media: platform: Add Mediatek ISP P1 V4L2 device driver
.../bindings/media/mediatek,camisp.txt | 73 +
Documentation/media/uapi/v4l/buffer.rst | 11 +-
.../media/uapi/v4l/pixfmt-mtisp-sbggr10.rst | 65 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst | 90 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr12.rst | 61 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst | 110 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr14.rst | 73 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst | 110 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr8.rst | 51 +
.../media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst | 78 +
Documentation/media/uapi/v4l/pixfmt-rgb.rst | 8 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 +
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/mtk-isp/Kconfig | 17 +
.../media/platform/mtk-isp/isp_50/Makefile | 3 +
.../platform/mtk-isp/isp_50/cam/Makefile | 6 +
.../platform/mtk-isp/isp_50/cam/mtk_cam-hw.c | 634 +++++
.../platform/mtk-isp/isp_50/cam/mtk_cam-hw.h | 64 +
.../platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h | 222 ++
.../mtk-isp/isp_50/cam/mtk_cam-regs.h | 95 +
.../platform/mtk-isp/isp_50/cam/mtk_cam.c | 2081 +++++++++++++++++
.../platform/mtk-isp/isp_50/cam/mtk_cam.h | 244 ++
drivers/media/v4l2-core/v4l2-ioctl.c | 37 +
include/uapi/linux/videodev2.h | 41 +
25 files changed, 4206 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,camisp.txt
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst
create mode 100644 drivers/media/platform/mtk-isp/Kconfig
create mode 100644 drivers/media/platform/mtk-isp/isp_50/Makefile
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/Makefile
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.c
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-regs.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.c
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.h
--
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [RFC,v5, 1/5] media: dt-bindings: mt8183: Added camera ISP Pass 1
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <20190902075135.1332-1-jungo.lin@mediatek.com>
This patch adds DT binding document for the Pass 1 (P1) unit
in Mediatek's camera ISP system. The Pass 1 unit grabs the sensor
data out from the sensor interface, applies ISP image effects
from tuning data and outputs the image data or statistics data to DRAM.
Signed-off-by: Jungo Lin <jungo.lin@mediatek.com>
---
.../bindings/media/mediatek,camisp.txt | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,camisp.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek,camisp.txt b/Documentation/devicetree/bindings/media/mediatek,camisp.txt
new file mode 100644
index 000000000000..e156f01747d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,camisp.txt
@@ -0,0 +1,73 @@
+* Mediatek Image Signal Processor Pass 1 (ISP P1)
+
+The Pass 1 unit of Mediatek's camera ISP system grabs the sensor data out
+from the sensor interface, applies ISP effects from tuning data and outputs
+the image data and statistics data to DRAM. Furthermore, Pass 1 unit has
+the ability to output two different resolutions frames at the same time to
+increase the performance of the camera application.
+
+Required properties:
+- compatible: Must be "mediatek,mt8183-camisp" for MT8183.
+- reg: Physical base address of the camera function block register and
+ length of memory mapped region. Must contain an entry for each entry
+ in reg-names.
+- reg-names: Must include the following entries:
+ "cam_sys": Camera base function block
+ "cam_uni": Camera UNI function block
+ "cam_a": Camera ISP P1 hardware unit A
+ "cam_b": Camera ISP P1 hardware unit B
+ "cam_c": Camera ISP P1 hardware unit C
+- interrupts: Must contain an entry for each entry in interrupt-names.
+- interrupt-names : Must include the following entries:
+ "cam_uni": Camera UNI interrupt
+ "cam_a": Camera unit A interrupt
+ "cam_b": Camera unit B interrupt
+ "cam_c": Camera unit C interrupt
+- iommus: Shall point to the respective IOMMU block with master port
+ as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+- clocks: A list of phandle and clock specifier pairs as listed
+ in clock-names property, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: Must be "camsys_cam_cgpdn" and "camsys_camtg_cgpdn".
+- mediatek,larb: Must contain the local arbiters in the current SoCs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,scp : The node of system control processor (SCP), see
+ Documentation/devicetree/bindings/remoteproc/mtk,scp.txt for details.
+
+Example:
+SoC specific DT entry:
+
+ camisp: camisp@1a000000 {
+ compatible = "mediatek,mt8183-camisp";
+ reg = <0 0x1a000000 0 0x1000>,
+ <0 0x1a003000 0 0x1000>,
+ <0 0x1a004000 0 0x2000>,
+ <0 0x1a006000 0 0x2000>,
+ <0 0x1a008000 0 0x2000>;
+ reg-names = "cam_sys",
+ "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ iommus = <&iommu M4U_PORT_CAM_IMGO>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_CAMTG>;
+ clock-names = "camsys_cam_cgpdn",
+ "camsys_camtg_cgpdn";
+ mediatek,larb = <&larb3>,
+ <&larb6>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
+ mediatek,scp = <&scp>;
+ };
--
2.18.0
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^ permalink raw reply related
* [RFC, v5, 4/5] media: pixfmt: Add Mediatek ISP P1 image & meta formats
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <20190902075135.1332-1-jungo.lin@mediatek.com>
Add packed/full-g bayer formats with 8/10/12/14 bit
for image output. Add Pass 1 (P1) specific meta formats for
parameter processing and 3A/other statistics.
(The current metadata format used in meta input and partial
meta nodes is only a temporary solution to kick off the driver
development and is not ready to be reviewed yet.)
Signed-off-by: Jungo Lin <jungo.lin@mediatek.com>
---
.../media/uapi/v4l/pixfmt-mtisp-sbggr10.rst | 65 +++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst | 90 ++++++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr12.rst | 61 ++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst | 110 ++++++++++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr14.rst | 73 ++++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst | 110 ++++++++++++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr8.rst | 51 ++++++++
.../media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst | 78 +++++++++++++
Documentation/media/uapi/v4l/pixfmt-rgb.rst | 8 ++
drivers/media/v4l2-core/v4l2-ioctl.c | 37 ++++++
include/uapi/linux/videodev2.h | 39 +++++++
11 files changed, 722 insertions(+)
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8.rst
create mode 100644 Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10.rst
new file mode 100644
index 000000000000..534edb4f0fd4
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10.rst
@@ -0,0 +1,65 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr10:
+.. _v4l2-pix-fmt-mtisp-sgbrg10:
+.. _v4l2-pix-fmt-mtisp-sgrbg10:
+.. _v4l2-pix-fmt-mtisp-srggb10:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR10 ('MBBA'), V4L2_PIX_FMT_MTISP_SGBRG10('MBGA'), V4L2_PIX_FMT_MTISP_SGRBG10('MBgA'), V4L2_PIX_FMT_MTISP_SRGGB10('MBRA')
+*******************************
+
+10-bit Packed Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format, meaning all the data bits for a pixel lying
+next to each other with no padding in memory, with a depth of 10 bits per pixel.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor.
+They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc.
+Below is an example of conventional RGB byte order BGGR.
+
+**Byte Order.**
+Each cell is one byte.
+
+pixels cross the byte boundary and have a ratio of 5 bytes for each 4 pixels.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00low bits 7--0`
+ - G\ :sub:`01low bits 5--0` (bits 7--2) B\ :sub:`00high bits 9--8`\ (bits 1--0)
+ * - start + 2:
+ - B\ :sub:`02low bits 3--0`\ (bits 7--4) G\ :sub:`01high bits 9--6`\ (bits 3--0)
+ - G\ :sub:`03low bits 1--0`\ (bits 7--6) B\ :sub:`02high bits 9--4`\ (bits 5--0)
+ * - start + 4:
+ - G\ :sub:`03high bits 9--2`
+ * - start + 6:
+ - G\ :sub:`10low bits 7--0`
+ - R\ :sub:`11low bits 5--0`\ (bits 7--2) G\ :sub:`10high bits 9--8`\ (bits 1--0)
+ * - start + 8:
+ - G\ :sub:`12low bits 3--0`\ (bits 7--4) R\ :sub:`11high bits 9--6`\ (bits 3--0)
+ - R\ :sub:`13low bits 1--0`\ (bits 7--6) G\ :sub:`12high bits 9--4`\ (bits 5--0)
+ * - start + 10:
+ - R\ :sub:`13high bits 9--2`
+ * - start + 12:
+ - B\ :sub:`20low bits 7--0`
+ - G\ :sub:`21low bits 5--0`\ (bits 7--2) B\ :sub:`20high bits 9--8`\ (bits 1--0)
+ * - start + 14:
+ - B\ :sub:`22low bits 3--0`\ (bits 7--4) G\ :sub:`21high bits 9--6`\ (bits 3--0)
+ - G\ :sub:`23low bits 1--0`\ (bits 7--6) B\ :sub:`22high bits 9--4`\ (bits 5--0)
+ * - start + 16:
+ - G\ :sub:`23high bits 9--2`
+ * - start + 18:
+ - G\ :sub:`30low bits 7--0`
+ - R\ :sub:`31low bits 5--0`\ (bits 7--2) G\ :sub:`30high bits 9--8`\ (bits 1--0)
+ * - start + 20:
+ - G\ :sub:`32low bits 3--0`\ (bits 7--4) R\ :sub:`31high bits 9--6`\ (bits 3--0)
+ - R\ :sub:`33low bits 1--0`\ (bits 7--6) G\ :sub:`32high bits 9--4`\ (bits 5--0)
+ * - start + 22:
+ - R\ :sub:`33high bits 9--2` (bits 7--0)
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst
new file mode 100644
index 000000000000..7be527711602
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr10f.rst
@@ -0,0 +1,90 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr10f:
+.. _v4l2-pix-fmt-mtisp-sgbrg10f:
+.. _v4l2-pix-fmt-mtisp-sgrbg10f:
+.. _v4l2-pix-fmt-mtisp-srggb10f:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR10F ('MFBA'), V4L2_PIX_FMT_MTISP_SGBRG10F('MFGA'), V4L2_PIX_FMT_MTISP_SGRBG10F('MFgA'), V4L2_PIX_FMT_MTISP_SRGGB10F('MFRA')
+*******************************
+
+10-bit Packed Full-G Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format with a depth of 10 bits per sample with every 4 pixels.
+Full-G means 1 more pixel for green channel every 2 pixels.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor. They are conventionally
+described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example of conventional
+RGB byte order BGGR.
+
+**Bit-packed representation.**
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - B\ :sub:`00`
+ - FG\ :sub:`01`
+ - G\ :sub:`02`
+ - B\ :sub:`03`
+ - FG\ :sub:`04`
+ - G\ :sub:`05`
+ * - G\ :sub:`10`
+ - R\ :sub:`11`
+ - FG\ :sub:`12`
+ - G\ :sub:`13`
+ - R\ :sub:`14`
+ - FG\ :sub:`15`
+
+**Byte Order.**
+Each cell is one byte.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00low bits 7--0`
+ - FG\ :sub:`01low bits 5--0`\ (bits 7--2) B\ :sub:`00high bits 9--8`\ (bits 1--0)
+ - G\ :sub:`02low bits 3--0`\ (bits 7--4) FG\ :sub:`01high bits 9--6`\ (bits 3--0)
+ - B\ :sub:`03low bits 1--0`\ (bits 7--6) G\ :sub:`02high bits 9--4`\ (bits 5--0)
+ * - start + 4:
+ - B\ :sub:`03high bits 9--2`
+ - FG\ :sub:`04low bits 7--0`
+ - G\ :sub:`05low bits 5--0`\ (bits 7--2) FG\ :sub:`04high bits 9--8`\ (bits 1--0)
+ - G\ :sub:`05high bits 3--0`
+ * - start + 8:
+ - G\ :sub:`10low bits 7--0`
+ - R\ :sub:`11low bits 5--0`\ (bits 7--2) G\ :sub:`10high bits 9--8`\ (bits 1--0)
+ - FG\ :sub:`12low bits 3--0`\ (bits 7--4) R\ :sub:`11high bits 9--6`\ (bits 3--0)
+ - G\ :sub:`13low bits 1--0`\ (bits 7--6) FG\ :sub:`12high bits 9--4`\ (bits 5--0)
+ * - start + 12:
+ - G\ :sub:`13high bits 9--2`
+ - R\ :sub:`14low bits 7--0`
+ - FG\ :sub:`15low bits 5--0`\ (bits 7--2) R\ :sub:`14high bits 9--8`\ (bits 1--0)
+ - FG\ :sub:`15high bits 3--0`
+ * - start + 16:
+ - B\ :sub:`20low bits 7--0`
+ - FG\ :sub:`21low bits 5--0`\ (bits 7--2) B\ :sub:`20high bits 9--8`\ (bits 1--0)
+ - G\ :sub:`22low bits 3--0`\ (bits 7--4) FG\ :sub:`21high bits 9--6`\ (bits 3--0)
+ - B\ :sub:`23low bits 1--0`\ (bits 7--6) G\ :sub:`22high bits 9--4`\ (bits 5--0)
+ * - start + 20:
+ - B\ :sub:`23high bits 9--2`
+ - FG\ :sub:`24low bits 7--0`
+ - G\ :sub:`25low bits 5--0`\ (bits 7--2) FG\ :sub:`24high bits 9--8`\ (bits 1--0)
+ - G\ :sub:`25high bits 3--0`
+ * - start + 24:
+ - G\ :sub:`30low bits 7--0`
+ - R\ :sub:`31low bits 5--0`\ (bits 7--2) G\ :sub:`30high bits 9--8`\ (bits 1--0)
+ - FG\ :sub:`32low bits 3--0`\ (bits 7--4) R\ :sub:`31high bits 9--6`\ (bits 3--0)
+ - G\ :sub:`33low bits 1--0`\ (bits 7--6) FG\ :sub:`32high bits 9--4`\ (bits 5--0)
+ * - start + 28:
+ - G\ :sub:`33high bits 9--2`
+ - R\ :sub:`34low bits 7--0`
+ - FG\ :sub:`35low bits 5--0`\ (bits 7--2) R\ :sub:`34high bits 9--8`\ (bits 1--0)
+ - FG\ :sub:`35high bits 3--0`
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12.rst
new file mode 100644
index 000000000000..cc888aac42c2
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12.rst
@@ -0,0 +1,61 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr12:
+.. _v4l2-pix-fmt-mtisp-sgbrg12:
+.. _v4l2-pix-fmt-mtisp-sgrbg12:
+.. _v4l2-pix-fmt-mtisp-srggb12:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR12 ('MBBC'), V4L2_PIX_FMT_MTISP_SGBRG12('MBGC'), V4L2_PIX_FMT_MTISP_SGRBG12('MBgC'), V4L2_PIX_FMT_MTISP_SRGGB12('MBRC')
+*******************************
+
+12-bit Packed Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format, meaning all the data bits for a pixel lying
+next to each other with no padding in memory, with a depth of 12 bits per pixel.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor.
+They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc.
+Below is an example of conventional RGB byte order BGGR.
+
+**Byte Order.**
+Each cell is one byte.
+
+pixels cross the byte boundary and have a ratio of 6 bytes for each 4 pixels.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00lowbits 7--0`
+ - G\ :sub:`01lowbits 3--0`\ (bits 7--4) B\ :sub:`00highbits 11--8`\ (bits 3--0)
+ - G\ :sub:`01highbits 7--0`
+ - B\ :sub:`02lowbits 7--0`
+ - G\ :sub:`03lowbits 3--0`\ (bits 7--4) B\ :sub:`02highbits 11--8`\ (bits 3--0)
+ - G\ :sub:`03highbits 7--0`
+ * - start + 6:
+ - G\ :sub:`10lowbits 7--0`
+ - R\ :sub:`11lowbits 3--0`\ (bits 7--4) G\ :sub:`10highbits 11--8`\ (bits 3--0)
+ - R\ :sub:`11highbits 7--0`
+ - G\ :sub:`12lowbits 7--0`
+ - R\ :sub:`13lowbits 3--0`\ (bits 7--4) G\ :sub:`12highbits 11--8`\ (bits 3--0)
+ - R\ :sub:`13highbits 7--0`
+ * - start + 12:
+ - B\ :sub:`20lowbits 7--0`
+ - G\ :sub:`21lowbits 3--0`\ (bits 7--4) B\ :sub:`20highbits 11--8`\ (bits 3--0)
+ - G\ :sub:`21highbits 7--0`
+ - B\ :sub:`22lowbits 7--0`
+ - G\ :sub:`23lowbits 3--0`\ (bits 7--4) B\ :sub:`22highbits 11--8`\ (bits 3--0)
+ - G\ :sub:`23highbits 7--0`
+ * - start + 18:
+ - G\ :sub:`30lowbits 7--0`
+ - R\ :sub:`31lowbits 3--0`\ (bits 7--4) G\ :sub:`30highbits 11--8`\ (bits 3--0)
+ - R\ :sub:`31highbits 7--0`
+ - G\ :sub:`32lowbits 7--0`
+ - R\ :sub:`33lowbits 3--0`\ (bits 7--4) G\ :sub:`32highbits 11--8`\ (bits 3--0)
+ - R\ :sub:`33highbits 7--0`
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst
new file mode 100644
index 000000000000..c063de9f9ad8
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr12f.rst
@@ -0,0 +1,110 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr12f:
+.. _v4l2-pix-fmt-mtisp-sgbrg12f:
+.. _v4l2-pix-fmt-mtisp-sgrbg12f:
+.. _v4l2-pix-fmt-mtisp-srggb12f:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR12F ('MFBC'), V4L2_PIX_FMT_MTISP_SGBRG12F('MFGC'), V4L2_PIX_FMT_MTISP_SGRBG12F('MFgC'), V4L2_PIX_FMT_MTISP_SRGGB12F('MFRC')
+*******************************
+
+12-bit Packed Full-G Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format with a depth of 12 bits per sample with every 4 pixels.
+Full-G means 1 more pixel for green channel every 2 pixels.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor. They are conventionally
+described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example of conventional
+RGB byte order BGGR.
+
+**Bit-packed representation.**
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - B\ :sub:`00`
+ - FG\ :sub:`01`
+ - G\ :sub:`02`
+ - B\ :sub:`03`
+ - FG\ :sub:`04`
+ - G\ :sub:`05`
+ * - G\ :sub:`10`
+ - R\ :sub:`11`
+ - FG\ :sub:`12`
+ - G\ :sub:`13`
+ - R\ :sub:`14`
+ - FG\ :sub:`15`
+
+**Byte Order.**
+Each cell is one byte.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00low bits 7--0`
+ - FG\ :sub:`01low bits 3--0`\ (bits 7--4) B\ :sub:`00high bits 11--8`\ (bits 3--0)
+ * - start + 2:
+ - FG\ :sub:`01high bits 7--0`
+ - G\ :sub:`02low bits 7--0`
+ * - start + 4:
+ - B\ :sub:`03low bits 3--0`\ (bits 7--4) G\ :sub:`02high bits 11--8`\ (bits 3--0)
+ - B\ :sub:`03high bits 7--0`
+ * - start + 6:
+ - FG\ :sub:`04low bits 7--0`
+ - G\ :sub:`05low bits 3--0`\ (bits 7--4) FG\ :sub:`04high bits 11--8`\ (bits 3--0)
+ * - start + 8:
+ - G\ :sub:`05high bits 7--0`
+ -
+ * - start + 10:
+ - G\ :sub:`10low bits 7--0`
+ - R\ :sub:`11low bits 3--0`\ (bits 7--4) G\ :sub:`10high bits 11--8`\ (bits 3--0)
+ * - start + 12:
+ - R\ :sub:`11high bits 7--0`
+ - FG\ :sub:`12low bits 7--0`
+ * - start + 14:
+ - G\ :sub:`13low bits 3--0`\ (bits 7--4) FG\ :sub:`12high bits 11--8`\ (bits 3--0)
+ - G\ :sub:`13high bits 7--0`
+ * - start + 16:
+ - R\ :sub:`14low bits 7--0`
+ - FG\ :sub:`15low bits 3--0`\ (bits 7--4) R\ :sub:`14high bits 11--8`\ (bits 3--0)
+ * - start + 18:
+ - FG\ :sub:`15high bits 7--0`
+ -
+ * - start + 20:
+ - B\ :sub:`20low bits 7--0`
+ - FG\ :sub:`21low bits 3--0`\ (bits 7--4) B\ :sub:`20high bits 11--8`\ (bits 3--0)
+ * - start + 22:
+ - FG\ :sub:`21high bits 7--0`
+ - G\ :sub:`22low bits 7--0`
+ * - start + 24:
+ - B\ :sub:`23low bits 3--0`\ (bits 7--4) G\ :sub:`22high bits 11--8`\ (bits 3--0)
+ - B\ :sub:`23high bits 7--0`
+ * - start + 26:
+ - FG\ :sub:`24low bits 7--0`
+ - G\ :sub:`25low bits 3--0`\ (bits 7--4) FG\ :sub:`24high bits 11--8`\ (bits 3--0)
+ * - start + 28:
+ - G\ :sub:`25high bits 7--0`
+ -
+ * - start + 30:
+ - G\ :sub:`30low bits 7--0`
+ - R\ :sub:`31low bits 3--0`\ (bits 7--4) G\ :sub:`30high bits 11--8`\ (bits 3--0)
+ * - start + 32:
+ - R\ :sub:`31high bits 7--0`
+ - FG\ :sub:`32low bits 7--0`
+ * - start + 34:
+ - G\ :sub:`33low bits 3--0`\ (bits 7--4) FG\ :sub:`32high bits 11--8`\ (bits 3--0)
+ - G\ :sub:`33high bits 7--0`
+ * - start + 36:
+ - R\ :sub:`34low bits 7--0`
+ - FG\ :sub:`35low bits 3--0`\ (bits 7--4) R\ :sub:`34high bits 11--8`\ (bits 3--0)
+ * - start + 38:
+ - FG\ :sub:`35high bits 7--0`
+ -
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14.rst
new file mode 100644
index 000000000000..39ea9882a792
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14.rst
@@ -0,0 +1,73 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr14:
+.. _v4l2-pix-fmt-mtisp-sgbrg14:
+.. _v4l2-pix-fmt-mtisp-sgrbg14:
+.. _v4l2-pix-fmt-mtisp-srggb14:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR14 ('MBBE'), V4L2_PIX_FMT_MTISP_SGBRG14('MBGE'), V4L2_PIX_FMT_MTISP_SGRBG14('MBgE'), V4L2_PIX_FMT_MTISP_SRGGB14('MBRE')
+*******************************
+
+14-bit Packed Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format, meaning all the data bits for a pixel lying
+next to each other with no padding in memory, with a depth of 14 bits per pixel.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor.
+They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc.
+Below is an example of conventional RGB byte order BGGR.
+
+**Byte Order.**
+Each cell is one byte.
+
+pixels cross the byte boundary and have a ratio of 7 bytes for each 4 pixels.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00low bits 7--0`
+ - G\ :sub:`01low bits 1--0`\ (bits 7--6) B\ :sub:`00high bits 13--8`\ (bits 5--0)
+ - G\ :sub:`01low bits 9--2`\
+ - B\ :sub:`02low bits 3--0`\ (bits 7--4) G\ :sub:`01high bits 13--10`\ (bits 3--0)
+ * - start + 4:
+ - B\ :sub:`02low bits 11--4`\
+ - G\ :sub:`03low bits 5--0`\ (bits 7--2) B\ :sub:`02high bits 13--12`\ (bits 1--0)
+ - G\ :sub:`03high bits 13--6`\
+ -
+ * - start + 8:
+ - G\ :sub:`10low bits 7--0`
+ - R\ :sub:`11low bits 1--0`\ (bits 7--6) G\ :sub:`10high bits 13--8`\ (bits 5--0)
+ - R\ :sub:`11low bits 9--2`\
+ - G\ :sub:`12low bits 3--0`\ (bits 7--4) R\ :sub:`11high bits 13--10`\ (bits 3--0)
+ * - start + 12:
+ - G\ :sub:`12low bits 11--4`\
+ - R\ :sub:`13low bits 5--0`\ (bits 7--2) G\ :sub:`12high bits 13--12`\ (bits 1--0)
+ - R\ :sub:`13high bits 13--6`\
+ -
+ * - start + 16:
+ - B\ :sub:`20low bits 7--0`
+ - G\ :sub:`21low bits 1--0`\ (bits 7--6) B\ :sub:`20high bits 13--8`\ (bits 5--0)
+ - G\ :sub:`21low bits 9--2`\
+ - B\ :sub:`22low bits 3--0`\ (bits 7--4) G\ :sub:`21high bits 13--10`\ (bits 3--0)
+ * - start + 20:
+ - B\ :sub:`22low bits 11--4`\
+ - G\ :sub:`23low bits 5--0`\ (bits 7--2) B\ :sub:`22high bits 13--12`\ (bits 1--0)
+ - G\ :sub:`23high bits 13--6`\
+ -
+ * - start + 24:
+ - G\ :sub:`30low bits 7--0`
+ - R\ :sub:`31low bits 1--0`\ (bits 7--6) G\ :sub:`30high bits 13--8`\ (bits 5--0)
+ - R\ :sub:`31low bits 9--2`\
+ - G\ :sub:`32low bits 3--0`\ (bits 7--4) R\ :sub:`31high bits 13--10`\ (bits 3--0)
+ * - start + 28:
+ - G\ :sub:`32low bits 11--4`\
+ - R\ :sub:`33low bits 5--0`\ (bits 7--2) G\ :sub:`32high bits 13--12`\ (bits 1--0)
+ - R\ :sub:`33high bits 13--6`\
+ -
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst
new file mode 100644
index 000000000000..010b1c190c60
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr14f.rst
@@ -0,0 +1,110 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr14f:
+.. _v4l2-pix-fmt-mtisp-sgbrg14f:
+.. _v4l2-pix-fmt-mtisp-sgrbg14f:
+.. _v4l2-pix-fmt-mtisp-srggb14f:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR14F ('MFBE'), V4L2_PIX_FMT_MTISP_SGBRG14F('MFGE'), V4L2_PIX_FMT_MTISP_SGRBG14F('MFgE'), V4L2_PIX_FMT_MTISP_SRGGB14F('MFRE')
+*******************************
+
+14-bit Packed Full-G Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format with a depth of 14 bits per sample with every 4 pixels.
+Full-G means 1 more pixel for green channel every 2 pixels.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor. They are conventionally
+described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example of conventional
+RGB byte order BGGR.
+
+**Bit-packed representation.**
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - B\ :sub:`00`
+ - FG\ :sub:`01`
+ - G\ :sub:`02`
+ - B\ :sub:`03`
+ - FG\ :sub:`04`
+ - G\ :sub:`05`
+ * - G\ :sub:`10`
+ - R\ :sub:`11`
+ - FG\ :sub:`12`
+ - G\ :sub:`13`
+ - R\ :sub:`14`
+ - FG\ :sub:`15`
+
+**Byte Order.**
+Each cell is one byte.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00low bits 7--0`
+ - FG\ :sub:`01low bits 1--0`\ (bits 7--6) B\ :sub:`00high bits 13--8`\ (bits 5--0)
+ - FG\ :sub:`01low bits 9--2`
+ - G\ :sub:`02low bits 3--0`\ (bits 7--4) FG\ :sub:`01high bits 13--10`\ (bits 3--0)
+ * - start + 4:
+ - G\ :sub:`02low bits 11--4`
+ - B\ :sub:`03low bits 5--0`\ (bits 7--2) G\ :sub:`02high bits 13--12`\ (bits 1--0)
+ - B\ :sub:`03high bits 13--6`
+ - FG\ :sub:`04low bits 7--0`
+ * - start + 8:
+ - G\ :sub:`05low bits 1--0`\ (bits 7--6) FG\ :sub:`04high bits 13--8`\ (bits 5--0)
+ - G\ :sub:`05high bits 9--2`
+ - G\ :sub:`05high bits 13--10`
+ -
+ * - start + 12:
+ - G\ :sub:`10low bits 7--0`
+ - R\ :sub:`11low bits 1--0`\ (bits 7--6) G\ :sub:`10high bits 13--8`\ (bits 5--0)
+ - R\ :sub:`11low bits 9--2`
+ - FG\ :sub:`12low bits 3--0`\ (bits 7--4) R\ :sub:`11high bits 13--10`\ (bits 3--0)
+ * - start + 16:
+ - FG\ :sub:`12low bits 11--4`
+ - G\ :sub:`13low bits 5--0`\ (bits 7--2) FG\ :sub:`12high bits 13--12`\ (bits 1--0)
+ - G\ :sub:`13high bits 13--6`
+ - R\ :sub:`14low bits 7--0`
+ * - start + 20:
+ - FG\ :sub:`15low bits 1--0`\ (bits 7--6) R\ :sub:`14high bits 13--8`\ (bits 5--0)
+ - FG\ :sub:`15high bits 9--2`
+ - FG\ :sub:`15high bits 13--10`
+ -
+ * - start + 24:
+ - B\ :sub:`20low bits 7--0`
+ - FG\ :sub:`21low bits 1--0`\ (bits 7--6) B\ :sub:`20high bits 13--8`\ (bits 5--0)
+ - FG\ :sub:`21low bits 9--2`
+ - G\ :sub:`22low bits 3--0`\ (bits 7--4) FG\ :sub:`21high bits 13--10`\ (bits 3--0)
+ * - start + 28:
+ - G\ :sub:`22low bits 11--4`
+ - B\ :sub:`23low bits 5--0`\ (bits 7--2) G\ :sub:`22high bits 13--12`\ (bits 1--0)
+ - B\ :sub:`23high bits 13--6`
+ - FG\ :sub:`24low bits 7--0`
+ * - start + 32:
+ - G\ :sub:`25low bits 1--0`\ (bits 7--6) FG\ :sub:`24high bits 13--8`\ (bits 5--0)
+ - G\ :sub:`25high bits 9--2`
+ - G\ :sub:`25high bits 13--10`
+ -
+ * - start + 36:
+ - G\ :sub:`30low bits 7--0`
+ - R\ :sub:`31low bits 1--0`\ (bits 7--6) G\ :sub:`30high bits 13--8`\ (bits 5--0)
+ - R\ :sub:`31low bits 9--2`
+ - FG\ :sub:`32low bits 3--0`\ (bits 7--4) R\ :sub:`31high bits 13--10`\ (bits 3--0)
+ * - start + 40:
+ - FG\ :sub:`32low bits 11--4`
+ - G\ :sub:`33low bits 5--0`\ (bits 7--2) FG\ :sub:`32high bits 13--12`\ (bits 1--0)
+ - G\ :sub:`33high bits 13--6`
+ - R\ :sub:`34low bits 7--0`
+ * - start + 44:
+ - FG\ :sub:`35low bits 1--0`\ (bits 7--6) R\ :sub:`34high bits 13--8`\ (bits 5--0)
+ - FG\ :sub:`35high bits 9--2`
+ - FG\ :sub:`35high bits 13--10`
+ -
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8.rst
new file mode 100644
index 000000000000..86cadbf38175
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8.rst
@@ -0,0 +1,51 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr8:
+.. _v4l2-pix-fmt-mtisp-sgbrg8:
+.. _v4l2-pix-fmt-mtisp-sgrbg8:
+.. _v4l2-pix-fmt-mtisp-srggb8:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR8 ('MBB8'), V4L2_PIX_FMT_MTISP_SGBRG8('MBG8'), V4L2_PIX_FMT_MTISP_SGRBG8('MBg8'), V4L2_PIX_FMT_MTISP_SRGGB8('MBR8')
+*******************************
+
+8-bit Packed Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format, meaning all the data bits for a pixel lying
+next to each other with no padding in memory, with a depth of 8 bits per pixel.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor.
+They are conventionally described as GRGR... BGBG..., RGRG... GBGB..., etc.
+Below is an example of conventional RGB byte order BGGR.
+
+**Byte Order.**
+Each cell is one byte.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00`
+ - G\ :sub:`01`
+ - B\ :sub:`02`
+ - G\ :sub:`03`
+ * - start + 4:
+ - G\ :sub:`10`
+ - R\ :sub:`11`
+ - G\ :sub:`12`
+ - R\ :sub:`13`
+ * - start + 8:
+ - B\ :sub:`20`
+ - G\ :sub:`21`
+ - B\ :sub:`22`
+ - G\ :sub:`23`
+ * - start + 12:
+ - G\ :sub:`30`
+ - R\ :sub:`31`
+ - G\ :sub:`32`
+ - R\ :sub:`33`
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst
new file mode 100644
index 000000000000..ca5151312bca
--- /dev/null
+++ b/Documentation/media/uapi/v4l/pixfmt-mtisp-sbggr8f.rst
@@ -0,0 +1,78 @@
+.. -*- coding: utf-8; mode: rst -*-
+
+.. _v4l2-pix-fmt-mtisp-sbggr8f:
+.. _v4l2-pix-fmt-mtisp-sgbrg8f:
+.. _v4l2-pix-fmt-mtisp-sgrbg8f:
+.. _v4l2-pix-fmt-mtisp-srggb8f:
+
+*******************************
+V4L2_PIX_FMT_MTISP_SBGGR8F ('MFB8'), V4L2_PIX_FMT_MTISP_SGBRG8F('MFG8'), V4L2_PIX_FMT_MTISP_SGRBG8F('MFg8'), V4L2_PIX_FMT_MTISP_SRGGB8F('MFR8')
+*******************************
+
+8-bit Packed Full-G Bayer formats.
+
+Description
+===========
+
+These four pixel formats are used by Mediatek ISP P1.
+This is a packed format with a depth of 8 bits per sample with every 4 pixels.
+Full-G means 1 more pixel for green channel every 2 pixels.
+The least significant byte is stored at lower memory addresses (little-endian).
+The RGB byte order follows raw sRGB / Bayer format from sensor. They are conventionally
+described as GRGR... BGBG..., RGRG... GBGB..., etc. Below is an example of conventional
+RGB byte order BGGR.
+
+**Bit-packed representation.**
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - B\ :sub:`00`
+ - FG\ :sub:`01`
+ - G\ :sub:`02`
+ - B\ :sub:`03`
+ - FG\ :sub:`04`
+ - G\ :sub:`05`
+ * - G\ :sub:`10`
+ - R\ :sub:`11`
+ - FG\ :sub:`12`
+ - G\ :sub:`13`
+ - R\ :sub:`14`
+ - FG\ :sub:`15`
+
+**Byte Order.**
+Each cell is one byte.
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - B\ :sub:`00`
+ - FG\ :sub:`01`
+ - G\ :sub:`02`
+ - B\ :sub:`03`
+ - FG\ :sub:`04`
+ - G\ :sub:`05`
+ * - start + 6:
+ - G\ :sub:`10`
+ - R\ :sub:`11`
+ - FG\ :sub:`12`
+ - G\ :sub:`13`
+ - R\ :sub:`14`
+ - FG\ :sub:`15`
+ * - start + 12:
+ - B\ :sub:`20`
+ - FG\ :sub:`21`
+ - G\ :sub:`22`
+ - B\ :sub:`23`
+ - FG\ :sub:`24`
+ - G\ :sub:`25`
+ * - start + 18:
+ - G\ :sub:`30`
+ - R\ :sub:`31`
+ - FG\ :sub:`32`
+ - G\ :sub:`33`
+ - R\ :sub:`34`
+ - FG\ :sub:`35`
\ No newline at end of file
diff --git a/Documentation/media/uapi/v4l/pixfmt-rgb.rst b/Documentation/media/uapi/v4l/pixfmt-rgb.rst
index 48ab80024835..1ba260c84083 100644
--- a/Documentation/media/uapi/v4l/pixfmt-rgb.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-rgb.rst
@@ -28,3 +28,11 @@ RGB Formats
pixfmt-srggb12p
pixfmt-srggb14p
pixfmt-srggb16
+ pixfmt-pixfmt-mtisp-srggb8
+ pixfmt-pixfmt-mtisp-srggb10
+ pixfmt-pixfmt-mtisp-srggb12
+ pixfmt-pixfmt-mtisp-srggb14
+ pixfmt-pixfmt-mtisp-srggb8f
+ pixfmt-pixfmt-mtisp-srggb10f
+ pixfmt-pixfmt-mtisp-srggb12f
+ pixfmt-pixfmt-mtisp-srggb14f
\ No newline at end of file
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index b1f4b991dba6..451dada2146d 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1293,6 +1293,38 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_KONICA420: descr = "GSPCA KONICA420"; break;
case V4L2_PIX_FMT_HSV24: descr = "24-bit HSV 8-8-8"; break;
case V4L2_PIX_FMT_HSV32: descr = "32-bit XHSV 8-8-8-8"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR8: descr = "8-bit Bayer BGGR MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG8: descr = "8-bit Bayer GBRG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG8: descr = "8-bit Bayer GRBG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB8: descr = "8-bit Bayer RGGB MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR10: descr = "10-bit Bayer BGGR MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG10: descr = "10-bit Bayer GBRG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG10: descr = "10-bit Bayer GRBG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB10: descr = "10-bit Bayer RGGB MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR12: descr = "12-bit Bayer BGGR MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG12: descr = "12-bit Bayer GBRG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG12: descr = "12-bit Bayer GRBG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB12: descr = "12-bit Bayer RGGB MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR14: descr = "14-bit Bayer BGGR MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG14: descr = "14-bit Bayer GBRG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG14: descr = "14-bit Bayer GRBG MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB14: descr = "14-bit Bayer RGGB MTISP Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR8F: descr = "8-bit Full-G Bayer BGGR Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG8F: descr = "8-bit Full-G Bayer GBRG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG8F: descr = "8-bit Full-G Bayer GRBG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB8F: descr = "8-bit Full-G Bayer RGGB Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR10F: descr = "10-bit Full-G Bayer BGGR Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG10F: descr = "10-bit Full-G Bayer GBRG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG10F: descr = "10-bit Full-G Bayer GRBG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB10F: descr = "10-bit Full-G Bayer RGGB Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR12F: descr = "12-bit Full-G Bayer BGGR Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG12F: descr = "12-bit Full-G Bayer GBRG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG12F: descr = "12-bit Full-G Bayer GRBG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB12F: descr = "12-bit Full-G Bayer RGGB Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SBGGR14F: descr = "14-bit Full-G Bayer BGGR Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGBRG14F: descr = "14-bit Full-G Bayer GBRG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SGRBG14F: descr = "14-bit Full-G Bayer GRBG Packed"; break;
+ case V4L2_PIX_FMT_MTISP_SRGGB14F: descr = "14-bit Full-G Bayer RGGB Packed"; break;
case V4L2_SDR_FMT_CU8: descr = "Complex U8"; break;
case V4L2_SDR_FMT_CU16LE: descr = "Complex U16LE"; break;
case V4L2_SDR_FMT_CS8: descr = "Complex S8"; break;
@@ -1308,6 +1340,11 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_META_FMT_VSP1_HGO: descr = "R-Car VSP1 1-D Histogram"; break;
case V4L2_META_FMT_VSP1_HGT: descr = "R-Car VSP1 2-D Histogram"; break;
case V4L2_META_FMT_UVC: descr = "UVC payload header metadata"; break;
+ case V4L2_META_FMT_MTISP_3A: descr = "AE/AWB Histogram"; break;
+ case V4L2_META_FMT_MTISP_AF: descr = "AF Histogram"; break;
+ case V4L2_META_FMT_MTISP_LCS: descr = "Local Contrast Enhancement Stat"; break;
+ case V4L2_META_FMT_MTISP_LMV: descr = "Local Motion Vector Histogram"; break;
+ case V4L2_META_FMT_MTISP_PARAMS: descr = "MTK ISP Tuning Metadata"; break;
default:
/* Compressed formats */
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index a4fd271348e7..e515e681838c 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -728,6 +728,40 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_IPU3_SGRBG10 v4l2_fourcc('i', 'p', '3', 'G') /* IPU3 packed 10-bit GRBG bayer */
#define V4L2_PIX_FMT_IPU3_SRGGB10 v4l2_fourcc('i', 'p', '3', 'r') /* IPU3 packed 10-bit RGGB bayer */
+/* Vendor specific - Mediatek ISP bayer formats */
+#define V4L2_PIX_FMT_MTISP_SBGGR8 v4l2_fourcc('M', 'B', 'B', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG8 v4l2_fourcc('M', 'B', 'G', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG8 v4l2_fourcc('M', 'B', 'g', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB8 v4l2_fourcc('M', 'B', 'R', '8') /* Packed 8-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR10 v4l2_fourcc('M', 'B', 'B', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG10 v4l2_fourcc('M', 'B', 'G', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG10 v4l2_fourcc('M', 'B', 'g', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB10 v4l2_fourcc('M', 'B', 'R', 'A') /* Packed 10-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR12 v4l2_fourcc('M', 'B', 'B', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG12 v4l2_fourcc('M', 'B', 'G', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG12 v4l2_fourcc('M', 'B', 'g', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB12 v4l2_fourcc('M', 'B', 'R', 'C') /* Packed 12-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR14 v4l2_fourcc('M', 'B', 'B', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG14 v4l2_fourcc('M', 'B', 'G', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG14 v4l2_fourcc('M', 'B', 'g', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB14 v4l2_fourcc('M', 'B', 'R', 'E') /* Packed 14-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR8F v4l2_fourcc('M', 'F', 'B', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG8F v4l2_fourcc('M', 'F', 'G', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG8F v4l2_fourcc('M', 'F', 'g', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB8F v4l2_fourcc('M', 'F', 'R', '8') /* Full-G 8-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR10F v4l2_fourcc('M', 'F', 'B', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG10F v4l2_fourcc('M', 'F', 'G', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG10F v4l2_fourcc('M', 'F', 'g', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB10F v4l2_fourcc('M', 'F', 'R', 'A') /* Full-G 10-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR12F v4l2_fourcc('M', 'F', 'B', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG12F v4l2_fourcc('M', 'F', 'G', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG12F v4l2_fourcc('M', 'F', 'g', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB12F v4l2_fourcc('M', 'F', 'R', 'C') /* Full-G 12-bit */
+#define V4L2_PIX_FMT_MTISP_SBGGR14F v4l2_fourcc('M', 'F', 'B', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGBRG14F v4l2_fourcc('M', 'F', 'G', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SGRBG14F v4l2_fourcc('M', 'F', 'g', 'E') /* Full-G 14-bit */
+#define V4L2_PIX_FMT_MTISP_SRGGB14F v4l2_fourcc('M', 'F', 'R', 'E') /* Full-G 14-bit */
+
/* SDR formats - used only for Software Defined Radio devices */
#define V4L2_SDR_FMT_CU8 v4l2_fourcc('C', 'U', '0', '8') /* IQ u8 */
#define V4L2_SDR_FMT_CU16LE v4l2_fourcc('C', 'U', '1', '6') /* IQ u16le */
@@ -749,6 +783,11 @@ struct v4l2_pix_format {
#define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */
#define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */
#define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */
+#define V4L2_META_FMT_MTISP_3A v4l2_fourcc('M', 'T', 'f', 'a') /* AE/AWB histogram */
+#define V4L2_META_FMT_MTISP_AF v4l2_fourcc('M', 'T', 'f', 'f') /* AF histogram */
+#define V4L2_META_FMT_MTISP_LCS v4l2_fourcc('M', 'T', 'f', 'c') /* Local contrast enhanced statistics */
+#define V4L2_META_FMT_MTISP_LMV v4l2_fourcc('M', 'T', 'f', 'm') /* Local motion vector histogram */
+#define V4L2_META_FMT_MTISP_PARAMS v4l2_fourcc('M', 'T', 'f', 'p') /* ISP tuning parameters */
/* priv field value to indicates that subsequent fields are valid. */
#define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related
* [RFC, v5, 5/5] media: platform: Add Mediatek ISP P1 V4L2 device driver
From: Jungo Lin @ 2019-09-02 7:51 UTC (permalink / raw)
To: tfiga, hverkuil-cisco, laurent.pinchart, matthias.bgg, mchehab
Cc: shik, devicetree, Sean.Cheng, suleiman, Rynn.Wu, srv_heupstream,
robh, ryan.yu, Jerry-ch.Chen, frankie.chiu, jungo.lin, sj.huang,
yuzhao, linux-mediatek, zwisler, ddavenport, frederic.chen,
linux-arm-kernel, linux-media
In-Reply-To: <20190902075135.1332-1-jungo.lin@mediatek.com>
This patch adds the Mediatek ISP P1 HW control device driver.
It handles the ISP HW configuration, provides interrupt handling and
initializes the V4L2 device nodes and other V4L2 functions. Moreover,
implement standard V4L2 video driver that utilizes V4L2 and media
framework APIs. It supports one media device, one sub-device and
several video devices during initialization. Moreover, it also connects
with sensor and seninf drivers with V4L2 async APIs. Communicate with
co-process via SCP communication to compose ISP registers in the
firmware.
(The current metadata interface used in meta input and partial
meta nodes is only a temporary solution to kick off the driver
development and is not ready to be reviewed yet.)
Signed-off-by: Jungo Lin <jungo.lin@mediatek.com>
---
This patch depends on "Add support for mt8183 SCP"[1].
[1] https://patchwork.kernel.org/cover/11095113/
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/mtk-isp/Kconfig | 17 +
.../media/platform/mtk-isp/isp_50/Makefile | 3 +
.../platform/mtk-isp/isp_50/cam/Makefile | 6 +
.../platform/mtk-isp/isp_50/cam/mtk_cam-hw.c | 634 +++++
.../platform/mtk-isp/isp_50/cam/mtk_cam-hw.h | 64 +
.../platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h | 222 ++
.../mtk-isp/isp_50/cam/mtk_cam-regs.h | 95 +
.../platform/mtk-isp/isp_50/cam/mtk_cam.c | 2081 +++++++++++++++++
.../platform/mtk-isp/isp_50/cam/mtk_cam.h | 244 ++
11 files changed, 3369 insertions(+)
create mode 100644 drivers/media/platform/mtk-isp/Kconfig
create mode 100644 drivers/media/platform/mtk-isp/isp_50/Makefile
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/Makefile
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.c
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-regs.h
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.c
create mode 100644 drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 8a19654b393a..672e3a74412b 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -147,6 +147,7 @@ source "drivers/media/platform/xilinx/Kconfig"
source "drivers/media/platform/rcar-vin/Kconfig"
source "drivers/media/platform/atmel/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/mtk-isp/Kconfig"
config VIDEO_TI_CAL
tristate "TI CAL (Camera Adaptation Layer) driver"
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 7cbbd925124c..89222e52bc7a 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -92,6 +92,8 @@ obj-$(CONFIG_VIDEO_MEDIATEK_MDP) += mtk-mdp/
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk-jpeg/
+obj-$(CONFIG_VIDEO_MEDIATEK_ISP_PASS1) += mtk-isp/isp_50/
+
obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
diff --git a/drivers/media/platform/mtk-isp/Kconfig b/drivers/media/platform/mtk-isp/Kconfig
new file mode 100644
index 000000000000..434dcd067b45
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/Kconfig
@@ -0,0 +1,17 @@
+config VIDEO_MEDIATEK_ISP_PASS1
+ tristate "Mediatek ISP Pass 1 driver"
+ depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select V4L2_FWNODE
+ select VIDEOBUF2_VMALLOC
+ select VIDEOBUF2_DMA_CONTIG
+ select MTK_SCP
+ default n
+ help
+ Pass 1 driver controls 3A (auto-focus, exposure,
+ and white balance) with tuning feature and outputs
+ the captured image buffers in Mediatek's camera system.
+
+ Choose y if you want to use Mediatek SoCs to create image
+ captured application such as video recording and still image
+ capturing.
\ No newline at end of file
diff --git a/drivers/media/platform/mtk-isp/isp_50/Makefile b/drivers/media/platform/mtk-isp/isp_50/Makefile
new file mode 100644
index 000000000000..ce79d283b209
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_VIDEO_MEDIATEK_ISP_PASS1) += cam/
\ No newline at end of file
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/Makefile b/drivers/media/platform/mtk-isp/isp_50/cam/Makefile
new file mode 100644
index 000000000000..53b54d3c26a0
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+mtk-cam-isp-objs += mtk_cam.o
+mtk-cam-isp-objs += mtk_cam-hw.o
+
+obj-$(CONFIG_VIDEO_MEDIATEK_ISP_PASS1) += mtk-cam-isp.o
\ No newline at end of file
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.c b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.c
new file mode 100644
index 000000000000..92948b4d69dd
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.c
@@ -0,0 +1,634 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/atomic.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+#include <linux/module.h>
+#include <linux/remoteproc/mtk_scp.h>
+#include <linux/pm_runtime.h>
+#include <linux/remoteproc.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/videodev2.h>
+#include <linux/vmalloc.h>
+
+#include <media/v4l2-event.h>
+
+#include "mtk_cam.h"
+#include "mtk_cam-hw.h"
+#include "mtk_cam-regs.h"
+
+#define MTK_ISP_COMPOSER_MEM_SIZE 0x200000
+#define MTK_ISP_CQ_BUFFER_COUNT 3
+#define MTK_ISP_CQ_ADDRESS_OFFSET 0x640
+
+/*
+ *
+ * MTK Camera ISP P1 HW supports 3 ISP HW (CAM A/B/C).
+ * The T-put capability of CAM B is the maximum (max line buffer: 5376 pixels)
+ * For CAM A/C, it only supports max line buffer with 3328 pixels.
+ * In current driver, only supports CAM B.
+ *
+ */
+#define MTK_ISP_CAM_ID_B 3
+#define MTK_ISP_IPI_SEND_TIMEOUT 50
+#define MTK_ISP_STOP_HW_TIMEOUT (33 * USEC_PER_MSEC)
+
+static void isp_tx_frame_worker(struct work_struct *work)
+{
+ struct mtk_cam_dev_request *req =
+ container_of(work, struct mtk_cam_dev_request, frame_work);
+ struct mtk_cam_dev *cam =
+ container_of(req->req.mdev, struct mtk_cam_dev, media_dev);
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(cam->dev);
+
+ scp_ipi_send(p1_dev->scp_pdev, SCP_IPI_ISP_FRAME, &req->frame_params,
+ sizeof(req->frame_params), MTK_ISP_IPI_SEND_TIMEOUT);
+}
+
+static void isp_composer_handler(void *data, unsigned int len, void *priv)
+{
+ struct mtk_isp_p1_device *p1_dev = (struct mtk_isp_p1_device *)priv;
+ struct device *dev = p1_dev->dev;
+ struct mtk_isp_scp_p1_cmd *ipi_msg;
+
+ ipi_msg = (struct mtk_isp_scp_p1_cmd *)data;
+
+ if (len < offsetofend(struct mtk_isp_scp_p1_cmd, ack_info)) {
+ dev_err(dev, "wrong IPI len:%d\n", len);
+ return;
+ }
+
+ if (ipi_msg->cmd_id != ISP_CMD_ACK ||
+ ipi_msg->ack_info.cmd_id != ISP_CMD_FRAME_ACK)
+ return;
+
+ p1_dev->composed_frame_seq_no = ipi_msg->ack_info.frame_seq_no;
+ dev_dbg(dev, "ack frame_num:%d\n", p1_dev->composed_frame_seq_no);
+}
+
+static int isp_composer_init(struct mtk_isp_p1_device *p1_dev)
+{
+ struct device *dev = p1_dev->dev;
+ int ret;
+
+ ret = scp_ipi_register(p1_dev->scp_pdev, SCP_IPI_ISP_CMD,
+ isp_composer_handler, p1_dev);
+ if (ret) {
+ dev_err(dev, "failed to register IPI cmd\n");
+ return ret;
+ }
+ ret = scp_ipi_register(p1_dev->scp_pdev, SCP_IPI_ISP_FRAME,
+ isp_composer_handler, p1_dev);
+ if (ret) {
+ dev_err(dev, "failed to register IPI frame\n");
+ goto unreg_ipi_cmd;
+ }
+
+ p1_dev->composer_wq =
+ alloc_ordered_workqueue(dev_name(p1_dev->dev),
+ __WQ_LEGACY | WQ_MEM_RECLAIM |
+ WQ_FREEZABLE);
+ if (!p1_dev->composer_wq) {
+ dev_err(dev, "failed to alloc composer workqueue\n");
+ goto unreg_ipi_frame;
+ }
+
+ return 0;
+
+unreg_ipi_frame:
+ scp_ipi_unregister(p1_dev->scp_pdev, SCP_IPI_ISP_FRAME);
+unreg_ipi_cmd:
+ scp_ipi_unregister(p1_dev->scp_pdev, SCP_IPI_ISP_CMD);
+
+ return ret;
+}
+
+static void isp_composer_uninit(struct mtk_isp_p1_device *p1_dev)
+{
+ destroy_workqueue(p1_dev->composer_wq);
+ scp_ipi_unregister(p1_dev->scp_pdev, SCP_IPI_ISP_CMD);
+ scp_ipi_unregister(p1_dev->scp_pdev, SCP_IPI_ISP_FRAME);
+}
+
+static void isp_composer_hw_init(struct mtk_isp_p1_device *p1_dev)
+{
+ struct mtk_isp_scp_p1_cmd composer_tx_cmd;
+
+ memset(&composer_tx_cmd, 0, sizeof(composer_tx_cmd));
+ composer_tx_cmd.cmd_id = ISP_CMD_INIT;
+ composer_tx_cmd.init_param.hw_module = MTK_ISP_CAM_ID_B;
+
+ /*
+ * Passed coherent reserved memory info. for SCP firmware usage.
+ * This buffer is used for SCP's ISP composer to compose.
+ * The size of is fixed to 0x200000 for the requirement of composer.
+ */
+ composer_tx_cmd.init_param.cq_addr.iova = p1_dev->composer_iova;
+ composer_tx_cmd.init_param.cq_addr.scp_addr = p1_dev->composer_scp_addr;
+
+ scp_ipi_send(p1_dev->scp_pdev, SCP_IPI_ISP_CMD, &composer_tx_cmd,
+ sizeof(composer_tx_cmd), MTK_ISP_IPI_SEND_TIMEOUT);
+}
+
+static void isp_composer_hw_deinit(struct mtk_isp_p1_device *p1_dev)
+{
+ struct mtk_isp_scp_p1_cmd composer_tx_cmd;
+
+ memset(&composer_tx_cmd, 0, sizeof(composer_tx_cmd));
+ composer_tx_cmd.cmd_id = ISP_CMD_DEINIT;
+
+ scp_ipi_send(p1_dev->scp_pdev, SCP_IPI_ISP_CMD, &composer_tx_cmd,
+ sizeof(composer_tx_cmd), MTK_ISP_IPI_SEND_TIMEOUT);
+
+ isp_composer_uninit(p1_dev);
+}
+
+void mtk_isp_hw_config(struct mtk_cam_dev *cam,
+ struct p1_config_param *config_param)
+{
+ struct mtk_isp_scp_p1_cmd composer_tx_cmd;
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(cam->dev);
+
+ memset(&composer_tx_cmd, 0, sizeof(composer_tx_cmd));
+ composer_tx_cmd.cmd_id = ISP_CMD_CONFIG;
+ memcpy(&composer_tx_cmd.config_param, config_param,
+ sizeof(*config_param));
+
+ scp_ipi_send(p1_dev->scp_pdev, SCP_IPI_ISP_CMD, &composer_tx_cmd,
+ sizeof(composer_tx_cmd), MTK_ISP_IPI_SEND_TIMEOUT);
+}
+
+void mtk_isp_stream(struct mtk_cam_dev *cam, int on)
+{
+ struct mtk_isp_scp_p1_cmd composer_tx_cmd;
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(cam->dev);
+
+ memset(&composer_tx_cmd, 0, sizeof(composer_tx_cmd));
+ composer_tx_cmd.cmd_id = ISP_CMD_STREAM;
+ composer_tx_cmd.is_stream_on = on;
+
+ scp_ipi_send(p1_dev->scp_pdev, SCP_IPI_ISP_CMD, &composer_tx_cmd,
+ sizeof(composer_tx_cmd), MTK_ISP_IPI_SEND_TIMEOUT);
+}
+
+int mtk_isp_hw_init(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+ int ret;
+
+ ret = rproc_boot(p1_dev->rproc_handle);
+ if (ret) {
+ dev_err(dev, "failed to rproc_boot\n");
+ return ret;
+ }
+
+ ret = isp_composer_init(p1_dev);
+ if (ret)
+ return ret;
+
+ pm_runtime_get_sync(dev);
+ isp_composer_hw_init(p1_dev);
+
+ p1_dev->enqueued_frame_seq_no = 0;
+ p1_dev->dequeued_frame_seq_no = 0;
+ p1_dev->composed_frame_seq_no = 0;
+ p1_dev->sof_count = 0;
+
+ dev_dbg(dev, "%s done\n", __func__);
+
+ return 0;
+}
+
+int mtk_isp_hw_release(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+
+ isp_composer_hw_deinit(p1_dev);
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+ rproc_shutdown(p1_dev->rproc_handle);
+
+ dev_dbg(dev, "%s done\n", __func__);
+
+ return 0;
+}
+
+void mtk_isp_req_enqueue(struct mtk_cam_dev *cam,
+ struct mtk_cam_dev_request *req)
+{
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(cam->dev);
+
+ /* Accumulated frame sequence number */
+ req->frame_params.frame_seq_no = ++p1_dev->enqueued_frame_seq_no;
+
+ INIT_WORK(&req->frame_work, isp_tx_frame_worker);
+ queue_work(p1_dev->composer_wq, &req->frame_work);
+ dev_dbg(cam->dev, "enqueue fd:%s frame_seq_no:%d job cnt:%d\n",
+ req->req.debug_str, req->frame_params.frame_seq_no,
+ cam->running_job_count);
+}
+
+static void isp_irq_handle_sof(struct mtk_isp_p1_device *p1_dev,
+ unsigned int dequeued_frame_seq_no)
+{
+ dma_addr_t base_addr = p1_dev->composer_iova;
+ struct device *dev = p1_dev->dev;
+ struct mtk_cam_dev_request *req;
+ int composed_frame_seq_no = p1_dev->composed_frame_seq_no;
+ unsigned int addr_offset;
+
+ /* Send V4L2_EVENT_FRAME_SYNC event */
+ mtk_cam_dev_event_frame_sync(&p1_dev->cam_dev, dequeued_frame_seq_no);
+
+ p1_dev->sof_count += 1;
+ /* Save frame information */
+ p1_dev->dequeued_frame_seq_no = dequeued_frame_seq_no;
+
+ req = mtk_cam_dev_get_req(&p1_dev->cam_dev, dequeued_frame_seq_no);
+ if (req)
+ req->timestamp = ktime_get_boottime_ns();
+
+ /* Update CQ base address if needed */
+ if (composed_frame_seq_no <= dequeued_frame_seq_no) {
+ dev_dbg(dev,
+ "SOF_INT_ST, no update, cq_num:%d, frame_seq:%d\n",
+ composed_frame_seq_no, dequeued_frame_seq_no);
+ return;
+ }
+ addr_offset = MTK_ISP_CQ_ADDRESS_OFFSET *
+ (dequeued_frame_seq_no % MTK_ISP_CQ_BUFFER_COUNT);
+ writel(base_addr + addr_offset, p1_dev->regs + REG_CQ_THR0_BASEADDR);
+ dev_dbg(dev,
+ "SOF_INT_ST, update next, cq_num:%d, frame_seq:%d cq_addr:0x%x\n",
+ composed_frame_seq_no, dequeued_frame_seq_no, addr_offset);
+}
+
+static void isp_irq_handle_dma_err(struct mtk_isp_p1_device *p1_dev)
+{
+ u32 val;
+
+ dev_err(p1_dev->dev,
+ "IMGO:0x%x, RRZO:0x%x, AAO=0x%x, AFO=0x%x, LMVO=0x%x\n",
+ readl(p1_dev->regs + REG_IMGO_ERR_STAT),
+ readl(p1_dev->regs + REG_RRZO_ERR_STAT),
+ readl(p1_dev->regs + REG_AAO_ERR_STAT),
+ readl(p1_dev->regs + REG_AFO_ERR_STAT),
+ readl(p1_dev->regs + REG_LMVO_ERR_STAT));
+ dev_err(p1_dev->dev,
+ "LCSO=0x%x, PSO=0x%x, FLKO=0x%x, BPCI:0x%x, LSCI=0x%x\n",
+ readl(p1_dev->regs + REG_LCSO_ERR_STAT),
+ readl(p1_dev->regs + REG_PSO_ERR_STAT),
+ readl(p1_dev->regs + REG_FLKO_ERR_STAT),
+ readl(p1_dev->regs + REG_BPCI_ERR_STAT),
+ readl(p1_dev->regs + REG_LSCI_ERR_STAT));
+
+ /* Disable DMA error mask to avoid too much error log */
+ val = readl(p1_dev->regs + REG_CTL_RAW_INT_EN);
+ writel((val & (~DMA_ERR_INT_EN)), p1_dev->regs + REG_CTL_RAW_INT_EN);
+ dev_dbg(p1_dev->dev, "disable DMA error mask:0x%x\n", val);
+}
+
+static irqreturn_t isp_irq_cam(int irq, void *data)
+{
+ struct mtk_isp_p1_device *p1_dev = (struct mtk_isp_p1_device *)data;
+ struct device *dev = p1_dev->dev;
+ unsigned int dequeued_frame_seq_no;
+ unsigned int irq_status, err_status, dma_status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&p1_dev->spinlock_irq, flags);
+ irq_status = readl(p1_dev->regs + REG_CTL_RAW_INT_STAT);
+ err_status = irq_status & INT_ST_MASK_CAM_ERR;
+ dma_status = readl(p1_dev->regs + REG_CTL_RAW_INT2_STAT);
+ dequeued_frame_seq_no = readl(p1_dev->regs + REG_FRAME_SEQ_NUM);
+ spin_unlock_irqrestore(&p1_dev->spinlock_irq, flags);
+
+ /*
+ * In normal case, the next SOF ISR should come after HW PASS1 DONE ISR.
+ * If these two ISRs come together, print warning msg to hint.
+ */
+ if ((irq_status & SOF_INT_ST) && (irq_status & HW_PASS1_DON_ST))
+ dev_warn(dev, "sof_done block cnt:%d\n", p1_dev->sof_count);
+
+ /* De-queue frame */
+ if (irq_status & SW_PASS1_DON_ST) {
+ mtk_cam_dev_dequeue_req_frame(&p1_dev->cam_dev,
+ p1_dev->dequeued_frame_seq_no);
+ mtk_cam_dev_req_try_queue(&p1_dev->cam_dev);
+ }
+
+ /* Save frame info. & update CQ address for frame HW en-queue */
+ if (irq_status & SOF_INT_ST)
+ isp_irq_handle_sof(p1_dev, dequeued_frame_seq_no);
+
+ /* Check ISP error status */
+ if (err_status) {
+ dev_err(dev, "int_err:0x%x 0x%x\n", irq_status, err_status);
+ /* Show DMA errors in detail */
+ if (err_status & DMA_ERR_ST)
+ isp_irq_handle_dma_err(p1_dev);
+ }
+
+ dev_dbg(dev, "SOF:%d irq:0x%x, dma:0x%x, frame_num:%d\n",
+ p1_dev->sof_count, irq_status, dma_status,
+ dequeued_frame_seq_no);
+
+ return IRQ_HANDLED;
+}
+
+static int isp_setup_scp_rproc(struct mtk_isp_p1_device *p1_dev,
+ struct platform_device *pdev)
+{
+ phandle rproc_phandle;
+ struct device *dev = p1_dev->dev;
+ dma_addr_t addr;
+ void *ptr;
+ int ret;
+
+ p1_dev->scp_pdev = scp_get_pdev(pdev);
+ if (!p1_dev->scp_pdev) {
+ dev_err(dev, "failed to get scp device\n");
+ return -ENODEV;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "mediatek,scp",
+ &rproc_phandle);
+ if (ret) {
+ dev_err(dev, "failed to get rproc_phandle:%d\n", ret);
+ return -EINVAL;
+ }
+
+ p1_dev->rproc_handle = rproc_get_by_phandle(rproc_phandle);
+ dev_dbg(dev, "p1 rproc_phandle: 0x%pK\n", p1_dev->rproc_handle);
+ if (!p1_dev->rproc_handle) {
+ dev_err(dev, "failed to get rproc_handle\n");
+ return -EINVAL;
+ }
+ p1_dev->cam_dev.smem_dev = &p1_dev->scp_pdev->dev;
+
+ /*
+ * Allocate coherent reserved memory for SCP firmware usage.
+ * The size of SCP composer's memory is fixed to 0x200000
+ * for the requirement of firmware.
+ */
+ ptr = dma_alloc_coherent(p1_dev->cam_dev.smem_dev,
+ MTK_ISP_COMPOSER_MEM_SIZE, &addr, GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ p1_dev->composer_scp_addr = addr;
+ p1_dev->composer_virt_addr = ptr;
+ dev_dbg(dev, "scp addr:%pad va:%pK\n", &addr, ptr);
+
+ /*
+ * This reserved memory is also be used by ISP P1 HW.
+ * Need to get iova address for ISP P1 DMA.
+ */
+ addr = dma_map_resource(dev, addr, MTK_ISP_COMPOSER_MEM_SIZE,
+ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
+ if (dma_mapping_error(dev, addr)) {
+ dev_err(dev, "failed to map scp iova\n");
+ ret = -ENOMEM;
+ goto fail_free_mem;
+ }
+ p1_dev->composer_iova = addr;
+ dev_dbg(dev, "scp iova addr:%pad\n", &addr);
+
+ return 0;
+
+fail_free_mem:
+ dma_free_coherent(p1_dev->cam_dev.smem_dev, MTK_ISP_COMPOSER_MEM_SIZE,
+ ptr, p1_dev->composer_scp_addr);
+ p1_dev->composer_scp_addr = 0;
+
+ return ret;
+}
+
+static int mtk_isp_pm_suspend(struct device *dev)
+{
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+ u32 val;
+ int ret;
+
+ dev_dbg(dev, "- %s\n", __func__);
+
+ if (pm_runtime_suspended(dev))
+ return 0;
+
+ /* Disable ISP's view finder and wait for TG idle if possible */
+ dev_dbg(dev, "cam suspend, disable VF\n");
+ val = readl(p1_dev->regs + REG_TG_VF_CON);
+ writel(val & (~TG_VF_CON_VFDATA_EN), p1_dev->regs + REG_TG_VF_CON);
+ readl_poll_timeout_atomic(p1_dev->regs + REG_TG_INTER_ST, val,
+ (val & TG_CS_MASK) == TG_IDLE_ST,
+ USEC_PER_MSEC, MTK_ISP_STOP_HW_TIMEOUT);
+
+ /* Disable CMOS */
+ val = readl(p1_dev->regs + REG_TG_SEN_MODE);
+ writel(val & (~TG_SEN_MODE_CMOS_EN), p1_dev->regs + REG_TG_SEN_MODE);
+
+ /* Force ISP HW to idle */
+ ret = pm_runtime_force_suspend(dev);
+ if (ret) {
+ dev_err(dev, "failed to force suspend:%d\n", ret);
+ goto reenable_hw;
+ }
+
+ return 0;
+
+reenable_hw:
+ val = readl(p1_dev->regs + REG_TG_SEN_MODE);
+ writel(val | TG_SEN_MODE_CMOS_EN, p1_dev->regs + REG_TG_SEN_MODE);
+ val = readl(p1_dev->regs + REG_TG_VF_CON);
+ writel(val | TG_VF_CON_VFDATA_EN, p1_dev->regs + REG_TG_VF_CON);
+
+ return ret;
+}
+
+static int mtk_isp_pm_resume(struct device *dev)
+{
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+ u32 val;
+ int ret;
+
+ dev_dbg(dev, "- %s\n", __func__);
+
+ if (pm_runtime_suspended(dev))
+ return 0;
+
+ /* Force ISP HW to resume */
+ ret = pm_runtime_force_resume(dev);
+ if (ret)
+ return ret;
+
+ /* Enable CMOS */
+ dev_dbg(dev, "cam resume, enable CMOS/VF\n");
+ val = readl(p1_dev->regs + REG_TG_SEN_MODE);
+ writel(val | TG_SEN_MODE_CMOS_EN, p1_dev->regs + REG_TG_SEN_MODE);
+
+ /* Enable VF */
+ val = readl(p1_dev->regs + REG_TG_VF_CON);
+ writel(val | TG_VF_CON_VFDATA_EN, p1_dev->regs + REG_TG_VF_CON);
+
+ return 0;
+}
+
+static int mtk_isp_runtime_suspend(struct device *dev)
+{
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "%s:disable clock\n", __func__);
+ clk_bulk_disable_unprepare(p1_dev->num_clks, p1_dev->clks);
+
+ return 0;
+}
+
+static int mtk_isp_runtime_resume(struct device *dev)
+{
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+ int ret;
+
+ dev_dbg(dev, "%s:enable clock\n", __func__);
+ ret = clk_bulk_prepare_enable(p1_dev->num_clks, p1_dev->clks);
+ if (ret) {
+ dev_err(dev, "failed to enable clock:%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_isp_probe(struct platform_device *pdev)
+{
+ /* List of clocks required by isp cam */
+ static const char * const clk_names[] = {
+ "camsys_cam_cgpdn", "camsys_camtg_cgpdn"
+ };
+ struct mtk_isp_p1_device *p1_dev;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int irq, ret, i;
+
+ p1_dev = devm_kzalloc(dev, sizeof(*p1_dev), GFP_KERNEL);
+ if (!p1_dev)
+ return -ENOMEM;
+
+ p1_dev->dev = dev;
+ dev_set_drvdata(dev, p1_dev);
+
+ /*
+ * Now only support single CAM with CAM B.
+ * Get CAM B register base with CAM B index.
+ * Support multiple CAMs in future.
+ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, MTK_ISP_CAM_ID_B);
+ p1_dev->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(p1_dev->regs)) {
+ dev_err(dev, "failed to map reister base\n");
+ return PTR_ERR(p1_dev->regs);
+ }
+ dev_dbg(dev, "cam, map_addr=0x%pK\n", p1_dev->regs);
+
+ /*
+ * The cam_sys unit only supports reg., but has no IRQ support.
+ * The reg. & IRQ index is shifted with 1 for CAM B in DTS.
+ */
+ irq = platform_get_irq(pdev, MTK_ISP_CAM_ID_B - 1);
+ if (!irq) {
+ dev_err(dev, "failed to get irq\n");
+ return -ENODEV;
+ }
+ ret = devm_request_irq(dev, irq, isp_irq_cam, 0, dev_name(dev),
+ p1_dev);
+ if (ret) {
+ dev_err(dev, "failed to request irq=%d\n", irq);
+ return ret;
+ }
+ dev_dbg(dev, "registered irq=%d\n", irq);
+ spin_lock_init(&p1_dev->spinlock_irq);
+
+ p1_dev->num_clks = ARRAY_SIZE(clk_names);
+ p1_dev->clks = devm_kcalloc(dev, p1_dev->num_clks,
+ sizeof(*p1_dev->clks), GFP_KERNEL);
+ if (!p1_dev->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < p1_dev->num_clks; ++i)
+ p1_dev->clks[i].id = clk_names[i];
+
+ ret = devm_clk_bulk_get(dev, p1_dev->num_clks, p1_dev->clks);
+ if (ret) {
+ dev_err(dev, "failed to get isp cam clock:%d\n", ret);
+ return ret;
+ }
+
+ ret = isp_setup_scp_rproc(p1_dev, pdev);
+ if (ret)
+ return ret;
+
+ pm_runtime_set_autosuspend_delay(dev, 2 * MTK_ISP_STOP_HW_TIMEOUT);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_enable(dev);
+
+ /* Initialize the v4l2 common part */
+ ret = mtk_cam_dev_init(pdev, &p1_dev->cam_dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int mtk_isp_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_isp_p1_device *p1_dev = dev_get_drvdata(dev);
+
+ mtk_cam_dev_cleanup(&p1_dev->cam_dev);
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_disable(dev);
+ dma_unmap_page_attrs(dev, p1_dev->composer_iova,
+ MTK_ISP_COMPOSER_MEM_SIZE, DMA_BIDIRECTIONAL,
+ DMA_ATTR_SKIP_CPU_SYNC);
+ dma_free_coherent(&p1_dev->scp_pdev->dev, MTK_ISP_COMPOSER_MEM_SIZE,
+ p1_dev->composer_virt_addr,
+ p1_dev->composer_scp_addr);
+ rproc_put(p1_dev->rproc_handle);
+
+ return 0;
+}
+
+static const struct dev_pm_ops mtk_isp_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mtk_isp_pm_suspend, mtk_isp_pm_resume)
+ SET_RUNTIME_PM_OPS(mtk_isp_runtime_suspend, mtk_isp_runtime_resume,
+ NULL)
+};
+
+static const struct of_device_id mtk_isp_of_ids[] = {
+ {.compatible = "mediatek,mt8183-camisp",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, mtk_isp_of_ids);
+
+static struct platform_driver mtk_isp_driver = {
+ .probe = mtk_isp_probe,
+ .remove = mtk_isp_remove,
+ .driver = {
+ .name = "mtk-cam-p1",
+ .of_match_table = of_match_ptr(mtk_isp_of_ids),
+ .pm = &mtk_isp_pm_ops,
+ }
+};
+
+module_platform_driver(mtk_isp_driver);
+
+MODULE_DESCRIPTION("Mediatek ISP P1 driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.h b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.h
new file mode 100644
index 000000000000..452dc06110e2
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-hw.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_HW_H__
+#define __MTK_CAM_HW_H__
+
+#include <linux/types.h>
+
+#include "mtk_cam.h"
+#include "mtk_cam-ipi.h"
+
+/*
+ * struct mtk_isp_p1_device - the Mediatek ISP P1 device information
+ *
+ * @dev: Pointer to device.
+ * @scp_pdev: Pointer to SCP platform device.
+ * @rproc_handle: Pointer to new remoteproc instance.
+ * @cam_dev: Embedded struct cam_dev
+ * @regs: Camera ISP HW base register address
+ * @num_clks: The number of driver's clocks
+ * @clks: The clock data array
+ * @spinlock_irq: Used to protect register read/write data
+ * @enqueued_frame_seq_no: Frame sequence number of enqueued frame
+ * @dequeued_frame_seq_no: Frame sequence number of dequeued frame
+ * @composed_frame_seq_no: Frame sequence number of composed frame
+ * @timestamp: Frame timestamp in ns
+ * @sof_count: SOF counter
+ * @composer_wq: The work queue for frame request composing
+ * @composer_scp_addr: SCP address of ISP composer memory
+ * @composer_iova: DMA address of ISP composer memory
+ * @virt_addr: Virtual address of ISP composer memory
+ *
+ */
+struct mtk_isp_p1_device {
+ struct device *dev;
+ struct platform_device *scp_pdev;
+ struct rproc *rproc_handle;
+ struct mtk_cam_dev cam_dev;
+ void __iomem *regs;
+ unsigned int num_clks;
+ struct clk_bulk_data *clks;
+ /* Used to protect register read/write data */
+ spinlock_t spinlock_irq;
+ unsigned int enqueued_frame_seq_no;
+ unsigned int dequeued_frame_seq_no;
+ unsigned int composed_frame_seq_no;
+ u8 sof_count;
+ struct workqueue_struct *composer_wq;
+ dma_addr_t composer_scp_addr;
+ dma_addr_t composer_iova;
+ void *composer_virt_addr;
+};
+
+int mtk_isp_hw_init(struct mtk_cam_dev *cam_dev);
+int mtk_isp_hw_release(struct mtk_cam_dev *cam_dev);
+void mtk_isp_hw_config(struct mtk_cam_dev *cam_dev,
+ struct p1_config_param *config_param);
+void mtk_isp_stream(struct mtk_cam_dev *cam_dev, int on);
+void mtk_isp_req_enqueue(struct mtk_cam_dev *cam_dev,
+ struct mtk_cam_dev_request *req);
+
+#endif /* __MTK_CAM_HW_H__ */
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h
new file mode 100644
index 000000000000..981b634dd91f
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-ipi.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_IPI_H__
+#define __MTK_CAM_IPI_H__
+
+#include <linux/types.h>
+
+/*
+ * struct img_size - Image size information.
+ *
+ * @w: Image width, the unit is pixel
+ * @h: Image height, the unit is pixel
+ * @xsize: Bytes per line based on width.
+ * @stride: Bytes per line when changing line.
+ * Stride is based on xsize + HW constrain(byte align).
+ *
+ */
+struct img_size {
+ u32 w;
+ u32 h;
+ u32 xsize;
+ u32 stride;
+} __packed;
+
+/*
+ * struct p1_img_crop - image corp information
+ *
+ * @left: The left of crop area.
+ * @top: The top of crop area.
+ * @width: The width of crop area.
+ * @height: The height of crop area.
+ *
+ */
+struct p1_img_crop {
+ u32 left;
+ u32 top;
+ u32 width;
+ u32 height;
+} __packed;
+
+/*
+ * struct dma_buffer - DMA buffer address information
+ *
+ * @iova: DMA address for ISP DMA device
+ * @scp_addr: SCP address for external co-process unit
+ *
+ */
+struct dma_buffer {
+ u32 iova;
+ u32 scp_addr;
+} __packed;
+
+/*
+ * struct p1_img_output - ISP P1 image output information
+ *
+ * @buffer: DMA buffer address of image.
+ * @size: The image size configuration.
+ * @crop: The crop configuration.
+ * @pixel_bits: The bits per image pixel.
+ * @img_fmt: The image format.
+ *
+ */
+struct p1_img_output {
+ struct dma_buffer buffer;
+ struct img_size size;
+ struct p1_img_crop crop;
+ u8 pixel_bits;
+ u32 img_fmt;
+} __packed;
+
+/*
+ * struct cfg_in_param - Image input parameters structure.
+ * Normally, it comes from sensor information.
+ *
+ * @continuous: Indicate the sensor mode. Continuous or single shot.
+ * @subsample: Indicate to enables SOF subsample or not.
+ * @pixel_mode: Describe 1/2/4 pixels per clock cycle.
+ * @data_pattern: Describe input data pattern.
+ * @raw_pixel_id: Bayer sequence.
+ * @tg_fps: The fps rate of TG (time generator).
+ * @img_fmt: The image format of input source.
+ * @p1_img_crop: The crop configuration of input source.
+ *
+ */
+struct cfg_in_param {
+ u8 continuous;
+ u8 subsample;
+ u8 pixel_mode;
+ u8 data_pattern;
+ u8 raw_pixel_id;
+ u16 tg_fps;
+ u32 img_fmt;
+ struct p1_img_crop crop;
+} __packed;
+
+/*
+ * struct cfg_main_out_param - The image output parameters of main stream.
+ *
+ * @bypass: Indicate this device is enabled or disabled or not.
+ * @pure_raw: Indicate the image path control.
+ * True: pure raw
+ * False: processing raw
+ * @pure_raw_pack: Indicate the image is packed or not.
+ * True: packed mode
+ * False: unpacked mode
+ * @p1_img_output: The output image information.
+ *
+ */
+struct cfg_main_out_param {
+ u8 bypass;
+ u8 pure_raw;
+ u8 pure_raw_pack;
+ struct p1_img_output output;
+} __packed;
+
+/*
+ * struct cfg_resize_out_param - The image output parameters of
+ * packed out stream.
+ *
+ * @bypass: Indicate this device is enabled or disabled or not.
+ * @p1_img_output: The output image information.
+ *
+ */
+struct cfg_resize_out_param {
+ u8 bypass;
+ struct p1_img_output output;
+} __packed;
+
+/*
+ * struct p1_config_param - ISP P1 configuration parameters.
+ *
+ * @cfg_in_param: The Image input parameters.
+ * @cfg_main_param: The main output image parameters.
+ * @cfg_resize_out_param: The packed output image parameters.
+ * @enabled_dmas: The enabled DMA port information.
+ *
+ */
+struct p1_config_param {
+ struct cfg_in_param cfg_in_param;
+ struct cfg_main_out_param cfg_main_param;
+ struct cfg_resize_out_param cfg_resize_param;
+ u32 enabled_dmas;
+} __packed;
+
+/*
+ * struct P1_meta_frame - ISP P1 meta frame information.
+ *
+ * @enabled_dma: The enabled DMA port information.
+ * @vb_index: The VB2 index of meta buffer.
+ * @meta_addr: DMA buffer address of meta buffer.
+ *
+ */
+struct P1_meta_frame {
+ u32 enabled_dma;
+ u32 vb_index;
+ struct dma_buffer meta_addr;
+} __packed;
+
+/*
+ * struct isp_init_info - ISP P1 composer init information.
+ *
+ * @hw_module: The ISP Camera HW module ID.
+ * @cq_addr: The DMA address of composer memory.
+ *
+ */
+struct isp_init_info {
+ u8 hw_module;
+ struct dma_buffer cq_addr;
+} __packed;
+
+/*
+ * struct isp_ack_info - ISP P1 IPI command ack information.
+ *
+ * @cmd_id: The IPI command ID is acked.
+ * @frame_seq_no: The IPI frame sequence number is acked.
+ *
+ */
+struct isp_ack_info {
+ u8 cmd_id;
+ u32 frame_seq_no;
+} __packed;
+
+/*
+ * The IPI command enumeration.
+ */
+enum mtk_isp_scp_cmds {
+ ISP_CMD_INIT,
+ ISP_CMD_CONFIG,
+ ISP_CMD_STREAM,
+ ISP_CMD_DEINIT,
+ ISP_CMD_ACK,
+ ISP_CMD_FRAME_ACK,
+ ISP_CMD_RESERVED,
+};
+
+/*
+ * struct mtk_isp_scp_p1_cmd - ISP P1 IPI command strcture.
+ *
+ * @cmd_id: The IPI command ID.
+ * @init_param: The init formation for ISP_CMD_INIT.
+ * @config_param: The cmd configuration for ISP_CMD_CONFIG.
+ * @enabled_dmas: The meta configuration information for ISP_CMD_CONFIG_META.
+ * @is_stream_on: The stream information for ISP_CMD_STREAM.
+ * @ack_info: The cmd ack. information for ISP_CMD_ACK.
+ *
+ */
+struct mtk_isp_scp_p1_cmd {
+ u8 cmd_id;
+ union {
+ struct isp_init_info init_param;
+ struct p1_config_param config_param;
+ u32 enabled_dmas;
+ struct P1_meta_frame meta_frame;
+ u8 is_stream_on;
+ struct isp_ack_info ack_info;
+ };
+} __packed;
+
+#endif /* __MTK_CAM_IPI_H__ */
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-regs.h b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-regs.h
new file mode 100644
index 000000000000..ab2277f45fa4
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam-regs.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_REGS_H__
+#define __MTK_CAM_REGS_H__
+
+/* ISP interrupt enable */
+#define REG_CTL_RAW_INT_EN 0x0020
+#define DMA_ERR_INT_EN BIT(29)
+
+/* ISP interrupt status */
+#define REG_CTL_RAW_INT_STAT 0x0024
+#define VS_INT_ST BIT(0)
+#define TG_ERR_ST BIT(4)
+#define TG_GBERR_ST BIT(5)
+#define CQ_CODE_ERR_ST BIT(6)
+#define CQ_APB_ERR_ST BIT(7)
+#define CQ_VS_ERR_ST BIT(8)
+#define HW_PASS1_DON_ST BIT(11)
+#define SOF_INT_ST BIT(12)
+#define AMX_ERR_ST BIT(15)
+#define RMX_ERR_ST BIT(16)
+#define BMX_ERR_ST BIT(17)
+#define RRZO_ERR_ST BIT(18)
+#define AFO_ERR_ST BIT(19)
+#define IMGO_ERR_ST BIT(20)
+#define AAO_ERR_ST BIT(21)
+#define PSO_ERR_ST BIT(22)
+#define LCSO_ERR_ST BIT(23)
+#define BNR_ERR_ST BIT(24)
+#define LSCI_ERR_ST BIT(25)
+#define DMA_ERR_ST BIT(29)
+#define SW_PASS1_DON_ST BIT(30)
+
+/* ISP interrupt 2 status */
+#define REG_CTL_RAW_INT2_STAT 0x0034
+#define AFO_DONE_ST BIT(5)
+#define AAO_DONE_ST BIT(7)
+
+/* Configures sensor mode */
+#define REG_TG_SEN_MODE 0x0230
+#define TG_SEN_MODE_CMOS_EN BIT(0)
+
+/* View finder mode control */
+#define REG_TG_VF_CON 0x0234
+#define TG_VF_CON_VFDATA_EN BIT(0)
+
+/* View finder mode control */
+#define REG_TG_INTER_ST 0x026c
+#define TG_CS_MASK 0x3f00
+#define TG_IDLE_ST BIT(8)
+
+/* IMGO error status register */
+#define REG_IMGO_ERR_STAT 0x1360
+/* RRZO error status register */
+#define REG_RRZO_ERR_STAT 0x1364
+/* AAO error status register */
+#define REG_AAO_ERR_STAT 0x1368
+/* AFO error status register */
+#define REG_AFO_ERR_STAT 0x136c
+/* LCSO error status register */
+#define REG_LCSO_ERR_STAT 0x1370
+/* BPCI error status register */
+#define REG_BPCI_ERR_STAT 0x137c
+/* LSCI error status register */
+#define REG_LSCI_ERR_STAT 0x1384
+/* LMVO error status register */
+#define REG_LMVO_ERR_STAT 0x1390
+/* FLKO error status register */
+#define REG_FLKO_ERR_STAT 0x1394
+/* PSO error status register */
+#define REG_PSO_ERR_STAT 0x13a0
+
+/* CQ0 base address */
+#define REG_CQ_THR0_BASEADDR 0x0198
+/* Frame sequence number */
+#define REG_FRAME_SEQ_NUM 0x13b8
+
+/* IRQ Error Mask */
+#define INT_ST_MASK_CAM_ERR ( \
+ TG_ERR_ST |\
+ TG_GBERR_ST |\
+ CQ_CODE_ERR_ST |\
+ CQ_APB_ERR_ST |\
+ CQ_VS_ERR_ST |\
+ BNR_ERR_ST |\
+ RMX_ERR_ST |\
+ BMX_ERR_ST |\
+ BNR_ERR_ST |\
+ LSCI_ERR_ST |\
+ DMA_ERR_ST)
+
+#endif /* __MTK_CAM_REGS_H__ */
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.c b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.c
new file mode 100644
index 000000000000..16c742f57c40
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.c
@@ -0,0 +1,2081 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mc.h>
+#include <media/v4l2-subdev.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "mtk_cam.h"
+#include "mtk_cam-hw.h"
+
+#define R_IMGO BIT(0)
+#define R_RRZO BIT(1)
+#define R_AAO BIT(3)
+#define R_AFO BIT(4)
+#define R_LCSO BIT(5)
+#define R_LMVO BIT(7)
+#define R_FLKO BIT(8)
+#define R_PSO BIT(10)
+
+#define MTK_ISP_ONE_PIXEL_MODE 1
+#define MTK_ISP_MIN_RESIZE_RATIO 6
+#define MTK_ISP_MAX_RUNNING_JOBS 3
+
+#define MTK_CAM_CIO_PAD_SRC 4
+#define MTK_CAM_CIO_PAD_SINK 11
+
+static inline struct mtk_cam_video_device *
+file_to_mtk_cam_node(struct file *__file)
+{
+ return container_of(video_devdata(__file),
+ struct mtk_cam_video_device, vdev);
+}
+
+static inline struct mtk_cam_video_device *
+mtk_cam_vbq_to_vdev(struct vb2_queue *__vq)
+{
+ return container_of(__vq, struct mtk_cam_video_device, vbq);
+}
+
+static inline struct mtk_cam_dev_request *
+mtk_cam_req_to_dev_req(struct media_request *__req)
+{
+ return container_of(__req, struct mtk_cam_dev_request, req);
+}
+
+static inline struct mtk_cam_dev_buffer *
+mtk_cam_vb2_buf_to_dev_buf(struct vb2_buffer *__vb)
+{
+ return container_of(__vb, struct mtk_cam_dev_buffer, vbb.vb2_buf);
+}
+
+static void mtk_cam_dev_job_done(struct mtk_cam_dev *cam,
+ struct mtk_cam_dev_request *req,
+ enum vb2_buffer_state state)
+{
+ struct media_request_object *obj, *obj_prev;
+ unsigned long flags;
+ u64 ts_eof = ktime_get_boottime_ns();
+
+ if (!cam->streaming)
+ return;
+
+ dev_dbg(cam->dev, "job done request:%s frame_seq:%d state:%d\n",
+ req->req.debug_str, req->frame_params.frame_seq_no, state);
+
+ list_for_each_entry_safe(obj, obj_prev, &req->req.objects, list) {
+ struct vb2_buffer *vb;
+ struct mtk_cam_dev_buffer *buf;
+ struct mtk_cam_video_device *node;
+
+ if (!vb2_request_object_is_buffer(obj))
+ continue;
+ vb = container_of(obj, struct vb2_buffer, req_obj);
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ spin_lock_irqsave(&node->buf_list_lock, flags);
+ list_del(&buf->list);
+ spin_unlock_irqrestore(&node->buf_list_lock, flags);
+ buf->vbb.sequence = req->frame_params.frame_seq_no;
+ if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
+ vb->timestamp = ts_eof;
+ else
+ vb->timestamp = req->timestamp;
+ vb2_buffer_done(&buf->vbb.vb2_buf, state);
+ }
+}
+
+struct mtk_cam_dev_request *mtk_cam_dev_get_req(struct mtk_cam_dev *cam,
+ unsigned int frame_seq_no)
+{
+ struct mtk_cam_dev_request *req, *req_prev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->running_job_lock, flags);
+ list_for_each_entry_safe(req, req_prev, &cam->running_job_list, list) {
+ dev_dbg(cam->dev, "frame_seq:%d, get frame_seq:%d\n",
+ req->frame_params.frame_seq_no, frame_seq_no);
+
+ /* Match by the en-queued request number */
+ if (req->frame_params.frame_seq_no == frame_seq_no) {
+ spin_unlock_irqrestore(&cam->running_job_lock, flags);
+ return req;
+ }
+ }
+ spin_unlock_irqrestore(&cam->running_job_lock, flags);
+
+ return NULL;
+}
+
+void mtk_cam_dev_dequeue_req_frame(struct mtk_cam_dev *cam,
+ unsigned int frame_seq_no)
+{
+ struct mtk_cam_dev_request *req, *req_prev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->running_job_lock, flags);
+ list_for_each_entry_safe(req, req_prev, &cam->running_job_list, list) {
+ dev_dbg(cam->dev, "frame_seq:%d, de-queue frame_seq:%d\n",
+ req->frame_params.frame_seq_no, frame_seq_no);
+
+ /* Match by the en-queued request number */
+ if (req->frame_params.frame_seq_no == frame_seq_no) {
+ cam->running_job_count--;
+ /* Pass to user space */
+ mtk_cam_dev_job_done(cam, req, VB2_BUF_STATE_DONE);
+ list_del(&req->list);
+ break;
+ } else if (req->frame_params.frame_seq_no < frame_seq_no) {
+ cam->running_job_count--;
+ /* Pass to user space for frame drop */
+ mtk_cam_dev_job_done(cam, req, VB2_BUF_STATE_ERROR);
+ dev_warn(cam->dev, "frame_seq:%d drop\n",
+ req->frame_params.frame_seq_no);
+ list_del(&req->list);
+ } else {
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&cam->running_job_lock, flags);
+}
+
+static void mtk_cam_dev_req_cleanup(struct mtk_cam_dev *cam)
+{
+ struct mtk_cam_dev_request *req, *req_prev;
+ unsigned long flags;
+
+ dev_dbg(cam->dev, "%s\n", __func__);
+
+ spin_lock_irqsave(&cam->pending_job_lock, flags);
+ list_for_each_entry_safe(req, req_prev, &cam->pending_job_list, list)
+ list_del(&req->list);
+ spin_unlock_irqrestore(&cam->pending_job_lock, flags);
+
+ spin_lock_irqsave(&cam->running_job_lock, flags);
+ list_for_each_entry_safe(req, req_prev, &cam->running_job_list, list)
+ list_del(&req->list);
+ spin_unlock_irqrestore(&cam->running_job_lock, flags);
+}
+
+void mtk_cam_dev_req_try_queue(struct mtk_cam_dev *cam)
+{
+ struct mtk_cam_dev_request *req, *req_prev;
+ unsigned long flags;
+
+ if (!cam->streaming) {
+ dev_dbg(cam->dev, "stream is off\n");
+ return;
+ }
+
+ spin_lock_irqsave(&cam->pending_job_lock, flags);
+ spin_lock_irqsave(&cam->running_job_lock, flags);
+ list_for_each_entry_safe(req, req_prev, &cam->pending_job_list, list) {
+ if (cam->running_job_count >= MTK_ISP_MAX_RUNNING_JOBS) {
+ dev_dbg(cam->dev, "jobs are full\n");
+ break;
+ }
+ cam->running_job_count++;
+ list_del(&req->list);
+ list_add_tail(&req->list, &cam->running_job_list);
+ mtk_isp_req_enqueue(cam, req);
+ }
+ spin_unlock_irqrestore(&cam->running_job_lock, flags);
+ spin_unlock_irqrestore(&cam->pending_job_lock, flags);
+}
+
+static struct media_request *mtk_cam_req_alloc(struct media_device *mdev)
+{
+ struct mtk_cam_dev_request *cam_dev_req;
+
+ cam_dev_req = kzalloc(sizeof(*cam_dev_req), GFP_KERNEL);
+
+ return &cam_dev_req->req;
+}
+
+static void mtk_cam_req_free(struct media_request *req)
+{
+ struct mtk_cam_dev_request *cam_dev_req = mtk_cam_req_to_dev_req(req);
+
+ kfree(cam_dev_req);
+}
+
+static void mtk_cam_req_queue(struct media_request *req)
+{
+ struct mtk_cam_dev_request *cam_req = mtk_cam_req_to_dev_req(req);
+ struct mtk_cam_dev *cam = container_of(req->mdev, struct mtk_cam_dev,
+ media_dev);
+ unsigned long flags;
+
+ /* update frame_params's dma_bufs in mtk_cam_vb2_buf_queue */
+ vb2_request_queue(req);
+
+ /* add to pending job list */
+ spin_lock_irqsave(&cam->pending_job_lock, flags);
+ list_add_tail(&cam_req->list, &cam->pending_job_list);
+ spin_unlock_irqrestore(&cam->pending_job_lock, flags);
+
+ mtk_cam_dev_req_try_queue(cam);
+}
+
+static unsigned int get_pixel_bits(unsigned int pix_fmt)
+{
+ switch (pix_fmt) {
+ case V4L2_PIX_FMT_MTISP_SBGGR8:
+ case V4L2_PIX_FMT_MTISP_SGBRG8:
+ case V4L2_PIX_FMT_MTISP_SGRBG8:
+ case V4L2_PIX_FMT_MTISP_SRGGB8:
+ case V4L2_PIX_FMT_MTISP_SBGGR8F:
+ case V4L2_PIX_FMT_MTISP_SGBRG8F:
+ case V4L2_PIX_FMT_MTISP_SGRBG8F:
+ case V4L2_PIX_FMT_MTISP_SRGGB8F:
+ return 8;
+ case V4L2_PIX_FMT_MTISP_SBGGR10:
+ case V4L2_PIX_FMT_MTISP_SGBRG10:
+ case V4L2_PIX_FMT_MTISP_SGRBG10:
+ case V4L2_PIX_FMT_MTISP_SRGGB10:
+ case V4L2_PIX_FMT_MTISP_SBGGR10F:
+ case V4L2_PIX_FMT_MTISP_SGBRG10F:
+ case V4L2_PIX_FMT_MTISP_SGRBG10F:
+ case V4L2_PIX_FMT_MTISP_SRGGB10F:
+ return 10;
+ case V4L2_PIX_FMT_MTISP_SBGGR12:
+ case V4L2_PIX_FMT_MTISP_SGBRG12:
+ case V4L2_PIX_FMT_MTISP_SGRBG12:
+ case V4L2_PIX_FMT_MTISP_SRGGB12:
+ case V4L2_PIX_FMT_MTISP_SBGGR12F:
+ case V4L2_PIX_FMT_MTISP_SGBRG12F:
+ case V4L2_PIX_FMT_MTISP_SGRBG12F:
+ case V4L2_PIX_FMT_MTISP_SRGGB12F:
+ return 12;
+ case V4L2_PIX_FMT_MTISP_SBGGR14:
+ case V4L2_PIX_FMT_MTISP_SGBRG14:
+ case V4L2_PIX_FMT_MTISP_SGRBG14:
+ case V4L2_PIX_FMT_MTISP_SRGGB14:
+ case V4L2_PIX_FMT_MTISP_SBGGR14F:
+ case V4L2_PIX_FMT_MTISP_SGBRG14F:
+ case V4L2_PIX_FMT_MTISP_SGRBG14F:
+ case V4L2_PIX_FMT_MTISP_SRGGB14F:
+ return 14;
+ default:
+ return 0;
+ }
+}
+
+static void cal_image_pix_mp(struct mtk_cam_dev *cam, unsigned int node_id,
+ struct v4l2_pix_format_mplane *mp)
+{
+ unsigned int bpl, ppl;
+ unsigned int pixel_bits = get_pixel_bits(mp->pixelformat);
+ unsigned int width = mp->width;
+
+ bpl = 0;
+ if (node_id == MTK_CAM_P1_MAIN_STREAM_OUT) {
+ /* Bayer encoding format & 2 bytes alignment */
+ bpl = ALIGN(DIV_ROUND_UP(width * pixel_bits, 8), 2);
+ } else if (node_id == MTK_CAM_P1_PACKED_BIN_OUT) {
+ /*
+ * The FULL-G encoding format
+ * 1 G component per pixel
+ * 1 R component per 4 pixel
+ * 1 B component per 4 pixel
+ * Total 4G/1R/1B in 4 pixel (pixel per line:ppl)
+ */
+ ppl = DIV_ROUND_UP(width * 6, 4);
+ bpl = DIV_ROUND_UP(ppl * pixel_bits, 8);
+
+ /* 4 bytes alignment for 10 bit & others are 8 bytes */
+ if (pixel_bits == 10)
+ bpl = ALIGN(bpl, 4);
+ else
+ bpl = ALIGN(bpl, 8);
+ }
+ /*
+ * This image output buffer will be input buffer of MTK CAM DIP HW
+ * For MTK CAM DIP HW constrained, it needs 4 bytes alignment
+ */
+ bpl = ALIGN(bpl, 4);
+
+ mp->plane_fmt[0].bytesperline = bpl;
+ mp->plane_fmt[0].sizeimage = bpl * mp->height;
+
+ dev_dbg(cam->dev, "node:%d width:%d bytesperline:%d sizeimage:%d\n",
+ node_id, width, bpl, mp->plane_fmt[0].sizeimage);
+}
+
+static const struct v4l2_format *
+mtk_cam_dev_find_fmt(struct mtk_cam_dev_node_desc *desc, u32 format)
+{
+ int i;
+ const struct v4l2_format *dev_fmt;
+
+ for (i = 0; i < desc->num_fmts; i++) {
+ dev_fmt = &desc->fmts[i];
+ if (dev_fmt->fmt.pix_mp.pixelformat == format)
+ return dev_fmt;
+ }
+
+ return NULL;
+}
+
+/* Get the default format setting */
+static void
+mtk_cam_dev_load_default_fmt(struct mtk_cam_dev *cam,
+ struct mtk_cam_dev_node_desc *queue_desc,
+ struct v4l2_format *dest)
+{
+ const struct v4l2_format *default_fmt =
+ &queue_desc->fmts[queue_desc->default_fmt_idx];
+
+ dest->type = queue_desc->buf_type;
+
+ /* Configure default format based on node type */
+ if (!queue_desc->image) {
+ dest->fmt.meta.dataformat = default_fmt->fmt.meta.dataformat;
+ dest->fmt.meta.buffersize = default_fmt->fmt.meta.buffersize;
+ return;
+ }
+
+ dest->fmt.pix_mp.pixelformat = default_fmt->fmt.pix_mp.pixelformat;
+ dest->fmt.pix_mp.width = default_fmt->fmt.pix_mp.width;
+ dest->fmt.pix_mp.height = default_fmt->fmt.pix_mp.height;
+ /* bytesperline & sizeimage calculation */
+ cal_image_pix_mp(cam, queue_desc->id, &dest->fmt.pix_mp);
+ dest->fmt.pix_mp.num_planes = 1;
+
+ dest->fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+ dest->fmt.pix_mp.field = V4L2_FIELD_NONE;
+ dest->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ dest->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ dest->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_SRGB;
+}
+
+/* Utility functions */
+static unsigned int get_sensor_pixel_id(unsigned int fmt)
+{
+ switch (fmt) {
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ return MTK_CAM_RAW_PXL_ID_B;
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ return MTK_CAM_RAW_PXL_ID_GB;
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ return MTK_CAM_RAW_PXL_ID_GR;
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ return MTK_CAM_RAW_PXL_ID_R;
+ default:
+ return MTK_CAM_RAW_PXL_ID_UNKNOWN;
+ }
+}
+
+static unsigned int get_sensor_fmt(unsigned int fmt)
+{
+ switch (fmt) {
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ return MTK_CAM_IMG_FMT_BAYER8;
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ return MTK_CAM_IMG_FMT_BAYER10;
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ return MTK_CAM_IMG_FMT_BAYER12;
+ case MEDIA_BUS_FMT_SBGGR14_1X14:
+ case MEDIA_BUS_FMT_SGBRG14_1X14:
+ case MEDIA_BUS_FMT_SGRBG14_1X14:
+ case MEDIA_BUS_FMT_SRGGB14_1X14:
+ return MTK_CAM_IMG_FMT_BAYER14;
+ default:
+ return MTK_CAM_IMG_FMT_UNKNOWN;
+ }
+}
+
+static unsigned int get_img_fmt(unsigned int fourcc)
+{
+ switch (fourcc) {
+ case V4L2_PIX_FMT_MTISP_SBGGR8:
+ case V4L2_PIX_FMT_MTISP_SGBRG8:
+ case V4L2_PIX_FMT_MTISP_SGRBG8:
+ case V4L2_PIX_FMT_MTISP_SRGGB8:
+ return MTK_CAM_IMG_FMT_BAYER8;
+ case V4L2_PIX_FMT_MTISP_SBGGR8F:
+ case V4L2_PIX_FMT_MTISP_SGBRG8F:
+ case V4L2_PIX_FMT_MTISP_SGRBG8F:
+ case V4L2_PIX_FMT_MTISP_SRGGB8F:
+ return MTK_CAM_IMG_FMT_FG_BAYER8;
+ case V4L2_PIX_FMT_MTISP_SBGGR10:
+ case V4L2_PIX_FMT_MTISP_SGBRG10:
+ case V4L2_PIX_FMT_MTISP_SGRBG10:
+ case V4L2_PIX_FMT_MTISP_SRGGB10:
+ return MTK_CAM_IMG_FMT_BAYER10;
+ case V4L2_PIX_FMT_MTISP_SBGGR10F:
+ case V4L2_PIX_FMT_MTISP_SGBRG10F:
+ case V4L2_PIX_FMT_MTISP_SGRBG10F:
+ case V4L2_PIX_FMT_MTISP_SRGGB10F:
+ return MTK_CAM_IMG_FMT_FG_BAYER10;
+ case V4L2_PIX_FMT_MTISP_SBGGR12:
+ case V4L2_PIX_FMT_MTISP_SGBRG12:
+ case V4L2_PIX_FMT_MTISP_SGRBG12:
+ case V4L2_PIX_FMT_MTISP_SRGGB12:
+ return MTK_CAM_IMG_FMT_BAYER12;
+ case V4L2_PIX_FMT_MTISP_SBGGR12F:
+ case V4L2_PIX_FMT_MTISP_SGBRG12F:
+ case V4L2_PIX_FMT_MTISP_SGRBG12F:
+ case V4L2_PIX_FMT_MTISP_SRGGB12F:
+ return MTK_CAM_IMG_FMT_FG_BAYER12;
+ case V4L2_PIX_FMT_MTISP_SBGGR14:
+ case V4L2_PIX_FMT_MTISP_SGBRG14:
+ case V4L2_PIX_FMT_MTISP_SGRBG14:
+ case V4L2_PIX_FMT_MTISP_SRGGB14:
+ return MTK_CAM_IMG_FMT_BAYER14;
+ case V4L2_PIX_FMT_MTISP_SBGGR14F:
+ case V4L2_PIX_FMT_MTISP_SGBRG14F:
+ case V4L2_PIX_FMT_MTISP_SGRBG14F:
+ case V4L2_PIX_FMT_MTISP_SRGGB14F:
+ return MTK_CAM_IMG_FMT_FG_BAYER14;
+ default:
+ return MTK_CAM_IMG_FMT_UNKNOWN;
+ }
+}
+
+static int config_img_fmt(struct mtk_cam_dev *cam, unsigned int node_id,
+ struct p1_img_output *out_fmt, int sd_width,
+ int sd_height)
+{
+ const struct v4l2_format *cfg_fmt = &cam->vdev_nodes[node_id].vdev_fmt;
+
+ /* Check output & input image size dimension */
+ if (cfg_fmt->fmt.pix_mp.width > sd_width ||
+ cfg_fmt->fmt.pix_mp.height > sd_height) {
+ dev_err(cam->dev, "node:%d cfg size is larger than sensor\n",
+ node_id);
+ return -EINVAL;
+ }
+
+ /* Check resize ratio for resize out stream due to HW constraint */
+ if (((cfg_fmt->fmt.pix_mp.width * 100 / sd_width) <
+ MTK_ISP_MIN_RESIZE_RATIO) ||
+ ((cfg_fmt->fmt.pix_mp.height * 100 / sd_height) <
+ MTK_ISP_MIN_RESIZE_RATIO)) {
+ dev_err(cam->dev, "node:%d resize ratio is less than %d%%\n",
+ node_id, MTK_ISP_MIN_RESIZE_RATIO);
+ return -EINVAL;
+ }
+
+ out_fmt->img_fmt = get_img_fmt(cfg_fmt->fmt.pix_mp.pixelformat);
+ out_fmt->pixel_bits = get_pixel_bits(cfg_fmt->fmt.pix_mp.pixelformat);
+ if (out_fmt->img_fmt == MTK_CAM_IMG_FMT_UNKNOWN ||
+ !out_fmt->pixel_bits) {
+ dev_err(cam->dev, "node:%d unknown pixel fmt:%d\n",
+ node_id, cfg_fmt->fmt.pix_mp.pixelformat);
+ return -EINVAL;
+ }
+ dev_dbg(cam->dev, "node:%d pixel_bits:%d img_fmt:0x%x\n",
+ node_id, out_fmt->pixel_bits, out_fmt->img_fmt);
+
+ out_fmt->size.w = cfg_fmt->fmt.pix_mp.width;
+ out_fmt->size.h = cfg_fmt->fmt.pix_mp.height;
+ out_fmt->size.stride = cfg_fmt->fmt.pix_mp.plane_fmt[0].bytesperline;
+ out_fmt->size.xsize = cfg_fmt->fmt.pix_mp.plane_fmt[0].bytesperline;
+
+ out_fmt->crop.left = 0;
+ out_fmt->crop.top = 0;
+ out_fmt->crop.width = sd_width;
+ out_fmt->crop.height = sd_height;
+
+ dev_dbg(cam->dev,
+ "node:%d size=%0dx%0d, stride:%d, xsize:%d, crop=%0dx%0d\n",
+ node_id, out_fmt->size.w, out_fmt->size.h,
+ out_fmt->size.stride, out_fmt->size.xsize,
+ out_fmt->crop.width, out_fmt->crop.height);
+
+ return 0;
+}
+
+static void mtk_cam_dev_init_stream(struct mtk_cam_dev *cam)
+{
+ int i;
+
+ cam->enabled_count = 0;
+ cam->enabled_dmas = 0;
+ cam->stream_count = 0;
+ cam->running_job_count = 0;
+
+ /* Get the enabled meta DMA ports */
+ for (i = 0; i < MTK_CAM_P1_TOTAL_NODES; i++) {
+ if (!cam->vdev_nodes[i].enabled)
+ continue;
+ cam->enabled_count++;
+ cam->enabled_dmas |= cam->vdev_nodes[i].desc.dma_port;
+ }
+
+ dev_dbg(cam->dev, "%s:%d:0x%x\n", __func__, cam->enabled_count,
+ cam->enabled_dmas);
+}
+
+static int mtk_cam_dev_isp_config(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ struct p1_config_param config_param;
+ struct cfg_in_param *cfg_in_param;
+ struct v4l2_subdev_format sd_fmt;
+ int sd_width, sd_height, sd_code;
+ unsigned int enabled_dma_ports = cam->enabled_dmas;
+ int ret;
+
+ /* Get sensor format configuration */
+ sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ ret = v4l2_subdev_call(cam->sensor, pad, get_fmt, NULL, &sd_fmt);
+ if (ret) {
+ dev_dbg(dev, "sensor g_fmt failed:%d\n", ret);
+ return ret;
+ }
+ sd_width = sd_fmt.format.width;
+ sd_height = sd_fmt.format.height;
+ sd_code = sd_fmt.format.code;
+ dev_dbg(dev, "sd fmt w*h=%d*%d, code=0x%x\n", sd_width, sd_height,
+ sd_code);
+
+ memset(&config_param, 0, sizeof(config_param));
+
+ /* Update cfg_in_param */
+ cfg_in_param = &config_param.cfg_in_param;
+ cfg_in_param->continuous = true;
+ /* Fix to one pixel mode in default */
+ cfg_in_param->pixel_mode = MTK_ISP_ONE_PIXEL_MODE;
+ cfg_in_param->crop.width = sd_width;
+ cfg_in_param->crop.height = sd_height;
+ cfg_in_param->raw_pixel_id = get_sensor_pixel_id(sd_code);
+ cfg_in_param->img_fmt = get_sensor_fmt(sd_code);
+ if (cfg_in_param->img_fmt == MTK_CAM_IMG_FMT_UNKNOWN ||
+ cfg_in_param->raw_pixel_id == MTK_CAM_RAW_PXL_ID_UNKNOWN) {
+ dev_err(dev, "unknown sd code:%d\n", sd_code);
+ return -EINVAL;
+ }
+
+ /* Update cfg_main_param */
+ config_param.cfg_main_param.pure_raw = true;
+ config_param.cfg_main_param.pure_raw_pack = true;
+ ret = config_img_fmt(cam, MTK_CAM_P1_MAIN_STREAM_OUT,
+ &config_param.cfg_main_param.output,
+ sd_width, sd_height);
+ if (ret)
+ return ret;
+
+ /* Update cfg_resize_param */
+ if (enabled_dma_ports & R_RRZO) {
+ ret = config_img_fmt(cam, MTK_CAM_P1_PACKED_BIN_OUT,
+ &config_param.cfg_resize_param.output,
+ sd_width, sd_height);
+ if (ret)
+ return ret;
+ } else {
+ config_param.cfg_resize_param.bypass = true;
+ }
+
+ /* Update enabled_dmas */
+ config_param.enabled_dmas = enabled_dma_ports;
+ mtk_isp_hw_config(cam, &config_param);
+ dev_dbg(dev, "%s done\n", __func__);
+
+ return 0;
+}
+
+void mtk_cam_dev_event_frame_sync(struct mtk_cam_dev *cam,
+ unsigned int frame_seq_no)
+{
+ struct v4l2_event event = {
+ .type = V4L2_EVENT_FRAME_SYNC,
+ .u.frame_sync.frame_sequence = frame_seq_no,
+ };
+
+ v4l2_event_queue(cam->subdev.devnode, &event);
+}
+
+static struct v4l2_subdev *
+mtk_cam_cio_get_active_sensor(struct mtk_cam_dev *cam)
+{
+ struct media_device *mdev = cam->seninf->entity.graph_obj.mdev;
+ struct device *dev = cam->dev;
+ struct media_entity *entity;
+ struct v4l2_subdev *sensor;
+
+ sensor = NULL;
+ media_device_for_each_entity(entity, mdev) {
+ dev_dbg(dev, "media entity: %s:0x%x:%d\n",
+ entity->name, entity->function, entity->stream_count);
+ if (entity->function == MEDIA_ENT_F_CAM_SENSOR &&
+ entity->stream_count) {
+ sensor = media_entity_to_v4l2_subdev(entity);
+ dev_dbg(dev, "sensor found: %s\n", entity->name);
+ break;
+ }
+ }
+
+ if (!sensor)
+ dev_err(dev, "no seninf connected\n");
+
+ return sensor;
+}
+
+static int mtk_cam_cio_stream_on(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ int ret;
+
+ if (!cam->seninf) {
+ dev_err(dev, "no seninf connected\n");
+ return -ENODEV;
+ }
+
+ /* Get active sensor from graph topology */
+ cam->sensor = mtk_cam_cio_get_active_sensor(cam);
+ if (!cam->sensor)
+ return -ENODEV;
+
+ /* Seninf must stream on first */
+ ret = v4l2_subdev_call(cam->seninf, video, s_stream, 1);
+ if (ret) {
+ dev_err(dev, "failed to stream on %s:%d\n",
+ cam->seninf->entity.name, ret);
+ return ret;
+ }
+
+ ret = v4l2_subdev_call(cam->sensor, video, s_stream, 1);
+ if (ret) {
+ dev_err(dev, "failed to stream on %s:%d\n",
+ cam->sensor->entity.name, ret);
+ goto fail_seninf_off;
+ }
+
+ ret = mtk_cam_dev_isp_config(cam);
+ if (ret)
+ goto fail_sensor_off;
+
+ cam->streaming = true;
+ mtk_isp_stream(cam, 1);
+ mtk_cam_dev_req_try_queue(cam);
+ dev_dbg(dev, "streamed on Pass 1\n");
+
+ return 0;
+
+fail_sensor_off:
+ v4l2_subdev_call(cam->sensor, video, s_stream, 0);
+fail_seninf_off:
+ v4l2_subdev_call(cam->seninf, video, s_stream, 0);
+
+ return ret;
+}
+
+static int mtk_cam_cio_stream_off(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ int ret;
+
+ ret = v4l2_subdev_call(cam->sensor, video, s_stream, 0);
+ if (ret) {
+ dev_err(dev, "failed to stream off %s:%d\n",
+ cam->sensor->entity.name, ret);
+ return -EPERM;
+ }
+
+ ret = v4l2_subdev_call(cam->seninf, video, s_stream, 0);
+ if (ret) {
+ dev_err(dev, "failed to stream off %s:%d\n",
+ cam->seninf->entity.name, ret);
+ return -EPERM;
+ }
+
+ cam->streaming = false;
+ mtk_isp_stream(cam, 0);
+ mtk_isp_hw_release(cam);
+
+ dev_dbg(dev, "streamed off Pass 1\n");
+
+ return 0;
+}
+
+static int mtk_cam_sd_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct mtk_cam_dev *cam = container_of(sd, struct mtk_cam_dev, subdev);
+
+ if (enable) {
+ /* Align vb2_core_streamon design */
+ if (cam->streaming) {
+ dev_warn(cam->dev, "already streaming on\n");
+ return 0;
+ }
+ return mtk_cam_cio_stream_on(cam);
+ }
+
+ if (!cam->streaming) {
+ dev_warn(cam->dev, "already streaming off\n");
+ return 0;
+ }
+ return mtk_cam_cio_stream_off(cam);
+}
+
+static int mtk_cam_sd_subscribe_event(struct v4l2_subdev *subdev,
+ struct v4l2_fh *fh,
+ struct v4l2_event_subscription *sub)
+{
+ switch (sub->type) {
+ case V4L2_EVENT_FRAME_SYNC:
+ return v4l2_event_subscribe(fh, sub, 0, NULL);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int mtk_cam_media_link_setup(struct media_entity *entity,
+ const struct media_pad *local,
+ const struct media_pad *remote, u32 flags)
+{
+ struct mtk_cam_dev *cam =
+ container_of(entity, struct mtk_cam_dev, subdev.entity);
+ u32 pad = local->index;
+
+ dev_dbg(cam->dev, "%s: %d->%d flags:0x%x\n",
+ __func__, pad, remote->index, flags);
+
+ /*
+ * The video nodes exposed by the driver have pads indexes
+ * from 0 to MTK_CAM_P1_TOTAL_NODES - 1.
+ */
+ if (pad < MTK_CAM_P1_TOTAL_NODES)
+ cam->vdev_nodes[pad].enabled =
+ !!(flags & MEDIA_LNK_FL_ENABLED);
+
+ return 0;
+}
+
+static void mtk_cam_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct mtk_cam_dev_buffer *buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ struct mtk_cam_dev_request *req = mtk_cam_req_to_dev_req(vb->request);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct device *dev = cam->dev;
+ unsigned long flags;
+
+ dev_dbg(dev, "%s: node:%d fd:%d idx:%d\n", __func__,
+ node->id, buf->vbb.request_fd, buf->vbb.vb2_buf.index);
+
+ /* added the buffer into the tracking list */
+ spin_lock_irqsave(&node->buf_list_lock, flags);
+ list_add_tail(&buf->list, &node->buf_list);
+ spin_unlock_irqrestore(&node->buf_list_lock, flags);
+
+ /* update buffer internal address */
+ req->frame_params.dma_bufs[buf->node_id].iova = buf->daddr;
+ req->frame_params.dma_bufs[buf->node_id].scp_addr = buf->scp_addr;
+}
+
+static int mtk_cam_vb2_buf_init(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct device *dev = cam->dev;
+ struct mtk_cam_dev_buffer *buf;
+ dma_addr_t addr;
+
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ buf->node_id = node->id;
+ buf->daddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+ buf->scp_addr = 0;
+
+ /* SCP address is only valid for meta input buffer */
+ if (!node->desc.smem_alloc)
+ return 0;
+
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ /* Use coherent address to get iova address */
+ addr = dma_map_resource(dev, buf->daddr, vb->planes[0].length,
+ DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
+ if (dma_mapping_error(dev, addr)) {
+ dev_err(dev, "failed to map meta addr:%pad\n", &buf->daddr);
+ return -EFAULT;
+ }
+ buf->scp_addr = buf->daddr;
+ buf->daddr = addr;
+
+ return 0;
+}
+
+static int mtk_cam_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb);
+ const struct v4l2_format *fmt = &node->vdev_fmt;
+ unsigned int size;
+
+ if (vb->vb2_queue->type == V4L2_BUF_TYPE_META_OUTPUT ||
+ vb->vb2_queue->type == V4L2_BUF_TYPE_META_CAPTURE)
+ size = fmt->fmt.meta.buffersize;
+ else
+ size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
+
+ if (vb2_plane_size(vb, 0) < size) {
+ dev_dbg(cam->dev, "plane size is too small:%lu<%u\n",
+ vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+
+ if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
+ if (vb2_get_plane_payload(vb, 0) != size) {
+ dev_dbg(cam->dev, "plane payload is mismatch:%lu:%u\n",
+ vb2_get_plane_payload(vb, 0), size);
+ return -EINVAL;
+ }
+ return 0;
+ }
+
+ v4l2_buf->field = V4L2_FIELD_NONE;
+ vb2_set_plane_payload(vb, 0, size);
+
+ return 0;
+}
+
+static void mtk_cam_vb2_buf_cleanup(struct vb2_buffer *vb)
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vb->vb2_queue);
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vb->vb2_queue);
+ struct mtk_cam_dev_buffer *buf;
+ struct device *dev = cam->dev;
+
+ if (!node->desc.smem_alloc)
+ return;
+
+ buf = mtk_cam_vb2_buf_to_dev_buf(vb);
+ dma_unmap_page_attrs(dev, buf->daddr,
+ vb->planes[0].length,
+ DMA_BIDIRECTIONAL,
+ DMA_ATTR_SKIP_CPU_SYNC);
+}
+
+static void mtk_cam_vb2_request_complete(struct vb2_buffer *vb)
+{
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vb->vb2_queue);
+
+ dev_dbg(cam->dev, "%s\n", __func__);
+}
+
+static int mtk_cam_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ unsigned int max_buffer_count = node->desc.max_buf_count;
+ const struct v4l2_format *fmt = &node->vdev_fmt;
+ unsigned int size;
+
+ /* Check the limitation of buffer size */
+ if (max_buffer_count)
+ *num_buffers = clamp_val(*num_buffers, 1, max_buffer_count);
+
+ if (node->desc.smem_alloc)
+ vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
+
+ if (vq->type == V4L2_BUF_TYPE_META_OUTPUT ||
+ vq->type == V4L2_BUF_TYPE_META_CAPTURE)
+ size = fmt->fmt.meta.buffersize;
+ else
+ size = fmt->fmt.pix_mp.plane_fmt[0].sizeimage;
+
+ /* Add for q.create_bufs with fmt.g_sizeimage(p) / 2 test */
+ if (*num_planes) {
+ if (sizes[0] < size || *num_planes != 1)
+ return -EINVAL;
+ } else {
+ *num_planes = 1;
+ sizes[0] = size;
+ }
+
+ return 0;
+}
+
+static void mtk_cam_vb2_return_all_buffers(struct mtk_cam_dev *cam,
+ struct mtk_cam_video_device *node,
+ enum vb2_buffer_state state)
+{
+ struct mtk_cam_dev_buffer *buf, *buf_prev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&node->buf_list_lock, flags);
+ list_for_each_entry_safe(buf, buf_prev, &node->buf_list, list) {
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vbb.vb2_buf, state);
+ }
+ spin_unlock_irqrestore(&node->buf_list_lock, flags);
+}
+
+static int mtk_cam_vb2_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vq);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ struct device *dev = cam->dev;
+ int ret;
+
+ if (!node->enabled) {
+ dev_err(dev, "Node:%d is not enabled\n", node->id);
+ ret = -ENOLINK;
+ goto fail_ret_buf;
+ }
+
+ mutex_lock(&cam->op_lock);
+ /* Start streaming of the whole pipeline now*/
+ if (!cam->pipeline.streaming_count) {
+ ret = media_pipeline_start(&node->vdev.entity, &cam->pipeline);
+ if (ret) {
+ dev_err(dev, "failed to start pipeline:%d\n", ret);
+ goto fail_unlock;
+ }
+ mtk_cam_dev_init_stream(cam);
+ ret = mtk_isp_hw_init(cam);
+ if (ret) {
+ dev_err(dev, "failed to init HW:%d\n", ret);
+ goto fail_stop_pipeline;
+ }
+ }
+
+ /* Media links are fixed after media_pipeline_start */
+ cam->stream_count++;
+ dev_dbg(dev, "%s: count info:%d:%d\n", __func__, cam->stream_count,
+ cam->enabled_count);
+ if (cam->stream_count < cam->enabled_count) {
+ mutex_unlock(&cam->op_lock);
+ return 0;
+ }
+
+ /* Stream on sub-devices node */
+ ret = v4l2_subdev_call(&cam->subdev, video, s_stream, 1);
+ if (ret)
+ goto fail_no_stream;
+ mutex_unlock(&cam->op_lock);
+
+ return 0;
+
+fail_no_stream:
+ cam->stream_count--;
+fail_stop_pipeline:
+ if (cam->stream_count == 0)
+ media_pipeline_stop(&node->vdev.entity);
+fail_unlock:
+ mutex_unlock(&cam->op_lock);
+fail_ret_buf:
+ mtk_cam_vb2_return_all_buffers(cam, node, VB2_BUF_STATE_QUEUED);
+
+ return ret;
+}
+
+static void mtk_cam_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct mtk_cam_dev *cam = vb2_get_drv_priv(vq);
+ struct mtk_cam_video_device *node = mtk_cam_vbq_to_vdev(vq);
+ struct device *dev = cam->dev;
+
+ mutex_lock(&cam->op_lock);
+ dev_dbg(dev, "%s node:%d count info:%d\n", __func__, node->id,
+ cam->stream_count);
+ /* Check the first node to stream-off */
+ if (cam->stream_count == cam->enabled_count)
+ v4l2_subdev_call(&cam->subdev, video, s_stream, 0);
+
+ mtk_cam_vb2_return_all_buffers(cam, node, VB2_BUF_STATE_ERROR);
+ cam->stream_count--;
+ if (cam->stream_count) {
+ mutex_unlock(&cam->op_lock);
+ return;
+ }
+ mutex_unlock(&cam->op_lock);
+
+ mtk_cam_dev_req_cleanup(cam);
+ media_pipeline_stop(&node->vdev.entity);
+}
+
+static int mtk_cam_vidioc_querycap(struct file *file, void *fh,
+ struct v4l2_capability *cap)
+{
+ struct mtk_cam_dev *cam = video_drvdata(file);
+
+ strscpy(cap->driver, dev_driver_string(cam->dev), sizeof(cap->driver));
+ strscpy(cap->card, dev_driver_string(cam->dev), sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+ dev_name(cam->dev));
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ if (f->index >= node->desc.num_fmts)
+ return -EINVAL;
+
+ /* f->description is filled in v4l_fill_fmtdesc function */
+ f->pixelformat = node->desc.fmts[f->index].fmt.pix_mp.pixelformat;
+ f->flags = 0;
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_g_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ f->fmt = node->vdev_fmt.fmt;
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_try_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_dev *cam = video_drvdata(file);
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+ struct device *dev = cam->dev;
+ const struct v4l2_format *dev_fmt;
+ struct v4l2_format try_fmt;
+
+ memset(&try_fmt, 0, sizeof(try_fmt));
+ try_fmt.type = f->type;
+
+ /* Validate pixelformat */
+ dev_fmt = mtk_cam_dev_find_fmt(&node->desc, f->fmt.pix_mp.pixelformat);
+ if (!dev_fmt) {
+ dev_dbg(dev, "unknown fmt:%d\n", f->fmt.pix_mp.pixelformat);
+ dev_fmt = &node->desc.fmts[node->desc.default_fmt_idx];
+ }
+ try_fmt.fmt.pix_mp.pixelformat = dev_fmt->fmt.pix_mp.pixelformat;
+
+ /* Validate image width & height range */
+ try_fmt.fmt.pix_mp.width = clamp_val(f->fmt.pix_mp.width,
+ IMG_MIN_WIDTH, IMG_MAX_WIDTH);
+ try_fmt.fmt.pix_mp.height = clamp_val(f->fmt.pix_mp.height,
+ IMG_MIN_HEIGHT, IMG_MAX_HEIGHT);
+ /* 4 bytes alignment for width */
+ try_fmt.fmt.pix_mp.width = ALIGN(try_fmt.fmt.pix_mp.width, 4);
+
+ /* Only support one plane */
+ try_fmt.fmt.pix_mp.num_planes = 1;
+
+ /* bytesperline & sizeimage calculation */
+ cal_image_pix_mp(cam, node->id, &try_fmt.fmt.pix_mp);
+
+ /* Constant format fields */
+ try_fmt.fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+ try_fmt.fmt.pix_mp.field = V4L2_FIELD_NONE;
+ try_fmt.fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ try_fmt.fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ try_fmt.fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_SRGB;
+
+ *f = try_fmt;
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_s_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_dev *cam = video_drvdata(file);
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ if (vb2_is_busy(node->vdev.queue)) {
+ dev_dbg(cam->dev, "%s: queue is busy\n", __func__);
+ return -EBUSY;
+ }
+
+ /* Get the valid format */
+ mtk_cam_vidioc_try_fmt(file, fh, f);
+ /* Configure to video device */
+ node->vdev_fmt = *f;
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_enum_framesizes(struct file *filp, void *priv,
+ struct v4l2_frmsizeenum *sizes)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(filp);
+ const struct v4l2_format *dev_fmt;
+
+ dev_fmt = mtk_cam_dev_find_fmt(&node->desc, sizes->pixel_format);
+ if (!dev_fmt || sizes->index)
+ return -EINVAL;
+
+ sizes->type = node->desc.frmsizes->type;
+ memcpy(&sizes->stepwise, &node->desc.frmsizes->stepwise,
+ sizeof(sizes->stepwise));
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_meta_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ if (f->index)
+ return -EINVAL;
+
+ /* f->description is filled in v4l_fill_fmtdesc function */
+ f->pixelformat = node->vdev_fmt.fmt.meta.dataformat;
+ f->flags = 0;
+
+ return 0;
+}
+
+static int mtk_cam_vidioc_g_meta_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct mtk_cam_video_device *node = file_to_mtk_cam_node(file);
+
+ f->fmt.meta.dataformat = node->vdev_fmt.fmt.meta.dataformat;
+ f->fmt.meta.buffersize = node->vdev_fmt.fmt.meta.buffersize;
+
+ return 0;
+}
+
+static const struct v4l2_subdev_core_ops mtk_cam_subdev_core_ops = {
+ .subscribe_event = mtk_cam_sd_subscribe_event,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_video_ops mtk_cam_subdev_video_ops = {
+ .s_stream = mtk_cam_sd_s_stream,
+};
+
+static const struct v4l2_subdev_ops mtk_cam_subdev_ops = {
+ .core = &mtk_cam_subdev_core_ops,
+ .video = &mtk_cam_subdev_video_ops,
+};
+
+static const struct media_entity_operations mtk_cam_media_entity_ops = {
+ .link_setup = mtk_cam_media_link_setup,
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct vb2_ops mtk_cam_vb2_ops = {
+ .queue_setup = mtk_cam_vb2_queue_setup,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .buf_init = mtk_cam_vb2_buf_init,
+ .buf_prepare = mtk_cam_vb2_buf_prepare,
+ .start_streaming = mtk_cam_vb2_start_streaming,
+ .stop_streaming = mtk_cam_vb2_stop_streaming,
+ .buf_queue = mtk_cam_vb2_buf_queue,
+ .buf_cleanup = mtk_cam_vb2_buf_cleanup,
+ .buf_request_complete = mtk_cam_vb2_request_complete,
+};
+
+static const struct v4l2_file_operations mtk_cam_v4l2_fops = {
+ .unlocked_ioctl = video_ioctl2,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .poll = vb2_fop_poll,
+ .mmap = vb2_fop_mmap,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl32 = v4l2_compat_ioctl32,
+#endif
+};
+
+static const struct media_device_ops mtk_cam_media_ops = {
+ .req_alloc = mtk_cam_req_alloc,
+ .req_free = mtk_cam_req_free,
+ .req_validate = vb2_request_validate,
+ .req_queue = mtk_cam_req_queue,
+};
+
+static int mtk_cam_media_register(struct mtk_cam_dev *cam,
+ struct media_device *media_dev)
+{
+ /* Reserved MTK_CAM_CIO_PAD_SINK + 1 pads to use */
+ unsigned int num_pads = MTK_CAM_CIO_PAD_SINK + 1;
+ struct device *dev = cam->dev;
+ int i, ret;
+
+ media_dev->dev = cam->dev;
+ strscpy(media_dev->model, dev_driver_string(dev),
+ sizeof(media_dev->model));
+ snprintf(media_dev->bus_info, sizeof(media_dev->bus_info),
+ "platform:%s", dev_name(dev));
+ media_dev->hw_revision = 0;
+ media_device_init(media_dev);
+ media_dev->ops = &mtk_cam_media_ops;
+
+ ret = media_device_register(media_dev);
+ if (ret) {
+ dev_err(dev, "failed to register media device:%d\n", ret);
+ return ret;
+ }
+
+ /* Initialize subdev pads */
+ cam->subdev_pads = devm_kcalloc(dev, num_pads,
+ sizeof(*cam->subdev_pads),
+ GFP_KERNEL);
+ if (!cam->subdev_pads) {
+ dev_err(dev, "failed to allocate subdev_pads\n");
+ ret = -ENOMEM;
+ goto fail_media_unreg;
+ }
+
+ ret = media_entity_pads_init(&cam->subdev.entity, num_pads,
+ cam->subdev_pads);
+ if (ret) {
+ dev_err(dev, "failed to initialize media pads:%d\n", ret);
+ goto fail_media_unreg;
+ }
+
+ /* Initialize all pads with MEDIA_PAD_FL_SOURCE */
+ for (i = 0; i < num_pads; i++)
+ cam->subdev_pads[i].flags = MEDIA_PAD_FL_SOURCE;
+
+ /* Customize the last one pad as CIO sink pad. */
+ cam->subdev_pads[MTK_CAM_CIO_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+
+ return 0;
+
+fail_media_unreg:
+ media_device_unregister(&cam->media_dev);
+ media_device_cleanup(&cam->media_dev);
+
+ return ret;
+}
+
+static int
+mtk_cam_video_register_device(struct mtk_cam_dev *cam,
+ struct mtk_cam_video_device *node)
+{
+ struct device *dev = cam->dev;
+ struct video_device *vdev = &node->vdev;
+ struct vb2_queue *vbq = &node->vbq;
+ unsigned int output = V4L2_TYPE_IS_OUTPUT(node->desc.buf_type);
+ unsigned int link_flags = node->desc.link_flags;
+ int ret;
+
+ /* Initialize mtk_cam_video_device */
+ if (link_flags & MEDIA_LNK_FL_IMMUTABLE)
+ node->enabled = true;
+ else
+ node->enabled = false;
+ mtk_cam_dev_load_default_fmt(cam, &node->desc, &node->vdev_fmt);
+
+ cam->subdev_pads[node->id].flags = output ?
+ MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
+
+ /* Initialize media entities */
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->vdev_pad);
+ if (ret) {
+ dev_err(dev, "failed to initialize media pad:%d\n", ret);
+ return ret;
+ }
+ node->vdev_pad.flags = output ? MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;
+
+ /* Initialize vbq */
+ vbq->type = node->desc.buf_type;
+ if (vbq->type == V4L2_BUF_TYPE_META_OUTPUT)
+ vbq->io_modes = VB2_MMAP;
+ else
+ vbq->io_modes = VB2_MMAP | VB2_DMABUF;
+
+ if (node->desc.smem_alloc) {
+ vbq->bidirectional = 1;
+ vbq->dev = cam->smem_dev;
+ } else {
+ vbq->dev = dev;
+ }
+ vbq->ops = &mtk_cam_vb2_ops;
+ vbq->mem_ops = &vb2_dma_contig_memops;
+ vbq->buf_struct_size = sizeof(struct mtk_cam_dev_buffer);
+ vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_BOOTIME;
+ if (output)
+ vbq->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_EOF;
+ else
+ vbq->timestamp_flags |= V4L2_BUF_FLAG_TSTAMP_SRC_SOE;
+ /* No minimum buffers limitation */
+ vbq->min_buffers_needed = 0;
+ vbq->drv_priv = cam;
+ vbq->lock = &node->vdev_lock;
+ vbq->supports_requests = true;
+ vbq->requires_requests = true;
+
+ ret = vb2_queue_init(vbq);
+ if (ret) {
+ dev_err(dev, "failed to init. vb2 queue:%d\n", ret);
+ goto fail_media_clean;
+ }
+
+ /* Initialize vdev */
+ snprintf(vdev->name, sizeof(vdev->name), "%s %s",
+ dev_driver_string(dev), node->desc.name);
+ /* set cap/type/ioctl_ops of the video device */
+ vdev->device_caps = node->desc.cap | V4L2_CAP_STREAMING;
+ vdev->ioctl_ops = node->desc.ioctl_ops;
+ vdev->fops = &mtk_cam_v4l2_fops;
+ vdev->release = video_device_release_empty;
+ vdev->lock = &node->vdev_lock;
+ vdev->v4l2_dev = &cam->v4l2_dev;
+ vdev->queue = &node->vbq;
+ vdev->vfl_dir = output ? VFL_DIR_TX : VFL_DIR_RX;
+ vdev->entity.function = MEDIA_ENT_F_IO_V4L;
+ vdev->entity.ops = NULL;
+ video_set_drvdata(vdev, cam);
+ dev_dbg(dev, "registered vdev:%d:%s\n", node->id, vdev->name);
+
+ /* Initialize miscellaneous variables */
+ mutex_init(&node->vdev_lock);
+ INIT_LIST_HEAD(&node->buf_list);
+ spin_lock_init(&node->buf_list_lock);
+
+ ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
+ if (ret) {
+ dev_err(dev, "failed to register vde:%d\n", ret);
+ goto fail_vb2_rel;
+ }
+
+ /* Create link between video node and the subdev pad */
+ if (output) {
+ ret = media_create_pad_link(&vdev->entity, 0,
+ &cam->subdev.entity,
+ node->id, link_flags);
+ } else {
+ ret = media_create_pad_link(&cam->subdev.entity,
+ node->id, &vdev->entity, 0,
+ link_flags);
+ }
+ if (ret)
+ goto fail_vdev_ureg;
+
+ return 0;
+
+fail_vdev_ureg:
+ video_unregister_device(vdev);
+fail_vb2_rel:
+ mutex_destroy(&node->vdev_lock);
+ vb2_queue_release(vbq);
+fail_media_clean:
+ media_entity_cleanup(&vdev->entity);
+
+ return ret;
+}
+
+static void
+mtk_cam_video_unregister_device(struct mtk_cam_video_device *node)
+{
+ video_unregister_device(&node->vdev);
+ media_entity_cleanup(&node->vdev.entity);
+ mutex_destroy(&node->vdev_lock);
+}
+
+static int mtk_cam_v4l2_register(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ int i, ret;
+
+ /* Set up media device & pads */
+ ret = mtk_cam_media_register(cam, &cam->media_dev);
+ if (ret)
+ return ret;
+ dev_info(dev, "Registered media%d\n", cam->media_dev.devnode->minor);
+
+ /* Set up v4l2 device */
+ cam->v4l2_dev.mdev = &cam->media_dev;
+ ret = v4l2_device_register(dev, &cam->v4l2_dev);
+ if (ret) {
+ dev_err(dev, "failed to register V4L2 device:%d\n", ret);
+ goto fail_media_unreg;
+ }
+ dev_info(dev, "Registered %s\n", cam->v4l2_dev.name);
+
+ /* Initialize subdev */
+ v4l2_subdev_init(&cam->subdev, &mtk_cam_subdev_ops);
+ cam->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
+ cam->subdev.entity.ops = &mtk_cam_media_entity_ops;
+ cam->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE |
+ V4L2_SUBDEV_FL_HAS_EVENTS;
+ snprintf(cam->subdev.name, sizeof(cam->subdev.name),
+ "%s", dev_driver_string(dev));
+ v4l2_set_subdevdata(&cam->subdev, cam);
+
+ ret = v4l2_device_register_subdev(&cam->v4l2_dev, &cam->subdev);
+ if (ret) {
+ dev_err(dev, "failed to initialize subdev:%d\n", ret);
+ goto fail_clean_media_entiy;
+ }
+ dev_dbg(dev, "registered %s\n", cam->subdev.name);
+
+ /* Create video nodes and links */
+ for (i = 0; i < MTK_CAM_P1_TOTAL_NODES; i++) {
+ struct mtk_cam_video_device *node = &cam->vdev_nodes[i];
+
+ node->id = node->desc.id;
+ ret = mtk_cam_video_register_device(cam, node);
+ if (ret)
+ goto fail_vdev_unreg;
+ }
+ vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
+
+ return 0;
+
+fail_vdev_unreg:
+ for (i--; i >= 0; i--)
+ mtk_cam_video_unregister_device(&cam->vdev_nodes[i]);
+fail_clean_media_entiy:
+ media_entity_cleanup(&cam->subdev.entity);
+ v4l2_device_unregister(&cam->v4l2_dev);
+fail_media_unreg:
+ media_device_unregister(&cam->media_dev);
+ media_device_cleanup(&cam->media_dev);
+
+ return ret;
+}
+
+static int mtk_cam_v4l2_unregister(struct mtk_cam_dev *cam)
+{
+ int i;
+
+ for (i = 0; i < MTK_CAM_P1_TOTAL_NODES; i++)
+ mtk_cam_video_unregister_device(&cam->vdev_nodes[i]);
+
+ vb2_dma_contig_clear_max_seg_size(cam->dev);
+ v4l2_device_unregister_subdev(&cam->subdev);
+ v4l2_device_unregister(&cam->v4l2_dev);
+ media_entity_cleanup(&cam->subdev.entity);
+ media_device_unregister(&cam->media_dev);
+ media_device_cleanup(&cam->media_dev);
+
+ return 0;
+}
+
+static int mtk_cam_dev_notifier_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_subdev *asd)
+{
+ struct mtk_cam_dev *cam =
+ container_of(notifier, struct mtk_cam_dev, notifier);
+
+ if (!(sd->entity.function & MEDIA_ENT_F_VID_IF_BRIDGE)) {
+ dev_dbg(cam->dev, "no MEDIA_ENT_F_VID_IF_BRIDGE function\n");
+ return -ENODEV;
+ }
+
+ cam->seninf = sd;
+ dev_dbg(cam->dev, "%s is bound\n", sd->entity.name);
+
+ return 0;
+}
+
+static void mtk_cam_dev_notifier_unbind(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_subdev *asd)
+{
+ struct mtk_cam_dev *cam =
+ container_of(notifier, struct mtk_cam_dev, notifier);
+
+ cam->seninf = NULL;
+ dev_dbg(cam->dev, "%s is unbound\n", sd->entity.name);
+}
+
+static int mtk_cam_dev_notifier_complete(struct v4l2_async_notifier *notifier)
+{
+ struct mtk_cam_dev *cam =
+ container_of(notifier, struct mtk_cam_dev, notifier);
+ struct device *dev = cam->dev;
+ int ret;
+
+ ret = media_create_pad_link(&cam->seninf->entity, MTK_CAM_CIO_PAD_SRC,
+ &cam->subdev.entity, MTK_CAM_CIO_PAD_SINK,
+ MEDIA_LNK_FL_IMMUTABLE |
+ MEDIA_LNK_FL_ENABLED);
+ if (ret) {
+ dev_err(dev, "failed to create pad link %s %s err:%d\n",
+ cam->seninf->entity.name, cam->subdev.entity.name,
+ ret);
+ return ret;
+ }
+
+ ret = v4l2_device_register_subdev_nodes(&cam->v4l2_dev);
+ if (ret) {
+ dev_err(dev, "failed to initialize subdev nodes:%d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static const struct v4l2_async_notifier_operations mtk_cam_v4l2_async_ops = {
+ .bound = mtk_cam_dev_notifier_bound,
+ .unbind = mtk_cam_dev_notifier_unbind,
+ .complete = mtk_cam_dev_notifier_complete,
+};
+
+static int mtk_cam_v4l2_async_register(struct mtk_cam_dev *cam)
+{
+ struct device *dev = cam->dev;
+ int ret;
+
+ v4l2_async_notifier_init(&cam->notifier);
+ ret = v4l2_async_notifier_parse_fwnode_endpoints(dev,
+ &cam->notifier, sizeof(struct v4l2_async_subdev), NULL);
+ if (ret) {
+ dev_err(dev, "failed to parse fwnode endpoints:%d\n", ret);
+ return ret;
+ }
+
+ cam->notifier.ops = &mtk_cam_v4l2_async_ops;
+ dev_dbg(dev, "mtk_cam v4l2_async_notifier_register\n");
+ ret = v4l2_async_notifier_register(&cam->v4l2_dev, &cam->notifier);
+ if (ret) {
+ dev_err(dev, "failed to register async notifier : %d\n", ret);
+ v4l2_async_notifier_cleanup(&cam->notifier);
+ }
+
+ return ret;
+}
+
+static void mtk_cam_v4l2_async_unregister(struct mtk_cam_dev *cam)
+{
+ v4l2_async_notifier_unregister(&cam->notifier);
+ v4l2_async_notifier_cleanup(&cam->notifier);
+}
+
+static const struct v4l2_ioctl_ops mtk_cam_v4l2_vcap_ioctl_ops = {
+ .vidioc_querycap = mtk_cam_vidioc_querycap,
+ .vidioc_enum_framesizes = mtk_cam_vidioc_enum_framesizes,
+ .vidioc_enum_fmt_vid_cap = mtk_cam_vidioc_enum_fmt,
+ .vidioc_g_fmt_vid_cap_mplane = mtk_cam_vidioc_g_fmt,
+ .vidioc_s_fmt_vid_cap_mplane = mtk_cam_vidioc_s_fmt,
+ .vidioc_try_fmt_vid_cap_mplane = mtk_cam_vidioc_try_fmt,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct v4l2_ioctl_ops mtk_cam_v4l2_meta_cap_ioctl_ops = {
+ .vidioc_querycap = mtk_cam_vidioc_querycap,
+ .vidioc_enum_fmt_meta_cap = mtk_cam_vidioc_meta_enum_fmt,
+ .vidioc_g_fmt_meta_cap = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_s_fmt_meta_cap = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_try_fmt_meta_cap = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+};
+
+static const struct v4l2_ioctl_ops mtk_cam_v4l2_meta_out_ioctl_ops = {
+ .vidioc_querycap = mtk_cam_vidioc_querycap,
+ .vidioc_enum_fmt_meta_out = mtk_cam_vidioc_meta_enum_fmt,
+ .vidioc_g_fmt_meta_out = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_s_fmt_meta_out = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_try_fmt_meta_out = mtk_cam_vidioc_g_meta_fmt,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+};
+
+static const struct v4l2_format meta_fmts[] = {
+ {
+ .fmt.meta = {
+ .dataformat = V4L2_META_FMT_MTISP_PARAMS,
+ .buffersize = 512 * SZ_1K,
+ },
+ },
+ {
+ .fmt.meta = {
+ .dataformat = V4L2_META_FMT_MTISP_3A,
+ .buffersize = 1200 * SZ_1K,
+ },
+ },
+ {
+ .fmt.meta = {
+ .dataformat = V4L2_META_FMT_MTISP_AF,
+ .buffersize = 640 * SZ_1K,
+ },
+ },
+ {
+ .fmt.meta = {
+ .dataformat = V4L2_META_FMT_MTISP_LCS,
+ .buffersize = 288 * SZ_1K,
+ },
+ },
+ {
+ .fmt.meta = {
+ .dataformat = V4L2_META_FMT_MTISP_LMV,
+ .buffersize = 256,
+ },
+ },
+};
+
+static const struct v4l2_format stream_out_fmts[] = {
+ /* This is a default image format */
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR10,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR8,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR12,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR14,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG8,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG10,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG12,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG14,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG8,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG10,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG12,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG14,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB8,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB10,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB12,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB14,
+ },
+ },
+};
+
+static const struct v4l2_format bin_out_fmts[] = {
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR8F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR10F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR12F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SBGGR14F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG8F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG10F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG12F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGBRG14F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG8F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG10F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG12F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SGRBG14F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB8F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB10F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB12F,
+ },
+ },
+ {
+ .fmt.pix_mp = {
+ .width = IMG_MAX_WIDTH,
+ .height = IMG_MAX_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_MTISP_SRGGB14F,
+ },
+ },
+};
+
+static const struct
+mtk_cam_dev_node_desc output_queues[] = {
+ {
+ .id = MTK_CAM_P1_META_IN_0,
+ .name = "meta input",
+ .cap = V4L2_CAP_META_OUTPUT,
+ .buf_type = V4L2_BUF_TYPE_META_OUTPUT,
+ .link_flags = 0,
+ .image = false,
+ .smem_alloc = true,
+ .fmts = meta_fmts,
+ .default_fmt_idx = 0,
+ .max_buf_count = 10,
+ .ioctl_ops = &mtk_cam_v4l2_meta_out_ioctl_ops,
+ },
+};
+
+static const struct
+mtk_cam_dev_node_desc capture_queues[] = {
+ {
+ .id = MTK_CAM_P1_MAIN_STREAM_OUT,
+ .name = "main stream",
+ .cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
+ .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+ .link_flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED,
+ .image = true,
+ .smem_alloc = false,
+ .dma_port = R_IMGO,
+ .fmts = stream_out_fmts,
+ .num_fmts = ARRAY_SIZE(stream_out_fmts),
+ .default_fmt_idx = 0,
+ .ioctl_ops = &mtk_cam_v4l2_vcap_ioctl_ops,
+ .frmsizes = &(struct v4l2_frmsizeenum) {
+ .index = 0,
+ .type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+ .stepwise = {
+ .max_width = IMG_MAX_WIDTH,
+ .min_width = IMG_MIN_WIDTH,
+ .max_height = IMG_MAX_HEIGHT,
+ .min_height = IMG_MIN_HEIGHT,
+ .step_height = 1,
+ .step_width = 1,
+ },
+ },
+ },
+ {
+ .id = MTK_CAM_P1_PACKED_BIN_OUT,
+ .name = "packed out",
+ .cap = V4L2_CAP_VIDEO_CAPTURE_MPLANE,
+ .buf_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
+ .link_flags = 0,
+ .image = true,
+ .smem_alloc = false,
+ .dma_port = R_RRZO,
+ .fmts = bin_out_fmts,
+ .num_fmts = ARRAY_SIZE(bin_out_fmts),
+ .default_fmt_idx = 0,
+ .ioctl_ops = &mtk_cam_v4l2_vcap_ioctl_ops,
+ .frmsizes = &(struct v4l2_frmsizeenum) {
+ .index = 0,
+ .type = V4L2_FRMSIZE_TYPE_CONTINUOUS,
+ .stepwise = {
+ .max_width = IMG_MAX_WIDTH,
+ .min_width = IMG_MIN_WIDTH,
+ .max_height = IMG_MAX_HEIGHT,
+ .min_height = IMG_MIN_HEIGHT,
+ .step_height = 1,
+ .step_width = 1,
+ },
+ },
+ },
+ {
+ .id = MTK_CAM_P1_META_OUT_0,
+ .name = "partial meta 0",
+ .cap = V4L2_CAP_META_CAPTURE,
+ .buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+ .link_flags = 0,
+ .image = false,
+ .smem_alloc = false,
+ .dma_port = R_AAO | R_FLKO | R_PSO,
+ .fmts = meta_fmts,
+ .default_fmt_idx = 1,
+ .max_buf_count = 5,
+ .ioctl_ops = &mtk_cam_v4l2_meta_cap_ioctl_ops,
+ },
+ {
+ .id = MTK_CAM_P1_META_OUT_1,
+ .name = "partial meta 1",
+ .cap = V4L2_CAP_META_CAPTURE,
+ .buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+ .link_flags = 0,
+ .image = false,
+ .smem_alloc = false,
+ .dma_port = R_AFO,
+ .fmts = meta_fmts,
+ .default_fmt_idx = 2,
+ .max_buf_count = 5,
+ .ioctl_ops = &mtk_cam_v4l2_meta_cap_ioctl_ops,
+ },
+ {
+ .id = MTK_CAM_P1_META_OUT_2,
+ .name = "partial meta 2",
+ .cap = V4L2_CAP_META_CAPTURE,
+ .buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+ .link_flags = 0,
+ .image = false,
+ .smem_alloc = false,
+ .dma_port = R_LCSO,
+ .fmts = meta_fmts,
+ .default_fmt_idx = 3,
+ .max_buf_count = 10,
+ .ioctl_ops = &mtk_cam_v4l2_meta_cap_ioctl_ops,
+ },
+ {
+ .id = MTK_CAM_P1_META_OUT_3,
+ .name = "partial meta 3",
+ .cap = V4L2_CAP_META_CAPTURE,
+ .buf_type = V4L2_BUF_TYPE_META_CAPTURE,
+ .link_flags = 0,
+ .image = false,
+ .smem_alloc = false,
+ .dma_port = R_LMVO,
+ .fmts = meta_fmts,
+ .default_fmt_idx = 4,
+ .max_buf_count = 10,
+ .ioctl_ops = &mtk_cam_v4l2_meta_cap_ioctl_ops,
+ },
+};
+
+/* The helper to configure the device context */
+static void mtk_cam_dev_queue_setup(struct mtk_cam_dev *cam)
+{
+ unsigned int node_idx;
+ int i;
+
+ node_idx = 0;
+ /* Setup the output queue */
+ for (i = 0; i < ARRAY_SIZE(output_queues); i++)
+ cam->vdev_nodes[node_idx++].desc = output_queues[i];
+
+ /* Setup the capture queue */
+ for (i = 0; i < ARRAY_SIZE(capture_queues); i++)
+ cam->vdev_nodes[node_idx++].desc = capture_queues[i];
+}
+
+int mtk_cam_dev_init(struct platform_device *pdev,
+ struct mtk_cam_dev *cam)
+{
+ int ret;
+
+ cam->dev = &pdev->dev;
+ mtk_cam_dev_queue_setup(cam);
+
+ spin_lock_init(&cam->pending_job_lock);
+ spin_lock_init(&cam->running_job_lock);
+ INIT_LIST_HEAD(&cam->pending_job_list);
+ INIT_LIST_HEAD(&cam->running_job_list);
+ mutex_init(&cam->op_lock);
+
+ /* v4l2 sub-device registration */
+ ret = mtk_cam_v4l2_register(cam);
+ if (ret)
+ return ret;
+
+ ret = mtk_cam_v4l2_async_register(cam);
+ if (ret)
+ goto fail_v4l2_unreg;
+
+ return 0;
+
+fail_v4l2_unreg:
+ mutex_destroy(&cam->op_lock);
+ mtk_cam_v4l2_unregister(cam);
+
+ return ret;
+}
+
+void mtk_cam_dev_cleanup(struct mtk_cam_dev *cam)
+{
+ mtk_cam_v4l2_async_unregister(cam);
+ mtk_cam_v4l2_unregister(cam);
+ mutex_destroy(&cam->op_lock);
+}
+
diff --git a/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.h b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.h
new file mode 100644
index 000000000000..0a340a1e65ea
--- /dev/null
+++ b/drivers/media/platform/mtk-isp/isp_50/cam/mtk_cam.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_CAM_H__
+#define __MTK_CAM_H__
+
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "mtk_cam-ipi.h"
+
+#define IMG_MAX_WIDTH 5376
+#define IMG_MAX_HEIGHT 4032
+#define IMG_MIN_WIDTH 80
+#define IMG_MIN_HEIGHT 60
+
+/*
+ * ID enum value for struct mtk_cam_dev_node_desc:id
+ * or mtk_cam_video_device:id
+ */
+enum {
+ MTK_CAM_P1_META_IN_0 = 0,
+ MTK_CAM_P1_MAIN_STREAM_OUT,
+ MTK_CAM_P1_PACKED_BIN_OUT,
+ MTK_CAM_P1_META_OUT_0,
+ MTK_CAM_P1_META_OUT_1,
+ MTK_CAM_P1_META_OUT_2,
+ MTK_CAM_P1_META_OUT_3,
+ MTK_CAM_P1_TOTAL_NODES
+};
+
+/* Supported image format list */
+#define MTK_CAM_IMG_FMT_UNKNOWN 0x0000
+#define MTK_CAM_IMG_FMT_BAYER8 0x2200
+#define MTK_CAM_IMG_FMT_BAYER10 0x2201
+#define MTK_CAM_IMG_FMT_BAYER12 0x2202
+#define MTK_CAM_IMG_FMT_BAYER14 0x2203
+#define MTK_CAM_IMG_FMT_FG_BAYER8 0x2204
+#define MTK_CAM_IMG_FMT_FG_BAYER10 0x2205
+#define MTK_CAM_IMG_FMT_FG_BAYER12 0x2206
+#define MTK_CAM_IMG_FMT_FG_BAYER14 0x2207
+
+/* Supported bayer pixel order */
+#define MTK_CAM_RAW_PXL_ID_B 0
+#define MTK_CAM_RAW_PXL_ID_GB 1
+#define MTK_CAM_RAW_PXL_ID_GR 2
+#define MTK_CAM_RAW_PXL_ID_R 3
+#define MTK_CAM_RAW_PXL_ID_UNKNOWN 4
+
+/*
+ * struct mtk_p1_frame_param - MTK ISP P1 driver frame parameters.
+ *
+ * @frame_seq_no: The frame sequence of frame in driver layer.
+ * @dma_bufs: The DMA buffer address information of enabled DMA nodes.
+ *
+ */
+struct mtk_p1_frame_param {
+ unsigned int frame_seq_no;
+ struct dma_buffer dma_bufs[MTK_CAM_P1_TOTAL_NODES];
+} __packed;
+
+/*
+ * struct mtk_cam_dev_request - MTK camera device request.
+ *
+ * @req: Embedded struct media request.
+ * @frame_params: The frame info. & address info. of enabled DMA nodes.
+ * @frame_work: work queue entry for frame transmission to SCP.
+ * @list: List entry of the object for @struct mtk_cam_dev:
+ * pending_job_list or running_job_list.
+ * @timestamp: Start of frame timestamp in ns
+ *
+ */
+struct mtk_cam_dev_request {
+ struct media_request req;
+ struct mtk_p1_frame_param frame_params;
+ struct work_struct frame_work;
+ struct list_head list;
+ u64 timestamp;
+};
+
+/*
+ * struct mtk_cam_dev_buffer - MTK camera device buffer.
+ *
+ * @vbb: Embedded struct vb2_v4l2_buffer.
+ * @list: List entry of the object for @struct mtk_cam_video_device:
+ * buf_list.
+ * @daddr: The DMA address of this buffer.
+ * @scp_addr: The SCP address of this buffer which
+ * is only supported for meta input node.
+ * @node_id: The vidoe node id which this buffer belongs to.
+ *
+ */
+struct mtk_cam_dev_buffer {
+ struct vb2_v4l2_buffer vbb;
+ struct list_head list;
+ /* Intenal part */
+ dma_addr_t daddr;
+ dma_addr_t scp_addr;
+ unsigned int node_id;
+};
+
+/*
+ * struct mtk_cam_dev_node_desc - MTK camera device node descriptor
+ *
+ * @id: id of the node
+ * @name: name of the node
+ * @cap: supported V4L2 capabilities
+ * @buf_type: supported V4L2 buffer type
+ * @dma_port: the dma ports associated to the node
+ * @link_flags: default media link flags
+ * @smem_alloc: using the smem_dev as alloc device or not
+ * @image: true for image node, false for meta node
+ * @num_fmts: the number of supported node formats
+ * @default_fmt_idx: default format of this node
+ * @max_buf_count: maximum VB2 buffer count
+ * @ioctl_ops: mapped to v4l2_ioctl_ops
+ * @fmts: supported format
+ * @frmsizes: supported V4L2 frame size number
+ *
+ */
+struct mtk_cam_dev_node_desc {
+ u8 id;
+ const char *name;
+ u32 cap;
+ u32 buf_type;
+ u32 dma_port;
+ u32 link_flags;
+ u8 smem_alloc:1;
+ u8 image:1;
+ u8 num_fmts;
+ u8 default_fmt_idx;
+ u8 max_buf_count;
+ const struct v4l2_ioctl_ops *ioctl_ops;
+ const struct v4l2_format *fmts;
+ const struct v4l2_frmsizeenum *frmsizes;
+};
+
+/*
+ * struct mtk_cam_video_device - Mediatek video device structure
+ *
+ * @id: Id for index of mtk_cam_dev:vdev_nodes array
+ * @enabled: Indicate the video device is enabled or not
+ * @desc: The node description of video device
+ * @vdev_fmt: The V4L2 format of video device
+ * @vdev_pad: The media pad graph object of video device
+ * @vbq: A videobuf queue of video device
+ * @vdev: The video device instance
+ * @vdev_lock: Serializes vb2 queue and video device operations
+ * @buf_list: List for enqueue buffers
+ * @buf_list_lock: Lock used to protect buffer list.
+ *
+ */
+struct mtk_cam_video_device {
+ unsigned int id;
+ unsigned int enabled;
+ struct mtk_cam_dev_node_desc desc;
+ struct v4l2_format vdev_fmt;
+ struct media_pad vdev_pad;
+ struct vb2_queue vbq;
+ struct video_device vdev;
+ /* Serializes vb2 queue and video device operations */
+ struct mutex vdev_lock;
+ struct list_head buf_list;
+ /* Lock used to protect buffer list */
+ spinlock_t buf_list_lock;
+};
+
+/*
+ * struct mtk_cam_dev - Mediatek camera device structure.
+ *
+ * @dev: Pointer to device.
+ * @smem_pdev: Pointer to shared memory device.
+ * @pipeline: Media pipeline information.
+ * @media_dev: Media device instance.
+ * @subdev: The V4L2 sub-device instance.
+ * @v4l2_dev: The V4L2 device driver instance.
+ * @notifier: The v4l2_device notifier data.
+ * @subdev_pads: Pointer to the number of media pads of this sub-device.
+ * @vdev_nodes: The array list of mtk_cam_video_device nodes.
+ * @seninf: Pointer to the seninf sub-device.
+ * @sensor: Pointer to the active sensor V4L2 sub-device when streaming on.
+ * @streaming: Indicate the overall streaming status is on or off.
+ * @enabled_dmas: The enabled dma port information when streaming on.
+ * @enabled_count: Number of enabled video nodes
+ * @stream_count: Number of streaming video nodes
+ * @running_job_count: Nunber of running jobs in the HW driver.
+ * @pending_job_list: List to keep the media requests before en-queue into
+ * HW driver.
+ * @pending_job_lock: Protect the pending_job_list data & running_job_count.
+ * @running_job_list: List to keep the media requests after en-queue into
+ * HW driver.
+ * @running_job_lock: Protect the running_job_list data.
+ * @op_lock: Serializes driver's VB2 callback operations.
+ *
+ */
+struct mtk_cam_dev {
+ struct device *dev;
+ struct device *smem_dev;
+ struct media_pipeline pipeline;
+ struct media_device media_dev;
+ struct v4l2_subdev subdev;
+ struct v4l2_device v4l2_dev;
+ struct v4l2_async_notifier notifier;
+ struct media_pad *subdev_pads;
+ struct mtk_cam_video_device vdev_nodes[MTK_CAM_P1_TOTAL_NODES];
+ struct v4l2_subdev *seninf;
+ struct v4l2_subdev *sensor;
+ unsigned int streaming;
+ unsigned int enabled_dmas;
+ unsigned int enabled_count;
+ unsigned int stream_count;
+ unsigned int running_job_count;
+ struct list_head pending_job_list;
+ /* Protect the pending_job_list data */
+ spinlock_t pending_job_lock;
+ struct list_head running_job_list;
+ /* Protect the running_job_list data & running_job_count */
+ spinlock_t running_job_lock;
+ /* Serializes driver's VB2 callback operations */
+ struct mutex op_lock;
+};
+
+int mtk_cam_dev_init(struct platform_device *pdev,
+ struct mtk_cam_dev *cam_dev);
+void mtk_cam_dev_cleanup(struct mtk_cam_dev *cam_dev);
+void mtk_cam_dev_req_try_queue(struct mtk_cam_dev *cam_dev);
+void mtk_cam_dev_dequeue_req_frame(struct mtk_cam_dev *cam_dev,
+ unsigned int frame_seq_no);
+void mtk_cam_dev_event_frame_sync(struct mtk_cam_dev *cam_dev,
+ unsigned int frame_seq_no);
+struct mtk_cam_dev_request *mtk_cam_dev_get_req(struct mtk_cam_dev *cam,
+ unsigned int frame_seq_no);
+
+#endif /* __MTK_CAM_H__ */
--
2.18.0
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^ permalink raw reply related
* Re: [PATCH 08/26] m68k: simplify ioremap_nocache
From: Geert Uytterhoeven @ 2019-09-02 7:53 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-ia64@vger.kernel.org, Linux-sh list,
Linux Kernel Mailing List, Guo Ren, sparclinux, linux-riscv,
Vincent Chen, Linux-Arch, linux-s390,
open list:QUALCOMM HEXAGON..., the arch/x86 maintainers, arcml,
linux-xtensa, Arnd Bergmann, linux-m68k, Openrisc, Greentime Hu,
MTD Maling List, Guan Xuetao, Linux ARM, Michal Simek,
Parisc List, linux-mips, alpha, nios2-dev
In-Reply-To: <20190830160620.GD26887@lst.de>
Hi Christoph,
On Fri, Aug 30, 2019 at 6:06 PM Christoph Hellwig <hch@lst.de> wrote:
> On Mon, Aug 19, 2019 at 10:56:02AM +0200, Geert Uytterhoeven wrote:
> > On Sat, Aug 17, 2019 at 9:48 AM Christoph Hellwig <hch@lst.de> wrote:
> > > Just define ioremap_nocache to ioremap instead of duplicating the
> > > inline. Also defined ioremap_uc in terms of ioremap instead of
> > > the using a double indirection.
> > >
> > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> >
> > Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
>
> Do you mind picking this up through the m68k tree?
Sure. Applied and queued for v5.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH 0/3] arm64: KVM: Kiss hyp_alternate_select() goodbye
From: Christoffer Dall @ 2019-09-02 8:00 UTC (permalink / raw)
To: Marc Zyngier; +Cc: kvmarm, linux-arm-kernel, kvm
In-Reply-To: <20190901211237.11673-1-maz@kernel.org>
On Sun, Sep 01, 2019 at 10:12:34PM +0100, Marc Zyngier wrote:
> hyp_alternate_select() is a leftover from the my second attempt at
> supporting VHE (the first one was never merged, thankfully), and is
> now an irrelevant relic. It was a way to patch function pointers
> without having to dereference memory, a bit like static keys for
> function calls.
>
> Lovely idea, but since Christoffer mostly separated the VHE and !VHE
> hypervisor paths, most of the uses of hyp_alternate_select() are
> gone. What is left is two instances that are better replaced by
> already existing static keys. One of the instances becomes
> cpus_have_const_cap(), and the rest is a light sprinkling of
> has_vhe().
>
> So off it goes.
I'm not sure I want to kiss hyp_alternate_select() at all, but away it
must go!
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
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^ permalink raw reply
* Re: [PATCH 14/26] asm-generic: don't provide __ioremap
From: Christoph Hellwig @ 2019-09-02 8:01 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: Christoph Hellwig, Cc
In-Reply-To: <CAK8P3a15WV-iNqTJxqgo_EYmTOp8HapTKrd56q0wziKePPMOtA@mail.gmail.com>
On Fri, Aug 30, 2019 at 09:47:45PM +0200, Arnd Bergmann wrote:
> On Fri, Aug 30, 2019 at 6:04 PM Christoph Hellwig <hch@lst.de> wrote:
> >
> > Arnd, can you consider this patch for asm-generic for 5.4? I don't
> > think I'll be able to feed the actual generic ioremap implementation
> > to Linus this merge window, but if we can get as many patches as
> > possible in through their maintainer trees that would make my life
> > much easier.
>
> Applied now, I missed it earlier when I was on vacation.
Thanks. I think the next two patches (15 and 16) should also be
fine for the asm-generic tree for 5.4. For patch 17 I'd rather have
all arch patches in first.
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