* [PATCH] dt-bindings: rng: exynos4-rng: Convert Exynos PRNG bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 11:33 UTC (permalink / raw)
To: Matt Mackall, Herbert Xu, Rob Herring, Mark Rutland, Kukjin Kim,
Krzysztof Kozlowski, linux-crypto, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos Pseudo Random Number Generator bindings to DT
schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/rng/samsung,exynos4-rng.txt | 19 ---------
.../bindings/rng/samsung,exynos4-rng.yaml | 41 +++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 42 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt
create mode 100644 Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml
diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt
deleted file mode 100644
index a13fbdb4bd88..000000000000
--- a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Exynos Pseudo Random Number Generator
-
-Required properties:
-
-- compatible : One of:
- - "samsung,exynos4-rng" for Exynos4210 and Exynos4412
- - "samsung,exynos5250-prng" for Exynos5250+
-- reg : Specifies base physical address and size of the registers map.
-- clocks : Phandle to clock-controller plus clock-specifier pair.
-- clock-names : "secss" as a clock name.
-
-Example:
-
- rng@10830400 {
- compatible = "samsung,exynos4-rng";
- reg = <0x10830400 0x200>;
- clocks = <&clock CLK_SSS>;
- clock-names = "secss";
- };
diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml
new file mode 100644
index 000000000000..994b0ba10d2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/samsung,exynos4-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Pseudo Random Number Generator
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos4-rng # for Exynos4210 and Exynos4412
+ - samsung,exynos5250-prng # for Exynos5250+
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: secss
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+
+examples:
+ - |
+ rng@10830400 {
+ compatible = "samsung,exynos4-rng";
+ reg = <0x10830400 0x200>;
+ clocks = <&clock 255>; // CLK_SSS
+ clock-names = "secss";
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 331c40ae6a01..cdd2f1f3e1f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14181,7 +14181,7 @@ L: linux-crypto@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Maintained
F: drivers/crypto/exynos-rng.c
-F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.txt
+F: Documentation/devicetree/bindings/rng/samsung,exynos4-rng.yaml
SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER
M: Łukasz Stelmach <l.stelmach@samsung.com>
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH] regulator: vexpress: Use PTR_ERR_OR_ZERO() in vexpress_regulator_probe()
From: Markus Elfring @ 2019-09-07 11:23 UTC (permalink / raw)
To: linux-arm-kernel, Liam Girdwood, Liviu Dudau, Lorenzo Pieralisi,
Mark Brown, Sudeep Holla
Cc: kernel-janitors, LKML
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Sat, 7 Sep 2019 13:07:22 +0200
Simplify this function implementation by using a known function.
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/regulator/vexpress-regulator.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/regulator/vexpress-regulator.c b/drivers/regulator/vexpress-regulator.c
index 1235f46e633e..5d39663efcaa 100644
--- a/drivers/regulator/vexpress-regulator.c
+++ b/drivers/regulator/vexpress-regulator.c
@@ -75,10 +75,7 @@ static int vexpress_regulator_probe(struct platform_device *pdev)
config.of_node = pdev->dev.of_node;
rdev = devm_regulator_register(&pdev->dev, desc, &config);
- if (IS_ERR(rdev))
- return PTR_ERR(rdev);
-
- return 0;
+ return PTR_ERR_OR_ZERO(rdev);
}
static const struct of_device_id vexpress_regulator_of_match[] = {
--
2.23.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Status of led-backlight driver
From: Pavel Machek @ 2019-09-07 10:07 UTC (permalink / raw)
To: kernel list, linux-arm-kernel, linux-omap, tony, sre, nekit1000,
mpartap, merlijn, tomi.valkeinen, jjhiblot
[-- Attachment #1.1: Type: text/plain, Size: 319 bytes --]
Hi!
I don't see the LED-backlight driver in -next. Could it be pushed? It
is one of last pieces to get working backlight on Motorola Droid 4...
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #1.2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [Xen-devel] [PATCH] ARM: xen: unexport HYPERVISOR_platform_op function
From: Julien Grall @ 2019-09-07 10:05 UTC (permalink / raw)
To: Andrew Cooper, Arnd Bergmann
Cc: Stefano Stabellini, Emil Velikov, Russell King, Denis Efremov,
linux-kernel@vger.kernel.org, Masahiro Yamada, xen-devel,
Linux ARM
In-Reply-To: <bda2a05b-e2d0-feee-761b-88deeeac2449@citrix.com>
Hi Andrew,
On 9/6/19 6:20 PM, Andrew Cooper wrote:
> On 06/09/2019 17:00, Arnd Bergmann wrote:
>> On Fri, Sep 6, 2019 at 5:55 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
>>> On 06/09/2019 16:39, Arnd Bergmann wrote:
>>>> HYPERVISOR_platform_op() is an inline function and should not
>>>> be exported. Since commit 15bfc2348d54 ("modpost: check for
>>>> static EXPORT_SYMBOL* functions"), this causes a warning:
>>>>
>>>> WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static EXPORT_SYMBOL_GPL
>>>>
>>>> Remove the extraneous export.
>>>>
>>>> Fixes: 15bfc2348d54 ("modpost: check for static EXPORT_SYMBOL* functions")
>>>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>>> Something is wonky. That symbol is (/ really ought to be) in the
>>> hypercall page and most definitely not inline.
>>>
>>> Which tree is that changeset from? I can't find the SHA.
>> This is from linux-next, I think from the kbuild tree.
>
> Thanks.
>
> Julien/Stefano: Why are any of these hypercalls out-of-line? ARM
> doesn't use the hypercall page, and there is no argument translation
> (not even in arm32 as there are no 5-argument hypercalls declared).
I am not sure how the hypercall page makes things different. You still
have to store the arguments in the correct register so...
>
> They'd surely be easier to implement with a few static inlines and some
> common code, than to try and replicate the x86 side hypercall_page
> interface ?
... I don't think they will be easier to implement with a few static
inlines. The implementation will likely end up to be similar to
arch/x86/asm/xen/hypercall.h.
Furthermore, one of the downside of per-arch static inline is it is more
difficult to ensure the prototype match for all the architectures.
Although, it might be possible to make them common by only requesting
per-arch to implement HYPERCALL_N(...).
So I think the code is better as it is.
While looking at the code, I also realized that the implementation of
HYPERCALL_dm_op might be incorrect for Arm32. Similarly do privcmd call,
I think dm_op call should enable user access as they will be used by
userspace.
We don't use dm_op on Arm so far, hence why I think this was unnoticed.
I will see if I can reproduce it and send a patch.
Cheers,
--
Julien Grall
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^ permalink raw reply
* [V4, 2/2] media: i2c: Add Omnivision OV02A10 camera sensor driver
From: dongchun.zhu @ 2019-09-07 9:27 UTC (permalink / raw)
To: mchehab, andriy.shevchenko, robh+dt, mark.rutland, sakari.ailus,
drinkcat, tfiga, matthias.bgg, bingbu.cao
Cc: devicetree, srv_heupstream, shengnan.wang, sj.huang,
linux-mediatek, dongchun.zhu, louis.kuo, linux-arm-kernel,
linux-media
In-Reply-To: <20190907092728.23897-1-dongchun.zhu@mediatek.com>
From: Dongchun Zhu <dongchun.zhu@mediatek.com>
This patch adds a V4L2 sub-device driver for OV02A10 image sensor.
The OV02A10 is a 1/5" CMOS sensor from Omnivision,
supporting output format: 10-bit Raw.
The OV02A10 has a single MIPI lane interface and use the I2C bus
for control and the CSI-2 bus for data.
Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
---
MAINTAINERS | 1 +
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov02a10.c | 1062 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 1075 insertions(+)
create mode 100644 drivers/media/i2c/ov02a10.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 41734fb..4b714a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11821,6 +11821,7 @@ M: Dongchun Zhu <dongchun.zhu@mediatek.com>
L: linux-media@vger.kernel.org
T: git git://linuxtv.org/media_tree.git
S: Maintained
+F: drivers/media/i2c/ov02a10.c
F: Documentation/devicetree/bindings/media/i2c/ov02a10.txt
OMNIVISION OV2680 SENSOR DRIVER
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 79ce9ec..22e0db4 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -617,6 +617,17 @@ config VIDEO_IMX355
To compile this driver as a module, choose M here: the
module will be called imx355.
+config VIDEO_OV02A10
+ tristate "OmniVision OV02A10 sensor support"
+ depends on VIDEO_V4L2 && I2C
+ depends on MEDIA_CAMERA_SUPPORT
+ help
+ This is a Video4Linux2 sensor driver for the OmniVision
+ OV02A10 camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ov02a10.
+
config VIDEO_OV2640
tristate "OmniVision OV2640 sensor support"
depends on VIDEO_V4L2 && I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index fd4ea86..d27f4e2 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o
obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
+obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o
obj-$(CONFIG_VIDEO_OV2640) += ov2640.o
obj-$(CONFIG_VIDEO_OV2680) += ov2680.o
obj-$(CONFIG_VIDEO_OV2685) += ov2685.o
diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c
new file mode 100644
index 0000000..fb677d5
--- /dev/null
+++ b/drivers/media/i2c/ov02a10.c
@@ -0,0 +1,1062 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-fwnode.h>
+
+#define CHIP_ID 0x2509
+#define OV02A10_REG_CHIP_ID_H 0x02
+#define OV02A10_REG_CHIP_ID_L 0x03
+#define OV02A10_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
+
+/* Bit[1] vertical upside down */
+/* Bit[0] horizontal mirror */
+#define REG_MIRROR_FLIP_CONTROL 0x3f
+
+/* Orientation */
+#define REG_MIRROR_FLIP_ENABLE 0x03
+
+#define REG_PAGE_SWITCH 0xfd
+#define REG_GLOBAL_EFFECTIVE 0x01
+#define REG_ENABLE BIT(0)
+#define OV02A10_MASK_8_BITS 0xff
+
+#define REG_SC_CTRL_MODE 0xac
+#define SC_CTRL_MODE_STANDBY 0x00
+#define SC_CTRL_MODE_STREAMING 0x01
+
+#define OV02A10_EXP_SHIFT 8
+#define OV02A10_REG_EXPOSURE_H 0x03
+#define OV02A10_REG_EXPOSURE_L 0x04
+#define OV02A10_EXPOSURE_MIN 4
+#define OV02A10_EXPOSURE_MAX_MARGIN 4
+#define OV02A10_EXPOSURE_STEP 1
+
+#define OV02A10_VTS_SHIFT 8
+#define OV02A10_REG_VTS_H 0x05
+#define OV02A10_REG_VTS_L 0x06
+#define OV02A10_VTS_MAX 0x209f
+#define OV02A10_VTS_MIN 0x04cf
+#define OV02A10_BASIC_LINE 1224
+
+#define OV02A10_REG_GAIN 0x24
+#define OV02A10_GAIN_MIN 0x10
+#define OV02A10_GAIN_MAX 0xf8
+#define OV02A10_GAIN_STEP 0x01
+#define OV02A10_GAIN_DEFAULT 0x40
+
+/* Test pattern control */
+#define OV02A10_REG_TEST_PATTERN 0xb6
+#define OV02A10_TEST_PATTERN_ENABLE BIT(0)
+
+#define OV02A10_LINK_FREQ_390MHZ 390000000ULL
+#define OV02A10_ECLK_FREQ 24000000
+#define OV02A10_DATA_LANES 1
+#define OV02A10_BITS_PER_SAMPLE 10
+
+static const char * const ov02a10_supply_names[] = {
+ "dovdd", /* Digital I/O power */
+ "avdd", /* Analog power */
+ "dvdd", /* Digital core power */
+};
+
+#define OV02A10_NUM_SUPPLIES ARRAY_SIZE(ov02a10_supply_names)
+
+struct ov02a10_reg {
+ u8 addr;
+ u8 val;
+};
+
+struct ov02a10_reg_list {
+ u32 num_of_regs;
+ const struct ov02a10_reg *regs;
+};
+
+struct ov02a10_mode {
+ u32 width;
+ u32 height;
+ u32 exp_def;
+ u32 hts_def;
+ u32 vts_def;
+ const struct ov02a10_reg_list reg_list;
+};
+
+struct ov02a10 {
+ struct clk *eclk;
+ u32 eclk_freq;
+
+ struct gpio_desc *pd_gpio;
+ struct gpio_desc *n_rst_gpio;
+ struct regulator_bulk_data supplies[OV02A10_NUM_SUPPLIES];
+
+ bool streaming;
+ bool upside_down;
+
+ /*
+ * Serialize control access, get/set format, get selection
+ * and start streaming.
+ */
+ struct mutex mutex;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct v4l2_ctrl *anal_gain;
+ struct v4l2_ctrl *exposure;
+ struct v4l2_ctrl *hblank;
+ struct v4l2_ctrl *vblank;
+ struct v4l2_ctrl *hflip;
+ struct v4l2_ctrl *vflip;
+ struct v4l2_ctrl *test_pattern;
+ struct v4l2_mbus_framefmt fmt;
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ const struct ov02a10_mode *cur_mode;
+};
+
+static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct ov02a10, subdev);
+}
+
+/*
+ * eclk 24Mhz
+ * pclk 39Mhz
+ * linelength 934(0x3a6)
+ * framelength 1390(0x56E)
+ * grabwindow_width 1600
+ * grabwindow_height 1200
+ * max_framerate 30fps
+ * mipi_datarate per lane 780Mbps
+ */
+static const struct ov02a10_reg ov02a10_1600x1200_regs[] = {
+ {0xfd, 0x01},
+ {0xac, 0x00},
+ {0xfd, 0x00},
+ {0x2f, 0x29},
+ {0x34, 0x00},
+ {0x35, 0x21},
+ {0x30, 0x15},
+ {0x33, 0x01},
+ {0xfd, 0x01},
+ {0x44, 0x00},
+ {0x2a, 0x4c},
+ {0x2b, 0x1e},
+ {0x2c, 0x60},
+ {0x25, 0x11},
+ {0x03, 0x01},
+ {0x04, 0xae},
+ {0x09, 0x00},
+ {0x0a, 0x02},
+ {0x06, 0xa6},
+ {0x31, 0x00},
+ {0x24, 0x40},
+ {0x01, 0x01},
+ {0xfb, 0x73},
+ {0xfd, 0x01},
+ {0x16, 0x04},
+ {0x1c, 0x09},
+ {0x21, 0x42},
+ {0x12, 0x04},
+ {0x13, 0x10},
+ {0x11, 0x40},
+ {0x33, 0x81},
+ {0xd0, 0x00},
+ {0xd1, 0x01},
+ {0xd2, 0x00},
+ {0x50, 0x10},
+ {0x51, 0x23},
+ {0x52, 0x20},
+ {0x53, 0x10},
+ {0x54, 0x02},
+ {0x55, 0x20},
+ {0x56, 0x02},
+ {0x58, 0x48},
+ {0x5d, 0x15},
+ {0x5e, 0x05},
+ {0x66, 0x66},
+ {0x68, 0x68},
+ {0x6b, 0x00},
+ {0x6c, 0x00},
+ {0x6f, 0x40},
+ {0x70, 0x40},
+ {0x71, 0x0a},
+ {0x72, 0xf0},
+ {0x73, 0x10},
+ {0x75, 0x80},
+ {0x76, 0x10},
+ {0x84, 0x00},
+ {0x85, 0x10},
+ {0x86, 0x10},
+ {0x87, 0x00},
+ {0x8a, 0x22},
+ {0x8b, 0x22},
+ {0x19, 0xf1},
+ {0x29, 0x01},
+ {0xfd, 0x01},
+ {0x9d, 0xd6},
+ {0xa0, 0x29},
+ {0xa1, 0x03},
+ {0xad, 0x62},
+ {0xae, 0x00},
+ {0xaf, 0x85},
+ {0xb1, 0x01},
+ {0x8e, 0x06},
+ {0x8f, 0x40},
+ {0x90, 0x04},
+ {0x91, 0xb0},
+ {0x45, 0x01},
+ {0x46, 0x00},
+ {0x47, 0x6c},
+ {0x48, 0x03},
+ {0x49, 0x8b},
+ {0x4a, 0x00},
+ {0x4b, 0x07},
+ {0x4c, 0x04},
+ {0x4d, 0xb7},
+ {0xf0, 0x40},
+ {0xf1, 0x40},
+ {0xf2, 0x40},
+ {0xf3, 0x40},
+ {0x3f, 0x00},
+ {0xfd, 0x01},
+ {0x05, 0x00},
+ {0x06, 0xa6},
+ {0xfd, 0x01},
+};
+
+static const char * const ov02a10_test_pattern_menu[] = {
+ "Disabled",
+ "Color Bar",
+};
+
+static const s64 link_freq_menu_items[] = {
+ OV02A10_LINK_FREQ_390MHZ
+};
+
+static u64 to_pixel_rate(u32 f_index)
+{
+ u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES;
+
+ do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE);
+
+ return pixel_rate;
+}
+
+static const struct ov02a10_mode supported_modes[] = {
+ {
+ .width = 1600,
+ .height = 1200,
+ .exp_def = 0x01ae,
+ .hts_def = 0x03a6,
+ .vts_def = 0x056e,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs),
+ .regs = ov02a10_1600x1200_regs,
+ },
+ },
+};
+
+static int ov02a10_write_array(struct ov02a10 *ov02a10,
+ const struct ov02a10_reg_list *r_list)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < r_list->num_of_regs; i++) {
+ ret = i2c_smbus_write_byte_data(client,
+ r_list->regs[i].addr,
+ r_list->regs[i].val);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ov02a10_read_smbus(struct ov02a10 *ov02a10, unsigned char reg,
+ unsigned char *val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_read_byte_data(client, reg);
+ if (ret >= 0) {
+ *val = (unsigned char)ret;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+static void ov02a10_fill_fmt(const struct ov02a10_mode *mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = mode->width;
+ fmt->height = mode->height;
+ fmt->field = V4L2_FIELD_NONE;
+}
+
+static int ov02a10_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming) {
+ mutex_unlock(&ov02a10->mutex);
+ return -EBUSY;
+ }
+
+ /* Only one sensor mode supported */
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+ ov02a10->fmt = fmt->format;
+
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+}
+
+static int ov02a10_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+
+ mutex_lock(&ov02a10->mutex);
+
+ fmt->format = ov02a10->fmt;
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+}
+
+static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ if (code->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ code->code = ov02a10->fmt.code;
+
+ return 0;
+}
+
+static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ fse->min_width = supported_modes[fse->index].width;
+ fse->max_width = supported_modes[fse->index].width;
+ fse->max_height = supported_modes[fse->index].height;
+ fse->min_height = supported_modes[fse->index].height;
+
+ return 0;
+}
+
+static int __ov02a10_power_on(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ struct device *dev = &client->dev;
+ int ret;
+
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, GPIOD_OUT_LOW);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, GPIOD_OUT_HIGH);
+
+ ret = clk_prepare_enable(ov02a10->eclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable eclk\n");
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(OV02A10_NUM_SUPPLIES, ov02a10->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable regulators\n");
+ goto disable_clk;
+ }
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, GPIOD_OUT_LOW);
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, GPIOD_OUT_HIGH);
+ usleep_range(5000, 6000);
+
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(ov02a10->eclk);
+
+ return ret;
+}
+
+static void __ov02a10_power_off(struct ov02a10 *ov02a10)
+{
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 1);
+ clk_disable_unprepare(ov02a10->eclk);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
+ regulator_bulk_disable(OV02A10_NUM_SUPPLIES, ov02a10->supplies);
+}
+
+static int __ov02a10_start_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_reg_list *reg_list;
+ int ret;
+
+ /* Apply default values of current mode */
+ reg_list = &ov02a10->cur_mode->reg_list;
+ ret = ov02a10_write_array(ov02a10, reg_list);
+ if (ret)
+ return ret;
+
+ /* Apply customized values from user */
+ ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler);
+ if (ret)
+ return ret;
+
+ /* Set orientation to 180 degree */
+ if (ov02a10->upside_down) {
+ ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL,
+ REG_MIRROR_FLIP_ENABLE);
+ if (ret) {
+ dev_err(&client->dev, "failed to set orientation\n");
+ return ret;
+ }
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Set stream on register */
+ return i2c_smbus_write_byte_data(client,
+ REG_SC_CTRL_MODE, SC_CTRL_MODE_STREAMING);
+}
+
+static int __ov02a10_stop_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+
+ return i2c_smbus_write_byte_data(client,
+ REG_SC_CTRL_MODE, SC_CTRL_MODE_STANDBY);
+}
+
+static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_subdev_format fmt = { 0 };
+
+ fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
+ fmt.format.width = ov02a10->cur_mode->width;
+ fmt.format.height = ov02a10->cur_mode->width;
+
+ ov02a10_set_fmt(sd, cfg, &fmt);
+
+ return 0;
+}
+
+static int ov02a10_s_stream(struct v4l2_subdev *sd, int on)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret = 0;
+
+ dev_dbg(&client->dev, "ov02a10 s_stream (%d)\n", on);
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming == on)
+ goto unlock_and_return;
+
+ if (on) {
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ goto unlock_and_return;
+ }
+
+ ret = __ov02a10_start_stream(ov02a10);
+ if (ret) {
+ __ov02a10_stop_stream(ov02a10);
+ ov02a10->streaming = !on;
+ goto err_rpm_put;
+ }
+ } else {
+ __ov02a10_stop_stream(ov02a10);
+ pm_runtime_put(&client->dev);
+ }
+
+ ov02a10->streaming = on;
+ mutex_unlock(&ov02a10->mutex);
+
+ return ret;
+
+err_rpm_put:
+ pm_runtime_put(&client->dev);
+unlock_and_return:
+ mutex_unlock(&ov02a10->mutex);
+
+ return ret;
+}
+
+static int __maybe_unused ov02a10_runtime_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ return __ov02a10_power_on(ov02a10);
+}
+
+static int __maybe_unused ov02a10_runtime_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ __ov02a10_power_off(ov02a10);
+
+ return 0;
+}
+
+static const struct dev_pm_ops ov02a10_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(ov02a10_runtime_suspend,
+ ov02a10_runtime_resume, NULL)
+};
+
+/*
+ * ov02a10_set_exposure - Function called when setting exposure time
+ * @priv: Pointer to device structure
+ * @val: Variable for exposure time, in the unit of micro-second
+ *
+ * Set exposure time based on input value.
+ *
+ * Return: 0 on success
+ */
+static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H,
+ ((val >> OV02A10_EXP_SHIFT) &
+ OV02A10_MASK_8_BITS));
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L,
+ (val & OV02A10_MASK_8_BITS));
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN,
+ (val & OV02A10_MASK_8_BITS));
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H,
+ (((val + ov02a10->cur_mode->height -
+ OV02A10_BASIC_LINE) >>
+ OV02A10_VTS_SHIFT) &
+ OV02A10_MASK_8_BITS));
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L,
+ ((val + ov02a10->cur_mode->height -
+ OV02A10_BASIC_LINE) &
+ OV02A10_MASK_8_BITS));
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ if (pattern)
+ pattern = OV02A10_TEST_PATTERN_ENABLE;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN,
+ pattern);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STREAMING);
+}
+
+static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov02a10 *ov02a10 = container_of(ctrl->handler,
+ struct ov02a10, ctrl_handler);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ s64 max_expo;
+ int ret;
+
+ /* Propagate change of current control to all related controls */
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Update max exposure while meeting expected vblanking */
+ max_expo = ov02a10->cur_mode->height + ctrl->val -
+ OV02A10_EXPOSURE_MAX_MARGIN;
+ __v4l2_ctrl_modify_range(ov02a10->exposure,
+ ov02a10->exposure->minimum, max_expo,
+ ov02a10->exposure->step,
+ ov02a10->exposure->default_value);
+ }
+
+ /* V4L2 controls values will be applied only when power is already up */
+ if (!pm_runtime_get_if_in_use(&client->dev))
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ ret = ov02a10_set_exposure(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = ov02a10_set_gain(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_VBLANK:
+ ret = ov02a10_set_vblank(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_TEST_PATTERN:
+ ret = ov02a10_set_test_pattern(ov02a10, ctrl->val);
+ break;
+ };
+
+ pm_runtime_put(&client->dev);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_video_ops ov02a10_video_ops = {
+ .s_stream = ov02a10_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = {
+ .init_cfg = ov02a10_entity_init_cfg,
+ .enum_mbus_code = ov02a10_enum_mbus_code,
+ .enum_frame_size = ov02a10_enum_frame_sizes,
+ .get_fmt = ov02a10_get_fmt,
+ .set_fmt = ov02a10_set_fmt,
+};
+
+static const struct v4l2_subdev_ops ov02a10_subdev_ops = {
+ .video = &ov02a10_video_ops,
+ .pad = &ov02a10_pad_ops,
+};
+
+static const struct media_entity_operations ov02a10_subdev_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = {
+ .s_ctrl = ov02a10_set_ctrl,
+};
+
+static int ov02a10_initialize_controls(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_mode *mode;
+ struct v4l2_ctrl_handler *handler;
+ struct v4l2_ctrl *ctrl;
+ u64 exposure_max;
+ u32 pixel_rate, h_blank;
+ int ret;
+
+ handler = &ov02a10->ctrl_handler;
+ mode = ov02a10->cur_mode;
+ ret = v4l2_ctrl_handler_init(handler, 7);
+ if (ret)
+ return ret;
+
+ handler->lock = &ov02a10->mutex;
+
+ ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
+ 0, 0, link_freq_menu_items);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ pixel_rate = to_pixel_rate(0);
+ v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
+ 0, pixel_rate, 1, pixel_rate);
+
+ h_blank = mode->hts_def - mode->width;
+ ov02a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
+ h_blank, h_blank, 1, h_blank);
+ if (ov02a10->hblank)
+ ov02a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ ov02a10->vblank = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_VBLANK, mode->vts_def -
+ mode->height,
+ OV02A10_VTS_MAX - mode->height, 1,
+ mode->vts_def - mode->height);
+
+ exposure_max = mode->vts_def - 4;
+ ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ OV02A10_EXPOSURE_MIN,
+ exposure_max,
+ OV02A10_EXPOSURE_STEP,
+ mode->exp_def);
+
+ ov02a10->anal_gain = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN,
+ OV02A10_GAIN_MIN,
+ OV02A10_GAIN_MAX,
+ OV02A10_GAIN_STEP,
+ OV02A10_GAIN_DEFAULT);
+
+ ov02a10->test_pattern =
+ v4l2_ctrl_new_std_menu_items(handler,
+ &ov02a10_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ov02a10_test_pattern_menu) -
+ 1, 0, 0,
+ ov02a10_test_pattern_menu);
+
+ if (handler->error) {
+ ret = handler->error;
+ dev_err(&client->dev, "failed to init controls(%d)\n", ret);
+ goto err_free_handler;
+ }
+
+ ov02a10->subdev.ctrl_handler = handler;
+
+ return 0;
+
+err_free_handler:
+ v4l2_ctrl_handler_free(handler);
+
+ return ret;
+}
+
+static int ov02a10_check_hwcfg(struct device *dev)
+{
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
+ unsigned int i, j;
+ int ret;
+
+ if (!fwnode)
+ return -ENXIO;
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return -ENXIO;
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return ret;
+
+ if (!bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequencies defined");
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
+ for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
+ if (link_freq_menu_items[i] ==
+ bus_cfg.link_frequencies[j])
+ break;
+ }
+
+ if (j == bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequency %lld supported",
+ link_freq_menu_items[i]);
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+ }
+
+check_hwcfg_error:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+}
+
+static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ u16 id;
+ u8 pid = 0;
+ u8 ver = 0;
+ int ret;
+
+ /* Check sensor revision */
+ ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_H, &pid);
+ if (ret)
+ return ret;
+
+ ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_L, &ver);
+ if (ret)
+ return ret;
+
+ id = OV02A10_ID(pid, ver);
+ if (id != CHIP_ID) {
+ dev_err(&client->dev, "Unexpected sensor id(%04x)\n", id);
+ return ret;
+ }
+
+ dev_info(&client->dev, "Detected OV%04X sensor\n", id);
+
+ return 0;
+}
+
+static int ov02a10_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct ov02a10 *ov02a10;
+ unsigned int rotation;
+ unsigned int i;
+ int ret;
+
+ dev_info(dev, "ov02a10 probe aaaa++\n");
+
+ ret = ov02a10_check_hwcfg(dev);
+ if (ret) {
+ dev_err(dev, "failed to check HW configuration: %d",
+ ret);
+ return ret;
+ }
+
+ ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL);
+ if (!ov02a10)
+ return -ENOMEM;
+
+ v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops);
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10;
+
+ /* Optional indication of physical rotation of sensor */
+ ret = fwnode_property_read_u32(dev_fwnode(dev), "rotation",
+ &rotation);
+ if (!ret) {
+ switch (rotation) {
+ case 180:
+ ov02a10->upside_down = true;
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10;
+ break;
+ case 0:
+ break;
+ default:
+ dev_warn(dev, "%u degrees rotation is not supported, ignoring...\n",
+ rotation);
+ }
+ }
+
+ /* Get system clock (eclk) */
+ ov02a10->eclk = devm_clk_get(dev, "eclk");
+ if (IS_ERR(ov02a10->eclk)) {
+ dev_err(dev, "failed to get eclk\n");
+ return -EINVAL;
+ }
+
+ ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
+ &ov02a10->eclk_freq);
+ if (ret) {
+ dev_err(dev, "failed to get eclk frequency\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq);
+ if (ret) {
+ dev_err(dev, "failed to set eclk frequency (24MHz)\n");
+ return ret;
+ }
+
+ if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ) {
+ dev_warn(dev, "wrong eclk frequency %d Hz, expected: %d Hz\n",
+ ov02a10->eclk_freq, OV02A10_ECLK_FREQ);
+ return -EINVAL;
+ }
+
+ ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH);
+ if (IS_ERR(ov02a10->pd_gpio)) {
+ dev_err(dev, "failed to get powerdown-gpios\n");
+ return -EINVAL;
+ }
+
+ ov02a10->n_rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(ov02a10->n_rst_gpio)) {
+ dev_err(dev, "failed to get reset-gpios\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < OV02A10_NUM_SUPPLIES; i++)
+ ov02a10->supplies[i].supply = ov02a10_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev,
+ OV02A10_NUM_SUPPLIES,
+ ov02a10->supplies);
+ if (ret) {
+ dev_err(dev, "failed to get regulators\n");
+ return ret;
+ }
+
+ mutex_init(&ov02a10->mutex);
+ ov02a10->cur_mode = &supported_modes[0];
+ ret = ov02a10_initialize_controls(ov02a10);
+ if (ret) {
+ dev_err(dev, "failed to initialize controls\n");
+ goto err_destroy_mutex;
+ }
+
+ ret = __ov02a10_power_on(ov02a10);
+ if (ret)
+ goto err_free_handler;
+
+ ret = ov02a10_check_sensor_id(ov02a10);
+ if (ret)
+ goto err_power_off;
+
+ ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops;
+ ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad);
+ if (ret < 0) {
+ dev_err(dev, "failed to init entity pads: %d", ret);
+ goto err_power_off;
+ }
+
+ ret = v4l2_async_register_subdev(&ov02a10->subdev);
+ if (ret) {
+ dev_err(dev, "failed to register V4L2 subdev: %d",
+ ret);
+ goto err_clean_entity;
+ }
+
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ pm_runtime_idle(dev);
+
+ dev_info(dev, "ov02a10 probe --\n");
+ return 0;
+
+err_clean_entity:
+ media_entity_cleanup(&ov02a10->subdev.entity);
+err_power_off:
+ __ov02a10_power_off(ov02a10);
+err_free_handler:
+ v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler);
+err_destroy_mutex:
+ mutex_destroy(&ov02a10->mutex);
+
+ return ret;
+}
+
+static int ov02a10_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(sd->ctrl_handler);
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ __ov02a10_power_off(ov02a10);
+ pm_runtime_set_suspended(&client->dev);
+ mutex_destroy(&ov02a10->mutex);
+
+ return 0;
+}
+
+static const struct of_device_id ov02a10_of_match[] = {
+ { .compatible = "ovti,ov02a10" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ov02a10_of_match);
+
+static struct i2c_driver ov02a10_i2c_driver = {
+ .driver = {
+ .name = "ov02a10",
+ .pm = &ov02a10_pm_ops,
+ .of_match_table = ov02a10_of_match,
+ },
+ .probe_new = &ov02a10_probe,
+ .remove = &ov02a10_remove,
+};
+
+module_i2c_driver(ov02a10_i2c_driver);
+
+MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
+MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver");
+MODULE_LICENSE("GPL v2");
+
--
2.9.2
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^ permalink raw reply related
* [V4, 1/2] media: dt-bindings: media: i2c: Add bindings for OV02A10
From: dongchun.zhu @ 2019-09-07 9:27 UTC (permalink / raw)
To: mchehab, andriy.shevchenko, robh+dt, mark.rutland, sakari.ailus,
drinkcat, tfiga, matthias.bgg, bingbu.cao
Cc: devicetree, srv_heupstream, shengnan.wang, sj.huang,
linux-mediatek, dongchun.zhu, louis.kuo, linux-arm-kernel,
linux-media
In-Reply-To: <20190907092728.23897-1-dongchun.zhu@mediatek.com>
From: Dongchun Zhu <dongchun.zhu@mediatek.com>
This patch adds device tree bindings documentation for OV02A10 camera sensor.
Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
---
.../devicetree/bindings/media/i2c/ov02a10.txt | 54 ++++++++++++++++++++++
MAINTAINERS | 7 +++
2 files changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov02a10.txt
diff --git a/Documentation/devicetree/bindings/media/i2c/ov02a10.txt b/Documentation/devicetree/bindings/media/i2c/ov02a10.txt
new file mode 100644
index 0000000..18acc4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov02a10.txt
@@ -0,0 +1,54 @@
+* Omnivision OV02A10 MIPI CSI-2 sensor
+
+Required Properties:
+- compatible: shall be "ovti,ov02a10"
+- clocks: reference to the eclk input clock
+- clock-names: shall be "eclk"
+- dovdd-supply: Digital I/O voltage supply, 1.8 volts
+- avdd-supply: Analog voltage supply, 2.8 volts
+- dvdd-supply: Digital core voltage supply, 1.8 volts
+- powerdown-gpios: reference to the GPIO connected to the powerdown pin,
+ if any. This is an active low signal to the OV02A10.
+- reset-gpios: reference to the GPIO connected to the reset pin, if any.
+ This is an active high signal to the OV02A10.
+
+Optional Properties:
+- rotation: as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt,
+ valid values are 0 (sensor mounted upright) and 180 (sensor
+ mounted upside down).
+
+The device node shall contain one 'port' child node with an
+'endpoint' subnode for its digital output video port,
+in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+&i2c4 {
+ ov02a10: camera-sensor@3d {
+ compatible = "ovti,ov02a10";
+ reg = <0x3d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_pins_cam1_mclk_on>;
+
+ clocks = <&topckgen CLK_TOP_MUX_CAMTG2>,
+ <&topckgen CLK_TOP_UNIVP_192M_D8>;
+ clock-names = "eclk", "freq_mux";
+ clock-frequency = <24000000>;
+
+ dovdd-supply = <&mt6358_vcamio_reg>;
+ avdd-supply = <&mt6358_vcama1_reg>;
+ dvdd-supply = <&mt6358_vcn18_reg>;
+ powerdown-gpios = <&pio 107 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 109 GPIO_ACTIVE_HIGH>;
+ rotation = <180>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ ov02a10_core: endpoint {
+ remote-endpoint = <&ov02a10_0>;
+ link-frequencies = /bits/ 64 <390000000>;
+ };
+ };
+ };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e..41734fb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11816,6 +11816,13 @@ T: git git://linuxtv.org/media_tree.git
S: Maintained
F: drivers/media/i2c/ov13858.c
+OMNIVISION OV02A10 SENSOR DRIVER
+M: Dongchun Zhu <dongchun.zhu@mediatek.com>
+L: linux-media@vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: Documentation/devicetree/bindings/media/i2c/ov02a10.txt
+
OMNIVISION OV2680 SENSOR DRIVER
M: Rui Miguel Silva <rmfrfs@gmail.com>
L: linux-media@vger.kernel.org
--
2.9.2
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^ permalink raw reply related
* [V4, 0/2] media: i2c: Add support for OV02A10 sensor
From: dongchun.zhu @ 2019-09-07 9:27 UTC (permalink / raw)
To: mchehab, andriy.shevchenko, robh+dt, mark.rutland, sakari.ailus,
drinkcat, tfiga, matthias.bgg, bingbu.cao
Cc: devicetree, srv_heupstream, shengnan.wang, sj.huang,
linux-mediatek, dongchun.zhu, louis.kuo, linux-arm-kernel,
linux-media
From: Dongchun Zhu <dongchun.zhu@mediatek.com>
Hello,
This patch adds driver and bindings for Omnivision's OV02A10 2 megapixel CMOS 1/5" sensor,
which has a single MIPI lane interface and output format of 10-bit Raw.
The driver is implemented wth V4L2 framework.
1. Async registered as a V4L2 I2C sub-device.
2. A media entity that can provide several source pads and sink pads to link with other device like Seninf, ISP one after another
to create a default overall camera topology, image frame or meta-data from sensor can flow through particular path to output
preview or capture image or 3A info.
Changes of v4 mainly address the comments from Sakari, Rob, Tomasz.
- Remove data-lanes property in DT
- Add link frequencies in DT to match the expect value that driver requires
- Omit open callback as int_cfg is implemented
- Use i2c_smbus_write_byte_data/i2c_smbus_read_byte_data instead of customed APIs
- Use do_div to calculate pixel rate
- Use usleep_range directly for shoter sleep case
- Re-adjust sensor power up/off sequence
- Re-set pd/rst GPIO inverter property according to the datasheet
- Refine set_exposure/set_gain/set_vblanking/set_test_pattern functions
- Fix other reviewed issues in v3
Changes of v3 are mainly addressing comments from Rob, Sakari, Bingbu.
- Fix coding style errors in dt-bindings
- Use macro flag to describle basic line 1224 when updating v-blanking
- Remove unnecessary debug log in driver
Mainly changes of v2 are addressing the comments from Nicolas, Bingbu, Sakari, Rob,
including,
- Put dt binding before driver in series
- Add MAINTAINERS entries
- Squash the MAINTAINERS entry and Kconfig to driver patch
- Add rotation support for driver
- Fix other reviewed issues in v1
Dongchun Zhu (2):
media: dt-bindings: media: i2c: Add bindings for OV02A10
media: i2c: Add Omnivision OV02A10 camera sensor driver
.../devicetree/bindings/media/i2c/ov02a10.txt | 54 +
MAINTAINERS | 8 +
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov02a10.c | 1062 ++++++++++++++++++++
5 files changed, 1136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov02a10.txt
create mode 100644 drivers/media/i2c/ov02a10.c
--
2.9.2
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^ permalink raw reply
* Re: [RFC 5/9] dt-bindings: arm: samsung: Convert Exynos PMU bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:22 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, Alessandro Zummo, Alexandre Belloni,
Lars-Peter Clausen, Arnd Bergmann, devicetree,
open list:IIO SUBSYSTEM AND DRIVERS, Marek Szyprowski,
linux-kernel@vger.kernel.org, Tomasz Figa, linux-samsung-soc,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Peter Meerwald-Stadler, Hartmut Knaack, Olof Johansson,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM, notify,
Jonathan Cameron, Paweł Chmiel
In-Reply-To: <CAL_JsqKyj3s-Mn3q_Lna0w38K3DJzvKN5d72WHzqt4CUVf5X4Q@mail.gmail.com>
On Fri, 6 Sep 2019 at 17:49, Rob Herring <robh+dt@kernel.org> wrote:
> >
> > The bindings never required any specific ordering. Also the driver
> > just go through all indices and parses them.
> >
> > Your second syntax fails:
> > Documentation/devicetree/bindings/arm/samsung/pmu.yaml:
> > properties:clock-names:items: {'enum': ['clkout0', 'clkout1',
> > 'clkout2', 'clkout3', 'clkout4', 'clkout5', 'clkout6', 'clkout7',
> > 'clkout8', 'clkout9', 'clkout10', 'clkout11', 'clkout12', 'clkout13',
> > 'clkout14', 'clkout15', 'clkout16']} is not of type 'array'
>
> Update dt-schema and try again. It should be allowed now. You'll also
> need to define minItems and maxItems though.
Thanks, works!
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2 11/11] dt-bindings: iio: adc: exynos: Remove old requirement of two register address ranges
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Commit fafb37cfae6d ("iio: exyno-adc: use syscon for PMU
register access") changed the Exynos ADC driver so the PMU syscon
phandle is required instead of second register address space. The
bindings were not updated so fix them now.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. New patch.
---
.../bindings/iio/adc/samsung,exynos-adc.yaml | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
index dd58121f25b1..b4c6c26681d9 100644
--- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
@@ -25,8 +25,7 @@ properties:
- samsung,s5pv210-adc
reg:
- minItems: 1
- maxItems: 2
+ maxItems: 1
clocks:
description:
@@ -55,7 +54,7 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle'
description:
Phandle to the PMU system controller node (to access the ADC_PHY
- register on Exynos5250/5420/5800/3250).
+ register on Exynos3250/4x12/5250/5420/5800).
has-touchscreen:
description:
@@ -83,19 +82,8 @@ allOf:
- samsung,exynos4212-adc
- samsung,s5pv210-adc
then:
- properties:
- reg:
- items:
- # For S5P and Exynos
- - description: base registers
- - description: phy registers
required:
- samsung,syscon-phandle
- else:
- properties:
- reg:
- items:
- - description: base registers
- if:
properties:
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 10/11] dt-bindings: iio: adc: exynos: Convert Exynos ADC bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung Exynos Analog to Digital Converter bindings to DT schema
format using json-schema.
This is a direct conversion of existing bindings so it also copies the
existing error in the bindings regarding the requirement of two register
address ranges for certain compatibles. The inconsistency in binding
was caused by commit fafb37cfae6d ("iio: exyno-adc: use syscon for PMU
register access").
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Rework reg, clocks and clock-names matching for specific compatibles,
2. Make samsung,syscon-phandle required only on certain compatibles,
3. Fix indentation.
---
.../bindings/iio/adc/samsung,exynos-adc.txt | 107 ------------
.../bindings/iio/adc/samsung,exynos-adc.yaml | 163 ++++++++++++++++++
2 files changed, 163 insertions(+), 107 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt
deleted file mode 100644
index e1fe02f3e3e9..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Samsung Exynos Analog to Digital Converter bindings
-
-The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
-
-New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
- and future SoCs from Samsung
-2. Add ADC driver under iio/adc framework
-3. Also adds the Documentation for device tree bindings
-
-Required properties:
-- compatible: Must be "samsung,exynos-adc-v1"
- for Exynos5250 controllers.
- Must be "samsung,exynos-adc-v2" for
- future controllers.
- Must be "samsung,exynos3250-adc" for
- controllers compatible with ADC of Exynos3250.
- Must be "samsung,exynos4212-adc" for
- controllers compatible with ADC of Exynos4212 and Exynos4412.
- Must be "samsung,exynos7-adc" for
- the ADC in Exynos7 and compatibles
- Must be "samsung,s3c2410-adc" for
- the ADC in s3c2410 and compatibles
- Must be "samsung,s3c2416-adc" for
- the ADC in s3c2416 and compatibles
- Must be "samsung,s3c2440-adc" for
- the ADC in s3c2440 and compatibles
- Must be "samsung,s3c2443-adc" for
- the ADC in s3c2443 and compatibles
- Must be "samsung,s3c6410-adc" for
- the ADC in s3c6410 and compatibles
- Must be "samsung,s5pv210-adc" for
- the ADC in s5pv210 and compatibles
-- reg: List of ADC register address range
- - The base address and range of ADC register
- - The base address and range of ADC_PHY register (every
- SoC except for s3c24xx/s3c64xx ADC)
-- interrupts: Contains the interrupt information for the timer. The
- format is being dependent on which interrupt controller
- the Samsung device uses.
-- #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks From common clock bindings: handles to clocks specified
- in "clock-names" property, in the same order.
-- clock-names From common clock bindings: list of clock input names
- used by ADC block:
- - "adc" : ADC bus clock
- - "sclk" : ADC special clock (only for Exynos3250 and
- compatible ADC block)
-- vdd-supply VDD input supply.
-
-- samsung,syscon-phandle Contains the PMU system controller node
- (To access the ADC_PHY register on Exynos5250/5420/5800/3250)
-Optional properties:
-- has-touchscreen: If present, indicates that a touchscreen is
- connected an usable.
-
-Note: child nodes can be added for auto probing from device tree.
-
-Example: adding device info in dtsi file
-
-adc: adc@12d10000 {
- compatible = "samsung,exynos-adc-v1";
- reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
- #io-channel-cells = <1>;
- io-channel-ranges;
-
- clocks = <&clock 303>;
- clock-names = "adc";
-
- vdd-supply = <&buck5_reg>;
- samsung,syscon-phandle = <&pmu_system_controller>;
-};
-
-Example: adding device info in dtsi file for Exynos3250 with additional sclk
-
-adc: adc@126c0000 {
- compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
- reg = <0x126C0000 0x100>;
- interrupts = <0 137 0>;
- #io-channel-cells = <1>;
- io-channel-ranges;
-
- clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
- clock-names = "adc", "sclk";
-
- vdd-supply = <&buck5_reg>;
- samsung,syscon-phandle = <&pmu_system_controller>;
-};
-
-Example: Adding child nodes in dts file
-
-adc@12d10000 {
-
- /* NTC thermistor is a hwmon device */
- ncp15wb473@0 {
- compatible = "murata,ncp15wb473";
- pullup-uv = <1800000>;
- pullup-ohm = <47000>;
- pulldown-ohm = <0>;
- io-channels = <&adc 4>;
- };
-};
-
-Note: Does not apply to ADC driver under arch/arm/plat-samsung/
-Note: The child node can be added under the adc node or separately.
diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
new file mode 100644
index 000000000000..dd58121f25b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Analog to Digital Converter (ADC)
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos-adc-v1 # Exynos5250
+ - samsung,exynos-adc-v2
+ - samsung,exynos3250-adc
+ - samsung,exynos4212-adc # Exynos4212 and Exynos4412
+ - samsung,exynos7-adc
+ - samsung,s3c2410-adc
+ - samsung,s3c2416-adc
+ - samsung,s3c2440-adc
+ - samsung,s3c2443-adc
+ - samsung,s3c6410-adc
+ - samsung,s5pv210-adc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ description:
+ Phandle to ADC bus clock. For Exynos3250 additional clock is needed.
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ description:
+ Must contain clock names (adc, sclk) matching phandles in clocks
+ property.
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+ vdd-supply:
+ description: VDD input supply
+ maxItems: 1
+
+ samsung,syscon-phandle:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ Phandle to the PMU system controller node (to access the ADC_PHY
+ register on Exynos5250/5420/5800/3250).
+
+ has-touchscreen:
+ description:
+ If present, indicates that a touchscreen is connected and usable.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - "#io-channel-cells"
+ - vdd-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos-adc-v1
+ - samsung,exynos-adc-v2
+ - samsung,exynos3250-adc
+ - samsung,exynos4212-adc
+ - samsung,s5pv210-adc
+ then:
+ properties:
+ reg:
+ items:
+ # For S5P and Exynos
+ - description: base registers
+ - description: phy registers
+ required:
+ - samsung,syscon-phandle
+ else:
+ properties:
+ reg:
+ items:
+ - description: base registers
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos3250-adc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: adc
+ - const: sclk
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: adc
+
+examples:
+ - |
+ adc: adc@12d10000 {
+ compatible = "samsung,exynos-adc-v1";
+ reg = <0x12d10000 0x100>;
+ interrupts = <0 106 0>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ clocks = <&clock 303>;
+ clock-names = "adc";
+
+ vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+
+ /* NTC thermistor is a hwmon device */
+ ncp15wb473@0 {
+ compatible = "murata,ncp15wb473";
+ pullup-uv = <1800000>;
+ pullup-ohm = <47000>;
+ pulldown-ohm = <0>;
+ io-channels = <&adc 4>;
+ };
+ };
+
+ - |
+ adc@126c0000 {
+ compatible = "samsung,exynos3250-adc";
+ reg = <0x126C0000 0x100>;
+ interrupts = <0 137 0>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ clocks = <&cmu 0>, // CLK_TSADC
+ <&cmu 1>; // CLK_SCLK_TSADC
+ clock-names = "adc", "sclk";
+
+ vdd-supply = <&buck5_reg>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 09/11] dt-bindings: rtc: s3c: Convert S3C/Exynos RTC bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung S3C/Exynos Real Time Clock bindings to DT schema format
using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Use deprecated property instead of custom select,
2. Rework clocks and clock-names matching for specific compatibles.
---
.../devicetree/bindings/rtc/s3c-rtc.txt | 31 -------
.../devicetree/bindings/rtc/s3c-rtc.yaml | 85 +++++++++++++++++++
2 files changed, 85 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/s3c-rtc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/s3c-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
deleted file mode 100644
index fdde63a5419c..000000000000
--- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Samsung's S3C Real Time Clock controller
-
-Required properties:
-- compatible: should be one of the following.
- * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
- * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc.
- * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc.
- * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
- * "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with
- exynos3250 rtc (use "samsung,s3c6410-rtc").
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: Two interrupt numbers to the cpu should be specified. First
- interrupt number is the rtc alarm interrupt and second interrupt number
- is the rtc tick interrupt. The number of cells representing a interrupt
- depends on the parent interrupt controller.
-- clocks: Must contain a list of phandle and clock specifier for the rtc
- clock and in the case of a s3c6410 compatible controller, also
- a source clock.
-- clock-names: Must contain "rtc" and for a s3c6410 compatible controller,
- a "rtc_src" sorted in the same order as the clocks property.
-
-Example:
-
- rtc@10070000 {
- compatible = "samsung,s3c6410-rtc";
- reg = <0x10070000 0x100>;
- interrupts = <44 0 45 0>;
- clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
- clock-names = "rtc", "rtc_src";
- };
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml
new file mode 100644
index 000000000000..951a6a485709
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C, S5P and Exynos Real Time Clock controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,s3c2410-rtc
+ - samsung,s3c2416-rtc
+ - samsung,s3c2443-rtc
+ - samsung,s3c6410-rtc
+ - const: samsung,exynos3250-rtc
+ deprecated: true
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ Must contain a list of phandle and clock specifier for the rtc
+ clock and in the case of a s3c6410 compatible controller, also
+ a source clock.
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ description:
+ Must contain "rtc" and for a s3c6410 compatible controller
+ also "rtc_src".
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ description:
+ Two interrupt numbers to the cpu should be specified. First
+ interrupt number is the rtc alarm interrupt and second interrupt number
+ is the rtc tick interrupt. The number of cells representing a interrupt
+ depends on the parent interrupt controller.
+ minItems: 2
+ maxItems: 2
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s3c6410-rtc
+ - samsung,exynos3250-rtc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: rtc
+ - const: rtc_src
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: rtc
+
+examples:
+ - |
+ rtc@10070000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x10070000 0x100>;
+ interrupts = <0 44 4>, <0 45 4>;
+ clocks = <&clock 0>, // CLK_RTC
+ <&s2mps11_osc 0>; // S2MPS11_CLK_AP
+ clock-names = "rtc", "rtc_src";
+ };
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 08/11] dt-bindings: arm: samsung: Convert Exynos System Registers bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung Exynos System Registers (SYSREG) bindings to DT schema
format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Example somehow fails:
Documentation/devicetree/bindings/arm/samsung/pmu.example.dt.yaml:
system-controller@10040000: compatible:0: 'samsung,exynos5250-pmu' is
not one of ['samsung,exynos4-sysreg', 'samsung,exynos5-sysreg']
It seems that PMU schema is applied to sysreq nodes (and vice-versa).
---
.../bindings/arm/samsung/sysreg.txt | 19 -----------
.../bindings/arm/samsung/sysreg.yaml | 33 +++++++++++++++++++
2 files changed, 33 insertions(+), 19 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/sysreg.txt
create mode 100644 Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
deleted file mode 100644
index 4fced6e9d5e4..000000000000
--- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
-
-Properties:
- - compatible : should contain two values. First value must be one from following list:
- - "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
- - "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
- second value must be always "syscon".
- - reg : offset and length of the register set.
-
-Example:
- syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
-
- syscon@10050000 {
- compatible = "samsung,exynos5-sysreg", "syscon";
- reg = <0x10050000 0x5000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
new file mode 100644
index 000000000000..a3d44646e441
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P/Exynos SoC series System Registers (SYSREG)
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - samsung,exynos4-sysreg
+ - samsung,exynos5-sysreg
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+examples:
+ - |
+ syscon@10010000 {
+ compatible = "samsung,exynos4-sysreg", "syscon";
+ reg = <0x10010000 0x400>;
+ };
+
+ syscon@10050000 {
+ compatible = "samsung,exynos5-sysreg", "syscon";
+ reg = <0x10050000 0x5000>;
+ };
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 07/11] dt-bindings: arm: samsung: Convert Exynos PMU bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung Exynos Power Management Unit (PMU) bindings to DT schema
format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Fix clock-names to match all elements against schema (any number of
any clkoutN values).
This currently fails:
properties:clock-names:items: {'enum': ['clkout0', 'clkout1', 'clkout2',
'clkout3', 'clkout4', 'clkout5', 'clkout6', 'clkout7', 'clkout8',
'clkout9', 'clkout10', 'clkout11', 'clkout12', 'clkout13', 'clkout14',
'clkout15', 'clkout16']} is not of type 'array
2. Add syscon reboot and poweroff nodes.
---
.../devicetree/bindings/arm/samsung/pmu.txt | 72 -----------
.../devicetree/bindings/arm/samsung/pmu.yaml | 117 ++++++++++++++++++
2 files changed, 117 insertions(+), 72 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.yaml
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
deleted file mode 100644
index 433bfd7593ac..000000000000
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-SAMSUNG Exynos SoC series PMU Registers
-
-Properties:
- - compatible : should contain two values. First value must be one from following list:
- - "samsung,exynos3250-pmu" - for Exynos3250 SoC,
- - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
- - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
- - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
- - "samsung,exynos5433-pmu" - for Exynos5433 SoC.
- - "samsung,exynos7-pmu" - for Exynos7 SoC.
- second value must be always "syscon".
-
- - reg : offset and length of the register set.
-
- - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
- The single specifier cell is used as index to list of clocks
- provided by PMU, which is currently:
- 0 : SoC clock output (CLKOUT pin)
-
- - clock-names : list of clock names for particular CLKOUT mux inputs in
- following format:
- "clkoutN", where N is a decimal number corresponding to
- CLKOUT mux control bits value for given input, e.g.
- "clkout0", "clkout7", "clkout15".
-
- - clocks : list of phandles and specifiers to all input clocks listed in
- clock-names property.
-
-Optional properties:
-
-Some PMUs are capable of behaving as an interrupt controller (mostly
-to wake up a suspended PMU). In which case, they can have the
-following properties:
-
-- interrupt-controller: indicate that said PMU is an interrupt controller
-
-- #interrupt-cells: must be identical to the that of the parent interrupt
- controller.
-
-
-Optional nodes:
-
-- nodes defining the restart and poweroff syscon children
-
-
-Example :
-pmu_system_controller: system-controller@10040000 {
- compatible = "samsung,exynos5250-pmu", "syscon";
- reg = <0x10040000 0x5000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- #clock-cells = <1>;
- clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
- "clkout4", "clkout8", "clkout9";
- clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
- <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
- <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
- <&clock CLK_XUSBXTI>;
-};
-
-Example of clock consumer :
-
-usb3503: usb3503@8 {
- /* ... */
- clock-names = "refclk";
- clocks = <&pmu_system_controller 0>;
- /* ... */
-};
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
new file mode 100644
index 000000000000..a5a02f8237fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC series Power Management Unit (PMU)
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - samsung,exynos3250-pmu
+ - samsung,exynos4210-pmu
+ - samsung,exynos4412-pmu
+ - samsung,exynos5250-pmu
+ - samsung,exynos5260-pmu
+ - samsung,exynos5410-pmu
+ - samsung,exynos5420-pmu
+ - samsung,exynos5433-pmu
+ - samsung,exynos7-pmu
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clock-names:
+ description:
+ List of clock names for particular CLKOUT mux inputs
+ minItems: 1
+ maxItems: 32
+ items:
+ enum:
+ - clkout0
+ - clkout1
+ - clkout2
+ - clkout3
+ - clkout4
+ - clkout5
+ - clkout6
+ - clkout7
+ - clkout8
+ - clkout9
+ - clkout10
+ - clkout11
+ - clkout12
+ - clkout13
+ - clkout14
+ - clkout15
+ - clkout16
+ - clkout17
+ - clkout18
+ - clkout19
+ - clkout20
+ - clkout21
+ - clkout22
+ - clkout23
+ - clkout24
+ - clkout25
+ - clkout26
+ - clkout27
+ - clkout28
+ - clkout29
+ - clkout30
+ - clkout31
+
+ clocks:
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller:
+ description:
+ Some PMUs are capable of behaving as an interrupt controller (mostly
+ to wake up a suspended PMU).
+
+ '#interrupt-cells':
+ description:
+ Must be identical to the that of the parent interrupt controller.
+ const: 3
+
+ syscon-poweroff:
+ $ref: "../../power/reset/syscon-poweroff.yaml#"
+ type: object
+ description:
+ Node for power off method
+
+ syscon-reboot:
+ $ref: "../../power/reset/syscon-reboot.yaml#"
+ type: object
+ description:
+ Node for reboot method
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clock-names
+ - clocks
+
+examples:
+ - |
+ pmu_system_controller: system-controller@10040000 {
+ compatible = "samsung,exynos5250-pmu", "syscon";
+ reg = <0x10040000 0x5000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ #clock-cells = <1>;
+ clock-names = "clkout16";
+ clocks = <&clock 0>; // CLK_FIN_PLL
+ };
--
2.17.1
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* [PATCH v2 06/11] dt-bindings: arm: samsung: Convert Exynos Chipid bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung Exynos Chipid bindings to DT schema format using
json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/arm/samsung/exynos-chipid.txt | 12 ---------
.../bindings/arm/samsung/exynos-chipid.yaml | 25 +++++++++++++++++++
2 files changed, 25 insertions(+), 12 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
create mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
deleted file mode 100644
index 85c5dfd4a720..000000000000
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-SAMSUNG Exynos SoCs Chipid driver.
-
-Required properties:
-- compatible : Should at least contain "samsung,exynos4210-chipid".
-
-- reg: offset and length of the register set
-
-Example:
- chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
- reg = <0x10000000 0x100>;
- };
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
new file mode 100644
index 000000000000..9c573ad7dc7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC series Chipid driver
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: samsung,exynos4210-chipid
+
+ reg:
+ maxItems: 1
+
+examples:
+ - |
+ chipid@10000000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x10000000 0x100>;
+ };
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 05/11] dt-bindings: arm: samsung: Document missing Exynos7 boards bindings
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Add missing documentation of ARMv8 Samsung Exynos7 SoC based boards
bindings.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index 98401a6db2a0..63acd57c4799 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -171,5 +171,11 @@ properties:
- samsung,tm2e # Samsung TM2E
- const: samsung,exynos5433
+ - description: Exynos7 based boards
+ items:
+ - enum:
+ - samsung,exynos7-espresso # Samsung Exynos7 Espresso
+ - const: samsung,exynos7
+
required:
- compatible
--
2.17.1
_______________________________________________
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^ permalink raw reply related
* [PATCH v2 04/11] dt-bindings: arm: samsung: Document missing S5Pv210 boards bindings
From: Krzysztof Kozlowski @ 2019-09-07 9:20 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Add missing documentation of Samsung S5Pv210 SoC based boards bindings.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
.../bindings/arm/samsung/samsung-boards.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index d8811edf7b7a..98401a6db2a0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -14,6 +14,16 @@ properties:
const: '/'
compatible:
oneOf:
+ - description: S5PV210 based boards
+ items:
+ - enum:
+ - aesop,torbreck # aESOP Torbreck based on S5PV210
+ - samsung,aquila # Samsung Aquila based on S5PC110
+ - samsung,goni # Samsung Goni based on S5PC110
+ - yic,smdkc110 # YIC System SMDKC110 based on S5PC110
+ - yic,smdkv210 # YIC System SMDKV210 based on S5PV210
+ - const: samsung,s5pv210
+
- description: S5PV210 based Aries boards
items:
- enum:
--
2.17.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 03/11] dt-bindings: arm: samsung: Convert Samsung board/soc bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:19 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert Samsung S5P and Exynos SoC bindings to DT schema format using
json-schema. This is purely conversion of already documented bindings
so it does not cover all of DTS in the Linux kernel (few S5P/Exynos and
all S3C are missing).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Make Google boards latest revision as const.
2. Split secure firmware into separate schema.
---
.../bindings/arm/samsung/samsung-boards.txt | 83 ---------
.../bindings/arm/samsung/samsung-boards.yaml | 165 ++++++++++++++++++
.../arm/samsung/samsung-secure-firmware.yaml | 31 ++++
3 files changed, 196 insertions(+), 83 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
create mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
create mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
deleted file mode 100644
index 56021bf2a916..000000000000
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-* Samsung's Exynos and S5P SoC based boards
-
-Required root node properties:
- - compatible = should be one or more of the following.
- - "samsung,aries" - for S5PV210-based Samsung Aries board.
- - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
- - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- - "samsung,monk" - for Exynos3250-based Samsung Simband board.
- - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
- - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- - "samsung,trats" - for Exynos4210-based Tizen Reference board.
- - "samsung,universal_c210" - for Exynos4210-based Samsung board.
- - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
- - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
- - "samsung,midas" - for Exynos4412-based Samsung Midas board.
- - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
- - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- - "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- - "samsung,xyref5260" - for Exynos5260-based Samsung board.
- - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
- - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
- - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
- - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
-
-* Other companies Exynos SoC based
- * FriendlyARM
- - "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
- TINY4412 board.
- * TOPEET
- - "topeet,itop4412-elite" - for Exynos4412-based TOPEET
- Elite base board.
-
- * Google
- - "google,pi" - for Exynos5800-based Google Peach Pi
- Rev 10+ board,
- also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
- "google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
- "google,pi-rev10", "google,peach".
-
- - "google,pit" - for Exynos5420-based Google Peach Pit
- Rev 6+ (Exynos5420),
- also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
- "google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
- "google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
- "google,pit-rev7", "google,pit-rev6", "google,peach".
-
- - "google,snow-rev4" - for Exynos5250-based Google Snow board,
- also: "google,snow"
- - "google,snow-rev5" - for Exynos5250-based Google Snow
- Rev 5+ board.
- - "google,spring" - for Exynos5250-based Google Spring board.
-
- * Hardkernel
- - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
- - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
- - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
- - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
- - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
- - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
- Odroid XU3 Lite board.
- - "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
- - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1.
-
- * Insignal
- - "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
- - "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
- Octa board.
- - "insignal,origen" - for Exynos4210-based Insignal Origen board.
- - "insignal,origen4412" - for Exynos4412-based Insignal Origen board.
-
-
-Optional nodes:
- - firmware node, specifying presence and type of secure firmware:
- - compatible: only "samsung,secure-firmware" is currently supported
- - reg: address of non-secure SYSRAM used for communication with firmware
-
- firmware@203f000 {
- compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
new file mode 100644
index 000000000000..d8811edf7b7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos and S5P SoC based boards
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: S5PV210 based Aries boards
+ items:
+ - enum:
+ - samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P)
+ - samsung,galaxys # Samsung Galaxy S (i9000)
+ - const: samsung,aries
+ - const: samsung,s5pv210
+
+ - description: Exynos3250 based boards
+ items:
+ - enum:
+ - samsung,monk # Samsung Simband
+ - samsung,rinato # Samsung Gear2
+ - const: samsung,exynos3250
+ - const: samsung,exynos3
+
+ - description: Samsung ARTIK5 boards
+ items:
+ - enum:
+ - samsung,artik5-eval # Samsung ARTIK5 eval board
+ - const: samsung,artik5 # Samsung ARTIK5 module
+ - const: samsung,exynos3250
+ - const: samsung,exynos3
+
+ - description: Exynos4210 based boards
+ items:
+ - enum:
+ - insignal,origen # Insignal Origen
+ - samsung,smdkv310 # Samsung SMDKV310 eval
+ - samsung,trats # Samsung Tizen Reference
+ - samsung,universal_c210 # Samsung C210
+ - const: samsung,exynos4210
+ - const: samsung,exynos4
+
+ - description: Exynos4412 based boards
+ items:
+ - enum:
+ - friendlyarm,tiny4412 # FriendlyARM TINY4412
+ - hardkernel,odroid-u3 # Hardkernel Odroid U3
+ - hardkernel,odroid-x # Hardkernel Odroid X
+ - hardkernel,odroid-x2 # Hardkernel Odroid X2
+ - insignal,origen4412 # Insignal Origen
+ - samsung,smdk4412 # Samsung SMDK4412 eval
+ - topeet,itop4412-elite # TOPEET Elite base
+ - const: samsung,exynos4412
+ - const: samsung,exynos4
+
+ - description: Samsung Midas family boards
+ items:
+ - enum:
+ - samsung,i9300 # Samsung GT-I9300
+ - samsung,i9305 # Samsung GT-I9305
+ - samsung,n710x # Samsung GT-N7100/GT-N7105
+ - samsung,trats2 # Samsung Tizen Reference
+ - const: samsung,midas
+ - const: samsung,exynos4412
+ - const: samsung,exynos4
+
+ - description: Exynos5250 based boards
+ items:
+ - enum:
+ - google,snow-rev5 # Google Snow Rev 5+
+ - google,spring # Google Spring
+ - insignal,arndale # Insignal Arndale
+ - samsung,smdk5250 # Samsung SMDK5250 eval
+ - const: samsung,exynos5250
+ - const: samsung,exynos5
+
+ - description: Google Snow Boards (Rev 4+)
+ items:
+ - const: google,snow-rev4
+ - const: google,snow
+ - const: samsung,exynos5250
+ - const: samsung,exynos5
+
+ - description: Exynos5260 based boards
+ items:
+ - enum:
+ - samsung,xyref5260 # Samsung Xyref5260 eval
+ - const: samsung,exynos5260
+ - const: samsung,exynos5
+
+ - description: Exynos5410 based boards
+ items:
+ - enum:
+ - hardkernel,odroid-xu # Hardkernel Odroid XU
+ - samsung,smdk5410 # Samsung SMDK5410 eval
+ - const: samsung,exynos5410
+ - const: samsung,exynos5
+
+ - description: Exynos5420 based boards
+ items:
+ - enum:
+ - insignal,arndale-octa # Insignal Arndale Octa
+ - samsung,smdk5420 # Samsung SMDK5420 eval
+ - const: samsung,exynos5420
+ - const: samsung,exynos5
+
+ - description: Google Peach Pit Boards (Rev 6+)
+ items:
+ - const: google,pit-rev16
+ - const: google,pit-rev15
+ - const: google,pit-rev14
+ - const: google,pit-rev13
+ - const: google,pit-rev12
+ - const: google,pit-rev11
+ - const: google,pit-rev10
+ - const: google,pit-rev9
+ - const: google,pit-rev8
+ - const: google,pit-rev7
+ - const: google,pit-rev6
+ - const: google,pit
+ - const: google,peach
+ - const: samsung,exynos5420
+ - const: samsung,exynos5
+
+ - description: Exynos5800 based boards
+ items:
+ - enum:
+ - hardkernel,odroid-xu3 # Hardkernel Odroid XU3
+ - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
+ - hardkernel,odroid-xu4 # Hardkernel Odroid XU4
+ - hardkernel,odroid-hc1 # Hardkernel Odroid HC1
+ - const: samsung,exynos5800
+ - const: samsung,exynos5
+
+ - description: Google Peach Pi Boards (Rev 10+)
+ items:
+ - const: google,pi-rev16
+ - const: google,pi-rev15
+ - const: google,pi-rev14
+ - const: google,pi-rev13
+ - const: google,pi-rev12
+ - const: google,pi-rev11
+ - const: google,pi-rev10
+ - const: google,pi
+ - const: google,peach
+ - const: samsung,exynos5800
+ - const: samsung,exynos5
+
+ - description: Exynos5433 based boards
+ items:
+ - enum:
+ - samsung,tm2 # Samsung TM2
+ - samsung,tm2e # Samsung TM2E
+ - const: samsung,exynos5433
+
+required:
+ - compatible
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
new file mode 100644
index 000000000000..51d23b6f8a94
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Secure Firmware
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: samsung,secure-firmware
+
+ reg:
+ description:
+ Address of non-secure SYSRAM used for communication with firmware.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ firmware@203f000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0203f000 0x1000>;
+ };
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 02/11] dt-bindings: power: syscon-poweroff: Convert bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:19 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
Convert the Syscon poweroff bindings to DT schema format using
json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Remove unneeded maxItems from uint32 fields,
2. Simplify if-else-then.
---
.../bindings/power/reset/syscon-poweroff.txt | 30 ----------
.../bindings/power/reset/syscon-poweroff.yaml | 60 +++++++++++++++++++
2 files changed, 60 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
deleted file mode 100644
index 022ed1f3bc80..000000000000
--- a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Generic SYSCON mapped register poweroff driver
-
-This is a generic poweroff driver using syscon to map the poweroff register.
-The poweroff is generally performed with a write to the poweroff register
-defined by the register map pointed by syscon reference plus the offset
-with the value and mask defined in the poweroff node.
-
-Required properties:
-- compatible: should contain "syscon-poweroff"
-- regmap: this is phandle to the register map node
-- offset: offset in the register map for the poweroff register (in bytes)
-- value: the poweroff value written to the poweroff register (32 bit access)
-
-Optional properties:
-- mask: update only the register bits defined by the mask (32 bit)
-
-Legacy usage:
-If a node doesn't contain a value property but contains a mask property, the
-mask property is used as the value.
-
-Default will be little endian mode, 32 bit access only.
-
-Examples:
-
- poweroff {
- compatible = "syscon-poweroff";
- regmap = <®mapnode>;
- offset = <0x0>;
- mask = <0x7a>;
- };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
new file mode 100644
index 000000000000..fb812937b534
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/syscon-poweroff.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic SYSCON mapped register poweroff driver
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |+
+ This is a generic poweroff driver using syscon to map the poweroff register.
+ The poweroff is generally performed with a write to the poweroff register
+ defined by the register map pointed by syscon reference plus the offset
+ with the value and mask defined in the poweroff node.
+ Default will be little endian mode, 32 bit access only.
+
+properties:
+ compatible:
+ const: syscon-poweroff
+
+ mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Update only the register bits defined by the mask (32 bit).
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the poweroff register (in bytes).
+
+ regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the register map node.
+
+ value:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The poweroff value written to the poweroff register (32 bit access).
+
+required:
+ - compatible
+ - regmap
+ - offset
+
+allOf:
+ - if:
+ not:
+ required:
+ - mask
+ then:
+ required:
+ - value
+
+examples:
+ - |
+ poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <®mapnode>;
+ offset = <0x0>;
+ mask = <0x7a>;
+ };
--
2.17.1
_______________________________________________
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^ permalink raw reply related
* [PATCH v2 01/11] dt-bindings: power: syscon-reboot: Convert bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-07 9:19 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Kukjin Kim, Krzysztof Kozlowski,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Sebastian Reichel, Alessandro Zummo,
Alexandre Belloni, Paweł Chmiel, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-iio,
linux-pm, linux-rtc
Convert the Syscon reboot bindings to DT schema format using
json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changes since v1:
1. Remove unneeded maxItems from uint32 fields,
2. Simplify if-else-then.
---
.../bindings/power/reset/syscon-reboot.txt | 30 ----------
.../bindings/power/reset/syscon-reboot.yaml | 60 +++++++++++++++++++
2 files changed, 60 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
deleted file mode 100644
index e23dea8344f8..000000000000
--- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Generic SYSCON mapped register reset driver
-
-This is a generic reset driver using syscon to map the reset register.
-The reset is generally performed with a write to the reset register
-defined by the register map pointed by syscon reference plus the offset
-with the value and mask defined in the reboot node.
-
-Required properties:
-- compatible: should contain "syscon-reboot"
-- regmap: this is phandle to the register map node
-- offset: offset in the register map for the reboot register (in bytes)
-- value: the reset value written to the reboot register (32 bit access)
-
-Optional properties:
-- mask: update only the register bits defined by the mask (32 bit)
-
-Legacy usage:
-If a node doesn't contain a value property but contains a mask property, the
-mask property is used as the value.
-
-Default will be little endian mode, 32 bit access only.
-
-Examples:
-
- reboot {
- compatible = "syscon-reboot";
- regmap = <®mapnode>;
- offset = <0x0>;
- mask = <0x1>;
- };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
new file mode 100644
index 000000000000..a7920f5eef79
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic SYSCON mapped register reset driver
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |+
+ This is a generic reset driver using syscon to map the reset register.
+ The reset is generally performed with a write to the reset register
+ defined by the register map pointed by syscon reference plus the offset
+ with the value and mask defined in the reboot node.
+ Default will be little endian mode, 32 bit access only.
+
+properties:
+ compatible:
+ const: syscon-reboot
+
+ mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Update only the register bits defined by the mask (32 bit).
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the reboot register (in bytes).
+
+ regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the register map node.
+
+ value:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The reset value written to the reboot register (32 bit access).
+
+required:
+ - compatible
+ - regmap
+ - offset
+
+allOf:
+ - if:
+ not:
+ required:
+ - mask
+ then:
+ required:
+ - value
+
+examples:
+ - |
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <®mapnode>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
--
2.17.1
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^ permalink raw reply related
* Re: [PATCH v2 0/5] ARM: make DaVinci part of the ARM v5 multiplatform build
From: Arnd Bergmann @ 2019-09-07 8:21 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David Lechner, Kevin Hilman, Bartosz Golaszewski, Sekhar Nori,
Linux Kernel Mailing List, Hans Verkuil, Mauro Carvalho Chehab,
Linux ARM, Linux Media Mailing List
In-Reply-To: <CAMpxmJX7osgdzx1Lc=627RpHZDs+ha8a6=AnhaQJ5HkLVp-xKg@mail.gmail.com>
On Wed, Aug 28, 2019 at 9:55 AM Bartosz Golaszewski
<bgolaszewski@baylibre.com> wrote:
> śr., 28 sie 2019 o 09:44 Sekhar Nori <nsekhar@ti.com> napisał(a):
>
> Actually I tested this without the clocksource conversion and it works
> - the previous driver still selects relevant config options. But I
> think you're right - it's worth picking up all the bug fixes from this
> series and then merging the rest once dm365 issue is fixed.
I just had another look at the series and found that the driver fixes
(patches 1 and 2) are queued in linux-next, and patch 3 was merged.
If you like, I could put the remaining two patches into the arm/late branch
and send that after the media and staging trees are merged into mainline.
Arnd
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^ permalink raw reply
* Re: [PATCH 2/9] crypto: Add Allwinner sun8i-ce Crypto Engine
From: Maxime Ripard @ 2019-09-07 8:19 UTC (permalink / raw)
To: Corentin Labbe
Cc: mark.rutland, devicetree, herbert, linux-sunxi, linux,
linux-kernel, wens, robh+dt, linux-crypto, davem,
linux-arm-kernel
In-Reply-To: <20190906184551.17858-3-clabbe.montjoie@gmail.com>
Hi,
I can't really comment on the crypto side, so my review is going to be
pretty boring.
On Fri, Sep 06, 2019 at 08:45:44PM +0200, Corentin Labbe wrote:
> +static const struct ce_variant ce_h3_variant = {
> + .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
> + CE_ID_NOTSUPP,
> + },
As far as I can see, it's always the same value, so I'm not sure why
it's a parameter.
> + .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
> + },
Ditto
> + .intreg = CE_ISR,
Ditto
> + .maxflow = 4,
Ditto
> + .ce_clks = {
> + { "ahb", 200000000 },
This is the default IIRC, and the clock driver will ignore any clock
rate change on it anyway, so the clock rate is pretty much useless
there.
> + { "mod", 48000000 },
48MHz seems pretty slow, especially compared to the other rates you
have listed there. Is that on purpose?
Also, I'm not sure what is the point of having the clocks names be
parameters there as well. It's constant across all the compatibles,
the only thing that isn't is the number of clocks and the module clock
rate. It's what you should have in there.
> + }
> +};
> +
> +static const struct ce_variant ce_h5_variant = {
> + .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
> + CE_ID_NOTSUPP,
> + },
> + .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
> + },
> + .intreg = CE_ISR,
> + .maxflow = 4,
> + .ce_clks = {
> + { "ahb", 200000000 },
> + { "mod", 300000000 },
> + }
> +};
> +
> +static const struct ce_variant ce_h6_variant = {
> + .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
> + CE_ALG_RAES,
> + },
> + .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
> + },
> + .model = CE_v2,
Can't that be derived from the version register and / or the
compatible? This seems to be redundant with each.
> + .intreg = CE_ISR,
> + .maxflow = 4,
> + .ce_clks = {
> + { "ahb", 200000000 },
> + { "mod", 300000000 },
> + { "mbus", 400000000 },
That rate is going to be ignored as well.
> + }
> +};
> +
> +static const struct ce_variant ce_a64_variant = {
> + .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
> + CE_ID_NOTSUPP,
> + },
> + .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
> + },
> + .intreg = CE_ISR,
> + .maxflow = 4,
> + .ce_clks = {
> + { "ahb", 200000000 },
> + { "mod", 300000000 },
> + }
> +};
You should order your variants by alphabetical order.
> +static const struct ce_variant ce_r40_variant = {
> + .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
> + CE_ID_NOTSUPP,
> + },
> + .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
> + },
> + .intreg = CE_ISR,
> + .maxflow = 4,
> + .ce_clks = {
> + { "ahb", 200000000 },
> + { "mod", 300000000 },
> + }
> +};
> +
...
> +int sun8i_ce_get_engine_number(struct sun8i_ce_dev *ce)
> +{
> + return atomic_inc_return(&ce->flow) % ce->variant->maxflow;
> +}
I'm not sure what this is supposed to be doing, but that mod there
seems pretty dangerous.
...
> +static int sun8i_ce_probe(struct platform_device *pdev)
> +{
> + struct resource *res;
> + u32 v;
> + int err, i, ce_method, id, irq;
> + unsigned long cr;
> + struct sun8i_ce_dev *ce;
> +
> + if (!pdev->dev.of_node)
> + return -ENODEV;
This is pretty much guaranteed already
> + ce = devm_kzalloc(&pdev->dev, sizeof(*ce), GFP_KERNEL);
> + if (!ce)
> + return -ENOMEM;
> +
> + ce->variant = of_device_get_match_data(&pdev->dev);
> + if (!ce->variant) {
> + dev_err(&pdev->dev, "Missing Crypto Engine variant\n");
> + return -EINVAL;
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + ce->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(ce->base)) {
> + err = PTR_ERR(ce->base);
> + dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
> + return err;
ioremap_resource already prints an error message on failure, so this
is redundant.
> + }
> +
> + for (i = 0; i < CE_MAX_CLOCKS; i++) {
> + if (!ce->variant->ce_clks[i].name)
> + continue;
> + dev_info(&pdev->dev, "Get %s clock\n", ce->variant->ce_clks[i].name);
There's no reason to print this at the info level
> + ce->ceclks[i] = devm_clk_get(&pdev->dev, ce->variant->ce_clks[i].name);
> + if (IS_ERR(ce->ceclks[i])) {
> + err = PTR_ERR(ce->ceclks[i]);
> + dev_err(&pdev->dev, "Cannot get %s CE clock err=%d\n",
> + ce->variant->ce_clks[i].name, err);
> + }
> + cr = clk_get_rate(ce->ceclks[i]);
So on error you'd call clk_get_rate on the clock still? That seems
pretty fragile, you should return there, it's a hard error.
> + if (ce->variant->ce_clks[i].freq) {
> + dev_info(&pdev->dev, "Set %s clock to %lu (%lu Mhz) from %lu (%lu Mhz)\n",
> + ce->variant->ce_clks[i].name,
> + ce->variant->ce_clks[i].freq,
> + ce->variant->ce_clks[i].freq / 1000000,
> + cr,
> + cr / 1000000);
Same remark about that message than the previous one.
> + err = clk_set_rate(ce->ceclks[i], ce->variant->ce_clks[i].freq);
> + if (err)
> + dev_err(&pdev->dev, "Fail to set %s clk speed to %lu\n",
> + ce->variant->ce_clks[i].name,
> + ce->variant->ce_clks[i].freq);
> + } else {
> + dev_info(&pdev->dev, "%s run at %lu\n",
> + ce->variant->ce_clks[i].name, cr);
Ditto.
> + }
> + err = clk_prepare_enable(ce->ceclks[i]);
Do you really need this right now though?
> + if (err) {
> + dev_err(&pdev->dev, "Cannot prepare_enable %s\n",
> + ce->variant->ce_clks[i].name);
> + return err;
> + }
> + }
> +
> + /* Get Non Secure IRQ */
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(ce->dev, "Cannot get NS IRQ\n");
> + return irq;
> + }
> +
> + err = devm_request_irq(&pdev->dev, irq, ce_irq_handler, 0,
> + "sun8i-ce-ns", ce);
> + if (err < 0) {
> + dev_err(ce->dev, "Cannot request NS IRQ\n");
> + return err;
> + }
> +
> + ce->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
> + if (IS_ERR(ce->reset)) {
> + if (PTR_ERR(ce->reset) == -EPROBE_DEFER)
> + return PTR_ERR(ce->reset);
> + dev_info(&pdev->dev, "No reset control found\n");
It's not optional though.
> + ce->reset = NULL;
> + }
> +
> + err = reset_control_deassert(ce->reset);
> + if (err) {
> + dev_err(&pdev->dev, "Cannot deassert reset control\n");
> + goto error_clk;
> + }
Again, you don't really need this at this moment. Using runtime_pm
would make more sense.
> + v = readl(ce->base + CE_CTR);
> + v >>= 16;
> + v &= 0x07;
This should be in a define
> + dev_info(&pdev->dev, "CE_NS Die ID %x\n", v);
And if that really makes sense to print it, the error message should
be made less cryptic.
> +
> + ce->dev = &pdev->dev;
> + platform_set_drvdata(pdev, ce);
> +
> + mutex_init(&ce->mlock);
> +
> + ce->chanlist = devm_kcalloc(ce->dev, ce->variant->maxflow,
> + sizeof(struct sun8i_ce_flow), GFP_KERNEL);
> + if (!ce->chanlist) {
> + err = -ENOMEM;
> + goto error_flow;
> + }
> +
> + for (i = 0; i < ce->variant->maxflow; i++) {
> + init_completion(&ce->chanlist[i].complete);
> + mutex_init(&ce->chanlist[i].lock);
> +
> + ce->chanlist[i].engine = crypto_engine_alloc_init(ce->dev, true);
> + if (!ce->chanlist[i].engine) {
> + dev_err(ce->dev, "Cannot allocate engine\n");
> + i--;
> + goto error_engine;
> + }
> + err = crypto_engine_start(ce->chanlist[i].engine);
> + if (err) {
> + dev_err(ce->dev, "Cannot start engine\n");
> + goto error_engine;
> + }
> + ce->chanlist[i].tl = dma_alloc_coherent(ce->dev,
> + sizeof(struct ce_task),
> + &ce->chanlist[i].t_phy,
> + GFP_KERNEL);
> + if (!ce->chanlist[i].tl) {
> + dev_err(ce->dev, "Cannot get DMA memory for task %d\n",
> + i);
> + err = -ENOMEM;
> + goto error_engine;
> + }
> + }
All this initialization should be done before calling
request_irq. You're using some of those fields in your handler.
> +
> +#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
> + ce->dbgfs_dir = debugfs_create_dir("sun8i-ce", NULL);
> + if (IS_ERR_OR_NULL(ce->dbgfs_dir)) {
> + dev_err(ce->dev, "Fail to create debugfs dir");
> + err = -ENOMEM;
> + goto error_engine;
> + }
> + ce->dbgfs_stats = debugfs_create_file("stats", 0444,
> + ce->dbgfs_dir, ce,
> + &sun8i_ce_debugfs_fops);
> + if (IS_ERR_OR_NULL(ce->dbgfs_stats)) {
> + dev_err(ce->dev, "Fail to create debugfs stat");
> + err = -ENOMEM;
> + goto error_debugfs;
> + }
> +#endif
> + for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
> + ce_algs[i].ce = ce;
> + switch (ce_algs[i].type) {
> + case CRYPTO_ALG_TYPE_SKCIPHER:
> + id = ce_algs[i].ce_algo_id;
> + ce_method = ce->variant->alg_cipher[id];
> + if (ce_method == CE_ID_NOTSUPP) {
> + dev_info(ce->dev,
> + "DEBUG: Algo of %s not supported\n",
> + ce_algs[i].alg.skcipher.base.cra_name);
> + ce_algs[i].ce = NULL;
> + break;
> + }
> + id = ce_algs[i].ce_blockmode;
> + ce_method = ce->variant->op_mode[id];
> + if (ce_method == CE_ID_NOTSUPP) {
> + dev_info(ce->dev, "DEBUG: Blockmode of %s not supported\n",
> + ce_algs[i].alg.skcipher.base.cra_name);
> + ce_algs[i].ce = NULL;
> + break;
> + }
> + dev_info(ce->dev, "DEBUG: Register %s\n",
> + ce_algs[i].alg.skcipher.base.cra_name);
> + err = crypto_register_skcipher(&ce_algs[i].alg.skcipher);
> + if (err) {
> + dev_err(ce->dev, "Fail to register %s\n",
> + ce_algs[i].alg.skcipher.base.cra_name);
> + ce_algs[i].ce = NULL;
> + goto error_alg;
> + }
> + break;
> + default:
> + dev_err(ce->dev, "ERROR: tryed to register an unknown algo\n");
> + }
> + }
> +
> + return 0;
> +error_alg:
> + i--;
> + for (; i >= 0; i--) {
> + switch (ce_algs[i].type) {
> + case CRYPTO_ALG_TYPE_SKCIPHER:
> + if (ce_algs[i].ce)
> + crypto_unregister_skcipher(&ce_algs[i].alg.skcipher);
> + break;
> + }
> + }
> +#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
> +error_debugfs:
> + debugfs_remove_recursive(ce->dbgfs_dir);
> +#endif
> + i = ce->variant->maxflow;
> +error_engine:
> + while (i >= 0) {
> + crypto_engine_exit(ce->chanlist[i].engine);
> + if (ce->chanlist[i].tl)
> + dma_free_coherent(ce->dev, sizeof(struct ce_task),
> + ce->chanlist[i].tl,
> + ce->chanlist[i].t_phy);
> + i--;
> + }
> +error_flow:
> + reset_control_assert(ce->reset);
> +error_clk:
> + for (i = 0; i < CE_MAX_CLOCKS; i++)
> + clk_disable_unprepare(ce->ceclks[i]);
> + return err;
> +}
So that function takes around 200-250 LoC, this is definitely too
much and should be split into multiple functions.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH 1/4] cpufreq: ti-cpufreq: add support for omap34xx and omap36xx
From: H. Nikolaus Schaller @ 2019-09-07 7:37 UTC (permalink / raw)
To: Benoît Cousson, Tony Lindgren, Rob Herring, Adam Ford,
André Roth, Mark Rutland, Rafael J. Wysocki, Viresh Kumar,
Enric Balletbo i Serra, Javier Martinez Canillas, Roger Quadros,
Teresa Remmet, Nikolaus Schaller
Cc: devicetree, Linux-OMAP, linux-pm, Linux Kernel Mailing List,
kernel, Discussions about the Letux Kernel, linux-arm-kernel
In-Reply-To: <0eb7129f6148faac0150d6299ac97347484c7125.1567839375.git.hns@goldelico.com>
> Am 07.09.2019 um 08:56 schrieb H. Nikolaus Schaller <hns@goldelico.com>:
>
> This adds code and tables to read the silicon revision and
> eFuse (speed binned / 720 MHz grade) bits for selecting
> opp-v2 table entries.
>
> Since these bits are not always part of the syscon register
> range (like for am33xx, am43, dra7), we add code to directly
> read the register values using ioremap() if syscon access fails.
>
> The format of the opp-supported-hw entries is that it has
> two 32 bit bitfields. E.g.:
>
> opp-supported-hw = <0xffffffff 3>
>
> The first value is matched against the bit position of the
> silicon revision which is (see TRM)
>
> omap34xx:
> BIT(0) ES1.0
> BIT(1) ES2.0
> BIT(2) ES2.1
> BIT(3) ES3.0
> BIT(4) ES3.1
> BIT(7) ES3.1.2
>
> omap36xx:
> BIT(0) ES1.0
> BIT(1) ES1.1
> BIT(2) ES1.2
>
> The second value is matched against the speed grade eFuse:
>
> BIT(0) no high speed OPP
> BIT(1) high speed OPP
>
> This means for the example above that it is always enabled
> while e.g.
>
> opp-supported-hw = <0x1 2>
>
> enables the OPP only for ES1.0 BIT(0) and if the high speed
> eFuse is set BIT(1).
>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
> drivers/cpufreq/ti-cpufreq.c | 91 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 89 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> index 2ad1ae17932d..f2f58d689320 100644
> --- a/drivers/cpufreq/ti-cpufreq.c
> +++ b/drivers/cpufreq/ti-cpufreq.c
> @@ -31,6 +31,11 @@
> #define DRA7_EFUSE_OD_MPU_OPP BIT(1)
> #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
>
> +#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
> +#define OMAP3_CONTROL_IDCODE 0x4830A204
> +#define OMAP34xx_ProdID_SKUID 0x4830A20C
> +#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
> +
> #define VERSION_COUNT 2
>
> struct ti_cpufreq_data;
> @@ -84,6 +89,13 @@ static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
> return calculated_efuse;
> }
>
> +static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> + unsigned long efuse)
> +{
> + /* OPP enable bit ("Speed Binned") */
> + return BIT(efuse);
> +}
> +
> static struct ti_cpufreq_soc_data am3x_soc_data = {
> .efuse_xlate = amx3_efuse_xlate,
> .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
> @@ -111,6 +123,56 @@ static struct ti_cpufreq_soc_data dra7_soc_data = {
> .multi_regulator = true,
> };
>
> +/*
> + * OMAP35x TRM (SPRUF98K):
> + * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
> + * Control OMAP Status Register 15:0 (Address 0x4800 244C)
> + * to separate between omap3503, omap3515, omap3525, omap3530
> + * and feature presence.
> + * There are encodings for versions limited to 400/266MHz
> + * but we ignore.
> + * Not clear if this also holds for omap34xx.
> + * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
> + * are stored in the SYSCON register range
> + * Register 0x4830A20C [ProdID.SKUID] [0:3]
> + * 0x0 for normal 600/430MHz device.
> + * 0x8 for 720/520MHz device.
> + * Not clear what omap34xx value is.
> + */
> +
> +static struct ti_cpufreq_soc_data omap34xx_soc_data = {
> + .efuse_xlate = omap3_efuse_xlate,
> + .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
> + .efuse_shift = 3,
> + .efuse_mask = BIT(3),
> + .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
> + .multi_regulator = false,
> +};
> +
> +/*
> + * AM/DM37x TRM (SPRUGN4M)
> + * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
> + * Control Device Status Register 15:0 (Address 0x4800 244C)
> + * to separate between am3703, am3715, dm3725, dm3730
> + * and feature presence.
> + * Speed Binned = Bit 9
> + * 0 800/600 MHz
> + * 1 1000/800 MHz
> + * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
> + * are stored in the SYSCON register range.
> + * There is no 0x4830A20C [ProdID.SKUID] register (exists but
> + * seems to always read as 0).
> + */
> +
> +static struct ti_cpufreq_soc_data omap36xx_soc_data = {
> + .efuse_xlate = omap3_efuse_xlate,
> + .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
> + .efuse_shift = 9,
> + .efuse_mask = BIT(9),
> + .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
> + .multi_regulator = false,
> +};
> +
> /**
> * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
> * @opp_data: pointer to ti_cpufreq_data context
> @@ -127,7 +189,17 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
>
> ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
> &efuse);
> - if (ret) {
> + if (ret == -EIO) {
> + /* not a syscon register! */
> + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
> + opp_data->soc_data->efuse_offset, 4);
> +
> + if (!regs)
> + return -ENOMEM;
> + efuse = readl(regs);
> + iounmap(regs);
> + }
> + else if (ret) {
> dev_err(dev,
> "Failed to read the efuse value from syscon: %d\n",
> ret);
> @@ -158,7 +230,17 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
>
> ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
> &revision);
> - if (ret) {
> + if (ret == -EIO) {
> + /* not a syscon register! */
> + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
> + opp_data->soc_data->rev_offset, 4);
> +
> + if (!regs)
> + return -ENOMEM;
> + revision = readl(regs);
> + iounmap(regs);
> + }
> + else if (ret) {
> dev_err(dev,
> "Failed to read the revision number from syscon: %d\n",
> ret);
> @@ -190,6 +272,11 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
> { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
> { .compatible = "ti,am43", .data = &am4x_soc_data, },
> { .compatible = "ti,dra7", .data = &dra7_soc_data },
> + { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
> + { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
> + /* legacy */
> + { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
> + { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
Well, I just realized that with the latest DTS changes,
ti,omap34xx and ti,omap36xx are legacy and
ti,omap3430 and ti,omap3630 are now official.
> {},
> };
>
> --
> 2.19.1
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 3/4] ARM: dts: omap3: bulk convert compatible to be explicitly ti, omap3430 or ti, omap3630 or ti, am3517
From: H. Nikolaus Schaller @ 2019-09-07 6:56 UTC (permalink / raw)
To: Benoît Cousson, Tony Lindgren, Rob Herring, Adam Ford,
André Roth, Mark Rutland, Rafael J. Wysocki, Viresh Kumar,
Enric Balletbo i Serra, Javier Martinez Canillas, Roger Quadros,
Teresa Remmet, H. Nikolaus Schaller
Cc: devicetree, linux-omap, linux-pm, linux-kernel, kernel,
letux-kernel, linux-arm-kernel
In-Reply-To: <cover.1567839375.git.hns@goldelico.com>
For the ti-cpufreq driver we need a clear separation between omap34 and omap36 families
since they have different silicon revisions and efuses.
So far ti,omap3630/ti,omap36xx is just an additional flag to ti,omap3 while omap34 has no
required entry.
Therefore we can not match omap34 boards properly.
This needs to add ti,omap3430 and ti,omap3630 where it is missing.
We also clean up some instances of missing ti,am3517 so that we can rely on
seeing either one of:
ti,am3517
ti,omap3430
ti,omap3630
in addition to ti,omap3.
We leave ti,omap34xx and ti,omap36xx untouched for compatibility.
The script to do the conversion is:
find arch/arm/boot/dts -name '*.dts*' -exec fgrep -q '"ti,omap34xx"' {} \; ! -exec fgrep -q '"ti,omap3430"' {} \; -exec sed -i '' 's/"ti,omap34xx"/"ti,omap3430", "ti,omap34xx"/' {} \;
find arch/arm/boot/dts -name '*.dts*' -exec fgrep -q '"ti,omap36xx"' {} \; ! -exec fgrep -q '"ti,omap3630"' {} \; -exec sed -i '' 's/"ti,omap36xx"/"ti,omap3630", "ti,omap36xx"/' {} \;
find arch/arm/boot/dts \( -name 'omap*.dts*' -o -name 'logic*.dts*' \) -exec fgrep -q '"ti,omap3"' {} \; ! -exec fgrep -q '"ti,omap3630"' {} \; ! -exec fgrep -q '"ti,omap36xx"' {} \; ! -exec fgrep -q '"ti,am3517"' {} \; ! -exec fgrep -q '"ti,omap34xx"' {} \; ! -exec fgrep -q '"ti,omap3430"' {} \; -exec sed -i '' 's/"ti,omap3"/"ti,omap3430", "ti,omap3"/' {} \;
So if your out-of-tree omap3 board does not show any OPPs, please check
the compatibility entry and update if needed.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
arch/arm/boot/dts/am3517_mt_ventoux.dts | 2 +-
arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts | 2 +-
arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts | 2 +-
arch/arm/boot/dts/omap3-beagle-xm.dts | 2 +-
arch/arm/boot/dts/omap3-beagle.dts | 2 +-
arch/arm/boot/dts/omap3-cm-t3530.dts | 2 +-
arch/arm/boot/dts/omap3-cm-t3730.dts | 2 +-
arch/arm/boot/dts/omap3-devkit8000-lcd43.dts | 2 +-
arch/arm/boot/dts/omap3-devkit8000-lcd70.dts | 2 +-
arch/arm/boot/dts/omap3-devkit8000.dts | 2 +-
arch/arm/boot/dts/omap3-gta04.dtsi | 2 +-
arch/arm/boot/dts/omap3-ha-lcd.dts | 2 +-
arch/arm/boot/dts/omap3-ha.dts | 2 +-
arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 2 +-
arch/arm/boot/dts/omap3-igep0020.dts | 2 +-
arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 2 +-
arch/arm/boot/dts/omap3-igep0030.dts | 2 +-
arch/arm/boot/dts/omap3-ldp.dts | 2 +-
arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 2 +-
arch/arm/boot/dts/omap3-lilly-dbb056.dts | 2 +-
arch/arm/boot/dts/omap3-n9.dts | 2 +-
arch/arm/boot/dts/omap3-n950.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-alto35.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-gallop43.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-palo35.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-palo43.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-summit.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-tobi.dts | 2 +-
arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts | 2 +-
arch/arm/boot/dts/omap3-pandora-1ghz.dts | 2 +-
arch/arm/boot/dts/omap3-sbc-t3530.dts | 2 +-
arch/arm/boot/dts/omap3-sbc-t3730.dts | 2 +-
arch/arm/boot/dts/omap3-sniper.dts | 2 +-
arch/arm/boot/dts/omap3-thunder.dts | 2 +-
arch/arm/boot/dts/omap3-zoom3.dts | 2 +-
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
37 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index e507e4ae0d88..e7d7124a34ba 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -8,7 +8,7 @@
/ {
model = "TeeJet Mt.Ventoux";
- compatible = "teejet,mt_ventoux", "ti,omap3";
+ compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
index f7a841a28865..2a0a98fe67f0 100644
--- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
index 7675bc3fa868..57bae2aa910e 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx Torpedo Development Kit";
- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 1aa99fc1487a..125ed933ca75 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard xM";
- compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index e3df3c166902..4ed3f93f5841 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard";
- compatible = "ti,omap3-beagle", "ti,omap3";
+ compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index 76e52c78cbb4..32dbaeaed147 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3530";
- compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
/* Regulator to trigger the reset signal of the Wifi module */
mmc2_sdio_reset: regulator-mmc2-sdio-reset {
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 6e944dfa0f3d..683819bf0915 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3730";
- compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
index a80fc60bc773..afed85078ad8 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
index 0753776071f8..07c51a105c0d 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index faafc48d8f61..162d0726b008 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
#include "omap3-devkit8000-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
aliases {
display1 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index b295f6fad2a5..25b6ed9203e1 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -11,7 +11,7 @@
/ {
model = "OMAP3 GTA04";
- compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
index badb9b3c8897..c9ecbc45c8e2 100644
--- a/arch/arm/boot/dts/omap3-ha-lcd.dts
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts
index a5365252bfbe..35c4e15abeb7 100644
--- a/arch/arm/boot/dts/omap3-ha.dts
+++ b/arch/arm/boot/dts/omap3-ha.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
index 03dcd05fb8a0..d134ce1cffc0 100644
--- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 6d0519e3dfd0..e341535a7162 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
index 060acd1e803a..9ca1d0f61964 100644
--- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 25170bd3c573..32f31035daa2 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 9a5fde2d9bce..ec9ba04ef43b 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -10,7 +10,7 @@
/ {
model = "TI OMAP3430 LDP (Zoom1 Labrador)";
- compatible = "ti,omap3-ldp", "ti,omap3";
+ compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index c22833d4e568..73d477898ec2 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -7,7 +7,7 @@
/ {
model = "INCOstartec LILLY-A83X module (DM3730)";
- compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
chosen {
bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
index fec335400074..ecb4ef738e07 100644
--- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -8,7 +8,7 @@
/ {
model = "INCOstartec LILLY-DBB056 (DM3730)";
- compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&twl {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 74c0ff2350d3..2495a696cec6 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N9";
- compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&i2c2 {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index 9886bf8b90ab..31d47a1fad84 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N950";
- compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3";
keys {
compatible = "gpio-keys";
diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
index 18338576c41d..7f04dfad8203 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
index f204c8af8281..bc5a04e03336 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
index c633f7cee68e..065c31cbf0e2 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
index fb88ebc9858c..e38c1c51392c 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35";
- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
index 76cca00d97b6..e6dc23159c4d 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
index cc081a9e4c1e..587c08ce282d 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
index 1de41c0826e0..f57de6010994 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -14,6 +14,6 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
index 9ed13118ed8e..281af6c113be 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo";
- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
index 81b957f33c9f..ea509956d7ac 100644
--- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -16,7 +16,7 @@
/ {
model = "Pandora Handheld Console 1GHz";
- compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3";
+ compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index ae96002abb3b..24bf3fd86641 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3530 with CM-T3530";
- compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 7de6df16fc17..eb3893b9535e 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3730 with CM-T3730";
- compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts
index 40a87330e8c3..b6879cdc5c13 100644
--- a/arch/arm/boot/dts/omap3-sniper.dts
+++ b/arch/arm/boot/dts/omap3-sniper.dts
@@ -9,7 +9,7 @@
/ {
model = "LG Optimus Black";
- compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3";
+ compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
index 6276e7079b36..64221e3b3477 100644
--- a/arch/arm/boot/dts/omap3-thunder.dts
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
- compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index db3a2fe84e99..d240e39f2151 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -9,7 +9,7 @@
/ {
model = "TI Zoom3";
- compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 0abd61108a53..7bfde8aac7ae 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3430 SDP";
- compatible = "ti,omap3430-sdp", "ti,omap3";
+ compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
--
2.19.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 1/4] cpufreq: ti-cpufreq: add support for omap34xx and omap36xx
From: H. Nikolaus Schaller @ 2019-09-07 6:56 UTC (permalink / raw)
To: Benoît Cousson, Tony Lindgren, Rob Herring, Adam Ford,
André Roth, Mark Rutland, Rafael J. Wysocki, Viresh Kumar,
Enric Balletbo i Serra, Javier Martinez Canillas, Roger Quadros,
Teresa Remmet, H. Nikolaus Schaller
Cc: devicetree, linux-omap, linux-pm, linux-kernel, kernel,
letux-kernel, linux-arm-kernel
In-Reply-To: <cover.1567839375.git.hns@goldelico.com>
This adds code and tables to read the silicon revision and
eFuse (speed binned / 720 MHz grade) bits for selecting
opp-v2 table entries.
Since these bits are not always part of the syscon register
range (like for am33xx, am43, dra7), we add code to directly
read the register values using ioremap() if syscon access fails.
The format of the opp-supported-hw entries is that it has
two 32 bit bitfields. E.g.:
opp-supported-hw = <0xffffffff 3>
The first value is matched against the bit position of the
silicon revision which is (see TRM)
omap34xx:
BIT(0) ES1.0
BIT(1) ES2.0
BIT(2) ES2.1
BIT(3) ES3.0
BIT(4) ES3.1
BIT(7) ES3.1.2
omap36xx:
BIT(0) ES1.0
BIT(1) ES1.1
BIT(2) ES1.2
The second value is matched against the speed grade eFuse:
BIT(0) no high speed OPP
BIT(1) high speed OPP
This means for the example above that it is always enabled
while e.g.
opp-supported-hw = <0x1 2>
enables the OPP only for ES1.0 BIT(0) and if the high speed
eFuse is set BIT(1).
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
drivers/cpufreq/ti-cpufreq.c | 91 +++++++++++++++++++++++++++++++++++-
1 file changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 2ad1ae17932d..f2f58d689320 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -31,6 +31,11 @@
#define DRA7_EFUSE_OD_MPU_OPP BIT(1)
#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
+#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
+#define OMAP3_CONTROL_IDCODE 0x4830A204
+#define OMAP34xx_ProdID_SKUID 0x4830A20C
+#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
+
#define VERSION_COUNT 2
struct ti_cpufreq_data;
@@ -84,6 +89,13 @@ static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
return calculated_efuse;
}
+static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ /* OPP enable bit ("Speed Binned") */
+ return BIT(efuse);
+}
+
static struct ti_cpufreq_soc_data am3x_soc_data = {
.efuse_xlate = amx3_efuse_xlate,
.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
@@ -111,6 +123,56 @@ static struct ti_cpufreq_soc_data dra7_soc_data = {
.multi_regulator = true,
};
+/*
+ * OMAP35x TRM (SPRUF98K):
+ * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
+ * Control OMAP Status Register 15:0 (Address 0x4800 244C)
+ * to separate between omap3503, omap3515, omap3525, omap3530
+ * and feature presence.
+ * There are encodings for versions limited to 400/266MHz
+ * but we ignore.
+ * Not clear if this also holds for omap34xx.
+ * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
+ * are stored in the SYSCON register range
+ * Register 0x4830A20C [ProdID.SKUID] [0:3]
+ * 0x0 for normal 600/430MHz device.
+ * 0x8 for 720/520MHz device.
+ * Not clear what omap34xx value is.
+ */
+
+static struct ti_cpufreq_soc_data omap34xx_soc_data = {
+ .efuse_xlate = omap3_efuse_xlate,
+ .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
+ .efuse_shift = 3,
+ .efuse_mask = BIT(3),
+ .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
+ .multi_regulator = false,
+};
+
+/*
+ * AM/DM37x TRM (SPRUGN4M)
+ * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
+ * Control Device Status Register 15:0 (Address 0x4800 244C)
+ * to separate between am3703, am3715, dm3725, dm3730
+ * and feature presence.
+ * Speed Binned = Bit 9
+ * 0 800/600 MHz
+ * 1 1000/800 MHz
+ * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
+ * are stored in the SYSCON register range.
+ * There is no 0x4830A20C [ProdID.SKUID] register (exists but
+ * seems to always read as 0).
+ */
+
+static struct ti_cpufreq_soc_data omap36xx_soc_data = {
+ .efuse_xlate = omap3_efuse_xlate,
+ .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
+ .efuse_shift = 9,
+ .efuse_mask = BIT(9),
+ .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
+ .multi_regulator = false,
+};
+
/**
* ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
* @opp_data: pointer to ti_cpufreq_data context
@@ -127,7 +189,17 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
&efuse);
- if (ret) {
+ if (ret == -EIO) {
+ /* not a syscon register! */
+ void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
+ opp_data->soc_data->efuse_offset, 4);
+
+ if (!regs)
+ return -ENOMEM;
+ efuse = readl(regs);
+ iounmap(regs);
+ }
+ else if (ret) {
dev_err(dev,
"Failed to read the efuse value from syscon: %d\n",
ret);
@@ -158,7 +230,17 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
&revision);
- if (ret) {
+ if (ret == -EIO) {
+ /* not a syscon register! */
+ void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
+ opp_data->soc_data->rev_offset, 4);
+
+ if (!regs)
+ return -ENOMEM;
+ revision = readl(regs);
+ iounmap(regs);
+ }
+ else if (ret) {
dev_err(dev,
"Failed to read the revision number from syscon: %d\n",
ret);
@@ -190,6 +272,11 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
{ .compatible = "ti,am33xx", .data = &am3x_soc_data, },
{ .compatible = "ti,am43", .data = &am4x_soc_data, },
{ .compatible = "ti,dra7", .data = &dra7_soc_data },
+ { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
+ { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
+ /* legacy */
+ { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
+ { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
{},
};
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related
* [PATCH 2/4] ARM: dts: replace opp-v1 tables by opp-v2 for omap34xx and omap36xx
From: H. Nikolaus Schaller @ 2019-09-07 6:56 UTC (permalink / raw)
To: Benoît Cousson, Tony Lindgren, Rob Herring, Adam Ford,
André Roth, Mark Rutland, Rafael J. Wysocki, Viresh Kumar,
Enric Balletbo i Serra, Javier Martinez Canillas, Roger Quadros,
Teresa Remmet, H. Nikolaus Schaller
Cc: devicetree, linux-omap, linux-pm, linux-kernel, kernel,
letux-kernel, linux-arm-kernel
In-Reply-To: <cover.1567839375.git.hns@goldelico.com>
In addition, move omap3 from whitelist to blacklist in cpufreq-dt-platdev
in the same patch, because doing either first breaks operation and
may make trouble in bisect.
We also can remove opp-v1 table for omap3-n950-n9 since it is now
automatically detected.
We also fix a wrong OPP4 voltage for omap3430 which must be
0.6V + 54*12.5mV = 1275mV. Otherwise the twl4030 driver will reject
this OPP.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
arch/arm/boot/dts/omap3-n950-n9.dtsi | 7 ---
arch/arm/boot/dts/omap34xx.dtsi | 65 ++++++++++++++++++++++++----
arch/arm/boot/dts/omap36xx.dtsi | 53 +++++++++++++++++++----
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +-
4 files changed, 102 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 5441e9ffdbb4..e98b0c615f19 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -11,13 +11,6 @@
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- 1000000 1375000
- >;
};
};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index f572a477f74c..91154829f86a 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -16,19 +16,66 @@
/ {
cpus {
cpu: cpu@0 {
- /* OMAP343x/OMAP35xx variants OPP1-5 */
- operating-points = <
- /* kHz uV */
- 125000 975000
- 250000 1075000
- 500000 1200000
- 550000 1270000
- 600000 1350000
- >;
+ /* OMAP343x/OMAP35xx variants OPP1-6 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
clock-latency = <300000>; /* From legacy driver */
};
};
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp1-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 3-3 of the omap3530 Data sheet (SPRS507F).
+ * Format is: <target min max>
+ */
+ opp-microvolt = <975000 975000 975000>;
+ /*
+ * first value is silicon revision bit mask
+ * second one 720MHz Device Identification bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp2-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1075000 1075000 1075000>;
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp3-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp4-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <1275000 1275000 1275000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp5-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp6-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ /* only high-speed grade omap3530 devices */
+ opp-supported-hw = <0xffffffff 2>;
+ };
+ };
+
ocp@68000000 {
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 6fb23ada1f64..44f25b0eb45b 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -19,15 +19,52 @@
};
cpus {
- /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+ /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
cpu: cpu@0 {
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- >;
- clock-latency = <300000>; /* From legacy driver */
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ };
+
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp50-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 4-19 of the DM3730 Data sheet (SPRS685B)
+ * Format is: <target min max>
+ */
+ opp-microvolt = <1012500 1012500 1012500>;
+ /*
+ * first value is silicon revision bit mask
+ * second one is "speed binned" bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp100-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp130-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1325000 1325000 1325000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp1g-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1375000 1375000 1375000>;
+ /* only on am/dm37x with speed-binned bit set */
+ opp-supported-hw = <0xffffffff 2>;
};
};
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 03dc4244ab00..68b7fc4225f8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -86,7 +86,6 @@ static const struct of_device_id whitelist[] __initconst = {
{ .compatible = "st-ericsson,u9540", },
{ .compatible = "ti,omap2", },
- { .compatible = "ti,omap3", },
{ .compatible = "ti,omap4", },
{ .compatible = "ti,omap5", },
@@ -132,6 +131,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "ti,am33xx", },
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
+ { .compatible = "ti,omap3", },
{ }
};
--
2.19.1
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