* [PATCH 2/3] pinctrl: meson-a1: add pinctrl driver for Meson A1 Soc
From: Qianggui Song @ 2019-09-17 6:07 UTC (permalink / raw)
To: Linus Walleij, linux-gpio
Cc: Qianggui Song, Mark Rutland, Hanjie Lin, Jianxin Pan,
Neil Armstrong, Martin Blumenstingl, Kevin Hilman, linux-kernel,
Rob Herring, linux-arm-kernel, Carlo Caione, linux-amlogic,
Xingyu Chen, Jerome Brunet
In-Reply-To: <1568700442-18540-1-git-send-email-qianggui.song@amlogic.com>
Add pinctrl driver for Meson A1 Soc which share the same register layout of
pinmux with previous Meson-G12A, however there is difference for gpio
and pin config register in A1. The register layout is as below:
/* first bank */ /* addr */
- P_PADCTRL_GPIOP_I base + 0x00 << 2
- P_PADCTRL_GPIOP_O base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2
- P_PADCTRL_GPIOP_DS base + 0x05 << 2
/* second bank */
- P_PADCTRL_GPIOB_I base + 0x10 << 2
- P_PADCTRL_GPIOB_O base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2
- P_PADCTRL_GPIOB_DS base + 0x15 << 2
Each bank contains at least 6 registers to be configured, if one bank has
more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between
two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say,
for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24,0x25 according
to above register layout.
Current Meson pinctrl driver can cover such change by using base address of
GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Soc that not support drive-strength like AXG
. Here a private data used to identify register layout is introduced.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
drivers/pinctrl/meson/Kconfig | 6 +
drivers/pinctrl/meson/Makefile | 1 +
drivers/pinctrl/meson/pinctrl-meson-a1.c | 942 +++++++++++++++++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 8 +-
drivers/pinctrl/meson/pinctrl-meson.h | 9 +
5 files changed, 964 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-a1.c
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index df55f61..3cb1191 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -54,4 +54,10 @@ config PINCTRL_MESON_G12A
select PINCTRL_MESON_AXG_PMX
default y
+config PINCTRL_MESON_A1
+ bool "Meson a1 Soc pinctrl driver"
+ depends on ARM64
+ select PINCTRL_MESON_AXG_PMX
+ default y
+
endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index a69c565..1a5bffe 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
+obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c
new file mode 100644
index 0000000..f3a88f1
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
@@ -0,0 +1,942 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Pin controller and GPIO driver for Amlogic Meson A1 SoC.
+ *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Qianggui Song <qianggui.song@amlogic.com>
+ */
+
+#include <dt-bindings/gpio/meson-a1-gpio.h>
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+static const struct pinctrl_pin_desc meson_a1_periphs_pins[] = {
+ MESON_PIN(GPIOP_0),
+ MESON_PIN(GPIOP_1),
+ MESON_PIN(GPIOP_2),
+ MESON_PIN(GPIOP_3),
+ MESON_PIN(GPIOP_4),
+ MESON_PIN(GPIOP_5),
+ MESON_PIN(GPIOP_6),
+ MESON_PIN(GPIOP_7),
+ MESON_PIN(GPIOP_8),
+ MESON_PIN(GPIOP_9),
+ MESON_PIN(GPIOP_10),
+ MESON_PIN(GPIOP_11),
+ MESON_PIN(GPIOP_12),
+ MESON_PIN(GPIOB_0),
+ MESON_PIN(GPIOB_1),
+ MESON_PIN(GPIOB_2),
+ MESON_PIN(GPIOB_3),
+ MESON_PIN(GPIOB_4),
+ MESON_PIN(GPIOB_5),
+ MESON_PIN(GPIOB_6),
+ MESON_PIN(GPIOX_0),
+ MESON_PIN(GPIOX_1),
+ MESON_PIN(GPIOX_2),
+ MESON_PIN(GPIOX_3),
+ MESON_PIN(GPIOX_4),
+ MESON_PIN(GPIOX_5),
+ MESON_PIN(GPIOX_6),
+ MESON_PIN(GPIOX_7),
+ MESON_PIN(GPIOX_8),
+ MESON_PIN(GPIOX_9),
+ MESON_PIN(GPIOX_10),
+ MESON_PIN(GPIOX_11),
+ MESON_PIN(GPIOX_12),
+ MESON_PIN(GPIOX_13),
+ MESON_PIN(GPIOX_14),
+ MESON_PIN(GPIOX_15),
+ MESON_PIN(GPIOX_16),
+ MESON_PIN(GPIOF_0),
+ MESON_PIN(GPIOF_1),
+ MESON_PIN(GPIOF_2),
+ MESON_PIN(GPIOF_3),
+ MESON_PIN(GPIOF_4),
+ MESON_PIN(GPIOF_5),
+ MESON_PIN(GPIOF_6),
+ MESON_PIN(GPIOF_7),
+ MESON_PIN(GPIOF_8),
+ MESON_PIN(GPIOF_9),
+ MESON_PIN(GPIOF_10),
+ MESON_PIN(GPIOF_11),
+ MESON_PIN(GPIOF_12),
+ MESON_PIN(GPIOA_0),
+ MESON_PIN(GPIOA_1),
+ MESON_PIN(GPIOA_2),
+ MESON_PIN(GPIOA_3),
+ MESON_PIN(GPIOA_4),
+ MESON_PIN(GPIOA_5),
+ MESON_PIN(GPIOA_6),
+ MESON_PIN(GPIOA_7),
+ MESON_PIN(GPIOA_8),
+ MESON_PIN(GPIOA_9),
+ MESON_PIN(GPIOA_10),
+ MESON_PIN(GPIOA_11),
+};
+
+/* psram */
+static const unsigned int psram_clkn_pins[] = { GPIOP_0 };
+static const unsigned int psram_clkp_pins[] = { GPIOP_1 };
+static const unsigned int psram_ce_n_pins[] = { GPIOP_2 };
+static const unsigned int psram_rst_n_pins[] = { GPIOP_3 };
+static const unsigned int psram_adq0_pins[] = { GPIOP_4 };
+static const unsigned int psram_adq1_pins[] = { GPIOP_5 };
+static const unsigned int psram_adq2_pins[] = { GPIOP_6 };
+static const unsigned int psram_adq3_pins[] = { GPIOP_7 };
+static const unsigned int psram_adq4_pins[] = { GPIOP_8 };
+static const unsigned int psram_adq5_pins[] = { GPIOP_9 };
+static const unsigned int psram_adq6_pins[] = { GPIOP_10 };
+static const unsigned int psram_adq7_pins[] = { GPIOP_11 };
+static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 };
+
+/* sdcard */
+static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 };
+static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 };
+static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 };
+static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 };
+static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 };
+static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 };
+
+static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 };
+
+/* spif */
+static const unsigned int spif_mo_pins[] = { GPIOB_0 };
+static const unsigned int spif_mi_pins[] = { GPIOB_1 };
+static const unsigned int spif_wp_n_pins[] = { GPIOB_2 };
+static const unsigned int spif_hold_n_pins[] = { GPIOB_3 };
+static const unsigned int spif_clk_pins[] = { GPIOB_4 };
+static const unsigned int spif_cs_pins[] = { GPIOB_5 };
+
+/* i2c0 */
+static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 };
+static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 };
+static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 };
+static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 };
+
+/* i2c1 */
+static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 };
+static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 };
+static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 };
+static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 };
+
+/* i2c2 */
+static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 };
+static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 };
+static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 };
+static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 };
+static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 };
+static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 };
+static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 };
+static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 };
+
+/* i2c3 */
+static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 };
+static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 };
+static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 };
+static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 };
+
+/* i2c slave */
+static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 };
+static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 };
+static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 };
+static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 };
+
+/* uart_a */
+static const unsigned int uart_a_tx_pins[] = { GPIOX_11 };
+static const unsigned int uart_a_rx_pins[] = { GPIOX_12 };
+static const unsigned int uart_a_cts_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_rts_pins[] = { GPIOX_14 };
+
+/* uart_b */
+static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 };
+static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 };
+static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 };
+static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 };
+
+/* uart_c */
+static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 };
+static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 };
+static const unsigned int uart_c_cts_pins[] = { GPIOX_2 };
+static const unsigned int uart_c_rts_pins[] = { GPIOX_3 };
+static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 };
+static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 };
+
+/* pmw_a */
+static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 };
+static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 };
+static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 };
+static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 };
+static const unsigned int pwm_a_a_pins[] = { GPIOA_5 };
+
+/* pmw_b */
+static const unsigned int pwm_b_x_pins[] = { GPIOX_8 };
+static const unsigned int pwm_b_f_pins[] = { GPIOF_7 };
+static const unsigned int pwm_b_a_pins[] = { GPIOA_11 };
+
+/* pmw_c */
+static const unsigned int pwm_c_x_pins[] = { GPIOX_9 };
+static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 };
+static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 };
+static const unsigned int pwm_c_a_pins[] = { GPIOA_10 };
+
+/* pwm_d */
+static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 };
+static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 };
+static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 };
+static const unsigned int pwm_d_f_pins[] = { GPIOF_11 };
+
+/* pwm_e */
+static const unsigned int pwm_e_p_pins[] = { GPIOP_3 };
+static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 };
+static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 };
+static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 };
+static const unsigned int pwm_e_f_pins[] = { GPIOF_3 };
+static const unsigned int pwm_e_a_pins[] = { GPIOA_0 };
+
+/* pwm_f */
+static const unsigned int pwm_f_b_pins[] = { GPIOB_6 };
+static const unsigned int pwm_f_x_pins[] = { GPIOX_3 };
+static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 };
+static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 };
+
+/* pwm_a_hiz */
+static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 };
+static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 };
+static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 };
+
+/* pwm_b_hiz */
+static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 };
+
+/* pmw_c_hiz */
+static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 };
+
+/* tdm_a */
+static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 };
+static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 };
+static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 };
+static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 };
+
+/* spi_a */
+static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 };
+static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 };
+static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 };
+static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 };
+static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 };
+static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 };
+static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 };
+static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 };
+
+static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 };
+static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 };
+static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
+static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 };
+
+/* pdm */
+static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 };
+static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 };
+static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 };
+static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 };
+
+static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
+static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 };
+static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
+static const unsigned int pdm_dclk_pins[] = { GPIOA_9 };
+
+/* gen_clk */
+static const unsigned int gen_clk_x_pins[] = { GPIOX_7 };
+static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 };
+static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 };
+static const unsigned int gen_clk_a_pins[] = { GPIOA_11 };
+
+/* jtag_a */
+static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 };
+static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 };
+
+/* clk_32_in */
+static const unsigned int clk_32k_in_pins[] = { GPIOF_2 };
+
+/* ir in */
+static const unsigned int remote_input_f_pins[] = { GPIOF_3 };
+static const unsigned int remote_input_a_pins[] = { GPIOA_11 };
+
+/* ir out */
+static const unsigned int remote_out_pins[] = { GPIOF_5 };
+
+/* spdif */
+static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 };
+static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 };
+
+/* sw */
+static const unsigned int swclk_pins[] = { GPIOF_4 };
+static const unsigned int swdio_pins[] = { GPIOF_5 };
+
+/* clk_25 */
+static const unsigned int clk25_pins[] = { GPIOF_10 };
+
+/* cec_a */
+static const unsigned int cec_a_pins[] = { GPIOF_2 };
+
+/* cec_b */
+static const unsigned int cec_b_pins[] = { GPIOF_2 };
+
+/* clk12_24 */
+static const unsigned int clk12_24_pins[] = { GPIOF_10 };
+
+/* mclk_0 */
+static const unsigned int mclk_0_pins[] = { GPIOA_0 };
+
+/* tdm_b */
+static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
+static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
+static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
+static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
+static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
+static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 };
+static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 };
+static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 };
+static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 };
+static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 };
+static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 };
+
+/* mclk_vad */
+static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
+
+/* tdm_vad */
+static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
+static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
+static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
+static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
+
+/* tst_out */
+static const unsigned int tst_out0_pins[] = { GPIOA_0 };
+static const unsigned int tst_out1_pins[] = { GPIOA_1 };
+static const unsigned int tst_out2_pins[] = { GPIOA_2 };
+static const unsigned int tst_out3_pins[] = { GPIOA_3 };
+static const unsigned int tst_out4_pins[] = { GPIOA_4 };
+static const unsigned int tst_out5_pins[] = { GPIOA_5 };
+static const unsigned int tst_out6_pins[] = { GPIOA_6 };
+static const unsigned int tst_out7_pins[] = { GPIOA_7 };
+static const unsigned int tst_out8_pins[] = { GPIOA_8 };
+static const unsigned int tst_out9_pins[] = { GPIOA_9 };
+static const unsigned int tst_out10_pins[] = { GPIOA_10 };
+static const unsigned int tst_out11_pins[] = { GPIOA_11 };
+
+/* mute */
+static const unsigned int mute_key_pins[] = { GPIOA_4 };
+static const unsigned int mute_en_pins[] = { GPIOA_5 };
+
+static struct meson_pmx_group meson_a1_periphs_groups[] = {
+ GPIO_GROUP(GPIOP_0),
+ GPIO_GROUP(GPIOP_1),
+ GPIO_GROUP(GPIOP_2),
+ GPIO_GROUP(GPIOP_3),
+ GPIO_GROUP(GPIOP_4),
+ GPIO_GROUP(GPIOP_5),
+ GPIO_GROUP(GPIOP_6),
+ GPIO_GROUP(GPIOP_7),
+ GPIO_GROUP(GPIOP_8),
+ GPIO_GROUP(GPIOP_9),
+ GPIO_GROUP(GPIOP_10),
+ GPIO_GROUP(GPIOP_11),
+ GPIO_GROUP(GPIOP_12),
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOF_0),
+ GPIO_GROUP(GPIOF_1),
+ GPIO_GROUP(GPIOF_2),
+ GPIO_GROUP(GPIOF_3),
+ GPIO_GROUP(GPIOF_4),
+ GPIO_GROUP(GPIOF_5),
+ GPIO_GROUP(GPIOF_6),
+ GPIO_GROUP(GPIOF_7),
+ GPIO_GROUP(GPIOF_8),
+ GPIO_GROUP(GPIOF_9),
+ GPIO_GROUP(GPIOF_10),
+ GPIO_GROUP(GPIOF_11),
+ GPIO_GROUP(GPIOF_12),
+ GPIO_GROUP(GPIOA_0),
+ GPIO_GROUP(GPIOA_1),
+ GPIO_GROUP(GPIOA_2),
+ GPIO_GROUP(GPIOA_3),
+ GPIO_GROUP(GPIOA_4),
+ GPIO_GROUP(GPIOA_5),
+ GPIO_GROUP(GPIOA_6),
+ GPIO_GROUP(GPIOA_7),
+ GPIO_GROUP(GPIOA_8),
+ GPIO_GROUP(GPIOA_9),
+ GPIO_GROUP(GPIOA_10),
+ GPIO_GROUP(GPIOA_11),
+
+ /* bank P func1 */
+ GROUP(psram_clkn, 1),
+ GROUP(psram_clkp, 1),
+ GROUP(psram_ce_n, 1),
+ GROUP(psram_rst_n, 1),
+ GROUP(psram_adq0, 1),
+ GROUP(psram_adq1, 1),
+ GROUP(psram_adq2, 1),
+ GROUP(psram_adq3, 1),
+ GROUP(psram_adq4, 1),
+ GROUP(psram_adq5, 1),
+ GROUP(psram_adq6, 1),
+ GROUP(psram_adq7, 1),
+ GROUP(psram_dqs_dm, 1),
+
+ /*bank P func2 */
+ GROUP(pwm_e_p, 2),
+
+ /*bank B func1 */
+ GROUP(spif_mo, 1),
+ GROUP(spif_mi, 1),
+ GROUP(spif_wp_n, 1),
+ GROUP(spif_hold_n, 1),
+ GROUP(spif_clk, 1),
+ GROUP(spif_cs, 1),
+ GROUP(pwm_f_b, 1),
+
+ /*bank B func2 */
+ GROUP(sdcard_d0_b, 2),
+ GROUP(sdcard_d1_b, 2),
+ GROUP(sdcard_d2_b, 2),
+ GROUP(sdcard_d3_b, 2),
+ GROUP(sdcard_clk_b, 2),
+ GROUP(sdcard_cmd_b, 2),
+
+ /*bank X func1 */
+ GROUP(sdcard_d0_x, 1),
+ GROUP(sdcard_d1_x, 1),
+ GROUP(sdcard_d2_x, 1),
+ GROUP(sdcard_d3_x, 1),
+ GROUP(sdcard_clk_x, 1),
+ GROUP(sdcard_cmd_x, 1),
+ GROUP(pwm_a_x6, 1),
+ GROUP(tdm_a_dout1, 1),
+ GROUP(tdm_a_dout0, 1),
+ GROUP(tdm_a_fs, 1),
+ GROUP(tdm_a_sclk, 1),
+ GROUP(uart_a_tx, 1),
+ GROUP(uart_a_rx, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(pwm_d_x15, 1),
+ GROUP(pwm_e_x16, 1),
+
+ /*bank X func2 */
+ GROUP(i2c2_sck_x0, 2),
+ GROUP(i2c2_sda_x1, 2),
+ GROUP(spi_a_mosi_x2, 2),
+ GROUP(spi_a_ss0_x3, 2),
+ GROUP(spi_a_sclk_x4, 2),
+ GROUP(spi_a_miso_x5, 2),
+ GROUP(tdm_a_din1, 2),
+ GROUP(tdm_a_din0, 2),
+ GROUP(tdm_a_slv_fs, 2),
+ GROUP(tdm_a_slv_sclk, 2),
+ GROUP(i2c3_sck_x, 2),
+ GROUP(i2c3_sda_x, 2),
+ GROUP(pwm_d_x13, 2),
+ GROUP(pwm_e_x14, 2),
+ GROUP(i2c2_sck_x15, 2),
+ GROUP(i2c2_sda_x16, 2),
+
+ /*bank X func3 */
+ GROUP(uart_c_tx_x0, 3),
+ GROUP(uart_c_rx_x1, 3),
+ GROUP(uart_c_cts, 3),
+ GROUP(uart_c_rts, 3),
+ GROUP(pdm_din0_x, 3),
+ GROUP(pdm_din1_x, 3),
+ GROUP(pdm_din2_x, 3),
+ GROUP(pdm_dclk_x, 3),
+ GROUP(uart_c_tx_x15, 3),
+ GROUP(uart_c_rx_x16, 3),
+
+ /*bank X func4 */
+ GROUP(pwm_e_x2, 4),
+ GROUP(pwm_f_x, 4),
+ GROUP(spi_a_mosi_x7, 4),
+ GROUP(spi_a_miso_x8, 4),
+ GROUP(spi_a_ss0_x9, 4),
+ GROUP(spi_a_sclk_x10, 4),
+
+ /*bank X func5 */
+ GROUP(uart_b_tx_x, 5),
+ GROUP(uart_b_rx_x, 5),
+ GROUP(i2c1_sda_x, 5),
+ GROUP(i2c1_sck_x, 5),
+
+ /*bank X func6 */
+ GROUP(pwm_a_x7, 6),
+ GROUP(pwm_b_x, 6),
+ GROUP(pwm_c_x, 6),
+ GROUP(pwm_d_x10, 6),
+
+ /*bank X func7 */
+ GROUP(gen_clk_x, 7),
+
+ /*bank F func1 */
+ GROUP(uart_b_tx_f, 1),
+ GROUP(uart_b_rx_f, 1),
+ GROUP(remote_input_f, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_f8, 1),
+ GROUP(pwm_a_f10, 1),
+ GROUP(i2c0_sck_f11, 1),
+ GROUP(i2c0_sda_f12, 1),
+
+ /*bank F func2 */
+ GROUP(clk_32k_in, 2),
+ GROUP(pwm_e_f, 2),
+ GROUP(pwm_f_f4, 2),
+ GROUP(remote_out, 2),
+ GROUP(spdif_in_f6, 2),
+ GROUP(spdif_in_f7, 2),
+ GROUP(pwm_a_hiz_f8, 2),
+ GROUP(pwm_a_hiz_f10, 2),
+ GROUP(pwm_d_f, 2),
+ GROUP(pwm_f_f12, 2),
+
+ /*bank F func3 */
+ GROUP(pwm_c_f3, 3),
+ GROUP(swclk, 3),
+ GROUP(swdio, 3),
+ GROUP(pwm_a_f6, 3),
+ GROUP(pwm_b_f, 3),
+ GROUP(pwm_c_f8, 3),
+ GROUP(clk25, 3),
+ GROUP(i2c_slave_sck_f, 3),
+ GROUP(i2c_slave_sda_f, 3),
+
+ /*bank F func4 */
+ GROUP(cec_a, 4),
+ GROUP(i2c3_sck_f, 4),
+ GROUP(i2c3_sda_f, 4),
+ GROUP(pmw_a_hiz_f6, 4),
+ GROUP(pwm_b_hiz, 4),
+ GROUP(pwm_c_hiz, 4),
+ GROUP(i2c0_sck_f9, 4),
+ GROUP(i2c0_sda_f10, 4),
+
+ /*bank F func5 */
+ GROUP(cec_b, 5),
+ GROUP(clk12_24, 5),
+
+ /*bank F func7 */
+ GROUP(gen_clk_f10, 7),
+
+ /*bank A func1 */
+ GROUP(mclk_0, 1),
+ GROUP(tdm_b_sclk, 1),
+ GROUP(tdm_b_fs, 1),
+ GROUP(tdm_b_dout0, 1),
+ GROUP(tdm_b_dout1, 1),
+ GROUP(tdm_b_dout2, 1),
+ GROUP(tdm_b_dout3, 1),
+ GROUP(tdm_b_dout4, 1),
+ GROUP(tdm_b_dout5, 1),
+ GROUP(remote_input_a, 1),
+
+ /*bank A func2 */
+ GROUP(pwm_e_a, 2),
+ GROUP(tdm_b_slv_sclk, 2),
+ GROUP(tdm_b_slv_fs, 2),
+ GROUP(tdm_b_din0, 2),
+ GROUP(tdm_b_din1, 2),
+ GROUP(tdm_b_din2, 2),
+ GROUP(i2c1_sda_a, 2),
+ GROUP(i2c1_sck_a, 2),
+
+ /*bank A func3 */
+ GROUP(i2c2_sck_a4, 3),
+ GROUP(i2c2_sda_a5, 3),
+ GROUP(pdm_din2_a, 3),
+ GROUP(pdm_din1_a, 3),
+ GROUP(pdm_din0_a, 3),
+ GROUP(pdm_dclk, 3),
+ GROUP(pwm_c_a, 3),
+ GROUP(pwm_b_a, 3),
+
+ /*bank A func4 */
+ GROUP(pwm_a_a, 4),
+ GROUP(spi_a_mosi_a, 4),
+ GROUP(spi_a_miso_a, 4),
+ GROUP(spi_a_ss0_a, 4),
+ GROUP(spi_a_sclk_a, 4),
+ GROUP(i2c_slave_sck_a, 4),
+ GROUP(i2c_slave_sda_a, 4),
+
+ /*bank A func5 */
+ GROUP(mclk_vad, 5),
+ GROUP(tdm_vad_sclk_a1, 5),
+ GROUP(tdm_vad_fs_a2, 5),
+ GROUP(tdm_vad_sclk_a5, 5),
+ GROUP(tdm_vad_fs_a6, 5),
+ GROUP(i2c2_sck_a8, 5),
+ GROUP(i2c2_sda_a9, 5),
+
+ /*bank A func6 */
+ GROUP(tst_out0, 6),
+ GROUP(tst_out1, 6),
+ GROUP(tst_out2, 6),
+ GROUP(tst_out3, 6),
+ GROUP(tst_out4, 6),
+ GROUP(tst_out5, 6),
+ GROUP(tst_out6, 6),
+ GROUP(tst_out7, 6),
+ GROUP(tst_out8, 6),
+ GROUP(tst_out9, 6),
+ GROUP(tst_out10, 6),
+ GROUP(tst_out11, 6),
+
+ /*bank A func7 */
+ GROUP(mute_key, 7),
+ GROUP(mute_en, 7),
+ GROUP(gen_clk_a, 7),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
+ "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
+ "GPIOP_10", "GPIOP_11", "GPIOP_12",
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+ "GPIOB_5", "GPIOB_6",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16",
+
+ "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
+ "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
+ "GPIOF_10", "GPIOF_11", "GPIOF_12",
+
+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+ "GPIOA_10", "GPIOA_11",
+};
+
+static const char * const psram_groups[] = {
+ "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
+ "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
+ "psram_adq6", "psram_adq7", "psram_dqs_dm",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_x", "pwm_b_f", "pwm_b_a",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
+ "pwm_e_a",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
+};
+
+static const char * const pwm_a_hiz_groups[] = {
+ "pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6",
+};
+
+static const char * const pwm_b_hiz_groups[] = {
+ "pwm_b_hiz",
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+ "pwm_c_hiz",
+};
+
+static const char * const spif_groups[] = {
+ "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
+ "spif_cs",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
+ "sdcard_clk_b", "sdcard_cmd_b",
+
+ "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
+ "sdcard_clk_x", "sdcard_cmd_x",
+};
+
+static const char * const tdm_a_groups[] = {
+ "tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk",
+ "tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
+ "uart_c_tx_x15", "uart_c_rx_x16",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16",
+ "i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
+};
+
+static const char * const i2c_slave_groups[] = {
+ "i2c_slave_sda_a", "i2c_slave_sck_a",
+ "i2c_slave_sda_f", "i2c_slave_sck_f",
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
+ "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
+
+ "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
+ "pdm_din1_a", "pdm_din0_a", "pdm_dclk",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
+};
+
+static const char * const remote_input_groups[] = {
+ "remote_input_f",
+ "remote_input_a",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in",
+};
+
+static const char * const remote_out_groups[] = {
+ "remote_out",
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_f6", "spdif_in_f7",
+};
+
+static const char * const sw_groups[] = {
+ "swclk", "swdio",
+};
+
+static const char * const clk25_groups[] = {
+ "clk_25",
+};
+
+static const char * const cec_a_groups[] = {
+ "cec_a",
+};
+
+static const char * const cec_b_groups[] = {
+ "cec_b",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24",
+};
+
+static const char * const mclk_0_groups[] = {
+ "mclk_0",
+};
+
+static const char * const tdm_b_groups[] = {
+ "tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
+ "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
+ "tdm_b_slv_sclk", "tdm_b_slv_fs",
+};
+
+static const char * const mclk_vad_groups[] = {
+ "mclk_vad",
+};
+
+static const char * const tdm_vad_groups[] = {
+ "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
+};
+
+static const char * const tst_out_groups[] = {
+ "tst_out0", "tst_out1", "tst_out2", "tst_out3",
+ "tst_out4", "tst_out5", "tst_out6", "tst_out7",
+ "tst_out8", "tst_out9", "tst_out10", "tst_out11",
+};
+
+static const char * const mute_groups[] = {
+ "mute_key", "mute_en",
+};
+
+static struct meson_pmx_func meson_a1_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(psram),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_a_hiz),
+ FUNCTION(pwm_b_hiz),
+ FUNCTION(pwm_c_hiz),
+ FUNCTION(spif),
+ FUNCTION(sdcard),
+ FUNCTION(tdm_a),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(i2c0),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(spi_a),
+ FUNCTION(pdm),
+ FUNCTION(gen_clk),
+ FUNCTION(remote_input),
+ FUNCTION(jtag_a),
+ FUNCTION(clk_32k_in),
+ FUNCTION(remote_out),
+ FUNCTION(spdif_in),
+ FUNCTION(sw),
+ FUNCTION(clk25),
+ FUNCTION(cec_a),
+ FUNCTION(cec_b),
+ FUNCTION(clk12_24),
+ FUNCTION(mclk_0),
+ FUNCTION(tdm_b),
+ FUNCTION(mclk_vad),
+ FUNCTION(tdm_vad),
+ FUNCTION(tst_out),
+ FUNCTION(mute),
+};
+
+static struct meson_bank meson_a1_periphs_banks[] = {
+ /* name first last irq pullen pull dir out in ds*/
+ BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
+ 0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
+ BANK_DS("B", GPIOB_0, GPIOB_6, 13, 19, 0x13, 0, 0x14, 0,
+ 0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0),
+ BANK_DS("X", GPIOX_0, GPIOX_16, 20, 36, 0x23, 0, 0x24, 0,
+ 0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0),
+ BANK_DS("F", GPIOF_0, GPIOF_12, 37, 49, 0x33, 0, 0x34, 0,
+ 0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0),
+ BANK_DS("A", GPIOA_0, GPIOA_11, 50, 61, 0x43, 0, 0x44, 0,
+ 0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
+};
+
+static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
+ /* name first lask reg offset */
+ BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0),
+ BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0),
+ BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
+};
+
+static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
+ .pmx_banks = meson_a1_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
+};
+
+static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .pins = meson_a1_periphs_pins,
+ .groups = meson_a1_periphs_groups,
+ .funcs = meson_a1_periphs_functions,
+ .banks = meson_a1_periphs_banks,
+ .num_pins = ARRAY_SIZE(meson_a1_periphs_pins),
+ .num_groups = ARRAY_SIZE(meson_a1_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_a1_periphs_banks),
+ .pmx_ops = &meson_axg_pmx_ops,
+ .pmx_data = &meson_a1_periphs_pmx_banks_data,
+ .reg_layout = A1_LAYOUT,
+};
+
+static const struct of_device_id meson_a1_pinctrl_dt_match[] = {
+ {
+ .compatible = "amlogic,meson-a1-periphs-pinctrl",
+ .data = &meson_a1_periphs_pinctrl_data,
+ },
+ { },
+};
+
+static struct platform_driver meson_a1_pinctrl_driver = {
+ .probe = meson_pinctrl_probe,
+ .driver = {
+ .name = "meson-a1-pinctrl",
+ .of_match_table = meson_a1_pinctrl_dt_match,
+ },
+};
+
+builtin_platform_driver(meson_a1_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 8bba9d0..885b89d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -688,8 +688,12 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
if (IS_ERR(pc->reg_ds)) {
- dev_dbg(pc->dev, "ds registers not found - skipping\n");
- pc->reg_ds = NULL;
+ if (pc->data->reg_layout == A1_LAYOUT) {
+ pc->reg_ds = pc->reg_pullen;
+ } else {
+ dev_dbg(pc->dev, "ds registers not found - skipping\n");
+ pc->reg_ds = NULL;
+ }
}
return 0;
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index c696f32..3d0c58d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -80,6 +80,14 @@ enum meson_pinconf_drv {
};
/**
+ * enum meson_reg_layout - identify two types of reg layout
+ */
+enum meson_reg_layout {
+ LEGACY_LAYOUT,
+ A1_LAYOUT,
+};
+
+/**
* struct meson bank
*
* @name: bank name
@@ -114,6 +122,7 @@ struct meson_pinctrl_data {
unsigned int num_banks;
const struct pinmux_ops *pmx_ops;
void *pmx_data;
+ unsigned int reg_layout;
};
struct meson_pinctrl {
--
1.9.1
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^ permalink raw reply related
* [PATCH 3/3] arm64: dts: meson: a1: add pinctrl controller support
From: Qianggui Song @ 2019-09-17 6:07 UTC (permalink / raw)
To: Linus Walleij, linux-gpio
Cc: Qianggui Song, Mark Rutland, Hanjie Lin, Jianxin Pan,
Neil Armstrong, Martin Blumenstingl, Kevin Hilman, linux-kernel,
devicetree, Rob Herring, linux-arm-kernel, Carlo Caione,
linux-amlogic, Xingyu Chen, Jerome Brunet
In-Reply-To: <1568700442-18540-1-git-send-email-qianggui.song@amlogic.com>
add peripheral pinctrl controller to a1 soc
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..0965259 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/meson-a1-gpio.h>
/ {
compatible = "amlogic,a1";
@@ -74,6 +75,23 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+ periphs_pinctrl: pinctrl@0400 {
+ compatible = "amlogic,meson-a1-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@0400 {
+ reg = <0x0 0x0400 0x0 0x003c>,
+ <0x0 0x0480 0x0 0x0118>;
+ reg-names = "mux", "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 62>;
+ };
+
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
1.9.1
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* RE: [PATCH V3 0/4] clk: imx8m: fix glitch/mux
From: Peng Fan @ 2019-09-17 6:20 UTC (permalink / raw)
To: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com
Cc: Abel Vesa, Anson Huang, linux-kernel@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, Leonard Crestez,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Jacky Bai
In-Reply-To: <1568043491-20680-1-git-send-email-peng.fan@nxp.com>
Hi Stephen, Shawn,
> Subject: [PATCH V3 0/4] clk: imx8m: fix glitch/mux
Sorry to ping early. Is there a chance to land this patchset in 5.3 release?
Thanks,
Peng.
>
> From: Peng Fan <peng.fan@nxp.com>
>
> V3:
> Add cover-letter
>
> V2:
> Added patch [2,3,4]/4 and avoid glitch when prepare
>
> There is two bypass bit in the pll, BYPASS and EXT_BYPASS.
> There is also a restriction that to avoid glitch, need set BYPASS bit when
> RESETB changed from 0 to 1, otherwise there will be glitch.
>
> However the BYPASS bit is also used as mux bit in imx8mm/imx8mn clk driver.
>
> This means two paths touch the same bit which is wrong. So switch to use
> EXT_BYPASS bit as the mux.
>
> Peng Fan (4):
> clk: imx: pll14xx: avoid glitch when set rate
> clk: imx: clk-pll14xx: unbypass PLL by default
> clk: imx: imx8mm: fix pll mux bit
> clk: imx: imx8mn: fix pll mux bit
>
> drivers/clk/imx/clk-imx8mm.c | 32 ++++++++++----------------------
> drivers/clk/imx/clk-imx8mn.c | 32 ++++++++++----------------------
> drivers/clk/imx/clk-pll14xx.c | 27 ++++++++++++++++++++++++++-
> 3 files changed, 46 insertions(+), 45 deletions(-)
>
> --
> 2.16.4
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^ permalink raw reply
* Re: [PATCH v4 1/5] locking/qspinlock: Rename arch_mcs_spin_unlock_contended to arch_mcs_pass_lock and make it more generic
From: Hanjun Guo @ 2019-09-17 6:25 UTC (permalink / raw)
To: Alex Kogan, linux, peterz, mingo, will.deacon, arnd, longman,
linux-arch, linux-arm-kernel, linux-kernel, tglx, bp, hpa, x86,
jglauber
Cc: rahul.x.yadav, dave.dice, steven.sistare, daniel.m.jordan
In-Reply-To: <20190906142541.34061-2-alex.kogan@oracle.com>
Hi Alex,
On 2019/9/6 22:25, Alex Kogan wrote:
> The new macro should accept the value to be stored into the lock argument
> as another argument. This allows using the same macro in cases where the
> value to be stored when passing the lock is different from 1.
>
> Signed-off-by: Alex Kogan <alex.kogan@oracle.com>
> Reviewed-by: Steve Sistare <steven.sistare@oracle.com>
> ---
> arch/arm/include/asm/mcs_spinlock.h | 4 ++--
> kernel/locking/mcs_spinlock.h | 6 +++---
> kernel/locking/qspinlock.c | 2 +-
> 3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/include/asm/mcs_spinlock.h b/arch/arm/include/asm/mcs_spinlock.h
> index 529d2cf4d06f..f3f9efdcd2ca 100644
> --- a/arch/arm/include/asm/mcs_spinlock.h
> +++ b/arch/arm/include/asm/mcs_spinlock.h
> @@ -14,9 +14,9 @@ do { \
> wfe(); \
> } while (0) \
>
> -#define arch_mcs_spin_unlock_contended(lock) \
> +#define arch_mcs_pass_lock(lock, val) \
arch_mcs_spin_unlock_contended() has a matching function arch_mcs_spin_lock_contended(),
please see include/asm-generic/mcs_spinlock.h, so if we update this function name,
should we update the matching one as well? and update the relevant comments as well?
> do { \
> - smp_store_release(lock, 1); \
> + smp_store_release((lock), (val)); \
> dsb_sev(); \
> } while (0)
>
> diff --git a/kernel/locking/mcs_spinlock.h b/kernel/locking/mcs_spinlock.h
> index 5e10153b4d3c..84327ca21650 100644
> --- a/kernel/locking/mcs_spinlock.h
> +++ b/kernel/locking/mcs_spinlock.h
> @@ -41,8 +41,8 @@ do { \
> * operations in the critical section has been completed before
> * unlocking.
> */
> -#define arch_mcs_spin_unlock_contended(l) \
Before this line of the code, there is:
#ifndef arch_mcs_spin_lock_contended
...
#define arch_mcs_spin_lock_contended(l) \
So #ifndef should be updated too.
Thanks
Hanjun
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* [RESEND PATCH] mm/hugetlb: topdown mmap supports for hugepage
From: shile.zhang @ 2019-09-17 6:41 UTC (permalink / raw)
To: linux; +Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <VI1PR0701MB2846C892037A515D0B3F4EF8A12B0@VI1PR0701MB2846.eurprd07.prod.outlook.com>
From: Shile Zhang <shile.zhang@linux.alibaba.com>
Similar to other arches, this adds topdown mmap support for hugepage
in user process address space allocation. It allows mmap big size
hugepage. This patch copied from the implementation in arch/x86.
Signed-off-by: Shile Zhang <shile.zhang@linux.alibaba.com>
---
arch/arm/include/asm/page.h | 1 +
arch/arm/mm/hugetlbpage.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index c2b75cb..dcb4df5 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -141,6 +141,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
#ifdef CONFIG_KUSER_HELPERS
#define __HAVE_ARCH_GATE_AREA 1
+#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
#endif
#ifdef CONFIG_ARM_LPAE
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
index a1e5aac..ba9e151 100644
--- a/arch/arm/mm/hugetlbpage.c
+++ b/arch/arm/mm/hugetlbpage.c
@@ -33,3 +33,88 @@ int pmd_huge(pmd_t pmd)
{
return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
}
+
+#ifdef CONFIG_HUGETLB_PAGE
+static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *file,
+ unsigned long addr, unsigned long len,
+ unsigned long pgoff, unsigned long flags)
+{
+ struct hstate *h = hstate_file(file);
+ struct vm_unmapped_area_info info;
+
+ info.flags = 0;
+ info.length = len;
+ info.low_limit = current->mm->mmap_legacy_base;
+ info.high_limit = TASK_SIZE;
+ info.align_mask = PAGE_MASK & ~huge_page_mask(h);
+ info.align_offset = 0;
+ return vm_unmapped_area(&info);
+}
+
+static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file,
+ unsigned long addr0, unsigned long len,
+ unsigned long pgoff, unsigned long flags)
+{
+ struct hstate *h = hstate_file(file);
+ struct vm_unmapped_area_info info;
+ unsigned long addr;
+
+ info.flags = VM_UNMAPPED_AREA_TOPDOWN;
+ info.length = len;
+ info.low_limit = PAGE_SIZE;
+ info.high_limit = current->mm->mmap_base;
+ info.align_mask = PAGE_MASK & ~huge_page_mask(h);
+ info.align_offset = 0;
+ addr = vm_unmapped_area(&info);
+
+ /*
+ * A failed mmap() very likely causes application failure,
+ * so fall back to the bottom-up function here. This scenario
+ * can happen with large stack limits and large mmap()
+ * allocations.
+ */
+ if (addr & ~PAGE_MASK) {
+ VM_BUG_ON(addr != -ENOMEM);
+ info.flags = 0;
+ info.low_limit = TASK_UNMAPPED_BASE;
+ info.high_limit = TASK_SIZE;
+ addr = vm_unmapped_area(&info);
+ }
+
+ return addr;
+}
+
+unsigned long
+hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
+ unsigned long len, unsigned long pgoff, unsigned long flags)
+{
+ struct hstate *h = hstate_file(file);
+ struct mm_struct *mm = current->mm;
+ struct vm_area_struct *vma;
+
+ if (len & ~huge_page_mask(h))
+ return -EINVAL;
+ if (len > TASK_SIZE)
+ return -ENOMEM;
+
+ if (flags & MAP_FIXED) {
+ if (prepare_hugepage_range(file, addr, len))
+ return -EINVAL;
+ return addr;
+ }
+
+ if (addr) {
+ addr = ALIGN(addr, huge_page_size(h));
+ vma = find_vma(mm, addr);
+ if (TASK_SIZE - len >= addr &&
+ (!vma || addr + len <= vma->vm_start))
+ return addr;
+ }
+ if (mm->get_unmapped_area == arch_get_unmapped_area)
+ return hugetlb_get_unmapped_area_bottomup(file, addr, len,
+ pgoff, flags);
+ else
+ return hugetlb_get_unmapped_area_topdown(file, addr, len,
+ pgoff, flags);
+}
+#endif /* CONFIG_HUGETLB_PAGE */
--
1.8.3.1
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* Re: [linux-sunxi] [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
From: Chen-Yu Tsai @ 2019-09-17 6:54 UTC (permalink / raw)
To: Jernej Skrabec
Cc: Stephen Boyd, Mike Turquette, linux-kernel, Maxime Ripard,
linux-sunxi, linux-clk, linux-arm-kernel
In-Reply-To: <20190914135100.327412-1-jernej.skrabec@siol.net>
On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec <jernej.skrabec@siol.net> wrote:
>
> Audio devices needs exact clock rates in order to correctly reproduce
> the sound. Until now, only integer factors were used to configure H6
> audio PLL which resulted in inexact rates. Fix that by adding support
> for fractional factors using sigma-delta modulation look-up table. It
> contains values for two most commonly used audio base frequencies.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> index d89353a3cdec..ed6338d74474 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> @@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
> * hardcode it to match with the clock names.
> */
> #define SUN50I_H6_PLL_AUDIO_REG 0x078
> +
> +static struct ccu_sdm_setting pll_audio_sdm_table[] = {
> + { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
> + { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
> +};
> +
> static struct ccu_nm pll_audio_base_clk = {
> .enable = BIT(31),
> .lock = BIT(28),
> .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
> .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
> + .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
> + BIT(24), 0x178, BIT(31)),
> .common = {
> + .features = CCU_FEATURE_SIGMA_DELTA_MOD,
> .reg = 0x078,
> .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
> &ccu_nm_ops,
> @@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
> };
>
> /*
> - * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
> - * fixed post-divider 2.
> + * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
> + * rates can be set exactly in conjunction with sigma-delta modulation.
> */
> static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
> clk_parent_pll_audio,
> - 8, 1, CLK_SET_RATE_PARENT);
> + 24, 1, CLK_SET_RATE_PARENT);
> static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
> clk_parent_pll_audio,
> 4, 1, CLK_SET_RATE_PARENT);
You need to fix the factors for the other two outputs as well, since all
three are derived from pll-audio-base.
ChenYu
> @@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
> }
>
> /*
> - * Force the post-divider of pll-audio to 8 and the output divider
> - * of it to 1, to make the clock name represents the real frequency.
> + * Force the post-divider of pll-audio to 12 and the output divider
> + * of it to 2, so 24576000 and 22579200 rates can be set exactly.
> */
> val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
> val &= ~(GENMASK(21, 16) | BIT(0));
> - writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
> + writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
>
> /*
> * First clock parent (osc32K) is unusable for CEC. But since there
> --
> 2.23.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190914135100.327412-1-jernej.skrabec%40siol.net.
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* Re: [PATCH 0/6] ARM, arm64: Remove arm_pm_restart()
From: Arnd Bergmann @ 2019-09-17 7:01 UTC (permalink / raw)
To: Thierry Reding; +Cc: Linux ARM, linux-kernel@vger.kernel.org, Guenter Roeck
In-Reply-To: <20190916202809.GA42800@mithrandir>
On Mon, Sep 16, 2019 at 10:28 PM Thierry Reding
<thierry.reding@gmail.com> wrote:
>
> All of the patches beyond the 6 in this set rely on the system reset and
> power "framework". I don't think there was broad concensus on that idea
> yet.
Ok, I see.
> If you think it's worth another try I'm happy to send the patches
> out again.
Maybe do that after we pull the first set into arm-soc then. If
we can reach consensus, I can merge them as a follow-up,
either through the soc tree as a new subsystem or through
the asm-generic tree as cross-architecture work.
Arnd
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* [PATCH v2] Documentation: document earlycon without options for more platforms
From: Christoph Hellwig @ 2019-09-17 7:15 UTC (permalink / raw)
To: corbet; +Cc: schwab, linux-arm-kernel, linux-doc
The earlycon options without arguments is supposed to work on all
device tree platforms, not just arm64.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
Changes since v1:
- add comma, fix typo
Documentation/admin-guide/kernel-parameters.txt | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 4c1971960afa..d5956c29b93b 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -977,12 +977,10 @@
earlycon= [KNL] Output early console device and options.
- [ARM64] The early console is determined by the
- stdout-path property in device tree's chosen node,
- or determined by the ACPI SPCR table.
-
- [X86] When used with no options the early console is
- determined by the ACPI SPCR table.
+ When used with no options, the early console is
+ determined by stdout-path property in device tree's
+ chosen node or the ACPI SPCR table if supported by
+ the platform.
cdns,<addr>[,options]
Start an early, polled-mode console on a Cadence
--
2.20.1
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* Re: [PATCH 2/3] pinctrl: meson-a1: add pinctrl driver for Meson A1 Soc
From: Neil Armstrong @ 2019-09-17 7:15 UTC (permalink / raw)
To: Qianggui Song, Linus Walleij, linux-gpio
Cc: Mark Rutland, Hanjie Lin, Jianxin Pan, Martin Blumenstingl,
Kevin Hilman, linux-kernel, Rob Herring, linux-arm-kernel,
Carlo Caione, linux-amlogic, Xingyu Chen, Jerome Brunet
In-Reply-To: <1568700442-18540-3-git-send-email-qianggui.song@amlogic.com>
Hi,
On 17/09/2019 08:07, Qianggui Song wrote:
> Add pinctrl driver for Meson A1 Soc which share the same register layout of
> pinmux with previous Meson-G12A, however there is difference for gpio
> and pin config register in A1. The register layout is as below:
>
> /* first bank */ /* addr */
> - P_PADCTRL_GPIOP_I base + 0x00 << 2
> - P_PADCTRL_GPIOP_O base + 0x01 << 2
> - P_PADCTRL_GPIOP_OEN base + 0x02 << 2
> - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2
> - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2
> - P_PADCTRL_GPIOP_DS base + 0x05 << 2
>
> /* second bank */
> - P_PADCTRL_GPIOB_I base + 0x10 << 2
> - P_PADCTRL_GPIOB_O base + 0x11 << 2
> - P_PADCTRL_GPIOB_OEN base + 0x12 << 2
> - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2
> - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2
> - P_PADCTRL_GPIOB_DS base + 0x15 << 2
>
> Each bank contains at least 6 registers to be configured, if one bank has
> more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between
> two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say,
> for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24,0x25 according
> to above register layout.
Sorry but the explanation is not very clear, could you show the G12A mapping
in comparison to explain your point and how reg_ds = reg_pullen solves the issue
here ?
>
> Current Meson pinctrl driver can cover such change by using base address of
> GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
> make wrong value to reg_ds for Soc that not support drive-strength like AXG
> . Here a private data used to identify register layout is introduced.
Could you also precise there is no AO pinctrl bank on A1.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
> drivers/pinctrl/meson/Kconfig | 6 +
> drivers/pinctrl/meson/Makefile | 1 +
> drivers/pinctrl/meson/pinctrl-meson-a1.c | 942 +++++++++++++++++++++++++++++++
> drivers/pinctrl/meson/pinctrl-meson.c | 8 +-
> drivers/pinctrl/meson/pinctrl-meson.h | 9 +
> 5 files changed, 964 insertions(+), 2 deletions(-)
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson-a1.c
>
> diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
> index df55f61..3cb1191 100644
> --- a/drivers/pinctrl/meson/Kconfig
> +++ b/drivers/pinctrl/meson/Kconfig
> @@ -54,4 +54,10 @@ config PINCTRL_MESON_G12A
> select PINCTRL_MESON_AXG_PMX
> default y
>
> +config PINCTRL_MESON_A1
> + bool "Meson a1 Soc pinctrl driver"
> + depends on ARM64
> + select PINCTRL_MESON_AXG_PMX
> + default y
> +
> endif
> diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
> index a69c565..1a5bffe 100644
> --- a/drivers/pinctrl/meson/Makefile
> +++ b/drivers/pinctrl/meson/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
> obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
> obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
> obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
> +obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c
> new file mode 100644
> index 0000000..f3a88f1
> --- /dev/null
> +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
> @@ -0,0 +1,942 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Pin controller and GPIO driver for Amlogic Meson A1 SoC.
> + *
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Qianggui Song <qianggui.song@amlogic.com>
> + */
> +
> +#include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include "pinctrl-meson.h"
> +#include "pinctrl-meson-axg-pmx.h"
> +
> +static const struct pinctrl_pin_desc meson_a1_periphs_pins[] = {
> + MESON_PIN(GPIOP_0),
> + MESON_PIN(GPIOP_1),
> + MESON_PIN(GPIOP_2),
> + MESON_PIN(GPIOP_3),
> + MESON_PIN(GPIOP_4),
> + MESON_PIN(GPIOP_5),
> + MESON_PIN(GPIOP_6),
> + MESON_PIN(GPIOP_7),
> + MESON_PIN(GPIOP_8),
> + MESON_PIN(GPIOP_9),
> + MESON_PIN(GPIOP_10),
> + MESON_PIN(GPIOP_11),
> + MESON_PIN(GPIOP_12),
> + MESON_PIN(GPIOB_0),
> + MESON_PIN(GPIOB_1),
> + MESON_PIN(GPIOB_2),
> + MESON_PIN(GPIOB_3),
> + MESON_PIN(GPIOB_4),
> + MESON_PIN(GPIOB_5),
> + MESON_PIN(GPIOB_6),
> + MESON_PIN(GPIOX_0),
> + MESON_PIN(GPIOX_1),
> + MESON_PIN(GPIOX_2),
> + MESON_PIN(GPIOX_3),
> + MESON_PIN(GPIOX_4),
> + MESON_PIN(GPIOX_5),
> + MESON_PIN(GPIOX_6),
> + MESON_PIN(GPIOX_7),
> + MESON_PIN(GPIOX_8),
> + MESON_PIN(GPIOX_9),
> + MESON_PIN(GPIOX_10),
> + MESON_PIN(GPIOX_11),
> + MESON_PIN(GPIOX_12),
> + MESON_PIN(GPIOX_13),
> + MESON_PIN(GPIOX_14),
> + MESON_PIN(GPIOX_15),
> + MESON_PIN(GPIOX_16),
> + MESON_PIN(GPIOF_0),
> + MESON_PIN(GPIOF_1),
> + MESON_PIN(GPIOF_2),
> + MESON_PIN(GPIOF_3),
> + MESON_PIN(GPIOF_4),
> + MESON_PIN(GPIOF_5),
> + MESON_PIN(GPIOF_6),
> + MESON_PIN(GPIOF_7),
> + MESON_PIN(GPIOF_8),
> + MESON_PIN(GPIOF_9),
> + MESON_PIN(GPIOF_10),
> + MESON_PIN(GPIOF_11),
> + MESON_PIN(GPIOF_12),
> + MESON_PIN(GPIOA_0),
> + MESON_PIN(GPIOA_1),
> + MESON_PIN(GPIOA_2),
> + MESON_PIN(GPIOA_3),
> + MESON_PIN(GPIOA_4),
> + MESON_PIN(GPIOA_5),
> + MESON_PIN(GPIOA_6),
> + MESON_PIN(GPIOA_7),
> + MESON_PIN(GPIOA_8),
> + MESON_PIN(GPIOA_9),
> + MESON_PIN(GPIOA_10),
> + MESON_PIN(GPIOA_11),
> +};
> +
> +/* psram */
> +static const unsigned int psram_clkn_pins[] = { GPIOP_0 };
> +static const unsigned int psram_clkp_pins[] = { GPIOP_1 };
> +static const unsigned int psram_ce_n_pins[] = { GPIOP_2 };
> +static const unsigned int psram_rst_n_pins[] = { GPIOP_3 };
> +static const unsigned int psram_adq0_pins[] = { GPIOP_4 };
> +static const unsigned int psram_adq1_pins[] = { GPIOP_5 };
> +static const unsigned int psram_adq2_pins[] = { GPIOP_6 };
> +static const unsigned int psram_adq3_pins[] = { GPIOP_7 };
> +static const unsigned int psram_adq4_pins[] = { GPIOP_8 };
> +static const unsigned int psram_adq5_pins[] = { GPIOP_9 };
> +static const unsigned int psram_adq6_pins[] = { GPIOP_10 };
> +static const unsigned int psram_adq7_pins[] = { GPIOP_11 };
> +static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 };
> +
> +/* sdcard */
> +static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 };
> +static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 };
> +static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 };
> +static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 };
> +static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 };
> +static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 };
> +
> +static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
> +static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
> +static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
> +static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
> +static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
> +static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 };
> +
> +/* spif */
> +static const unsigned int spif_mo_pins[] = { GPIOB_0 };
> +static const unsigned int spif_mi_pins[] = { GPIOB_1 };
> +static const unsigned int spif_wp_n_pins[] = { GPIOB_2 };
> +static const unsigned int spif_hold_n_pins[] = { GPIOB_3 };
> +static const unsigned int spif_clk_pins[] = { GPIOB_4 };
> +static const unsigned int spif_cs_pins[] = { GPIOB_5 };
> +
> +/* i2c0 */
> +static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 };
> +static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 };
> +static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 };
> +static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 };
> +
> +/* i2c1 */
> +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 };
> +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 };
> +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 };
> +static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 };
> +
> +/* i2c2 */
> +static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 };
> +static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 };
> +static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 };
> +static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 };
> +static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 };
> +static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 };
> +static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 };
> +static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 };
> +
> +/* i2c3 */
> +static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 };
> +static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 };
> +static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 };
> +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 };
> +
> +/* i2c slave */
> +static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 };
> +static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 };
> +static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 };
> +static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 };
> +
> +/* uart_a */
> +static const unsigned int uart_a_tx_pins[] = { GPIOX_11 };
> +static const unsigned int uart_a_rx_pins[] = { GPIOX_12 };
> +static const unsigned int uart_a_cts_pins[] = { GPIOX_13 };
> +static const unsigned int uart_a_rts_pins[] = { GPIOX_14 };
> +
> +/* uart_b */
> +static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 };
> +static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 };
> +static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 };
> +static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 };
> +
> +/* uart_c */
> +static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 };
> +static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 };
> +static const unsigned int uart_c_cts_pins[] = { GPIOX_2 };
> +static const unsigned int uart_c_rts_pins[] = { GPIOX_3 };
> +static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 };
> +static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 };
> +
> +/* pmw_a */
> +static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 };
> +static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 };
> +static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 };
> +static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 };
> +static const unsigned int pwm_a_a_pins[] = { GPIOA_5 };
> +
> +/* pmw_b */
> +static const unsigned int pwm_b_x_pins[] = { GPIOX_8 };
> +static const unsigned int pwm_b_f_pins[] = { GPIOF_7 };
> +static const unsigned int pwm_b_a_pins[] = { GPIOA_11 };
> +
> +/* pmw_c */
> +static const unsigned int pwm_c_x_pins[] = { GPIOX_9 };
> +static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 };
> +static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 };
> +static const unsigned int pwm_c_a_pins[] = { GPIOA_10 };
> +
> +/* pwm_d */
> +static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 };
> +static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 };
> +static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 };
> +static const unsigned int pwm_d_f_pins[] = { GPIOF_11 };
> +
> +/* pwm_e */
> +static const unsigned int pwm_e_p_pins[] = { GPIOP_3 };
> +static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 };
> +static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 };
> +static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 };
> +static const unsigned int pwm_e_f_pins[] = { GPIOF_3 };
> +static const unsigned int pwm_e_a_pins[] = { GPIOA_0 };
> +
> +/* pwm_f */
> +static const unsigned int pwm_f_b_pins[] = { GPIOB_6 };
> +static const unsigned int pwm_f_x_pins[] = { GPIOX_3 };
> +static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 };
> +static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 };
> +
> +/* pwm_a_hiz */
> +static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 };
> +static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 };
> +static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 };
> +
> +/* pwm_b_hiz */
> +static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 };
> +
> +/* pmw_c_hiz */
> +static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 };
> +
> +/* tdm_a */
> +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 };
> +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 };
> +static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 };
> +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 };
> +static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 };
> +static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 };
> +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 };
> +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 };
> +
> +/* spi_a */
> +static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 };
> +static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 };
> +static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 };
> +static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 };
> +static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 };
> +static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 };
> +static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 };
> +static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 };
> +
> +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 };
> +static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 };
> +static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
> +static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 };
> +
> +/* pdm */
> +static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 };
> +static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 };
> +static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 };
> +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 };
> +
> +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
> +static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 };
> +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
> +static const unsigned int pdm_dclk_pins[] = { GPIOA_9 };
> +
> +/* gen_clk */
> +static const unsigned int gen_clk_x_pins[] = { GPIOX_7 };
> +static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 };
> +static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 };
> +static const unsigned int gen_clk_a_pins[] = { GPIOA_11 };
> +
> +/* jtag_a */
> +static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 };
> +static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 };
> +static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 };
> +static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 };
> +
> +/* clk_32_in */
> +static const unsigned int clk_32k_in_pins[] = { GPIOF_2 };
> +
> +/* ir in */
> +static const unsigned int remote_input_f_pins[] = { GPIOF_3 };
> +static const unsigned int remote_input_a_pins[] = { GPIOA_11 };
> +
> +/* ir out */
> +static const unsigned int remote_out_pins[] = { GPIOF_5 };
> +
> +/* spdif */
> +static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 };
> +static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 };
> +
> +/* sw */
> +static const unsigned int swclk_pins[] = { GPIOF_4 };
> +static const unsigned int swdio_pins[] = { GPIOF_5 };
> +
> +/* clk_25 */
> +static const unsigned int clk25_pins[] = { GPIOF_10 };
> +
> +/* cec_a */
> +static const unsigned int cec_a_pins[] = { GPIOF_2 };
> +
> +/* cec_b */
> +static const unsigned int cec_b_pins[] = { GPIOF_2 };
> +
> +/* clk12_24 */
> +static const unsigned int clk12_24_pins[] = { GPIOF_10 };
> +
> +/* mclk_0 */
> +static const unsigned int mclk_0_pins[] = { GPIOA_0 };
> +
> +/* tdm_b */
> +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
> +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
> +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
> +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
> +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
> +static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
> +static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 };
> +static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 };
> +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 };
> +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 };
> +static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 };
> +static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 };
> +static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 };
> +
> +/* mclk_vad */
> +static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
> +
> +/* tdm_vad */
> +static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
> +static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
> +static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
> +static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
> +
> +/* tst_out */
> +static const unsigned int tst_out0_pins[] = { GPIOA_0 };
> +static const unsigned int tst_out1_pins[] = { GPIOA_1 };
> +static const unsigned int tst_out2_pins[] = { GPIOA_2 };
> +static const unsigned int tst_out3_pins[] = { GPIOA_3 };
> +static const unsigned int tst_out4_pins[] = { GPIOA_4 };
> +static const unsigned int tst_out5_pins[] = { GPIOA_5 };
> +static const unsigned int tst_out6_pins[] = { GPIOA_6 };
> +static const unsigned int tst_out7_pins[] = { GPIOA_7 };
> +static const unsigned int tst_out8_pins[] = { GPIOA_8 };
> +static const unsigned int tst_out9_pins[] = { GPIOA_9 };
> +static const unsigned int tst_out10_pins[] = { GPIOA_10 };
> +static const unsigned int tst_out11_pins[] = { GPIOA_11 };
> +
> +/* mute */
> +static const unsigned int mute_key_pins[] = { GPIOA_4 };
> +static const unsigned int mute_en_pins[] = { GPIOA_5 };
> +
> +static struct meson_pmx_group meson_a1_periphs_groups[] = {
> + GPIO_GROUP(GPIOP_0),
> + GPIO_GROUP(GPIOP_1),
> + GPIO_GROUP(GPIOP_2),
> + GPIO_GROUP(GPIOP_3),
> + GPIO_GROUP(GPIOP_4),
> + GPIO_GROUP(GPIOP_5),
> + GPIO_GROUP(GPIOP_6),
> + GPIO_GROUP(GPIOP_7),
> + GPIO_GROUP(GPIOP_8),
> + GPIO_GROUP(GPIOP_9),
> + GPIO_GROUP(GPIOP_10),
> + GPIO_GROUP(GPIOP_11),
> + GPIO_GROUP(GPIOP_12),
> + GPIO_GROUP(GPIOB_0),
> + GPIO_GROUP(GPIOB_1),
> + GPIO_GROUP(GPIOB_2),
> + GPIO_GROUP(GPIOB_3),
> + GPIO_GROUP(GPIOB_4),
> + GPIO_GROUP(GPIOB_5),
> + GPIO_GROUP(GPIOB_6),
> + GPIO_GROUP(GPIOX_0),
> + GPIO_GROUP(GPIOX_1),
> + GPIO_GROUP(GPIOX_2),
> + GPIO_GROUP(GPIOX_3),
> + GPIO_GROUP(GPIOX_4),
> + GPIO_GROUP(GPIOX_5),
> + GPIO_GROUP(GPIOX_6),
> + GPIO_GROUP(GPIOX_7),
> + GPIO_GROUP(GPIOX_8),
> + GPIO_GROUP(GPIOX_9),
> + GPIO_GROUP(GPIOX_10),
> + GPIO_GROUP(GPIOX_11),
> + GPIO_GROUP(GPIOX_12),
> + GPIO_GROUP(GPIOX_13),
> + GPIO_GROUP(GPIOX_14),
> + GPIO_GROUP(GPIOX_15),
> + GPIO_GROUP(GPIOX_16),
> + GPIO_GROUP(GPIOF_0),
> + GPIO_GROUP(GPIOF_1),
> + GPIO_GROUP(GPIOF_2),
> + GPIO_GROUP(GPIOF_3),
> + GPIO_GROUP(GPIOF_4),
> + GPIO_GROUP(GPIOF_5),
> + GPIO_GROUP(GPIOF_6),
> + GPIO_GROUP(GPIOF_7),
> + GPIO_GROUP(GPIOF_8),
> + GPIO_GROUP(GPIOF_9),
> + GPIO_GROUP(GPIOF_10),
> + GPIO_GROUP(GPIOF_11),
> + GPIO_GROUP(GPIOF_12),
> + GPIO_GROUP(GPIOA_0),
> + GPIO_GROUP(GPIOA_1),
> + GPIO_GROUP(GPIOA_2),
> + GPIO_GROUP(GPIOA_3),
> + GPIO_GROUP(GPIOA_4),
> + GPIO_GROUP(GPIOA_5),
> + GPIO_GROUP(GPIOA_6),
> + GPIO_GROUP(GPIOA_7),
> + GPIO_GROUP(GPIOA_8),
> + GPIO_GROUP(GPIOA_9),
> + GPIO_GROUP(GPIOA_10),
> + GPIO_GROUP(GPIOA_11),
> +
> + /* bank P func1 */
> + GROUP(psram_clkn, 1),
> + GROUP(psram_clkp, 1),
> + GROUP(psram_ce_n, 1),
> + GROUP(psram_rst_n, 1),
> + GROUP(psram_adq0, 1),
> + GROUP(psram_adq1, 1),
> + GROUP(psram_adq2, 1),
> + GROUP(psram_adq3, 1),
> + GROUP(psram_adq4, 1),
> + GROUP(psram_adq5, 1),
> + GROUP(psram_adq6, 1),
> + GROUP(psram_adq7, 1),
> + GROUP(psram_dqs_dm, 1),
> +
> + /*bank P func2 */
> + GROUP(pwm_e_p, 2),
> +
> + /*bank B func1 */
> + GROUP(spif_mo, 1),
> + GROUP(spif_mi, 1),
> + GROUP(spif_wp_n, 1),
> + GROUP(spif_hold_n, 1),
> + GROUP(spif_clk, 1),
> + GROUP(spif_cs, 1),
> + GROUP(pwm_f_b, 1),
> +
> + /*bank B func2 */
> + GROUP(sdcard_d0_b, 2),
> + GROUP(sdcard_d1_b, 2),
> + GROUP(sdcard_d2_b, 2),
> + GROUP(sdcard_d3_b, 2),
> + GROUP(sdcard_clk_b, 2),
> + GROUP(sdcard_cmd_b, 2),
> +
> + /*bank X func1 */
> + GROUP(sdcard_d0_x, 1),
> + GROUP(sdcard_d1_x, 1),
> + GROUP(sdcard_d2_x, 1),
> + GROUP(sdcard_d3_x, 1),
> + GROUP(sdcard_clk_x, 1),
> + GROUP(sdcard_cmd_x, 1),
> + GROUP(pwm_a_x6, 1),
> + GROUP(tdm_a_dout1, 1),
> + GROUP(tdm_a_dout0, 1),
> + GROUP(tdm_a_fs, 1),
> + GROUP(tdm_a_sclk, 1),
> + GROUP(uart_a_tx, 1),
> + GROUP(uart_a_rx, 1),
> + GROUP(uart_a_cts, 1),
> + GROUP(uart_a_rts, 1),
> + GROUP(pwm_d_x15, 1),
> + GROUP(pwm_e_x16, 1),
> +
> + /*bank X func2 */
> + GROUP(i2c2_sck_x0, 2),
> + GROUP(i2c2_sda_x1, 2),
> + GROUP(spi_a_mosi_x2, 2),
> + GROUP(spi_a_ss0_x3, 2),
> + GROUP(spi_a_sclk_x4, 2),
> + GROUP(spi_a_miso_x5, 2),
> + GROUP(tdm_a_din1, 2),
> + GROUP(tdm_a_din0, 2),
> + GROUP(tdm_a_slv_fs, 2),
> + GROUP(tdm_a_slv_sclk, 2),
> + GROUP(i2c3_sck_x, 2),
> + GROUP(i2c3_sda_x, 2),
> + GROUP(pwm_d_x13, 2),
> + GROUP(pwm_e_x14, 2),
> + GROUP(i2c2_sck_x15, 2),
> + GROUP(i2c2_sda_x16, 2),
> +
> + /*bank X func3 */
> + GROUP(uart_c_tx_x0, 3),
> + GROUP(uart_c_rx_x1, 3),
> + GROUP(uart_c_cts, 3),
> + GROUP(uart_c_rts, 3),
> + GROUP(pdm_din0_x, 3),
> + GROUP(pdm_din1_x, 3),
> + GROUP(pdm_din2_x, 3),
> + GROUP(pdm_dclk_x, 3),
> + GROUP(uart_c_tx_x15, 3),
> + GROUP(uart_c_rx_x16, 3),
> +
> + /*bank X func4 */
> + GROUP(pwm_e_x2, 4),
> + GROUP(pwm_f_x, 4),
> + GROUP(spi_a_mosi_x7, 4),
> + GROUP(spi_a_miso_x8, 4),
> + GROUP(spi_a_ss0_x9, 4),
> + GROUP(spi_a_sclk_x10, 4),
> +
> + /*bank X func5 */
> + GROUP(uart_b_tx_x, 5),
> + GROUP(uart_b_rx_x, 5),
> + GROUP(i2c1_sda_x, 5),
> + GROUP(i2c1_sck_x, 5),
> +
> + /*bank X func6 */
> + GROUP(pwm_a_x7, 6),
> + GROUP(pwm_b_x, 6),
> + GROUP(pwm_c_x, 6),
> + GROUP(pwm_d_x10, 6),
> +
> + /*bank X func7 */
> + GROUP(gen_clk_x, 7),
> +
> + /*bank F func1 */
> + GROUP(uart_b_tx_f, 1),
> + GROUP(uart_b_rx_f, 1),
> + GROUP(remote_input_f, 1),
> + GROUP(jtag_a_clk, 1),
> + GROUP(jtag_a_tms, 1),
> + GROUP(jtag_a_tdi, 1),
> + GROUP(jtag_a_tdo, 1),
> + GROUP(gen_clk_f8, 1),
> + GROUP(pwm_a_f10, 1),
> + GROUP(i2c0_sck_f11, 1),
> + GROUP(i2c0_sda_f12, 1),
> +
> + /*bank F func2 */
> + GROUP(clk_32k_in, 2),
> + GROUP(pwm_e_f, 2),
> + GROUP(pwm_f_f4, 2),
> + GROUP(remote_out, 2),
> + GROUP(spdif_in_f6, 2),
> + GROUP(spdif_in_f7, 2),
> + GROUP(pwm_a_hiz_f8, 2),
> + GROUP(pwm_a_hiz_f10, 2),
> + GROUP(pwm_d_f, 2),
> + GROUP(pwm_f_f12, 2),
> +
> + /*bank F func3 */
> + GROUP(pwm_c_f3, 3),
> + GROUP(swclk, 3),
> + GROUP(swdio, 3),
> + GROUP(pwm_a_f6, 3),
> + GROUP(pwm_b_f, 3),
> + GROUP(pwm_c_f8, 3),
> + GROUP(clk25, 3),
> + GROUP(i2c_slave_sck_f, 3),
> + GROUP(i2c_slave_sda_f, 3),
> +
> + /*bank F func4 */
> + GROUP(cec_a, 4),
> + GROUP(i2c3_sck_f, 4),
> + GROUP(i2c3_sda_f, 4),
> + GROUP(pmw_a_hiz_f6, 4),
> + GROUP(pwm_b_hiz, 4),
> + GROUP(pwm_c_hiz, 4),
> + GROUP(i2c0_sck_f9, 4),
> + GROUP(i2c0_sda_f10, 4),
> +
> + /*bank F func5 */
> + GROUP(cec_b, 5),
> + GROUP(clk12_24, 5),
> +
> + /*bank F func7 */
> + GROUP(gen_clk_f10, 7),
> +
> + /*bank A func1 */
> + GROUP(mclk_0, 1),
> + GROUP(tdm_b_sclk, 1),
> + GROUP(tdm_b_fs, 1),
> + GROUP(tdm_b_dout0, 1),
> + GROUP(tdm_b_dout1, 1),
> + GROUP(tdm_b_dout2, 1),
> + GROUP(tdm_b_dout3, 1),
> + GROUP(tdm_b_dout4, 1),
> + GROUP(tdm_b_dout5, 1),
> + GROUP(remote_input_a, 1),
> +
> + /*bank A func2 */
> + GROUP(pwm_e_a, 2),
> + GROUP(tdm_b_slv_sclk, 2),
> + GROUP(tdm_b_slv_fs, 2),
> + GROUP(tdm_b_din0, 2),
> + GROUP(tdm_b_din1, 2),
> + GROUP(tdm_b_din2, 2),
> + GROUP(i2c1_sda_a, 2),
> + GROUP(i2c1_sck_a, 2),
> +
> + /*bank A func3 */
> + GROUP(i2c2_sck_a4, 3),
> + GROUP(i2c2_sda_a5, 3),
> + GROUP(pdm_din2_a, 3),
> + GROUP(pdm_din1_a, 3),
> + GROUP(pdm_din0_a, 3),
> + GROUP(pdm_dclk, 3),
> + GROUP(pwm_c_a, 3),
> + GROUP(pwm_b_a, 3),
> +
> + /*bank A func4 */
> + GROUP(pwm_a_a, 4),
> + GROUP(spi_a_mosi_a, 4),
> + GROUP(spi_a_miso_a, 4),
> + GROUP(spi_a_ss0_a, 4),
> + GROUP(spi_a_sclk_a, 4),
> + GROUP(i2c_slave_sck_a, 4),
> + GROUP(i2c_slave_sda_a, 4),
> +
> + /*bank A func5 */
> + GROUP(mclk_vad, 5),
> + GROUP(tdm_vad_sclk_a1, 5),
> + GROUP(tdm_vad_fs_a2, 5),
> + GROUP(tdm_vad_sclk_a5, 5),
> + GROUP(tdm_vad_fs_a6, 5),
> + GROUP(i2c2_sck_a8, 5),
> + GROUP(i2c2_sda_a9, 5),
> +
> + /*bank A func6 */
> + GROUP(tst_out0, 6),
> + GROUP(tst_out1, 6),
> + GROUP(tst_out2, 6),
> + GROUP(tst_out3, 6),
> + GROUP(tst_out4, 6),
> + GROUP(tst_out5, 6),
> + GROUP(tst_out6, 6),
> + GROUP(tst_out7, 6),
> + GROUP(tst_out8, 6),
> + GROUP(tst_out9, 6),
> + GROUP(tst_out10, 6),
> + GROUP(tst_out11, 6),
> +
> + /*bank A func7 */
> + GROUP(mute_key, 7),
> + GROUP(mute_en, 7),
> + GROUP(gen_clk_a, 7),
> +};
> +
> +static const char * const gpio_periphs_groups[] = {
> + "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
> + "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
> + "GPIOP_10", "GPIOP_11", "GPIOP_12",
> +
> + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
> + "GPIOB_5", "GPIOB_6",
> +
> + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
> + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
> + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
> + "GPIOX_15", "GPIOX_16",
> +
> + "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
> + "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
> + "GPIOF_10", "GPIOF_11", "GPIOF_12",
> +
> + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
> + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
> + "GPIOA_10", "GPIOA_11",
> +};
> +
> +static const char * const psram_groups[] = {
> + "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
> + "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
> + "psram_adq6", "psram_adq7", "psram_dqs_dm",
> +};
> +
> +static const char * const pwm_a_groups[] = {
> + "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
> +};
> +
> +static const char * const pwm_b_groups[] = {
> + "pwm_b_x", "pwm_b_f", "pwm_b_a",
> +};
> +
> +static const char * const pwm_c_groups[] = {
> + "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
> +};
> +
> +static const char * const pwm_d_groups[] = {
> + "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
> +};
> +
> +static const char * const pwm_e_groups[] = {
> + "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
> + "pwm_e_a",
> +};
> +
> +static const char * const pwm_f_groups[] = {
> + "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
> +};
> +
> +static const char * const pwm_a_hiz_groups[] = {
> + "pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6",
> +};
> +
> +static const char * const pwm_b_hiz_groups[] = {
> + "pwm_b_hiz",
> +};
> +
> +static const char * const pwm_c_hiz_groups[] = {
> + "pwm_c_hiz",
> +};
> +
> +static const char * const spif_groups[] = {
> + "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
> + "spif_cs",
> +};
> +
> +static const char * const sdcard_groups[] = {
> + "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
> + "sdcard_clk_b", "sdcard_cmd_b",
> +
> + "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
> + "sdcard_clk_x", "sdcard_cmd_x",
> +};
> +
> +static const char * const tdm_a_groups[] = {
> + "tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk",
> + "tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1",
> +};
> +
> +static const char * const uart_a_groups[] = {
> + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
> +};
> +
> +static const char * const uart_b_groups[] = {
> + "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
> +};
> +
> +static const char * const uart_c_groups[] = {
> + "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
> + "uart_c_tx_x15", "uart_c_rx_x16",
> +};
> +
> +static const char * const i2c0_groups[] = {
> + "i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10",
> +};
> +
> +static const char * const i2c1_groups[] = {
> + "i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a",
> +};
> +
> +static const char * const i2c2_groups[] = {
> + "i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16",
> + "i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9",
> +};
> +
> +static const char * const i2c3_groups[] = {
> + "i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
> +};
> +
> +static const char * const i2c_slave_groups[] = {
> + "i2c_slave_sda_a", "i2c_slave_sck_a",
> + "i2c_slave_sda_f", "i2c_slave_sck_f",
> +};
> +
> +static const char * const spi_a_groups[] = {
> + "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
> + "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
> +
> + "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
> +};
> +
> +static const char * const pdm_groups[] = {
> + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
> + "pdm_din1_a", "pdm_din0_a", "pdm_dclk",
> +};
> +
> +static const char * const gen_clk_groups[] = {
> + "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
> +};
> +
> +static const char * const remote_input_groups[] = {
> + "remote_input_f",
> + "remote_input_a",
> +};
> +
> +static const char * const jtag_a_groups[] = {
> + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
> +};
> +
> +static const char * const clk_32k_in_groups[] = {
> + "clk_32k_in",
> +};
> +
> +static const char * const remote_out_groups[] = {
> + "remote_out",
> +};
> +
> +static const char * const spdif_in_groups[] = {
> + "spdif_in_f6", "spdif_in_f7",
> +};
> +
> +static const char * const sw_groups[] = {
> + "swclk", "swdio",
> +};
> +
> +static const char * const clk25_groups[] = {
> + "clk_25",
> +};
> +
> +static const char * const cec_a_groups[] = {
> + "cec_a",
> +};
> +
> +static const char * const cec_b_groups[] = {
> + "cec_b",
> +};
> +
> +static const char * const clk12_24_groups[] = {
> + "clk12_24",
> +};
> +
> +static const char * const mclk_0_groups[] = {
> + "mclk_0",
> +};
> +
> +static const char * const tdm_b_groups[] = {
> + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
> + "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
> + "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
> + "tdm_b_slv_sclk", "tdm_b_slv_fs",
> +};
> +
> +static const char * const mclk_vad_groups[] = {
> + "mclk_vad",
> +};
> +
> +static const char * const tdm_vad_groups[] = {
> + "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
> +};
> +
> +static const char * const tst_out_groups[] = {
> + "tst_out0", "tst_out1", "tst_out2", "tst_out3",
> + "tst_out4", "tst_out5", "tst_out6", "tst_out7",
> + "tst_out8", "tst_out9", "tst_out10", "tst_out11",
> +};
> +
> +static const char * const mute_groups[] = {
> + "mute_key", "mute_en",
> +};
> +
> +static struct meson_pmx_func meson_a1_periphs_functions[] = {
> + FUNCTION(gpio_periphs),
> + FUNCTION(psram),
> + FUNCTION(pwm_a),
> + FUNCTION(pwm_b),
> + FUNCTION(pwm_c),
> + FUNCTION(pwm_d),
> + FUNCTION(pwm_e),
> + FUNCTION(pwm_f),
> + FUNCTION(pwm_a_hiz),
> + FUNCTION(pwm_b_hiz),
> + FUNCTION(pwm_c_hiz),
> + FUNCTION(spif),
> + FUNCTION(sdcard),
> + FUNCTION(tdm_a),
> + FUNCTION(uart_a),
> + FUNCTION(uart_b),
> + FUNCTION(uart_c),
> + FUNCTION(i2c0),
> + FUNCTION(i2c1),
> + FUNCTION(i2c2),
> + FUNCTION(i2c3),
> + FUNCTION(spi_a),
> + FUNCTION(pdm),
> + FUNCTION(gen_clk),
> + FUNCTION(remote_input),
> + FUNCTION(jtag_a),
> + FUNCTION(clk_32k_in),
> + FUNCTION(remote_out),
> + FUNCTION(spdif_in),
> + FUNCTION(sw),
> + FUNCTION(clk25),
> + FUNCTION(cec_a),
> + FUNCTION(cec_b),
> + FUNCTION(clk12_24),
> + FUNCTION(mclk_0),
> + FUNCTION(tdm_b),
> + FUNCTION(mclk_vad),
> + FUNCTION(tdm_vad),
> + FUNCTION(tst_out),
> + FUNCTION(mute),
> +};
> +
> +static struct meson_bank meson_a1_periphs_banks[] = {
> + /* name first last irq pullen pull dir out in ds*/
> + BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
> + 0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
> + BANK_DS("B", GPIOB_0, GPIOB_6, 13, 19, 0x13, 0, 0x14, 0,
> + 0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0),
> + BANK_DS("X", GPIOX_0, GPIOX_16, 20, 36, 0x23, 0, 0x24, 0,
> + 0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0),
> + BANK_DS("F", GPIOF_0, GPIOF_12, 37, 49, 0x33, 0, 0x34, 0,
> + 0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0),
> + BANK_DS("A", GPIOA_0, GPIOA_11, 50, 61, 0x43, 0, 0x44, 0,
> + 0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
> +};
> +
> +static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
> + /* name first lask reg offset */
> + BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
> + BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
> + BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0),
> + BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0),
> + BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
> +};
> +
> +static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
> + .pmx_banks = meson_a1_periphs_pmx_banks,
> + .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
> +};
> +
> +static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
> + .name = "periphs-banks",
> + .pins = meson_a1_periphs_pins,
> + .groups = meson_a1_periphs_groups,
> + .funcs = meson_a1_periphs_functions,
> + .banks = meson_a1_periphs_banks,
> + .num_pins = ARRAY_SIZE(meson_a1_periphs_pins),
> + .num_groups = ARRAY_SIZE(meson_a1_periphs_groups),
> + .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions),
> + .num_banks = ARRAY_SIZE(meson_a1_periphs_banks),
> + .pmx_ops = &meson_axg_pmx_ops,
> + .pmx_data = &meson_a1_periphs_pmx_banks_data,
> + .reg_layout = A1_LAYOUT,
> +};
> +
> +static const struct of_device_id meson_a1_pinctrl_dt_match[] = {
> + {
> + .compatible = "amlogic,meson-a1-periphs-pinctrl",
> + .data = &meson_a1_periphs_pinctrl_data,
> + },
> + { },
> +};
> +
> +static struct platform_driver meson_a1_pinctrl_driver = {
> + .probe = meson_pinctrl_probe,
> + .driver = {
> + .name = "meson-a1-pinctrl",
> + .of_match_table = meson_a1_pinctrl_dt_match,
> + },
> +};
> +
> +builtin_platform_driver(meson_a1_pinctrl_driver);
> diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
> index 8bba9d0..885b89d 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson.c
> +++ b/drivers/pinctrl/meson/pinctrl-meson.c
> @@ -688,8 +688,12 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
>
> pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
> if (IS_ERR(pc->reg_ds)) {
> - dev_dbg(pc->dev, "ds registers not found - skipping\n");
> - pc->reg_ds = NULL;
> + if (pc->data->reg_layout == A1_LAYOUT) {
If the ds_reg is not used in A1_LAYOUT, simply avoid mapping it and mark
it unneeded for A1 SoCs in the bindings instead.
> + pc->reg_ds = pc->reg_pullen;
> + } else {
> + dev_dbg(pc->dev, "ds registers not found - skipping\n");
> + pc->reg_ds = NULL;
> + }
> }
>
> return 0;
> diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
> index c696f32..3d0c58d 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson.h
> +++ b/drivers/pinctrl/meson/pinctrl-meson.h
> @@ -80,6 +80,14 @@ enum meson_pinconf_drv {
> };
>
> /**
> + * enum meson_reg_layout - identify two types of reg layout
> + */
> +enum meson_reg_layout {
> + LEGACY_LAYOUT,
> + A1_LAYOUT,
> +};
> +
> +/**
> * struct meson bank
> *
> * @name: bank name
> @@ -114,6 +122,7 @@ struct meson_pinctrl_data {
> unsigned int num_banks;
> const struct pinmux_ops *pmx_ops;
> void *pmx_data;
> + unsigned int reg_layout;
> };
>
> struct meson_pinctrl {
>
Apart that look good to me,
Neil
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^ permalink raw reply
* Re: [PATCH 1/3] pinctrl: add compatible for Amlogic Meson A1 pin controller
From: Neil Armstrong @ 2019-09-17 7:18 UTC (permalink / raw)
To: Qianggui Song, Linus Walleij, linux-gpio
Cc: Mark Rutland, devicetree, Hanjie Lin, Jianxin Pan,
Martin Blumenstingl, Kevin Hilman, linux-kernel, Rob Herring,
linux-arm-kernel, Carlo Caione, linux-amlogic, Xingyu Chen,
Jerome Brunet
In-Reply-To: <1568700442-18540-2-git-send-email-qianggui.song@amlogic.com>
Hi,
On 17/09/2019 08:07, Qianggui Song wrote:
> Add new compatible name for Amlogic's Meson-A1 pin controller
> add a dt-binding header file which document the detail pin names.
Please add in the commit log that A1 doesn't need the DS bank reg,
so when we will convert these bindings to yaml we will be aware of it.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
> .../devicetree/bindings/pinctrl/meson,pinctrl.txt | 1 +
> include/dt-bindings/gpio/meson-a1-gpio.h | 73 ++++++++++++++++++++++
> 2 files changed, 74 insertions(+)
> create mode 100644 include/dt-bindings/gpio/meson-a1-gpio.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
> index 10dc4f7..0aff1f2 100644
> --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
> @@ -15,6 +15,7 @@ Required properties for the root node:
> "amlogic,meson-axg-aobus-pinctrl"
> "amlogic,meson-g12a-periphs-pinctrl"
> "amlogic,meson-g12a-aobus-pinctrl"
> + "amlogic,meson-a1-periphs-pinctrl"
> - reg: address and size of registers controlling irq functionality
>
> === GPIO sub-nodes ===
> diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h
> new file mode 100644
> index 0000000..40e57a5
> --- /dev/null
> +++ b/include/dt-bindings/gpio/meson-a1-gpio.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Qianggui Song <qianggui.song@amlogic.com>
> + */
> +
> +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
> +#define _DT_BINDINGS_MESON_A1_GPIO_H
> +
> +#define GPIOP_0 0
> +#define GPIOP_1 1
> +#define GPIOP_2 2
> +#define GPIOP_3 3
> +#define GPIOP_4 4
> +#define GPIOP_5 5
> +#define GPIOP_6 6
> +#define GPIOP_7 7
> +#define GPIOP_8 8
> +#define GPIOP_9 9
> +#define GPIOP_10 10
> +#define GPIOP_11 11
> +#define GPIOP_12 12
> +#define GPIOB_0 13
> +#define GPIOB_1 14
> +#define GPIOB_2 15
> +#define GPIOB_3 16
> +#define GPIOB_4 17
> +#define GPIOB_5 18
> +#define GPIOB_6 19
> +#define GPIOX_0 20
> +#define GPIOX_1 21
> +#define GPIOX_2 22
> +#define GPIOX_3 23
> +#define GPIOX_4 24
> +#define GPIOX_5 25
> +#define GPIOX_6 26
> +#define GPIOX_7 27
> +#define GPIOX_8 28
> +#define GPIOX_9 29
> +#define GPIOX_10 30
> +#define GPIOX_11 31
> +#define GPIOX_12 32
> +#define GPIOX_13 33
> +#define GPIOX_14 34
> +#define GPIOX_15 35
> +#define GPIOX_16 36
> +#define GPIOF_0 37
> +#define GPIOF_1 38
> +#define GPIOF_2 39
> +#define GPIOF_3 40
> +#define GPIOF_4 41
> +#define GPIOF_5 42
> +#define GPIOF_6 43
> +#define GPIOF_7 44
> +#define GPIOF_8 45
> +#define GPIOF_9 46
> +#define GPIOF_10 47
> +#define GPIOF_11 48
> +#define GPIOF_12 49
> +#define GPIOA_0 50
> +#define GPIOA_1 51
> +#define GPIOA_2 52
> +#define GPIOA_3 53
> +#define GPIOA_4 54
> +#define GPIOA_5 55
> +#define GPIOA_6 56
> +#define GPIOA_7 57
> +#define GPIOA_8 58
> +#define GPIOA_9 59
> +#define GPIOA_10 60
> +#define GPIOA_11 61
> +
> +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
>
With that fixed,
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Neil
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^ permalink raw reply
* Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
From: Tero Kristo @ 2019-09-17 7:21 UTC (permalink / raw)
To: Tony Lindgren, Suman Anna
Cc: Nishanth Menon, Dave Gerlach, Keerthy, linux-kernel,
Peter Ujfalusi, Faiz Abbas, Greg Kroah-Hartman, linux-omap,
linux-arm-kernel, Roger Quadros
In-Reply-To: <20190724064758.GU5447@atomide.com>
On 24/07/2019 09:47, Tony Lindgren wrote:
> * Suman Anna <s-anna@ti.com> [190723 21:02]:
>> Hi Tony,
>>
>> On 7/23/19 6:28 AM, Tony Lindgren wrote:
>>> The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
>>> Otherwise we get the following warning on beagle-x15:
> ...
>>> @@ -2962,9 +2958,8 @@
>>> <SYSC_IDLE_SMART>;
>>> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
>>> clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
>>> - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
>>> - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
>>> - clock-names = "fck", "ahclkx", "ahclkr";
>>> + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
>>> + clock-names = "fck", "ahclkx";
>>
>> The equivalent change to MCASP8 is missing.
>
> Thanks for spotting it, probably should be set up the same way as
> MCASP4 too looking at the TRM.
>
> Tero, care to check the dra7 mcasp clocks we have defined?
Sorry, missed this earlier.
>
> $ grep MCASP drivers/clk/ti/clk-7xx.c
> { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
> { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
> { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
> { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
> { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
> { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
> { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
> { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
>
> Is bit 24 above correct for MCASP8 or should it too be 22 like
> adjacent MCASP4 in the TRM?
So yeah, mcasp8 is wrong here, should be 22 as rest of them. I did fix
mcasp8 clocks partially when doing the conversion but missed the
parenting here; it was completely broken before.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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* Re: [PATCH 05/11] drm/bridge: analogix-anx78xx: correct value of TX_P0
From: Andrzej Hajda @ 2019-09-17 7:28 UTC (permalink / raw)
To: Brian Masney, Enric Balletbo i Serra
Cc: mark.rutland, devicetree, jernej.skrabec, dri-devel, narmstrong,
airlied, linux-arm-msm, linus.walleij, jonas, linux-kernel,
robh+dt, bjorn.andersson, robdclark, agross, Laurent Pinchart,
daniel, freedreno, sean, linux-arm-kernel
In-Reply-To: <20190916120228.GA3045@onstation.org>
On 16.09.2019 14:02, Brian Masney wrote:
> On Mon, Sep 16, 2019 at 01:32:58PM +0200, Enric Balletbo i Serra wrote:
>> Hi,
>>
>> On 16/9/19 12:49, Laurent Pinchart wrote:
>>> Hi Brian,
>>>
>>> On Mon, Sep 16, 2019 at 06:36:14AM -0400, Brian Masney wrote:
>>>> On Mon, Sep 16, 2019 at 12:02:09PM +0200, Andrzej Hajda wrote:
>>>>> On 15.08.2019 02:48, Brian Masney wrote:
>>>>>> When attempting to configure this driver on a Nexus 5 phone (msm8974),
>>>>>> setting up the dummy i2c bus for TX_P0 would fail due to an -EBUSY
>>>>>> error. The downstream MSM kernel sources [1] shows that the proper value
>>>>>> for TX_P0 is 0x78, not 0x70, so correct the value to allow device
>>>>>> probing to succeed.
>>>>>>
>>>>>> [1] https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/drivers/video/slimport/slimport_tx_reg.h
>>>>>>
>>>>>> Signed-off-by: Brian Masney <masneyb@onstation.org>
>>>>>> ---
>>>>>> drivers/gpu/drm/bridge/analogix-anx78xx.h | 2 +-
>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h b/drivers/gpu/drm/bridge/analogix-anx78xx.h
>>>>>> index 25e063bcecbc..bc511fc605c9 100644
>>>>>> --- a/drivers/gpu/drm/bridge/analogix-anx78xx.h
>>>>>> +++ b/drivers/gpu/drm/bridge/analogix-anx78xx.h
>>>>>> @@ -6,7 +6,7 @@
>>>>>> #ifndef __ANX78xx_H
>>>>>> #define __ANX78xx_H
>>>>>>
>>>>>> -#define TX_P0 0x70
>>>>>> +#define TX_P0 0x78
>>>>>
>>>>> This bothers me little. There are no upstream users, grepping android
>>>>> sources suggests that both values can be used [1][2] (grep for "#define
>>>>> TX_P0"), moreover there is code suggesting both values can be valid [3].
>>>>>
>>>>> Could you verify datasheet which i2c slave addresses are valid for this
>>>>> chip, if both I guess this patch should be reworked.
>>>>>
>>>>>
>>>>> [1]:
>>>>> https://android.googlesource.com/kernel/msm/+/android-msm-flo-3.4-jb-mr2/drivers/misc/slimport_anx7808/slimport_tx_reg.h
>>>>>
>>>>> [2]:
>>>>> https://github.com/AndroidGX/SimpleGX-MM-6.0_H815_20d/blob/master/drivers/video/slimport/anx7812/slimport7812_tx_reg.h
>>>>>
>>>>> [3]:
>>>>> https://github.com/commaai/android_kernel_leeco_msm8996/blob/master/drivers/video/msm/mdss/dp/slimport_custom_declare.h#L73
>>>> This address is 0x78 on my Nexus 5. Given [3] above it looks like we
>>>> need to support both addresses. What do you think about moving these
>>>> addresses into device tree?
>>> Assuming that the device supports different addresses (I can't validate
>>> that as I don't have access to the datasheet), and different addresses
>>> need to be used on different systems, then the address to be used needs
>>> to be provided by the firmware (DT in this case). Two options are
>>> possible, either specifying the address explicitly in the device's DT
>>> node, or specifying free addresses (in the form of a white list or black
>>> list) and allocating an address from that pool. The latter has been
>>> discussed in a BoF at the Linux Plumbers Conference last week,
>>> https://linuxplumbersconf.org/event/4/contributions/542/.
>>>
>>>> The downstream and upstream kernel sources divide these addresses by two
>>>> to get the i2c address. Here's the code in upstream:
>>>>
>>>> https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/bridge/analogix-anx78xx.c#L1353
>>>> https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/bridge/analogix-anx78xx.c#L41
>>>>
>>>> I'm not sure why the actual i2c address isn't used in this code.
>> The ANX7802/12/14/16 has a slave I2C bus that provides the interface to access
>> or control the chip from the AP. The I2C slave addresses used to control the
>> ANX7802/12/14/16 are 70h, 72h, 7Ah, 7Eh and 80h. Every address allows you to
>> access to different registers of the chip and AFAICS is not configurable.
>>
>> I don't think these addresses should be configured via DT but for the driver itself.
>>
>> My wild guess is that the ANX7808 has different addresses, but I don't have the
>> datasheet of this version.
> I'm able to communicate with the 7808 on my Nexus 5 using the 0x78
> address. Given that the addresses appear to be fixed per model, maybe it
> makes sense to drop the address #defines and add the addresses to the
> data pointer in the driver's of_match_table like so:
>
> static const struct of_device_id anx78xx_match_table[] = {
> { .compatible = "analogix,anx7808", .data = PTR_TO_7808_ADDRS },
> { .compatible = "analogix,anx7812", .data = PTR_TO_781X_ADDRS },
> { .compatible = "analogix,anx7814", .data = PTR_TO_781X_ADDRS },
> { .compatible = "analogix,anx7818", .data = PTR_TO_781X_ADDRS },
> { /* sentinel */ },
> };
With given feedback from other users and lack of datasheets for chips
(except anx7814) we can try this approach.
Regards
Andrzej
>
> Brian
>
>
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* [PATCH] arm64: dts: lx2160a: Correct CPU core idle state name
From: Ran Wang @ 2019-09-17 7:33 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, linux-kernel, Li Yang, Rob Herring,
Ran Wang, linux-arm-kernel
lx2160a support PW15 but not PW20, correct name to avoid confusing.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 36 +++++++++++++-------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 408e0ec..b032f38 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -33,7 +33,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@1 {
@@ -49,7 +49,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@100 {
@@ -65,7 +65,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@101 {
@@ -81,7 +81,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@200 {
@@ -97,7 +97,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@201 {
@@ -113,7 +113,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@300 {
@@ -129,7 +129,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@301 {
@@ -145,7 +145,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@400 {
@@ -161,7 +161,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@401 {
@@ -177,7 +177,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@500 {
@@ -193,7 +193,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@501 {
@@ -209,7 +209,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@600 {
@@ -225,7 +225,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@601 {
@@ -241,7 +241,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@700 {
@@ -257,7 +257,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cpu@701 {
@@ -273,7 +273,7 @@
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
- cpu-idle-states = <&cpu_pw20>;
+ cpu-idle-states = <&cpu_pw15>;
};
cluster0_l2: l2-cache0 {
@@ -340,9 +340,9 @@
cache-level = <2>;
};
- cpu_pw20: cpu-pw20 {
+ cpu_pw15: cpu-pw15 {
compatible = "arm,idle-state";
- idle-state-name = "PW20";
+ idle-state-name = "PW15";
arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
--
2.7.4
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^ permalink raw reply related
* Re: [REGRESSION] sdhci no longer detects SD cards on LX2160A
From: Marc Gonzalez @ 2019-09-17 8:06 UTC (permalink / raw)
To: Russell King - ARM Linux admin, Adrian Hunter; +Cc: linux-mmc, Linux ARM
In-Reply-To: <20190916171509.GG25745@shell.armlinux.org.uk>
On 16/09/2019 19:15, Russell King - ARM Linux admin wrote:
> The platform has an iommu, which is in pass-through mode, via
> arm_smmu.disable_bypass=0.
Could be 954a03be033c7cef80ddc232e7cbdb17df735663
"iommu/arm-smmu: Break insecure users by disabling bypass by default"
Although it had already landed in v5.2
Regards.
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* Re: [PATCH] KVM: arm64: vgic-v4: Move the GICv4 residency flow to be driven by vcpu_load/put
From: Zenghui Yu @ 2019-09-17 8:10 UTC (permalink / raw)
To: Marc Zyngier, linux-arm-kernel, kvmarm, kvm; +Cc: Andre Przywara
In-Reply-To: <20190903155747.219802-1-maz@kernel.org>
Hi Marc,
I've run this patch on my box and got the following messages:
---8<
[ 2258.490030] BUG: sleeping function called from invalid context at
kernel/irq/manage.c:138
[ 2258.490034] in_atomic(): 1, irqs_disabled(): 0, pid: 59278, name: CPU
0/KVM
[ 2258.490039] CPU: 32 PID: 59278 Comm: CPU 0/KVM Kdump: loaded Tainted:
G W 5.3.0+ #26
[ 2258.490041] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.58
10/29/2018
[ 2258.490043] Call trace:
[ 2258.490056] dump_backtrace+0x0/0x188
[ 2258.490060] show_stack+0x24/0x30
[ 2258.490066] dump_stack+0xb0/0xf4
[ 2258.490072] ___might_sleep+0x10c/0x130
[ 2258.490074] __might_sleep+0x58/0x90
[ 2258.490078] synchronize_irq+0x58/0xd8
[ 2258.490079] disable_irq+0x2c/0x38
[ 2258.490083] vgic_v4_load+0x9c/0xc0
[ 2258.490084] vgic_v3_load+0x94/0x170
[ 2258.490088] kvm_vgic_load+0x3c/0x60
[ 2258.490092] kvm_arch_vcpu_load+0xd4/0x1d0
[ 2258.490095] vcpu_load+0x50/0x70
[ 2258.490097] kvm_arch_vcpu_ioctl_run+0x94/0x978
[ 2258.490098] kvm_vcpu_ioctl+0x3d8/0xa28
[ 2258.490104] do_vfs_ioctl+0xc4/0x8e8
[ 2258.490106] ksys_ioctl+0x8c/0xa0
[ 2258.490108] __arm64_sys_ioctl+0x28/0x58
[ 2258.490112] el0_svc_common.constprop.0+0x7c/0x188
[ 2258.490114] el0_svc_handler+0x34/0xb8
[ 2258.490117] el0_svc+0x8/0xc
[ 2259.497070] BUG: sleeping function called from invalid context at
kernel/irq/manage.c:138
[ 2259.497077] in_atomic(): 1, irqs_disabled(): 0, pid: 59278, name: CPU
0/KVM
[ 2259.497082] CPU: 33 PID: 59278 Comm: CPU 0/KVM Kdump: loaded Tainted:
G W 5.3.0+ #26
[ 2259.497083] Hardware name: Huawei TaiShan 2280 /BC11SPCD, BIOS 1.58
10/29/2018
[ 2259.497086] Call trace:
[ 2259.497098] dump_backtrace+0x0/0x188
[ 2259.497101] show_stack+0x24/0x30
[ 2259.497109] dump_stack+0xb0/0xf4
[ 2259.497115] ___might_sleep+0x10c/0x130
[ 2259.497117] __might_sleep+0x58/0x90
[ 2259.497120] synchronize_irq+0x58/0xd8
[ 2259.497122] disable_irq+0x2c/0x38
[ 2259.497126] vgic_v4_load+0x9c/0xc0
[ 2259.497127] vgic_v3_load+0x94/0x170
[ 2259.497130] kvm_vgic_load+0x3c/0x60
[ 2259.497134] kvm_arch_vcpu_load+0xd4/0x1d0
[ 2259.497137] kvm_sched_in+0x30/0x40
[ 2259.497139] finish_task_switch+0x134/0x258
[ 2259.497142] __schedule+0x33c/0x780
[ 2259.497144] schedule+0x48/0xd8
[ 2259.497147] kvm_vcpu_block+0xb8/0x390
[ 2259.497148] kvm_handle_wfx+0xa0/0x230
[ 2259.497150] handle_exit+0x14c/0x1c8
[ 2259.497152] kvm_arch_vcpu_ioctl_run+0x354/0x978
[ 2259.497154] kvm_vcpu_ioctl+0x3d8/0xa28
[ 2259.497161] do_vfs_ioctl+0xc4/0x8e8
[ 2259.497163] ksys_ioctl+0x8c/0xa0
[ 2259.497165] __arm64_sys_ioctl+0x28/0x58
[ 2259.497168] el0_svc_common.constprop.0+0x7c/0x188
[ 2259.497171] el0_svc_handler+0x34/0xb8
[ 2259.497175] el0_svc+0x8/0xc
The logic of disabling the doorbell interrupt in vgic_v4_load() might
need a fix?
Thanks,
zenghui
On 2019/9/3 23:57, Marc Zyngier wrote:
> When the VHE code was reworked, a lot of the vgic stuff was moved around,
> but the GICv4 residency code did stay untouched, meaning that we come
> in and out of residency on each flush/sync, which is obviously suboptimal.
>
> To address this, let's move things around a bit:
>
> - Residency entry (flush) moves to vcpu_load
> - Residency exit (sync) moves to vcpu_put
> - On blocking (entry to WFI), we "put"
> - On unblocking (exit from WFI, we "load"
>
> Because these can nest (load/block/put/load/unblock/put, for example),
> we now have per-VPE tracking of the residency state.
>
> Additionally, vgic_v4_put gains a "need doorbell" parameter, which only
> gets set to true when blocking because of a WFI. This allows a finer
> control of the doorbell, which now also gets disabled as soon as
> it gets signaled.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> drivers/irqchip/irq-gic-v4.c | 7 +++-
> include/kvm/arm_vgic.h | 4 +--
> include/linux/irqchip/arm-gic-v4.h | 2 ++
> virt/kvm/arm/arm.c | 12 ++++---
> virt/kvm/arm/vgic/vgic-v3.c | 4 +++
> virt/kvm/arm/vgic/vgic-v4.c | 55 ++++++++++++++----------------
> virt/kvm/arm/vgic/vgic.c | 4 ---
> virt/kvm/arm/vgic/vgic.h | 2 --
> 8 files changed, 48 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v4.c b/drivers/irqchip/irq-gic-v4.c
> index 563e87ed0766..45969927cc81 100644
> --- a/drivers/irqchip/irq-gic-v4.c
> +++ b/drivers/irqchip/irq-gic-v4.c
> @@ -141,12 +141,17 @@ static int its_send_vpe_cmd(struct its_vpe *vpe, struct its_cmd_info *info)
> int its_schedule_vpe(struct its_vpe *vpe, bool on)
> {
> struct its_cmd_info info;
> + int ret;
>
> WARN_ON(preemptible());
>
> info.cmd_type = on ? SCHEDULE_VPE : DESCHEDULE_VPE;
>
> - return its_send_vpe_cmd(vpe, &info);
> + ret = its_send_vpe_cmd(vpe, &info);
> + if (!ret)
> + vpe->resident = on;
> +
> + return ret;
> }
>
> int its_invall_vpe(struct its_vpe *vpe)
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index af4f09c02bf1..4dc58d7a0010 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -396,7 +396,7 @@ int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
> int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
> struct kvm_kernel_irq_routing_entry *irq_entry);
>
> -void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
> -void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
> +int vgic_v4_load(struct kvm_vcpu *vcpu);
> +int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);
>
> #endif /* __KVM_ARM_VGIC_H */
> diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h
> index e6b155713b47..ab1396afe08a 100644
> --- a/include/linux/irqchip/arm-gic-v4.h
> +++ b/include/linux/irqchip/arm-gic-v4.h
> @@ -35,6 +35,8 @@ struct its_vpe {
> /* Doorbell interrupt */
> int irq;
> irq_hw_number_t vpe_db_lpi;
> + /* VPE resident */
> + bool resident;
> /* VPE proxy mapping */
> int vpe_proxy_event;
> /*
> diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
> index 35a069815baf..4e69268621b6 100644
> --- a/virt/kvm/arm/arm.c
> +++ b/virt/kvm/arm/arm.c
> @@ -321,20 +321,24 @@ void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
> /*
> * If we're about to block (most likely because we've just hit a
> * WFI), we need to sync back the state of the GIC CPU interface
> - * so that we have the lastest PMR and group enables. This ensures
> + * so that we have the latest PMR and group enables. This ensures
> * that kvm_arch_vcpu_runnable has up-to-date data to decide
> * whether we have pending interrupts.
> + *
> + * For the same reason, we want to tell GICv4 that we need
> + * doorbells to be signalled, should an interrupt become pending.
> */
> preempt_disable();
> kvm_vgic_vmcr_sync(vcpu);
> + vgic_v4_put(vcpu, true);
> preempt_enable();
> -
> - kvm_vgic_v4_enable_doorbell(vcpu);
> }
>
> void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
> {
> - kvm_vgic_v4_disable_doorbell(vcpu);
> + preempt_disable();
> + vgic_v4_load(vcpu);
> + preempt_enable();
> }
>
> int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
> index 8d69f007dd0c..48307a9eb1d8 100644
> --- a/virt/kvm/arm/vgic/vgic-v3.c
> +++ b/virt/kvm/arm/vgic/vgic-v3.c
> @@ -664,6 +664,8 @@ void vgic_v3_load(struct kvm_vcpu *vcpu)
>
> if (has_vhe())
> __vgic_v3_activate_traps(vcpu);
> +
> + WARN_ON(vgic_v4_load(vcpu));
> }
>
> void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
> @@ -676,6 +678,8 @@ void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
>
> void vgic_v3_put(struct kvm_vcpu *vcpu)
> {
> + WARN_ON(vgic_v4_put(vcpu, false));
> +
> vgic_v3_vmcr_sync(vcpu);
>
> kvm_call_hyp(__vgic_v3_save_aprs, vcpu);
> diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c
> index 477af6aebb97..3a8a28854b13 100644
> --- a/virt/kvm/arm/vgic/vgic-v4.c
> +++ b/virt/kvm/arm/vgic/vgic-v4.c
> @@ -85,6 +85,10 @@ static irqreturn_t vgic_v4_doorbell_handler(int irq, void *info)
> {
> struct kvm_vcpu *vcpu = info;
>
> + /* We got the message, no need to fire again */
> + if (!irqd_irq_disabled(&irq_to_desc(irq)->irq_data))
> + disable_irq_nosync(irq);
> +
> vcpu->arch.vgic_cpu.vgic_v3.its_vpe.pending_last = true;
> kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
> kvm_vcpu_kick(vcpu);
> @@ -192,20 +196,30 @@ void vgic_v4_teardown(struct kvm *kvm)
> its_vm->vpes = NULL;
> }
>
> -int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu)
> +int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db)
> {
> - if (!vgic_supports_direct_msis(vcpu->kvm))
> + struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
> + struct irq_desc *desc = irq_to_desc(vpe->irq);
> +
> + if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident)
> return 0;
>
> - return its_schedule_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe, false);
> + /*
> + * If blocking, a doorbell is required. Undo the nested
> + * disable_irq() calls...
> + */
> + while (need_db && irqd_irq_disabled(&desc->irq_data))
> + enable_irq(vpe->irq);
> +
> + return its_schedule_vpe(vpe, false);
> }
>
> -int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu)
> +int vgic_v4_load(struct kvm_vcpu *vcpu)
> {
> - int irq = vcpu->arch.vgic_cpu.vgic_v3.its_vpe.irq;
> + struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
> int err;
>
> - if (!vgic_supports_direct_msis(vcpu->kvm))
> + if (!vgic_supports_direct_msis(vcpu->kvm) || vpe->resident)
> return 0;
>
> /*
> @@ -214,11 +228,14 @@ int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu)
> * doc in drivers/irqchip/irq-gic-v4.c to understand how this
> * turns into a VMOVP command at the ITS level.
> */
> - err = irq_set_affinity(irq, cpumask_of(smp_processor_id()));
> + err = irq_set_affinity(vpe->irq, cpumask_of(smp_processor_id()));
> if (err)
> return err;
>
> - err = its_schedule_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe, true);
> + /* Disabled the doorbell, as we're about to enter the guest */
> + disable_irq(vpe->irq);
> +
> + err = its_schedule_vpe(vpe, true);
> if (err)
> return err;
>
> @@ -226,9 +243,7 @@ int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu)
> * Now that the VPE is resident, let's get rid of a potential
> * doorbell interrupt that would still be pending.
> */
> - err = irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, false);
> -
> - return err;
> + return irq_set_irqchip_state(vpe->irq, IRQCHIP_STATE_PENDING, false);
> }
>
> static struct vgic_its *vgic_get_its(struct kvm *kvm,
> @@ -335,21 +350,3 @@ int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int virq,
> mutex_unlock(&its->its_lock);
> return ret;
> }
> -
> -void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu)
> -{
> - if (vgic_supports_direct_msis(vcpu->kvm)) {
> - int irq = vcpu->arch.vgic_cpu.vgic_v3.its_vpe.irq;
> - if (irq)
> - enable_irq(irq);
> - }
> -}
> -
> -void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu)
> -{
> - if (vgic_supports_direct_msis(vcpu->kvm)) {
> - int irq = vcpu->arch.vgic_cpu.vgic_v3.its_vpe.irq;
> - if (irq)
> - disable_irq(irq);
> - }
> -}
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index 45a870cb63f5..99b02ca730a8 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -857,8 +857,6 @@ void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
> {
> struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
>
> - WARN_ON(vgic_v4_sync_hwstate(vcpu));
> -
> /* An empty ap_list_head implies used_lrs == 0 */
> if (list_empty(&vcpu->arch.vgic_cpu.ap_list_head))
> return;
> @@ -882,8 +880,6 @@ static inline void vgic_restore_state(struct kvm_vcpu *vcpu)
> /* Flush our emulation state into the GIC hardware before entering the guest. */
> void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
> {
> - WARN_ON(vgic_v4_flush_hwstate(vcpu));
> -
> /*
> * If there are no virtual interrupts active or pending for this
> * VCPU, then there is no work to do and we can bail out without
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index 83066a81b16a..c7fefd6b1c80 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -316,7 +316,5 @@ void vgic_its_invalidate_cache(struct kvm *kvm);
> bool vgic_supports_direct_msis(struct kvm *kvm);
> int vgic_v4_init(struct kvm *kvm);
> void vgic_v4_teardown(struct kvm *kvm);
> -int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
> -int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);
>
> #endif
>
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^ permalink raw reply
* Re: [REGRESSION] sdhci no longer detects SD cards on LX2160A
From: Russell King - ARM Linux admin @ 2019-09-17 8:19 UTC (permalink / raw)
To: Marc Gonzalez; +Cc: linux-mmc, Adrian Hunter, Linux ARM
In-Reply-To: <b19a0640-5d71-a005-eb0f-c6840f181e5d@free.fr>
On Tue, Sep 17, 2019 at 10:06:12AM +0200, Marc Gonzalez wrote:
> On 16/09/2019 19:15, Russell King - ARM Linux admin wrote:
>
> > The platform has an iommu, which is in pass-through mode, via
> > arm_smmu.disable_bypass=0.
>
> Could be 954a03be033c7cef80ddc232e7cbdb17df735663
> "iommu/arm-smmu: Break insecure users by disabling bypass by default"
>
> Although it had already landed in v5.2
It is not - and the two lines that you quoted above are sufficient
to negate that as a cause. (Please read the help for the option that
the commit referrs to.)
In fact, with bypass disabled, the SoC fails due to other masters.
That's already been discussed privately between myself and Will
Deacon.
arm_smmu.disable_bypass=0 re-enables bypass mode irrespective of
the default setting in the Kconfig.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
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^ permalink raw reply
* Re: [PATCH v3] mm/kasan: dump alloc and free stack for page allocator
From: Vlastimil Babka @ 2019-09-17 8:19 UTC (permalink / raw)
To: Andrey Ryabinin, Walter Wu
Cc: wsd_upstream, Arnd Bergmann, linux-mm, Andrey Konovalov,
linux-mediatek, linux-kernel, kasan-dev, Martin Schwidefsky,
Alexander Potapenko, linux-arm-kernel, Matthias Brugger, Qian Cai,
Andrew Morton, Dmitry Vyukov
In-Reply-To: <4e76e7ce-1d61-524a-622b-663c01d19707@virtuozzo.com>
On 9/16/19 5:57 PM, Andrey Ryabinin wrote:
>> --- a/mm/page_alloc.c
>> +++ b/mm/page_alloc.c
>> @@ -710,8 +710,12 @@ static int __init early_debug_pagealloc(char *buf)
>> if (kstrtobool(buf, &enable))
>> return -EINVAL;
>>
>> - if (enable)
>> + if (enable) {
>> static_branch_enable(&_debug_pagealloc_enabled);
>> +#ifdef CONFIG_PAGE_OWNER
>> + page_owner_free_stack_disabled = false;
>
> I think this won't work with CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
Good point, thanks.
>> +#endif
>> + }
>>
>> return 0;
>> }
>> diff --git a/mm/page_owner.c b/mm/page_owner.c
>> index dee931184788..b589bfbc4795 100644
>> --- a/mm/page_owner.c
>> +++ b/mm/page_owner.c
>> @@ -24,13 +24,15 @@ struct page_owner {
>> short last_migrate_reason;
>> gfp_t gfp_mask;
>> depot_stack_handle_t handle;
>> -#ifdef CONFIG_DEBUG_PAGEALLOC
>> +#ifdef CONFIG_PAGE_OWNER_FREE_STACK
>> depot_stack_handle_t free_handle;
>> #endif
>> };
>>
>> static bool page_owner_disabled = true;
>> +bool page_owner_free_stack_disabled = true;
>> DEFINE_STATIC_KEY_FALSE(page_owner_inited);
>> +static DEFINE_STATIC_KEY_FALSE(page_owner_free_stack);
>>
>> static depot_stack_handle_t dummy_handle;
>> static depot_stack_handle_t failure_handle;
>> @@ -46,6 +48,9 @@ static int __init early_page_owner_param(char *buf)
>> if (strcmp(buf, "on") == 0)
>> page_owner_disabled = false;
>>
>> + if (!page_owner_disabled && IS_ENABLED(CONFIG_KASAN))
>
> I'd rather keep all logic in one place, i.e. "if (!page_owner_disabled && (IS_ENABLED(CONFIG_KASAN) || debug_pagealloc_enabled())"
> With this no changes in early_debug_pagealloc() required and CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y should also work correctly.
In this function it would not work if the debug_pagealloc param gets
processed later than page_owner, but should be doable in
init_page_owner(), I'll try, thanks.
>
>> + page_owner_free_stack_disabled = false;
>> +
>> return 0;
>> }
>> early_param("page_owner", early_page_owner_param);
>
>
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^ permalink raw reply
* [PATCH 01/13] arm64: dts: rockchip: fix iface clock-name on px30 iommus
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
The iommu clock names are aclk+iface not aclk+hclk as in the vendor kernel,
so fix that in the px30.dtsi
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index eb992d60e6ba..1fd12bd09e83 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -831,7 +831,7 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
@@ -863,7 +863,7 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
#iommu-cells = <0>;
status = "disabled";
--
2.20.1
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^ permalink raw reply related
* [PATCH 02/13] arm64: dts: rockchip: remove static xin32k from px30
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
Similar to all other Rockchip SoCs the px30 does not have a static
32kHz clock. Instead it again gets supplied from an external component
like the pmic.
So drop the static clock, so that we can hook up the right one.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 1fd12bd09e83..06328f1b05e8 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -195,13 +195,6 @@
clock-output-names = "xin24m";
};
- xin32k: xin32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-
pmu: power-management@ff000000 {
compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff000000 0x0 0x1000>;
--
2.20.1
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* [PATCH 03/13] arm64: dts: rockchip: remove px30 emmc_pwren pinctrl
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
That gpio1-b0 can only be flash_cs apart from a regular gpio,
so there is no power-related pinmux for the emmc for this pin.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 06328f1b05e8..a178d6e2c279 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1648,11 +1648,6 @@
<1 RK_PB2 2 &pcfg_pull_up_8ma>;
};
- emmc_pwren: emmc-pwren {
- rockchip,pins =
- <1 RK_PB0 2 &pcfg_pull_none>;
- };
-
emmc_rstnout: emmc-rstnout {
rockchip,pins =
<1 RK_PB3 2 &pcfg_pull_none>;
--
2.20.1
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* [PATCH 06/13] arm64: dts: rockchip: add emmc-powersequence to px30-evb
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
Hook the reset line into an emmc-pwrseq for it to get initialized nicely.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index d78fb172a66f..6d50f6abcb48 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -61,6 +61,13 @@
power-supply = <&vcc3v3_lcd>;
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&emmc_reset>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -110,6 +117,7 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
+ mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v0>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
@@ -364,6 +372,12 @@
};
};
+ emmc {
+ emmc_reset: emmc-reset {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int: pmic_int {
rockchip,pins =
--
2.20.1
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* [PATCH 04/13] arm64: dts: rockchip: add default px30 emmc pinctrl
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
emmc chips are normally hooked up in standard ways using the full 8bit
bus connection, so there should be no need for all future boards to define
this on their own. So add default pin setups for 8bit busses and special
boards really only needing 4 or 1 bit connections can override.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index a178d6e2c279..f2bbdfa0e4aa 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -794,6 +794,8 @@
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
--
2.20.1
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* [PATCH 05/13] arm64: dts: rockchip: fix the px30-evb power tree
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
Add the board's pmic (rk809) and hook up the real supplies to their
consumers. This is especially important as cpufreq would otherwise hang
the system when scaling the frequency without adjusting the voltage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 254 +++++++++++++++++++++-
1 file changed, 246 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 6eb7407a84aa..d78fb172a66f 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -58,6 +58,7 @@
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
+ power-supply = <&vcc3v3_lcd>;
};
sdio_pwrseq: sdio-pwrseq {
@@ -74,13 +75,6 @@
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
};
- vcc_phy: vcc-phy-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc_phy";
- regulator-always-on;
- regulator-boot-on;
- };
-
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -91,6 +85,22 @@
};
};
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
&display_subsystem {
status = "okay";
};
@@ -100,12 +110,14 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
+ vmmc-supply = <&vcc_3v0>;
+ vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&gmac {
clock_in_out = "output";
- phy-supply = <&vcc_phy>;
+ phy-supply = <&vcc_rmii>;
snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
@@ -114,6 +126,219 @@
&i2c0 {
status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <0>;
+ clock-output-names = "xin32k";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v0: vcc_rmii: DCDC_REG4 {
+ regulator-name = "vcc_3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG5 {
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v0: LDO_REG1 {
+ regulator-name = "vcc_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v0_pmu: LDO_REG4 {
+ regulator-name = "vcc3v0_pmu";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG7 {
+ regulator-name = "vcc2v8_dvp";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-name = "vcc1v8_dvp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc1v5_dvp: LDO_REG9 {
+ regulator-name = "vcc1v5_dvp";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1500000>;
+ };
+ };
+
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-name = "vcc3v3_lcd";
+ regulator-boot-on;
+ };
+
+ vcc5v0_host: SWITCH_REG2 {
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
};
&i2s1_2ch {
@@ -122,6 +347,13 @@
&io_domains {
status = "okay";
+
+ vccio1-supply = <&vccio_sdio>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v0>;
+ vccio4-supply = <&vcc3v0_pmu>;
+ vccio5-supply = <&vcc_3v0>;
+ vccio6-supply = <&vccio_flash>;
};
&pinctrl {
@@ -164,6 +396,9 @@
&pmu_io_domains {
status = "okay";
+
+ pmuio1-supply = <&vcc3v0_pmu>;
+ pmuio2-supply = <&vcc3v0_pmu>;
};
&pwm1 {
@@ -171,6 +406,7 @@
};
&saradc {
+ vref-supply = <&vcc_1v8>;
status = "okay";
};
@@ -183,6 +419,8 @@
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
status = "okay";
};
--
2.20.1
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* [PATCH 07/13] arm64: dts: rockchip: move px30-evb console output to uart 5
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
The px30-evb exposes uart2 through a uart-to-usb converter on the board
but these pins are shared with the sdmmc controller. With both activated
this results in a race condition depending in the probe order.
Whichever of the two probes first will break the other peripheral.
The px30-evb also exposes uart5 through pin its pin headers, so it's way
saner to use these pins for serial output and keep the sdmmc working in
all cases.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 6d50f6abcb48..80524afe94da 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -14,7 +14,7 @@
compatible = "rockchip,px30-evb", "rockchip,px30";
chosen {
- stdout-path = "serial2:1500000n8";
+ stdout-path = "serial5:115200n8";
};
adc-keys {
@@ -454,7 +454,7 @@
status = "okay";
};
-&uart2 {
+&uart5 {
status = "okay";
};
--
2.20.1
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* [PATCH 08/13] arm64: dts: rockchip: remove unused pin settings from px30
From: Heiko Stuebner @ 2019-09-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, devicetree, Heiko Stuebner, linux-kernel,
linux-rockchip, robh+dt, christoph.muellner
In-Reply-To: <20190917082659.25549-1-heiko@sntech.de>
These are unused gpio-settings for specific function pins, that
are not used by anything and only clutter up the dtsi.
They can be re-added when a relevant user is added.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 40 --------------------------
1 file changed, 40 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index f2bbdfa0e4aa..63499d27994c 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1159,11 +1159,6 @@
rockchip,pins =
<0 RK_PB5 1 &pcfg_pull_none>;
};
-
- uart0_rts_gpio: uart0-rts-gpio {
- rockchip,pins =
- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart1 {
@@ -1182,11 +1177,6 @@
rockchip,pins =
<1 RK_PC3 1 &pcfg_pull_none>;
};
-
- uart1_rts_gpio: uart1-rts-gpio {
- rockchip,pins =
- <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart2-m0 {
@@ -1221,11 +1211,6 @@
rockchip,pins =
<0 RK_PC3 2 &pcfg_pull_none>;
};
-
- uart3m0_rts_gpio: uart3m0-rts-gpio {
- rockchip,pins =
- <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart3-m1 {
@@ -1244,11 +1229,6 @@
rockchip,pins =
<1 RK_PB5 2 &pcfg_pull_none>;
};
-
- uart3m1_rts_gpio: uart3m1-rts-gpio {
- rockchip,pins =
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart4 {
@@ -1597,16 +1577,6 @@
<1 RK_PD4 1 &pcfg_pull_up_8ma>,
<1 RK_PD5 1 &pcfg_pull_up_8ma>;
};
-
- sdmmc_gpio: sdmmc-gpio {
- rockchip,pins =
- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
};
sdio {
@@ -1627,16 +1597,6 @@
<1 RK_PD0 1 &pcfg_pull_up>,
<1 RK_PD1 1 &pcfg_pull_up>;
};
-
- sdio_gpio: sdio-gpio {
- rockchip,pins =
- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
};
emmc {
--
2.20.1
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