* Re: Re: [PATCH 5/5] arm64: dts: imx8mq: add DCSS node
From: Laurentiu Palcu @ 2019-09-24 7:25 UTC (permalink / raw)
To: Stephen Boyd
Cc: devicetree@vger.kernel.org, Fabio Estevam, Sascha Hauer,
linux-kernel@vger.kernel.org, dl-linux-imx,
Pengutronix Kernel Team, Shawn Guo, agx@sigxcpu.org,
linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de
In-Reply-To: <20190923165443.D1B1C20882@mail.kernel.org>
On Mon, Sep 23, 2019 at 09:54:42AM -0700, Stephen Boyd wrote:
> Quoting Laurentiu Palcu (2019-09-23 07:13:19)
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 52aae34..d4aa778 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -871,6 +871,31 @@
> > interrupt-controller;
> > #interrupt-cells = <1>;
> > };
> > +
> > + dcss: dcss@0x32e00000 {
>
> Drop the 0x prefix on node names.
Thanks, will do.
laurentiu
>
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "nxp,imx8mq-dcss";
> > + reg = <0x32e00000 0x2D000>, <0x32e2f000 0x1000>;
> > + interrupts = <6>, <8>, <9>;
> > + interrupt-names = "ctx_ld", "ctxld_kick", "vblank";
> > + interrupt-parent = <&irqsteer>;
> > + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
> > + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
> > + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
> > + <&clk IMX8MQ_VIDEO2_PLL_OUT>,
> > + <&clk IMX8MQ_CLK_DISP_DTRC>;
> > + clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> > + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
> > + <&clk IMX8MQ_CLK_DISP_RTRM>,
> > + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
> > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
> > + <&clk IMX8MQ_SYS1_PLL_800M>,
> > + <&clk IMX8MQ_CLK_27M>;
> > + assigned-clock-rates = <800000000>,
> > + <400000000>;
> > + status = "disabled";
> > + };
>
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* [PATCH v2] PM / devfreq: Check NULL governor in available_governors_show
From: Leonard Crestez @ 2019-09-24 7:26 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Matthias Kaehlcke
Cc: Artur Świgoń, linux-pm, linux-imx, linux-arm-kernel,
Lukasz Luba
The governor is initialized after sysfs attributes become visible so in
theory the governor field can be NULL here.
Fixes: bcf23c79c4e46 ("PM / devfreq: Fix available_governor sysfs")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
---
drivers/devfreq/devfreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Changes since v1:
* Add Fixes tag and Reviewed-by
Link to v1: https://patchwork.kernel.org/patch/11157333/
Don't add cc: stable since it's a theoretical race condition.
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index b905963cea7d..60859a2400bc 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -1193,11 +1193,11 @@ static ssize_t available_governors_show(struct device *d,
/*
* The devfreq with immutable governor (e.g., passive) shows
* only own governor.
*/
- if (df->governor->immutable) {
+ if (df->governor && df->governor->immutable) {
count = scnprintf(&buf[count], DEVFREQ_NAME_LEN,
"%s ", df->governor_name);
/*
* The devfreq device shows the registered governor except for
* immutable governors such as passive governor .
--
2.17.1
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* Re: Re: [PATCH 5/5] arm64: dts: imx8mq: add DCSS node
From: Laurentiu Palcu @ 2019-09-24 7:29 UTC (permalink / raw)
To: Fabio Estevam
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Sascha Hauer, linux-kernel, dl-linux-imx, Pengutronix Kernel Team,
Shawn Guo, Guido Günther,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Lucas Stach
In-Reply-To: <CAOMZO5AOVfBpz2Azh65iT_W3CBZUxf9KnqA=kdow7XWd4j--Qg@mail.gmail.com>
Hi Fabio,
On Mon, Sep 23, 2019 at 01:12:42PM -0300, Fabio Estevam wrote:
> Hi Laurentiu,
>
> On Mon, Sep 23, 2019 at 11:14 AM Laurentiu Palcu
> <laurentiu.palcu@nxp.com> wrote:
>
> > +
> > + dcss: dcss@0x32e00000 {
>
> Node names should be generic, so:
>
> dcss: display-controller@32e00000
fair enough, done.
>
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "nxp,imx8mq-dcss";
> > + reg = <0x32e00000 0x2D000>, <0x32e2f000 0x1000>;
>
> 0x2d000 for consistency.
will change this as well.
Thanks,
laurentiu
>
> > + interrupts = <6>, <8>, <9>;
>
> The interrupts are passed in the <GIC_SPI xxx IRQ_TYPE_LEVEL_HIGH> format.
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* [PATCH v3 0/5] Add support for mt2701 JPEG ENC support
From: Xia Jiang @ 2019-09-24 7:42 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
This patchset add support for mt2701 JPEG ENC support.
This is the compliance test result for jpeg dec and enc.
The JPEG dec log:
------------------------------------------------------------
v4l2-compliance -d /dev/video0
v4l2-compliance SHA: 847834c10d11b1cf67c95a8555115e4aa7b4f51b, 32 bits
Compliance test for mtk-jpeg device /dev/video0:
Driver Info:
Driver name : mtk-jpeg
Card type : mtk-jpeg decoder
Bus info : platform:15004000.jpegdec
Driver version : 5.3.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected JPEG Decoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for mtk-jpeg device /dev/video0: 44, Succeeded: 44, Failed: 0, Warnings: 0
------------------------------------------------------------
The JPEG enc log:
------------------------------------------------------------
v4l2-compliance -d /dev/video1
v4l2-compliance SHA: 847834c10d11b1cf67c95a8555115e4aa7b4f51b, 32 bits
Compliance test for mtk-jpeg device /dev/video1:
Driver Info:
Driver name : mtk-jpeg
Card type : mtk-jpeg encoder
Bus info : platform:1500a000.jpegenc
Driver version : 5.3.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected JPEG Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 4 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for mtk-jpeg device /dev/video1: 44, Succeeded: 44, Failed: 0, Warnings: 0
------------------------------------------------------------
Change compared to v2:
-delete Change-Id
-only test once handler->error after the last v4l2_ctrl_new_std()
-add a new separate patch for adding V4L2_CID_JPEG_ENABLE_EXIF
-change device tree node property compatible to an SoC specific compatible
-delete changing GPLv2 license to SPDX patch which new kernel has include
Xia Jiang (5):
media: dt-bindings: Add jpeg enc device tree node document
arm: dts: Add jpeg enc device tree node
media: platform: Rename jpeg dec file name
media: v4l2-ctrl: Add jpeg enc exif mode control
media: platform: Add jpeg dec/enc feature
.../bindings/media/mediatek-jpeg-encoder.txt | 37 +
.../media/uapi/v4l/ext-ctrls-jpeg.rst | 10 +
arch/arm/boot/dts/mt2701.dtsi | 13 +
drivers/media/platform/mtk-jpeg/Makefile | 5 +-
.../media/platform/mtk-jpeg/mtk_jpeg_core.c | 739 ++++++++++++++----
.../media/platform/mtk-jpeg/mtk_jpeg_core.h | 114 ++-
.../{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} | 2 +-
.../{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} | 9 +-
...{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} | 2 +-
...{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} | 2 +-
.../{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} | 0
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c | 175 +++++
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h | 60 ++
.../platform/mtk-jpeg/mtk_jpeg_enc_reg.h | 49 ++
drivers/media/v4l2-core/v4l2-ctrls.c | 1 +
include/uapi/linux/v4l2-controls.h | 2 +
16 files changed, 1044 insertions(+), 176 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} (99%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} (91%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} (98%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} (92%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} (100%)
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
--
2.18.0
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* [PATCH v3 1/5] media: dt-bindings: Add jpeg enc device tree node document
From: Xia Jiang @ 2019-09-24 7:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: Xia Jiang, devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-1-xia.jiang@mediatek.com>
Add jpeg enc device tree node document.
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
v3: change compatible to SoC specific compatible
v2: no changes
---
.../bindings/media/mediatek-jpeg-encoder.txt | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
new file mode 100644
index 000000000000..fa8da699493b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
@@ -0,0 +1,37 @@
+* MediaTek JPEG Encoder
+
+MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
+
+Required properties:
+- compatible : should be one of:
+ "mediatek,mt2701-jpgenc"
+ ...
+ followed by "mediatek,mtk-jpgenc"
+- reg : physical base address of the JPEG encoder registers and length of
+ memory mapped region.
+- interrupts : interrupt number to the interrupt controller.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,larb: must contain the local arbiters in the current SoCs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- iommus: should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+
+Example:
+ jpegenc: jpegenc@1500a000 {
+ compatible = "mediatek,mt2701-jpgenc",
+ "mediatek,mtk-jpgenc";
+ reg = <0 0x1500a000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_VENC>;
+ clock-names = "jpgenc";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
+ <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
+ };
--
2.18.0
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* [PATCH v3 2/5] arm: dts: Add jpeg enc device tree node
From: Xia Jiang @ 2019-09-24 7:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: Xia Jiang, devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-1-xia.jiang@mediatek.com>
Add jpeg enc device tree node.
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
v3: change compatible to SoC specific compatible
v2: no changes
---
arch/arm/boot/dts/mt2701.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 180377e56ef4..b9b370428f66 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -568,6 +568,19 @@
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
+ jpegenc: jpegenc@1500a000 {
+ compatible = "mediatek,mt2701-jpgenc",
+ "mediatek,mtk-jpgenc";
+ reg = <0 0x1500a000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_VENC>;
+ clock-names = "jpgenc";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
+ <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
--
2.18.0
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* [PATCH v3 3/5] media: platform: Rename jpeg dec file name
From: Xia Jiang @ 2019-09-24 7:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: Xia Jiang, devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-1-xia.jiang@mediatek.com>
Rename the files which are for decode feature. This is preparing
path since the jpeg enc patch will be added later.
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
v3: no changes
v2: no changes
---
drivers/media/platform/mtk-jpeg/Makefile | 2 +-
drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c | 4 ++--
.../platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} | 2 +-
.../platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} | 2 +-
.../mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} | 2 +-
.../mtk-jpeg/{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} | 2 +-
.../platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} | 0
7 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} (99%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} (98%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} (98%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} (92%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} (100%)
diff --git a/drivers/media/platform/mtk-jpeg/Makefile b/drivers/media/platform/mtk-jpeg/Makefile
index 92a4fc046bfe..48516dcf96e6 100644
--- a/drivers/media/platform/mtk-jpeg/Makefile
+++ b/drivers/media/platform/mtk-jpeg/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
-mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_hw.o mtk_jpeg_parse.o
+mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_dec_hw.o mtk_jpeg_dec_parse.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index ee802fc3bcdf..5f0990fce8ef 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -23,9 +23,9 @@
#include <media/videobuf2-dma-contig.h>
#include <soc/mediatek/smi.h>
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
#include "mtk_jpeg_core.h"
-#include "mtk_jpeg_parse.h"
+#include "mtk_jpeg_dec_parse.h"
static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
{
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
similarity index 99%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
index ddf0dfa78e20..922dbe421fae 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
@@ -9,7 +9,7 @@
#include <linux/kernel.h>
#include <media/videobuf2-core.h>
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
similarity index 98%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
index 9c6584eaad99..a37be1a48415 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
@@ -11,7 +11,7 @@
#include <media/videobuf2-core.h>
#include "mtk_jpeg_core.h"
-#include "mtk_jpeg_reg.h"
+#include "mtk_jpeg_dec_reg.h"
enum {
MTK_JPEG_DEC_RESULT_EOF_DONE = 0,
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
similarity index 98%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
index f862d38f3af7..b95c45791c29 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
@@ -8,7 +8,7 @@
#include <linux/kernel.h>
#include <linux/videodev2.h>
-#include "mtk_jpeg_parse.h"
+#include "mtk_jpeg_dec_parse.h"
#define TEM 0x01
#define SOF0 0xc0
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
similarity index 92%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
index 0a48eeabaff2..2918f15811f8 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
@@ -8,7 +8,7 @@
#ifndef _MTK_JPEG_PARSE_H
#define _MTK_JPEG_PARSE_H
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
bool mtk_jpeg_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va,
u32 src_size);
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
similarity index 100%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
--
2.18.0
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^ permalink raw reply related
* [PATCH v3 4/5] media: v4l2-ctrl: Add jpeg enc exif mode control
From: Xia Jiang @ 2019-09-24 7:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: Xia Jiang, devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-1-xia.jiang@mediatek.com>
Add jpeg enc CID definition for exif mode control.
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
v3: new add patch for V4L2_CID_JPEG_ENABLE_EXIF
---
Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst | 10 ++++++++++
drivers/media/v4l2-core/v4l2-ctrls.c | 1 +
include/uapi/linux/v4l2-controls.h | 2 ++
3 files changed, 13 insertions(+)
diff --git a/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst b/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
index 60ce3f949319..d44a539e2eb4 100644
--- a/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
+++ b/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
@@ -109,5 +109,15 @@ JPEG Control IDs
+``V4L2_CID_JPEG_ENABLE_EXIF (integer)``
+ ``V4L2_CID_JPEG_ENABLE_EXIF (integer)`` control determines JPEG
+ encoder mode. Its value of 0 means JPEG mode, 1 means EXIF mode. If
+ EXIF mode is enabled, the JPEG encoder will not write out SOI marker
+ (start from 0xffd8) but write out from DQT marker(start from
+ 0xffdb). Software program can fill the EXIF content above the DQT
+ marker to finish one EXIF JPEG.
+
+
+
For more details about JPEG specification, refer to :ref:`itu-t81`,
:ref:`jfif`, :ref:`w3c-jpeg-jfif`.
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index 371537dd8cd3..c96c10480ebd 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -1025,6 +1025,7 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_JPEG_RESTART_INTERVAL: return "Restart Interval";
case V4L2_CID_JPEG_COMPRESSION_QUALITY: return "Compression Quality";
case V4L2_CID_JPEG_ACTIVE_MARKER: return "Active Markers";
+ case V4L2_CID_JPEG_ENABLE_EXIF: return "Enable Exif";
/* Image source controls */
/* Keep the order of the 'case's the same as in v4l2-controls.h! */
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index a2669b79b294..da619f43de65 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -1022,6 +1022,8 @@ enum v4l2_jpeg_chroma_subsampling {
#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
+#define V4L2_CID_JPEG_ENABLE_EXIF (V4L2_CID_JPEG_CLASS_BASE + 5)
+
/* Image source controls */
#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
--
2.18.0
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^ permalink raw reply related
* Re: [PATCH] PM / devfreq: Lock devfreq in trans_stat_show
From: Leonard Crestez @ 2019-09-24 7:44 UTC (permalink / raw)
To: Chanwoo Choi, Matthias Kaehlcke
Cc: Artur Świgoń, linux-pm@vger.kernel.org,
Krzysztof Kozlowski, Lukasz Luba, Kyungmin Park, MyungJoo Ham,
dl-linux-imx, Georgi Djakov, linux-arm-kernel@lists.infradead.org
In-Reply-To: <979d107f-0a52-3aa4-a397-acb0ff754a3c@samsung.com>
On 2019-09-24 5:07 AM, Chanwoo Choi wrote:
> Hi,
>
> On 19. 9. 24. 오전 1:27, Leonard Crestez wrote:
>> There is no locking in this sysfs show function so stats printing can
>> race with a devfreq_update_status called as part of freq switching or
>> with initialization.
>>
>> Also add an assert in devfreq_update_status to make it clear that lock
>> must be held by caller.
>>
>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
>> ---
>> drivers/devfreq/devfreq.c | 13 ++++++++++---
>> 1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> Changes since v1:
>> * Split from series: low-priority bugfix not strictly required for PM QoS
>> * Only keep lock during update, release before sprintf
>>
>> diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
>> index 4c58fbf7d4e4..00fc23fea5b2 100644
>> --- a/drivers/devfreq/devfreq.c
>> +++ b/drivers/devfreq/devfreq.c
>> @@ -206,10 +206,11 @@ int devfreq_update_status(struct devfreq *devfreq, unsigned long freq)
>> {
>> int lev, prev_lev, ret = 0;
>> unsigned long cur_time;
>>
>> cur_time = jiffies;
>> + lockdep_assert_held(&devfreq->lock);
>
> It better to move lock checking before 'cur_time = jiffies'
> in order to reduce the redundant code execution.
OK but I don't see how this makes a difference for an assert? It just
prints a warning and carries on.
>> /* Immediately exit if previous_freq is not initialized yet. */
>> if (!devfreq->previous_freq)
>> goto out;
>>
>> @@ -1507,16 +1508,22 @@ static ssize_t trans_stat_show(struct device *dev,
>> struct devfreq *devfreq = to_devfreq(dev);
>> ssize_t len;
>> int i, j;
>> unsigned int max_state = devfreq->profile->max_state;
>>
>> - if (!devfreq->stop_polling &&
>> - devfreq_update_status(devfreq, devfreq->previous_freq))
>> - return 0;
>> if (max_state == 0)
>> return sprintf(buf, "Not Supported.\n");
>>
>> + /* lock and update */
>
> It is not necessary. Anyone can know that this code is related to mutex lock/unlock.
OK. You're the second person to mention this but it's quite strange to
see objections raised against comments.
>> + mutex_lock(&devfreq->lock);
>> + if (!devfreq->stop_polling &&
>> + devfreq_update_status(devfreq, devfreq->previous_freq)) {
>> + mutex_unlock(&devfreq->lock);
>> + return 0;
>> + }
>> + mutex_unlock(&devfreq->lock);
>> +
>> len = sprintf(buf, " From : To\n");
>> len += sprintf(buf + len, " :");
>> for (i = 0; i < max_state; i++)
>> len += sprintf(buf + len, "%10lu",
>> devfreq->profile->freq_table[i]);
>>
>
> Basically, it is necessary. Please edit it by my comments.
> Also, you have to add the following 'fixes' as following:
> and send it stable mailing list.
>
> Fixes: 39688ce6facd ("PM / devfreq: account suspend/resume for stats")
>
> If you edit it by my comments, feel free to add my tag:
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
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^ permalink raw reply
* [PATCH v3 5/5] media: platform: Add jpeg dec/enc feature
From: Xia Jiang @ 2019-09-24 7:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Rick Chang
Cc: Xia Jiang, devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-1-xia.jiang@mediatek.com>
Add mtk jpeg encode v4l2 driver based on jpeg decode, because that jpeg
decode and encode have great similarities with function operation.
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
v3: delete Change-Id
only test once handler->error after the last v4l2_ctrl_new_std()
seperate changes of v4l2-ctrls.c and v4l2-controls.h to new patch
v2: fix compliance test fail, check created buffer size in driver
---
drivers/media/platform/mtk-jpeg/Makefile | 5 +-
.../media/platform/mtk-jpeg/mtk_jpeg_core.c | 735 ++++++++++++++----
.../media/platform/mtk-jpeg/mtk_jpeg_core.h | 114 ++-
.../media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h | 7 +-
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c | 175 +++++
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h | 60 ++
.../platform/mtk-jpeg/mtk_jpeg_enc_reg.h | 49 ++
7 files changed, 975 insertions(+), 170 deletions(-)
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
diff --git a/drivers/media/platform/mtk-jpeg/Makefile b/drivers/media/platform/mtk-jpeg/Makefile
index 48516dcf96e6..76c33aad0f3f 100644
--- a/drivers/media/platform/mtk-jpeg/Makefile
+++ b/drivers/media/platform/mtk-jpeg/Makefile
@@ -1,3 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_dec_hw.o mtk_jpeg_dec_parse.o
+mtk_jpeg-objs := mtk_jpeg_core.o \
+ mtk_jpeg_dec_hw.o \
+ mtk_jpeg_dec_parse.o \
+ mtk_jpeg_enc_hw.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index 5f0990fce8ef..aa18b01802ed 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -3,6 +3,7 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*/
#include <linux/clk.h>
@@ -23,6 +24,7 @@
#include <media/videobuf2-dma-contig.h>
#include <soc/mediatek/smi.h>
+#include "mtk_jpeg_enc_hw.h"
#include "mtk_jpeg_dec_hw.h"
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_parse.h"
@@ -31,7 +33,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
{
.fourcc = V4L2_PIX_FMT_JPEG,
.colplanes = 1,
- .flags = MTK_JPEG_FMT_FLAG_DEC_OUTPUT,
+ .flags = MTK_JPEG_FMT_FLAG_DEC_OUTPUT |
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE,
},
{
.fourcc = V4L2_PIX_FMT_YUV420M,
@@ -51,6 +54,42 @@ static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
.v_align = 3,
.flags = MTK_JPEG_FMT_FLAG_DEC_CAPTURE,
},
+ {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 2, 2},
+ .colplanes = 2,
+ .h_align = 4,
+ .v_align = 4,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 2, 2},
+ .colplanes = 2,
+ .h_align = 4,
+ .v_align = 4,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 4, 4},
+ .colplanes = 1,
+ .h_align = 4,
+ .v_align = 3,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 4, 4},
+ .colplanes = 1,
+ .h_align = 4,
+ .v_align = 3,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
};
#define MTK_JPEG_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_formats)
@@ -65,11 +104,19 @@ struct mtk_jpeg_src_buf {
struct list_head list;
int flags;
struct mtk_jpeg_dec_param dec_param;
+ struct mtk_jpeg_enc_param enc_param;
};
+#define MTK_MAX_CTRLS_HINT 20
+
static int debug;
module_param(debug, int, 0644);
+static inline struct mtk_jpeg_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
+{
+ return container_of(ctrl->handler, struct mtk_jpeg_ctx, ctrl_hdl);
+}
+
static inline struct mtk_jpeg_ctx *mtk_jpeg_fh_to_ctx(struct v4l2_fh *fh)
{
return container_of(fh, struct mtk_jpeg_ctx, fh);
@@ -86,10 +133,70 @@ static int mtk_jpeg_querycap(struct file *file, void *priv,
{
struct mtk_jpeg_dev *jpeg = video_drvdata(file);
- strscpy(cap->driver, MTK_JPEG_NAME " decoder", sizeof(cap->driver));
- strscpy(cap->card, MTK_JPEG_NAME " decoder", sizeof(cap->card));
- snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
- dev_name(jpeg->dev));
+ strscpy(cap->driver, MTK_JPEG_NAME, sizeof(cap->driver));
+ if (jpeg->mode == MTK_JPEG_ENC)
+ strscpy(cap->card, MTK_JPEG_NAME " encoder", sizeof(cap->card));
+ else
+ strscpy(cap->card, MTK_JPEG_NAME " decoder", sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+ dev_name(jpeg->dev));
+
+ return 0;
+}
+
+static int vidioc_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct mtk_jpeg_ctx *ctx = ctrl_to_ctx(ctrl);
+ struct jpeg_enc_param *p = &ctx->jpeg_param;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ int ret = 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_JPEG_RESTART_INTERVAL:
+ p->restart_interval = ctrl->val;
+ break;
+ case V4L2_CID_JPEG_COMPRESSION_QUALITY:
+ p->enc_quality = ctrl->val;
+ break;
+ case V4L2_CID_JPEG_ENABLE_EXIF:
+ p->enable_exif = ctrl->val;
+ break;
+ }
+
+ v4l2_dbg(2, debug, &jpeg->v4l2_dev, "%s val = %d",
+ v4l2_ctrl_get_name(ctrl->id), ctrl->val);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops mtk_jpeg_ctrl_ops = {
+ .s_ctrl = vidioc_jpeg_s_ctrl,
+};
+
+int mtk_jpeg_ctrls_setup(struct mtk_jpeg_ctx *ctx)
+{
+ const struct v4l2_ctrl_ops *ops = &mtk_jpeg_ctrl_ops;
+ struct v4l2_ctrl_handler *handler = &ctx->ctrl_hdl;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+
+ v4l2_ctrl_handler_init(handler, MTK_MAX_CTRLS_HINT);
+
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ v4l2_ctrl_new_std(handler, ops, V4L2_CID_JPEG_RESTART_INTERVAL,
+ 0, 100, 1, 0);
+ v4l2_ctrl_new_std(handler, ops,
+ V4L2_CID_JPEG_COMPRESSION_QUALITY, 48, 100, 1,
+ 90);
+ v4l2_ctrl_new_std(handler, ops, V4L2_CID_JPEG_ENABLE_EXIF, 0,
+ 1, 1, 0);
+
+ if (handler->error) {
+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
+ return handler->error;
+ }
+ }
+
+ v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
return 0;
}
@@ -118,23 +225,29 @@ static int mtk_jpeg_enum_fmt(struct mtk_jpeg_fmt *mtk_jpeg_formats, int n,
static int mtk_jpeg_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
+ struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
+
return mtk_jpeg_enum_fmt(mtk_jpeg_formats, MTK_JPEG_NUM_FORMATS, f,
+ ctx->jpeg->mode == MTK_JPEG_ENC ?
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE :
MTK_JPEG_FMT_FLAG_DEC_CAPTURE);
}
static int mtk_jpeg_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
+ struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
+
return mtk_jpeg_enum_fmt(mtk_jpeg_formats, MTK_JPEG_NUM_FORMATS, f,
+ ctx->jpeg->mode == MTK_JPEG_ENC ?
+ MTK_JPEG_FMT_FLAG_ENC_OUTPUT :
MTK_JPEG_FMT_FLAG_DEC_OUTPUT);
}
-static struct mtk_jpeg_q_data *mtk_jpeg_get_q_data(struct mtk_jpeg_ctx *ctx,
- enum v4l2_buf_type type)
+static struct mtk_jpeg_q_data *
+mtk_jpeg_get_q_data(struct mtk_jpeg_ctx *ctx, enum v4l2_buf_type type)
{
- if (V4L2_TYPE_IS_OUTPUT(type))
- return &ctx->out_q;
- return &ctx->cap_q;
+ return V4L2_TYPE_IS_OUTPUT(type) ? &ctx->out_q : &ctx->cap_q;
}
static struct mtk_jpeg_fmt *mtk_jpeg_find_format(struct mtk_jpeg_ctx *ctx,
@@ -143,9 +256,14 @@ static struct mtk_jpeg_fmt *mtk_jpeg_find_format(struct mtk_jpeg_ctx *ctx,
{
unsigned int k, fmt_flag;
- fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
- MTK_JPEG_FMT_FLAG_DEC_OUTPUT :
- MTK_JPEG_FMT_FLAG_DEC_CAPTURE;
+ if (ctx->jpeg->mode == MTK_JPEG_ENC)
+ fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
+ MTK_JPEG_FMT_FLAG_ENC_OUTPUT :
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE;
+ else
+ fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
+ MTK_JPEG_FMT_FLAG_DEC_OUTPUT :
+ MTK_JPEG_FMT_FLAG_DEC_CAPTURE;
for (k = 0; k < MTK_JPEG_NUM_FORMATS; k++) {
struct mtk_jpeg_fmt *fmt = &mtk_jpeg_formats[k];
@@ -202,7 +320,7 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_format *f,
{
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
- int i;
+ int i, align_w, align_h;
memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved));
pix_mp->field = V4L2_FIELD_NONE;
@@ -216,36 +334,111 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_format *f,
pix_mp->pixelformat = fmt->fourcc;
if (q_type == MTK_JPEG_FMT_TYPE_OUTPUT) {
- struct v4l2_plane_pix_format *pfmt = &pix_mp->plane_fmt[0];
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ pix_mp->height = clamp(pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT);
+ pix_mp->width = clamp(pix_mp->width,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH);
+ align_w = pix_mp->width;
+ align_h = pix_mp->height;
+ align_w = round_up(align_w, 2);
+ if (pix_mp->num_planes == 1U) {
+ align_w = align_w << 1;
+ mtk_jpeg_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH,
+ 5, &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT,
+ 3);
+ pix_mp->plane_fmt[0].bytesperline = align_w;
+ pix_mp->plane_fmt[0].sizeimage =
+ align_w * align_h;
+ } else if (pix_mp->num_planes == 2U) {
+ mtk_jpeg_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH,
+ 4, &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT,
+ 4);
+ pix_mp->plane_fmt[0].bytesperline = align_w;
+ pix_mp->plane_fmt[0].sizeimage =
+ align_w * align_h;
+ pix_mp->plane_fmt[1].bytesperline = align_w;
+ pix_mp->plane_fmt[1].sizeimage =
+ (align_w * align_h) / 2;
+ } else {
+ v4l2_err(&ctx->jpeg->v4l2_dev,
+ "Unsupport num planes = %d\n",
+ pix_mp->num_planes);
+ }
+ goto end;
+ } else {
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[0];
+
+ mtk_jpeg_bound_align_image(&pix_mp->width,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, 0,
+ &pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, 0);
+
+ pfmt->bytesperline = 0;
+ /* Source size must be aligned to 128 */
+ pfmt->sizeimage = mtk_jpeg_align(pfmt->sizeimage, 128);
+ if (pfmt->sizeimage == 0)
+ pfmt->sizeimage = MTK_JPEG_DEFAULT_SIZEIMAGE;
+
+ goto end;
+ }
+ }
+ /* type is MTK_JPEG_FMT_TYPE_CAPTURE */
+ if (jpeg->mode == MTK_JPEG_ENC) {
mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
MTK_JPEG_MAX_WIDTH, 0,
&pix_mp->height, MTK_JPEG_MIN_HEIGHT,
MTK_JPEG_MAX_HEIGHT, 0);
- memset(pfmt->reserved, 0, sizeof(pfmt->reserved));
- pfmt->bytesperline = 0;
- /* Source size must be aligned to 128 */
- pfmt->sizeimage = mtk_jpeg_align(pfmt->sizeimage, 128);
- if (pfmt->sizeimage == 0)
- pfmt->sizeimage = MTK_JPEG_DEFAULT_SIZEIMAGE;
- goto end;
+ if (fmt->fourcc == V4L2_PIX_FMT_JPEG) {
+ pix_mp->plane_fmt[0].bytesperline = 0;
+ pix_mp->plane_fmt[0].sizeimage =
+ mtk_jpeg_align(pix_mp->plane_fmt[0].sizeimage,
+ 128);
+ if (pix_mp->plane_fmt[0].sizeimage == 0)
+ pix_mp->plane_fmt[0].sizeimage =
+ MTK_JPEG_DEFAULT_SIZEIMAGE;
+ }
+ } else {
+ pix_mp->height = clamp(pix_mp->height, MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT);
+ pix_mp->width = clamp(pix_mp->width, MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH);
+ mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, fmt->h_align,
+ &pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, fmt->v_align);
+
+ for (i = 0; i < fmt->colplanes; i++) {
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[i];
+ u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
+ u32 h = pix_mp->height * fmt->v_sample[i] / 4;
+
+ pfmt->bytesperline = stride;
+ pfmt->sizeimage = stride * h;
+ }
}
- /* type is MTK_JPEG_FMT_TYPE_CAPTURE */
- mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
- MTK_JPEG_MAX_WIDTH, fmt->h_align,
- &pix_mp->height, MTK_JPEG_MIN_HEIGHT,
- MTK_JPEG_MAX_HEIGHT, fmt->v_align);
-
for (i = 0; i < fmt->colplanes; i++) {
- struct v4l2_plane_pix_format *pfmt = &pix_mp->plane_fmt[i];
- u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
- u32 h = pix_mp->height * fmt->v_sample[i] / 4;
-
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[i];
memset(pfmt->reserved, 0, sizeof(pfmt->reserved));
- pfmt->bytesperline = stride;
- pfmt->sizeimage = stride * h;
}
end:
v4l2_dbg(2, debug, &jpeg->v4l2_dev, "wxh:%ux%u\n",
@@ -446,9 +639,9 @@ static int mtk_jpeg_subscribe_event(struct v4l2_fh *fh,
switch (sub->type) {
case V4L2_EVENT_SOURCE_CHANGE:
return v4l2_src_change_event_subscribe(fh, sub);
- default:
- return -EINVAL;
}
+
+ return v4l2_ctrl_subscribe_event(fh, sub);
}
static int mtk_jpeg_g_selection(struct file *file, void *priv,
@@ -571,6 +764,13 @@ static int mtk_jpeg_queue_setup(struct vb2_queue *q,
if (!q_data)
return -EINVAL;
+ if (*num_planes) {
+ for (i = 0; i < *num_planes; i++)
+ if (sizes[i] < q_data->sizeimage[i])
+ return -EINVAL;
+ return 0;
+ }
+
*num_planes = q_data->fmt->colplanes;
for (i = 0; i < q_data->fmt->colplanes; i++) {
sizes[i] = q_data->sizeimage[i];
@@ -651,10 +851,92 @@ static void mtk_jpeg_set_queue_data(struct mtk_jpeg_ctx *ctx,
param->dec_w, param->dec_h);
}
+static void mtk_jpeg_set_param(struct mtk_jpeg_ctx *ctx,
+ struct mtk_jpeg_enc_param *param)
+{
+ struct mtk_jpeg_q_data *q_data_src = &ctx->out_q;
+ struct jpeg_enc_param *jpeg_params = &ctx->jpeg_param;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ u32 width_even;
+ u32 is_420;
+ u32 padding_width;
+ u32 padding_height;
+
+ switch (q_data_src->fmt->fourcc) {
+ case V4L2_PIX_FMT_YUYV:
+ param->enc_format = JPEG_YUV_FORMAT_YUYV;
+ break;
+ case V4L2_PIX_FMT_YVYU:
+ param->enc_format = JPEG_YUV_FORMAT_YVYU;
+ break;
+ case V4L2_PIX_FMT_NV12M:
+ param->enc_format = JPEG_YUV_FORMAT_NV12;
+ break;
+ case V4L2_PIX_FMT_NV21M:
+ param->enc_format = JPEG_YUV_FORMAT_NV12;
+ break;
+ default:
+ v4l2_err(&jpeg->v4l2_dev, "Unsupport fourcc =%d\n",
+ q_data_src->fmt->fourcc);
+ break;
+ }
+ param->enc_w = q_data_src->w;
+ param->enc_h = q_data_src->h;
+
+ if (jpeg_params->enc_quality >= 97)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q97;
+ else if (jpeg_params->enc_quality >= 95)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q95;
+ else if (jpeg_params->enc_quality >= 92)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q92;
+ else if (jpeg_params->enc_quality >= 90)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q90;
+ else if (jpeg_params->enc_quality >= 87)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q87;
+ else if (jpeg_params->enc_quality >= 84)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q84;
+ else if (jpeg_params->enc_quality >= 80)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q80;
+ else if (jpeg_params->enc_quality >= 74)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q74;
+ else if (jpeg_params->enc_quality >= 64)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q64;
+ else if (jpeg_params->enc_quality >= 60)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q60;
+ else
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q48;
+
+ param->enable_exif = jpeg_params->enable_exif;
+ param->restart_interval = jpeg_params->restart_interval;
+
+ width_even = ((param->enc_w + 1) >> 1) << 1;
+ is_420 = (param->enc_format == JPEG_YUV_FORMAT_NV12 ||
+ param->enc_format == JPEG_YUV_FORMAT_NV12) ? 1 : 0;
+ padding_width = mtk_jpeg_align(param->enc_w, 16);
+ padding_height = mtk_jpeg_align(param->enc_h, is_420 ? 16 : 8);
+ if (!is_420)
+ width_even = width_even << 1;
+
+ param->img_stride = mtk_jpeg_align(width_even, (is_420 ? 16 : 32));
+ param->mem_stride = mtk_jpeg_align(width_even, (is_420 ? 16 : 32));
+ param->total_encdu =
+ ((padding_width >> 4) * (padding_height >> (is_420 ? 4 : 3)) *
+ (is_420 ? 6 : 4)) - 1;
+
+ v4l2_dbg(0, 2, &jpeg->v4l2_dev, "fmt %d, w,h %d,%d, enable_exif %d,",
+ "enc_quality %d, restart_interval %d,img_stride %d,",
+ "mem_stride %d,totalEncDu %d\n",
+ param->enc_format, param->enc_w, param->enc_h,
+ param->enable_exif, param->enc_quality,
+ param->restart_interval, param->img_stride,
+ param->mem_stride, param->total_encdu);
+}
+
static void mtk_jpeg_buf_queue(struct vb2_buffer *vb)
{
struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct mtk_jpeg_dec_param *param;
+ struct mtk_jpeg_enc_param *enc_param;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
struct mtk_jpeg_src_buf *jpeg_src_buf;
bool header_valid;
@@ -666,29 +948,45 @@ static void mtk_jpeg_buf_queue(struct vb2_buffer *vb)
goto end;
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(vb);
- param = &jpeg_src_buf->dec_param;
- memset(param, 0, sizeof(*param));
-
- if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
- v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos\n");
- goto end;
- }
- header_valid = mtk_jpeg_parse(param, (u8 *)vb2_plane_vaddr(vb, 0),
- vb2_get_plane_payload(vb, 0));
- if (!header_valid) {
- v4l2_err(&jpeg->v4l2_dev, "Header invalid.\n");
- vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
- return;
- }
-
- if (ctx->state == MTK_JPEG_INIT) {
- struct vb2_queue *dst_vq = v4l2_m2m_get_vq(
- ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ enc_param = &jpeg_src_buf->enc_param;
+ memset(enc_param, 0, sizeof(*enc_param));
+ mtk_jpeg_set_param(ctx, enc_param);
+ if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
+ v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos");
+ goto end;
+ }
+ if (ctx->state == MTK_JPEG_INIT)
+ ctx->state = MTK_JPEG_RUNNING;
+ } else {
+ param = &jpeg_src_buf->dec_param;
+ memset(param, 0, sizeof(*param));
+
+ if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
+ v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos\n");
+ goto end;
+ }
+ header_valid = mtk_jpeg_parse(param,
+ (u8 *)vb2_plane_vaddr(vb, 0),
+ vb2_get_plane_payload(vb, 0));
+ if (!header_valid) {
+ v4l2_err(&jpeg->v4l2_dev, "Header invalid.\n");
+ vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
+ return;
+ }
- mtk_jpeg_queue_src_chg_event(ctx);
- mtk_jpeg_set_queue_data(ctx, param);
- ctx->state = vb2_is_streaming(dst_vq) ?
- MTK_JPEG_SOURCE_CHANGE : MTK_JPEG_RUNNING;
+ if (ctx->state == MTK_JPEG_INIT) {
+ struct vb2_queue *dst_vq;
+
+ dst_vq = v4l2_m2m_get_vq
+ (ctx->fh.m2m_ctx,
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ mtk_jpeg_queue_src_chg_event(ctx);
+ mtk_jpeg_set_queue_data(ctx, param);
+ ctx->state = vb2_is_streaming(dst_vq) ?
+ MTK_JPEG_SOURCE_CHANGE :
+ MTK_JPEG_RUNNING;
+ }
}
end:
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, to_vb2_v4l2_buffer(vb));
@@ -731,16 +1029,16 @@ static void mtk_jpeg_stop_streaming(struct vb2_queue *q)
* subsampling. Update capture queue when the stream is off.
*/
if (ctx->state == MTK_JPEG_SOURCE_CHANGE &&
- !V4L2_TYPE_IS_OUTPUT(q->type)) {
+ !V4L2_TYPE_IS_OUTPUT(q->type) &&
+ ctx->jpeg->mode == MTK_JPEG_DEC) {
struct mtk_jpeg_src_buf *src_buf;
vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
src_buf = mtk_jpeg_vb2_to_srcbuf(&vb->vb2_buf);
mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
ctx->state = MTK_JPEG_RUNNING;
- } else if (V4L2_TYPE_IS_OUTPUT(q->type)) {
+ } else if (V4L2_TYPE_IS_OUTPUT(q->type))
ctx->state = MTK_JPEG_INIT;
- }
while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
@@ -795,6 +1093,28 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx *ctx,
return 0;
}
+static void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx,
+ struct vb2_buffer *dst_buf,
+ struct mtk_jpeg_enc_bs *bs)
+{
+ bs->dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0) &
+ (~JPEG_ENC_DST_ADDR_OFFSET_MASK);
+ bs->dma_addr_offset = 0;
+ bs->dma_addr_offsetmask = bs->dma_addr & JPEG_ENC_DST_ADDR_OFFSET_MASK;
+ bs->size = mtk_jpeg_align(vb2_plane_size(dst_buf, 0), 128);
+}
+
+static void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx,
+ struct vb2_buffer *src_buf,
+ struct mtk_jpeg_enc_fb *fb)
+{
+ int i;
+
+ for (i = 0; i < src_buf->num_planes; i++)
+ fb->fb_addr[i].dma_addr =
+ vb2_dma_contig_plane_dma_addr(src_buf, i);
+}
+
static void mtk_jpeg_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
@@ -805,6 +1125,8 @@ static void mtk_jpeg_device_run(void *priv)
struct mtk_jpeg_src_buf *jpeg_src_buf;
struct mtk_jpeg_bs bs;
struct mtk_jpeg_fb fb;
+ struct mtk_jpeg_enc_bs enc_bs;
+ struct mtk_jpeg_enc_fb enc_fb;
int i;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
@@ -815,30 +1137,45 @@ static void mtk_jpeg_device_run(void *priv)
for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&dst_buf->vb2_buf, i, 0);
buf_state = VB2_BUF_STATE_DONE;
- goto dec_end;
+ goto device_run_end;
}
- if (mtk_jpeg_check_resolution_change(ctx, &jpeg_src_buf->dec_param)) {
- mtk_jpeg_queue_src_chg_event(ctx);
- ctx->state = MTK_JPEG_SOURCE_CHANGE;
- v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
- return;
- }
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ mtk_jpeg_set_enc_dst(ctx, &dst_buf->vb2_buf, &enc_bs);
+ mtk_jpeg_set_enc_src(ctx, &src_buf->vb2_buf, &enc_fb);
+
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ mtk_jpeg_enc_set_config(jpeg->reg_base,
+ &jpeg_src_buf->enc_param, &enc_bs,
+ &enc_fb);
+
+ mtk_jpeg_enc_start(jpeg->reg_base);
+ } else {
+ if (mtk_jpeg_check_resolution_change
+ (ctx, &jpeg_src_buf->dec_param)) {
+ mtk_jpeg_queue_src_chg_event(ctx);
+ ctx->state = MTK_JPEG_SOURCE_CHANGE;
+ v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+ return;
+ }
- mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
- if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param, &dst_buf->vb2_buf, &fb))
- goto dec_end;
+ mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
+ if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param,
+ &dst_buf->vb2_buf, &fb))
+ goto device_run_end;
- spin_lock_irqsave(&jpeg->hw_lock, flags);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
- mtk_jpeg_dec_set_config(jpeg->dec_reg_base,
- &jpeg_src_buf->dec_param, &bs, &fb);
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+ mtk_jpeg_dec_set_config(jpeg->reg_base,
+ &jpeg_src_buf->dec_param, &bs, &fb);
- mtk_jpeg_dec_start(jpeg->dec_reg_base);
+ mtk_jpeg_dec_start(jpeg->reg_base);
+ }
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return;
-dec_end:
+device_run_end:
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, buf_state);
@@ -898,30 +1235,30 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
ret = mtk_smi_larb_get(jpeg->larb);
if (ret)
dev_err(jpeg->dev, "mtk_smi_larb_get larbvdec fail %d\n", ret);
- clk_prepare_enable(jpeg->clk_jdec_smi);
- clk_prepare_enable(jpeg->clk_jdec);
+ if (jpeg->mode == MTK_JPEG_DEC)
+ clk_prepare_enable(jpeg->clk_jpeg_smi);
+ clk_prepare_enable(jpeg->clk_jpeg);
}
static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg)
{
- clk_disable_unprepare(jpeg->clk_jdec);
- clk_disable_unprepare(jpeg->clk_jdec_smi);
+ clk_disable_unprepare(jpeg->clk_jpeg);
+ if (jpeg->mode == MTK_JPEG_DEC)
+ clk_disable_unprepare(jpeg->clk_jpeg_smi);
mtk_smi_larb_put(jpeg->larb);
}
-static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
+static irqreturn_t mtk_jpeg_irq(int irq, void *priv)
{
struct mtk_jpeg_dev *jpeg = priv;
struct mtk_jpeg_ctx *ctx;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mtk_jpeg_src_buf *jpeg_src_buf;
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
- u32 dec_irq_ret;
- u32 dec_ret;
+ u32 irq_ret;
+ u32 ret, result_size;
int i;
- dec_ret = mtk_jpeg_dec_get_int_status(jpeg->dec_reg_base);
- dec_irq_ret = mtk_jpeg_dec_enum_result(dec_ret);
ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev);
if (!ctx) {
v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n");
@@ -932,21 +1269,42 @@ static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
- if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ ret = mtk_jpeg_enc_get_int_status(jpeg->reg_base);
+ irq_ret = mtk_jpeg_enc_enum_result(jpeg->reg_base, ret,
+ &result_size);
- if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) {
- dev_err(jpeg->dev, "decode failed\n");
- goto dec_end;
- }
+ if (irq_ret >= MTK_JPEG_ENC_RESULT_STALL)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+
+ if (irq_ret != MTK_JPEG_ENC_RESULT_DONE) {
+ dev_err(jpeg->dev, "encode failed\n");
+ goto irq_end;
+ }
- for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
- vb2_set_plane_payload(&dst_buf->vb2_buf, i,
- jpeg_src_buf->dec_param.comp_size[i]);
+ vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
+ result_size);
+ } else {
+ ret = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
+ irq_ret = mtk_jpeg_dec_enum_result(ret);
+
+ if (irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+
+ if (irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) {
+ dev_err(jpeg->dev, "decode failed\n");
+ goto irq_end;
+ }
+
+ for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
+ vb2_set_plane_payload
+ (&dst_buf->vb2_buf, i,
+ jpeg_src_buf->dec_param.comp_size[i]);
+ }
buf_state = VB2_BUF_STATE_DONE;
-dec_end:
+irq_end:
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
@@ -956,32 +1314,72 @@ static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
static void mtk_jpeg_set_default_params(struct mtk_jpeg_ctx *ctx)
{
struct mtk_jpeg_q_data *q = &ctx->out_q;
- int i;
+ int i, align_w, align_h;
+
+ ctx->fh.ctrl_handler = &ctx->ctrl_hdl;
ctx->colorspace = V4L2_COLORSPACE_JPEG,
ctx->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
ctx->quantization = V4L2_QUANTIZATION_DEFAULT;
ctx->xfer_func = V4L2_XFER_FUNC_DEFAULT;
- q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
+ if (ctx->jpeg->mode == MTK_JPEG_ENC) {
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUYV,
MTK_JPEG_FMT_TYPE_OUTPUT);
- q->w = MTK_JPEG_MIN_WIDTH;
- q->h = MTK_JPEG_MIN_HEIGHT;
- q->bytesperline[0] = 0;
- q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+
+ align_w = q->w;
+ align_h = q->h;
+ align_w = round_up(align_w, 2);
+ align_w = align_w << 1;
+ v4l_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, 5,
+ &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, 3, 0);
+
+ if (align_w < MTK_JPEG_MIN_WIDTH &&
+ (align_w + 32) <= MTK_JPEG_MAX_WIDTH)
+ align_w += 32;
+ if (align_h < MTK_JPEG_MIN_HEIGHT &&
+ (align_h + 8) <= MTK_JPEG_MAX_HEIGHT)
+ align_h += 8;
+
+ q->sizeimage[0] = align_w * align_h;
+ q->bytesperline[0] = align_w;
+ } else {
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
+ MTK_JPEG_FMT_TYPE_OUTPUT);
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+ q->bytesperline[0] = 0;
+ q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+ }
q = &ctx->cap_q;
- q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUV420M,
+ if (ctx->jpeg->mode == MTK_JPEG_ENC) {
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
+ MTK_JPEG_FMT_TYPE_CAPTURE);
+ q->bytesperline[0] = 0;
+ q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+ } else {
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUV420M,
MTK_JPEG_FMT_TYPE_CAPTURE);
- q->w = MTK_JPEG_MIN_WIDTH;
- q->h = MTK_JPEG_MIN_HEIGHT;
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
- for (i = 0; i < q->fmt->colplanes; i++) {
- u32 stride = q->w * q->fmt->h_sample[i] / 4;
- u32 h = q->h * q->fmt->v_sample[i] / 4;
+ for (i = 0; i < q->fmt->colplanes; i++) {
+ u32 stride = q->w * q->fmt->h_sample[i] / 4;
+ u32 h = q->h * q->fmt->v_sample[i] / 4;
- q->bytesperline[i] = stride;
- q->sizeimage[i] = stride * h;
+ q->bytesperline[i] = stride;
+ q->sizeimage[i] = stride * h;
+ }
}
}
@@ -1013,6 +1411,13 @@ static int mtk_jpeg_open(struct file *file)
goto error;
}
+ ret = mtk_jpeg_ctrls_setup(ctx);
+ if (ret) {
+ v4l2_err(&jpeg->v4l2_dev, "Failed to setup controls() (%d)\n",
+ ret);
+ goto error;
+ }
+
mtk_jpeg_set_default_params(ctx);
mutex_unlock(&jpeg->lock);
return 0;
@@ -1033,6 +1438,7 @@ static int mtk_jpeg_release(struct file *file)
mutex_lock(&jpeg->lock);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
kfree(ctx);
@@ -1057,6 +1463,7 @@ static int mtk_jpeg_clk_init(struct mtk_jpeg_dev *jpeg)
node = of_parse_phandle(jpeg->dev->of_node, "mediatek,larb", 0);
if (!node)
return -EINVAL;
+
pdev = of_find_device_by_node(node);
if (WARN_ON(!pdev)) {
of_node_put(node);
@@ -1066,19 +1473,24 @@ static int mtk_jpeg_clk_init(struct mtk_jpeg_dev *jpeg)
jpeg->larb = &pdev->dev;
- jpeg->clk_jdec = devm_clk_get(jpeg->dev, "jpgdec");
- if (IS_ERR(jpeg->clk_jdec))
- return PTR_ERR(jpeg->clk_jdec);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ jpeg->clk_jpeg = devm_clk_get(jpeg->dev, "jpgenc");
+ return PTR_ERR_OR_ZERO(jpeg->clk_jpeg);
+ }
+
+ jpeg->clk_jpeg = devm_clk_get(jpeg->dev, "jpgdec");
+ if (IS_ERR(jpeg->clk_jpeg))
+ return PTR_ERR(jpeg->clk_jpeg);
- jpeg->clk_jdec_smi = devm_clk_get(jpeg->dev, "jpgdec-smi");
- return PTR_ERR_OR_ZERO(jpeg->clk_jdec_smi);
+ jpeg->clk_jpeg_smi = devm_clk_get(jpeg->dev, "jpgdec-smi");
+ return PTR_ERR_OR_ZERO(jpeg->clk_jpeg_smi);
}
static int mtk_jpeg_probe(struct platform_device *pdev)
{
struct mtk_jpeg_dev *jpeg;
struct resource *res;
- int dec_irq;
+ int jpeg_irq;
int ret;
jpeg = devm_kzalloc(&pdev->dev, sizeof(*jpeg), GFP_KERNEL);
@@ -1088,28 +1500,26 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
mutex_init(&jpeg->lock);
spin_lock_init(&jpeg->hw_lock);
jpeg->dev = &pdev->dev;
+ jpeg->mode = (enum mtk_jpeg_mode)of_device_get_match_data(jpeg->dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- jpeg->dec_reg_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(jpeg->dec_reg_base)) {
- ret = PTR_ERR(jpeg->dec_reg_base);
+ jpeg->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(jpeg->reg_base)) {
+ ret = PTR_ERR(jpeg->reg_base);
return ret;
}
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- dec_irq = platform_get_irq(pdev, 0);
- if (!res || dec_irq < 0) {
- dev_err(&pdev->dev, "Failed to get dec_irq %d.\n", dec_irq);
- ret = -EINVAL;
- return ret;
+ jpeg_irq = platform_get_irq(pdev, 0);
+ if (jpeg_irq < 0) {
+ dev_err(&pdev->dev, "Failed to get jpeg_irq %d.\n", jpeg_irq);
+ return jpeg_irq;
}
- ret = devm_request_irq(&pdev->dev, dec_irq, mtk_jpeg_dec_irq, 0,
+ ret = devm_request_irq(&pdev->dev, jpeg_irq, mtk_jpeg_irq, 0,
pdev->name, jpeg);
if (ret) {
- dev_err(&pdev->dev, "Failed to request dec_irq %d (%d)\n",
- dec_irq, ret);
- ret = -EINVAL;
+ dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n",
+ jpeg_irq, ret);
goto err_req_irq;
}
@@ -1133,33 +1543,35 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
goto err_m2m_init;
}
- jpeg->dec_vdev = video_device_alloc();
- if (!jpeg->dec_vdev) {
+ jpeg->vfd_jpeg = video_device_alloc();
+ if (!jpeg->vfd_jpeg) {
ret = -ENOMEM;
- goto err_dec_vdev_alloc;
+ goto err_vfd_jpeg_alloc;
}
- snprintf(jpeg->dec_vdev->name, sizeof(jpeg->dec_vdev->name),
- "%s-dec", MTK_JPEG_NAME);
- jpeg->dec_vdev->fops = &mtk_jpeg_fops;
- jpeg->dec_vdev->ioctl_ops = &mtk_jpeg_ioctl_ops;
- jpeg->dec_vdev->minor = -1;
- jpeg->dec_vdev->release = video_device_release;
- jpeg->dec_vdev->lock = &jpeg->lock;
- jpeg->dec_vdev->v4l2_dev = &jpeg->v4l2_dev;
- jpeg->dec_vdev->vfl_dir = VFL_DIR_M2M;
- jpeg->dec_vdev->device_caps = V4L2_CAP_STREAMING |
+ snprintf(jpeg->vfd_jpeg->name, sizeof(jpeg->vfd_jpeg->name),
+ "%s-%s", MTK_JPEG_NAME,
+ jpeg->mode == MTK_JPEG_ENC ? "enc" : "dec");
+ jpeg->vfd_jpeg->fops = &mtk_jpeg_fops;
+ jpeg->vfd_jpeg->ioctl_ops = &mtk_jpeg_ioctl_ops;
+ jpeg->vfd_jpeg->minor = -1;
+ jpeg->vfd_jpeg->release = video_device_release;
+ jpeg->vfd_jpeg->lock = &jpeg->lock;
+ jpeg->vfd_jpeg->v4l2_dev = &jpeg->v4l2_dev;
+ jpeg->vfd_jpeg->vfl_dir = VFL_DIR_M2M;
+ jpeg->vfd_jpeg->device_caps = V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_M2M_MPLANE;
- ret = video_register_device(jpeg->dec_vdev, VFL_TYPE_GRABBER, 3);
+ ret = video_register_device(jpeg->vfd_jpeg, VFL_TYPE_GRABBER, -1);
if (ret) {
v4l2_err(&jpeg->v4l2_dev, "Failed to register video device\n");
- goto err_dec_vdev_register;
+ goto err_vfd_jpeg_register;
}
- video_set_drvdata(jpeg->dec_vdev, jpeg);
+ video_set_drvdata(jpeg->vfd_jpeg, jpeg);
v4l2_info(&jpeg->v4l2_dev,
- "decoder device registered as /dev/video%d (%d,%d)\n",
- jpeg->dec_vdev->num, VIDEO_MAJOR, jpeg->dec_vdev->minor);
+ "jpeg device %d registered as /dev/video%d (%d,%d)\n",
+ jpeg->mode, jpeg->vfd_jpeg->num, VIDEO_MAJOR,
+ jpeg->vfd_jpeg->minor);
platform_set_drvdata(pdev, jpeg);
@@ -1167,10 +1579,10 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
return 0;
-err_dec_vdev_register:
- video_device_release(jpeg->dec_vdev);
+err_vfd_jpeg_register:
+ video_device_release(jpeg->vfd_jpeg);
-err_dec_vdev_alloc:
+err_vfd_jpeg_alloc:
v4l2_m2m_release(jpeg->m2m_dev);
err_m2m_init:
@@ -1190,8 +1602,8 @@ static int mtk_jpeg_remove(struct platform_device *pdev)
struct mtk_jpeg_dev *jpeg = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
- video_unregister_device(jpeg->dec_vdev);
- video_device_release(jpeg->dec_vdev);
+ video_unregister_device(jpeg->vfd_jpeg);
+ video_device_release(jpeg->vfd_jpeg);
v4l2_m2m_release(jpeg->m2m_dev);
v4l2_device_unregister(&jpeg->v4l2_dev);
@@ -1202,7 +1614,11 @@ static __maybe_unused int mtk_jpeg_pm_suspend(struct device *dev)
{
struct mtk_jpeg_dev *jpeg = dev_get_drvdata(dev);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ else
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+
mtk_jpeg_clk_off(jpeg);
return 0;
@@ -1213,7 +1629,10 @@ static __maybe_unused int mtk_jpeg_pm_resume(struct device *dev)
struct mtk_jpeg_dev *jpeg = dev_get_drvdata(dev);
mtk_jpeg_clk_on(jpeg);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ else
+ mtk_jpeg_dec_reset(jpeg->reg_base);
return 0;
}
@@ -1249,11 +1668,15 @@ static const struct dev_pm_ops mtk_jpeg_pm_ops = {
static const struct of_device_id mtk_jpeg_match[] = {
{
.compatible = "mediatek,mt8173-jpgdec",
- .data = NULL,
+ .data = (void *)MTK_JPEG_DEC,
},
{
.compatible = "mediatek,mt2701-jpgdec",
- .data = NULL,
+ .data = (void *)MTK_JPEG_DEC,
+ },
+ {
+ .compatible = "mediatek,mtk-jpgenc",
+ .data = (void *)MTK_JPEG_ENC,
},
{},
};
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
index 999bd1427809..9fbf0373971b 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
@@ -3,6 +3,7 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*/
#ifndef _MTK_JPEG_CORE_H
@@ -17,6 +18,8 @@
#define MTK_JPEG_FMT_FLAG_DEC_OUTPUT BIT(0)
#define MTK_JPEG_FMT_FLAG_DEC_CAPTURE BIT(1)
+#define MTK_JPEG_FMT_FLAG_ENC_OUTPUT BIT(2)
+#define MTK_JPEG_FMT_FLAG_ENC_CAPTURE BIT(3)
#define MTK_JPEG_FMT_TYPE_OUTPUT 1
#define MTK_JPEG_FMT_TYPE_CAPTURE 2
@@ -28,12 +31,63 @@
#define MTK_JPEG_DEFAULT_SIZEIMAGE (1 * 1024 * 1024)
+#define MTK_JPEG_ENCODE 0
+#define MTK_JPEG_DECODE 1
+
+/**
+ * enum mtk_jpeg_ctx_state - contex state of jpeg
+ */
enum mtk_jpeg_ctx_state {
MTK_JPEG_INIT = 0,
MTK_JPEG_RUNNING,
MTK_JPEG_SOURCE_CHANGE,
};
+/**
+ * enum mtk_jpeg_mode - mode of jpeg
+ */
+enum mtk_jpeg_mode {
+ MTK_JPEG_ENC,
+ MTK_JPEG_DEC,
+};
+
+/**
+ * enum jpeg_enc_yuv_fmt - yuv format of jpeg enc
+ */
+enum jpeg_enc_yuv_fmt {
+ JPEG_YUV_FORMAT_YUYV = 0,
+ JPEG_YUV_FORMAT_YVYU = 1,
+ JPEG_YUV_FORMAT_NV12 = 2,
+ JEPG_YUV_FORMAT_NV21 = 3,
+};
+
+/**
+ * enum JPEG_ENCODE_QUALITY_ENUM - number of jpeg encoder quality
+ */
+enum JPEG_ENCODE_QUALITY_ENUM {
+ JPEG_ENCODE_QUALITY_Q60 = 0x0,
+ JPEG_ENCODE_QUALITY_Q80 = 0x1,
+ JPEG_ENCODE_QUALITY_Q90 = 0x2,
+ JPEG_ENCODE_QUALITY_Q95 = 0x3,
+
+ JPEG_ENCODE_QUALITY_Q39 = 0x4,
+ JPEG_ENCODE_QUALITY_Q68 = 0x5,
+ JPEG_ENCODE_QUALITY_Q84 = 0x6,
+ JPEG_ENCODE_QUALITY_Q92 = 0x7,
+
+ JPEG_ENCODE_QUALITY_Q48 = 0x8,
+ JPEG_ENCODE_QUALITY_Q74 = 0xA,
+ JPEG_ENCODE_QUALITY_Q87 = 0xB,
+
+ JPEG_ENCODE_QUALITY_Q34 = 0xC,
+ JPEG_ENCODE_QUALITY_Q64 = 0xE,
+ JPEG_ENCODE_QUALITY_Q82 = 0xF,
+
+ JPEG_ENCODE_QUALITY_Q97 = 0x10,
+
+ JPEG_ENCODE_QUALITY_ALL = 0xFFFFFFFF
+};
+
/**
* struct mt_jpeg - JPEG IP abstraction
* @lock: the mutex protecting this structure
@@ -43,11 +97,12 @@ enum mtk_jpeg_ctx_state {
* @v4l2_dev: v4l2 device for mem2mem mode
* @m2m_dev: v4l2 mem2mem device data
* @alloc_ctx: videobuf2 memory allocator's context
- * @dec_vdev: video device node for decoder mem2mem mode
- * @dec_reg_base: JPEG registers mapping
- * @clk_jdec: JPEG hw working clock
- * @clk_jdec_smi: JPEG SMI bus clock
+ * @vfd_jpeg: video device node for jpeg mem2mem mode
+ * @reg_base: JPEG registers mapping
+ * @clk_jpeg: JPEG hw working clock
+ * @clk_jpeg_smi: JPEG SMI bus clock
* @larb: SMI device
+ * @mode: compression (encode) operation or decompression (decode)
*/
struct mtk_jpeg_dev {
struct mutex lock;
@@ -57,11 +112,12 @@ struct mtk_jpeg_dev {
struct v4l2_device v4l2_dev;
struct v4l2_m2m_dev *m2m_dev;
void *alloc_ctx;
- struct video_device *dec_vdev;
- void __iomem *dec_reg_base;
- struct clk *clk_jdec;
- struct clk *clk_jdec_smi;
+ struct video_device *vfd_jpeg;
+ void __iomem *reg_base;
+ struct clk *clk_jpeg;
+ struct clk *clk_jpeg_smi;
struct device *larb;
+ enum mtk_jpeg_mode mode;
};
/**
@@ -101,15 +157,51 @@ struct mtk_jpeg_q_data {
u32 sizeimage[VIDEO_MAX_PLANES];
};
+/**
+ * jpeg_enc_param - parameters of jpeg encode control
+ * @enable_exif: EXIF enable for jpeg encode mode
+ * @enc_quality: destination image quality in encode mode
+ * @restart_interval: JPEG restart interval for JPEG encoding
+ */
+struct jpeg_enc_param {
+ u32 enable_exif;
+ u32 enc_quality;
+ u32 restart_interval;
+};
+
+/**
+ * mtk_jpeg_enc_param: General jpeg encoding parameters
+ * @enc_w: image width
+ * @enc_h: image height
+ * @enable_exif: EXIF enable for jpeg encode mode
+ * @enc_quality: destination image quality in encode mode
+ * @enc_format: input image format
+ * @restart_interval: JPEG restart interval for JPEG encoding
+ * @img_stride: jpeg encoder image stride
+ * @mem_stride: jpeg encoder memory stride
+ * @total_encdu: total 8x8 block number
+ */
+struct mtk_jpeg_enc_param {
+ u32 enc_w;
+ u32 enc_h;
+ u32 enable_exif;
+ u32 enc_quality;
+ u32 enc_format;
+ u32 restart_interval;
+ u32 img_stride;
+ u32 mem_stride;
+ u32 total_encdu;
+};
+
/**
* mtk_jpeg_ctx - the device context data
* @jpeg: JPEG IP device for this context
* @out_q: source (output) queue information
* @cap_q: destination (capture) queue queue information
* @fh: V4L2 file handle
- * @dec_param parameters for HW decoding
* @state: state of the context
- * @header_valid: set if header has been parsed and valid
+ * @jpeg_param: jpeg encode parameters
+ * @ctrl_hdl: controls handler
* @colorspace: enum v4l2_colorspace; supplemental to pixelformat
* @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
* @quantization: enum v4l2_quantization, colorspace quantization
@@ -121,6 +213,8 @@ struct mtk_jpeg_ctx {
struct mtk_jpeg_q_data cap_q;
struct v4l2_fh fh;
enum mtk_jpeg_ctx_state state;
+ struct jpeg_enc_param jpeg_param;
+ struct v4l2_ctrl_handler ctrl_hdl;
enum v4l2_colorspace colorspace;
enum v4l2_ycbcr_encoding ycbcr_enc;
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
index a37be1a48415..39d743fb572f 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
@@ -3,10 +3,11 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*/
-#ifndef _MTK_JPEG_HW_H
-#define _MTK_JPEG_HW_H
+#ifndef _MTK_JPEG_DEC_HW_H
+#define _MTK_JPEG_DEC_HW_H
#include <media/videobuf2-core.h>
@@ -80,4 +81,4 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
void mtk_jpeg_dec_reset(void __iomem *dec_reg_base);
void mtk_jpeg_dec_start(void __iomem *dec_reg_base);
-#endif /* _MTK_JPEG_HW_H */
+#endif /* _MTK_JPEG_DEC_HW_H */
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
new file mode 100644
index 000000000000..ac27774ccfed
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <media/videobuf2-core.h>
+
+#include "mtk_jpeg_enc_hw.h"
+
+void mtk_jpeg_enc_reset(void __iomem *base)
+{
+ writel(0x00, base + JPGENC_RSTB);
+ writel(JPEG_ENC_RESET_BIT, base + JPGENC_RSTB);
+ writel(0x00, base + JPGENC_CODEC_SEL);
+}
+
+u32 mtk_jpeg_enc_get_int_status(void __iomem *base)
+{
+ u32 ret;
+
+ ret = readl(base + JPGENC_INT_STS) &
+ JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ;
+ if (ret)
+ writel(0, base + JPGENC_INT_STS);
+
+ return ret;
+}
+
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base)
+{
+ return readl(base + JPGENC_DMA_ADDR0) - readl(base + JPGENC_DST_ADDR0);
+}
+
+u32 mtk_jpeg_enc_enum_result(void __iomem *base, u32 irq_status, u32 *file_size)
+{
+ *file_size = mtk_jpeg_enc_get_file_size(base);
+ if (irq_status & JPEG_DRV_ENC_INT_STATUS_DONE)
+ return MTK_JPEG_ENC_RESULT_DONE;
+ else if (irq_status & JPEG_DRV_ENC_INT_STATUS_STALL)
+ return MTK_JPEG_ENC_RESULT_STALL;
+ else if (irq_status & JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ)
+ return MTK_JPEG_ENC_RESULT_VCODEC_IRQ;
+ return MTK_JPEG_ENC_RESULT_ERROR_UNKNOWN;
+}
+
+static void mtk_jpeg_enc_set_blk_num(void __iomem *base, u32 blk_num)
+{
+ writel(blk_num, base + JPGENC_BLK_NUM);
+}
+
+static void mtk_jpeg_enc_set_encFormat(void __iomem *base, u32 enc_format)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value &= ~JPEG_ENC_CTRL_YUV_BIT;
+ value |= JPGENC_FORMAT(enc_format);
+ writel(value, base + JPGENC_CTRL);
+}
+
+static void mtk_jpeg_enc_set_img_size(void __iomem *base, u32 width, u32 height)
+{
+ u32 value;
+
+ value = JPGENC_WIDTH_HEIGHT(width, height);
+ writel(value, base + JPGENC_IMG_SIZE);
+}
+
+static void mtk_jpeg_enc_set_src_img(void __iomem *base, u32 width,
+ u32 height, u32 yuv_format,
+ u32 total_encdu)
+{
+ mtk_jpeg_enc_set_img_size(base, width, height);
+ mtk_jpeg_enc_set_encFormat(base, yuv_format);
+ mtk_jpeg_enc_set_blk_num(base, total_encdu);
+}
+
+static void mtk_jpeg_enc_set_src_buf(void __iomem *base, u32 img_stride,
+ u32 mem_stride, u32 src_addr,
+ u32 src_addr_c)
+{
+ writel(img_stride, base + JPGENC_IMG_STRIDE);
+ writel(mem_stride, base + JPGENC_STRIDE);
+ writel(src_addr, base + JPGENC_SRC_LUMA_ADDR);
+ writel(src_addr_c, base + JPGENC_SRC_CHROMA_ADDR);
+}
+
+static void mtk_jpeg_enc_set_dst_buf(void __iomem *base, u32 dst_addr,
+ u32 stall_size, u32 init_offset,
+ u32 offset_mask)
+{
+ writel(JPGENC_INIT_OFFSET(init_offset), base + JPGENC_OFFSET_ADDR);
+ writel(JPGENC_OFFSET_MASK(offset_mask), base + JPGENC_BYTE_OFFSET_MASK);
+ writel(JPGENC_DST_ADDR(dst_addr), base + JPGENC_DST_ADDR0);
+ writel(JPGENC_STALL_ADDR(dst_addr, stall_size),
+ base + JPGENC_STALL_ADDR0);
+}
+
+static void mtk_jpeg_enc_set_quality(void __iomem *base, u32 quality)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_QUALITY);
+ value = JPGENC_SET_QUALITY(value, quality);
+ writel(value, base + JPGENC_QUALITY);
+}
+
+static void mtk_jpeg_enc_set_restart_interval(void __iomem *base,
+ u32 restart_interval)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ if (restart_interval)
+ value |= JPEG_ENC_CTRL_RESTART_EN_BIT;
+ else
+ value &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
+ writel(value, base + JPGENC_CTRL);
+ writel(restart_interval, base + JPGENC_RST_MCU_NUM);
+}
+
+static void mtk_jpeg_enc_set_encode_mode(void __iomem *base, u32 exif_en)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value &= ~JPEG_ENC_CTRL_FILE_FORMAT_BIT;
+ writel(value, base + JPGENC_CTRL);
+
+ if (exif_en) {
+ value = readl(base + JPGENC_CTRL);
+ value |= JPEG_ENC_EN_JFIF_EXIF;
+ writel(value, base + JPGENC_CTRL);
+ }
+}
+
+static void mtk_jpeg_enc_set_ctrl_cfg(void __iomem *base, u32 exif_en,
+ u32 quality, u32 restart_interval)
+{
+ mtk_jpeg_enc_set_quality(base, quality);
+
+ mtk_jpeg_enc_set_restart_interval(base, restart_interval);
+
+ mtk_jpeg_enc_set_encode_mode(base, exif_en);
+}
+
+void mtk_jpeg_enc_start(void __iomem *base)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
+ writel(value, base + JPGENC_CTRL);
+}
+
+void mtk_jpeg_enc_set_config(void __iomem *base,
+ struct mtk_jpeg_enc_param *config,
+ struct mtk_jpeg_enc_bs *bs,
+ struct mtk_jpeg_enc_fb *fb)
+{
+ mtk_jpeg_enc_set_src_img(base, config->enc_w, config->enc_h,
+ config->enc_format, config->total_encdu);
+ mtk_jpeg_enc_set_src_buf(base, config->img_stride, config->mem_stride,
+ fb->fb_addr[0].dma_addr,
+ fb->fb_addr[1].dma_addr);
+ mtk_jpeg_enc_set_dst_buf(base, bs->dma_addr, bs->size,
+ bs->dma_addr_offset, bs->dma_addr_offsetmask);
+ mtk_jpeg_enc_set_ctrl_cfg(base, config->enable_exif,
+ config->enc_quality,
+ config->restart_interval);
+}
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
new file mode 100644
index 000000000000..7080240f6dac
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+
+#ifndef _MTK_JPEG_ENC_HW_H
+#define _MTK_JPEG_ENC_HW_H
+
+#include <media/videobuf2-core.h>
+
+#include "mtk_jpeg_core.h"
+#include "mtk_jpeg_enc_reg.h"
+
+#define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
+
+#define JPEG_ENC_CTRL_YUV_BIT 0x18
+#define JPEG_ENC_CTRL_RESTART_EN_BIT BIT(10)
+#define JPEG_ENC_CTRL_FILE_FORMAT_BIT BIT(5)
+#define JPEG_ENC_EN_JFIF_EXIF BIT(5)
+#define JPEG_ENC_CTRL_INT_EN_BIT BIT(2)
+#define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
+#define JPEG_ENC_RESET_BIT BIT(0)
+
+enum {
+ MTK_JPEG_ENC_RESULT_DONE = 0,
+ MTK_JPEG_ENC_RESULT_STALL,
+ MTK_JPEG_ENC_RESULT_VCODEC_IRQ,
+ MTK_JPEG_ENC_RESULT_ERROR_UNKNOWN
+};
+
+struct mtk_jpeg_enc_bs {
+ dma_addr_t dma_addr;
+ size_t size;
+ u32 dma_addr_offset;
+ u32 dma_addr_offsetmask;
+};
+
+struct mtk_jpeg_mem {
+ dma_addr_t dma_addr;
+ size_t size;
+};
+
+struct mtk_jpeg_enc_fb {
+ struct mtk_jpeg_mem fb_addr[MTK_JPEG_COMP_MAX];
+ u32 num_planes;
+};
+
+void mtk_jpeg_enc_reset(void __iomem *base);
+u32 mtk_jpeg_enc_get_int_status(void __iomem *base);
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base);
+u32 mtk_jpeg_enc_enum_result(void __iomem *base, u32 irq_status,
+ u32 *file_size);
+void mtk_jpeg_enc_start(void __iomem *enc_reg_base);
+void mtk_jpeg_enc_set_config(void __iomem *base,
+ struct mtk_jpeg_enc_param *config,
+ struct mtk_jpeg_enc_bs *bs,
+ struct mtk_jpeg_enc_fb *fb);
+#endif /* _MTK_JPEG_ENC_HW_H */
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
new file mode 100644
index 000000000000..d785621cb4c6
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+#ifndef _MTK_JPEG_ENC_REG_H
+#define _MTK_JPEG_ENC_REG_H
+#define MTK_JPEG_COMP_MAX 3
+
+#define JPEG_DRV_ENC_INT_STATUS_DONE BIT(0)
+#define JPEG_DRV_ENC_INT_STATUS_STALL BIT(1)
+#define JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ BIT(4)
+#define JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ 0x13
+
+#define JPGENC_RSTB 0x100
+#define JPGENC_CTRL 0x104
+#define JPGENC_QUALITY 0x108
+#define JPGENC_BLK_NUM 0x10C
+#define JPGENC_BLK_CNT 0x110
+#define JPGENC_INT_STS 0x11C
+#define JPGENC_DST_ADDR0 0x120
+#define JPGENC_DMA_ADDR0 0x124
+#define JPGENC_STALL_ADDR0 0x128
+#define JPGENC_OFFSET_ADDR 0x138
+#define JPGENC_RST_MCU_NUM 0x150
+#define JPGENC_IMG_SIZE 0x154
+#define JPGENC_DEBUG_INFO0 0x160
+#define JPGENC_DEBUG_INFO1 0x164
+#define JPGENC_TOTAL_CYCLE 0x168
+#define JPGENC_BYTE_OFFSET_MASK 0x16C
+#define JPGENC_SRC_LUMA_ADDR 0x170
+#define JPGENC_SRC_CHROMA_ADDR 0x174
+#define JPGENC_STRIDE 0x178
+#define JPGENC_IMG_STRIDE 0x17C
+#define JPGENC_DCM_CTRL 0x300
+#define JPGENC_CODEC_SEL 0x314
+#define JPGENC_ULTRA_THRES 0x318
+
+#define JPGENC_FORMAT(x) (((x) & 3) << 3)
+#define JPGENC_WIDTH_HEIGHT(w, h) (((w) << 16) | (h))
+#define JPGENC_INIT_OFFSET(x) ((x) & (~0xF))
+#define JPGENC_OFFSET_MASK(x) ((x) & 0xF)
+#define JPGENC_DST_ADDR(x) ((x) & (~0xF))
+#define JPGENC_STALL_ADDR(x, y) (((x) + (y)) & (~0xF))
+#define JPGENC_QUALITY_MASK 0xFFFF0000
+#define JPGENC_SET_QUALITY(x, y) (((x) & JPGENC_QUALITY_MASK) | (y))
+
+#endif /* _MTK_JPEG_ENC_REG_H */
--
2.18.0
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^ permalink raw reply related
* [PATCH v2 00/22] mtd: spi-nor: Quad Enable and (un)lock methods
From: Tudor.Ambarus @ 2019-09-24 7:45 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Patches 1 - 14 are just clean up patches for the Flash Register
Operations.
Patches 15 - 22 deal with the Quad Enable and the (un)lock methods.
Fixed the clearing of QE bit on (un)lock() operations. Reworked the
Quad Enable methods and the disabling of the block write protection
at power-up.
Again, this is just compile tested, I don't have (yet) a relevant
spansion-like flash memory to test the (un)lock() methods, so I'll need
your help for testing this patch set.
The patch set can be tested using mtd-utils:
1/ do a read-erase-write-read-back test immediately after boot, to check
the spi_nor_unlock_all() method. The focus is on the erase/write
methods, we want to see if the flash is unlocked at power-up.
mtd_debug read /dev/mtd-yours offset size read-file
hexdump read-file
mtd_debug erase /dev/mtd-yours offset size
dd if=/dev/urandom of=write-file bs=please-choose count=please-choose
mtd_debug write /dev/mtd-yours offset write-file-size write-file
mtd_debug read /dev/mtd-yours offset write-file-size read-file
sha1sum read-file write-file
2/ lock flash then try to erase/write it, to see if the lock works
flash_lock /dev/mtd-yours offset block-count
Do the read-erase-write-read-back test from 1/. The contents of
flash should not change in the erase and write steps.
3/ unlock flash and do the read-erase-write-read-back from 1/. The value of the
QEE should not change and you should be able to erase and write the flash.
Test 1/ should be successful.
v2:
- Introduce spi_nor_write_16bit_cr_and_check() as per Vignesh's suggestion. The
Configuration Register contains bits that can be updated in future: FREEZE,
CMP. Provide a generic method that allows updating all bits of the
Configuration Register.
- Fix SNOR_F_NO_READ_CR case in
"mtd: spi-nor: Rework the disabling of block write protection". When the flash
doesn't support the CR Read command, we make an assumption about the value of
the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then
spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure
the QE bit has value one, because of the previous call to spi_nor_quad_enable().
- Fix if statement in spi_nor_write_sr_and_check():
if (nor->flags & SNOR_F_HAS_16BIT_SR)
- Fix documentation warnings.
- New patch: "mtd: spi-nor: Check all the bits written, not just the BP ones".
- Drop Global Unlock patches, will send them in a different patch set.
Tudor Ambarus (22):
mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
mtd: spi-nor: Rename nor->params to nor->flash
mtd: spi-nor: Rework read_sr()
mtd: spi-nor: Rework read_fsr()
mtd: spi-nor: Rework read_cr()
mtd: spi-nor: Rework write_enable/disable()
mtd: spi-nor: Fix retlen handling in sst_write()
mtd: spi-nor: Rework write_sr()
mtd: spi-nor: Rework spi_nor_read/write_sr2()
mtd: spi-nor: Report error in spi_nor_xread_sr()
mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
mtd: spi-nor: Drop duplicated new line
mtd: spi-nor: Drop spansion_quad_enable()
mtd: spi-nor: Fix errno on quad_enable methods
mtd: spi-nor: Check all the bits written, not just the BP ones
mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
mtd: spi-nor: Rework macronix_quad_enable()
mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable()
mtd: spi-nor: Update sr2_bit7_quad_enable()
mtd: spi-nor: Rework the disabling of block write protection
drivers/mtd/spi-nor/aspeed-smc.c | 23 +-
drivers/mtd/spi-nor/cadence-quadspi.c | 54 +-
drivers/mtd/spi-nor/hisi-sfc.c | 23 +-
drivers/mtd/spi-nor/intel-spi.c | 24 +-
drivers/mtd/spi-nor/mtk-quadspi.c | 25 +-
drivers/mtd/spi-nor/nxp-spifi.c | 23 +-
drivers/mtd/spi-nor/spi-nor.c | 1716 ++++++++++++++++++---------------
include/linux/mtd/spi-nor.h | 74 +-
8 files changed, 1058 insertions(+), 904 deletions(-)
--
2.9.5
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^ permalink raw reply
* [PATCH v2 01/22] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment
From: Tudor.Ambarus @ 2019-09-24 7:45 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The pointer to 'struct spi_nor' is kzalloc'ed above in the code.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/hisi-sfc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
index 6dac9dd8bf42..c99ed9cdbf9c 100644
--- a/drivers/mtd/spi-nor/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -364,7 +364,6 @@ static int hisi_spi_nor_register(struct device_node *np,
nor->write_reg = hisi_spi_nor_write_reg;
nor->read = hisi_spi_nor_read;
nor->write = hisi_spi_nor_write;
- nor->erase = NULL;
ret = spi_nor_scan(nor, NULL, &hwcaps);
if (ret)
return ret;
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 03/22] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition
From: Tudor.Ambarus @ 2019-09-24 7:45 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode',
to comply with the SPI NOR int (*read_reg)() method. The 'const'
qualifier has no meaning for parameters passed by value, drop it.
Going furher, the opcode was passed to cqspi_calc_rdreg() and never used,
drop it.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index ebda612641a4..22008fecd326 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -285,7 +285,7 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
return IRQ_HANDLED;
}
-static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
+static unsigned int cqspi_calc_rdreg(struct spi_nor *nor)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
u32 rdreg = 0;
@@ -354,8 +354,7 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
return cqspi_wait_idle(cqspi);
}
-static int cqspi_command_read(struct spi_nor *nor,
- const u8 *txbuf, const unsigned n_tx,
+static int cqspi_command_read(struct spi_nor *nor, u8 opcode,
u8 *rxbuf, size_t n_rx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
@@ -373,9 +372,9 @@ static int cqspi_command_read(struct spi_nor *nor,
return -EINVAL;
}
- reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+ reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
- rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
+ rdreg = cqspi_calc_rdreg(nor);
writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@@ -471,7 +470,7 @@ static int cqspi_read_setup(struct spi_nor *nor)
unsigned int reg;
reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
- reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
+ reg |= cqspi_calc_rdreg(nor);
/* Setup dummy clock cycles */
dummy_clk = nor->read_dummy;
@@ -604,7 +603,7 @@ static int cqspi_write_setup(struct spi_nor *nor)
/* Set opcode. */
reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, reg_base + CQSPI_REG_WR_INSTR);
- reg = cqspi_calc_rdreg(nor, nor->program_opcode);
+ reg = cqspi_calc_rdreg(nor);
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
reg = readl(reg_base + CQSPI_REG_SIZE);
@@ -1087,7 +1086,7 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
ret = cqspi_set_protocol(nor, 0);
if (!ret)
- ret = cqspi_command_read(nor, &opcode, 1, buf, len);
+ ret = cqspi_command_read(nor, opcode, buf, len);
return ret;
}
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 02/22] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'
From: Tudor.Ambarus @ 2019-09-24 7:45 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Move all SPI NOR controller driver specific ops in a dedicated
structure. 'struct spi_nor' becomes lighter.
Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'.
Rename wite/read_buf to buf, the name of the functions are
suggestive enough. Constify buf in int (*write_reg). Comply with these
changes in the SPI NOR controller drivers.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/aspeed-smc.c | 23 ++++++-----
drivers/mtd/spi-nor/cadence-quadspi.c | 39 ++++++++++--------
drivers/mtd/spi-nor/hisi-sfc.c | 22 +++++-----
drivers/mtd/spi-nor/intel-spi.c | 24 ++++++-----
drivers/mtd/spi-nor/mtk-quadspi.c | 25 +++++++-----
drivers/mtd/spi-nor/nxp-spifi.c | 23 +++++++----
drivers/mtd/spi-nor/spi-nor.c | 76 ++++++++++++++++++++---------------
include/linux/mtd/spi-nor.h | 51 +++++++++++++----------
8 files changed, 166 insertions(+), 117 deletions(-)
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index 009c1da8574c..2b7cabbb680c 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -320,7 +320,8 @@ static void aspeed_smc_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_unlock(&chip->controller->mutex);
}
-static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct aspeed_smc_chip *chip = nor->priv;
@@ -331,8 +332,8 @@ static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return 0;
}
-static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct aspeed_smc_chip *chip = nor->priv;
@@ -746,6 +747,15 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
return 0;
}
+static const struct spi_nor_controller_ops aspeed_smc_controller_ops = {
+ .prepare = aspeed_smc_prep,
+ .unprepare = aspeed_smc_unprep,
+ .read_reg = aspeed_smc_read_reg,
+ .write_reg = aspeed_smc_write_reg,
+ .read = aspeed_smc_read_user,
+ .write = aspeed_smc_write_user,
+};
+
static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
struct device_node *np, struct resource *r)
{
@@ -805,12 +815,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
nor->dev = dev;
nor->priv = chip;
spi_nor_set_flash_node(nor, child);
- nor->read = aspeed_smc_read_user;
- nor->write = aspeed_smc_write_user;
- nor->read_reg = aspeed_smc_read_reg;
- nor->write_reg = aspeed_smc_write_reg;
- nor->prepare = aspeed_smc_prep;
- nor->unprepare = aspeed_smc_unprep;
+ nor->controller_ops = &aspeed_smc_controller_ops;
ret = aspeed_smc_chip_setup_init(chip, r);
if (ret)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 7bef63947b29..ebda612641a4 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -356,18 +356,19 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
static int cqspi_command_read(struct spi_nor *nor,
const u8 *txbuf, const unsigned n_tx,
- u8 *rxbuf, const unsigned n_rx)
+ u8 *rxbuf, size_t n_rx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int rdreg;
unsigned int reg;
- unsigned int read_len;
+ size_t read_len;
int status;
if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
- dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
+ dev_err(nor->dev,
+ "Invalid input argument, len %zu rxbuf 0x%p\n",
n_rx, rxbuf);
return -EINVAL;
}
@@ -404,19 +405,19 @@ static int cqspi_command_read(struct spi_nor *nor,
}
static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
- const u8 *txbuf, const unsigned n_tx)
+ const u8 *txbuf, size_t n_tx)
{
struct cqspi_flash_pdata *f_pdata = nor->priv;
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
unsigned int data;
- u32 write_len;
+ size_t write_len;
int ret;
if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(nor->dev,
- "Invalid input argument, cmdlen %d txbuf 0x%p\n",
+ "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
n_tx, txbuf);
return -EINVAL;
}
@@ -1050,7 +1051,7 @@ static int cqspi_erase(struct spi_nor *nor, loff_t offs)
return ret;
/* Send write enable, then erase commands. */
- ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
if (ret)
return ret;
@@ -1080,7 +1081,7 @@ static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_unlock(&cqspi->bus_mutex);
}
-static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
{
int ret;
@@ -1091,7 +1092,8 @@ static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return ret;
}
-static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
int ret;
@@ -1216,6 +1218,16 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
init_completion(&cqspi->rx_dma_complete);
}
+static const struct spi_nor_controller_ops cqspi_controller_ops = {
+ .prepare = cqspi_prep,
+ .unprepare = cqspi_unprep,
+ .read_reg = cqspi_read_reg,
+ .write_reg = cqspi_write_reg,
+ .read = cqspi_read,
+ .write = cqspi_write,
+ .erase = cqspi_erase,
+};
+
static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
{
struct platform_device *pdev = cqspi->pdev;
@@ -1265,14 +1277,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
nor->dev = dev;
spi_nor_set_flash_node(nor, np);
nor->priv = f_pdata;
-
- nor->read_reg = cqspi_read_reg;
- nor->write_reg = cqspi_write_reg;
- nor->read = cqspi_read;
- nor->write = cqspi_write;
- nor->erase = cqspi_erase;
- nor->prepare = cqspi_prep;
- nor->unprepare = cqspi_unprep;
+ nor->controller_ops = &cqspi_controller_ops;
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
dev_name(dev), cs);
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
index c99ed9cdbf9c..a1258216f89d 100644
--- a/drivers/mtd/spi-nor/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -177,7 +177,7 @@ static void hisi_spi_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
}
static int hisi_spi_nor_op_reg(struct spi_nor *nor,
- u8 opcode, int len, u8 optype)
+ u8 opcode, size_t len, u8 optype)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -200,7 +200,7 @@ static int hisi_spi_nor_op_reg(struct spi_nor *nor,
}
static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+ size_t len)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -215,7 +215,7 @@ static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
}
static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
- u8 *buf, int len)
+ const u8 *buf, size_t len)
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
@@ -311,6 +311,15 @@ static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
return len;
}
+static const struct spi_nor_controller_ops hisi_controller_ops = {
+ .prepare = hisi_spi_nor_prep,
+ .unprepare = hisi_spi_nor_unprep,
+ .read_reg = hisi_spi_nor_read_reg,
+ .write_reg = hisi_spi_nor_write_reg,
+ .read = hisi_spi_nor_read,
+ .write = hisi_spi_nor_write,
+};
+
/**
* Get spi flash device information and register it as a mtd device.
*/
@@ -357,13 +366,8 @@ static int hisi_spi_nor_register(struct device_node *np,
}
priv->host = host;
nor->priv = priv;
+ nor->controller_ops = &hisi_controller_ops;
- nor->prepare = hisi_spi_nor_prep;
- nor->unprepare = hisi_spi_nor_unprep;
- nor->read_reg = hisi_spi_nor_read_reg;
- nor->write_reg = hisi_spi_nor_write_reg;
- nor->read = hisi_spi_nor_read;
- nor->write = hisi_spi_nor_write;
ret = spi_nor_scan(nor, NULL, &hwcaps);
if (ret)
return ret;
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 43e55a2e9b27..dc38f19ac7ae 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -426,7 +426,7 @@ static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
return 0;
}
-static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
+static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
{
u32 val, status;
int ret;
@@ -469,7 +469,7 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
return 0;
}
-static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
+static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
int optype)
{
u32 val = 0, status;
@@ -535,7 +535,8 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
return 0;
}
-static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct intel_spi *ispi = nor->priv;
int ret;
@@ -555,7 +556,8 @@ static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return intel_spi_read_block(ispi, buf, len);
}
-static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct intel_spi *ispi = nor->priv;
int ret;
@@ -864,6 +866,14 @@ static void intel_spi_fill_partition(struct intel_spi *ispi,
}
}
+static const struct spi_nor_controller_ops intel_spi_controller_ops = {
+ .read_reg = intel_spi_read_reg,
+ .write_reg = intel_spi_write_reg,
+ .read = intel_spi_read,
+ .write = intel_spi_write,
+ .erase = intel_spi_erase,
+};
+
struct intel_spi *intel_spi_probe(struct device *dev,
struct resource *mem, const struct intel_spi_boardinfo *info)
{
@@ -897,11 +907,7 @@ struct intel_spi *intel_spi_probe(struct device *dev,
ispi->nor.dev = ispi->dev;
ispi->nor.priv = ispi;
- ispi->nor.read_reg = intel_spi_read_reg;
- ispi->nor.write_reg = intel_spi_write_reg;
- ispi->nor.read = intel_spi_read;
- ispi->nor.write = intel_spi_write;
- ispi->nor.erase = intel_spi_erase;
+ ispi->nor.controller_ops = &intel_spi_controller_ops;
ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
if (ret) {
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
index 34db01ab6cab..b1691680d174 100644
--- a/drivers/mtd/spi-nor/mtk-quadspi.c
+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
@@ -151,9 +151,9 @@ static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
}
static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
- u8 *tx, int txlen, u8 *rx, int rxlen)
+ const u8 *tx, size_t txlen, u8 *rx, size_t rxlen)
{
- int len = 1 + txlen + rxlen;
+ size_t len = 1 + txlen + rxlen;
int i, ret, idx;
if (len > MTK_NOR_MAX_SHIFT)
@@ -193,7 +193,7 @@ static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
}
/* Do a WRSR (Write Status Register) command */
-static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
+static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, const u8 sr)
{
writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
@@ -354,7 +354,7 @@ static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
return len;
}
-static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len)
{
int ret;
struct mtk_nor *mtk_nor = nor->priv;
@@ -376,8 +376,8 @@ static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return ret;
}
-static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
- int len)
+static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
int ret;
struct mtk_nor *mtk_nor = nor->priv;
@@ -419,6 +419,13 @@ static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
return 0;
}
+static const struct spi_nor_controller_ops mtk_controller_ops = {
+ .read_reg = mtk_nor_read_reg,
+ .write_reg = mtk_nor_write_reg,
+ .read = mtk_nor_read,
+ .write = mtk_nor_write,
+};
+
static int mtk_nor_init(struct mtk_nor *mtk_nor,
struct device_node *flash_node)
{
@@ -438,12 +445,8 @@ static int mtk_nor_init(struct mtk_nor *mtk_nor,
nor->dev = mtk_nor->dev;
nor->priv = mtk_nor;
spi_nor_set_flash_node(nor, flash_node);
+ nor->controller_ops = &mtk_controller_ops;
- /* fill the hooks to spi nor */
- nor->read = mtk_nor_read;
- nor->read_reg = mtk_nor_read_reg;
- nor->write = mtk_nor_write;
- nor->write_reg = mtk_nor_write_reg;
nor->mtd.name = "mtk_nor";
/* initialized with NULL */
ret = spi_nor_scan(nor, NULL, &hwcaps);
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index 4a871587392b..9a5b1a7c636a 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -123,7 +123,8 @@ static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
return ret;
}
-static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ size_t len)
{
struct nxp_spifi *spifi = nor->priv;
u32 cmd;
@@ -145,7 +146,8 @@ static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return nxp_spifi_wait_for_cmd(spifi);
}
-static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len)
{
struct nxp_spifi *spifi = nor->priv;
u32 cmd;
@@ -263,9 +265,18 @@ static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
{
u8 id[SPI_NOR_MAX_ID_LEN];
- nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
+ nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
+ SPI_NOR_MAX_ID_LEN);
}
+static const struct spi_nor_controller_ops nxp_spifi_controller_ops = {
+ .read_reg = nxp_spifi_read_reg,
+ .write_reg = nxp_spifi_write_reg,
+ .read = nxp_spifi_read,
+ .write = nxp_spifi_write,
+ .erase = nxp_spifi_erase,
+};
+
static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
struct device_node *np)
{
@@ -332,11 +343,7 @@ static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
spifi->nor.dev = spifi->dev;
spi_nor_set_flash_node(&spifi->nor, np);
spifi->nor.priv = spifi;
- spifi->nor.read = nxp_spifi_read;
- spifi->nor.write = nxp_spifi_write;
- spifi->nor.erase = nxp_spifi_erase;
- spifi->nor.read_reg = nxp_spifi_read_reg;
- spifi->nor.write_reg = nxp_spifi_write_reg;
+ spifi->nor.controller_ops = &nxp_spifi_controller_ops;
/*
* The first read on a hard reset isn't reliable so do a
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 1d8621d43160..b8c7ded0f145 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -338,7 +338,7 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
if (nor->spimem)
return spi_nor_spimem_read_data(nor, from, len, buf);
- return nor->read(nor, from, len, buf);
+ return nor->controller_ops->read(nor, from, len, buf);
}
/**
@@ -385,7 +385,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
if (nor->spimem)
return spi_nor_spimem_write_data(nor, to, len, buf);
- return nor->write(nor, to, len, buf);
+ return nor->controller_ops->write(nor, to, len, buf);
}
/*
@@ -406,7 +406,8 @@ static int read_sr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDSR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -435,7 +436,8 @@ static int read_fsr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDFSR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -464,7 +466,8 @@ static int read_cr(struct spi_nor *nor)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->read_reg(nor, SPINOR_OP_RDCR, nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR,
+ nor->bouncebuf, 1);
}
if (ret < 0) {
@@ -492,7 +495,8 @@ static int write_sr(struct spi_nor *nor, u8 val)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ nor->bouncebuf, 1);
}
/*
@@ -511,7 +515,7 @@ static int write_enable(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
}
/*
@@ -529,7 +533,7 @@ static int write_disable(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
}
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -631,8 +635,9 @@ static int macronix_set_4byte(struct spi_nor *nor, bool enable)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B,
- NULL, 0);
+ return nor->controller_ops->write_reg(nor, enable ? SPINOR_OP_EN4B :
+ SPINOR_OP_EX4B,
+ NULL, 0);
}
static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
@@ -660,7 +665,8 @@ static int spansion_set_4byte(struct spi_nor *nor, bool enable)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_BRWR,
+ nor->bouncebuf, 1);
}
static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
@@ -677,7 +683,8 @@ static int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WREAR, nor->bouncebuf, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WREAR,
+ nor->bouncebuf, 1);
}
static int winbond_set_4byte(struct spi_nor *nor, bool enable)
@@ -712,7 +719,7 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
}
static int s3an_sr_ready(struct spi_nor *nor)
@@ -740,7 +747,7 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
}
static int spi_nor_sr_ready(struct spi_nor *nor)
@@ -774,7 +781,7 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
}
static int spi_nor_fsr_ready(struct spi_nor *nor)
@@ -871,7 +878,8 @@ static int erase_chip(struct spi_nor *nor)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CHIP_ERASE,
+ NULL, 0);
}
static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
@@ -880,10 +888,9 @@ static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
mutex_lock(&nor->lock);
- if (nor->prepare) {
- ret = nor->prepare(nor, ops);
+ if (nor->controller_ops && nor->controller_ops->prepare) {
+ ret = nor->controller_ops->prepare(nor, ops);
if (ret) {
- dev_err(nor->dev, "failed in the preparation.\n");
mutex_unlock(&nor->lock);
return ret;
}
@@ -893,8 +900,8 @@ static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
{
- if (nor->unprepare)
- nor->unprepare(nor, ops);
+ if (nor->controller_ops && nor->controller_ops->unprepare)
+ nor->controller_ops->unprepare(nor, ops);
mutex_unlock(&nor->lock);
}
@@ -935,8 +942,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
addr = spi_nor_convert_addr(nor, addr);
- if (nor->erase)
- return nor->erase(nor, addr);
+ if (nor->controller_ops && nor->controller_ops->erase)
+ return nor->controller_ops->erase(nor, addr);
if (nor->spimem) {
struct spi_mem_op op =
@@ -957,8 +964,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
addr >>= 8;
}
- return nor->write_reg(nor, nor->erase_opcode, nor->bouncebuf,
- nor->addr_width);
+ return nor->controller_ops->write_reg(nor, nor->erase_opcode,
+ nor->bouncebuf, nor->addr_width);
}
/**
@@ -1678,7 +1685,8 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ sr_cr, 2);
}
if (ret < 0) {
@@ -1873,7 +1881,7 @@ static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
}
static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
@@ -1888,7 +1896,7 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
return spi_mem_exec_op(nor->spimem, &op);
}
- return nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
}
/**
@@ -2520,8 +2528,8 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
tmp = spi_mem_exec_op(nor->spimem, &op);
} else {
- tmp = nor->read_reg(nor, SPINOR_OP_RDID, id,
- SPI_NOR_MAX_ID_LEN);
+ tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
+ SPI_NOR_MAX_ID_LEN);
}
if (tmp < 0) {
dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp);
@@ -2722,9 +2730,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
static int spi_nor_check(struct spi_nor *nor)
{
if (!nor->dev ||
- (!nor->spimem &&
- (!nor->read || !nor->write || !nor->read_reg ||
- !nor->write_reg))) {
+ (!nor->spimem && nor->controller_ops &&
+ (!nor->controller_ops->read ||
+ !nor->controller_ops->write ||
+ !nor->controller_ops->read_reg ||
+ !nor->controller_ops->write_reg))) {
pr_err("spi-nor: please fill all the necessary fields!\n");
return -EINVAL;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fc0b4b19c900..d1d736d3c8ab 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -466,6 +466,34 @@ enum spi_nor_pp_command_index {
struct spi_nor;
/**
+ * struct spi_nor_controller_ops - SPI NOR controller driver specific
+ * operations.
+ * @prepare: [OPTIONAL] do some preparations for the
+ * read/write/erase/lock/unlock operations.
+ * @unprepare: [OPTIONAL] do some post work after the
+ * read/write/erase/lock/unlock operations.
+ * @read_reg: read out the register.
+ * @write_reg: write data to the register.
+ * @read: read data from the SPI NOR.
+ * @write: write data to the SPI NOR.
+ * @erase: erase a sector of the SPI NOR at the offset @offs; if
+ * not provided by the driver, spi-nor will send the erase
+ * opcode via write_reg().
+ */
+struct spi_nor_controller_ops {
+ int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
+ int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
+ size_t len);
+
+ ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
+ ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
+ const u8 *buf);
+ int (*erase)(struct spi_nor *nor, loff_t offs);
+};
+
+/**
* struct spi_nor_locking_ops - SPI NOR locking methods
* @lock: lock a region of the SPI NOR.
* @unlock: unlock a region of the SPI NOR.
@@ -549,17 +577,7 @@ struct flash_info;
* @read_proto: the SPI protocol for read operations
* @write_proto: the SPI protocol for write operations
* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
- * @prepare: [OPTIONAL] do some preparations for the
- * read/write/erase/lock/unlock operations
- * @unprepare: [OPTIONAL] do some post work after the
- * read/write/erase/lock/unlock operations
- * @read_reg: [DRIVER-SPECIFIC] read out the register
- * @write_reg: [DRIVER-SPECIFIC] write data to the register
- * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
- * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
- * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
- * at the offset @offs; if not provided by the driver,
- * spi-nor will send the erase opcode via write_reg()
+ * @controller_ops: SPI NOR controller driver specific operations.
* @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from
* the SPI NOR Status Register.
* @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
@@ -588,16 +606,7 @@ struct spi_nor {
bool sst_write_second;
u32 flags;
- int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
- void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
- int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
- int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
-
- ssize_t (*read)(struct spi_nor *nor, loff_t from,
- size_t len, u_char *read_buf);
- ssize_t (*write)(struct spi_nor *nor, loff_t to,
- size_t len, const u_char *write_buf);
- int (*erase)(struct spi_nor *nor, loff_t offs);
+ const struct spi_nor_controller_ops *controller_ops;
int (*clear_sr_bp)(struct spi_nor *nor);
struct spi_nor_flash_parameter params;
--
2.9.5
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 04/22] mtd: spi-nor: Rename nor->params to nor->flash
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Rename nor->params to nor->flash for a clearer separation
between the controller and flash operations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 286 +++++++++++++++++++++---------------------
include/linux/mtd/spi-nor.h | 12 +-
2 files changed, 149 insertions(+), 149 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8c7ded0f145..7d0c1b598250 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -172,7 +172,7 @@ struct spi_nor_fixups {
int (*post_bfpt)(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params);
+ struct spi_nor_flash_parameter *flash);
void (*post_sfdp)(struct spi_nor *nor);
};
@@ -608,7 +608,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
if (!spi_nor_has_uniform_erase(nor)) {
- struct spi_nor_erase_map *map = &nor->params.erase_map;
+ struct spi_nor_erase_map *map = &nor->flash.erase_map;
struct spi_nor_erase_type *erase;
int i;
@@ -927,10 +927,10 @@ static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
{
- if (!nor->params.convert_addr)
+ if (!nor->flash.convert_addr)
return addr;
- return nor->params.convert_addr(nor, addr);
+ return nor->flash.convert_addr(nor, addr);
}
/*
@@ -1140,7 +1140,7 @@ static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
struct list_head *erase_list,
u64 addr, u32 len)
{
- const struct spi_nor_erase_map *map = &nor->params.erase_map;
+ const struct spi_nor_erase_map *map = &nor->flash.erase_map;
const struct spi_nor_erase_type *erase, *prev_erase = NULL;
struct spi_nor_erase_region *region;
struct spi_nor_erase_command *cmd = NULL;
@@ -1628,7 +1628,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->lock(nor, ofs, len);
+ ret = nor->flash.locking_ops->lock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
return ret;
@@ -1643,7 +1643,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->unlock(nor, ofs, len);
+ ret = nor->flash.locking_ops->unlock(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
@@ -1658,7 +1658,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
if (ret)
return ret;
- ret = nor->params.locking_ops->is_locked(nor, ofs, len);
+ ret = nor->flash.locking_ops->is_locked(nor, ofs, len);
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
@@ -2093,7 +2093,7 @@ static int
is25lp256_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
/*
* IS25LP256 supports 4B opcodes, but the BFPT advertises a
@@ -2115,7 +2115,7 @@ static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
/*
* MX25L25635F supports 4B opcodes but MX25L25635E does not.
@@ -2144,7 +2144,7 @@ static void gd25q256_default_init(struct spi_nor *nor)
* indicate the quad_enable method for this case, we need
* to set it in the default_init fixup hook.
*/
- nor->params.quad_enable = macronix_quad_enable;
+ nor->flash.quad_enable = macronix_quad_enable;
}
static struct spi_nor_fixups gd25q256_fixups = {
@@ -2777,7 +2777,7 @@ static int s3an_nor_setup(struct spi_nor *nor,
nor->mtd.erasesize = 8 * nor->page_size;
} else {
/* Flash in Default addressing mode */
- nor->params.convert_addr = s3an_convert_addr;
+ nor->flash.convert_addr = s3an_convert_addr;
nor->mtd.erasesize = nor->info->sector_size;
}
@@ -3017,7 +3017,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor,
static void
spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
{
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
unsigned int cap;
/* DTR modes are not supported yet, mask them all. */
@@ -3034,7 +3034,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
if (rdidx >= 0 &&
- spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
+ spi_nor_spimem_check_readop(nor, &flash->reads[rdidx]))
*hwcaps &= ~BIT(cap);
ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
@@ -3042,7 +3042,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
continue;
if (spi_nor_spimem_check_pp(nor,
- ¶ms->page_programs[ppidx]))
+ &flash->page_programs[ppidx]))
*hwcaps &= ~BIT(cap);
}
}
@@ -3091,7 +3091,7 @@ spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
}
struct sfdp_bfpt_read {
- /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
+ /* The Fast Read x-y-z hardware capability in flash->hwcaps.mask. */
u32 hwcaps;
/*
@@ -3322,11 +3322,11 @@ static int
spi_nor_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
if (nor->info->fixups && nor->info->fixups->post_bfpt)
return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
- params);
+ flash);
return 0;
}
@@ -3336,7 +3336,7 @@ spi_nor_post_bfpt_fixups(struct spi_nor *nor,
* @nor: pointer to a 'struct spi_nor'
* @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
* the Basic Flash Parameter Table length and version
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be
* filled
*
* The Basic Flash Parameter Table is the main and only mandatory table as
@@ -3363,9 +3363,9 @@ spi_nor_post_bfpt_fixups(struct spi_nor *nor,
*/
static int spi_nor_parse_bfpt(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
struct sfdp_bfpt bfpt;
size_t len;
@@ -3406,23 +3406,23 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
}
/* Flash Memory Density (in bits). */
- params->size = bfpt.dwords[BFPT_DWORD(2)];
- if (params->size & BIT(31)) {
- params->size &= ~BIT(31);
+ flash->size = bfpt.dwords[BFPT_DWORD(2)];
+ if (flash->size & BIT(31)) {
+ flash->size &= ~BIT(31);
/*
- * Prevent overflows on params->size. Anyway, a NOR of 2^64
+ * Prevent overflows on flash->size. Anyway, a NOR of 2^64
* bits is unlikely to exist so this error probably means
* the BFPT we are reading is corrupted/wrong.
*/
- if (params->size > 63)
+ if (flash->size > 63)
return -EINVAL;
- params->size = 1ULL << params->size;
+ flash->size = 1ULL << flash->size;
} else {
- params->size++;
+ flash->size++;
}
- params->size >>= 3; /* Convert to bytes. */
+ flash->size >>= 3; /* Convert to bytes. */
/* Fast Read settings. */
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
@@ -3430,13 +3430,13 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
struct spi_nor_read_command *read;
if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
- params->hwcaps.mask &= ~rd->hwcaps;
+ flash->hwcaps.mask &= ~rd->hwcaps;
continue;
}
- params->hwcaps.mask |= rd->hwcaps;
+ flash->hwcaps.mask |= rd->hwcaps;
cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
- read = ¶ms->reads[cmd];
+ read = &flash->reads[cmd];
half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
}
@@ -3446,7 +3446,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Erase Types defined in the bfpt table.
*/
erase_mask = 0;
- memset(¶ms->erase_map, 0, sizeof(params->erase_map));
+ memset(&flash->erase_map, 0, sizeof(flash->erase_map));
for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
u32 erasesize;
@@ -3465,7 +3465,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
opcode, i);
}
- spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
+ spi_nor_init_uniform_erase_map(map, erase_mask, flash->size);
/*
* Sort all the map's Erase Types in ascending order with the smallest
* erase size being the first member in the erase_type array.
@@ -3483,43 +3483,42 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
/* Stop here if not JESD216 rev A or later. */
if (bfpt_header->length < BFPT_DWORD_MAX)
- return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
- params);
+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, flash);
/* Page size: this field specifies 'N' so the page size = 2^N bytes. */
- params->page_size = bfpt.dwords[BFPT_DWORD(11)];
- params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
- params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
- params->page_size = 1U << params->page_size;
+ flash->page_size = bfpt.dwords[BFPT_DWORD(11)];
+ flash->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
+ flash->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
+ flash->page_size = 1U << flash->page_size;
/* Quad Enable Requirements. */
switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
case BFPT_DWORD15_QER_NONE:
- params->quad_enable = NULL;
+ flash->quad_enable = NULL;
break;
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
- params->quad_enable = spansion_no_read_cr_quad_enable;
+ flash->quad_enable = spansion_no_read_cr_quad_enable;
break;
case BFPT_DWORD15_QER_SR1_BIT6:
- params->quad_enable = macronix_quad_enable;
+ flash->quad_enable = macronix_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT7:
- params->quad_enable = sr2_bit7_quad_enable;
+ flash->quad_enable = sr2_bit7_quad_enable;
break;
case BFPT_DWORD15_QER_SR2_BIT1:
- params->quad_enable = spansion_read_cr_quad_enable;
+ flash->quad_enable = spansion_read_cr_quad_enable;
break;
default:
return -EINVAL;
}
- return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
+ return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, flash);
}
#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
@@ -3721,7 +3720,7 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
/**
* spi_nor_init_non_uniform_erase_map() - initialize the non-uniform erase map
* @nor: pointer to a 'struct spi_nor'
- * @params: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
+ * @flash: pointer to a duplicate 'struct spi_nor_flash_parameter' that is
* used for storing SFDP parsed data
* @smpt: pointer to the sector map parameter table
*
@@ -3729,10 +3728,10 @@ spi_nor_region_check_overlay(struct spi_nor_erase_region *region,
*/
static int
spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
- struct spi_nor_flash_parameter *params,
+ struct spi_nor_flash_parameter *flash,
const u32 *smpt)
{
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase = map->erase_type;
struct spi_nor_erase_region *region;
u64 offset;
@@ -3811,7 +3810,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
* spi_nor_parse_smpt() - parse Sector Map Parameter Table
* @nor: pointer to a 'struct spi_nor'
* @smpt_header: sector map parameter table header
- * @params: pointer to a duplicate 'struct spi_nor_flash_parameter'
+ * @flash: pointer to a duplicate 'struct spi_nor_flash_parameter'
* that is used for storing SFDP parsed data
*
* This table is optional, but when available, we parse it to identify the
@@ -3822,7 +3821,7 @@ spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
*/
static int spi_nor_parse_smpt(struct spi_nor *nor,
const struct sfdp_parameter_header *smpt_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
const u32 *sector_map;
u32 *smpt;
@@ -3851,11 +3850,11 @@ static int spi_nor_parse_smpt(struct spi_nor *nor,
goto out;
}
- ret = spi_nor_init_non_uniform_erase_map(nor, params, sector_map);
+ ret = spi_nor_init_non_uniform_erase_map(nor, flash, sector_map);
if (ret)
goto out;
- spi_nor_regions_sort_erase_types(¶ms->erase_map);
+ spi_nor_regions_sort_erase_types(&flash->erase_map);
/* fall through */
out:
kfree(smpt);
@@ -3880,13 +3879,13 @@ struct sfdp_4bait {
* @nor: pointer to a 'struct spi_nor'.
* @param_header: pointer to the 'struct sfdp_parameter_header' describing
* the 4-Byte Address Instruction Table length and version.
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be.
*
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_parse_4bait(struct spi_nor *nor,
const struct sfdp_parameter_header *param_header,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
static const struct sfdp_4bait reads[] = {
{ SNOR_HWCAPS_READ, BIT(0) },
@@ -3910,8 +3909,8 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
{ 0u /* not used */, BIT(11) },
{ 0u /* not used */, BIT(12) },
};
- struct spi_nor_pp_command *params_pp = params->page_programs;
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_pp_command *flash_pp = flash->page_programs;
+ struct spi_nor_erase_map *map = &flash->erase_map;
struct spi_nor_erase_type *erase_type = map->erase_type;
u32 *dwords;
size_t len;
@@ -3949,7 +3948,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
const struct sfdp_4bait *read = &reads[i];
discard_hwcaps |= read->hwcaps;
- if ((params->hwcaps.mask & read->hwcaps) &&
+ if ((flash->hwcaps.mask & read->hwcaps) &&
(dwords[0] & read->supported_bit))
read_hwcaps |= read->hwcaps;
}
@@ -3965,7 +3964,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
/*
* The 4 Byte Address Instruction (Optional) Table is the only
* SFDP table that indicates support for Page Program Commands.
- * Bypass the params->hwcaps.mask and consider 4BAIT the biggest
+ * Bypass the flash->hwcaps.mask and consider 4BAIT the biggest
* authority for specifying Page Program support.
*/
discard_hwcaps |= program->hwcaps;
@@ -4000,26 +3999,26 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
* Discard all operations from the 4-byte instruction set which are
* not supported by this memory.
*/
- params->hwcaps.mask &= ~discard_hwcaps;
- params->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
+ flash->hwcaps.mask &= ~discard_hwcaps;
+ flash->hwcaps.mask |= (read_hwcaps | pp_hwcaps);
/* Use the 4-byte address instruction set. */
for (i = 0; i < SNOR_CMD_READ_MAX; i++) {
- struct spi_nor_read_command *read_cmd = ¶ms->reads[i];
+ struct spi_nor_read_command *read_cmd = &flash->reads[i];
read_cmd->opcode = spi_nor_convert_3to4_read(read_cmd->opcode);
}
/* 4BAIT is the only SFDP table that indicates page program support. */
if (pp_hwcaps & SNOR_HWCAPS_PP)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP],
SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
if (pp_hwcaps & SNOR_HWCAPS_PP_1_1_4)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP_1_1_4],
SPINOR_OP_PP_1_1_4_4B,
SNOR_PROTO_1_1_4);
if (pp_hwcaps & SNOR_HWCAPS_PP_1_4_4)
- spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_4_4],
+ spi_nor_set_pp_settings(&flash_pp[SNOR_CMD_PP_1_4_4],
SPINOR_OP_PP_1_4_4_4B,
SNOR_PROTO_1_4_4);
@@ -4050,7 +4049,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
/**
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
* @nor: pointer to a 'struct spi_nor'
- * @params: pointer to the 'struct spi_nor_flash_parameter' to be
+ * @flash: pointer to the 'struct spi_nor_flash_parameter' to be
* filled
*
* The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
@@ -4062,7 +4061,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_parse_sfdp(struct spi_nor *nor,
- struct spi_nor_flash_parameter *params)
+ struct spi_nor_flash_parameter *flash)
{
const struct sfdp_parameter_header *param_header, *bfpt_header;
struct sfdp_parameter_header *param_headers = NULL;
@@ -4131,7 +4130,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
bfpt_header = param_header;
}
- err = spi_nor_parse_bfpt(nor, bfpt_header, params);
+ err = spi_nor_parse_bfpt(nor, bfpt_header, flash);
if (err)
goto exit;
@@ -4141,11 +4140,11 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
switch (SFDP_PARAM_HEADER_ID(param_header)) {
case SFDP_SECTOR_MAP_ID:
- err = spi_nor_parse_smpt(nor, param_header, params);
+ err = spi_nor_parse_smpt(nor, param_header, flash);
break;
case SFDP_4BAIT_ID:
- err = spi_nor_parse_4bait(nor, param_header, params);
+ err = spi_nor_parse_4bait(nor, param_header, flash);
break;
default:
@@ -4183,7 +4182,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- read = &nor->params.reads[cmd];
+ read = &nor->flash.reads[cmd];
nor->read_opcode = read->opcode;
nor->read_proto = read->proto;
@@ -4214,7 +4213,7 @@ static int spi_nor_select_pp(struct spi_nor *nor,
if (cmd < 0)
return -EINVAL;
- pp = &nor->params.page_programs[cmd];
+ pp = &nor->flash.page_programs[cmd];
nor->program_opcode = pp->opcode;
nor->write_proto = pp->proto;
return 0;
@@ -4275,7 +4274,7 @@ spi_nor_select_uniform_erase(struct spi_nor_erase_map *map,
static int spi_nor_select_erase(struct spi_nor *nor)
{
- struct spi_nor_erase_map *map = &nor->params.erase_map;
+ struct spi_nor_erase_map *map = &nor->flash.erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size;
@@ -4324,7 +4323,7 @@ static int spi_nor_select_erase(struct spi_nor *nor)
static int spi_nor_default_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
u32 ignored_mask, shared_mask;
int err;
@@ -4332,7 +4331,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,
* Keep only the hardware capabilities supported by both the SPI
* controller and the SPI flash memory.
*/
- shared_mask = hwcaps->mask & params->hwcaps.mask;
+ shared_mask = hwcaps->mask & flash->hwcaps.mask;
if (nor->spimem) {
/*
@@ -4385,36 +4384,36 @@ static int spi_nor_default_setup(struct spi_nor *nor,
static int spi_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
- if (!nor->params.setup)
+ if (!nor->flash.setup)
return 0;
- return nor->params.setup(nor, hwcaps);
+ return nor->flash.setup(nor, hwcaps);
}
static void macronix_set_default_init(struct spi_nor *nor)
{
- nor->params.quad_enable = macronix_quad_enable;
- nor->params.set_4byte = macronix_set_4byte;
+ nor->flash.quad_enable = macronix_quad_enable;
+ nor->flash.set_4byte = macronix_set_4byte;
}
static void st_micron_set_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
- nor->params.quad_enable = NULL;
- nor->params.set_4byte = st_micron_set_4byte;
+ nor->flash.quad_enable = NULL;
+ nor->flash.set_4byte = st_micron_set_4byte;
}
static void winbond_set_default_init(struct spi_nor *nor)
{
- nor->params.set_4byte = winbond_set_4byte;
+ nor->flash.set_4byte = winbond_set_4byte;
}
/**
- * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
- * settings based on MFR register and ->default_init() hook.
+ * spi_nor_manufacturer_init_flash_params() - Initialize the flash's
+ * parameters and settings based on MFR register and ->default_init() hook.
* @nor: pointer to a 'struct spi-nor'.
*/
-static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
+static void spi_nor_manufacturer_init_flash_params(struct spi_nor *nor)
{
/* Init flash parameters based on MFR */
switch (JEDEC_MFR(nor->info)) {
@@ -4440,93 +4439,93 @@ static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
}
/**
- * spi_nor_sfdp_init_params() - Initialize the flash's parameters and settings
- * based on JESD216 SFDP standard.
+ * spi_nor_sfdp_init_flash_params() - Initialize the flash's parameters and
+ * settings based on JESD216 SFDP standard.
* @nor: pointer to a 'struct spi-nor'.
*
* The method has a roll-back mechanism: in case the SFDP parsing fails, the
* legacy flash parameters and settings will be restored.
*/
-static void spi_nor_sfdp_init_params(struct spi_nor *nor)
+static void spi_nor_sfdp_init_flash_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter sfdp_params;
+ struct spi_nor_flash_parameter sfdp_flash;
- memcpy(&sfdp_params, &nor->params, sizeof(sfdp_params));
+ memcpy(&sfdp_flash, &nor->flash, sizeof(sfdp_flash));
- if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
+ if (spi_nor_parse_sfdp(nor, &sfdp_flash)) {
nor->addr_width = 0;
nor->flags &= ~SNOR_F_4B_OPCODES;
} else {
- memcpy(&nor->params, &sfdp_params, sizeof(nor->params));
+ memcpy(&nor->flash, &sfdp_flash, sizeof(nor->flash));
}
}
/**
- * spi_nor_info_init_params() - Initialize the flash's parameters and settings
- * based on nor->info data.
+ * spi_nor_info_init_flash_params() - Initialize the flash's parameters and
+ * settings based on nor->info data.
* @nor: pointer to a 'struct spi-nor'.
*/
-static void spi_nor_info_init_params(struct spi_nor *nor)
+static void spi_nor_info_init_flash_params(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = &nor->params;
- struct spi_nor_erase_map *map = ¶ms->erase_map;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
+ struct spi_nor_erase_map *map = &flash->erase_map;
const struct flash_info *info = nor->info;
struct device_node *np = spi_nor_get_flash_node(nor);
u8 i, erase_mask;
/* Initialize legacy flash parameters and settings. */
- params->quad_enable = spansion_quad_enable;
- params->set_4byte = spansion_set_4byte;
- params->setup = spi_nor_default_setup;
+ flash->quad_enable = spansion_quad_enable;
+ flash->set_4byte = spansion_set_4byte;
+ flash->setup = spi_nor_default_setup;
/* Set SPI NOR sizes. */
- params->size = (u64)info->sector_size * info->n_sectors;
- params->page_size = info->page_size;
+ flash->size = (u64)info->sector_size * info->n_sectors;
+ flash->page_size = info->page_size;
if (!(info->flags & SPI_NOR_NO_FR)) {
/* Default to Fast Read for DT and non-DT platform devices. */
- params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
/* Mask out Fast Read if not requested at DT instantiation. */
if (np && !of_property_read_bool(np, "m25p,fast-read"))
- params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
+ flash->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
}
/* (Fast) Read settings. */
- params->hwcaps.mask |= SNOR_HWCAPS_READ;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ],
0, 0, SPINOR_OP_READ,
SNOR_PROTO_1_1_1);
- if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
+ if (flash->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_FAST],
0, 8, SPINOR_OP_READ_FAST,
SNOR_PROTO_1_1_1);
if (info->flags & SPI_NOR_DUAL_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_2],
0, 8, SPINOR_OP_READ_1_1_2,
SNOR_PROTO_1_1_2);
}
if (info->flags & SPI_NOR_QUAD_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_4],
0, 8, SPINOR_OP_READ_1_1_4,
SNOR_PROTO_1_1_4);
}
if (info->flags & SPI_NOR_OCTAL_READ) {
- params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
- spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
+ flash->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(&flash->reads[SNOR_CMD_READ_1_1_8],
0, 8, SPINOR_OP_READ_1_1_8,
SNOR_PROTO_1_1_8);
}
/* Page Program settings. */
- params->hwcaps.mask |= SNOR_HWCAPS_PP;
- spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
+ flash->hwcaps.mask |= SNOR_HWCAPS_PP;
+ spi_nor_set_pp_settings(&flash->page_programs[SNOR_CMD_PP],
SPINOR_OP_PP, SNOR_PROTO_1_1_1);
/*
@@ -4549,7 +4548,7 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
erase_mask |= BIT(i);
spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
SPINOR_OP_SE);
- spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
+ spi_nor_init_uniform_erase_map(map, erase_mask, flash->size);
}
static void spansion_post_sfdp_fixups(struct spi_nor *nor)
@@ -4567,7 +4566,7 @@ static void spansion_post_sfdp_fixups(struct spi_nor *nor)
static void s3an_post_sfdp_fixups(struct spi_nor *nor)
{
- nor->params.setup = s3an_nor_setup;
+ nor->flash.setup = s3an_nor_setup;
}
/**
@@ -4599,24 +4598,25 @@ static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
}
/**
- * spi_nor_late_init_params() - Late initialization of default flash parameters.
+ * spi_nor_late_init_flash_params() - Late initialization of default flash
+ * parameters.
* @nor: pointer to a 'struct spi_nor'
*
* Used to set default flash parameters and settings when the ->default_init()
* hook or the SFDP parser let voids.
*/
-static void spi_nor_late_init_params(struct spi_nor *nor)
+static void spi_nor_late_init_flash_params(struct spi_nor *nor)
{
/*
* NOR protection support. When locking_ops are not provided, we pick
* the default ones.
*/
- if (nor->flags & SNOR_F_HAS_LOCK && !nor->params.locking_ops)
- nor->params.locking_ops = &stm_locking_ops;
+ if (nor->flags & SNOR_F_HAS_LOCK && !nor->flash.locking_ops)
+ nor->flash.locking_ops = &stm_locking_ops;
}
/**
- * spi_nor_init_params() - Initialize the flash's parameters and settings.
+ * spi_nor_init_flash_params() - Initialize the flash's parameters and settings.
* @nor: pointer to a 'struct spi-nor'.
*
* The flash parameters and settings are initialized based on a sequence of
@@ -4624,18 +4624,18 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
*
* 1/ Default flash parameters initialization. The initializations are done
* based on nor->info data:
- * spi_nor_info_init_params()
+ * spi_nor_info_init_flash_params()
*
* which can be overwritten by:
* 2/ Manufacturer flash parameters initialization. The initializations are
* done based on MFR register, or when the decisions can not be done solely
* based on MFR, by using specific flash_info tweeks, ->default_init():
- * spi_nor_manufacturer_init_params()
+ * spi_nor_manufacturer_init_flash_params()
*
* which can be overwritten by:
* 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
* should be more accurate that the above.
- * spi_nor_sfdp_init_params()
+ * spi_nor_sfdp_init_flash_params()
*
* Please note that there is a ->post_bfpt() fixup hook that can overwrite
* the flash parameters and settings immediately after parsing the Basic
@@ -4649,22 +4649,22 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
* spi_nor_post_sfdp_fixups()
*
* 5/ Late default flash parameters initialization, used when the
- * ->default_init() hook or the SFDP parser do not set specific params.
- * spi_nor_late_init_params()
+ * ->default_init() hook or the SFDP parser do not set specific flash params.
+ * spi_nor_late_init_flash_params()
*/
-static void spi_nor_init_params(struct spi_nor *nor)
+static void spi_nor_init_flash_params(struct spi_nor *nor)
{
- spi_nor_info_init_params(nor);
+ spi_nor_info_init_flash_params(nor);
- spi_nor_manufacturer_init_params(nor);
+ spi_nor_manufacturer_init_flash_params(nor);
if ((nor->info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
!(nor->info->flags & SPI_NOR_SKIP_SFDP))
- spi_nor_sfdp_init_params(nor);
+ spi_nor_sfdp_init_flash_params(nor);
spi_nor_post_sfdp_fixups(nor);
- spi_nor_late_init_params(nor);
+ spi_nor_late_init_flash_params(nor);
}
/**
@@ -4675,14 +4675,14 @@ static void spi_nor_init_params(struct spi_nor *nor)
*/
static int spi_nor_quad_enable(struct spi_nor *nor)
{
- if (!nor->params.quad_enable)
+ if (!nor->flash.quad_enable)
return 0;
if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
spi_nor_get_protocol_width(nor->write_proto) == 4))
return 0;
- return nor->params.quad_enable(nor);
+ return nor->flash.quad_enable(nor);
}
static int spi_nor_init(struct spi_nor *nor)
@@ -4690,7 +4690,7 @@ static int spi_nor_init(struct spi_nor *nor)
int err;
if (nor->clear_sr_bp) {
- if (nor->params.quad_enable == spansion_quad_enable)
+ if (nor->flash.quad_enable == spansion_quad_enable)
nor->clear_sr_bp = spi_nor_spansion_clear_sr_bp;
err = nor->clear_sr_bp(nor);
@@ -4717,7 +4717,7 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- nor->params.set_4byte(nor, true);
+ nor->flash.set_4byte(nor, true);
}
return 0;
@@ -4741,7 +4741,7 @@ void spi_nor_restore(struct spi_nor *nor)
/* restore the addressing mode */
if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET)
- nor->params.set_4byte(nor, false);
+ nor->flash.set_4byte(nor, false);
}
EXPORT_SYMBOL_GPL(spi_nor_restore);
@@ -4841,7 +4841,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
struct device_node *np = spi_nor_get_flash_node(nor);
- struct spi_nor_flash_parameter *params = &nor->params;
+ struct spi_nor_flash_parameter *flash = &nor->flash;
int ret;
int i;
@@ -4900,7 +4900,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
nor->clear_sr_bp = spi_nor_clear_sr_bp;
/* Init flash parameters based on flash_info struct and SFDP */
- spi_nor_init_params(nor);
+ spi_nor_init_flash_params(nor);
if (!mtd->name)
mtd->name = dev_name(dev);
@@ -4908,12 +4908,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->type = MTD_NORFLASH;
mtd->writesize = 1;
mtd->flags = MTD_CAP_NORFLASH;
- mtd->size = params->size;
+ mtd->size = flash->size;
mtd->_erase = spi_nor_erase;
mtd->_read = spi_nor_read;
mtd->_resume = spi_nor_resume;
- if (nor->params.locking_ops) {
+ if (nor->flash.locking_ops) {
mtd->_lock = spi_nor_lock;
mtd->_unlock = spi_nor_unlock;
mtd->_is_locked = spi_nor_is_locked;
@@ -4938,7 +4938,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
- nor->page_size = params->page_size;
+ nor->page_size = flash->page_size;
mtd->writebufsize = nor->page_size;
if (of_property_read_bool(np, "broken-flash-reset"))
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index d1d736d3c8ab..12961b157743 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -580,10 +580,10 @@ struct flash_info;
* @controller_ops: SPI NOR controller driver specific operations.
* @clear_sr_bp: [FLASH-SPECIFIC] clears the Block Protection Bits from
* the SPI NOR Status Register.
- * @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
- * The structure includes legacy flash parameters and
- * settings that can be overwritten by the spi_nor_fixups
- * hooks, or dynamically when parsing the SFDP tables.
+ * @flash: SPI-NOR flash parameters and settings. The structure
+ * includes default flash parameters and settings that can
+ * be overwritten by the spi_nor_fixups hooks, or
+ * dynamically when parsing the SFDP tables.
* @priv: the private data
*/
struct spi_nor {
@@ -609,7 +609,7 @@ struct spi_nor {
const struct spi_nor_controller_ops *controller_ops;
int (*clear_sr_bp)(struct spi_nor *nor);
- struct spi_nor_flash_parameter params;
+ struct spi_nor_flash_parameter flash;
void *priv;
};
@@ -640,7 +640,7 @@ spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
{
- return !!nor->params.erase_map.uniform_erase_type;
+ return !!nor->flash.erase_map.uniform_erase_type;
}
static inline void spi_nor_set_flash_node(struct spi_nor *nor,
--
2.9.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related
* [PATCH v2 05/22] mtd: spi-nor: Rework read_sr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_sr(struct spi_nor *nor)
becomes
static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Status Register will be written. This way we avoid
the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
S/pr_err/dev_err and drop duplicated dev_err in callers, in case the
function returns error.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 131 +++++++++++++++++++++---------------------
1 file changed, 65 insertions(+), 66 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7d0c1b598250..a23783641146 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -388,12 +388,14 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
return nor->controller_ops->write(nor, to, len, buf);
}
-/*
- * Read the status register, returning its value in the location
- * Return the status register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_sr() - Read the Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_sr(struct spi_nor *nor)
+static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
{
int ret;
@@ -402,20 +404,17 @@ static int read_sr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, sr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR,
- nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, sr, 1);
}
- if (ret < 0) {
- pr_err("error %d reading SR\n", (int) ret);
- return ret;
- }
+ if (ret)
+ dev_err(nor->dev, "error %d reading SR\n", ret);
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -752,12 +751,14 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
static int spi_nor_sr_ready(struct spi_nor *nor)
{
- int sr = read_sr(nor);
- if (sr < 0)
- return sr;
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
- if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
- if (sr & SR_E_ERR)
+ if (nor->flags & SNOR_F_USE_CLSR &&
+ nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+ if (nor->bouncebuf[0] & SR_E_ERR)
dev_err(nor->dev, "Erase Error occurred\n");
else
dev_err(nor->dev, "Programming Error occurred\n");
@@ -766,7 +767,7 @@ static int spi_nor_sr_ready(struct spi_nor *nor)
return -EIO;
}
- return !(sr & SR_WIP);
+ return !(nor->bouncebuf[0] & SR_WIP);
}
static int spi_nor_clear_fsr(struct spi_nor *nor)
@@ -1341,11 +1342,11 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
if (ret)
return ret;
- ret = read_sr(nor);
- if (ret < 0)
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
return ret;
- return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
+ return ((nor->bouncebuf[0] & mask) != (status_new & mask)) ? -EIO : 0;
}
static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
@@ -1440,16 +1441,18 @@ static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- int status_old, status_new;
+ int ret, status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
- if (status_old < 0)
- return status_old;
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ status_old = nor->bouncebuf[0];
/* If nothing in our range is unlocked, we don't need to do anything */
if (stm_is_locked_sr(nor, ofs, len, status_old))
@@ -1520,16 +1523,18 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
- int status_old, status_new;
+ int ret, status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
- if (status_old < 0)
- return status_old;
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ status_old = nor->bouncebuf[0];
/* If nothing in our range is locked, we don't need to do anything */
if (stm_is_unlocked_sr(nor, ofs, len, status_old))
@@ -1604,13 +1609,12 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
*/
static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
- int status;
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- status = read_sr(nor);
- if (status < 0)
- return status;
+ if (ret)
+ return ret;
- return stm_is_locked_sr(nor, ofs, len, status);
+ return stm_is_locked_sr(nor, ofs, len, nor->bouncebuf[0]);
}
static const struct spi_nor_locking_ops stm_locking_ops = {
@@ -1717,24 +1721,28 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
*/
static int macronix_quad_enable(struct spi_nor *nor)
{
- int ret, val;
+ int ret;
- val = read_sr(nor);
- if (val < 0)
- return val;
- if (val & SR_QUAD_EN_MX)
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
write_enable(nor);
- write_sr(nor, val | SR_QUAD_EN_MX);
+ write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
ret = spi_nor_wait_till_ready(nor);
if (ret)
return ret;
- ret = read_sr(nor);
- if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (!(nor->bouncebuf[0] & SR_QUAD_EN_MX)) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL;
}
@@ -1805,12 +1813,10 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
int ret;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev, "error while reading status register\n");
- return -EINVAL;
- }
- sr_cr[0] = ret;
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
+ return ret;
+
sr_cr[1] = CR_QUAD_EN_SPAN;
return write_sr_cr(nor, sr_cr);
@@ -1848,12 +1854,9 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(dev, "error while reading status register\n");
- return -EINVAL;
- }
- sr_cr[0] = ret;
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
+ return ret;
ret = write_sr_cr(nor, sr_cr);
if (ret)
@@ -1964,15 +1967,13 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
int ret;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev, "error while reading status register\n");
+ ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+ if (ret)
return ret;
- }
write_enable(nor);
- ret = write_sr(nor, ret & ~mask);
+ ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) {
dev_err(nor->dev, "write to status register failed\n");
return ret;
@@ -2018,13 +2019,11 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
if (ret & CR_QUAD_EN_SPAN) {
sr_cr[1] = ret;
- ret = read_sr(nor);
- if (ret < 0) {
- dev_err(nor->dev,
- "error while reading status register\n");
+ ret = spi_nor_read_sr(nor, &sr_cr[0]);
+ if (ret)
return ret;
- }
- sr_cr[0] = ret & ~mask;
+
+ sr_cr[0] &= ~mask;
ret = write_sr_cr(nor, sr_cr);
if (ret)
--
2.9.5
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 07/22] mtd: spi-nor: Rework read_cr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_cr(struct spi_nor *nor)
becomes
static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Configuration Register will be written. This way
we avoid the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
Vendors are using both the "Configuration Register" and the
"Status Register 2" terminology when referring to the second byte
of the Status Register. Indicate in the description of the function
that we use the SPINOR_OP_RDCR (35h) command to interrogate the
Configuration Register.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 66 +++++++++++++++++++++----------------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8cd1cadcb8b1..0fb124bd2e77 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -448,12 +448,16 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
return ret;
}
-/*
- * Read configuration register, returning its value in the
- * location. Return the configuration register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_cr() - Read the Configuration Register using the
+ * SPINOR_OP_RDCR (35h) command.
+ * @nor: pointer to 'struct spi_nor'
+ * @cr: buffer where the value of the Configuration Register
+ * will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_cr(struct spi_nor *nor)
+static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
{
int ret;
@@ -462,20 +466,17 @@ static int read_cr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, cr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR,
- nor->bouncebuf, 1);
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
}
- if (ret < 0) {
+ if (ret)
dev_err(nor->dev, "error %d reading CR\n", ret);
- return ret;
- }
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -1768,7 +1769,8 @@ static int macronix_quad_enable(struct spi_nor *nor)
* some very old and few memories don't support this instruction. If a pull-up
* resistor is present on the MISO/IO1 line, we might still be able to pass the
* "read back" test because the QSPI memory doesn't recognize the command,
- * so leaves the MISO/IO1 line state unchanged, hence read_cr() returns 0xFF.
+ * so leaves the MISO/IO1 line state unchanged, hence spi_nor_read_cr(nor, cr)
+ * gets the 0xFF value.
*
* bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
* memories.
@@ -1787,8 +1789,11 @@ static int spansion_quad_enable(struct spi_nor *nor)
return ret;
/* read back and check it */
- ret = read_cr(nor);
- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+ ret = spi_nor_read_cr(nor, &nor->bouncebuf[0]);
+ if (ret)
+ return ret;
+
+ if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@@ -1839,21 +1844,18 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
*/
static int spansion_read_cr_quad_enable(struct spi_nor *nor)
{
- struct device *dev = nor->dev;
u8 *sr_cr = nor->bouncebuf;
int ret;
/* Check current Quad Enable bit value. */
- ret = read_cr(nor);
- if (ret < 0) {
- dev_err(dev, "error while reading configuration register\n");
- return -EINVAL;
- }
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
- if (ret & CR_QUAD_EN_SPAN)
+ if (sr_cr[1] & CR_QUAD_EN_SPAN)
return 0;
- sr_cr[1] = ret | CR_QUAD_EN_SPAN;
+ sr_cr[1] |= CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
ret = spi_nor_read_sr(nor, &sr_cr[0]);
@@ -1865,8 +1867,11 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return ret;
/* Read back and check it. */
- ret = read_cr(nor);
- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
+ return ret;
+
+ if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@@ -2007,20 +2012,15 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
u8 *sr_cr = nor->bouncebuf;
/* Check current Quad Enable bit value. */
- ret = read_cr(nor);
- if (ret < 0) {
- dev_err(nor->dev,
- "error while reading configuration register\n");
+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
+ if (ret)
return ret;
- }
/*
* When the configuration register Quad Enable bit is one, only the
* Write Status (01h) command with two data bytes may be used.
*/
- if (ret & CR_QUAD_EN_SPAN) {
- sr_cr[1] = ret;
-
+ if (sr_cr[1] & CR_QUAD_EN_SPAN) {
ret = spi_nor_read_sr(nor, &sr_cr[0]);
if (ret)
return ret;
--
2.9.5
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 06/22] mtd: spi-nor: Rework read_fsr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int read_fsr(struct spi_nor *nor)
becomes
static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
The new function returns 0 on success and -errno otherwise.
We let the callers pass the pointer to the buffer where the
value of the Flag Status Register will be written. This way
we avoid the casts between int and u8, which can be confusing.
Prepend spi_nor_ to the function name, all functions should begin
with that.
S/pr_err/dev_err and drop duplicated dev_err in callers, in case the
function returns error.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 42 ++++++++++++++++++++++--------------------
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index a23783641146..8cd1cadcb8b1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -417,12 +417,15 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
return ret;
}
-/*
- * Read the flag status register, returning its value in the location
- * Return the status register value.
- * Returns negative if error occurred.
+/**
+ * spi_nor_read_fsr() - Read the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ * @fsr: buffer where the value of the Flag Status Register will be
+ * written.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int read_fsr(struct spi_nor *nor)
+static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
{
int ret;
@@ -431,20 +434,18 @@ static int read_fsr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_IN(1, fsr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDFSR,
- nor->bouncebuf, 1);
+ fsr, 1);
}
- if (ret < 0) {
- pr_err("error %d reading FSR\n", ret);
- return ret;
- }
+ if (ret)
+ dev_err(nor->dev, "error %d reading FSR\n", ret);
- return nor->bouncebuf[0];
+ return ret;
}
/*
@@ -787,25 +788,26 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
static int spi_nor_fsr_ready(struct spi_nor *nor)
{
- int fsr = read_fsr(nor);
- if (fsr < 0)
- return fsr;
+ int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
- if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
- if (fsr & FSR_E_ERR)
+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+ if (nor->bouncebuf[0] & FSR_E_ERR)
dev_err(nor->dev, "Erase operation failed.\n");
else
dev_err(nor->dev, "Program operation failed.\n");
- if (fsr & FSR_PT_ERR)
+ if (nor->bouncebuf[0] & FSR_PT_ERR)
dev_err(nor->dev,
- "Attempted to modify a protected sector.\n");
+ "Attempted to modify a protected sector.\n");
spi_nor_clear_fsr(nor);
return -EIO;
}
- return fsr & FSR_READY;
+ return nor->bouncebuf[0] & FSR_READY;
}
static int spi_nor_ready(struct spi_nor *nor)
--
2.9.5
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* [PATCH v2 09/22] mtd: spi-nor: Fix retlen handling in sst_write()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
In case the write of the first byte failed, retlen was incorrectly
incremented to *retlen += actual; on the exit path. retlen should be
incremented when actual data was written to the flash.
Rename 'sst_write_err' label to 'out' as it is no longer generic for
all the write errors in the sst_write() method, and may introduce
confusion.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0aee068a5835..be5dee622d51 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2665,12 +2665,12 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
/* write one byte. */
ret = spi_nor_write_data(nor, to, 1, buf);
if (ret < 0)
- goto sst_write_err;
+ goto unlock_and_unprep;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto unlock_and_unprep;
}
to += actual;
@@ -2681,12 +2681,12 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
/* write two bytes. */
ret = spi_nor_write_data(nor, to, 2, buf + actual);
if (ret < 0)
- goto sst_write_err;
+ goto out;
WARN(ret != 2, "While writing 2 bytes written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
to += 2;
nor->sst_write_second = true;
}
@@ -2694,35 +2694,35 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_write_disable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
/* Write out trailing byte if it exists. */
if (actual != len) {
ret = spi_nor_write_enable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
if (ret < 0)
- goto sst_write_err;
+ goto out;
WARN(ret != 1, "While writing 1 byte written %i bytes\n",
(int)ret);
ret = spi_nor_wait_till_ready(nor);
if (ret)
- goto sst_write_err;
+ goto out;
ret = spi_nor_write_disable(nor);
if (ret)
- goto sst_write_err;
+ goto out;
actual += 1;
}
-sst_write_err:
+out:
*retlen += actual;
unlock_and_unprep:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
--
2.9.5
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* [PATCH v2 08/22] mtd: spi-nor: Rework write_enable/disable()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
static int write_enable(struct spi_nor *nor)
static int write_disable(struct spi_nor *nor)
become
static int spi_nor_write_enable(struct spi_nor *nor)
static int spi_nor_write_disable(struct spi_nor *nor)
Check for errors after each call to them. Move them up in the
file as the first SPI NOR Register Operations, to avoid further
forward declarations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 175 +++++++++++++++++++++++++++++-------------
1 file changed, 120 insertions(+), 55 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0fb124bd2e77..0aee068a5835 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -389,6 +389,64 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
}
/**
+ * spi_nor_write_enable() - Set write enable latch with Write Enable command.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_enable(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WREN,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error %d on Write Enable\n", ret);
+
+ return ret;
+}
+
+/**
+ * spi_nor_write_disable() - Send Write Disable instruction to the chip.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_disable(struct spi_nor *nor)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI,
+ NULL, 0);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error %d on Write Disable\n", ret);
+
+ return ret;
+}
+
+/**
* spi_nor_read_sr() - Read the Status Register.
* @nor: pointer to 'struct spi_nor'
* @sr: buffer where the value of the Status Register will be written.
@@ -500,43 +558,6 @@ static int write_sr(struct spi_nor *nor, u8 val)
nor->bouncebuf, 1);
}
-/*
- * Set write enable latch with Write Enable command.
- * Returns negative if error occurred.
- */
-static int write_enable(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
-}
-
-/*
- * Send write disable instruction to the chip.
- */
-static int write_disable(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
-}
-
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return mtd->priv;
@@ -645,9 +666,15 @@ static int st_micron_set_4byte(struct spi_nor *nor, bool enable)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = macronix_set_4byte(nor, enable);
- write_disable(nor);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_write_disable(nor);
return ret;
}
@@ -701,9 +728,15 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
* Register to be set to 1, so all 3-byte-address reads come from the
* second 16M. We must clear the register to enable normal behavior.
*/
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = spi_nor_write_ear(nor, 0);
- write_disable(nor);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_write_disable(nor);
return ret;
}
@@ -1219,7 +1252,9 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
list_for_each_entry_safe(cmd, next, &erase_list, list) {
nor->erase_opcode = cmd->opcode;
while (cmd->count) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto destroy_erase_cmd_list;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
@@ -1274,7 +1309,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
if (erase_chip(nor)) {
ret = -EIO;
@@ -1302,7 +1339,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
while (len) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
ret = spi_nor_erase_sector(nor, addr);
if (ret)
@@ -1323,7 +1362,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
goto erase_err;
}
- write_disable(nor);
+ ret = spi_nor_write_disable(nor);
erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
@@ -1336,7 +1375,10 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
ret = write_sr(nor, status_new);
if (ret)
return ret;
@@ -1681,7 +1723,9 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
{
int ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
if (nor->spimem) {
struct spi_mem_op op =
@@ -1733,7 +1777,9 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
@@ -1936,7 +1982,9 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = spi_nor_write_sr2(nor, sr2);
if (ret < 0) {
@@ -1978,7 +2026,9 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
if (ret)
return ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
if (ret) {
@@ -2601,7 +2651,9 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
if (ret)
return ret;
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto unlock_and_unprep;
nor->sst_write_second = false;
@@ -2640,14 +2692,19 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
}
nor->sst_write_second = false;
- write_disable(nor);
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto sst_write_err;
+
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
/* Write out trailing byte if it exists. */
if (actual != len) {
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto sst_write_err;
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
@@ -2658,11 +2715,16 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
- write_disable(nor);
+
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto sst_write_err;
+
actual += 1;
}
sst_write_err:
*retlen += actual;
+unlock_and_unprep:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
@@ -2710,7 +2772,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
addr = spi_nor_convert_addr(nor, addr);
- write_enable(nor);
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto write_err;
+
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
if (ret < 0)
goto write_err;
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 10/22] mtd: spi-nor: Rework write_sr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The Status Register can be written with one or two bytes.
Merge:
static int write_sr(struct spi_nor *nor, u8 val)
static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
into
static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
Avoid duplicating code by moving the calls to spi_nor_write_enable() and
spi_nor_wait_till_ready() inside spi_nor_write_sr().
Move the spi_nor_wait_till_ready() together with the spi_nor_ready()
methods to avoid forward declarations.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 426 +++++++++++++++++++-----------------------
1 file changed, 191 insertions(+), 235 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index be5dee622d51..31a4622d1eb9 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -537,25 +537,198 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
return ret;
}
+static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr, 1));
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+}
+
+static int s3an_sr_ready(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = spi_nor_xread_sr(nor, nor->bouncebuf);
+ if (ret < 0) {
+ dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ return ret;
+ }
+
+ return !!(nor->bouncebuf[0] & XSR_RDY);
+}
+
+static int spi_nor_clear_sr(struct spi_nor *nor)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+}
+
+static int spi_nor_sr_ready(struct spi_nor *nor)
+{
+ int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
+
+ if (nor->flags & SNOR_F_USE_CLSR &&
+ nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
+ if (nor->bouncebuf[0] & SR_E_ERR)
+ dev_err(nor->dev, "Erase Error occurred\n");
+ else
+ dev_err(nor->dev, "Programming Error occurred\n");
+
+ spi_nor_clear_sr(nor);
+ return -EIO;
+ }
+
+ return !(nor->bouncebuf[0] & SR_WIP);
+}
+
+static int spi_nor_clear_fsr(struct spi_nor *nor)
+{
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_NO_DATA);
+
+ return spi_mem_exec_op(nor->spimem, &op);
+ }
+
+ return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+}
+
+static int spi_nor_fsr_ready(struct spi_nor *nor)
+{
+ int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
+
+ if (ret)
+ return ret;
+
+ if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+ if (nor->bouncebuf[0] & FSR_E_ERR)
+ dev_err(nor->dev, "Erase operation failed.\n");
+ else
+ dev_err(nor->dev, "Program operation failed.\n");
+
+ if (nor->bouncebuf[0] & FSR_PT_ERR)
+ dev_err(nor->dev,
+ "Attempted to modify a protected sector.\n");
+
+ spi_nor_clear_fsr(nor);
+ return -EIO;
+ }
+
+ return nor->bouncebuf[0] & FSR_READY;
+}
+
+static int spi_nor_ready(struct spi_nor *nor)
+{
+ int sr, fsr;
+
+ if (nor->flags & SNOR_F_READY_XSR_RDY)
+ sr = s3an_sr_ready(nor);
+ else
+ sr = spi_nor_sr_ready(nor);
+ if (sr < 0)
+ return sr;
+ fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
+ if (fsr < 0)
+ return fsr;
+ return sr && fsr;
+}
+
/*
- * Write status register 1 byte
- * Returns negative if error occurred.
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+ */
+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
+ unsigned long timeout_jiffies)
+{
+ unsigned long deadline;
+ int timeout = 0, ret;
+
+ deadline = jiffies + timeout_jiffies;
+
+ while (!timeout) {
+ if (time_after_eq(jiffies, deadline))
+ timeout = 1;
+
+ ret = spi_nor_ready(nor);
+ if (ret < 0)
+ return ret;
+ if (ret)
+ return 0;
+
+ cond_resched();
+ }
+
+ dev_err(nor->dev, "flash operation timed out\n");
+
+ return -ETIMEDOUT;
+}
+
+static int spi_nor_wait_till_ready(struct spi_nor *nor)
+{
+ return spi_nor_wait_till_ready_with_timeout(nor,
+ DEFAULT_READY_WAIT_JIFFIES);
+}
+
+/**
+ * spi_nor_write_sr() - Write the Status Register.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr: buffer to write to the Status Register.
+ * @len: number of bytes to write to the Status Register.
+ *
+ * Return: 0 on success, -errno otherwise.
*/
-static int write_sr(struct spi_nor *nor, u8 val)
+static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
{
- nor->bouncebuf[0] = val;
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
+ SPI_MEM_OP_DATA_OUT(len, sr, 1));
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
+ sr, len);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- nor->bouncebuf, 1);
+ if (ret) {
+ dev_err(nor->dev, "error while writing Status Register\n");
+ return ret;
+ }
+
+ ret = spi_nor_wait_till_ready(nor);
+
+ return ret;
}
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -741,161 +914,6 @@ static int winbond_set_4byte(struct spi_nor *nor, bool enable)
return ret;
}
-static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, sr, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
-}
-
-static int s3an_sr_ready(struct spi_nor *nor)
-{
- int ret;
-
- ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
- return ret;
- }
-
- return !!(nor->bouncebuf[0] & XSR_RDY);
-}
-
-static int spi_nor_clear_sr(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
-}
-
-static int spi_nor_sr_ready(struct spi_nor *nor)
-{
- int ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
-
- if (ret)
- return ret;
-
- if (nor->flags & SNOR_F_USE_CLSR &&
- nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
- if (nor->bouncebuf[0] & SR_E_ERR)
- dev_err(nor->dev, "Erase Error occurred\n");
- else
- dev_err(nor->dev, "Programming Error occurred\n");
-
- spi_nor_clear_sr(nor);
- return -EIO;
- }
-
- return !(nor->bouncebuf[0] & SR_WIP);
-}
-
-static int spi_nor_clear_fsr(struct spi_nor *nor)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_NO_DATA);
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
-}
-
-static int spi_nor_fsr_ready(struct spi_nor *nor)
-{
- int ret = spi_nor_read_fsr(nor, &nor->bouncebuf[0]);
-
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
- if (nor->bouncebuf[0] & FSR_E_ERR)
- dev_err(nor->dev, "Erase operation failed.\n");
- else
- dev_err(nor->dev, "Program operation failed.\n");
-
- if (nor->bouncebuf[0] & FSR_PT_ERR)
- dev_err(nor->dev,
- "Attempted to modify a protected sector.\n");
-
- spi_nor_clear_fsr(nor);
- return -EIO;
- }
-
- return nor->bouncebuf[0] & FSR_READY;
-}
-
-static int spi_nor_ready(struct spi_nor *nor)
-{
- int sr, fsr;
-
- if (nor->flags & SNOR_F_READY_XSR_RDY)
- sr = s3an_sr_ready(nor);
- else
- sr = spi_nor_sr_ready(nor);
- if (sr < 0)
- return sr;
- fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
- if (fsr < 0)
- return fsr;
- return sr && fsr;
-}
-
-/*
- * Service routine to read status register until ready, or timeout occurs.
- * Returns non-zero if error.
- */
-static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
- unsigned long timeout_jiffies)
-{
- unsigned long deadline;
- int timeout = 0, ret;
-
- deadline = jiffies + timeout_jiffies;
-
- while (!timeout) {
- if (time_after_eq(jiffies, deadline))
- timeout = 1;
-
- ret = spi_nor_ready(nor);
- if (ret < 0)
- return ret;
- if (ret)
- return 0;
-
- cond_resched();
- }
-
- dev_err(nor->dev, "flash operation timed out\n");
-
- return -ETIMEDOUT;
-}
-
-static int spi_nor_wait_till_ready(struct spi_nor *nor)
-{
- return spi_nor_wait_till_ready_with_timeout(nor,
- DEFAULT_READY_WAIT_JIFFIES);
-}
-
/*
* Erase the whole flash memory
*
@@ -1375,15 +1393,9 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
{
int ret;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- ret = write_sr(nor, status_new);
- if (ret)
- return ret;
+ nor->bouncebuf[0] = status_new;
- ret = spi_nor_wait_till_ready(nor);
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
if (ret)
return ret;
@@ -1713,49 +1725,6 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
return ret;
}
-/*
- * Write status Register and configuration register with 2 bytes
- * The first byte will be written to the status register, while the
- * second byte will be written to the configuration register.
- * Return negative if error occurred.
- */
-static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
-{
- int ret;
-
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(2, sr_cr, 1));
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR,
- sr_cr, 2);
- }
-
- if (ret < 0) {
- dev_err(nor->dev,
- "error while writing configuration register\n");
- return -EINVAL;
- }
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret) {
- dev_err(nor->dev,
- "timeout while writing configuration register\n");
- return ret;
- }
-
- return 0;
-}
-
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -1777,13 +1746,9 @@ static int macronix_quad_enable(struct spi_nor *nor)
if (nor->bouncebuf[0] & SR_QUAD_EN_MX)
return 0;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- write_sr(nor, nor->bouncebuf[0] | SR_QUAD_EN_MX);
+ nor->bouncebuf[0] |= SR_QUAD_EN_MX;
- ret = spi_nor_wait_till_ready(nor);
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
if (ret)
return ret;
@@ -1830,7 +1795,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
sr_cr[0] = 0;
sr_cr[1] = CR_QUAD_EN_SPAN;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -1872,7 +1837,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = CR_QUAD_EN_SPAN;
- return write_sr_cr(nor, sr_cr);
+ return spi_nor_write_sr(nor, sr_cr, 2);
}
/**
@@ -1908,7 +1873,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
return ret;
@@ -2026,19 +1991,10 @@ static int spi_nor_clear_sr_bp(struct spi_nor *nor)
if (ret)
return ret;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
+ nor->bouncebuf[0] &= mask;
- ret = write_sr(nor, nor->bouncebuf[0] & ~mask);
- if (ret) {
- dev_err(nor->dev, "write to status register failed\n");
- return ret;
- }
+ ret = spi_nor_write_sr(nor, &nor->bouncebuf[0], 1);
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- dev_err(nor->dev, "timeout while writing status register\n");
return ret;
}
@@ -2077,7 +2033,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
sr_cr[0] &= ~mask;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
dev_err(nor->dev, "16-bit write register failed\n");
return ret;
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 12/22] mtd: spi-nor: Report error in spi_nor_xread_sr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Report error inside spi_nor_xread_sr(), to spare the callers of
duplicating the error message.
Add method description. Drop unnecessary cast to int when reporting
the error. Comparing the return code with zero is enough, drop the
checking for negative return values.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 33130ee84164..b7f86f518331 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -537,8 +537,17 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
return ret;
}
+/**
+ * spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 1),
@@ -546,10 +555,16 @@ static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(1, sr, 1));
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR,
+ sr, 1);
}
- return nor->controller_ops->read_reg(nor, SPINOR_OP_XRDSR, sr, 1);
+ if (ret)
+ dev_err(nor->dev, "error %d reading XRDSR\n", ret);
+
+ return ret;
}
static int s3an_sr_ready(struct spi_nor *nor)
@@ -557,10 +572,8 @@ static int s3an_sr_ready(struct spi_nor *nor)
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ if (ret)
return ret;
- }
return !!(nor->bouncebuf[0] & XSR_RDY);
}
@@ -2800,10 +2813,8 @@ static int s3an_nor_setup(struct spi_nor *nor,
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
- if (ret < 0) {
- dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
+ if (ret)
return ret;
- }
nor->erase_opcode = SPINOR_OP_XSE;
nor->program_opcode = SPINOR_OP_XPP;
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 11/22] mtd: spi-nor: Rework spi_nor_read/write_sr2()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Move the methods up in the file, where the other Register
operations reside.
The error is reported inside each SR2 function, to spare the callers
of duplicating code.
Constify sr2 in spi_nor_write_sr2(). Do the spi_nor_write_enable() and
spi_nor_wait_till_ready() inside spi_nor_write_sr2(), as the
spi_nor_write_sr() does.
While modyfing sr2_bit7_quad_enable(), add a new line for better code
readability.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 118 ++++++++++++++++++++++++++----------------
1 file changed, 74 insertions(+), 44 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 31a4622d1eb9..33130ee84164 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -731,6 +731,74 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
return ret;
}
+/**
+ * spi_nor_write_sr2() - Write the Status Register 2 using the
+ * SPINOR_OP_WRSR2 (3eh) command.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr2: buffer to write to the Status Register.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
+{
+ int ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(1, sr2, 1));
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2,
+ sr2, 1);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error while writing Status Register 2\n");
+
+ ret = spi_nor_wait_till_ready(nor);
+
+ return ret;
+}
+
+/**
+ * spi_nor_read_sr2() - Read the Status Register 2 using the
+ * SPINOR_OP_RDSR2 (3fh) command.
+ * @nor: pointer to 'struct spi_nor'
+ * @sr2: buffer where the value of the Status Register will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr2, 1));
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2,
+ sr2, 1);
+ }
+
+ if (ret)
+ dev_err(nor->dev, "error while reading Status Register 2\n");
+
+ return ret;
+}
+
static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
{
return mtd->priv;
@@ -1890,36 +1958,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return 0;
}
-static int spi_nor_write_sr2(struct spi_nor *nor, u8 *sr2)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(1, sr2, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
-}
-
-static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
-{
- if (nor->spimem) {
- struct spi_mem_op op =
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 1),
- SPI_MEM_OP_NO_ADDR,
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_IN(1, sr2, 1));
-
- return spi_mem_exec_op(nor->spimem, &op);
- }
-
- return nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
-}
-
/**
* sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor'
@@ -1941,31 +1979,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
ret = spi_nor_read_sr2(nor, sr2);
if (ret)
return ret;
+
if (*sr2 & SR2_QUAD_EN_BIT7)
return 0;
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
ret = spi_nor_write_sr2(nor, sr2);
- if (ret < 0) {
- dev_err(nor->dev, "error while writing status register 2\n");
- return -EINVAL;
- }
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret < 0) {
- dev_err(nor->dev, "timeout while writing status register 2\n");
+ if (ret)
return ret;
- }
/* Read back and check it. */
ret = spi_nor_read_sr2(nor, sr2);
- if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {
+ if (ret)
+ return ret;
+
+ if (!(*sr2 & SR2_QUAD_EN_BIT7)) {
dev_err(nor->dev, "SR2 Quad bit not set\n");
return -EINVAL;
}
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 14/22] mtd: spi-nor: Drop duplicated new line
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Two new lines, remove one.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 191a76c3f7bb..d971f5a4b11f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -841,7 +841,6 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
-
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
--
2.9.5
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^ permalink raw reply related
* [PATCH v2 13/22] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()
From: Tudor.Ambarus @ 2019-09-24 7:46 UTC (permalink / raw)
To: vigneshr, boris.brezillon, marek.vasut, linux-mtd, geert+renesas,
jonas
Cc: linux-aspeed, Tudor.Ambarus, andrew, richard, linux-kernel, vz,
linux-mediatek, joel, miquel.raynal, matthias.bgg,
computersforpeace, dwmw2, linux-arm-kernel
In-Reply-To: <20190924074533.6618-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case
of errors. The callers didn't check their return value. Make them
of type void and print an error in case the operations fail.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/spi-nor.c | 36 ++++++++++++++++++++++++++++++------
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b7f86f518331..191a76c3f7bb 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -578,8 +578,16 @@ static int s3an_sr_ready(struct spi_nor *nor)
return !!(nor->bouncebuf[0] & XSR_RDY);
}
-static int spi_nor_clear_sr(struct spi_nor *nor)
+/**
+ * spi_nor_clear_sr() - Clear the Status Register 1.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Prints error in case the operation fails.
+ */
+static void spi_nor_clear_sr(struct spi_nor *nor)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 1),
@@ -587,10 +595,14 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR,
+ NULL, 0);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ if (ret)
+ dev_err(nor->dev, "error %d clearing Status Register 1\n", ret);
}
static int spi_nor_sr_ready(struct spi_nor *nor)
@@ -614,8 +626,16 @@ static int spi_nor_sr_ready(struct spi_nor *nor)
return !(nor->bouncebuf[0] & SR_WIP);
}
-static int spi_nor_clear_fsr(struct spi_nor *nor)
+/**
+ * spi_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Prints error in case the operation fails.
+ */
+static void spi_nor_clear_fsr(struct spi_nor *nor)
{
+ int ret;
+
if (nor->spimem) {
struct spi_mem_op op =
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 1),
@@ -623,10 +643,14 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_NO_DATA);
- return spi_mem_exec_op(nor->spimem, &op);
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR,
+ NULL, 0);
}
- return nor->controller_ops->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
+ if (ret)
+ dev_err(nor->dev, "error %d clearing FSR\n", ret);
}
static int spi_nor_fsr_ready(struct spi_nor *nor)
--
2.9.5
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