* Re: [PATCH v1 1/9] dmaengine: Actions: get rid of bit fields from dma descriptor
From: Amit Tomer @ 2020-05-14 18:34 UTC (permalink / raw)
To: Vinod Koul
Cc: Andre Przywara, linux-actions, cristian.ciocaltea,
Manivannan Sadhasivam, dmaengine, dan.j.williams,
Andreas Färber, linux-arm-kernel
In-Reply-To: <20200514182750.GJ14092@vkoul-mobl>
Hi,
On Thu, May 14, 2020 at 11:58 PM Vinod Koul <vkoul@kernel.org> wrote:
>
> On 14-05-20, 21:40, Amit Singh Tomar wrote:
> > At the moment, Driver uses bit fields to describe registers of the DMA
> > descriptor structure that makes it less portable and maintainable, and
> > Andre suugested(and even sketched important bits for it) to make use of
> > array to describe this DMA descriptors instead. It gives the flexibility
> > while extending support for other platform such as Actions S700.
> >
> > This commit removes the "owl_dma_lli_hw" (that includes bit-fields) and
> > uses array to describe DMA descriptor.
>
> So i see patch 1/9 and 2/9 in my inbox... where are the rest ? No cover
> to detail out what the rest contains, who should merge them etc etc!
>
> If you are sending a series to different subsystem please make a habit
> to CC everyone on cover letter so that we understand details about the
> series. If not dependent, just send as individual units to subsystems!
Ok, I would make note of it and Cc everyone on cover letter going forward.
Thanks
-Amit
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^ permalink raw reply
* Re: [PATCH v1 1/9] dmaengine: Actions: get rid of bit fields from dma descriptor
From: Vinod Koul @ 2020-05-14 18:27 UTC (permalink / raw)
To: Amit Singh Tomar
Cc: andre.przywara, linux-actions, cristian.ciocaltea,
manivannan.sadhasivam, dmaengine, dan.j.williams, afaerber,
linux-arm-kernel
In-Reply-To: <1589472657-3930-2-git-send-email-amittomer25@gmail.com>
On 14-05-20, 21:40, Amit Singh Tomar wrote:
> At the moment, Driver uses bit fields to describe registers of the DMA
> descriptor structure that makes it less portable and maintainable, and
> Andre suugested(and even sketched important bits for it) to make use of
> array to describe this DMA descriptors instead. It gives the flexibility
> while extending support for other platform such as Actions S700.
>
> This commit removes the "owl_dma_lli_hw" (that includes bit-fields) and
> uses array to describe DMA descriptor.
So i see patch 1/9 and 2/9 in my inbox... where are the rest ? No cover
to detail out what the rest contains, who should merge them etc etc!
If you are sending a series to different subsystem please make a habit
to CC everyone on cover letter so that we understand details about the
series. If not dependent, just send as individual units to subsystems!
--
~Vinod
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^ permalink raw reply
* Re: [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
From: kbuild test robot @ 2020-05-14 18:09 UTC (permalink / raw)
To: Lars Povlsen, SoC Team, Arnd Bergmann, Stephen Boyd,
Linus Walleij
Cc: devicetree, kbuild-all, Steen Hegelund, linux-clk,
Microchip Linux Driver Support, linux-gpio, linux-arm-kernel,
Olof Johansson, Michael Turquette, Lars Povlsen
In-Reply-To: <20200513125532.24585-10-lars.povlsen@microchip.com>
[-- Attachment #1: Type: text/plain, Size: 1908 bytes --]
Hi Lars,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on pinctrl/devel clk/clk-next linus/master v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Lars-Povlsen/Adding-support-for-Microchip-Sparx5-SoC/20200514-163536
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/pinctrl/pinctrl-ocelot.c:28: warning: "clrsetbits" redefined
28 | #define clrsetbits(addr, clear, set) |
In file included from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/pinctrl-ocelot.c:10:
arch/powerpc/include/asm/io.h:849: note: this is the location of the previous definition
849 | #define clrsetbits(type, addr, clear, set) |
vim +/clrsetbits +28 drivers/pinctrl/pinctrl-ocelot.c
27
> 28 #define clrsetbits(addr, clear, set) \
29 writel((readl(addr) & ~(clear)) | (set), (addr))
30
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66031 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* Re: [PATCH v3] ACPI/IORT: Fix PMCG node always look for a single ID mapping.
From: Tuan Phan @ 2020-05-14 18:06 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Hanjun Guo, Robin Murphy, Neil Leeder, Tuan Phan,
Rafael J. Wysocki, linux-kernel, Shameer Kolothum, linux-acpi,
Sudeep Holla, patches, Will Deacon, linux-arm-kernel, Len Brown
In-Reply-To: <20200514092944.GA18032@e121166-lin.cambridge.arm.com>
> On May 14, 2020, at 2:29 AM, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
>
> Please update the subject:
>
> Subject: "ACPI/IORT: Fix PMCG node single ID mapping handling"
>
> On Wed, May 13, 2020 at 05:12:02PM -0700, Tuan Phan wrote:
>> PMCG node can have zero ID mapping if its overflow interrupt
>> is wire based. The code to parse PMCG node can not assume it will
>> have a single ID mapping.
>
> "An IORT PMCG node can have no ID mapping if its overflow interrupt is
> wire based therefore the code that parses the PMCG node can not assume
> the node will always have a single mapping present at index 0.
>
> Fix iort_get_id_mapping_index() by checking for an overflow interrupt
> and mapping count."
Thanks for the correction. Will update it.
>
>> Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")
>> Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>
>> Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
>> ---
>> v1 -> v2:
>> - Use pmcg node to detect wired base overflow interrupt.
>>
>> v2 -> v3:
>> - Address Hanjun and Robin's comments.
>>
>> drivers/acpi/arm64/iort.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>
> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index ed3d2d1..12bb70e 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -414,6 +414,7 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
>> static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>> {
>> struct acpi_iort_smmu_v3 *smmu;
>> + struct acpi_iort_pmcg *pmcg;
>>
>> switch (node->type) {
>> case ACPI_IORT_NODE_SMMU_V3:
>> @@ -441,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>>
>> return smmu->id_mapping_index;
>> case ACPI_IORT_NODE_PMCG:
>> + pmcg = (struct acpi_iort_pmcg *)node->node_data;
>> + if (pmcg->overflow_gsiv || node->mapping_count == 0)
>> + return -EINVAL;
>> +
>> return 0;
>> default:
>> return -EINVAL;
>> --
>> 2.7.4
>>
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^ permalink raw reply
* Re: [PATCH] coresight: etm4x: Add support to disable trace unit power up
From: Mathieu Poirier @ 2020-05-14 18:00 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Suzuki K Poulose, linux-arm-msm, coresight, linux-kernel,
Stephen Boyd, Tingwei Zhang, Leo Yan, linux-arm-kernel,
Mike Leach
In-Reply-To: <20200514105915.27516-1-saiprakash.ranjan@codeaurora.org>
Good morning Sai,
On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
> From: Tingwei Zhang <tingwei@codeaurora.org>
>
> On some Qualcomm Technologies Inc. SoCs like SC7180, there
> exists a hardware errata where the APSS (Application Processor
> SubSystem)/CPU watchdog counter is stopped when ETM register
> TRCPDCR.PU=1.
Fun stuff...
> Since the ETMs share the same power domain as
> that of respective CPU cores, they are powered on when the
> CPU core is powered on. So we can disable powering up of the
> trace unit after checking for this errata via new property
> called "qcom,tupwr-disable".
>
> Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
> ---
> .../devicetree/bindings/arm/coresight.txt | 6 ++++
> drivers/hwtracing/coresight/coresight-etm4x.c | 29 ++++++++++++-------
Please split in two patches.
> 2 files changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 846f6daae71b..d2030128fe46 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -108,6 +108,12 @@ its hardware characteristcs.
> * arm,cp14: must be present if the system accesses ETM/PTM management
> registers via co-processor 14.
>
> + * qcom,tupwr-disable: boolean. Indicates that trace unit power up can
> + be disabled on Qualcomm Technologies Inc. systems where ETMs are in
> + the same power domain as their CPU cores. This property is required
> + to identify such systems with hardware errata where the CPU watchdog
> + counter is stopped when TRCPDCR.PU=1.
> +
I think something like "qcom,skip-power-up" would be clearer.
Also, a better choice of words is that TRCPDCR.PU does not have to be set on
Qualcomm...
> * Optional property for TMC:
>
> * arm,buffer-size: size of contiguous buffer space for TMC ETR
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index fb0f5f4f3a91..6886b44f6947 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -104,6 +104,11 @@ struct etm4_enable_arg {
> int rc;
> };
>
> +static inline bool etm4_can_disable_tupwr(struct device *dev)
> +{
> + return fwnode_property_present(dev_fwnode(dev), "qcom,tupwr-disable");
> +}
> +
Please call fwnode_property_present() at initialisation time to set a new
drvdata::skip_power_up variable. From there just switch on that in
etm4_enable/disable_hw().
Thanks,
Mathieu
> static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> {
> int i, rc;
> @@ -196,12 +201,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
> writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
>
> - /*
> - * Request to keep the trace unit powered and also
> - * emulation of powerdown
> - */
> - writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
> - drvdata->base + TRCPDCR);
> + if (!etm4_can_disable_tupwr(etm_dev)) {
> + /*
> + * Request to keep the trace unit powered and also
> + * emulation of powerdown
> + */
> + writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
> + drvdata->base + TRCPDCR);
> + }
>
> /* Enable the trace unit */
> writel_relaxed(1, drvdata->base + TRCPRGCTLR);
> @@ -476,10 +483,12 @@ static void etm4_disable_hw(void *info)
>
> CS_UNLOCK(drvdata->base);
>
> - /* power can be removed from the trace unit now */
> - control = readl_relaxed(drvdata->base + TRCPDCR);
> - control &= ~TRCPDCR_PU;
> - writel_relaxed(control, drvdata->base + TRCPDCR);
> + if (!etm4_can_disable_tupwr(etm_dev)) {
> + /* power can be removed from the trace unit now */
> + control = readl_relaxed(drvdata->base + TRCPDCR);
> + control &= ~TRCPDCR_PU;
> + writel_relaxed(control, drvdata->base + TRCPDCR);
> + }
>
> control = readl_relaxed(drvdata->base + TRCPRGCTLR);
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
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^ permalink raw reply
* Re: [PATCH v4 7/7] drm/mediatek: mtk_dsi: Create connector for bridges
From: Enric Balletbo i Serra @ 2020-05-14 17:35 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Nicolas Boichat, Daniel Vetter, Enric Balletbo Serra,
linux-kernel, dri-devel, David Airlie,
moderated list:ARM/Mediatek SoC support, Laurent Pinchart,
Philipp Zabel, Hsin-Yi Wang, Matthias Brugger,
Collabora Kernel ML, Sam Ravnborg, Linux ARM
In-Reply-To: <37191700-5832-2931-5764-7f7fddd023b9@collabora.com>
Hi again,
On 14/5/20 19:12, Enric Balletbo i Serra wrote:
> Hi Chun-Kuang,
>
> On 14/5/20 18:44, Chun-Kuang Hu wrote:
>> Hi, Enric:
>>
>> Enric Balletbo i Serra <enric.balletbo@collabora.com> 於 2020年5月14日 週四 下午11:42寫道：
>>>
>>> Hi Chun-Kuang,
>>>
>>> On 14/5/20 16:28, Chun-Kuang Hu wrote:
>>>> Hi, Enric:
>>>>
>>>> Enric Balletbo Serra <eballetbo@gmail.com> 於 2020年5月14日 週四 上午12:41寫道：
>>>>>
>>>>> Hi Chun-Kuang,
>>>>>
>>>>> Missatge de Enric Balletbo i Serra <enric.balletbo@collabora.com> del
>>>>> dia dv., 1 de maig 2020 a les 17:25:
>>>>>>
>>>>>> Use the drm_bridge_connector helper to create a connector for pipelines
>>>>>> that use drm_bridge. This allows splitting connector operations across
>>>>>> multiple bridges when necessary, instead of having the last bridge in
>>>>>> the chain creating the connector and handling all connector operations
>>>>>> internally.
>>>>>>
>>>>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>>>>>> Acked-by: Sam Ravnborg <sam@ravnborg.org>
>>>>>
>>>>> A gentle ping on this, I think that this one is the only one that
>>>>> still needs a review in the series.
>>>>
>>>> This is what I reply in patch v3:
>>>>
>>>
>>> Sorry for missing this.
>>>
>>>> I think the panel is wrapped into next_bridge here,
>>>>
>>>
>>> Yes, you can have for example:
>>>
>>> 1. drm_bridge (mtk_dsi) -> drm_bridge (ps8640 - dsi-to-edp) -> drm_panel_bridge
>>> (edp panel)
>>>
>>> or a
>>>
>>> 2. drm_bridge (mtk_dsi)-> drm_panel_bridge (dsi panel)
>>>
>>> The _first_ one is my use case
>>>
>>>> if (panel) {
>>>
>>> This handles the second case, where you attach a dsi panel.
>>>
>>>> dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
>>>>
>>>> so the next_bridge is a panel_bridge, in its attach function
>>>> panel_bridge_attach(),
>>>> according to the flag DRM_BRIDGE_ATTACH_NO_CONNECTOR, if not exist,
>>>> it would create connector and attach connector to panel.
>>>>
>>>> I'm not sure this flag would exist or not, but for both case, it's strange.
>>>> If exist, you create connector in this patch but no where to attach
>>>> connector to panel.
>>>
>>> Yes, in fact, this is transitional patch needed, as once I converted mtk_dpi,
>>> mtk_dsi and mtk_hdmi to the new drm_bridge API the drm_bridge_connector_init()
>>> will be done in mtk_drm_drv. We will need to call drm_bridge_connector_init for
>>> dpi and dsi pipes and remove that call from mtk_dsi and mtk_dpi drivers. The
>>> graphic controller driver should create connectors and CRTCs, as example you can
>>> take a look at drivers/gpu/drm/omapdrm/omap_drv.c
>>>
>>
>> I have such question because I've reviewed omap's driver. In omap's
>> driver, after it call drm_bridge_connector_init(), it does this:
>>
>> if (pipe->output->panel) {
>> ret = drm_panel_attach(pipe->output->panel,
>> pipe->connector);
>> if (ret < 0)
>> return ret;
>> }
>>
>> In this patch, you does not do this.
>>
>
> I see, so yes, I am probably missing call drm_panel_attach in case there is a
> direct panel attached. Thanks for pointing it.
>
> I'll send a new version adding the drm_panel_attach call.
>
Wait, shouldn't panel be attached on the call of mtk_dsi_bridge_attach as
next_bridge points to a bridge or a panel?
static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
/* Attach the panel or bridge to the dsi bridge */
return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
&dsi->bridge, flags);
}
Or I am continuing misunderstanding all this?
>>>> If not exist, the next_brige would create one connector and this brige
>>>> would create another connector.
>>>>
>>>> I think in your case, mtk_dsi does not directly connect to a panel, so
>>>
>>> Exactly
>>>
>>>> I need a exact explain. Or someone could test this on a
>>>> directly-connect-panel platform.
>>>
>>> I don't think I am breaking this use case but AFAICS there is no users in
>>> mainline that directly connect a panel using the mediatek driver. As I said my
>>> use case is the other so I can't really test. Do you know anyone that can test this?
>>
>> I'm not sure who can test this, but [1], which is sent by YT Shen in a
>> series, is a patch to support dsi command mode so dsi could directly
>> connect to panel.
>>
>> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.7-rc5&id=21898816831fc60c92dd634ab4316a24da7eb4af
>>
>> It's better that someone could test this case, but if no one would
>> test this, I could also accept a good-look patch.
>>
>> Regards,
>> Chun-Kuang.
>>
>>>
>>> Thanks,
>>> Enric
>>>
>>>>
>>>> Regards,
>>>> Chun-Kuang.
>>>>
>>>>>
>>>>> Thanks,
>>>>> Enric
>>>>>
>>>>>> ---
>>>>>>
>>>>>> Changes in v4: None
>>>>>> Changes in v3:
>>>>>> - Move the bridge.type line to the patch that adds drm_bridge support. (Laurent Pinchart)
>>>>>>
>>>>>> Changes in v2: None
>>>>>>
>>>>>> drivers/gpu/drm/mediatek/mtk_dsi.c | 13 ++++++++++++-
>>>>>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>>>>> index 4f3bd095c1ee..471fcafdf348 100644
>>>>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>>>>> @@ -17,6 +17,7 @@
>>>>>>
>>>>>> #include <drm/drm_atomic_helper.h>
>>>>>> #include <drm/drm_bridge.h>
>>>>>> +#include <drm/drm_bridge_connector.h>
>>>>>> #include <drm/drm_mipi_dsi.h>
>>>>>> #include <drm/drm_of.h>
>>>>>> #include <drm/drm_panel.h>
>>>>>> @@ -183,6 +184,7 @@ struct mtk_dsi {
>>>>>> struct drm_encoder encoder;
>>>>>> struct drm_bridge bridge;
>>>>>> struct drm_bridge *next_bridge;
>>>>>> + struct drm_connector *connector;
>>>>>> struct phy *phy;
>>>>>>
>>>>>> void __iomem *regs;
>>>>>> @@ -977,10 +979,19 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
>>>>>> */
>>>>>> dsi->encoder.possible_crtcs = 1;
>>>>>>
>>>>>> - ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, 0);
>>>>>> + ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
>>>>>> + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
>>>>>> if (ret)
>>>>>> goto err_cleanup_encoder;
>>>>>>
>>>>>> + dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
>>>>>> + if (IS_ERR(dsi->connector)) {
>>>>>> + DRM_ERROR("Unable to create bridge connector\n");
>>>>>> + ret = PTR_ERR(dsi->connector);
>>>>>> + goto err_cleanup_encoder;
>>>>>> + }
>>>>>> + drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
>>>>>> +
>>>>>> return 0;
>>>>>>
>>>>>> err_cleanup_encoder:
>>>>>> --
>>>>>> 2.26.2
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> Linux-mediatek mailing list
>>>>>> Linux-mediatek@lists.infradead.org
>>>>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
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^ permalink raw reply
* Re: [PATCH] cpuidle: psci: Fixup execution order when entering a domain idle state
From: Sudeep Holla @ 2020-05-14 17:28 UTC (permalink / raw)
To: Ulf Hansson
Cc: Lorenzo Pieralisi, Benjamin Gaignard, Linux PM, Stephen Boyd,
Daniel Lezcano, Rafael J . Wysocki, Lina Iyer, Bjorn Andersson,
Sudeep Holla, Linux ARM
In-Reply-To: <CAPDyKFoVo8L7eiGdEVNYR2DY7cszDuLkmX8O_SfyUKh73pbpMQ@mail.gmail.com>
On Thu, May 14, 2020 at 05:41:37PM +0200, Ulf Hansson wrote:
> On Thu, 14 May 2020 at 16:20, Sudeep Holla <sudeep.holla@arm.com> wrote:
> >
> > On Mon, May 11, 2020 at 03:33:46PM +0200, Ulf Hansson wrote:
> > > Moving forward, platforms are going to need to execute specific "last-man"
> > > operations before a domain idle state can be entered.
> >
> > I need to dig the thread details, but I remember commenting on one of
> > the similar discussion. It was something to do with voting which wasn't
> > necessary at all. I am interested in the details here.
> >
> > > In one way or the other, these operations needs to be triggered while
> > > walking the hierarchical topology via runtime PM and genpd, as it's at that
> > > point the last-man becomes known.
> > >
> > > Moreover, executing last-man operations needs to be done after the CPU PM
> > > notifications are sent through cpu_pm_enter(), as otherwise it's likely
> > > that some notifications would fail. Therefore, let's re-order the sequence
> > > in psci_enter_domain_idle_state(), so cpu_pm_enter() gets called prior
> > > pm_runtime_put_sync().
> > >
> >
> > More details on why notifications fail ?
>
> Well, at this moment this is more of a hypothetical issue as there is
> no last-man notification sent/used yet.
>
Ah OK.
> However, typically we would call cpu_cluster_pm_enter() in the path as
> when the psci_pd_power_off() is called (for psci PM domains), when a
> valid domain state has been found.
>
Please don't use cpu_cluster_pm_enter. I thought the whole idea of genpd
will remove the notion of cluster and we will never need to use
cpu_cluster_pm_*
> This means, we would violate the cpu_cluster_pm_enter() API, as it's
> clearly stated in its corresponding function header, that
> cpu_pm_enter() needs to be called first (and that's also how others
> are currently using it).
>
Ah so, it was just for use of cpu_cluster_pm_* which I would like to
avoid. That was one of the motivation for using genpd I thought.
> Note that, I am currently exploring whether we shall call
> cpu_cluster_pm_enter|exit() at all, or whether we can use some other
> new genpd mechanism to accomplish the similar thing.
>
Good, you do think so.
> >
> > > Fixes: ce85aef570df ("cpuidle: psci: Manage runtime PM in the idle path")
> > > Reported-by: Lina Iyer <ilina@codeaurora.org>
> > > Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> > > ---
> > > drivers/cpuidle/cpuidle-psci.c | 8 +++++++-
> > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c
> > > index bae9140a65a5..d0fb585073c6 100644
> > > --- a/drivers/cpuidle/cpuidle-psci.c
> > > +++ b/drivers/cpuidle/cpuidle-psci.c
> > > @@ -58,6 +58,10 @@ static int psci_enter_domain_idle_state(struct cpuidle_device *dev,
> > > u32 state;
> > > int ret;
> > >
> > > + ret = cpu_pm_enter();
> > > + if (ret)
> > > + return -1;
> > > +
> >
> > This change is ignoring the retention case psci_enter_state handles and
> > this may affect performance by doing unnecessary save/restore.
>
> This was already the case before. CPU_PM_CPU_IDLE_ENTER_PARAM() ends
> up always setting "is_retention" to 0, when __CPU_PM_CPU_IDLE_ENTER()
> is called.
>
Ah OK, I recall now, sorry for the noise.
--
Regards,
Sudeep
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^ permalink raw reply
* Re: [PATCH] ARM: mm: make act_mm() respect THREAD_SIZE_ORDER
From: Ard Biesheuvel @ 2020-05-14 17:19 UTC (permalink / raw)
To: Linus Walleij; +Cc: Florian Fainelli, Russell King, Linux ARM
In-Reply-To: <20200514135737.309146-1-linus.walleij@linaro.org>
On Thu, 14 May 2020 at 15:59, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> Recent work with KASan exposed the folling hard-coded bitmask
> in arch/arm/mm/proc-macros.S:
>
> bic \rd, sp, #8128
> bic \rd, \rd, #63
>
> This forms the bitmask 0x1FFF that is coinciding with
> (PAGE_SIZE << THREAD_SIZE_ORDER) - 1, this code was assuming
> that THREAD_SIZE is always 8K (8192).
>
> As KASan was increasing THREAD_SIZE_ORDER to 2, I ran into
> this bug.
>
> Fix it by this little oneline suggested by Ard:
>
> bic \rd, sp, #(4095 << THREAD_SIZE_ORDER) & ~63
>
Perhaps
(THREAD_SIZE - 1) & ~63
is a bit cleaner here?
> Cc: Ard Biesheuvel <ardb@kernel.org>
> Cc: Florian Fainelli <f.fainelli@gmail.com>
> Suggested-by: Ard Biesheuvel <ardb@kernel.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> I'm sending this as a separate preparatory fix as it is
> a nice fix in its own right. I am now testing KASan on
> ARMv4 and ARMv5 and with some minimal busybox userspace
> it is quite possible to run it on even really small
> devices like the Gemini-based routers and NAS from
> D-Link.
> ---
> arch/arm/mm/proc-macros.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
> index 5461d589a1e2..ba100b2d0ac2 100644
> --- a/arch/arm/mm/proc-macros.S
> +++ b/arch/arm/mm/proc-macros.S
> @@ -30,7 +30,7 @@
> * act_mm - get current->active_mm
> */
> .macro act_mm, rd
> - bic \rd, sp, #8128
> + bic \rd, sp, #(4095 << THREAD_SIZE_ORDER) & ~63
> bic \rd, \rd, #63
> ldr \rd, [\rd, #TI_TASK]
> .if (TSK_ACTIVE_MM > IMM12_MASK)
> --
> 2.25.4
>
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^ permalink raw reply
* [PATCH v5 21/21] mtd: nand: Rename a core structure
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Prepare the migration to a generic ECC engine by renaming the
nand_ecc_req structure into nand_ecc_props. This structure will be the
base of a wider 'nand_ecc' structure.
In nand_device, these properties are still named "eccreq" even if
"eccprops" might be more descriptive. This is just a transition step,
this field is being replaced very soon by a much wider structure. The
impact of renaming this field would be huge compared to its interest.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
include/linux/mtd/nand.h | 8 ++++----
include/linux/mtd/spinand.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 60d158e183ce..6add464fd18b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -128,11 +128,11 @@ struct nand_page_io_req {
};
/**
- * struct nand_ecc_req - NAND ECC requirements
+ * struct nand_ecc_props - NAND ECC properties
* @strength: ECC strength
- * @step_size: ECC step/block size
+ * @step_size: Number of bytes per step
*/
-struct nand_ecc_req {
+struct nand_ecc_props {
unsigned int strength;
unsigned int step_size;
};
@@ -191,7 +191,7 @@ struct nand_ops {
struct nand_device {
struct mtd_info mtd;
struct nand_memory_organization memorg;
- struct nand_ecc_req eccreq;
+ struct nand_ecc_props eccreq;
struct nand_row_converter rowconv;
struct nand_bbt bbt;
const struct nand_ops *ops;
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 1077c45721ff..7b78c4ba9b3e 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -309,7 +309,7 @@ struct spinand_info {
struct spinand_devid devid;
u32 flags;
struct nand_memory_organization memorg;
- struct nand_ecc_req eccreq;
+ struct nand_ecc_props eccreq;
struct spinand_ecc_info eccinfo;
struct {
const struct spinand_op_variants *read_cache;
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 20/21] mtd: nand: Add a NAND page I/O request type
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Use an enum to differentiate the type of I/O (reading or writing a
page). Also update the request iterator.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/spi/core.c | 4 ++--
include/linux/mtd/nand.h | 18 ++++++++++++++++--
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 6ea16c6ed27f..48e822a384ff 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -497,7 +497,7 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
mutex_lock(&spinand->lock);
- nanddev_io_for_each_page(nand, from, ops, &iter) {
+ nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) {
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
@@ -545,7 +545,7 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
mutex_lock(&spinand->lock);
- nanddev_io_for_each_page(nand, to, ops, &iter) {
+ nanddev_io_for_each_page(nand, NAND_PAGE_WRITE, to, ops, &iter) {
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a1f38c778d0e..60d158e183ce 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -82,8 +82,19 @@ struct nand_pos {
unsigned int page;
};
+/**
+ * enum nand_page_io_req_type - Direction of an I/O request
+ * @NAND_PAGE_READ: from the chip, to the controller
+ * @NAND_PAGE_WRITE: from the controller, to the chip
+ */
+enum nand_page_io_req_type {
+ NAND_PAGE_READ = 0,
+ NAND_PAGE_WRITE,
+};
+
/**
* struct nand_page_io_req - NAND I/O request object
+ * @type: the type of page I/O: read or write
* @pos: the position this I/O request is targeting
* @dataoffs: the offset within the page
* @datalen: number of data bytes to read from/write to this page
@@ -99,6 +110,7 @@ struct nand_pos {
* specific commands/operations.
*/
struct nand_page_io_req {
+ enum nand_page_io_req_type type;
struct nand_pos pos;
unsigned int dataoffs;
unsigned int datalen;
@@ -624,11 +636,13 @@ static inline void nanddev_pos_next_page(struct nand_device *nand,
* layer.
*/
static inline void nanddev_io_iter_init(struct nand_device *nand,
+ enum nand_page_io_req_type reqtype,
loff_t offs, struct mtd_oob_ops *req,
struct nand_io_iter *iter)
{
struct mtd_info *mtd = nanddev_to_mtd(nand);
+ iter->req.type = reqtype;
iter->req.mode = req->mode;
iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos);
iter->req.ooboffs = req->ooboffs;
@@ -698,8 +712,8 @@ static inline bool nanddev_io_iter_end(struct nand_device *nand,
*
* Should be used for iterate over pages that are contained in an MTD request.
*/
-#define nanddev_io_for_each_page(nand, start, req, iter) \
- for (nanddev_io_iter_init(nand, start, req, iter); \
+#define nanddev_io_for_each_page(nand, type, start, req, iter) \
+ for (nanddev_io_iter_init(nand, type, start, req, iter); \
!nanddev_io_iter_end(nand, iter); \
nanddev_io_iter_next_page(nand, iter))
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 17/21] mtd: nand: Move nand_device forward declaration to the top
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
This structure might be used earlier in this file, let's move the
forward declaration at the top.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
include/linux/mtd/nand.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 0c7483843a32..a1f38c778d0e 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -12,6 +12,8 @@
#include <linux/mtd/mtd.h>
+struct nand_device;
+
/**
* struct nand_memory_organization - Memory organization structure
* @bits_per_cell: number of bits per NAND cell
@@ -133,8 +135,6 @@ struct nand_bbt {
unsigned long *cache;
};
-struct nand_device;
-
/**
* struct nand_ops - NAND operations
* @erase: erase a specific block. No need to check if the block is bad before
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 19/21] mtd: nand: Drop useless 'depends on' in Kconfig
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Both OneNAND and raw NAND bits can't be compiled if MTD is disabled
because of the if/endif logic in drivers/mtd/Kconfig. There is no need
for an extra "depends on MTD" in their respective Kconfig files.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/onenand/Kconfig | 1 -
drivers/mtd/nand/raw/Kconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/mtd/nand/onenand/Kconfig b/drivers/mtd/nand/onenand/Kconfig
index 572b8fe69abb..1a0e65bc246e 100644
--- a/drivers/mtd/nand/onenand/Kconfig
+++ b/drivers/mtd/nand/onenand/Kconfig
@@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig MTD_ONENAND
tristate "OneNAND Device Support"
- depends on MTD
depends on HAS_IOMEM
help
This enables support for accessing all type of OneNAND flash
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index a80a46bb5b8b..eb7c2973f940 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -12,7 +12,6 @@ config MTD_NAND_ECC_SW_HAMMING_SMC
menuconfig MTD_RAW_NAND
tristate "Raw/Parallel NAND Device Support"
- depends on MTD
select MTD_NAND_CORE
select MTD_NAND_ECC_SW_HAMMING
help
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 18/21] mtd: nand: Add an extra level in the Kconfig hierarchy
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Use an extra level in Kconfig for all NAND related entries.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a5d8a211cb8a..c1a45b071165 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -1,7 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
+
+menu "NAND"
+
config MTD_NAND_CORE
tristate
source "drivers/mtd/nand/onenand/Kconfig"
source "drivers/mtd/nand/raw/Kconfig"
source "drivers/mtd/nand/spi/Kconfig"
+
+endmenu
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 16/21] dt-bindings: mtd: Deprecate the nand-ecc-mode property
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
This property does not describe very well its purpose: it describes
the ECC engine type, also called provider. Deprecate it in favor of
nand-ecc-provider. In the mean time, update a bit the description of
the property to make it more accurate.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../devicetree/bindings/mtd/nand-controller.yaml | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index a35ff8227427..256080ba50bd 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -46,16 +46,17 @@ patternProperties:
description:
Contains the native Ready/Busy IDs.
- nand-ecc-mode:
+ nand-ecc-provider:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ none, soft, hw, on-die ]
description:
- Desired ECC engine, either hardware (most of the time
- embedded in the NAND controller) or software correction
- (Linux will handle the calculations). soft_bch is deprecated
- and should be replaced by soft and nand-ecc-algo.
- hw_syndrome is deprecated and should be
+ Desired ECC engine provider, either hardware (most of the time
+ embedded in the NAND controller, but can also be external) or
+ software correction (the OS will handle the calculations).
+ The nand-ecc-mode property is deprecated in favor of this one.
+ soft_bch is deprecated and should be replaced by soft and
+ nand-ecc-algo. hw_syndrome is deprecated and should be
replaced by hw and nand-ecc-placement.
nand-ecc-placement:
@@ -148,7 +149,7 @@ examples:
nand@0 {
reg = <0>;
- nand-ecc-mode = "soft";
+ nand-ecc-provider = "soft";
nand-ecc-algo = "bch";
/* controller specific properties */
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 15/21] dt-bindings: mtd: Deprecate hw_syndrome from the ECC modes
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
This mode should not be used anymore, it is actually a mix between a
mode and a placement.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index 35512f2c66fa..a35ff8227427 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -49,12 +49,14 @@ patternProperties:
nand-ecc-mode:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- - enum: [ none, soft, hw, hw_syndrome, on-die ]
+ - enum: [ none, soft, hw, on-die ]
description:
Desired ECC engine, either hardware (most of the time
embedded in the NAND controller) or software correction
(Linux will handle the calculations). soft_bch is deprecated
and should be replaced by soft and nand-ecc-algo.
+ hw_syndrome is deprecated and should be
+ replaced by hw and nand-ecc-placement.
nand-ecc-placement:
allOf:
--
2.20.1
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* [PATCH v5 11/21] mtd: rawnand: Use the new ECC engine type enumeration
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Mechanical switch from the legacy enumeration to the new enumeration in
drivers and board files.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 2 +-
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +-
arch/arm/mach-s3c24xx/common-smdk.c | 2 +-
arch/arm/mach-s3c24xx/mach-anubis.c | 2 +-
arch/arm/mach-s3c24xx/mach-at2440evb.c | 2 +-
arch/arm/mach-s3c24xx/mach-bast.c | 2 +-
arch/arm/mach-s3c24xx/mach-gta02.c | 2 +-
arch/arm/mach-s3c24xx/mach-jive.c | 2 +-
arch/arm/mach-s3c24xx/mach-mini2440.c | 2 +-
arch/arm/mach-s3c24xx/mach-osiris.c | 2 +-
arch/arm/mach-s3c24xx/mach-qt2410.c | 2 +-
arch/arm/mach-s3c24xx/mach-rx1950.c | 2 +-
arch/arm/mach-s3c24xx/mach-rx3715.c | 2 +-
arch/arm/mach-s3c24xx/mach-vstms.c | 2 +-
arch/arm/mach-s3c64xx/mach-hmt.c | 2 +-
arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-real6410.c | 2 +-
drivers/mtd/nand/raw/ams-delta.c | 2 +-
drivers/mtd/nand/raw/atmel/nand-controller.c | 14 ++--
drivers/mtd/nand/raw/au1550nd.c | 2 +-
.../mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 3 +-
drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 +--
.../mtd/nand/raw/cadence-nand-controller.c | 4 +-
drivers/mtd/nand/raw/cafe_nand.c | 2 +-
drivers/mtd/nand/raw/cmx270_nand.c | 2 +-
drivers/mtd/nand/raw/cs553x_nand.c | 2 +-
drivers/mtd/nand/raw/davinci_nand.c | 22 +++---
drivers/mtd/nand/raw/denali.c | 2 +-
drivers/mtd/nand/raw/diskonchip.c | 2 +-
drivers/mtd/nand/raw/fsl_elbc_nand.c | 18 ++---
drivers/mtd/nand/raw/fsl_ifc_nand.c | 10 +--
drivers/mtd/nand/raw/fsl_upm.c | 2 +-
drivers/mtd/nand/raw/fsmc_nand.c | 12 ++--
drivers/mtd/nand/raw/gpio.c | 2 +-
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 2 +-
drivers/mtd/nand/raw/hisi504_nand.c | 6 +-
.../mtd/nand/raw/ingenic/ingenic_nand_drv.c | 14 ++--
drivers/mtd/nand/raw/lpc32xx_mlc.c | 2 +-
drivers/mtd/nand/raw/lpc32xx_slc.c | 2 +-
drivers/mtd/nand/raw/marvell_nand.c | 17 ++---
drivers/mtd/nand/raw/meson_nand.c | 2 +-
drivers/mtd/nand/raw/mpc5121_nfc.c | 2 +-
drivers/mtd/nand/raw/mtk_nand.c | 6 +-
drivers/mtd/nand/raw/mxc_nand.c | 23 ++++---
drivers/mtd/nand/raw/nand_base.c | 68 +++++++++++--------
drivers/mtd/nand/raw/nand_micron.c | 4 +-
drivers/mtd/nand/raw/nand_toshiba.c | 3 +-
drivers/mtd/nand/raw/nandsim.c | 4 +-
drivers/mtd/nand/raw/ndfc.c | 2 +-
drivers/mtd/nand/raw/omap2.c | 20 +++---
drivers/mtd/nand/raw/orion_nand.c | 2 +-
drivers/mtd/nand/raw/pasemi_nand.c | 2 +-
drivers/mtd/nand/raw/plat_nand.c | 2 +-
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
drivers/mtd/nand/raw/r852.c | 2 +-
drivers/mtd/nand/raw/s3c2410.c | 16 ++---
drivers/mtd/nand/raw/sh_flctl.c | 4 +-
drivers/mtd/nand/raw/sharpsl.c | 2 +-
drivers/mtd/nand/raw/socrates_nand.c | 3 +-
drivers/mtd/nand/raw/stm32_fmc2_nand.c | 9 +--
drivers/mtd/nand/raw/sunxi_nand.c | 18 ++---
drivers/mtd/nand/raw/tango_nand.c | 2 +-
drivers/mtd/nand/raw/tegra_nand.c | 2 +-
drivers/mtd/nand/raw/tmio_nand.c | 2 +-
drivers/mtd/nand/raw/txx9ndfmc.c | 2 +-
drivers/mtd/nand/raw/vf610_nfc.c | 4 +-
drivers/mtd/nand/raw/xway_nand.c | 2 +-
include/linux/mtd/rawnand.h | 4 +-
include/linux/platform_data/mtd-davinci.h | 10 +--
.../linux/platform_data/mtd-nand-s3c2410.h | 2 +-
78 files changed, 222 insertions(+), 206 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index a273ab25c668..ce2b212d4834 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -306,7 +306,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
.core_chipsel = 1,
.parts = da830_evm_nand_partitions,
.nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.bbt_td = &da830_evm_nand_bbt_main_descr,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 5b3549f1236c..fbf0eb33e988 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -239,7 +239,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
.core_chipsel = 1,
.parts = da850_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.timing = &da850_evm_nandflash_timing,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 5113273fda69..6548a8c79a93 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -82,7 +82,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 4,
};
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 4c8a592754ac..6d1e02c80d24 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -76,7 +76,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_HW_ECC_ENGINE,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 2328b15ac067..aebf0b4a4a88 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -146,7 +146,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 4,
};
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 3461d12bbfc0..2b1a2621f55e 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -162,7 +162,7 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
.timing = &davinci_evm_nandflash_timing,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 4600b617f9b4..f600082baa12 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -91,7 +91,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
.mask_ale = 0x40000,
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 1,
.options = 0,
};
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index dfce421c0579..ecad01d62c56 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -432,7 +432,7 @@ static struct davinci_nand_pdata mityomapl138_nandflash_data = {
.core_chipsel = 1,
.parts = mityomapl138_nandflash_partition,
.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.bbt_options = NAND_BBT_USE_FLASH,
.options = NAND_BUSWIDTH_16,
.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index ce99f782811a..a21099fbe414 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -90,7 +90,7 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_ntosd2_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
};
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 5390a8630cf0..0c7fb78995a6 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -206,7 +206,7 @@ static struct davinci_nand_pdata omapl138_hawk_nandflash_data = {
.core_chipsel = 1,
.parts = omapl138_hawk_nandflash_partition,
.nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.options = NAND_BUSWIDTH_16,
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 58e30cad386c..6aa598d5191b 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -166,7 +166,7 @@ static struct s3c2410_platform_nand smdk_nand_info = {
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(smdk_nand_sets),
.sets = smdk_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* devices we initialise */
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 072966dcad78..60de8f86e66a 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -218,7 +218,7 @@ static struct s3c2410_platform_nand __initdata anubis_nand_info = {
.nr_sets = ARRAY_SIZE(anubis_nand_sets),
.sets = anubis_nand_sets,
.select_chip = anubis_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* IDE channels */
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 58c5ef3cf1d7..1d52a29f373a 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -109,7 +109,7 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
.sets = at2440evb_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* DM9000AEP 10/100 ethernet controller */
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index a7c3955ae8f6..f8deca7e1d41 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -294,7 +294,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
.nr_sets = ARRAY_SIZE(bast_nand_sets),
.sets = bast_nand_sets,
.select_chip = bast_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* DM9000 */
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 594901f3b8e5..d7ee1043b96a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -416,7 +416,7 @@ static struct s3c2410_platform_nand __initdata gta02_nand_info = {
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(gta02_nand_sets),
.sets = gta02_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 885e8f12e4b9..ac2b98bc2d82 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -228,7 +228,7 @@ static struct s3c2410_platform_nand __initdata jive_nand_info = {
.twrph1 = 40,
.sets = jive_nand_sets,
.nr_sets = ARRAY_SIZE(jive_nand_sets),
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static int __init jive_mtdset(char *options)
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 9035f868fb34..1fbeab0dffa5 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -296,7 +296,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
.sets = mini2440_nand_sets,
.ignore_unset_ecc = 1,
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_CONTROLLER,
};
/* DM9000AEP 10/100 ethernet controller */
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ee3630cb236a..c241256843a5 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -234,7 +234,7 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = {
.nr_sets = ARRAY_SIZE(osiris_nand_sets),
.sets = osiris_nand_sets,
.select_chip = osiris_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* PCMCIA control and configuration */
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 5d48e5b6e738..ae986d0973c2 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -281,7 +281,7 @@ static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
.sets = qt2410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
/* UDC */
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index fde98b175c75..3acd2eacfd30 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -620,7 +620,7 @@ static struct s3c2410_platform_nand rx1950_nand_info = {
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
.sets = rx1950_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 529c6faf862f..e17f067e6e66 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -158,7 +158,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
.sets = rx3715_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct platform_device *rx3715_devices[] __initdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index d76b28b65e65..3950afb70e82 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -112,7 +112,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = {
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(vstms_nand_sets),
.sets = vstms_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct platform_device *vstms_devices[] __initdata = {
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index e7080215c624..c1b9af42535a 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -199,7 +199,7 @@ static struct s3c2410_platform_nand hmt_nand_info = {
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(hmt_nand_sets),
.sets = hmt_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct gpio_led hmt_leds[] = {
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 0dd36ae49e6a..4ddfa97a418e 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -136,7 +136,7 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
.sets = mini6410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 0ff88b6859c4..db7c6edd7551 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -188,7 +188,7 @@ static struct s3c2410_platform_nand real6410_nand_info = {
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(real6410_nand_sets),
.sets = real6410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_SOFT,
};
static struct platform_device *real6410_devices[] __initdata = {
diff --git a/drivers/mtd/nand/raw/ams-delta.c b/drivers/mtd/nand/raw/ams-delta.c
index d66dab25df20..b83b600825e2 100644
--- a/drivers/mtd/nand/raw/ams-delta.c
+++ b/drivers/mtd/nand/raw/ams-delta.c
@@ -260,7 +260,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
return err;
}
- this->ecc.mode = NAND_ECC_SOFT;
+ this->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
this->ecc.algo = NAND_ECC_HAMMING;
platform_set_drvdata(pdev, priv);
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 46a3724a788e..cbe9ced0810b 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1118,15 +1118,15 @@ static int atmel_nand_ecc_init(struct nand_chip *chip)
nc = to_nand_controller(chip->controller);
- switch (chip->ecc.mode) {
- case NAND_ECC_NONE:
- case NAND_ECC_SOFT:
+ switch (chip->ecc.engine_type) {
+ case NAND_ECC_ENGINE_NONE:
+ case NAND_ECC_ENGINE_SOFT:
/*
* Nothing to do, the core will initialize everything for us.
*/
break;
- case NAND_ECC_HW:
+ case NAND_ECC_ENGINE_CONTROLLER:
ret = atmel_nand_pmecc_init(chip);
if (ret)
return ret;
@@ -1140,7 +1140,7 @@ static int atmel_nand_ecc_init(struct nand_chip *chip)
default:
/* Other modes are not supported. */
dev_err(nc->dev, "Unsupported ECC mode: %d\n",
- chip->ecc.mode);
+ chip->ecc.engine_type);
return -ENOTSUPP;
}
@@ -1155,7 +1155,7 @@ static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
if (ret)
return ret;
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return 0;
/* Adjust the ECC operations for the HSMC IP. */
@@ -1498,7 +1498,7 @@ static void atmel_nand_init(struct atmel_nand_controller *nc,
/* Default to HW ECC if pmecc is available. */
if (nc->pmecc)
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
}
static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
diff --git a/drivers/mtd/nand/raw/au1550nd.c b/drivers/mtd/nand/raw/au1550nd.c
index 2ac84cb0501d..6ca3e905a0b6 100644
--- a/drivers/mtd/nand/raw/au1550nd.c
+++ b/drivers/mtd/nand/raw/au1550nd.c
@@ -294,7 +294,7 @@ static int au1550nd_probe(struct platform_device *pdev)
nand_controller_init(&ctx->controller);
ctx->controller.ops = &au1550nd_ops;
this->controller = &ctx->controller;
- this->ecc.mode = NAND_ECC_SOFT;
+ this->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
this->ecc.algo = NAND_ECC_HAMMING;
if (pd->devwidth)
diff --git a/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c
index 591775173034..2a284f1d29b8 100644
--- a/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c
@@ -391,7 +391,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
nand_chip->legacy.chip_delay = 50;
b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
- b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
+ /* TODO: implement ECC */
+ b47n->nand_chip.ecc.engine_type = NAND_ECC_ENGINE_NONE;
/* Enable NAND flash access */
bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index fe7cd3aa0cd6..bd4fb55ce71c 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -2470,9 +2470,9 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
cfg->col_adr_bytes = 2;
cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
- if (chip->ecc.mode != NAND_ECC_HW) {
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER) {
dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",
- chip->ecc.mode);
+ chip->ecc.engine_type);
return -EINVAL;
}
@@ -2492,7 +2492,7 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
return -EINVAL;
}
- if (chip->ecc.mode != NAND_ECC_NONE &&
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_NONE &&
(!chip->ecc.size || !chip->ecc.strength)) {
if (chip->base.eccreq.step_size && chip->base.eccreq.strength) {
/* use detected ECC parameters */
@@ -2633,7 +2633,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
chip->legacy.read_buf = brcmnand_read_buf;
chip->legacy.write_buf = brcmnand_write_buf;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.read_page = brcmnand_read_page;
chip->ecc.write_page = brcmnand_write_page;
chip->ecc.read_page_raw = brcmnand_read_page_raw;
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c
index e7abb15c7253..ec2fd9100cef 100644
--- a/drivers/mtd/nand/raw/cadence-nand-controller.c
+++ b/drivers/mtd/nand/raw/cadence-nand-controller.c
@@ -2610,7 +2610,7 @@ static int cadence_nand_attach_chip(struct nand_chip *chip)
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->options |= NAND_NO_SUBPAGE_WRITE;
@@ -2756,7 +2756,7 @@ static int cadence_nand_chip_init(struct cdns_nand_ctrl *cdns_ctrl,
* Default to HW ECC engine mode. If the nand-ecc-mode property is given
* in the DT node, this entry will be overwritten in nand_scan_ident().
*/
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
ret = nand_scan(chip, cdns_chip->nsels);
if (ret) {
diff --git a/drivers/mtd/nand/raw/cafe_nand.c b/drivers/mtd/nand/raw/cafe_nand.c
index 6afafc8bda2a..2f56a9383282 100644
--- a/drivers/mtd/nand/raw/cafe_nand.c
+++ b/drivers/mtd/nand/raw/cafe_nand.c
@@ -629,7 +629,7 @@ static int cafe_nand_attach_chip(struct nand_chip *chip)
goto out_free_dma;
}
- cafe->nand.ecc.mode = NAND_ECC_HW;
+ cafe->nand.ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
cafe->nand.ecc.size = mtd->writesize;
cafe->nand.ecc.bytes = 14;
diff --git a/drivers/mtd/nand/raw/cmx270_nand.c b/drivers/mtd/nand/raw/cmx270_nand.c
index 045b6175ae79..cabc7e5d4b31 100644
--- a/drivers/mtd/nand/raw/cmx270_nand.c
+++ b/drivers/mtd/nand/raw/cmx270_nand.c
@@ -176,7 +176,7 @@ static int __init cmx270_init(void)
/* 15 us command delay time */
this->legacy.chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
+ this->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
this->ecc.algo = NAND_ECC_HAMMING;
/* read/write functions */
diff --git a/drivers/mtd/nand/raw/cs553x_nand.c b/drivers/mtd/nand/raw/cs553x_nand.c
index df5e24a2bbd7..4badeb99048f 100644
--- a/drivers/mtd/nand/raw/cs553x_nand.c
+++ b/drivers/mtd/nand/raw/cs553x_nand.c
@@ -286,7 +286,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
goto out_mtd;
}
- this->ecc.mode = NAND_ECC_HW;
+ this->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
this->ecc.size = 256;
this->ecc.bytes = 3;
this->ecc.hwctl = cs_enable_hwecc;
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 9ac1636fb9ae..3e4c9f6294f3 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -613,11 +613,11 @@ static struct davinci_nand_pdata
if (!of_property_read_string(pdev->dev.of_node,
"ti,davinci-ecc-mode", &mode)) {
if (!strncmp("none", mode, 4))
- pdata->ecc_mode = NAND_ECC_NONE;
+ pdata->engine_type = NAND_ECC_ENGINE_NONE;
if (!strncmp("soft", mode, 4))
- pdata->ecc_mode = NAND_ECC_SOFT;
+ pdata->engine_type = NAND_ECC_ENGINE_SOFT;
if (!strncmp("hw", mode, 2))
- pdata->ecc_mode = NAND_ECC_HW;
+ pdata->engine_type = NAND_ECC_ENGINE_CONTROLLER;
}
if (!of_property_read_u32(pdev->dev.of_node,
"ti,davinci-ecc-bits", &prop))
@@ -668,21 +668,21 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
if (IS_ERR(pdata))
return PTR_ERR(pdata);
- switch (info->chip.ecc.mode) {
- case NAND_ECC_NONE:
+ switch (info->chip.ecc.engine_type) {
+ case NAND_ECC_ENGINE_NONE:
pdata->ecc_bits = 0;
break;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
pdata->ecc_bits = 0;
/*
- * This driver expects Hamming based ECC when ecc_mode is set
- * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
- * avoid adding an extra ->ecc_algo field to
+ * This driver expects Hamming based ECC when engine_type is set
+ * to NAND_ECC_ENGINE_SOFT. Force ecc.algo to NAND_ECC_HAMMING
+ * to avoid adding an extra ->ecc_algo field to
* davinci_nand_pdata.
*/
info->chip.ecc.algo = NAND_ECC_HAMMING;
break;
- case NAND_ECC_HW:
+ case NAND_ECC_ENGINE_CONTROLLER:
if (pdata->ecc_bits == 4) {
int chunks = mtd->writesize / 512;
@@ -846,7 +846,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
info->chip.legacy.write_buf = nand_davinci_write_buf;
/* Use board-specific ECC config */
- info->chip.ecc.mode = pdata->ecc_mode;
+ info->chip.ecc.engine_type = pdata->engine_type;
info->chip.ecc.placement = pdata->ecc_placement;
spin_lock_irq(&davinci_nand_lock);
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index f52b59403895..6a5818c4429b 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -1237,7 +1237,7 @@ int denali_chip_init(struct denali_controller *denali,
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->ecc.read_page = denali_read_page;
chip->ecc.write_page = denali_write_page;
diff --git a/drivers/mtd/nand/raw/diskonchip.c b/drivers/mtd/nand/raw/diskonchip.c
index a836de521535..c6b64a0ff297 100644
--- a/drivers/mtd/nand/raw/diskonchip.c
+++ b/drivers/mtd/nand/raw/diskonchip.c
@@ -1456,7 +1456,7 @@ static int __init doc_probe(unsigned long physadr)
nand->ecc.calculate = doc200x_calculate_ecc;
nand->ecc.correct = doc200x_correct_data;
- nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
nand->ecc.size = 512;
nand->ecc.bytes = 6;
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index e1dc675b12bb..5b2624e32291 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -244,7 +244,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
return -EIO;
}
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return 0;
elbc_fcm_ctrl->max_bitflips = 0;
@@ -727,12 +727,12 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
unsigned int al;
- switch (chip->ecc.mode) {
+ switch (chip->ecc.engine_type) {
/*
* if ECC was not chosen in DT, decide whether to use HW or SW ECC from
* CS Base Register
*/
- case NAND_ECC_NONE:
+ case NAND_ECC_ENGINE_NONE:
/* If CS Base Register selects full hardware ECC then use it */
if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
BR_DECC_CHK_GEN) {
@@ -740,23 +740,23 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
chip->ecc.write_page = fsl_elbc_write_page;
chip->ecc.write_subpage = fsl_elbc_write_subpage;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops);
chip->ecc.size = 512;
chip->ecc.bytes = 3;
chip->ecc.strength = 1;
} else {
/* otherwise fall back to default software ECC */
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
}
break;
/* if SW ECC was chosen in DT, we do not need to set anything here */
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
break;
- /* should we also implement NAND_ECC_HW to do as the code above? */
+ /* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */
default:
return -EINVAL;
}
@@ -786,8 +786,8 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
chip->page_shift);
dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
chip->phys_erase_shift);
- dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
- chip->ecc.mode);
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.engine_type = %d\n",
+ chip->ecc.engine_type);
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
chip->ecc.steps);
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 2af09edf405b..856988fd6a70 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -309,7 +309,7 @@ static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
ifc_nand_ctrl->index += column;
- if (chip->ecc.mode == NAND_ECC_HW)
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER)
ifc_nand_ctrl->eccread = 1;
fsl_ifc_do_read(chip, 0, mtd);
@@ -724,8 +724,8 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
chip->page_shift);
dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
chip->phys_erase_shift);
- dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
- chip->ecc.mode);
+ dev_dbg(priv->dev, "%s: nand->ecc.engine_type = %d\n", __func__,
+ chip->ecc.engine_type);
dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
chip->ecc.steps);
dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
@@ -912,7 +912,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
if (csor & CSOR_NAND_ECC_DEC_EN) {
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
/* Hardware generates ECC per 512 Bytes */
@@ -925,7 +925,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
chip->ecc.strength = 8;
}
} else {
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
}
diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c
index f31fae3a4c68..d33ccb082c88 100644
--- a/drivers/mtd/nand/raw/fsl_upm.c
+++ b/drivers/mtd/nand/raw/fsl_upm.c
@@ -163,7 +163,7 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
fun->chip.legacy.read_byte = fun_read_byte;
fun->chip.legacy.read_buf = fun_read_buf;
fun->chip.legacy.write_buf = fun_write_buf;
- fun->chip.ecc.mode = NAND_ECC_SOFT;
+ fun->chip.ecc.engine_type = NAND_ECC_ENGINE_SOFT;
fun->chip.ecc.algo = NAND_ECC_HAMMING;
if (fun->mchip_count > 1)
fun->chip.legacy.select_chip = fun_select_chip;
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 2a9222e99bcc..4d3325aa40ae 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -900,8 +900,8 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
return 0;
}
- switch (nand->ecc.mode) {
- case NAND_ECC_HW:
+ switch (nand->ecc.engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
nand->ecc.calculate = fsmc_read_hwecc_ecc1;
nand->ecc.correct = nand_correct_data;
@@ -910,14 +910,14 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
break;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
if (nand->ecc.algo == NAND_ECC_BCH) {
dev_info(host->dev,
"Using 4-bit SW BCH ECC scheme\n");
break;
}
- case NAND_ECC_ON_DIE:
+ case NAND_ECC_ENGINE_ON_DIE:
break;
default:
@@ -929,7 +929,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
* Don't set layout for BCH4 SW ECC. This will be
* generated later in nand_bch_init() later.
*/
- if (nand->ecc.mode == NAND_ECC_HW) {
+ if (nand->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER) {
switch (mtd->oobsize) {
case 16:
case 64:
@@ -1059,7 +1059,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
* Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
* can overwrite this value if the DT provides a different value.
*/
- nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->ecc.size = 512;
nand->badblockbits = 7;
diff --git a/drivers/mtd/nand/raw/gpio.c b/drivers/mtd/nand/raw/gpio.c
index f6b12354024f..aab80484d782 100644
--- a/drivers/mtd/nand/raw/gpio.c
+++ b/drivers/mtd/nand/raw/gpio.c
@@ -271,7 +271,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
nand_set_flash_node(chip, pdev->dev.of_node);
chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
chip->options = gpiomtd->plat.options;
chip->legacy.chip_delay = gpiomtd->plat.chip_delay;
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
index cc4cb190968e..fe445d1d32cb 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
@@ -2184,7 +2184,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
ecc->write_page_raw = gpmi_ecc_write_page_raw;
ecc->read_oob_raw = gpmi_ecc_read_oob_raw;
ecc->write_oob_raw = gpmi_ecc_write_oob_raw;
- ecc->mode = NAND_ECC_HW;
+ ecc->engine_type = NAND_ECC_ENGINE_CONTROLLER;
ecc->size = bch_geo->ecc_chunk_size;
ecc->strength = bch_geo->ecc_strength;
mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);
diff --git a/drivers/mtd/nand/raw/hisi504_nand.c b/drivers/mtd/nand/raw/hisi504_nand.c
index 0b48be54ba6f..34ce43945a00 100644
--- a/drivers/mtd/nand/raw/hisi504_nand.c
+++ b/drivers/mtd/nand/raw/hisi504_nand.c
@@ -186,7 +186,7 @@ static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
- if (chip->ecc.mode == NAND_ECC_NONE) {
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_NONE) {
hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
<< HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
@@ -468,7 +468,7 @@ static void hisi_nfc_cmdfunc(struct nand_chip *chip, unsigned command,
case NAND_CMD_STATUS:
flag = hinfc_read(host, HINFC504_CON);
- if (chip->ecc.mode == NAND_ECC_HW)
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER)
hinfc_write(host,
flag & ~(HINFC504_CON_ECCTYPE_MASK <<
HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
@@ -721,7 +721,7 @@ static int hisi_nfc_attach_chip(struct nand_chip *chip)
}
hinfc_write(host, flag, HINFC504_CON);
- if (chip->ecc.mode == NAND_ECC_HW)
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER)
hisi_nfc_ecc_probe(host);
return 0;
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
index e7bd845fdbf5..889024bdbdec 100644
--- a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
@@ -243,8 +243,8 @@ static int ingenic_nand_attach_chip(struct nand_chip *chip)
(chip->ecc.strength / 8);
}
- switch (chip->ecc.mode) {
- case NAND_ECC_HW:
+ switch (chip->ecc.engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
if (!nfc->ecc) {
dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
return -ENODEV;
@@ -254,22 +254,22 @@ static int ingenic_nand_attach_chip(struct nand_chip *chip)
chip->ecc.calculate = ingenic_nand_ecc_calculate;
chip->ecc.correct = ingenic_nand_ecc_correct;
fallthrough;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
(nfc->ecc) ? "hardware ECC" : "software ECC",
chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
break;
- case NAND_ECC_NONE:
+ case NAND_ECC_ENGINE_NONE:
dev_info(nfc->dev, "not using ECC\n");
break;
default:
dev_err(nfc->dev, "ECC mode %d not supported\n",
- chip->ecc.mode);
+ chip->ecc.engine_type);
return -EINVAL;
}
/* The NAND core will generate the ECC layout for SW ECC */
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return 0;
/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
@@ -365,7 +365,7 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
chip->options = NAND_NO_SUBPAGE_WRITE;
chip->legacy.select_chip = ingenic_nand_select_chip;
chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->controller = &nfc->controller;
nand_set_flash_node(chip, np);
diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c
index 241b58b83240..53fa2b2f6be2 100644
--- a/drivers/mtd/nand/raw/lpc32xx_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c
@@ -656,7 +656,7 @@ static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
if (!host->dummy_buf)
return -ENOMEM;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
host->mlcsubpages = mtd->writesize / 512;
diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c
index 522c7a276d6f..3371a9e84188 100644
--- a/drivers/mtd/nand/raw/lpc32xx_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_slc.c
@@ -881,7 +881,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, host);
/* NAND callbacks for LPC32xx SLC hardware */
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->legacy.read_byte = lpc32xx_nand_read_byte;
chip->legacy.read_buf = lpc32xx_nand_read_buf;
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index a79ce4bdd31c..91cfc9547ba6 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -2247,7 +2247,8 @@ static int marvell_nand_ecc_init(struct mtd_info *mtd,
struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
int ret;
- if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) {
+ if (ecc->engine_type != NAND_ECC_ENGINE_NONE &&
+ (!ecc->size || !ecc->strength)) {
if (chip->base.eccreq.step_size && chip->base.eccreq.strength) {
ecc->size = chip->base.eccreq.step_size;
ecc->strength = chip->base.eccreq.strength;
@@ -2259,15 +2260,15 @@ static int marvell_nand_ecc_init(struct mtd_info *mtd,
}
}
- switch (ecc->mode) {
- case NAND_ECC_HW:
+ switch (ecc->engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
if (ret)
return ret;
break;
- case NAND_ECC_NONE:
- case NAND_ECC_SOFT:
- case NAND_ECC_ON_DIE:
+ case NAND_ECC_ENGINE_NONE:
+ case NAND_ECC_ENGINE_SOFT:
+ case NAND_ECC_ENGINE_ON_DIE:
if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
mtd->writesize != SZ_2K) {
dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
@@ -2465,7 +2466,7 @@ static int marvell_nand_attach_chip(struct nand_chip *chip)
return ret;
}
- if (chip->ecc.mode == NAND_ECC_HW) {
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER) {
/*
* Subpage write not available with hardware ECC, prohibit also
* subpage read as in userspace subpage access would still be
@@ -2640,7 +2641,7 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
* Default to HW ECC engine mode. If the nand-ecc-mode property is given
* in the DT node, this entry will be overwritten in nand_scan_ident().
*/
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
/*
* Save a reference value for timing registers before
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
index 3f376471f3f7..c7bbdb4239a9 100644
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -1197,7 +1197,7 @@ static int meson_nand_attach_chip(struct nand_chip *nand)
if (ret)
return -EINVAL;
- nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand->ecc.write_page_raw = meson_nfc_write_page_raw;
nand->ecc.write_page = meson_nfc_write_page_hwecc;
nand->ecc.write_oob_raw = nand_write_oob_std;
diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c
index a2fcb739e5f8..d2889fb0b81a 100644
--- a/drivers/mtd/nand/raw/mpc5121_nfc.c
+++ b/drivers/mtd/nand/raw/mpc5121_nfc.c
@@ -688,7 +688,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
chip->legacy.set_features = nand_get_set_features_notsupp;
chip->legacy.get_features = nand_get_set_features_notsupp;
chip->bbt_options = NAND_BBT_USE_FLASH;
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
/* Support external chip-select logic on ADS5121 board */
diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c
index e7ec30e784fd..4d028676df8f 100644
--- a/drivers/mtd/nand/raw/mtk_nand.c
+++ b/drivers/mtd/nand/raw/mtk_nand.c
@@ -1226,8 +1226,8 @@ static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
int free, ret;
/* support only ecc hw mode */
- if (nand->ecc.mode != NAND_ECC_HW) {
- dev_err(dev, "ecc.mode not supported\n");
+ if (nand->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER) {
+ dev_err(dev, "ecc.engine_type not supported\n");
return -EINVAL;
}
@@ -1390,7 +1390,7 @@ static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
nand->legacy.cmd_ctrl = mtk_nfc_cmd_ctrl;
/* set default mode in case dt entry is missing */
- nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 59554c187e01..4b7cc756dadf 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -669,7 +669,7 @@ static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
struct mxc_nand_host *host = nand_get_controller_data(chip);
uint16_t config1;
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return;
config1 = readw(NFC_V1_V2_CONFIG1);
@@ -687,7 +687,7 @@ static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
struct mxc_nand_host *host = nand_get_controller_data(chip);
uint32_t config2;
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return;
config2 = readl(NFC_V3_CONFIG2);
@@ -1117,7 +1117,8 @@ static void preset_v1(struct mtd_info *mtd)
struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
uint16_t config1 = 0;
- if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
+ if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER &&
+ mtd->writesize)
config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
if (!host->devtype_data->irqpending_quirk)
@@ -1227,7 +1228,7 @@ static void preset_v2(struct mtd_info *mtd)
if (mtd->writesize) {
uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
- if (nand_chip->ecc.mode == NAND_ECC_HW)
+ if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER)
config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
host->eccsize = get_eccsize(mtd);
@@ -1303,7 +1304,7 @@ static void preset_v3(struct mtd_info *mtd)
}
if (mtd->writesize) {
- if (chip->ecc.mode == NAND_ECC_HW)
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER)
config2 |= NFC_V3_CONFIG2_ECC_EN;
config2 |= NFC_V3_CONFIG2_PPB(
@@ -1680,8 +1681,8 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
struct mxc_nand_host *host = nand_get_controller_data(chip);
struct device *dev = mtd->dev.parent;
- switch (chip->ecc.mode) {
- case NAND_ECC_HW:
+ switch (chip->ecc.engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
chip->ecc.read_page = mxc_nand_read_page;
chip->ecc.read_page_raw = mxc_nand_read_page_raw;
chip->ecc.read_oob = mxc_nand_read_oob;
@@ -1690,7 +1691,7 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
chip->ecc.write_oob = mxc_nand_write_oob;
break;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
break;
default:
@@ -1728,7 +1729,7 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
*/
host->used_oobsize = min(mtd->oobsize, 218U);
- if (chip->ecc.mode == NAND_ECC_HW) {
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER) {
if (is_imx21_nfc(host) || is_imx27_nfc(host))
chip->ecc.strength = 1;
else
@@ -1843,9 +1844,9 @@ static int mxcnd_probe(struct platform_device *pdev)
mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
if (host->pdata.hw_ecc) {
- this->ecc.mode = NAND_ECC_HW;
+ this->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
} else {
- this->ecc.mode = NAND_ECC_SOFT;
+ this->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
this->ecc.algo = NAND_ECC_HAMMING;
}
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f69a3336bc17..17af2fef8f71 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4978,28 +4978,35 @@ static const char * const nand_ecc_placement[] = {
[NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved",
};
-static int of_get_nand_ecc_mode(struct device_node *np)
+static enum nand_ecc_engine_type
+of_get_nand_ecc_engine_type(struct device_node *np)
{
+ enum nand_ecc_engine_type eng_type;
const char *pm;
- int err, i;
+ int err;
err = of_property_read_string(np, "nand-ecc-mode", &pm);
- if (err < 0)
- return err;
+ if (err)
+ return NAND_ECC_ENGINE_INVALID;
- for (i = NAND_ECC_NONE; i < ARRAY_SIZE(nand_ecc_modes); i++)
- if (!strcasecmp(pm, nand_ecc_modes[i]))
- return i;
+ for (eng_type = NAND_ECC_ENGINE_NONE;
+ eng_type < ARRAY_SIZE(nand_ecc_engine_providers); eng_type++) {
+ if (!strcasecmp(pm, nand_ecc_engine_providers[eng_type]))
+ return eng_type;
+ }
/*
* For backward compatibility we support few obsoleted values that don't
- * have their mappings into the nand_ecc_mode enum anymore (they were
- * merged with other enums).
+ * have their mappings into the nand_ecc_engine_providers enum anymore
+ * (they were merged with other enums).
*/
if (!strcasecmp(pm, "soft_bch"))
- return NAND_ECC_SOFT;
+ return NAND_ECC_ENGINE_SOFT;
- return -ENODEV;
+ if (!strcasecmp(pm, "hw_syndrome"))
+ return NAND_ECC_ENGINE_CONTROLLER;
+
+ return NAND_ECC_ENGINE_INVALID;
}
enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np)
@@ -5109,8 +5116,9 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np)
static int nand_dt_init(struct nand_chip *chip)
{
struct device_node *dn = nand_get_flash_node(chip);
+ enum nand_ecc_engine_type ecc_type;
enum nand_ecc_algo ecc_algo;
- int ecc_mode, ecc_strength, ecc_step;
+ int ecc_strength, ecc_step;
if (!dn)
return 0;
@@ -5124,14 +5132,14 @@ static int nand_dt_init(struct nand_chip *chip)
if (of_get_nand_on_flash_bbt(dn))
chip->bbt_options |= NAND_BBT_USE_FLASH;
- ecc_mode = of_get_nand_ecc_mode(dn);
+ ecc_type = of_get_nand_ecc_engine_type(dn);
ecc_algo = of_get_nand_ecc_algo(dn);
chip->ecc.placement = of_get_nand_ecc_placement(dn);
ecc_strength = of_get_nand_ecc_strength(dn);
ecc_step = of_get_nand_ecc_step_size(dn);
- if (ecc_mode >= 0)
- chip->ecc.mode = ecc_mode;
+ if (ecc_type != NAND_ECC_ENGINE_INVALID)
+ chip->ecc.engine_type = ecc_type;
if (ecc_algo != NAND_ECC_UNKNOWN)
chip->ecc.algo = ecc_algo;
@@ -5253,7 +5261,7 @@ static int nand_set_ecc_soft_ops(struct nand_chip *chip)
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
- if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
+ if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_SOFT))
return -EINVAL;
switch (ecc->algo) {
@@ -5718,7 +5726,8 @@ static int nand_scan_tail(struct nand_chip *chip)
* If no default placement scheme is given, select an appropriate one.
*/
if (!mtd->ooblayout &&
- !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
+ !(ecc->engine_type == NAND_ECC_ENGINE_SOFT &&
+ ecc->algo == NAND_ECC_BCH)) {
switch (mtd->oobsize) {
case 8:
case 16:
@@ -5736,7 +5745,7 @@ static int nand_scan_tail(struct nand_chip *chip)
* page with ECC layout when ->oobsize <= 128 for
* compatibility reasons.
*/
- if (ecc->mode == NAND_ECC_NONE) {
+ if (ecc->engine_type == NAND_ECC_ENGINE_NONE) {
mtd_set_ooblayout(mtd,
&nand_ooblayout_lp_ops);
break;
@@ -5754,8 +5763,9 @@ static int nand_scan_tail(struct nand_chip *chip)
* selected and we have 256 byte pagesize fallback to software ECC
*/
- switch (ecc->mode) {
- case NAND_ECC_HW:
+ switch (ecc->engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
+
switch (ecc->placement) {
case NAND_ECC_PLACEMENT_FREE:
/* Use standard hwecc read page function? */
@@ -5811,7 +5821,7 @@ static int nand_scan_tail(struct nand_chip *chip)
}
pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
ecc->size, mtd->writesize);
- ecc->mode = NAND_ECC_SOFT;
+ ecc->engine_type = NAND_ECC_ENGINE_SOFT;
ecc->algo = NAND_ECC_HAMMING;
break;
@@ -5823,7 +5833,7 @@ static int nand_scan_tail(struct nand_chip *chip)
}
fallthrough;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
ret = nand_set_ecc_soft_ops(chip);
if (ret) {
ret = -EINVAL;
@@ -5831,7 +5841,7 @@ static int nand_scan_tail(struct nand_chip *chip)
}
break;
- case NAND_ECC_ON_DIE:
+ case NAND_ECC_ENGINE_ON_DIE:
if (!ecc->read_page || !ecc->write_page) {
WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
ret = -EINVAL;
@@ -5843,8 +5853,8 @@ static int nand_scan_tail(struct nand_chip *chip)
ecc->write_oob = nand_write_oob_std;
break;
- case NAND_ECC_NONE:
- pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
+ case NAND_ECC_ENGINE_NONE:
+ pr_warn("NAND_ECC_ENGINE_NONE selected by board driver. This is not recommended!\n");
ecc->read_page = nand_read_page_raw;
ecc->write_page = nand_write_page_raw;
ecc->read_oob = nand_read_oob_std;
@@ -5857,7 +5867,7 @@ static int nand_scan_tail(struct nand_chip *chip)
break;
default:
- WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
+ WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);
ret = -EINVAL;
goto err_nand_manuf_cleanup;
}
@@ -5934,8 +5944,8 @@ static int nand_scan_tail(struct nand_chip *chip)
chip->pagecache.page = -1;
/* Large page NAND with SOFT_ECC should support subpage reads */
- switch (ecc->mode) {
- case NAND_ECC_SOFT:
+ switch (ecc->engine_type) {
+ case NAND_ECC_ENGINE_SOFT:
if (chip->page_shift > 9)
chip->options |= NAND_SUBPAGE_READ;
break;
@@ -6077,7 +6087,7 @@ EXPORT_SYMBOL(nand_scan_with_ids);
*/
void nand_cleanup(struct nand_chip *chip)
{
- if (chip->ecc.mode == NAND_ECC_SOFT &&
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_SOFT &&
chip->ecc.algo == NAND_ECC_BCH)
nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c
index b2b047b245f4..fc7f69b65b2c 100644
--- a/drivers/mtd/nand/raw/nand_micron.c
+++ b/drivers/mtd/nand/raw/nand_micron.c
@@ -454,13 +454,13 @@ static int micron_nand_init(struct nand_chip *chip)
ondie = micron_supports_on_die_ecc(chip);
if (ondie == MICRON_ON_DIE_MANDATORY &&
- chip->ecc.mode != NAND_ECC_ON_DIE) {
+ chip->ecc.engine_type != NAND_ECC_ENGINE_ON_DIE) {
pr_err("On-die ECC forcefully enabled, not supported\n");
ret = -EINVAL;
goto err_free_manuf_data;
}
- if (chip->ecc.mode == NAND_ECC_ON_DIE) {
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_ON_DIE) {
if (ondie == MICRON_ON_DIE_UNSUPPORTED) {
pr_err("On-die ECC selected but not supported\n");
ret = -EINVAL;
diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c
index ae069905d7e4..d36608e53bb0 100644
--- a/drivers/mtd/nand/raw/nand_toshiba.c
+++ b/drivers/mtd/nand/raw/nand_toshiba.c
@@ -211,7 +211,8 @@ static int toshiba_nand_init(struct nand_chip *chip)
chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
/* Check that chip is BENAND and ECC mode is on-die */
- if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE &&
+ if (nand_is_slc(chip) &&
+ chip->ecc.engine_type == NAND_ECC_ENGINE_ON_DIE &&
chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
toshiba_nand_benand_init(chip);
diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
index 23cda67a3f53..cc6d99b93cd4 100644
--- a/drivers/mtd/nand/raw/nandsim.c
+++ b/drivers/mtd/nand/raw/nandsim.c
@@ -2206,7 +2206,7 @@ static int ns_attach_chip(struct nand_chip *chip)
return -EINVAL;
}
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_BCH;
chip->ecc.size = 512;
chip->ecc.strength = bch;
@@ -2245,7 +2245,7 @@ static int __init ns_init_module(void)
nsmtd = nand_to_mtd(chip);
nand_set_controller_data(chip, (void *)ns);
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
/* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
/* and 'badblocks' parameters to work */
diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c
index d324396ab7ff..e387c7e175fd 100644
--- a/drivers/mtd/nand/raw/ndfc.c
+++ b/drivers/mtd/nand/raw/ndfc.c
@@ -149,7 +149,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
chip->ecc.correct = nand_correct_data;
chip->ecc.hwctl = ndfc_enable_hwecc;
chip->ecc.calculate = ndfc_calculate_ecc;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 256;
chip->ecc.bytes = 3;
chip->ecc.strength = 1;
diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c
index ad77c112a78a..fecb9634bea5 100644
--- a/drivers/mtd/nand/raw/omap2.c
+++ b/drivers/mtd/nand/raw/omap2.c
@@ -884,8 +884,8 @@ static int omap_correct_data(struct nand_chip *chip, u_char *dat,
int stat = 0;
/* Ex NAND_ECC_HW12_2048 */
- if ((info->nand.ecc.mode == NAND_ECC_HW) &&
- (info->nand.ecc.size == 2048))
+ if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER &&
+ info->nand.ecc.size == 2048)
blockCnt = 4;
else
blockCnt = 1;
@@ -2006,11 +2006,11 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
return -EINVAL;
/*
- * Bail out earlier to let NAND_ECC_SOFT code create its own
+ * Bail out earlier to let NAND_ECC_ENGINE_SOFT code create its own
* ooblayout instead of using ours.
*/
if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
return 0;
}
@@ -2019,7 +2019,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
switch (info->ecc_opt) {
case OMAP_ECC_HAM1_CODE_HW:
dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.bytes = 3;
chip->ecc.size = 512;
chip->ecc.strength = 1;
@@ -2036,7 +2036,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
chip->ecc.bytes = 7;
chip->ecc.strength = 4;
@@ -2056,7 +2056,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
case OMAP_ECC_BCH4_CODE_HW:
pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
/* 14th bit is kept reserved for ROM-code compatibility */
chip->ecc.bytes = 7 + 1;
@@ -2078,7 +2078,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
chip->ecc.bytes = 13;
chip->ecc.strength = 8;
@@ -2098,7 +2098,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
case OMAP_ECC_BCH8_CODE_HW:
pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
/* 14th bit is kept reserved for ROM-code compatibility */
chip->ecc.bytes = 13 + 1;
@@ -2121,7 +2121,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
case OMAP_ECC_BCH16_CODE_HW:
pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
chip->ecc.bytes = 26;
chip->ecc.strength = 16;
diff --git a/drivers/mtd/nand/raw/orion_nand.c b/drivers/mtd/nand/raw/orion_nand.c
index d27b39a7223c..9c3d530fc565 100644
--- a/drivers/mtd/nand/raw/orion_nand.c
+++ b/drivers/mtd/nand/raw/orion_nand.c
@@ -139,7 +139,7 @@ static int __init orion_nand_probe(struct platform_device *pdev)
nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
nc->legacy.read_buf = orion_nand_read_buf;
- nc->ecc.mode = NAND_ECC_SOFT;
+ nc->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
nc->ecc.algo = NAND_ECC_HAMMING;
if (board->chip_delay)
diff --git a/drivers/mtd/nand/raw/pasemi_nand.c b/drivers/mtd/nand/raw/pasemi_nand.c
index 9cfe7395172a..e896b70ca58f 100644
--- a/drivers/mtd/nand/raw/pasemi_nand.c
+++ b/drivers/mtd/nand/raw/pasemi_nand.c
@@ -132,7 +132,7 @@ static int pasemi_nand_probe(struct platform_device *ofdev)
chip->legacy.read_buf = pasemi_read_buf;
chip->legacy.write_buf = pasemi_write_buf;
chip->legacy.chip_delay = 0;
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
/* Enable the following for a flash based bad block table */
diff --git a/drivers/mtd/nand/raw/plat_nand.c b/drivers/mtd/nand/raw/plat_nand.c
index dc0f3074ddbf..a9e949096096 100644
--- a/drivers/mtd/nand/raw/plat_nand.c
+++ b/drivers/mtd/nand/raw/plat_nand.c
@@ -66,7 +66,7 @@ static int plat_nand_probe(struct platform_device *pdev)
data->chip.options |= pdata->chip.options;
data->chip.bbt_options |= pdata->chip.bbt_options;
- data->chip.ecc.mode = NAND_ECC_SOFT;
+ data->chip.ecc.engine_type = NAND_ECC_ENGINE_SOFT;
data->chip.ecc.algo = NAND_ECC_HAMMING;
platform_set_drvdata(pdev, data);
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 9ab22c5d4166..71bb0bdec126 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2548,7 +2548,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
ecc->write_page_raw = qcom_nandc_write_page_raw;
ecc->write_oob = qcom_nandc_write_oob;
- ecc->mode = NAND_ECC_HW;
+ ecc->engine_type = NAND_ECC_ENGINE_CONTROLLER;
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
diff --git a/drivers/mtd/nand/raw/r852.c b/drivers/mtd/nand/raw/r852.c
index 764715bae6a6..5faf98705881 100644
--- a/drivers/mtd/nand/raw/r852.c
+++ b/drivers/mtd/nand/raw/r852.c
@@ -857,7 +857,7 @@ static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
chip->legacy.write_buf = r852_write_buf;
/* ecc */
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->ecc.size = R852_DMA_LEN;
chip->ecc.bytes = SM_OOB_SIZE;
diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c
index 0009c1820e21..4499e2020c24 100644
--- a/drivers/mtd/nand/raw/s3c2410.c
+++ b/drivers/mtd/nand/raw/s3c2410.c
@@ -903,7 +903,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
nmtd->info = info;
nmtd->set = set;
- chip->ecc.mode = info->platform->ecc_mode;
+ chip->ecc.engine_type = info->platform->engine_type;
/*
* If you use u-boot BBT creation code, specifying this flag will
@@ -928,24 +928,24 @@ static int s3c2410_nand_attach_chip(struct nand_chip *chip)
struct mtd_info *mtd = nand_to_mtd(chip);
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
- switch (chip->ecc.mode) {
+ switch (chip->ecc.engine_type) {
- case NAND_ECC_NONE:
+ case NAND_ECC_ENGINE_NONE:
dev_info(info->device, "ECC disabled\n");
break;
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_SOFT:
/*
- * This driver expects Hamming based ECC when ecc_mode is set
- * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
- * avoid adding an extra ecc_algo field to
+ * This driver expects Hamming based ECC when engine_type is set
+ * to NAND_ECC_ENGINE_SOFT. Force ecc.algo to NAND_ECC_HAMMING
+ * to avoid adding an extra ecc_algo field to
* s3c2410_platform_nand.
*/
chip->ecc.algo = NAND_ECC_HAMMING;
dev_info(info->device, "soft ECC\n");
break;
- case NAND_ECC_HW:
+ case NAND_ECC_ENGINE_CONTROLLER:
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
chip->ecc.correct = s3c2410_nand_correct_data;
chip->ecc.strength = 1;
diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c
index 058e99d0cbcf..cf87436a62d9 100644
--- a/drivers/mtd/nand/raw/sh_flctl.c
+++ b/drivers/mtd/nand/raw/sh_flctl.c
@@ -1039,12 +1039,12 @@ static int flctl_chip_attach_chip(struct nand_chip *chip)
chip->ecc.strength = 4;
chip->ecc.read_page = flctl_read_page_hwecc;
chip->ecc.write_page = flctl_write_page_hwecc;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
/* 4 symbols ECC enabled */
flctl->flcmncr_base |= _4ECCEN;
} else {
- chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
chip->ecc.algo = NAND_ECC_HAMMING;
}
diff --git a/drivers/mtd/nand/raw/sharpsl.c b/drivers/mtd/nand/raw/sharpsl.c
index b47a9eaff89b..8a280b2e8e90 100644
--- a/drivers/mtd/nand/raw/sharpsl.c
+++ b/drivers/mtd/nand/raw/sharpsl.c
@@ -157,7 +157,7 @@ static int sharpsl_nand_probe(struct platform_device *pdev)
/* 15 us command delay time */
this->legacy.chip_delay = 15;
/* set eccmode using hardware ECC */
- this->ecc.mode = NAND_ECC_HW;
+ this->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
this->ecc.size = 256;
this->ecc.bytes = 3;
this->ecc.strength = 1;
diff --git a/drivers/mtd/nand/raw/socrates_nand.c b/drivers/mtd/nand/raw/socrates_nand.c
index 20f40c0e812c..1b96840b6025 100644
--- a/drivers/mtd/nand/raw/socrates_nand.c
+++ b/drivers/mtd/nand/raw/socrates_nand.c
@@ -153,7 +153,8 @@ static int socrates_nand_probe(struct platform_device *ofdev)
nand_chip->legacy.read_buf = socrates_nand_read_buf;
nand_chip->legacy.dev_ready = socrates_nand_device_ready;
- nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
+ /* enable ECC */
+ nand_chip->ecc.engine_type = NAND_ECC_ENGINE_SOFT;
nand_chip->ecc.algo = NAND_ECC_HAMMING;
/* TODO: I have no idea what real delay is. */
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 30083e52b2fc..d1275d3b15ad 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -1736,14 +1736,15 @@ static int stm32_fmc2_attach_chip(struct nand_chip *chip)
int ret;
/*
- * Only NAND_ECC_HW mode is actually supported
+ * Only NAND_ECC_ENGINE_CONTROLLER mode is actually supported
* Hamming => ecc.strength = 1
* BCH4 => ecc.strength = 4
* BCH8 => ecc.strength = 8
* ECC sector size = 512
*/
- if (chip->ecc.mode != NAND_ECC_HW) {
- dev_err(fmc2->dev, "nand_ecc_mode is not well defined in the DT\n");
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER) {
+ dev_err(fmc2->dev,
+ "nand_ecc_engine_type is not well defined in the DT\n");
return -EINVAL;
}
@@ -1953,7 +1954,7 @@ static int stm32_fmc2_probe(struct platform_device *pdev)
NAND_USES_DMA;
/* Default ECC settings */
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = FMC2_ECC_STEP_SIZE;
chip->ecc.strength = FMC2_ECC_BCH8;
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index 26d862213cac..1239107e16cc 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -1575,7 +1575,7 @@ static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section,
* only have 2 bytes available in the first user data
* section.
*/
- if (!section && ecc->mode == NAND_ECC_HW) {
+ if (!section && ecc->engine_type == NAND_ECC_ENGINE_CONTROLLER) {
oobregion->offset = 2;
oobregion->length = 2;
@@ -1720,11 +1720,11 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
{
- switch (ecc->mode) {
- case NAND_ECC_HW:
+ switch (ecc->engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
sunxi_nand_hw_ecc_ctrl_cleanup(ecc);
break;
- case NAND_ECC_NONE:
+ case NAND_ECC_ENGINE_NONE:
default:
break;
}
@@ -1752,14 +1752,14 @@ static int sunxi_nand_attach_chip(struct nand_chip *nand)
if (!ecc->size || !ecc->strength)
return -EINVAL;
- switch (ecc->mode) {
- case NAND_ECC_HW:
+ switch (ecc->engine_type) {
+ case NAND_ECC_ENGINE_CONTROLLER:
ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np);
if (ret)
return ret;
break;
- case NAND_ECC_NONE:
- case NAND_ECC_SOFT:
+ case NAND_ECC_ENGINE_NONE:
+ case NAND_ECC_ENGINE_SOFT:
break;
default:
return -EINVAL;
@@ -1991,7 +1991,7 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
* Set the ECC mode to the default value in case nothing is specified
* in the DT.
*/
- nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand_set_flash_node(nand, np);
mtd = nand_to_mtd(nand);
diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c
index b92de603e6db..bfbe71f65523 100644
--- a/drivers/mtd/nand/raw/tango_nand.c
+++ b/drivers/mtd/nand/raw/tango_nand.c
@@ -511,7 +511,7 @@ static int tango_attach_chip(struct nand_chip *chip)
{
struct nand_ecc_ctrl *ecc = &chip->ecc;
- ecc->mode = NAND_ECC_HW;
+ ecc->engine_type = NAND_ECC_ENGINE_CONTROLLER;
ecc->algo = NAND_ECC_BCH;
ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
index f9d046b2cd3b..feb26494443e 100644
--- a/drivers/mtd/nand/raw/tegra_nand.c
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -916,7 +916,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
if (chip->bbt_options & NAND_BBT_USE_FLASH)
chip->bbt_options |= NAND_BBT_NO_OOB;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.size = 512;
chip->ecc.steps = mtd->writesize / chip->ecc.size;
if (chip->base.eccreq.step_size != 512) {
diff --git a/drivers/mtd/nand/raw/tmio_nand.c b/drivers/mtd/nand/raw/tmio_nand.c
index db030f1701ee..c299ea6a611b 100644
--- a/drivers/mtd/nand/raw/tmio_nand.c
+++ b/drivers/mtd/nand/raw/tmio_nand.c
@@ -410,7 +410,7 @@ static int tmio_probe(struct platform_device *dev)
nand_chip->legacy.read_buf = tmio_nand_read_buf;
/* set eccmode using hardware ECC */
- nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
nand_chip->ecc.size = 512;
nand_chip->ecc.bytes = 6;
nand_chip->ecc.strength = 2;
diff --git a/drivers/mtd/nand/raw/txx9ndfmc.c b/drivers/mtd/nand/raw/txx9ndfmc.c
index 2642d5bb3241..cf9c4bd56e1a 100644
--- a/drivers/mtd/nand/raw/txx9ndfmc.c
+++ b/drivers/mtd/nand/raw/txx9ndfmc.c
@@ -329,7 +329,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
chip->ecc.calculate = txx9ndfmc_calculate_ecc;
chip->ecc.correct = txx9ndfmc_correct_data;
chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_CONTROLLER;
chip->ecc.strength = 1;
chip->legacy.chip_delay = 100;
chip->controller = &drvdata->controller;
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index bd9e16de78a2..a9fa1ae22634 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -732,7 +732,7 @@ static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
else
vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
- if (nfc->chip.ecc.mode == NAND_ECC_HW) {
+ if (nfc->chip.ecc.engine_type == NAND_ECC_ENGINE_CONTROLLER) {
/* Set ECC status offset in SRAM */
vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
CONFIG_ECC_SRAM_ADDR_MASK,
@@ -761,7 +761,7 @@ static int vf610_nfc_attach_chip(struct nand_chip *chip)
return -ENXIO;
}
- if (chip->ecc.mode != NAND_ECC_HW)
+ if (chip->ecc.engine_type != NAND_ECC_ENGINE_CONTROLLER)
return 0;
if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
diff --git a/drivers/mtd/nand/raw/xway_nand.c b/drivers/mtd/nand/raw/xway_nand.c
index 834f794816a9..36dea82063bd 100644
--- a/drivers/mtd/nand/raw/xway_nand.c
+++ b/drivers/mtd/nand/raw/xway_nand.c
@@ -180,7 +180,7 @@ static int xway_nand_probe(struct platform_device *pdev)
data->chip.legacy.read_byte = xway_read_byte;
data->chip.legacy.chip_delay = 30;
- data->chip.ecc.mode = NAND_ECC_SOFT;
+ data->chip.ecc.engine_type = NAND_ECC_ENGINE_SOFT;
data->chip.ecc.algo = NAND_ECC_HAMMING;
platform_set_drvdata(pdev, data);
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 0c2cfe4a5928..ce7f1f301bf6 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -338,7 +338,7 @@ static const struct nand_ecc_caps __name = { \
/**
* struct nand_ecc_ctrl - Control structure for ECC
- * @mode: ECC mode
+ * @engine_type: ECC engine type
* @placement: OOB bytes placement
* @algo: ECC algorithm
* @steps: number of ECC steps per page
@@ -391,7 +391,7 @@ static const struct nand_ecc_caps __name = { \
* @write_oob: function to write chip OOB data
*/
struct nand_ecc_ctrl {
- enum nand_ecc_mode mode;
+ enum nand_ecc_engine_type engine_type;
enum nand_ecc_placement placement;
enum nand_ecc_algo algo;
int steps;
diff --git a/include/linux/platform_data/mtd-davinci.h b/include/linux/platform_data/mtd-davinci.h
index 3383101c233b..e632f392291a 100644
--- a/include/linux/platform_data/mtd-davinci.h
+++ b/include/linux/platform_data/mtd-davinci.h
@@ -60,16 +60,16 @@ struct davinci_nand_pdata { /* platform_data */
struct mtd_partition *parts;
unsigned nr_parts;
- /* none == NAND_ECC_NONE (strongly *not* advised!!)
- * soft == NAND_ECC_SOFT
- * else == NAND_ECC_HW, according to ecc_bits
+ /* none == NAND_ECC_ENGINE_NONE (strongly *not* advised!!)
+ * soft == NAND_ECC_ENGINE_SOFT
+ * else == NAND_ECC_ENGINE_CONTROLLER, according to ecc_bits
*
* All DaVinci-family chips support 1-bit hardware ECC.
* Newer ones also support 4-bit ECC, but are awkward
* using it with large page chips.
*/
- enum nand_ecc_mode ecc_mode;
- enum nand_ecc_placement ecc_placement;
+ enum nand_ecc_engine_type engine_type;
+ enum nand_ecc_placement ecc_placement;
u8 ecc_bits;
/* e.g. NAND_BUSWIDTH_16 */
diff --git a/include/linux/platform_data/mtd-nand-s3c2410.h b/include/linux/platform_data/mtd-nand-s3c2410.h
index 08675b16f9e1..25390fc3e795 100644
--- a/include/linux/platform_data/mtd-nand-s3c2410.h
+++ b/include/linux/platform_data/mtd-nand-s3c2410.h
@@ -49,7 +49,7 @@ struct s3c2410_platform_nand {
unsigned int ignore_unset_ecc:1;
- enum nand_ecc_mode ecc_mode;
+ enum nand_ecc_engine_type engine_type;
int nr_sets;
struct s3c2410_nand_set *sets;
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 14/21] dt-bindings: mtd: Add the nand-ecc-placement property
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Placement is where the ECC bytes are expected.
No value means the controller can do whatever it desires (default is
to put ECC bytes at the end of the OOB area). Alternative placement is
"interleaved" (also sometimes referred as "syndrome") where data and
OOB are mixed.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../devicetree/bindings/mtd/nand-controller.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index d529f8587ba6..35512f2c66fa 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -56,6 +56,16 @@ patternProperties:
(Linux will handle the calculations). soft_bch is deprecated
and should be replaced by soft and nand-ecc-algo.
+ nand-ecc-placement:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ - enum: [ free, interleaved ]
+ description:
+ Location for the ECC bytes. Free is the default and means the
+ controller in charge is free to put them where it wants.
+ Default state is to put ECC bytes at the end of the OOB area.
+ Otherwise, ECC bytes may be interleaved with data.
+
nand-ecc-algo:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 13/21] mtd: rawnand: Drop the legacy ECC type enumeration
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Now that all files have been migrated to use the new enumeration, drop
the old one which is unused.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/nand_base.c | 8 --------
include/linux/mtd/rawnand.h | 12 ------------
2 files changed, 20 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 130db134bd58..59a66c641db0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4959,14 +4959,6 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
return ret;
}
-static const char * const nand_ecc_modes[] = {
- [NAND_ECC_NONE] = "none",
- [NAND_ECC_SOFT] = "soft",
- [NAND_ECC_HW] = "hw",
- [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
- [NAND_ECC_ON_DIE] = "on-die",
-};
-
static const char * const nand_ecc_engine_providers[] = {
[NAND_ECC_ENGINE_NONE] = "none",
[NAND_ECC_ENGINE_SOFT] = "soft",
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index ce7f1f301bf6..a41225b8f6fb 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -80,18 +80,6 @@ struct nand_chip;
#define NAND_DATA_IFACE_CHECK_ONLY -1
-/*
- * Constants for ECC_MODES
- */
-enum nand_ecc_mode {
- NAND_ECC_INVALID,
- NAND_ECC_NONE,
- NAND_ECC_SOFT,
- NAND_ECC_HW,
- NAND_ECC_HW_SYNDROME,
- NAND_ECC_ON_DIE,
-};
-
/**
* enum nand_ecc_engine_type - NAND ECC engine type/provider
* @NAND_ECC_ENGINE_INVALID: Invalid value
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 12/21] mtd: rawnand: Deprecate nand-ecc-mode in favor of nand-ecc-provider
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Use nand-ecc-provider as the provider DT property. Fallback to
nand-ecc-mode if the property does not exist.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/nand_base.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 17af2fef8f71..130db134bd58 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4985,7 +4985,9 @@ of_get_nand_ecc_engine_type(struct device_node *np)
const char *pm;
int err;
- err = of_property_read_string(np, "nand-ecc-mode", &pm);
+ err = of_property_read_string(np, "nand-ecc-provider", &pm);
+ if (err)
+ err = of_property_read_string(np, "nand-ecc-mode", &pm);
if (err)
return NAND_ECC_ENGINE_INVALID;
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 10/21] mtd: rawnand: Create a helper to retrieve the ECC placement
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Use it from nand_dt_init() to initialize the ECC structure.
This allows the deprecation of the hw_syndrome ECC mode.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 7e5a86fa38ee..f69a3336bc17 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5002,6 +5002,34 @@ static int of_get_nand_ecc_mode(struct device_node *np)
return -ENODEV;
}
+enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np)
+{
+ enum nand_ecc_placement placement;
+ const char *pm;
+ int err;
+
+ err = of_property_read_string(np, "nand-ecc-placement", &pm);
+ if (!err) {
+ for (placement = NAND_ECC_PLACEMENT_INTERLEAVED;
+ placement < ARRAY_SIZE(nand_ecc_placement); placement++) {
+ if (!strcasecmp(pm, nand_ecc_placement[placement]))
+ return placement;
+ }
+ }
+
+ /*
+ * For backward compatibility we support few obsoleted values that don't
+ * have their mappings into the nand_ecc_placement enum anymore.
+ */
+ err = of_property_read_string(np, "nand-ecc-mode", &pm);
+ if (!err) {
+ if (!strcasecmp(pm, "hw_syndrome"))
+ return NAND_ECC_PLACEMENT_INTERLEAVED;
+ }
+
+ return NAND_ECC_PLACEMENT_FREE;
+}
+
static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING] = "hamming",
[NAND_ECC_BCH] = "bch",
@@ -5098,6 +5126,7 @@ static int nand_dt_init(struct nand_chip *chip)
ecc_mode = of_get_nand_ecc_mode(dn);
ecc_algo = of_get_nand_ecc_algo(dn);
+ chip->ecc.placement = of_get_nand_ecc_placement(dn);
ecc_strength = of_get_nand_ecc_strength(dn);
ecc_step = of_get_nand_ecc_step_size(dn);
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 09/21] mtd: rawnand: Create a new enumeration to describe properly ECC types
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
Now that the misleading mix between ECC engine type and OOB placement
has been addressed, add a new enumeration to properly define ECC types
(also called provider or mode).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/raw/nand_base.c | 7 +++++++
include/linux/mtd/rawnand.h | 16 ++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 48529c21239c..7e5a86fa38ee 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4967,6 +4967,13 @@ static const char * const nand_ecc_modes[] = {
[NAND_ECC_ON_DIE] = "on-die",
};
+static const char * const nand_ecc_engine_providers[] = {
+ [NAND_ECC_ENGINE_NONE] = "none",
+ [NAND_ECC_ENGINE_SOFT] = "soft",
+ [NAND_ECC_ENGINE_CONTROLLER] = "hw",
+ [NAND_ECC_ENGINE_ON_DIE] = "on-die",
+};
+
static const char * const nand_ecc_placement[] = {
[NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved",
};
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 59021ceb9b00..0c2cfe4a5928 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -92,6 +92,22 @@ enum nand_ecc_mode {
NAND_ECC_ON_DIE,
};
+/**
+ * enum nand_ecc_engine_type - NAND ECC engine type/provider
+ * @NAND_ECC_ENGINE_INVALID: Invalid value
+ * @NAND_ECC_ENGINE_NONE: No ECC correction
+ * @NAND_ECC_ENGINE_SOFT: Software ECC correction
+ * @NAND_ECC_ENGINE_CONTROLLER: Hardware controller ECC correction
+ * @NAND_ECC_ENGINE_ON_DIE: On chip hardware ECC correction
+ */
+enum nand_ecc_engine_type {
+ NAND_ECC_ENGINE_INVALID,
+ NAND_ECC_ENGINE_NONE,
+ NAND_ECC_ENGINE_SOFT,
+ NAND_ECC_ENGINE_CONTROLLER,
+ NAND_ECC_ENGINE_ON_DIE,
+};
+
/**
* enum nand_ecc_placement - NAND ECC placement
* @NAND_ECC_PLACEMENT_FREE: The driver can decide where to put ECC bytes.
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 08/21] mtd: rawnand: Separate the ECC engine type and the OOB placement
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
The use of "SYNDROME" placement should not be encoded in the ECC
engine mode (also called type, or provider).
Create a "placement" field in NAND chip and change all occurrences of
the NAND_ECC_HW_SYNDROME enumeration to be just NAND_ECC_HW and
possibly a placement entry like NAND_ECC_PLACEMENT_INTERLEAVED.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm/mach-davinci/board-dm355-leopard.c | 3 +-
drivers/mtd/nand/raw/cafe_nand.c | 3 +-
drivers/mtd/nand/raw/davinci_nand.c | 5 +-
drivers/mtd/nand/raw/denali.c | 3 +-
drivers/mtd/nand/raw/diskonchip.c | 3 +-
drivers/mtd/nand/raw/lpc32xx_slc.c | 3 +-
drivers/mtd/nand/raw/nand_base.c | 108 +++++++++++---------
drivers/mtd/nand/raw/r852.c | 3 +-
include/linux/mtd/rawnand.h | 6 +-
include/linux/platform_data/mtd-davinci.h | 1 +
10 files changed, 80 insertions(+), 58 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index b9e9950dd300..4c8a592754ac 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -76,7 +76,8 @@ static struct davinci_nand_pdata davinci_nand_data = {
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW_SYNDROME,
+ .ecc_mode = NAND_HW_ECC_ENGINE,
+ .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
};
diff --git a/drivers/mtd/nand/raw/cafe_nand.c b/drivers/mtd/nand/raw/cafe_nand.c
index 2a0df13df5f3..6afafc8bda2a 100644
--- a/drivers/mtd/nand/raw/cafe_nand.c
+++ b/drivers/mtd/nand/raw/cafe_nand.c
@@ -629,7 +629,8 @@ static int cafe_nand_attach_chip(struct nand_chip *chip)
goto out_free_dma;
}
- cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
+ cafe->nand.ecc.mode = NAND_ECC_HW;
+ cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
cafe->nand.ecc.size = mtd->writesize;
cafe->nand.ecc.bytes = 14;
cafe->nand.ecc.strength = 4;
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 5ea562098c8c..9ac1636fb9ae 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -207,7 +207,7 @@ static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
/*
* 4-bit hardware ECC ... context maintained over entire AEMIF
*
- * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
+ * This is a syndrome engine, but we avoid NAND_ECC_PLACEMENT_INTERLEAVED
* since that forces use of a problematic "infix OOB" layout.
* Among other things, it trashes manufacturer bad block markers.
* Also, and specific to this hardware, it ECC-protects the "prepad"
@@ -847,6 +847,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
/* Use board-specific ECC config */
info->chip.ecc.mode = pdata->ecc_mode;
+ info->chip.ecc.placement = pdata->ecc_placement;
spin_lock_irq(&davinci_nand_lock);
@@ -889,7 +890,7 @@ static int nand_davinci_remove(struct platform_device *pdev)
struct davinci_nand_info *info = platform_get_drvdata(pdev);
spin_lock_irq(&davinci_nand_lock);
- if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
+ if (info->chip.ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)
ecc4_busy = false;
spin_unlock_irq(&davinci_nand_lock);
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index 7a76b761dd0b..f52b59403895 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -1237,7 +1237,8 @@ int denali_chip_init(struct denali_controller *denali,
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
chip->options |= NAND_NO_SUBPAGE_WRITE;
- chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->ecc.read_page = denali_read_page;
chip->ecc.write_page = denali_write_page;
chip->ecc.read_page_raw = denali_read_page_raw;
diff --git a/drivers/mtd/nand/raw/diskonchip.c b/drivers/mtd/nand/raw/diskonchip.c
index 97f0b05b47c1..a836de521535 100644
--- a/drivers/mtd/nand/raw/diskonchip.c
+++ b/drivers/mtd/nand/raw/diskonchip.c
@@ -1456,7 +1456,8 @@ static int __init doc_probe(unsigned long physadr)
nand->ecc.calculate = doc200x_calculate_ecc;
nand->ecc.correct = doc200x_correct_data;
- nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
nand->ecc.size = 512;
nand->ecc.bytes = 6;
nand->ecc.strength = 2;
diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c
index 163f976353f8..522c7a276d6f 100644
--- a/drivers/mtd/nand/raw/lpc32xx_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_slc.c
@@ -881,7 +881,8 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, host);
/* NAND callbacks for LPC32xx SLC hardware */
- chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->legacy.read_byte = lpc32xx_nand_read_byte;
chip->legacy.read_buf = lpc32xx_nand_read_buf;
chip->legacy.write_buf = lpc32xx_nand_write_buf;
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index b84fb5e6ecbe..48529c21239c 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5720,61 +5720,73 @@ static int nand_scan_tail(struct nand_chip *chip)
switch (ecc->mode) {
case NAND_ECC_HW:
- /* Use standard hwecc read page function? */
- if (!ecc->read_page)
- ecc->read_page = nand_read_page_hwecc;
- if (!ecc->write_page)
- ecc->write_page = nand_write_page_hwecc;
- if (!ecc->read_page_raw)
- ecc->read_page_raw = nand_read_page_raw;
- if (!ecc->write_page_raw)
- ecc->write_page_raw = nand_write_page_raw;
- if (!ecc->read_oob)
- ecc->read_oob = nand_read_oob_std;
- if (!ecc->write_oob)
- ecc->write_oob = nand_write_oob_std;
- if (!ecc->read_subpage)
- ecc->read_subpage = nand_read_subpage;
- if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
- ecc->write_subpage = nand_write_subpage_hwecc;
- fallthrough;
- case NAND_ECC_HW_SYNDROME:
- if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
- (!ecc->read_page ||
- ecc->read_page == nand_read_page_hwecc ||
- !ecc->write_page ||
- ecc->write_page == nand_write_page_hwecc)) {
- WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
- ret = -EINVAL;
- goto err_nand_manuf_cleanup;
- }
- /* Use standard syndrome read/write page function? */
- if (!ecc->read_page)
- ecc->read_page = nand_read_page_syndrome;
- if (!ecc->write_page)
- ecc->write_page = nand_write_page_syndrome;
- if (!ecc->read_page_raw)
- ecc->read_page_raw = nand_read_page_raw_syndrome;
- if (!ecc->write_page_raw)
- ecc->write_page_raw = nand_write_page_raw_syndrome;
- if (!ecc->read_oob)
- ecc->read_oob = nand_read_oob_syndrome;
- if (!ecc->write_oob)
- ecc->write_oob = nand_write_oob_syndrome;
+ switch (ecc->placement) {
+ case NAND_ECC_PLACEMENT_FREE:
+ /* Use standard hwecc read page function? */
+ if (!ecc->read_page)
+ ecc->read_page = nand_read_page_hwecc;
+ if (!ecc->write_page)
+ ecc->write_page = nand_write_page_hwecc;
+ if (!ecc->read_page_raw)
+ ecc->read_page_raw = nand_read_page_raw;
+ if (!ecc->write_page_raw)
+ ecc->write_page_raw = nand_write_page_raw;
+ if (!ecc->read_oob)
+ ecc->read_oob = nand_read_oob_std;
+ if (!ecc->write_oob)
+ ecc->write_oob = nand_write_oob_std;
+ if (!ecc->read_subpage)
+ ecc->read_subpage = nand_read_subpage;
+ if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
+ ecc->write_subpage = nand_write_subpage_hwecc;
+ fallthrough;
- if (mtd->writesize >= ecc->size) {
- if (!ecc->strength) {
- WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
+ case NAND_ECC_PLACEMENT_INTERLEAVED:
+ if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
+ (!ecc->read_page ||
+ ecc->read_page == nand_read_page_hwecc ||
+ !ecc->write_page ||
+ ecc->write_page == nand_write_page_hwecc)) {
+ WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
ret = -EINVAL;
goto err_nand_manuf_cleanup;
}
+ /* Use standard syndrome read/write page function? */
+ if (!ecc->read_page)
+ ecc->read_page = nand_read_page_syndrome;
+ if (!ecc->write_page)
+ ecc->write_page = nand_write_page_syndrome;
+ if (!ecc->read_page_raw)
+ ecc->read_page_raw = nand_read_page_raw_syndrome;
+ if (!ecc->write_page_raw)
+ ecc->write_page_raw = nand_write_page_raw_syndrome;
+ if (!ecc->read_oob)
+ ecc->read_oob = nand_read_oob_syndrome;
+ if (!ecc->write_oob)
+ ecc->write_oob = nand_write_oob_syndrome;
+
+ if (mtd->writesize >= ecc->size) {
+ if (!ecc->strength) {
+ WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
+ ret = -EINVAL;
+ goto err_nand_manuf_cleanup;
+ }
+ break;
+ }
+ pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
+ ecc->size, mtd->writesize);
+ ecc->mode = NAND_ECC_SOFT;
+ ecc->algo = NAND_ECC_HAMMING;
break;
+
+ default:
+ pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
+ ecc->placement);
+ ret = -EINVAL;
+ goto err_nand_manuf_cleanup;
}
- pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
- ecc->size, mtd->writesize);
- ecc->mode = NAND_ECC_SOFT;
- ecc->algo = NAND_ECC_HAMMING;
fallthrough;
+
case NAND_ECC_SOFT:
ret = nand_set_ecc_soft_ops(chip);
if (ret) {
diff --git a/drivers/mtd/nand/raw/r852.c b/drivers/mtd/nand/raw/r852.c
index 77774250fb11..764715bae6a6 100644
--- a/drivers/mtd/nand/raw/r852.c
+++ b/drivers/mtd/nand/raw/r852.c
@@ -857,7 +857,8 @@ static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
chip->legacy.write_buf = r852_write_buf;
/* ecc */
- chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
chip->ecc.size = R852_DMA_LEN;
chip->ecc.bytes = SM_OOB_SIZE;
chip->ecc.strength = 2;
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index dc1b38fccfcf..59021ceb9b00 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -323,6 +323,7 @@ static const struct nand_ecc_caps __name = { \
/**
* struct nand_ecc_ctrl - Control structure for ECC
* @mode: ECC mode
+ * @placement: OOB bytes placement
* @algo: ECC algorithm
* @steps: number of ECC steps per page
* @size: data bytes per ECC step
@@ -350,7 +351,7 @@ static const struct nand_ecc_caps __name = { \
* controller and always return contiguous in-band and
* out-of-band data even if they're not stored
* contiguously on the NAND chip (e.g.
- * NAND_ECC_HW_SYNDROME interleaves in-band and
+ * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
* out-of-band data).
* @write_page_raw: function to write a raw page without ECC. This function
* should hide the specific layout used by the ECC
@@ -358,7 +359,7 @@ static const struct nand_ecc_caps __name = { \
* in-band and out-of-band data. ECC controller is
* responsible for doing the appropriate transformations
* to adapt to its specific layout (e.g.
- * NAND_ECC_HW_SYNDROME interleaves in-band and
+ * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
* out-of-band data).
* @read_page: function to read a page according to the ECC generator
* requirements; returns maximum number of bitflips corrected in
@@ -375,6 +376,7 @@ static const struct nand_ecc_caps __name = { \
*/
struct nand_ecc_ctrl {
enum nand_ecc_mode mode;
+ enum nand_ecc_placement placement;
enum nand_ecc_algo algo;
int steps;
int size;
diff --git a/include/linux/platform_data/mtd-davinci.h b/include/linux/platform_data/mtd-davinci.h
index 03e92c71b3fa..3383101c233b 100644
--- a/include/linux/platform_data/mtd-davinci.h
+++ b/include/linux/platform_data/mtd-davinci.h
@@ -69,6 +69,7 @@ struct davinci_nand_pdata { /* platform_data */
* using it with large page chips.
*/
enum nand_ecc_mode ecc_mode;
+ enum nand_ecc_placement ecc_placement;
u8 ecc_bits;
/* e.g. NAND_BUSWIDTH_16 */
--
2.20.1
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^ permalink raw reply related
* [PATCH v5 07/21] mtd: rawnand: Create a new enumeration to describe OOB placement
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
There is currently a confusion between the ECC type/mode/provider
(eg. hardware, software, on-die or none) and the ECC bytes placement.
Create a new enumeration to describe this placement.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/raw/nand_base.c | 4 ++++
include/linux/mtd/rawnand.h | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c407fd15ad46..b84fb5e6ecbe 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4967,6 +4967,10 @@ static const char * const nand_ecc_modes[] = {
[NAND_ECC_ON_DIE] = "on-die",
};
+static const char * const nand_ecc_placement[] = {
+ [NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved",
+};
+
static int of_get_nand_ecc_mode(struct device_node *np)
{
const char *pm;
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 4e0c75b1abc2..dc1b38fccfcf 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -92,6 +92,18 @@ enum nand_ecc_mode {
NAND_ECC_ON_DIE,
};
+/**
+ * enum nand_ecc_placement - NAND ECC placement
+ * @NAND_ECC_PLACEMENT_FREE: The driver can decide where to put ECC bytes.
+ * Default behavior is to put them at the end of the
+ * OOB area.
+ * @NAND_ECC_PLACEMENT_INTERLEAVED: Syndrome layout: interleave data and OOB.
+ */
+enum nand_ecc_placement {
+ NAND_ECC_PLACEMENT_FREE,
+ NAND_ECC_PLACEMENT_INTERLEAVED,
+};
+
enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
--
2.20.1
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* [PATCH v5 06/21] mtd: rawnand: Add an invalid ECC mode to discriminate with valid ones
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
Boris Brezillon, linux-mtd, Thomas Petazzoni, Miquel Raynal,
Mason Yang, Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
NAND ECC modes (or providers) have their own enumeration but, unlike
their algorithms counterpart, there is no invalid or uninitialized
value to discriminate between an error and having chosen a no-ECC
situation. Add an "invalid" entry for this purpose.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
---
drivers/mtd/nand/raw/nand_base.c | 2 +-
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index e4296b67adbc..c407fd15ad46 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4976,7 +4976,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
if (err < 0)
return err;
- for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
+ for (i = NAND_ECC_NONE; i < ARRAY_SIZE(nand_ecc_modes); i++)
if (!strcasecmp(pm, nand_ecc_modes[i]))
return i;
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index bc7c7d9adae9..4e0c75b1abc2 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -84,6 +84,7 @@ struct nand_chip;
* Constants for ECC_MODES
*/
enum nand_ecc_mode {
+ NAND_ECC_INVALID,
NAND_ECC_NONE,
NAND_ECC_SOFT,
NAND_ECC_HW,
--
2.20.1
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* [PATCH v5 05/21] mtd: rawnand: Return an enum from of_get_nand_ecc_algo()
From: Miquel Raynal @ 2020-05-14 17:16 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus
Cc: Tudor Ambarus, Julien Su, Schrempf Frieder, Paul Cercueil,
linux-mtd, Thomas Petazzoni, Miquel Raynal, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200514171651.24851-1-miquel.raynal@bootlin.com>
There is an enumeration to list ECC algorithm, let's use it instead of
returning an int.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/raw/nand_base.c | 35 +++++++++++++++++---------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index deb8c21a3cf1..e4296b67adbc 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4997,17 +4997,20 @@ static const char * const nand_ecc_algos[] = {
[NAND_ECC_RS] = "rs",
};
-static int of_get_nand_ecc_algo(struct device_node *np)
+static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
{
+ enum nand_ecc_algo ecc_algo;
const char *pm;
- int err, i;
+ int err;
err = of_property_read_string(np, "nand-ecc-algo", &pm);
if (!err) {
- for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
- if (!strcasecmp(pm, nand_ecc_algos[i]))
- return i;
- return -ENODEV;
+ for (ecc_algo = NAND_ECC_HAMMING;
+ ecc_algo < ARRAY_SIZE(nand_ecc_algos);
+ ecc_algo++) {
+ if (!strcasecmp(pm, nand_ecc_algos[ecc_algo]))
+ return ecc_algo;
+ }
}
/*
@@ -5015,15 +5018,14 @@ static int of_get_nand_ecc_algo(struct device_node *np)
* for some obsoleted values that were specifying ECC algorithm.
*/
err = of_property_read_string(np, "nand-ecc-mode", &pm);
- if (err < 0)
- return err;
+ if (!err) {
+ if (!strcasecmp(pm, "soft"))
+ return NAND_ECC_HAMMING;
+ else if (!strcasecmp(pm, "soft_bch"))
+ return NAND_ECC_BCH;
+ }
- if (!strcasecmp(pm, "soft"))
- return NAND_ECC_HAMMING;
- else if (!strcasecmp(pm, "soft_bch"))
- return NAND_ECC_BCH;
-
- return -ENODEV;
+ return NAND_ECC_UNKNOWN;
}
static int of_get_nand_ecc_step_size(struct device_node *np)
@@ -5068,7 +5070,8 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np)
static int nand_dt_init(struct nand_chip *chip)
{
struct device_node *dn = nand_get_flash_node(chip);
- int ecc_mode, ecc_algo, ecc_strength, ecc_step;
+ enum nand_ecc_algo ecc_algo;
+ int ecc_mode, ecc_strength, ecc_step;
if (!dn)
return 0;
@@ -5090,7 +5093,7 @@ static int nand_dt_init(struct nand_chip *chip)
if (ecc_mode >= 0)
chip->ecc.mode = ecc_mode;
- if (ecc_algo >= 0)
+ if (ecc_algo != NAND_ECC_UNKNOWN)
chip->ecc.algo = ecc_algo;
if (ecc_strength >= 0)
--
2.20.1
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