* Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
From: Robin Murphy @ 2020-05-15 15:30 UTC (permalink / raw)
To: Lars Povlsen, Marc Zyngier
Cc: devicetree, Alexandre Belloni, Arnd Bergmann, Stephen Boyd,
Linus Walleij, linux-kernel, Microchip Linux Driver Support,
linux-gpio, SoC Team, Michael Turquette, Olof Johansson,
Steen Hegelund, linux-clk, linux-arm-kernel
In-Reply-To: <871rnlp740.fsf@soft-dev15.microsemi.net>
On 2020-05-15 16:09, Lars Povlsen wrote:
[...]
>>> + cpu0: cpu@0 {
>>> + compatible = "arm,cortex-a53", "arm,armv8";
Side note: only one compatible string for the real CPU please, running a
DT bindings check should complain about that.
>>> + device_type = "cpu";
>>> + reg = <0x0 0x0>;
>>> + enable-method = "spin-table";
>>
>> Really? This is 2020, not 2012 any more. Surely a new platform
>> boots using PSCI, and not *this*.
>>
>
> We don't currently support PSCI. The platform does not have TrustZone,
> hence we don't use ATF.
AIUI, part of the purpose of ATF is to provide a nice standardised
platform interface regardless of whether you care about Secure software
or not. It shouldn't take much to knock up a trivial ATF port that just
uses an internal spin-table for its PSCI backend - in fact I suspect
that's probably just a copy-paste from the RPi3 port ;)
Robin.
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* Re: [PATCH] arm64: dts: mt8173: fix vcodec-enc clock
From: Matthias Brugger @ 2020-05-15 15:28 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: gtk_ruiwang, devicetree, Yunfei Dong, linux-kernel, Rob Herring,
linux-mediatek, Qianqian Yan
In-Reply-To: <20200504124442.208004-1-hsinyi@chromium.org>
On 04/05/2020 14:44, Hsin-Yi Wang wrote:
> Fix the assigned-clock-parents to higher frequency clock to avoid h264
> encode timeout:
>
> [ 134.763465] mtk_vpu 10020000.vpu: vpu ipi 4 ack time out !
> [ 134.769008] [MTK_VCODEC][ERROR][18]: vpu_enc_send_msg() vpu_ipi_send msg_id c002 len 32 fail -5
> [ 134.777707] [MTK_VCODEC][ERROR][18]: vpu_enc_encode() AP_IPIMSG_ENC_ENCODE 0 fail
>
> venc_sel is the clock used by h264 encoder, and venclt_sel is the clock
> used by vp8 encoder. Assign venc_sel to vcodecpll_ck and venclt_sel to
> vcodecpll_370p5.
>
> vcodecpll 1482000000
> vcodecpll_ck 494000000
> venc_sel 494000000
> ...
> vcodecpll_370p5 370500000
> venclt_sel 370500000
>
> Fixes: fbbad0287cec ("arm64: dts: Using standard CCF interface to set vcodec clk")
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Applied to v5.7-fixes
Thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index a212bf124e81..d0e9a2aada2e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1422,8 +1422,8 @@ vcodec_enc: vcodec@18002000 {
> "venc_lt_sel";
> assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
> <&topckgen CLK_TOP_VENC_LT_SEL>;
> - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
> - <&topckgen CLK_TOP_UNIVPLL1_D2>;
> + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
> + <&topckgen CLK_TOP_VCODECPLL_370P5>;
> };
>
> jpegdec: jpegdec@18004000 {
>
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* [PATCH] arm64: kvm: Fix incorrect comment on kvm_get_hyp_vector()
From: David Brazdil @ 2020-05-15 15:25 UTC (permalink / raw)
To: Marc Zyngier; +Cc: David Brazdil, kvmarm, linux-arm-kernel, linux-kernel
The comment used to say that kvm_get_hyp_vector is only called on VHE systems.
In fact, it is also called from the nVHE init function cpu_init_hyp_mode().
Fix the comment to stop confusing devs.
Signed-off-by: David Brazdil <dbrazdil@google.com>
---
arch/arm64/include/asm/kvm_mmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 30b0e8d6b895..796f6a2e794a 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -473,7 +473,7 @@ static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
extern void *__kvm_bp_vect_base;
extern int __kvm_harden_el2_vector_slot;
-/* This is only called on a VHE system */
+/* This is called on both VHE and !VHE systems */
static inline void *kvm_get_hyp_vector(void)
{
struct bp_hardening_data *data = arm64_get_bp_hardening_data();
--
2.26.2
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* Re: [Linux-stm32] [PATCH v7 5/6] clocksource: Add Low Power STM32 timers driver
From: Daniel Lezcano @ 2020-05-15 15:25 UTC (permalink / raw)
To: Benjamin GAIGNARD, Fabrice GASNIER, lee.jones@linaro.org,
robh+dt@kernel.org, mark.rutland@arm.com,
mcoquelin.stm32@gmail.com, Alexandre TORGUE, tglx@linutronix.de
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Pascal PAILLET-LME, Benjamin Gaignard,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <bbac5aa5-1c95-456e-3141-006d4fa86095@st.com>
Hi Benjamin,
On 05/05/2020 09:26, Benjamin GAIGNARD wrote:
>
>
> On 4/20/20 2:16 PM, Benjamin Gaignard wrote:
>> From: Benjamin Gaignard <benjamin.gaignard@linaro.org>
>>
>> Implement clock event driver using low power STM32 timers.
>> Low power timer counters running even when CPUs are stopped.
>> It could be used as clock event broadcaster to wake up CPUs but not like
>> a clocksource because each it rise an interrupt the counter restart from 0.
>>
>> Low power timers have a 16 bits counter and a prescaler which allow to
>> divide the clock per power of 2 to up 128 to target a 32KHz rate.
> Gentle ping to reviewers on this driver part of the series.
> The bindings and the MFD have been reviewed so I hope I can progress
> on the driver part too.
[ ... ]
sorry for the delay.
How do you want these patches to be merged?
Shall I pick patch 6/7 ?
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
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* Re: [PATCH] ARM: dts: at91: Configure I2C SCL gpio as open drain
From: Codrin.Ciubotariu @ 2020-05-15 15:24 UTC (permalink / raw)
To: alexandre.belloni
Cc: devicetree, linux-kernel, Ludovic.Desroches, robh+dt,
linux-arm-kernel
In-Reply-To: <20200515145849.GV34497@piout.net>
On 15.05.2020 17:58, Alexandre Belloni wrote:
> On 15/05/2020 17:00:01+0300, Codrin Ciubotariu wrote:
>> The SCL gpio pin used by I2C bus for recovery needs to be configured as
>> open drain.
>>
>> Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl")
>> Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl")
>> Fixes: 8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl")
>> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
>> ---
>> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++---
>> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 6 +++---
>> arch/arm/boot/dts/sama5d3.dtsi | 6 +++---
>> arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
>> 4 files changed, 12 insertions(+), 12 deletions(-)
>>
>
> Applied, thanks. There was a small conflict in the sama5d2 board dts,
> please check.
It is ok, with the exception that it should also be added for the
scl-gpios property from the i2c2 node. I am making a patch.
>
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>
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* Re: [PATCH] arm64: vdso: Fix CFI info in sigreturn.
From: Mark Rutland @ 2020-05-15 15:23 UTC (permalink / raw)
To: Daniel Kiss
Cc: Tamas Zsoldos, Vincenzo Frascino,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <DDD18BB4-B773-4471-B5E0-9DDD839B7D46@arm.com>
Hi Daniel,
On Fri, May 08, 2020 at 09:52:14AM +0000, Daniel Kiss wrote:
> [PATCH] arm64: vdso: Fix CFI info in sigreturn.
>
> When the signal handler is called the registers set up as the return address
> points to the __kernel_rt_sigreturn. The NOP here is the placeholder of the
> branch and link instruction that "calls" the signal handler. In case of a
> return address the unwinder identifies the location of the caller because
> in some cases the return address might not exist. Since the .cfi_startproc
> is after the NOP, it won't be associated with any location and the
> unwinder will stop walking.
> This change corrects the generated EHFrames only.
> Signed-off-by: Daniel Kiss <daniel.kiss@arm.com(opens in new tab)>
> Signed-off-by: Tamas Zsoldos <tamas.zsoldos@arm.com(opens in new tab)>
Something appears to have gone wrong here; was this copy-pasted from
somewhere?
> ---
> arch/arm64/kernel/vdso/sigreturn.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> diff --git a/arch/arm64/kernel/vdso/sigreturn.S b/arch/arm64/kernel/vdso/sigreturn.S
> index 12324863d5c2..5d50ee92faa4 100644
> --- a/arch/arm64/kernel/vdso/sigreturn.S
> +++ b/arch/arm64/kernel/vdso/sigreturn.S
> @@ -13,13 +13,13 @@
> .text
> - nop
> -SYM_FUNC_START(__kernel_rt_sigreturn)
> .cfi_startproc
> .cfi_signal_frame
> .cfi_def_cfa x29, 0
> .cfi_offset x29, 0 * 8
> .cfi_offset x30, 1 * 8
> + nop /* placeholder for bl signalhandler */
> +SYM_FUNC_START(__kernel_rt_sigreturn)
> mov x8, #__NR_rt_sigreturn
> svc #0
> .cfi_endproc
This appears to have been whitespace damaged (leading tabs have gone).
Can you please resend this via git-send-email?
Thanks,
Mark.
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* [PATCH] arm64: kvm: Clean up cpu_init_hyp_mode()
From: David Brazdil @ 2020-05-15 15:20 UTC (permalink / raw)
To: Marc Zyngier; +Cc: David Brazdil, kvmarm, linux-arm-kernel, linux-kernel
Pull bits of code to the only place where it is used. Remove empty function
__cpu_init_stage2(). Remove redundant has_vhe() check since this function is
nVHE-only. No functional changes intended.
Signed-off-by: David Brazdil <dbrazdil@google.com>
---
arch/arm64/include/asm/kvm_asm.h | 2 ++
arch/arm64/include/asm/kvm_host.h | 35 -------------------------------
arch/arm64/kvm/arm.c | 32 +++++++++++++++++++++++-----
3 files changed, 29 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 59e314f38e43..0c9b5fc4ba0a 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -70,6 +70,8 @@ extern int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu);
extern int __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu);
+extern void __kvm_enable_ssbs(void);
+
extern u64 __vgic_v3_get_ich_vtr_el2(void);
extern u64 __vgic_v3_read_vmcr(void);
extern void __vgic_v3_write_vmcr(u32 vmcr);
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index a723f84fab83..69a338a390a6 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -533,39 +533,6 @@ static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr();
}
-void __kvm_enable_ssbs(void);
-
-static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
- unsigned long hyp_stack_ptr,
- unsigned long vector_ptr)
-{
- /*
- * Calculate the raw per-cpu offset without a translation from the
- * kernel's mapping to the linear mapping, and store it in tpidr_el2
- * so that we can use adr_l to access per-cpu variables in EL2.
- */
- u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_data) -
- (u64)kvm_ksym_ref(kvm_host_data));
-
- /*
- * Call initialization code, and switch to the full blown HYP code.
- * If the cpucaps haven't been finalized yet, something has gone very
- * wrong, and hyp will crash and burn when it uses any
- * cpus_have_const_cap() wrapper.
- */
- BUG_ON(!system_capabilities_finalized());
- __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
-
- /*
- * Disabling SSBD on a non-VHE system requires us to enable SSBS
- * at EL2.
- */
- if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
- arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
- kvm_call_hyp(__kvm_enable_ssbs);
- }
-}
-
static inline bool kvm_arch_requires_vhe(void)
{
/*
@@ -601,8 +568,6 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
struct kvm_device_attr *attr);
-static inline void __cpu_init_stage2(void) {}
-
/* Guest/host FPSIMD coordination helpers */
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index e01d44df98df..b0b569f2cdd0 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1273,19 +1273,41 @@ static void cpu_init_hyp_mode(void)
{
phys_addr_t pgd_ptr;
unsigned long hyp_stack_ptr;
- unsigned long stack_page;
unsigned long vector_ptr;
+ unsigned long tpidr_el2;
/* Switch from the HYP stub to our own HYP init vector */
__hyp_set_vectors(kvm_get_idmap_vector());
+ /*
+ * Calculate the raw per-cpu offset without a translation from the
+ * kernel's mapping to the linear mapping, and store it in tpidr_el2
+ * so that we can use adr_l to access per-cpu variables in EL2.
+ */
+ tpidr_el2 = ((unsigned long)this_cpu_ptr(&kvm_host_data) -
+ (unsigned long)kvm_ksym_ref(kvm_host_data));
+
pgd_ptr = kvm_mmu_get_httbr();
- stack_page = __this_cpu_read(kvm_arm_hyp_stack_page);
- hyp_stack_ptr = stack_page + PAGE_SIZE;
+ hyp_stack_ptr = __this_cpu_read(kvm_arm_hyp_stack_page) + PAGE_SIZE;
vector_ptr = (unsigned long)kvm_get_hyp_vector();
- __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
- __cpu_init_stage2();
+ /*
+ * Call initialization code, and switch to the full blown HYP code.
+ * If the cpucaps haven't been finalized yet, something has gone very
+ * wrong, and hyp will crash and burn when it uses any
+ * cpus_have_const_cap() wrapper.
+ */
+ BUG_ON(!system_capabilities_finalized());
+ __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
+
+ /*
+ * Disabling SSBD on a non-VHE system requires us to enable SSBS
+ * at EL2.
+ */
+ if (this_cpu_has_cap(ARM64_SSBS) &&
+ arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
+ kvm_call_hyp(__kvm_enable_ssbs);
+ }
}
static void cpu_hyp_reset(void)
--
2.26.2
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* Re: [PATCH v2 2/3] ARM: mediatek: Replace <linux/clk-provider.h> by <linux/of_clk.h>
From: Matthias Brugger @ 2020-05-15 15:20 UTC (permalink / raw)
To: Geert Uytterhoeven, soc
Cc: Arnd Bergmann, Kevin Hilman, linux-kernel, Lubomir Rintel,
linux-mediatek, Olof Johansson, linux-arm-kernel
In-Reply-To: <20200505154536.4099-3-geert+renesas@glider.be>
On 05/05/2020 17:45, Geert Uytterhoeven wrote:
> The Mediatek platform code is not a clock provider, and just needs to
> call of_clk_init().
>
> Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
applied to v5.7-next/soc
Thanks!
> ---
> v2:
> - Add Reviewed-by.
> ---
> arch/arm/mach-mediatek/mediatek.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
> index f6f102fa9e23a0f8..e6e9f93a1f01c7d0 100644
> --- a/arch/arm/mach-mediatek/mediatek.c
> +++ b/arch/arm/mach-mediatek/mediatek.c
> @@ -9,7 +9,7 @@
> #include <linux/io.h>
> #include <asm/mach/arch.h>
> #include <linux/of.h>
> -#include <linux/clk-provider.h>
> +#include <linux/of_clk.h>
> #include <linux/clocksource.h>
>
>
>
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* Re: [PATCH v3 4/4] serial: 8250_dw: Fix common clocks usage race condition
From: Serge Semin @ 2020-05-15 15:19 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Maxime Ripard, Kefeng Wang, Thomas Bogendoerfer, Catalin Marinas,
Arnd Bergmann, Paul Burton, Greg Kroah-Hartman, linux-kernel,
Russell King, Serge Semin, Alexey Malahov, Long Cheng,
linux-mediatek, Ralf Baechle, linux-serial, Jiri Slaby,
Heikki Krogerus, linux-mips, Will Deacon, linux-arm-kernel
In-Reply-To: <20200515141046.GF1634618@smile.fi.intel.com>
On Fri, May 15, 2020 at 05:10:46PM +0300, Andy Shevchenko wrote:
> On Thu, May 07, 2020 at 02:31:35AM +0300, Serge Semin wrote:
> > The race condition may happen if the UART reference clock is shared with
> > some other device (on Baikal-T1 SoC it's another DW UART port). In this
> > case if that device changes the clock rate while serial console is using
> > it the DW 8250 UART port might not only end up with an invalid uartclk
> > value saved, but may also experience a distorted output data since
> > baud-clock could have been changed. In order to fix this lets at least
> > try to adjust the 8250 port setting like UART clock rate in case if the
> > reference clock rate change is discovered. The driver will call the new
> > method to update 8250 UART port clock rate settings. It's done by means of
> > the clock event notifier registered at the port startup and unregistered
> > in the shutdown callback method.
>
> I'm wondering if clock framework itself can provide such a notifier?
>
> > Note 1. In order to avoid deadlocks we had to execute the UART port update
> > method in a dedicated deferred work. This is due to (in my opinion
> > redundant) the clock update implemented in the dw8250_set_termios()
> > method.
>
> So, and how you propose to update the clock when ->set_termios() is called?
First of all If you are worried about the current implementation, please don't,
it still updates the clock in set_termios (please see the set_termios
code). The method hasn't changed much and does the updating the same way it did
before.
Secondly, 8250 driver should be using the same reference clock as it is
pre-defined by the platform with no change. The baud rate updates are supposed to
be performed by the divider embedded into the 8250 controller, otherwise the
divisor functionality is left completely unused. If a platform engineer needs to
speed the uart up, the ref clock rate can be tuned by for instance the
"assigned-clock-rates" property.
>
> > Note 2. Before the ref clock is manually changed by the custom
> > set_termios() function we swap the port uartclk value with new rate
> > adjusted to be suitable for the requested baud. It is necessary in
> > order to effectively disable a functionality of the ref clock events
> > handler for the current UART port, since uartclk update will be done
> > a bit further in the generic serial8250_do_set_termios() function.
>
> ...
>
> > + struct notifier_block clk_notifier;
> > + struct work_struct clk_work;
>
> Oh, this seems too much.
> Perhaps, the compatible based quirk with your initial approach is much better for time being.
It's already in 8250_dw, useful not for a single platform and won't hurt any
other one. So I'll leave it here and wait for the Greg feedback.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
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* Re: [PATCH v3 16/20] arm64: dts: juno: Fix GPU interrupt order
From: André Przywara @ 2020-05-15 15:13 UTC (permalink / raw)
To: Sudeep Holla
Cc: Mark Rutland, Rob Herring, Lorenzo Pieralisi, devicetree,
Liviu Dudau, linux-arm-kernel
In-Reply-To: <20200513182405.GE27686@bogus>
On 13/05/2020 19:24, Sudeep Holla wrote:
Hi,
> On Wed, May 13, 2020 at 11:30:12AM +0100, Andre Przywara wrote:
>> The Mali binding insists on the GPU interrupts to be in ordered as: job,
>> mmu, gpu.
>> Sort the GPU interrupts and interrupt-names properties accordingly.
>>
>
> I assume this is not a bug fix, just clean up to make it 100% binding
> compliant. Things work just fine without this too. Just for my info.
Yes, that's true, it works either way right now.
Originally I was under the impression that the purpose of
interrupt-names was to allow any order of interrupts, but according to
Rob this is just to support optional IRQs (so having a shorter list).
The bindings require a certain order, and the dt-schema validation
complains if that differs in the DT.
Cheers,
Andre
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^ permalink raw reply
* Re: [PATCH v3 08/20] arm64: dts: arm: model: Fix GIC compatible names
From: André Przywara @ 2020-05-15 15:10 UTC (permalink / raw)
To: Sudeep Holla
Cc: Mark Rutland, Rob Herring, Lorenzo Pieralisi, devicetree,
Marc Zyngier, Liviu Dudau, linux-arm-kernel
In-Reply-To: <20200513182144.GD27686@bogus>
On 13/05/2020 19:21, Sudeep Holla wrote:
> On Wed, May 13, 2020 at 11:30:04AM +0100, Andre Przywara wrote:
>> The GIC DT binding only allows certain combinations of DT compatible
>> strings. The somewhat awkward "arm,cortex-a15-gic", "arm,cortex-a9-gic"
>> is not among those.
>>
>> Drop that combination of different "cortex" based strings used for the
>> models, and replace it with the more useful combination including
>> "arm,gic-400".
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi | 2 +-
>> arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> index 15fe81738e94..f17e744163a5 100644
>> --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> @@ -6,7 +6,7 @@
>>
>> / {
>> gic: interrupt-controller@2c001000 {
>> - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>
> Do we need to still retain "arm,cortex-a15-gic" ?
I'd rather would like to keep that. "arm,gic-400" was introduced only
later into Linux as a compatible string, so dropping this would break
older kernels. I don't see any difference between a9-gic and a15-gic in
term of kernel support, so a9-gic can surely go.
Cheers,
Andre
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^ permalink raw reply
* Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
From: Lars Povlsen @ 2020-05-15 15:09 UTC (permalink / raw)
To: Marc Zyngier
Cc: devicetree, Alexandre Belloni, Arnd Bergmann, Stephen Boyd,
Linus Walleij, linux-kernel, linux-clk, linux-gpio, SoC Team,
Michael Turquette, linux-arm-kernel, Olof Johansson,
Microchip Linux Driver Support, Steen Hegelund, Lars Povlsen
In-Reply-To: <2d230dab95ee96727a42f9c242c93c18@misterjones.org>
Marc Zyngier writes:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 2020-05-13 13:55, Lars Povlsen wrote:
>> This adds the basic DT structure for the Microchip Sparx5 SoC, and the
>> reference boards, pcb125, pcb134 and pcb135. The two latter have a
>> NAND vs a eMMC centric variant (as a mount option),
>>
>> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
>> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>> ---
>> MAINTAINERS | 1 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/microchip/Makefile | 4 +
>> arch/arm64/boot/dts/microchip/sparx5.dtsi | 135 ++++++++++++++++++
>> .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++
>> .../dts/microchip/sparx5_pcb134_board.dtsi | 15 ++
>> .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++
>> .../dts/microchip/sparx5_pcb135_board.dtsi | 15 ++
>> .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++
>> 12 files changed, 271 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/microchip/Makefile
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1b5a18d3dbb9f..5aa28d6e39d4f 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2084,6 +2084,7 @@ M: Lars Povlsen <lars.povlsen@microchip.com>
>> M: Steen Hegelund <Steen.Hegelund@microchip.com>
>> M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
>> L: linux-arm-kernel@lists.infradead.org (moderated for
>> non-subscribers)
>> +F: arch/arm64/boot/dts/microchip/
>> N: sparx5
>> S: Supported
>>
>> diff --git a/arch/arm64/boot/dts/Makefile
>> b/arch/arm64/boot/dts/Makefile
>> index f19b762c008d8..9680a7f20c307 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -17,6 +17,7 @@ subdir-y += intel
>> subdir-y += lg
>> subdir-y += marvell
>> subdir-y += mediatek
>> +subdir-y += microchip
>> subdir-y += nvidia
>> subdir-y += qcom
>> subdir-y += realtek
>> diff --git a/arch/arm64/boot/dts/microchip/Makefile
>> b/arch/arm64/boot/dts/microchip/Makefile
>> new file mode 100644
>> index 0000000000000..c6e0313eea0f9
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/microchip/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
>> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> new file mode 100644
>> index 0000000000000..3136b4369f507
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> @@ -0,0 +1,135 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + compatible = "microchip,sparx5";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + };
>> + };
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0x0 0x0>;
>> + enable-method = "spin-table";
>
> Really? This is 2020, not 2012 any more. Surely a new platform
> boots using PSCI, and not *this*.
>
We don't currently support PSCI. The platform does not have TrustZone,
hence we don't use ATF.
We use U-Boot as the (only) bootloader, providing the spintable. I looked
at adding PSCI (in U-Boot) initially, but as most other platforms were
using ATF the PSCI support was buggy and caused me to go for spintable.
Is spintable being deprecated?
>> + cpu-release-addr = <0x0 0x0000fff8>;
>> + next-level-cache = <&L2_0>;
>> + };
>> + cpu1: cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0x0 0x1>;
>> + enable-method = "spin-table";
>> + cpu-release-addr = <0x0 0x0000fff8>;
>> + next-level-cache = <&L2_0>;
>> + };
>> + L2_0: l2-cache0 {
>> + compatible = "cache";
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts =
>> + <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>
> You have a GICv3. These interrupt specifiers are not the ones GICv3
> expects.
I'll go back and look at this.
>
>> + };
>> +
>> + clocks: clocks {
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges;
>> + ahb_clk: ahb-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <250000000>;
>> + };
>> + sys_clk: sys-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <625000000>;
>> + };
>> + };
>> +
>> + axi: axi@600000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + gic: interrupt-controller@600300000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-controller;
>> + reg = <0x6 0x00300000 0x20000>, /* GICD */
>> + <0x6 0x00340000 0x1000000>; /* GICR */
>
> You are missing the GICv3 compatibility interfaces (GICV/GICH), which
> are implemented by the CPUs.
I'll get these sorted out.
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + uart0: serial@600100000 {
>> + compatible = "ns16550a";
>> + reg = <0x6 0x00100000 0x20>;
>> + clocks = <&ahb_clk>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@600102000 {
>> + compatible = "ns16550a";
>> + reg = <0x6 0x00102000 0x20>;
>> + clocks = <&ahb_clk>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + timer1: timer@600105000 {
>> + compatible = "snps,dw-apb-timer";
>> + reg = <0x6 0x00105000 0x1000>;
>> + clocks = <&ahb_clk>;
>> + clock-names = "timer";
>> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + };
>> +};
>
> Where is the PMU node?
>
I'll add the PMU node.
Thank you for your comments!
> Thanks,
>
> M.
--
Lars Povlsen,
Microchip
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* Re: [PATCH] coresight: etm4x: Add support to disable trace unit power up
From: Sai Prakash Ranjan @ 2020-05-15 15:07 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Suzuki K Poulose, linux-arm-msm, Coresight ML,
Linux Kernel Mailing List, Stephen Boyd, Tingwei Zhang, Leo Yan,
linux-arm-kernel, Mike Leach
In-Reply-To: <CANLsYkxun2EWGeLU42ShbqkJMtCTh+Q9L3t=CXQR+-2zVuuJYg@mail.gmail.com>
Hi Mathieu,
On 2020-05-15 20:22, Mathieu Poirier wrote:
> On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
> <saiprakash.ranjan@codeaurora.org> wrote:
>>
>> Hi Mathieu,
>>
>> On 2020-05-14 23:30, Mathieu Poirier wrote:
>> > Good morning Sai,
>> >
>> > On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
>> >> From: Tingwei Zhang <tingwei@codeaurora.org>
>> >>
>> >> On some Qualcomm Technologies Inc. SoCs like SC7180, there
>> >> exists a hardware errata where the APSS (Application Processor
>> >> SubSystem)/CPU watchdog counter is stopped when ETM register
>> >> TRCPDCR.PU=1.
>> >
>> > Fun stuff...
>> >
>>
>> Yes :)
>>
>> >> Since the ETMs share the same power domain as
>> >> that of respective CPU cores, they are powered on when the
>> >> CPU core is powered on. So we can disable powering up of the
>> >> trace unit after checking for this errata via new property
>> >> called "qcom,tupwr-disable".
>> >>
>> >> Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
>> >> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> >
>> > Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> > Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
>> >
>>
>> Tingwei is the author, so if I understand correctly, his signed-off-by
>> should appear first, am I wrong?
>
> It's a gray area and depends on who's code is more prevalent in the
> patch. If Tingwei wrote the most of the code then his name is in the
> "from:" section, yours as co-developer and he signs off on it (as I
> suggested). If you did most of the work then it is the opposite.
> Adding a Co-developed and a signed-off with the same name doesn't make
> sense.
>
I did check the documentation for submitting patches:
Documentation/process/submitting-patches.rst. And it clearly states
that "Co-developed-by must be followed by Signed-off by the co-author
and the last Signed-off-by: must always be that of the developer
submitting the patch".
Quoting below from the doc:
Co-developed-by: <snip> ...Since
Co-developed-by: denotes authorship, every Co-developed-by: must be
immediately
followed by a Signed-off-by: of the associated co-author. Standard
sign-off
procedure applies, i.e. the ordering of Signed-off-by: tags should
reflect the
chronological history of the patch insofar as possible, regardless of
whether
the author is attributed via From: or Co-developed-by:. Notably, the
last
Signed-off-by: must always be that of the developer submitting the
patch.
>>
>> >> ---
>> >> .../devicetree/bindings/arm/coresight.txt | 6 ++++
>> >> drivers/hwtracing/coresight/coresight-etm4x.c | 29
>> >> ++++++++++++-------
>> >
>> > Please split in two patches.
>> >
>>
>> Sure, I will split the dt-binding into separate patch, checkpatch did
>> warn.
>
> And you still sent me the patch... I usually run checkpatch before
> all the submissions I review and flatly ignore patches that return
> errors. You got lucky...
>
I did not mean to ignore it or else I wouldn't have run checkpatch
itself.
I checked other cases like "arm,scatter-gather" where the binding and
the
driver change was in a single patch, hence I thought it's not a very
strict rule.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
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* Re: [PATCH v3 3/4] serial: 8250_dw: Simplify the ref clock rate setting procedure
From: Andy Shevchenko @ 2020-05-15 15:05 UTC (permalink / raw)
To: Serge Semin
Cc: Maxime Ripard, Kefeng Wang, Thomas Bogendoerfer, Catalin Marinas,
Arnd Bergmann, Paul Burton, Greg Kroah-Hartman, linux-kernel,
Russell King, Serge Semin, Alexey Malahov, Long Cheng,
linux-mediatek, Ralf Baechle, linux-serial, Jiri Slaby,
Heikki Krogerus, linux-mips, Will Deacon, linux-arm-kernel
In-Reply-To: <20200515145007.xjrx5mminxrh374d@mobilestation>
On Fri, May 15, 2020 at 05:50:07PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 05:05:47PM +0300, Andy Shevchenko wrote:
> > On Thu, May 07, 2020 at 02:31:34AM +0300, Serge Semin wrote:
> > > Really instead of twice checking the clk_round_rate() return value
> > > we could do it once, and if it isn't error the clock rate can be changed.
> > > By doing so we decrease a number of ret-value tests and remove a weird
> > > goto-based construction implemented in the dw8250_set_termios() method.
> >
> > > rate = clk_round_rate(d->clk, baud * 16);
> > > - if (rate < 0)
> > > - ret = rate;
> >
> > > - else if (rate == 0)
> > > - ret = -ENOENT;
> >
> > This case now handled differently.
> > I don't think it's good idea to change semantics.
> >
> > So, I don't see how this, after leaving the rate==0 case, would be better than
> > original one.
>
> Semantic doesn't change. The code does exactly the same as before. If it didn't
> I either would have provided a comment about this or just didn't introduce the
> change in the first place. I guess you just don't see the whole picture of the
> method. Take a look in the code. The ret variable's been used to skip the
> "p->uartclk = rate" assignment. That's it. So the (rate == 0) will still be
> considered as error condition, which causes the clock rate left unchanged.
> Here is the code diff so you wouldn't need to dive deep into the driver
> sources:
>
> < clk_disable_unprepare(d->clk);
> < rate = clk_round_rate(d->clk, baud * 16);
> < if (rate < 0)
> < ret = rate;
> < else if (rate == 0)
> < ret = -ENOENT;
> < else
> < ret = clk_set_rate(d->clk, rate);
> < clk_prepare_enable(d->clk);
> <
> < if (ret)
> < goto out;
> <
> < p->uartclk = rate;
> <
> <out:
> ---
> > clk_disable_unprepare(d->clk);
> > rate = clk_round_rate(d->clk, baud * 16);
> > if (rate > 0) {
> > ret = clk_set_rate(d->clk, rate);
> > if (!ret)
> > p->uartclk = rate;
> > }
> > clk_prepare_enable(d->clk);
Thanks.
Indeed, in the above it looks clear.
--
With Best Regards,
Andy Shevchenko
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^ permalink raw reply
* Re: [PATCH v1 8/9] arm64: dts: actions: Add MMC controller support for S700
From: André Przywara @ 2020-05-15 15:01 UTC (permalink / raw)
To: Amit Singh Tomar, afaerber, manivannan.sadhasivam, robh+dt
Cc: devicetree, linux-actions, linux-arm-kernel, cristian.ciocaltea
In-Reply-To: <1589472657-3930-9-git-send-email-amittomer25@gmail.com>
On 14/05/2020 17:10, Amit Singh Tomar wrote:
Hi,
> This commits adds support for MMC controllers present on Actions S700 SoC,
> there are 3 MMC controllers in this SoC which can be used for accessing
> SD/EMMC/SDIO cards.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> ---
> Changes since RFC:
> * No change.
> ---
> arch/arm64/boot/dts/actions/s700.dtsi | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
> index 56f2f84812cb..3f1fc3e48415 100644
> --- a/arch/arm64/boot/dts/actions/s700.dtsi
> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
> @@ -258,5 +258,38 @@
> dma-requests = <44>;
> clocks = <&cmu CLK_DMAC>;
> };
> +
> + mmc0: mmc@e0210000 {
> + compatible = "actions,owl-mmc";
I was wondering if we should add a SoC specific compatible here, to be
on the safe side. The BSP driver seems to differentiate between S900 and
S700, although it looks like only to cover some misplaced platform setup.
But if we later find a problem, the DTs stay the same, and the driver
can easily be fixed.
So, using "actions,s700-mmc", "actions,owl-mmc" here, adding this combo
to the binding, but leaving the driver alone for now.
Cheers,
Andre
> + reg = <0x0 0xe0210000 0x0 0x4000>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD0>;
> + resets = <&cmu RESET_SD0>;
> + dmas = <&dma 2>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@e0214000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0214000 0x0 0x4000>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD1>;
> + resets = <&cmu RESET_SD1>;
> + dmas = <&dma 3>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc2: mmc@e0218000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0218000 0x0 0x4000>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD2>;
> + resets = <&cmu RESET_SD2>;
> + dmas = <&dma 4>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> };
> };
>
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^ permalink raw reply
* Re: [PATCH v2 0/7] usb: gadget: udc: atmel: add usb device support for SAM9x60 SoC
From: Alexandre Belloni @ 2020-05-15 15:02 UTC (permalink / raw)
To: cristian.birsan
Cc: mark.rutland, balbi, devicetree, gregkh, linux-usb, linux-kernel,
ludovic.desroches, robh+dt, linux-arm-kernel
In-Reply-To: <20200515111631.31210-1-cristian.birsan@microchip.com>
Hi,
On 15/05/2020 14:16:24+0300, cristian.birsan@microchip.com wrote:
> From: Cristian Birsan <cristian.birsan@microchip.com>
>
> This patch set adds usb device support for SAM9x60 SoC.
> The DPRAM memory for the USB High Speed Device Port (UDPHS) hardware
> block was increased and the allocation method is changed. This patch
> series simplifies the endpoint allocation scheme to acomodate this SoC
> and the old ones.
>
> Changes in v2:
> - drop the patch that adds reference to pmc for sam9x60
> - use dt-bindings: usb prefix
> - enable usb device in device tree
>
> Claudiu Beznea (1):
> usb: gadget: udc: atmel: use of_find_matching_node_and_match
>
> Cristian Birsan (6):
> dt-bindings: usb: atmel: Update DT bindings documentation for sam9x60
> usb: gadget: udc: atmel: simplify endpoint allocation
> usb: gadget: udc: atmel: use 1 bank endpoints for control transfers
> usb: gadget: udc: atmel: rename errata into caps
> usb: gadget: udc: atmel: update endpoint allocation for sam9x60
> ARM: dts: at91: sam9x60ek: enable usb device
This should probably be rebased on top of
https://lore.kernel.org/linux-arm-kernel/20200507155651.1094142-1-gregory.clement@bootlin.com/
so we avoid having to define the endpoints in the device tree in the
first place.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH] ARM: dts: at91: Configure I2C SCL gpio as open drain
From: Alexandre Belloni @ 2020-05-15 14:58 UTC (permalink / raw)
To: Codrin Ciubotariu
Cc: devicetree, linux-kernel, ludovic.desroches, robh+dt,
linux-arm-kernel
In-Reply-To: <20200515140001.287932-1-codrin.ciubotariu@microchip.com>
On 15/05/2020 17:00:01+0300, Codrin Ciubotariu wrote:
> The SCL gpio pin used by I2C bus for recovery needs to be configured as
> open drain.
>
> Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl")
> Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl")
> Fixes: 8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl")
> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
> ---
> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 6 +++---
> arch/arm/boot/dts/sama5d3.dtsi | 6 +++---
> arch/arm/boot/dts/sama5d4.dtsi | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
Applied, thanks. There was a small conflict in the sama5d2 board dts,
please check.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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* [GIT PULL 11/11] arm64: tegra: Device tree changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-arm64-dt
for you to fetch changes up to 74265112c60be0209817c682ba68661c05da1d38:
arm64: tegra: Enable VI I2C on Jetson Nano (2020-05-15 16:28:58 +0200)
Thanks,
Thierry
----------------------------------------------------------------
arm64: tegra: Device tree changes for v5.8-rc1
This contains a couple of fixes for minor issues, enables XUDC support
on Tegra194, and enables EMC frequency scaling and video capture on
Tegra210.
----------------------------------------------------------------
Jon Hunter (2):
arm64: tegra: Fix ethernet phy-mode for Jetson Xavier
arm64: tegra: Allow the PMIC RTC to wakeup Jetson Xavier
Joseph Lo (1):
arm64: tegra: Add external memory controller node for Tegra210
Nagarjuna Kristam (1):
arm64: tegra: Add XUDC node on Tegra194
Rob Herring (1):
arm64: tegra: Kill off "simple-panel" compatibles
Sowjanya Komatineni (4):
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
arm64: tegra: Fix SOR powergate clocks and reset
arm64: tegra: Add reset-cells to memory controller
arm64: tegra: Add Tegra VI CSI support in device tree
Thierry Reding (3):
Merge branch 'for-5.8/dt-bindings' into for-5.8/arm64/dt
arm64: tegra: Hook up EMC cooling device
arm64: tegra: Enable VI I2C on Jetson Nano
Vidya Sagar (1):
arm64: tegra: Fix flag for 64-bit resources in 'ranges' property
arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +-
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 5 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 30 ++++++--
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 +++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 89 ++++++++++++++++++++--
include/dt-bindings/clock/tegra210-car.h | 2 +-
7 files changed, 125 insertions(+), 17 deletions(-)
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^ permalink raw reply
* [GIT PULL 10/11] ARM: tegra: Device tree changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-arm-dt
for you to fetch changes up to 94ea9681a9f5c7a72ae63c015e44a02530927b61:
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points (2020-05-06 19:02:40 +0200)
Thanks,
Thierry
----------------------------------------------------------------
ARM: tegra: Device tree changes for v5.8-rc1
This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.
----------------------------------------------------------------
Dmitry Osipenko (2):
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
Rob Herring (1):
ARM: tegra: Kill off "simple-panel" compatibles
arch/arm/boot/dts/tegra114-dalmore.dts | 3 +-
arch/arm/boot/dts/tegra124-venice2.dts | 2 +-
arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 2 +-
arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 +-
arch/arm/boot/dts/tegra20-harmony.dts | 2 +-
arch/arm/boot/dts/tegra20-medcom-wide.dts | 2 +-
arch/arm/boot/dts/tegra20-paz00.dts | 2 +-
arch/arm/boot/dts/tegra20-seaboard.dts | 2 +-
arch/arm/boot/dts/tegra20-ventana.dts | 2 +-
arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +-
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +-
arch/arm/boot/dts/tegra30-beaver.dts | 40 ++++++++++++++++++++++++--
arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +-
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +-
14 files changed, 50 insertions(+), 17 deletions(-)
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^ permalink raw reply
* [GIT PULL 09/11] ARM: tegra: Core changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-arm-core
for you to fetch changes up to b9bf73aed99ed3170b37fbbf98557c70a6f19e50:
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 (2020-05-06 19:01:17 +0200)
Thanks,
Thierry
----------------------------------------------------------------
ARM: tegra: Core changes for v5.8-rc1
This contains core changes needed for the CPU frequency scaling and CPU
idle drivers on Tegra20 and Tegra30.
----------------------------------------------------------------
Dmitry Osipenko (7):
firmware: tf: Different way of L2 cache enabling after LP2 suspend
ARM: tegra: Initialize r0 register for firmware wake-up
ARM: tegra: Do not fully reinitialize L2 on resume
ARM: tegra: Correct PL310 Auxiliary Control Register initialization
ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
Thierry Reding (2):
firmware: tegra: Make BPMP a regular driver
Merge branch 'for-5.8/firmware' into for-5.8/arm/core
arch/arm/mach-tegra/pm.c | 4 ++++
arch/arm/mach-tegra/reset-handler.S | 7 ++++++-
arch/arm/mach-tegra/sleep-tegra30.S | 16 +++++++++-------
arch/arm/mach-tegra/tegra.c | 8 ++++++--
drivers/firmware/tegra/bpmp.c | 9 +++------
drivers/firmware/trusted_foundations.c | 21 +++++++++++++++++++--
include/linux/firmware/trusted_foundations.h | 1 +
7 files changed, 48 insertions(+), 18 deletions(-)
_______________________________________________
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^ permalink raw reply
* [GIT PULL 08/11] soc/tegra: Changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-soc
for you to fetch changes up to e4cc4f54be01b91b3e1b55430709d2a113f4e08f:
soc: tegra: Fix tegra_pmc_get_suspend_mode definition (2020-05-07 22:03:10 +0200)
Thanks,
Thierry
----------------------------------------------------------------
soc/tegra: Changes for v5.8-rc1
Enables Tegra186 and Tegra194 to be woken from suspend by the PMIC and
exports a bit more information about SoCs via sysfs.
----------------------------------------------------------------
Arnd Bergmann (1):
soc: tegra: Fix tegra_pmc_get_suspend_mode definition
Corentin Labbe (1):
soc/tegra: pmc: Select GENERIC_PINCONF
Jon Hunter (4):
soc/tegra: fuse: Add custom SoC attributes
soc/tegra: fuse: Trivial clean-up of tegra_init_revision()
soc/tegra: fuse: Update the SoC revision attribute to display a name
soc/tegra: pmc: Enable PMIC wake event on Tegra194
Thierry Reding (1):
soc/tegra: pmc: Enable PMIC wake event on Tegra186
drivers/soc/tegra/Kconfig | 1 +
drivers/soc/tegra/fuse/fuse-tegra.c | 57 +++++++++++++++++++++++++++++++++-
drivers/soc/tegra/fuse/fuse-tegra20.c | 1 +
drivers/soc/tegra/fuse/fuse-tegra30.c | 6 ++++
drivers/soc/tegra/fuse/fuse.h | 8 +++++
drivers/soc/tegra/fuse/tegra-apbmisc.c | 32 +++++++++++--------
drivers/soc/tegra/pmc.c | 2 ++
include/soc/tegra/pmc.h | 15 +++++----
8 files changed, 102 insertions(+), 20 deletions(-)
_______________________________________________
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^ permalink raw reply
* [GIT PULL 07/11] memory: tegra: Changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-memory
for you to fetch changes up to b7d4cab0360484786b2a53b1bb603b564218112f:
memory: tegra: Delete some dead code (2020-05-12 22:52:00 +0200)
Thanks,
Thierry
----------------------------------------------------------------
memory: tegra: Changes for v5.8-rc1
Contains a few cleanup patches and an implementation to scale the EMC
frequency on Tegra210 systems.
----------------------------------------------------------------
Arnd Bergmann (1):
memory: tegra: Avoid unused function warnings
Christophe JAILLET (1):
memory: tegra: Fix an error handling path in tegra186_emc_probe()
Dan Carpenter (1):
memory: tegra: Delete some dead code
Dmitry Osipenko (9):
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Use custom CCLK implementation
clk: tegra30: Use custom CCLK implementation
memory: tegra: Make debugfs permissions human-readable
memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interrupt
memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interrupt
Geert Uytterhoeven (2):
of: Make <linux/of_reserved_mem.h> self-contained
memory: tegra: Drop <linux/clk-provider.h>
Joseph Lo (7):
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
clk: tegra: Export functions for EMC clock scaling
clk: tegra: Implement Tegra210 EMC clock
clk: tegra: Remove the old emc_mux clock for Tegra210
memory: tegra: Add EMC scaling support code for Tegra210
memory: tegra: Add EMC scaling sequence code for Tegra210
Sowjanya Komatineni (4):
dt-bindings: clock: tegra: Remove PMC clock IDs
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
dt-bindings: tegra: Add VI and CSI bindings
clk: tegra: Add Tegra210 CSI TPG clock gate
Thierry Reding (9):
of: reserved-memory: Support lookup of regions by name
of: reserved-memory: Support multiple regions per device
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
Merge branch 'for-5.8/dt-bindings' into for-5.8/clk
clk: tegra: Rename Tegra124 EMC clock source file
Merge branch 'for-5.8/dt-bindings' into for-5.8/memory
Merge branch 'for-5.8/of' into for-5.8/memory
Merge branch 'for-5.8/clk' into for-5.8/memory
memory: tegra: Support derated timings on Tegra210
.../bindings/cpufreq/nvidia,tegra20-cpufreq.txt | 56 +
.../display/tegra/nvidia,tegra20-host1x.txt | 73 +-
.../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 6 +
.../memory-controllers/nvidia,tegra210-emc.yaml | 82 +
drivers/clk/tegra/Kconfig | 4 -
drivers/clk/tegra/Makefile | 4 +-
drivers/clk/tegra/clk-pll.c | 12 +-
drivers/clk/tegra/clk-tegra-super-cclk.c | 212 ++
.../clk/tegra/{clk-emc.c => clk-tegra124-emc.c} | 0
drivers/clk/tegra/clk-tegra20.c | 7 +-
drivers/clk/tegra/clk-tegra210-emc.c | 369 ++++
drivers/clk/tegra/clk-tegra210.c | 94 +-
drivers/clk/tegra/clk-tegra30.c | 6 +-
drivers/clk/tegra/clk.h | 24 +-
drivers/memory/tegra/Kconfig | 14 +
drivers/memory/tegra/Makefile | 4 +
drivers/memory/tegra/mc.h | 1 +
drivers/memory/tegra/tegra124-emc.c | 6 +-
drivers/memory/tegra/tegra186-emc.c | 21 +-
drivers/memory/tegra/tegra186.c | 4 +-
drivers/memory/tegra/tegra20-emc.c | 34 +-
drivers/memory/tegra/tegra210-emc-cc-r21021.c | 1775 +++++++++++++++++
drivers/memory/tegra/tegra210-emc-core.c | 2100 ++++++++++++++++++++
drivers/memory/tegra/tegra210-emc-table.c | 90 +
drivers/memory/tegra/tegra210-emc.h | 1016 ++++++++++
drivers/memory/tegra/tegra210-mc.h | 50 +
drivers/memory/tegra/tegra30-emc.c | 122 +-
drivers/of/of_reserved_mem.c | 41 +-
include/dt-bindings/clock/tegra114-car.h | 14 +-
include/dt-bindings/clock/tegra124-car-common.h | 14 +-
include/dt-bindings/clock/tegra20-car.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 20 +-
include/dt-bindings/clock/tegra30-car.h | 14 +-
include/linux/clk/tegra.h | 27 +
include/linux/of_reserved_mem.h | 12 +
35 files changed, 6131 insertions(+), 199 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c
rename drivers/clk/tegra/{clk-emc.c => clk-tegra124-emc.c} (100%)
create mode 100644 drivers/clk/tegra/clk-tegra210-emc.c
create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c
create mode 100644 drivers/memory/tegra/tegra210-emc-core.c
create mode 100644 drivers/memory/tegra/tegra210-emc-table.c
create mode 100644 drivers/memory/tegra/tegra210-emc.h
create mode 100644 drivers/memory/tegra/tegra210-mc.h
_______________________________________________
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^ permalink raw reply
* [GIT PULL 06/11] media: tegra: Changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-media
for you to fetch changes up to ba8f6682bcb3312645c6cb77499ceaa66cc950a6:
media: tegra-video: Do not enable COMPILE_TEST (2020-05-12 23:09:33 +0200)
Thanks,
Thierry
----------------------------------------------------------------
media: tegra: Changes for v5.8-rc1
This contains a V4L2 video capture driver for Tegra210.
----------------------------------------------------------------
Dmitry Osipenko (1):
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
Joseph Lo (1):
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
Lukas Bulwahn (1):
MAINTAINERS: correct path in TEGRA VIDEO DRIVER
Samuel Zou (1):
media: tegra-video: Make tegra210_video_formats static
Sowjanya Komatineni (5):
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
dt-bindings: clock: tegra: Remove PMC clock IDs
dt-bindings: tegra: Add VI and CSI bindings
media: tegra-video: Add Tegra210 Video input driver
MAINTAINERS: Add Tegra Video driver section
Thierry Reding (3):
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
Merge branch 'for-5.8/dt-bindings' into for-5.8/media
media: tegra-video: Do not enable COMPILE_TEST
.../bindings/cpufreq/nvidia,tegra20-cpufreq.txt | 56 +
.../display/tegra/nvidia,tegra20-host1x.txt | 73 +-
.../devicetree/bindings/i2c/nvidia,tegra20-i2c.txt | 6 +
.../memory-controllers/nvidia,tegra210-emc.yaml | 82 ++
MAINTAINERS | 10 +
drivers/staging/media/Kconfig | 2 +
drivers/staging/media/Makefile | 1 +
drivers/staging/media/tegra-video/Kconfig | 12 +
drivers/staging/media/tegra-video/Makefile | 8 +
drivers/staging/media/tegra-video/TODO | 11 +
drivers/staging/media/tegra-video/csi.c | 539 ++++++++++
drivers/staging/media/tegra-video/csi.h | 147 +++
drivers/staging/media/tegra-video/tegra210.c | 978 ++++++++++++++++++
drivers/staging/media/tegra-video/vi.c | 1074 ++++++++++++++++++++
drivers/staging/media/tegra-video/vi.h | 257 +++++
drivers/staging/media/tegra-video/video.c | 155 +++
drivers/staging/media/tegra-video/video.h | 29 +
include/dt-bindings/clock/tegra114-car.h | 14 +-
include/dt-bindings/clock/tegra124-car-common.h | 14 +-
include/dt-bindings/clock/tegra20-car.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 16 +-
include/dt-bindings/clock/tegra30-car.h | 14 +-
22 files changed, 3457 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
create mode 100644 drivers/staging/media/tegra-video/Kconfig
create mode 100644 drivers/staging/media/tegra-video/Makefile
create mode 100644 drivers/staging/media/tegra-video/TODO
create mode 100644 drivers/staging/media/tegra-video/csi.c
create mode 100644 drivers/staging/media/tegra-video/csi.h
create mode 100644 drivers/staging/media/tegra-video/tegra210.c
create mode 100644 drivers/staging/media/tegra-video/vi.c
create mode 100644 drivers/staging/media/tegra-video/vi.h
create mode 100644 drivers/staging/media/tegra-video/video.c
create mode 100644 drivers/staging/media/tegra-video/video.h
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* [GIT PULL 05/11] firmware: tegra: Changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-firmware
for you to fetch changes up to b720aaa347f227c416e8aed2f12ca62ea4f1cd4e:
firmware: tf: Different way of L2 cache enabling after LP2 suspend (2020-05-06 18:27:26 +0200)
Thanks,
Thierry
----------------------------------------------------------------
firmware: tegra: Changes for v5.8-rc1
This contains a change that makes the BPMP driver a regular driver,
which fixes some weird suspend/resume ordering issues. Another fix is
also included to implement another way of enabling the L2 cache after
LP2 suspend.
----------------------------------------------------------------
Dmitry Osipenko (1):
firmware: tf: Different way of L2 cache enabling after LP2 suspend
Thierry Reding (1):
firmware: tegra: Make BPMP a regular driver
drivers/firmware/tegra/bpmp.c | 9 +++------
drivers/firmware/trusted_foundations.c | 21 +++++++++++++++++++--
include/linux/firmware/trusted_foundations.h | 1 +
3 files changed, 23 insertions(+), 8 deletions(-)
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* [GIT PULL 04/11] of: Changes for v5.8-rc1
From: Thierry Reding @ 2020-05-15 14:53 UTC (permalink / raw)
To: arm, soc; +Cc: linux-tegra, Thierry Reding, linux-arm-kernel, Jon Hunter
In-Reply-To: <20200515145311.1580134-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.8-of
for you to fetch changes up to 4a470f00e10e3336350ab60ec6c3206177093019:
of: Make <linux/of_reserved_mem.h> self-contained (2020-05-12 22:45:39 +0200)
Thanks,
Thierry
----------------------------------------------------------------
of: Changes for v5.8-rc1
These changes add support for multiple reserved-memory regions per
device.
----------------------------------------------------------------
Geert Uytterhoeven (1):
of: Make <linux/of_reserved_mem.h> self-contained
Thierry Reding (2):
of: reserved-memory: Support lookup of regions by name
of: reserved-memory: Support multiple regions per device
drivers/of/of_reserved_mem.c | 41 +++++++++++++++++++++++++++++------------
include/linux/of_reserved_mem.h | 12 ++++++++++++
2 files changed, 41 insertions(+), 12 deletions(-)
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