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* Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
From: Guenter Roeck @ 2020-05-19  2:50 UTC (permalink / raw)
  To: Ira Weiny
  Cc: Peter Zijlstra, Benjamin Herrenschmidt, Dave Hansen, dri-devel,
	linux-mips, James E.J. Bottomley, Max Filippov, Paul Mackerras,
	H. Peter Anvin, sparclinux, Dan Williams, Helge Deller, x86,
	linux-csky, Christoph Hellwig, Ingo Molnar, linux-snps-arc,
	linux-xtensa, Borislav Petkov, Al Viro, Andy Lutomirski,
	Thomas Gleixner, linux-arm-kernel, Chris Zankel,
	Thomas Bogendoerfer, linux-parisc, linux-kernel, Christian Koenig,
	Andrew Morton, linuxppc-dev, David S. Miller
In-Reply-To: <20200519000352.GF3025231@iweiny-DESK2.sc.intel.com>

Hi Ira,

On 5/18/20 5:03 PM, Ira Weiny wrote:
> On Sun, May 17, 2020 at 09:29:32PM -0700, Guenter Roeck wrote:
>> On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
>>> On Sat, May 16, 2020 at 03:33:06PM -0700, Guenter Roeck wrote:
>>>> On Thu, May 07, 2020 at 07:59:55AM -0700, ira.weiny@intel.com wrote:
>>>>> From: Ira Weiny <ira.weiny@intel.com>
>>>>>
>>>>> Every single architecture (including !CONFIG_HIGHMEM) calls...
>>>>>
>>>>> 	pagefault_enable();
>>>>> 	preempt_enable();
>>>>>
>>>>> ... before returning from __kunmap_atomic().  Lift this code into the
>>>>> kunmap_atomic() macro.
>>>>>
>>>>> While we are at it rename __kunmap_atomic() to kunmap_atomic_high() to
>>>>> be consistent.
>>>>>
>>>>> Reviewed-by: Christoph Hellwig <hch@lst.de>
>>>>> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>>>>
>>>> This patch results in:
>>>>
>>>> Starting init: /bin/sh exists but couldn't execute it (error -14)
>>>>
>>>> when trying to boot microblazeel:petalogix-ml605 in qemu.
>>>
>>> Thanks for the report.  I'm not readily seeing the issue.
>>>
>>> Do you have a kernel config?  Specifically is CONFIG_HIGHMEM set?
>>>
>> See below. Yes, CONFIG_HIGHMEM is set.
>>
>> The scripts used to build and boot the image are at:
>>
>> https://github.com/groeck/linux-build-test/tree/master/rootfs/microblazeel
> 
> Despite finding the obvious error earlier today I've still been trying to get
> this to work.
> 
> I had to make some slight modifications to use the 0-day cross compile build
> and my local qemu build.  But those were pretty minor modifications.  I'm
> running on x86_64 host.
> 
> With those slight mods to the scripts I get the following error even without my
> patch set on 5.7-rc4.  I have 1 cpu pegged at 100% while it is running...  Is
> there anything I can do to get more debug output?  Perhaps I just need to let
> it run longer?
> 

I don't think so. Try running it with "-d" parameter (run-qemu-microblazeel.sh
-d petalogix-s3adsp1800); that gives you the qemu command line. Once it says
"running", abort the script and execute qemu directly. Oh, and please update
the repository; turns out I didn't push for a while and made a number of
changes.

My compiler was compiled with buildroot (a long time ago). I don't recall if
it needed something special in the configuration, unfortunately.

Guenter

> Thanks,
> Ira
> 
> 16:46:54 > ../linux-build-test/rootfs/microblazeel/run-qemu-microblazeel.sh 
> Build reference: v5.7-rc4-2-g7c2411d7fb6a
> 
> Building microblaze:petalogix-s3adsp1800:qemu_microblazeel_defconfig ...
> running ................ failed (silent)
> ------------
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
> ------------
> Building microblaze:petalogix-ml605:qemu_microblazeel_ml605_defconfig ...
> running ................ failed (silent)
> ------------
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
> ------------
> 
> <env changes>
> 16:47:23 > git di
> diff --git a/rootfs/microblazeel/run-qemu-microblazeel.sh b/rootfs/microblazeel/run-qemu-microblazeel.sh
> index 68d4de39ab50..0d6a4f85308f 100755
> --- a/rootfs/microblazeel/run-qemu-microblazeel.sh
> +++ b/rootfs/microblazeel/run-qemu-microblazeel.sh
> @@ -3,7 +3,8 @@
>  dir=$(cd $(dirname $0); pwd)
>  . ${dir}/../scripts/common.sh
>  
> -QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +#QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +QEMU=/home/iweiny/dev/qemu/microblazeel-softmmu/qemu-system-microblazeel
>  PREFIX=microblazeel-linux-
>  ARCH=microblaze
>  PATH_MICROBLAZE=/opt/kernel/microblazeel/gcc-4.9.1/usr/bin
> diff --git a/rootfs/scripts/common.sh b/rootfs/scripts/common.sh
> index 8fa6a9be2b2f..c4550a27beaa 100644
> --- a/rootfs/scripts/common.sh
> +++ b/rootfs/scripts/common.sh
> @@ -1,5 +1,9 @@
>  #!/bin/bash
>  
> +# Set up make.cross
> +export COMPILER_INSTALL_PATH=$HOME/0day
> +export GCC_VERSION=6.5.0
> +
>  # Set the following variable to true to skip DC395/AM53C97 build tests
>  __skip_dc395=0
>  
> @@ -569,7 +573,7 @@ doclean()
>         then
>                 git clean -x -d -f -q
>         else
> -               make ARCH=${ARCH} mrproper >/dev/null 2>&1
> +               make.cross ARCH=${ARCH} mrproper >/dev/null 2>&1
>         fi
>  }
>  
> @@ -669,7 +673,7 @@ __setup_config()
>         cp ${__progdir}/${defconfig} arch/${arch}/configs
>      fi
>  
> -    if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${defconfig} >/dev/null 2>&1 </dev/null; then
> +    if ! make.cross ARCH=${ARCH} ${defconfig} >/dev/null 2>&1 </dev/null; then
>         return 2
>      fi
>  
> @@ -687,7 +691,7 @@ __setup_config()
>         if [[ "${rel}" = "v3.16" ]]; then
>             target="oldconfig"
>         fi
> -       if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${target} >/dev/null 2>&1 </dev/null; then
> +       if ! make.cross ARCH=${ARCH} ${target} >/dev/null 2>&1 </dev/null; then
>             return 1
>         fi
>      fi
> @@ -1038,7 +1042,7 @@ dosetup()
>      rootfs="$(setup_rootfs ${dynamic} ${rootfs})"
>      __common_fixups "${fixups}" "${rootfs}"
>  
> -    make -j${maxload} ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${EXTRAS} </dev/null >/dev/null 2>${logfile}
> +    make.cross -j${maxload} ARCH=${ARCH} ${EXTRAS} </dev/null >/dev/null 2>${logfile}
>      rv=$?
>      if [ ${rv} -ne 0 ]
>      then
> 
> </env changes>
> 


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* RE: [PATCH 3/3] dt-bindings: timer: Convert i.MX SYSCTR to json-schema
From: Aisheng Dong @ 2020-05-19  2:51 UTC (permalink / raw)
  To: Anson Huang, daniel.lezcano@linaro.org, tglx@linutronix.de,
	robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, Jacky Bai,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
  Cc: dl-linux-imx
In-Reply-To: <1589813260-20036-4-git-send-email-Anson.Huang@nxp.com>

> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Monday, May 18, 2020 10:48 PM
> 
> Convert the i.MX SYSCTR binding to DT schema format using json-schema.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng
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* RE: [PATCH] ARM: dts: imx: make src node name generic
From: Aisheng Dong @ 2020-05-19  2:52 UTC (permalink / raw)
  To: Anson Huang, robh+dt@kernel.org, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
  Cc: dl-linux-imx
In-Reply-To: <1589805593-14164-1-git-send-email-Anson.Huang@nxp.com>

> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Monday, May 18, 2020 8:40 PM
> 
> Node name should be generic, use "reset-controller" instead of "src" for
> i.MX6/i.MX7 SoCs src nodes.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> ---
>  arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
>  arch/arm/boot/dts/imx6sl.dtsi  | 2 +-
>  arch/arm/boot/dts/imx6sx.dtsi  | 2 +-
>  arch/arm/boot/dts/imx6ul.dtsi  | 2 +-
>  arch/arm/boot/dts/imx7s.dtsi   | 2 +-
>  5 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index 1763c2b..39d4afd 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -858,7 +858,7 @@
>  				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			src: src@20d8000 {
> +			src: reset-controller@20d8000 {
>  				compatible = "fsl,imx6q-src", "fsl,imx51-src";
>  				reg = <0x020d8000 0x4000>;
>  				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, diff --git
> a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index
> fcb84fe..911d8cf 100644
> --- a/arch/arm/boot/dts/imx6sl.dtsi
> +++ b/arch/arm/boot/dts/imx6sl.dtsi
> @@ -678,7 +678,7 @@
>  				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			src: src@20d8000 {
> +			src: reset-controller@20d8000 {
>  				compatible = "fsl,imx6sl-src", "fsl,imx51-src";
>  				reg = <0x020d8000 0x4000>;
>  				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, diff --git
> a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index
> d6f8317..e031337 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -754,7 +754,7 @@
>  				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			src: src@20d8000 {
> +			src: reset-controller@20d8000 {
>  				compatible = "fsl,imx6sx-src", "fsl,imx51-src";
>  				reg = <0x020d8000 0x4000>;
>  				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, diff --git
> a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index
> 2ccf67c..35e7301 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -676,7 +676,7 @@
>  				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>  			};
> 
> -			src: src@20d8000 {
> +			src: reset-controller@20d8000 {
>  				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
>  				reg = <0x020d8000 0x4000>;
>  				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, diff --git
> a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index
> 76e3ffb..8bac491 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -624,7 +624,7 @@
>  				clock-names = "ckil", "osc";
>  			};
> 
> -			src: src@30390000 {
> +			src: reset-controller@30390000 {
>  				compatible = "fsl,imx7d-src", "syscon";
>  				reg = <0x30390000 0x10000>;
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.7.4

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* Re: [PATCH][v2] iommu: arm-smmu-v3: Copy SMMU table for kdump kernel
From: Prabhakar Kushwaha @ 2020-05-19  2:54 UTC (permalink / raw)
  To: Will Deacon
  Cc: Ganapatrao Prabhakerrao Kulkarni, Marc Zyngier, Bhupesh Sharma,
	kexec mailing list, Bjorn Helgaas, Prabhakar Kushwaha,
	Robin Murphy, linux-arm-kernel
In-Reply-To: <20200518155545.GO32394@willie-the-truck>

Hi Will,

Sorry, I replied 1:1. Now replying with mailing list

On Mon, May 18, 2020 at 9:25 PM Will Deacon <will@kernel.org> wrote:
>
> On Mon, May 11, 2020 at 07:46:06PM -0700, Prabhakar Kushwaha wrote:
> > An SMMU Stream table is created by the primary kernel. This table is
> > used by the SMMU to perform address translations for device-originated
> > transactions. Any crash (if happened) launches the kdump kernel which
> > re-creates the SMMU Stream table. New transactions will be translated
> > via this new table.
> >
> > There are scenarios, where devices are still having old pending
> > transactions (configured in the primary kernel). These transactions
> > come in-between Stream table creation and device-driver probe.
> > As new stream table does not have entry for older transactions,
> > it will be aborted by SMMU.
> >
> > Similar observations were found with PCIe-Intel 82576 Gigabit
> > Network card. It sends old Memory Read transaction in kdump kernel.
> > Transactions configured for older Stream table entries, that do not
> > exist any longer in the new table, will cause a PCIe Completion Abort.
> > Returned PCIe completion abort further leads to AER Errors from APEI
> > Generic Hardware Error Source (GHES) with completion timeout.
> > A network device hang is observed even after continuous
> > reset/recovery from driver, Hence device is no more usable.
> >
> > So, If we are in a kdump kernel try to copy SMMU Stream table from
> > primary/old kernel to preserve the mappings until the device driver
> > takes over.
> >
> > Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
> > ---
> > Changes for v2: Used memremap in-place of ioremap
> >
> > V2 patch has been sanity tested.
>
> Are you sure?
>

I tested v1 patch thoroughly.

After replacing ioremap with memremap, I tested 1-2 cycle per type.
I can test this patch thoroughly to check any kind of possible error.

> > V1 patch has been tested with
> > A) PCIe-Intel 82576 Gigabit Network card in following
> > configurations with "no AER error". Each iteration has
> > been tested on both Suse kdump rfs And default Centos distro rfs.
> >
> >  1)  with 2 level stream table
> >        ----------------------------------------------------
> >        SMMU               |  Normal Ping   | Flood Ping
> >        -----------------------------------------------------
> >        Default Operation  |  100 times     | 10 times
> >        -----------------------------------------------------
> >        IOMMU bypass       |  41 times      | 10 times
> >        -----------------------------------------------------
> >
> >  2)  with Linear stream table.
> >        -----------------------------------------------------
> >        SMMU               |  Normal Ping   | Flood Ping
> >        ------------------------------------------------------
> >        Default Operation  |  100 times     | 10 times
> >        ------------------------------------------------------
> >        IOMMU bypass       |  55 times      | 10 times
> >        -------------------------------------------------------
> >
> > B) This patch is also tested with Micron Technology Inc 9200 PRO NVMe
> > SSD card with 2 level stream table using "fio" in mixed read/write and
> > only read configurations. It is tested for both Default Operation and
> > IOMMU bypass mode for minimum 10 iterations across Centos kdump rfs and
> > default Centos ditstro rfs.
> >
> > This patch is not full proof solution. Issue can still come
> > from the point device is discovered and driver probe called.
> > This patch has reduced window of scenario from "SMMU Stream table
> > creation - device-driver" to "device discovery - device-driver".
> > Usually, device discovery to device-driver is very small time. So
> > the probability is very low.
> >
> > Note: device-discovery will overwrite existing stream table entries
> > with both SMMU stage as by-pass.
> >
> >
> >  drivers/iommu/arm-smmu-v3.c | 36 +++++++++++++++++++++++++++++++++++-
> >  1 file changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> > index 82508730feb7..d492d92c2dd7 100644
> > --- a/drivers/iommu/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm-smmu-v3.c
> > @@ -1847,7 +1847,13 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> >                       break;
> >               case STRTAB_STE_0_CFG_S1_TRANS:
> >               case STRTAB_STE_0_CFG_S2_TRANS:
> > -                     ste_live = true;
> > +                     /*
> > +                      * As kdump kernel copy STE table from previous
> > +                      * kernel. It still may have valid stream table entries.
> > +                      * Forcing entry as false to allow overwrite.
> > +                      */
> > +                     if (!is_kdump_kernel())
> > +                             ste_live = true;
> >                       break;
> >               case STRTAB_STE_0_CFG_ABORT:
> >                       BUG_ON(!disable_bypass);
> > @@ -3264,6 +3270,9 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
> >               return -ENOMEM;
> >       }
> >
> > +     if (is_kdump_kernel())
> > +             return 0;
> > +
> >       for (i = 0; i < cfg->num_l1_ents; ++i) {
> >               arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);
> >               strtab += STRTAB_L1_DESC_DWORDS << 3;
> > @@ -3272,6 +3281,23 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
> >       return 0;
> >  }
> >
> > +static void arm_smmu_copy_table(struct arm_smmu_device *smmu,
> > +                            struct arm_smmu_strtab_cfg *cfg, u32 size)
> > +{
> > +     struct arm_smmu_strtab_cfg rdcfg;
> > +
> > +     rdcfg.strtab_dma = readq_relaxed(smmu->base + ARM_SMMU_STRTAB_BASE);
> > +     rdcfg.strtab_base_cfg = readq_relaxed(smmu->base
> > +                                           + ARM_SMMU_STRTAB_BASE_CFG);
> > +
> > +     rdcfg.strtab_dma &= STRTAB_BASE_ADDR_MASK;
> > +     rdcfg.strtab = memremap(rdcfg.strtab_dma, size, MEMREMAP_WB);
> > +
> > +     memcpy_fromio(cfg->strtab, rdcfg.strtab, size);
> > +

this need a fix. It should be memcpy.

> > +     cfg->strtab_base_cfg = rdcfg.strtab_base_cfg;
>
> Sorry, but this is unacceptable. These things were allocated by the DMA API
> so you can't just memcpy them around and hope for the best.
>

I was referring copy_context_table() in drivers/iommu/intel-iommu.c.
here i see usage of memremap and memcpy to copy older iommu table.
did I take wrong reference?

What kind of issue you are foreseeing in using memcpy(). May be we can
try to find a solution.

-pk

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* RE: [PATCH V2] dt-bindings: reset: Convert i.MX reset to json-schema
From: Aisheng Dong @ 2020-05-19  2:55 UTC (permalink / raw)
  To: Anson Huang, p.zabel@pengutronix.de, robh+dt@kernel.org,
	shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
  Cc: dl-linux-imx
In-Reply-To: <1589796212-9993-1-git-send-email-Anson.Huang@nxp.com>

> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Monday, May 18, 2020 6:04 PM
> 
> Convert the i.MX reset binding to DT schema format using json-schema.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> Changes since V1:
> 	- add the compatible strings per SoC;
> 	- use "reset-controller" as node name instead of src;
> 	- add interrupt items description.
> ---
>  .../devicetree/bindings/reset/fsl,imx-src.txt      | 49 -----------
>  .../devicetree/bindings/reset/fsl,imx-src.yaml     | 98
> ++++++++++++++++++++++
>  2 files changed, 98 insertions(+), 49 deletions(-)  delete mode 100644
> Documentation/devicetree/bindings/reset/fsl,imx-src.txt
>  create mode 100644
> Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> deleted file mode 100644
> index 6ed79e6..0000000
> --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -Freescale i.MX System Reset Controller
> -======================================
> -
> -Please also refer to reset.txt in this directory for common reset -controller
> binding usage.
> -
> -Required properties:
> -- compatible: Should be "fsl,<chip>-src"
> -- reg: should be register base and length as documented in the
> -  datasheet
> -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
> -  in this order.
> -- #reset-cells: 1, see below
> -
> -example:
> -
> -src: src@20d8000 {
> -        compatible = "fsl,imx6q-src";
> -        reg = <0x020d8000 0x4000>;
> -        interrupts = <0 91 0x04 0 96 0x04>;
> -        #reset-cells = <1>;
> -};
> -
> -Specifying reset lines connected to IP modules
> -==============================================
> -
> -The system reset controller can be used to reset the GPU, VPU, -IPU, and
> OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes should
> specify the reset line on the SRC in their resets -property, containing a phandle
> to the SRC device node and a -RESET_INDEX specifying which module to reset,
> as described in -reset.txt
> -
> -example:
> -
> -        ipu1: ipu@2400000 {
> -                resets = <&src 2>;
> -        };
> -        ipu2: ipu@2800000 {
> -                resets = <&src 4>;
> -        };
> -
> -The following RESET_INDEX values are valid for i.MX5:
> -GPU_RESET     0
> -VPU_RESET     1
> -IPU1_RESET    2
> -OPEN_VG_RESET 3
> -The following additional RESET_INDEX value is valid for i.MX6:
> -IPU2_RESET    4
> diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> new file mode 100644
> index 0000000..7cd6095
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---

[...]

> +title: Freescale i.MX System Reset Controller
> +
> +maintainers:
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  The system reset controller can be used to reset the GPU, VPU,
> +  IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
> +  nodes should specify the reset line on the SRC in their resets
> +  property, containing a phandle to the SRC device node and a
> +  RESET_INDEX specifying which module to reset, as described in
> +  reset.txt
> +
> +  The following RESET_INDEX values are valid for i.MX5:
> +    GPU_RESET     0
> +    VPU_RESET     1
> +    IPU1_RESET    2
> +    OPEN_VG_RESET 3
> +  The following additional RESET_INDEX value is valid for i.MX6:
> +    IPU2_RESET    4
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - description: on i.MX51 the following compatible must be specified

Unnecessary description

Otherwise:

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng

> +        items:
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX50 the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx50-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX53 the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx53-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX6Q the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx6q-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX6SX the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx6sx-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX6SL the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx6sl-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX6UL the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx6ul-src"
> +          - const: "fsl,imx51-src"
> +
> +      - description: on i.MX6SLL the following compatibles must be specified
> +        items:
> +          - const: "fsl,imx6sll-src"
> +          - const: "fsl,imx51-src"
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: SRC interrupt
> +      - description: CPU WDOG interrupts out of SRC
> +    minItems: 1
> +    maxItems: 2
> +
> +  '#reset-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    reset-controller@73fd0000 {
> +        compatible = "fsl,imx51-src";
> +        reg = <0x73fd0000 0x4000>;
> +        interrupts = <75>;
> +        #reset-cells = <1>;
> +    };
> --
> 2.7.4

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* RE: [PATCH V2] dt-bindings: clock: Convert i.MX7D clock to json-schema
From: Anson Huang @ 2020-05-19  2:57 UTC (permalink / raw)
  To: Aisheng Dong, mturquette@baylibre.com, sboyd@kernel.org,
	robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, Frank Li,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
  Cc: dl-linux-imx
In-Reply-To: <AM6PR04MB4966B101D3E0A0820FAD4CDC80B90@AM6PR04MB4966.eurprd04.prod.outlook.com>



> Subject: RE: [PATCH V2] dt-bindings: clock: Convert i.MX7D clock to
> json-schema
> 
> > From: Anson Huang <Anson.Huang@nxp.com>
> > Sent: Monday, May 18, 2020 10:53 PM
> >
> > Convert the i.MX7D clock binding to DT schema format using json-schema.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> > Changes since V1:
> > 	- Update maintainer's e-mail address.
> > ---
> >  .../devicetree/bindings/clock/imx7d-clock.txt      | 13 -----
> >  .../devicetree/bindings/clock/imx7d-clock.yaml     | 64
> > ++++++++++++++++++++++
> >  2 files changed, 64 insertions(+), 13 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/clock/imx7d-clock.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/imx7d-clock.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.txt
> > b/Documentation/devicetree/bindings/clock/imx7d-clock.txt
> > deleted file mode 100644
> > index 9d3026d..0000000
> > --- a/Documentation/devicetree/bindings/clock/imx7d-clock.txt
> > +++ /dev/null
> > @@ -1,13 +0,0 @@
> > -* Clock bindings for Freescale i.MX7 Dual
> > -
> > -Required properties:
> > -- compatible: Should be "fsl,imx7d-ccm"
> > -- reg: Address and length of the register set
> > -- #clock-cells: Should be <1>
> > -- clocks: list of clock specifiers, must contain an entry for each
> > required
> > -  entry in clock-names
> > -- clock-names: should include entries "ckil", "osc"
> > -
> > -The clock consumer should specify the desired clock by having the
> > clock -ID in its "clocks" phandle cell.  See
> > include/dt-bindings/clock/imx7d-clock.h
> > -for the full list of i.MX7 Dual clock IDs.
> > diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml
> > b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml
> > new file mode 100644
> > index 0000000..8cd0573
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml
> > @@ -0,0 +1,64 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +title: Clock bindings for Freescale i.MX7 Dual
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +  - Anson Huang <Anson.Huang@nxp.com>
> > +
> > +description: |
> > +  The clock consumer should specify the desired clock by having the
> > +clock
> > +  ID in its "clocks" phandle cell. See
> > +include/dt-bindings/clock/imx7d-clock.h
> > +  for the full list of i.MX7 Dual clock IDs.
> > +
> > +properties:
> > +  compatible:
> > +    const: fsl,imx7d-ccm
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    items:
> > +      - description: CCM interrupt request 1
> > +      - description: CCM interrupt request 2
> 
> Do we have a more specific description from RM?
> Otherwise, I'm fine with this patch.

I checked both RM and design doc before, can NOT find any description about
these 2 interrupts, so I did NOT add detail descriptions for them.

Anson
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* [v2] ARM: dts: ls1021a: output PPS signal on FIPER2
From: Yangbo Lu @ 2020-05-19  2:53 UTC (permalink / raw)
  To: linux-arm-kernel; +Cc: Richard Cochran, Li Yang, Shawn Guo, Yangbo Lu

The timer fixed interval period pulse generator register
is used to generate periodic pulses. The down count
register loads the value programmed in the fixed period
interval (FIPER). At every tick of the timer accumulator
overflow, the counter decrements by the value of
TMR_CTRL[TCLK_PERIOD]. It generates a pulse when the down
counter value reaches zero. It reloads the down counter
in the cycle following a pulse. To use the TMR_FIPER
register to generate a 1 PPS event, the value
(10^9 nanoseconds) - TCLK_PERIOD should be programmed.
It should be 999999995 since TCLK_PERIOD is 5.

This patch is to output PPS signal on FIPER2 which is more
desired by user.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
Changes for v2:
	- Added more discription in commit message.
---
 arch/arm/boot/dts/ls1021a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 760a68c..b2ff27a 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -772,7 +772,7 @@
 			fsl,tmr-prsc    = <2>;
 			fsl,tmr-add     = <0xaaaaaaab>;
 			fsl,tmr-fiper1  = <999999995>;
-			fsl,tmr-fiper2  = <99990>;
+			fsl,tmr-fiper2  = <999999995>;
 			fsl,max-adj     = <499999999>;
 			fsl,extts-fifo;
 		};
-- 
2.7.4


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* RE: [PATCH] ARM: dts: ls1021a: output PPS signal on FIPER2
From: Y.b. Lu @ 2020-05-19  2:58 UTC (permalink / raw)
  To: Shawn Guo; +Cc: Richard Cochran, linux-arm-kernel@lists.infradead.org, Leo Li
In-Reply-To: <20200517135424.GA25973@dragon>

> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Sunday, May 17, 2020 9:54 PM
> To: Y.b. Lu <yangbo.lu@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; Leo Li <leoyang.li@nxp.com>;
> Richard Cochran <richardcochran@gmail.com>
> Subject: Re: [PATCH] ARM: dts: ls1021a: output PPS signal on FIPER2
> 
> On Thu, May 14, 2020 at 03:13:45AM +0000, Y.b. Lu wrote:
> > Hi Shawn,
> >
> > > -----Original Message-----
> > > From: Shawn Guo <shawnguo@kernel.org>
> > > Sent: Wednesday, May 13, 2020 4:23 PM
> > > To: Y.b. Lu <yangbo.lu@nxp.com>
> > > Cc: linux-arm-kernel@lists.infradead.org; Leo Li <leoyang.li@nxp.com>;
> > > Richard Cochran <richardcochran@gmail.com>
> > > Subject: Re: [PATCH] ARM: dts: ls1021a: output PPS signal on FIPER2
> > >
> > > On Mon, Apr 27, 2020 at 11:56:55AM +0800, Yangbo Lu wrote:
> > > > Output PPS signal on FIPER2 (Fixed Period Interval Pulse)
> > > > which is more desired by user.
> > > >
> > > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> > > > ---
> > > >  arch/arm/boot/dts/ls1021a.dtsi | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/arm/boot/dts/ls1021a.dtsi
> b/arch/arm/boot/dts/ls1021a.dtsi
> > > > index 760a68c..b2ff27a 100644
> > > > --- a/arch/arm/boot/dts/ls1021a.dtsi
> > > > +++ b/arch/arm/boot/dts/ls1021a.dtsi
> > > > @@ -772,7 +772,7 @@
> > > >  			fsl,tmr-prsc    = <2>;
> > > >  			fsl,tmr-add     = <0xaaaaaaab>;
> > > >  			fsl,tmr-fiper1  = <999999995>;
> > > > -			fsl,tmr-fiper2  = <99990>;
> > > > +			fsl,tmr-fiper2  = <999999995>;
> > >
> > > Not sure code change matches patch subject and commit log.  The change
> > > is about changing fsl,tmr-fiper2 setting from one value to another.
> >
> > The calculation refers to
> Documentation/devicetree/bindings/ptp/ptp-qoriq.txt. It looks complicated.
> > But to be simple, to get 1PPS signal (period is 1s) on FIPER2, the value should
> be set as,
> > fiper2 = <desired period> - <tclk-period> = 1000000000ns - 5ns =
> 999999995.
> 
> Please update commit log to include how new value comes.

Sent out v2. Thanks!

> 
> Shawn

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* Re: [PATCH v2 2/2] i2c: mediatek: Add i2c ac-timing adjust support
From: Qii Wang @ 2020-05-19  2:57 UTC (permalink / raw)
  To: Joe Perches, Geert Uytterhoeven
  Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	srv_heupstream, Wolfram Sang, leilk.liu,
	Linux Kernel Mailing List, linux-mediatek, Linux I2C, Linux ARM
In-Reply-To: <CAMuHMdXjLakWDDEy=02prC7XjAs_xBnt2mArPFNwyHgUoWw6-g@mail.gmail.com>

On Mon, 2020-05-18 at 17:44 +0200, Geert Uytterhoeven wrote:
> On Thu, May 14, 2020 at 3:13 PM Qii Wang <qii.wang@mediatek.com> wrote:
> > This patch adds a algorithm to calculate some ac-timing parameters
> > which can fully meet I2C Spec.
> >
> > Signed-off-by: Qii Wang <qii.wang@mediatek.com>
> > ---
> >  drivers/i2c/busses/i2c-mt65xx.c | 328 +++++++++++++++++++++++++++++++++-------
> >  1 file changed, 277 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index 0ca6c38a..7020618 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> 
> > +/*
> > + * Check and Calculate i2c ac-timing
> > + *
> > + * Hardware design:
> > + * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
> > + * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
> > + *
> > + * Sample_ns is rounded down for xxx_cnt_div would be greater
> > + * than the smallest spec.
> > + * The sda_timing is chosen as the middle value between
> > + * the largest and smallest.
> > + */
> > +static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
> > +                                  unsigned int clk_src,
> > +                                  unsigned int check_speed,
> > +                                  unsigned int step_cnt,
> > +                                  unsigned int sample_cnt)
> > +{
> > +       const struct i2c_spec_values *spec;
> > +       unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
> > +       unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
> > +       long long sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src;
> 
> So sample_ns is a 64-bit value. Is that really needed?
> 

(1000000000 * (sample_cnt + 1)) / clk_src value is a 32-bit, (1000000000
* (sample_cnt + 1)) will over 32-bit if sample_cnt is 7.

I think 1000000000 and clk_src is too big, maybe I can reduce then with
be divided all by 1000.
example:

unsigned int sample_ns;
unsigned int clk_src_khz = clk_src / 1000;

if(clk_src_khz)
	sample_ns = (1000000 * (sample_cnt + 1)) / clk_src_khz;
else
	return -EINVAL;

> > +       if (!i2c->dev_comp->timing_adjust)
> > +               return 0;
> > +
> > +       if (i2c->dev_comp->ltiming_adjust)
> > +               max_sta_cnt = 0x100;
> > +
> > +       spec = mtk_i2c_get_spec(check_speed);
> > +
> > +       if (i2c->dev_comp->ltiming_adjust)
> > +               clk_ns = 1000000000 / clk_src;
> > +       else
> > +               clk_ns = sample_ns / 2;
> > +
> > +       su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
> > +       if (su_sta_cnt > max_sta_cnt)
> > +               return -1;
> > +
> > +       low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
> 
> So this is a 32-bit by 64-bit division (indeed, not 64-by-32!)
> 
> noreply@ellerman.id.au reports:
> 
>     ERROR: modpost: "__udivdi3" [drivers/i2c/busses/i2c-mt65xx.ko] undefined!
>     ERROR: modpost: "__divdi3" [drivers/i2c/busses/i2c-mt65xx.ko] undefined!
> 
> for 32-bit builds.
> 
> > +       max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
> > +       if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
> > +               if (low_cnt > step_cnt) {
> > +                       high_cnt = 2 * step_cnt - low_cnt;
> > +               } else {
> > +                       high_cnt = step_cnt;
> > +                       low_cnt = step_cnt;
> > +               }
> > +       } else {
> > +               return -2;
> > +       }
> > +
> > +       sda_max = spec->max_hd_dat_ns / sample_ns;
> > +       if (sda_max > low_cnt)
> > +               sda_max = 0;
> > +
> > +       sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
> 
> One more.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

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* RE: [PATCH] arm64: dts: ls1043a-rdb: add compatible for board
From: Y.b. Lu @ 2020-05-19  3:01 UTC (permalink / raw)
  To: linux-arm-kernel@lists.infradead.org; +Cc: Shawn Guo, Leo Li
In-Reply-To: <20200430025646.16766-1-yangbo.lu@nxp.com>

Any comments?
Thanks!

> -----Original Message-----
> From: Yangbo Lu <yangbo.lu@nxp.com>
> Sent: Thursday, April 30, 2020 10:57 AM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Y.b. Lu <yangbo.lu@nxp.com>; Shawn Guo <shawnguo@kernel.org>; Leo Li
> <leoyang.li@nxp.com>
> Subject: [PATCH] arm64: dts: ls1043a-rdb: add compatible for board
> 
> Add compatible for board to identify.
> 
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> index dde50c8..9a93e9a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
> @@ -13,6 +13,7 @@
> 
>  / {
>  	model = "LS1043A RDB Board";
> +	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
> 
>  	aliases {
>  		serial0 = &duart0;
> --
> 2.7.4


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* RE: [PATCH 1/3] dt-bindings: timer: Convert i.MX GPT to json-schema
From: Anson Huang @ 2020-05-19  3:03 UTC (permalink / raw)
  To: Aisheng Dong, daniel.lezcano@linaro.org, tglx@linutronix.de,
	robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, Jacky Bai,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
  Cc: dl-linux-imx
In-Reply-To: <AM6PR04MB49669345E21DC28009C486E680B90@AM6PR04MB4966.eurprd04.prod.outlook.com>



> Subject: RE: [PATCH 1/3] dt-bindings: timer: Convert i.MX GPT to json-schema
> 
> > From: Anson Huang <Anson.Huang@nxp.com>
> > Sent: Monday, May 18, 2020 10:48 PM
> >
> > Convert the i.MX GPT binding to DT schema format using json-schema.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> >  .../devicetree/bindings/timer/fsl,imxgpt.txt       |  45 ---------
> >  .../devicetree/bindings/timer/fsl,imxgpt.yaml      | 109
> > +++++++++++++++++++++
> >  2 files changed, 109 insertions(+), 45 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
> > b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
> > deleted file mode 100644
> > index 5d8fd5b..0000000
> > --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
> > +++ /dev/null
> > @@ -1,45 +0,0 @@
> > -Freescale i.MX General Purpose Timer (GPT)
> > -
> > -Required properties:
> > -
> > -- compatible : should be one of following:
> > -  for i.MX1:
> > -  - "fsl,imx1-gpt";
> > -  for i.MX21:
> > -  - "fsl,imx21-gpt";
> > -  for i.MX27:
> > -  - "fsl,imx27-gpt", "fsl,imx21-gpt";
> > -  for i.MX31:
> > -  - "fsl,imx31-gpt";
> > -  for i.MX25:
> > -  - "fsl,imx25-gpt", "fsl,imx31-gpt";
> > -  for i.MX50:
> > -  - "fsl,imx50-gpt", "fsl,imx31-gpt";
> > -  for i.MX51:
> > -  - "fsl,imx51-gpt", "fsl,imx31-gpt";
> > -  for i.MX53:
> > -  - "fsl,imx53-gpt", "fsl,imx31-gpt";
> > -  for i.MX6Q:
> > -  - "fsl,imx6q-gpt", "fsl,imx31-gpt";
> > -  for i.MX6DL:
> > -  - "fsl,imx6dl-gpt";
> > -  for i.MX6SL:
> > -  - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
> > -  for i.MX6SX:
> > -  - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
> > -- reg : specifies base physical address and size of the registers.
> > -- interrupts : should be the gpt interrupt.
> > -- clocks : the clocks provided by the SoC to drive the timer, must contain
> > -           an entry for each entry in clock-names.
> > -- clock-names : must include "ipg" entry first, then "per" entry.
> > -
> > -Example:
> > -
> > -gpt1: timer@10003000 {
> > -	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
> > -	reg = <0x10003000 0x1000>;
> > -	interrupts = <26>;
> > -	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
> > -		 <&clks IMX27_CLK_PER1_GATE>;
> > -	clock-names = "ipg", "per";
> > -};
> > diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
> > b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
> > new file mode 100644
> > index 0000000..5c7186b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
> > @@ -0,0 +1,109 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +title: Freescale i.MX General Purpose Timer (GPT)
> > +
> > +maintainers:
> > +  - Sascha Hauer <s.hauer@pengutronix.de>
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - description: on i.MX1 the following compatible must be
> > +specified
> 
> Such a description seems not necessary in order to make the doc more clean

You meant the description is NOT necessary for those simple compatible string platforms or for
all platforms, I feel like having the description is more clear for users.

Anson
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* Re: [V6, 1/2] media: dt-bindings: media: i2c: Document DW9768 bindings
From: Dongchun Zhu @ 2020-05-19  3:10 UTC (permalink / raw)
  To: Rob Herring
  Cc: Mark Rutland, linux-devicetree, Andy Shevchenko, Louis Kuo,
	srv_heupstream, Linus Walleij,
	Shengnan Wang (王圣男), Tomasz Figa,
	Bartosz Golaszewski, Sj Huang, Nicolas Boichat,
	moderated list:ARM/Mediatek SoC support, Sakari Ailus,
	Matthias Brugger, Cao Bing Bu, Mauro Carvalho Chehab,
	list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg  Roedel <joro@8bytes.org>, ,
	Linux Media Mailing List
In-Reply-To: <20200518143148.GA18032@bogus>

Hi Tomasz, Rob,

Thanks for the timely review and good suggestions.

On Mon, 2020-05-18 at 08:31 -0600, Rob Herring wrote:
> On Mon, May 18, 2020 at 04:12:28PM +0200, Tomasz Figa wrote:
> > Hi Dongchun,
> > 
> > On Mon, May 18, 2020 at 3:29 PM Dongchun Zhu <dongchun.zhu@mediatek.com> wrote:
> > >
> > > Add DeviceTree binding documentation for Dongwoon Anatech DW9768 voice
> > > coil actuator.
> > 
> > Thanks for the patch. Please see my comments below.
> > 
> > >
> > > Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > 
> > This version includes significant changes, so the reviewed-by tag
> > shouldn't have been carried out.
> > 

Sorry, this is my fault.
In fact, I've struggled with it at the beginning.
Yes, you are right.
Now the new version of patch-set includes huge changes relative to the
last edition.
It would be removed in next release.

> > > ---
> > >  .../bindings/media/i2c/dongwoon,dw9768.yaml        | 105 +++++++++++++++++++++
> > >  MAINTAINERS                                        |   7 ++
> > >  2 files changed, 112 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/media/i2c/dongwoon,dw9768.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9768.yaml b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9768.yaml
> > > new file mode 100644
> > > index 0000000..b909e83
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9768.yaml
> > > @@ -0,0 +1,105 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +# Copyright (c) 2020 MediaTek Inc.
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9768.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Dongwoon Anatech DW9768 Voice Coil Motor (VCM) Lens Device Tree Bindings
> > > +
> > > +maintainers:
> > > +  - Dongchun Zhu <dongchun.zhu@mediatek.com>
> > > +
> > > +description: |-
> > > +  The Dongwoon DW9768 is a single 10-bit digital-to-analog (DAC) converter
> > > +  with 100 mA output current sink capability. VCM current is controlled with
> > > +  a linear mode driver. The DAC is controlled via a 2-wire (I2C-compatible)
> > > +  serial interface that operates at clock rates up to 1MHz. This chip
> > > +  integrates Advanced Actuator Control (AAC) technology and is intended for
> > > +  driving voice coil lenses in camera modules.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      # for DW9768 VCM
> > > +      - dongwoon,dw9768
> > > +      # for GT9769 VCM
> > > +      - giantec,gt9769
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  vin-supply:
> > > +    description:
> > > +      Definition of the regulator used as I2C I/O interface power supply.
> > > +
> > > +  vdd-supply:
> > > +    description:
> > > +      Definition of the regulator used as VCM chip power supply.
> > > +
> > > +  dongwoon,aac-mode:
> > > +    description:
> > > +      Indication of AAC mode select.
> > > +    allOf:
> > > +      - $ref: "/schemas/types.yaml#/definitions/uint32"
> > > +      - enum:
> > > +          - 0    #  Direct (default)
> 
> Default can be expressed as 'default: 0'.
> 

Thanks for the reminder.
Next release I'd try to write DT property "dongwoon,aac-mode" like this:
dongwoon,aac-mode:
  description:
    Indication of AAC mode select.
  allOf:
    - $ref: "/schemas/types.yaml#/definitions/uint32"
    - enum:
        - 0  # Direct
        - 1  # AAC2 (operation time# 0.48 x Tvib)
        - 2  # AAC3 (operation time# 0.70 x Tvib)
        - 3  # AAC4 (operation time# 0.75 x Tvib)
        - 5  # AAC8 (operation time# 1.13 x Tvib)
      default: 0

> > > +          - 1    #  AAC2 (operation time# 0.48 x Tvib)
> > > +          - 2    #  AAC3 (operation time# 0.70 x Tvib)
> > > +          - 3    #  AAC4 (operation time# 0.75 x Tvib)
> > > +          - 4    #  Reserved
> > > +          - 5    #  AAC8 (operation time# 1.13 x Tvib)
> > > +          - 6    #  Reserved
> > > +          - 7    #  Reserved
> > 
> > I'll ultimately leave it to DT maintainers, but is there any reason to
> > define the reserved values?
> 
> No.
> 
> > 
> > > +
> > > +  dongwoon,aac-timing:
> > > +    description:
> > > +      Indication of AAC Timing count, unit of 0.1 milliseconds.
> 
> Why not just use standard units (-us)?
> 

That sounds nice.
I'd re-write the description like this in next release:
dongwoon,aac-timing:
  description:
    Number of AAC Timing count that controlled by one 6-bit period
    of vibration register AACT[5:0], the unit of which is 100us.
  allOf:
    - $ref: "/schemas/types.yaml#/definitions/uint32"
    - minimum: 0x00
    - maximum: 0x3F
    - default: 0x20

> > > +      Valid values vary from 0 to 63 (default 32).
> 
> Looks like constraints.
> 

Yes. This property is controlled by one 6-bit reg.
So here we need to constrain the data set to a narrow range.

> > > +    allOf:
> > > +      - $ref: "/schemas/types.yaml#/definitions/uint32"
> > > +
> > > +  dongwoon,clock-dividing-rate:
> > > +    description:
> > > +      Indication of VCM internal clock dividing rate select, as one multiple
> > > +      factor to calculate VCM ring periodic time Tvib.
> > > +    allOf:
> > > +      - $ref: "/schemas/types.yaml#/definitions/uint32"
> > > +      - enum:
> > > +          - 0    #  Dividing Rate -  2
> > > +          - 1    #  Dividing Rate -  1 (default)
> > > +          - 2    #  Dividing Rate -  1/2
> > > +          - 3    #  Dividing Rate -  1/4
> > > +          - 4    #  Dividing Rate -  8
> > > +          - 5    #  Dividing Rate -  4
> > > +          - 6    #  Dividing Rate -  Reserved
> > > +          - 7    #  Dividing Rate -  Reserved
> > 
> > Ditto.
> > 

Thanks for kindly reminder.
Reserved values would be removed in next release.
Like this:
dongwoon,clock-dividing-rate:
  description:
    Indication of VCM internal clock dividing rate select, as one    
    multiplier to calculate VCM ring periodic time Tvib.
  allOf:
    - $ref: "/schemas/types.yaml#/definitions/uint32"
    - enum:
        - 0   #  Dividing Rate -  2
        - 1   #  Dividing Rate -  1
        - 2    #  Dividing Rate -  1/2
        - 3    #  Dividing Rate -  1/4
        - 4    #  Dividing Rate -  8
        - 5    #  Dividing Rate -  4
      default: 1

> > Best regards,
> > Tomasz

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* Re: [PATCH v2 1/3] mm/memory-failure: Add memory_failure_queue_kick()
From: HORIGUCHI NAOYA(堀口 直也) @ 2020-05-19  3:15 UTC (permalink / raw)
  To: Andrew Morton
  Cc: Mark Rutland, Tony Luck, linux-mm@kvack.org, Catalin Marinas,
	Xie XiuQi, Rafael J. Wysocki, linux-acpi@vger.kernel.org,
	Tyler Baicar, James Morse, Borislav Petkov, Naoya Horiguchi,
	Will Deacon, linux-arm-kernel@lists.infradead.org, Len Brown
In-Reply-To: <20200518125828.e4e3973c743556e976c5ee65@linux-foundation.org>

On Mon, May 18, 2020 at 12:58:28PM -0700, Andrew Morton wrote:
> On Mon, 18 May 2020 14:45:05 +0200 "Rafael J. Wysocki" <rjw@rjwysocki.net> wrote:
> 
> > On Friday, May 1, 2020 6:45:41 PM CEST James Morse wrote:
> > > The GHES code calls memory_failure_queue() from IRQ context to schedule
> > > work on the current CPU so that memory_failure() can sleep.
> > > 
> > > For synchronous memory errors the arch code needs to know any signals
> > > that memory_failure() will trigger are pending before it returns to
> > > user-space, possibly when exiting from the IRQ.
> > > 
> > > Add a helper to kick the memory failure queue, to ensure the scheduled
> > > work has happened. This has to be called from process context, so may
> > > have been migrated from the original cpu. Pass the cpu the work was
> > > queued on.
> > > 
> > > Change memory_failure_work_func() to permit being called on the 'wrong'
> > > cpu.
> > > 
> > > --- a/include/linux/mm.h
> > > +++ b/include/linux/mm.h
> > > @@ -3012,6 +3012,7 @@ enum mf_flags {
> > >  };
> > >  extern int memory_failure(unsigned long pfn, int flags);
> > >  extern void memory_failure_queue(unsigned long pfn, int flags);
> > > +extern void memory_failure_queue_kick(int cpu);
> > >  extern int unpoison_memory(unsigned long pfn);
> > >  extern int get_hwpoison_page(struct page *page);
> > >  #define put_hwpoison_page(page)	put_page(page)
> > > diff --git a/mm/memory-failure.c b/mm/memory-failure.c
> > > index a96364be8ab4..c4afb407bf0f 100644
> > > --- a/mm/memory-failure.c
> > > +++ b/mm/memory-failure.c
> > > @@ -1493,7 +1493,7 @@ static void memory_failure_work_func(struct work_struct *work)
> > >  	unsigned long proc_flags;
> > >  	int gotten;
> > >  
> > > -	mf_cpu = this_cpu_ptr(&memory_failure_cpu);
> > > +	mf_cpu = container_of(work, struct memory_failure_cpu, work);
> > >  	for (;;) {
> > >  		spin_lock_irqsave(&mf_cpu->lock, proc_flags);
> > >  		gotten = kfifo_get(&mf_cpu->fifo, &entry);
> > > @@ -1507,6 +1507,19 @@ static void memory_failure_work_func(struct work_struct *work)
> > >  	}
> > >  }
> > >  
> > > +/*
> > > + * Process memory_failure work queued on the specified CPU.
> > > + * Used to avoid return-to-userspace racing with the memory_failure workqueue.
> > > + */
> > > +void memory_failure_queue_kick(int cpu)
> > > +{
> > > +	struct memory_failure_cpu *mf_cpu;
> > > +
> > > +	mf_cpu = &per_cpu(memory_failure_cpu, cpu);
> > > +	cancel_work_sync(&mf_cpu->work);
> > > +	memory_failure_work_func(&mf_cpu->work);
> > > +}
> > > +
> > >  static int __init memory_failure_init(void)
> > >  {
> > >  	struct memory_failure_cpu *mf_cpu;
> > > 
> > 
> > I could apply this provided an ACK from the mm people.
> > 
> 
> Naoya Horiguchi is the memory-failure.c person.  A review would be
> appreciated please?
> 
> I'm struggling with it a bit.  memory_failure_queue_kick() should be
> called on the cpu which is identified by arg `cpu', yes? 
> memory_failure_work_func() appears to assume this.
> 
> If that's right then a) why bother passing in the `cpu' arg?  and b)
> what keeps this thread pinned to that CPU?  cancel_work_sync() can
> schedule.

If I read correctly, memory_failure work is queue on the CPU on which the
user process ran when it touched the corrupted memory, and the process can
be scheduled on another CPU when the kernel returned back to userspace after
handling the GHES event.  So we need to remember where the memory_failure
event is queued to flush proper work queue.  So I feel that this properly
implements it.

Considering the effect to the other caller, currently memory_failure_queue()
has 2 callers, ghes_handle_memory_failure() and cec_add_elem(). The former
is what we try to change now.  And the latter is to execute soft offline
(which is related to corrected non-fatal errors), so that's not affected by
the reported issue.  So I don't think that this change breaks the other
caller.

So I'm fine with the suggested change.

Acked-by: Naoya Horiguchi <naoya.horiguchi@nec.com>

Thanks,
Naoya Horiguchi
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* RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
From: Qiang Zhao @ 2020-05-19  3:37 UTC (permalink / raw)
  To: Gustavo A. R. Silva, Leo Li
  Cc: Kees Cook, linuxppc-dev@lists.ozlabs.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, Gustavo A. R. Silva
In-Reply-To: <20200518221904.GA22274@embeddedor>


On 2020/5/19 6:19, Gustavo A. R. Silva <gustavoars@kernel.org> wrote:

> -----Original Message-----
> From: Gustavo A. R. Silva <gustavoars@kernel.org>
> Sent: 2020年5月19日 6:19
> To: Qiang Zhao <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Gustavo A. R. Silva <gustavo@embeddedor.com>;
> Kees Cook <keescook@chromium.org>
> Subject: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size()
> helper
> 
> The current codebase makes use of one-element arrays in the following
> form:
> 
> struct something {
>     int length;
>     u8 data[1];
> };
> 
> struct something *instance;
> 
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
> 
> but the preferred mechanism to declare variable-length types such as these
> ones is a flexible array member[1][2], introduced in C99:
> 
> struct foo {
>         int stuff;
>         struct boo array[];
> };
> 
> By making use of the mechanism above, we will get a compiler warning in case
> the flexible array does not occur last in the structure, which will help us prevent
> some kind of undefined behavior bugs from being inadvertently introduced[3]
> to the codebase from now on. So, replace the one-element array with a
> flexible-array member.
> 
> Also, make use of the new struct_size() helper to properly calculate the size of
> struct qe_firmware.
> 
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
> 
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.
> org%2Fonlinedocs%2Fgcc%2FZero-Length.html&amp;data=02%7C01%7Cqiang.
> zhao%40nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C637254368610203908&amp;sdata=70
> a6VBg3oWQf9a5KICuCEuIj6gw57NKYhNv2JL8JdDY%3D&amp;reserved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2FKSPP%2Flinux%2Fissues%2F21&amp;data=02%7C01%7Cqiang.zhao%40
> nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b4c6fa92c
> d99c5c301635%7C0%7C0%7C637254368610213901&amp;sdata=kVyNBYHbm
> a5jCO9pbkoHMetHEYGvWDq6Xw%2BBeC7uHII%3D&amp;reserved=0
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
> 
> Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
> ---
>  drivers/soc/fsl/qe/qe.c | 4 ++--
>  include/soc/fsl/qe/qe.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
>  	unsigned int i;
>  	unsigned int j;
>  	u32 crc;
> -	size_t calc_size = sizeof(struct qe_firmware);
> +	size_t calc_size;
>  	size_t length;
>  	const struct qe_header *hdr;
> 
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
>  	}
> 
>  	/* Validate the length and check if there's a CRC */
> -	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> +	calc_size = struct_size(firmware, microcode, firmware->count);
> 
>  	for (i = 0; i < firmware->count; i++)
>  		/*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index
> e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
>  		u8 revision;		/* The microcode version revision */
>  		u8 padding;		/* Reserved, for alignment */
>  		u8 reserved[4];		/* Reserved, for future expansion */
> -	} __attribute__ ((packed)) microcode[1];
> +	} __packed microcode[];
>  	/* All microcode binaries should be located here */
>  	/* CRC32 should be located here, after the microcode binaries */  }
> __attribute__ ((packed));
> --
> 2.26.2
[>] 

Reviewed-by: Qiang Zhao <qiang.zhao@nxp.com>

Best Regards
Qiang Zhao

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* Re: [RFC] dt-bindings: mailbox: add doorbell support to ARM MHU
From: Viresh Kumar @ 2020-05-19  3:40 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: devicetree, Arnd Bergmann, Jassi Brar, linux-kernel, Rob Herring,
	Sudeep Holla, Frank Rowand, linux-arm-kernel
In-Reply-To: <20200519012927.GT2165@builder.lan>

On 18-05-20, 18:29, Bjorn Andersson wrote:
> On Thu 14 May 22:17 PDT 2020, Viresh Kumar wrote:
> > This stuff has been doing rounds on the mailing list since several years
> > now with no agreed conclusion by all the parties. And here is another
> > attempt to get some feedback from everyone involved to close this once
> > and for ever. Your comments will very much be appreciated.
> > 
> > The ARM MHU is defined here in the TRM [1] for your reference, which
> > states following:
> > 
> > 	"The MHU drives the signal using a 32-bit register, with all 32
> > 	bits logically ORed together. The MHU provides a set of
> > 	registers to enable software to set, clear, and check the status
> > 	of each of the bits of this register independently.  The use of
> > 	32 bits for each interrupt line enables software to provide more
> > 	information about the source of the interrupt. For example, each
> > 	bit of the register can be associated with a type of event that
> > 	can contribute to raising the interrupt."
> > 
> 
> Does this mean that there are 32 different signals and they are all ORed
> into the same interrupt line to trigger software action when something
> happens?
> 
> Or does it mean that this register is used to pass multi-bit information
> and when any such information is passed an interrupt will be triggered?
> If so, what does that information mean? How is it tied into other Linux
> drivers/subsystems?

I have started to believe the hardware is written badly at this point
:)

The thing is that the register can be used to send a 32 bit data
(which the driver already provides), or it can be used by writing
different bits to the SET register concurrently, without corrupting
the other bits as writing 0 to a bit has no effect, we have a separate
CLEAR register for that. And so it says that all the bits are ORed
together to generate the interrupt, i.e. any bit set will generate an
interrupt. Which also means that you can't send data 0 with the
register.

-- 
viresh

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* [PATCH V3] dt-bindings: reset: Convert i.MX reset to json-schema
From: Anson Huang @ 2020-05-19  3:42 UTC (permalink / raw)
  To: p.zabel, robh+dt, shawnguo, s.hauer, kernel, festevam, devicetree,
	linux-arm-kernel, linux-kernel
  Cc: Linux-imx

Convert the i.MX reset binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Changes since V2:
	- remove unnecessary compatible item descriptions.
---
 .../devicetree/bindings/reset/fsl,imx-src.txt      | 49 -------------
 .../devicetree/bindings/reset/fsl,imx-src.yaml     | 82 ++++++++++++++++++++++
 2 files changed, 82 insertions(+), 49 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/reset/fsl,imx-src.txt
 create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx-src.yaml

diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
deleted file mode 100644
index 6ed79e6..0000000
--- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Freescale i.MX System Reset Controller
-======================================
-
-Please also refer to reset.txt in this directory for common reset
-controller binding usage.
-
-Required properties:
-- compatible: Should be "fsl,<chip>-src"
-- reg: should be register base and length as documented in the
-  datasheet
-- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
-  in this order.
-- #reset-cells: 1, see below
-
-example:
-
-src: src@20d8000 {
-        compatible = "fsl,imx6q-src";
-        reg = <0x020d8000 0x4000>;
-        interrupts = <0 91 0x04 0 96 0x04>;
-        #reset-cells = <1>;
-};
-
-Specifying reset lines connected to IP modules
-==============================================
-
-The system reset controller can be used to reset the GPU, VPU,
-IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
-nodes should specify the reset line on the SRC in their resets
-property, containing a phandle to the SRC device node and a
-RESET_INDEX specifying which module to reset, as described in
-reset.txt
-
-example:
-
-        ipu1: ipu@2400000 {
-                resets = <&src 2>;
-        };
-        ipu2: ipu@2800000 {
-                resets = <&src 4>;
-        };
-
-The following RESET_INDEX values are valid for i.MX5:
-GPU_RESET     0
-VPU_RESET     1
-IPU1_RESET    2
-OPEN_VG_RESET 3
-The following additional RESET_INDEX value is valid for i.MX6:
-IPU2_RESET    4
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
new file mode 100644
index 0000000..27c5e34
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX System Reset Controller
+
+maintainers:
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  The system reset controller can be used to reset the GPU, VPU,
+  IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
+  nodes should specify the reset line on the SRC in their resets
+  property, containing a phandle to the SRC device node and a
+  RESET_INDEX specifying which module to reset, as described in
+  reset.txt
+
+  The following RESET_INDEX values are valid for i.MX5:
+    GPU_RESET     0
+    VPU_RESET     1
+    IPU1_RESET    2
+    OPEN_VG_RESET 3
+  The following additional RESET_INDEX value is valid for i.MX6:
+    IPU2_RESET    4
+
+properties:
+  compatible:
+    oneOf:
+      - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx50-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx53-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx6q-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx6sx-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx6sl-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx6ul-src"
+          - const: "fsl,imx51-src"
+      - items:
+          - const: "fsl,imx6sll-src"
+          - const: "fsl,imx51-src"
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: SRC interrupt
+      - description: CPU WDOG interrupts out of SRC
+    minItems: 1
+    maxItems: 2
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@73fd0000 {
+        compatible = "fsl,imx51-src";
+        reg = <0x73fd0000 0x4000>;
+        interrupts = <75>;
+        #reset-cells = <1>;
+    };
-- 
2.7.4


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* Re: [RFC] dt-bindings: mailbox: add doorbell support to ARM MHU
From: Jassi Brar @ 2020-05-19  4:05 UTC (permalink / raw)
  To: Viresh Kumar
  Cc: Devicetree List, Arnd Bergmann, Linux Kernel Mailing List,
	Bjorn Andersson, Rob Herring, Sudeep Holla, Frank Rowand,
	linux-arm-kernel
In-Reply-To: <20200519034055.hfvifqz442yfduhg@vireshk-i7>

On Mon, May 18, 2020 at 10:40 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 18-05-20, 18:29, Bjorn Andersson wrote:
> > On Thu 14 May 22:17 PDT 2020, Viresh Kumar wrote:
> > > This stuff has been doing rounds on the mailing list since several years
> > > now with no agreed conclusion by all the parties. And here is another
> > > attempt to get some feedback from everyone involved to close this once
> > > and for ever. Your comments will very much be appreciated.
> > >
> > > The ARM MHU is defined here in the TRM [1] for your reference, which
> > > states following:
> > >
> > >     "The MHU drives the signal using a 32-bit register, with all 32
> > >     bits logically ORed together. The MHU provides a set of
> > >     registers to enable software to set, clear, and check the status
> > >     of each of the bits of this register independently.  The use of
> > >     32 bits for each interrupt line enables software to provide more
> > >     information about the source of the interrupt. For example, each
> > >     bit of the register can be associated with a type of event that
> > >     can contribute to raising the interrupt."
> > >
> >
> > Does this mean that there are 32 different signals and they are all ORed
> > into the same interrupt line to trigger software action when something
> > happens?
> >
> > Or does it mean that this register is used to pass multi-bit information
> > and when any such information is passed an interrupt will be triggered?
> > If so, what does that information mean? How is it tied into other Linux
> > drivers/subsystems?
>
> I have started to believe the hardware is written badly at this point
> :)
>
H/W is actually fine :)   Its just that the driver is written to
_also_ support a platform (my original) that doesn't have shmem and
need to pass data via 32bit registers.
Frankly, I am not against the doorbell mode, I am against implementing
two modes in a driver. If it really helped (note the past tense) the
SCMI, we could implement the driver only in doorbell mode but
unfortunately SCMI would still be _broken_ for non-doorbell
controllers.

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* [PATCH V2 0/3] Covert i.MX GPT/TPM/SYSCTR timer binding to json-schema
From: Anson Huang @ 2020-05-19  3:55 UTC (permalink / raw)
  To: daniel.lezcano, tglx, robh+dt, shawnguo, s.hauer, kernel,
	festevam, ping.bai, aisheng.dong, linux-kernel, devicetree,
	linux-arm-kernel
  Cc: Linux-imx

This patch series converts i.MX GPT, TPM and system counter timer
binding to json-schema, test build passed.

Changes compared to V1 are listed in each patch.

Anson Huang (3):
  dt-bindings: timer: Convert i.MX GPT to json-schema
  dt-bindings: timer: Convert i.MX TPM to json-schema
  dt-bindings: timer: Convert i.MX SYSCTR to json-schema

 .../devicetree/bindings/timer/fsl,imxgpt.txt       | 45 ------------
 .../devicetree/bindings/timer/fsl,imxgpt.yaml      | 80 ++++++++++++++++++++++
 .../devicetree/bindings/timer/nxp,sysctr-timer.txt | 25 -------
 .../bindings/timer/nxp,sysctr-timer.yaml           | 54 +++++++++++++++
 .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 --------
 .../devicetree/bindings/timer/nxp,tpm-timer.yaml   | 61 +++++++++++++++++
 6 files changed, 195 insertions(+), 98 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
 create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
 delete mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
 delete mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml

-- 
2.7.4


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* [PATCH V2 1/3] dt-bindings: timer: Convert i.MX GPT to json-schema
From: Anson Huang @ 2020-05-19  3:55 UTC (permalink / raw)
  To: daniel.lezcano, tglx, robh+dt, shawnguo, s.hauer, kernel,
	festevam, ping.bai, aisheng.dong, linux-kernel, devicetree,
	linux-arm-kernel
  Cc: Linux-imx
In-Reply-To: <1589860547-3207-1-git-send-email-Anson.Huang@nxp.com>

Convert the i.MX GPT binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
	- remove unnecessary compatible item descriptions;
	- remove unnecessary maxItems for clocks/clock-names;
---
 .../devicetree/bindings/timer/fsl,imxgpt.txt       | 45 ------------
 .../devicetree/bindings/timer/fsl,imxgpt.yaml      | 80 ++++++++++++++++++++++
 2 files changed, 80 insertions(+), 45 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
 create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml

diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
deleted file mode 100644
index 5d8fd5b..0000000
--- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Freescale i.MX General Purpose Timer (GPT)
-
-Required properties:
-
-- compatible : should be one of following:
-  for i.MX1:
-  - "fsl,imx1-gpt";
-  for i.MX21:
-  - "fsl,imx21-gpt";
-  for i.MX27:
-  - "fsl,imx27-gpt", "fsl,imx21-gpt";
-  for i.MX31:
-  - "fsl,imx31-gpt";
-  for i.MX25:
-  - "fsl,imx25-gpt", "fsl,imx31-gpt";
-  for i.MX50:
-  - "fsl,imx50-gpt", "fsl,imx31-gpt";
-  for i.MX51:
-  - "fsl,imx51-gpt", "fsl,imx31-gpt";
-  for i.MX53:
-  - "fsl,imx53-gpt", "fsl,imx31-gpt";
-  for i.MX6Q:
-  - "fsl,imx6q-gpt", "fsl,imx31-gpt";
-  for i.MX6DL:
-  - "fsl,imx6dl-gpt";
-  for i.MX6SL:
-  - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
-  for i.MX6SX:
-  - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
-- reg : specifies base physical address and size of the registers.
-- interrupts : should be the gpt interrupt.
-- clocks : the clocks provided by the SoC to drive the timer, must contain
-           an entry for each entry in clock-names.
-- clock-names : must include "ipg" entry first, then "per" entry.
-
-Example:
-
-gpt1: timer@10003000 {
-	compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
-	reg = <0x10003000 0x1000>;
-	interrupts = <26>;
-	clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
-		 <&clks IMX27_CLK_PER1_GATE>;
-	clock-names = "ipg", "per";
-};
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
new file mode 100644
index 0000000..5479290
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/fsl,imxgpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX General Purpose Timer (GPT)
+
+maintainers:
+  - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+  compatible:
+    oneOf:
+      - const: "fsl,imx1-gpt"
+      - const: "fsl,imx21-gpt"
+      - items:
+          - const: "fsl,imx27-gpt"
+          - const: "fsl,imx21-gpt"
+      - const: "fsl,imx31-gpt"
+      - items:
+          - const: "fsl,imx25-gpt"
+          - const: "fsl,imx31-gpt"
+      - items:
+          - const: "fsl,imx50-gpt"
+          - const: "fsl,imx31-gpt"
+      - items:
+          - const: "fsl,imx51-gpt"
+          - const: "fsl,imx31-gpt"
+      - items:
+          - const: "fsl,imx53-gpt"
+          - const: "fsl,imx31-gpt"
+      - items:
+          - const: "fsl,imx6q-gpt"
+          - const: "fsl,imx31-gpt"
+      - const: "fsl,imx6dl-gpt"
+      - items:
+          - const: "fsl,imx6sl-gpt"
+          - const: "fsl,imx6dl-gpt"
+      - items:
+          - const: "fsl,imx6sx-gpt"
+          - const: "fsl,imx6dl-gpt"
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: SoC GPT ipg clock
+      - description: SoC GPT per clock
+
+  clock-names:
+    items:
+      - const: ipg
+      - const: per
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx27-clock.h>
+
+    timer@10003000 {
+        compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
+        reg = <0x10003000 0x1000>;
+        interrupts = <26>;
+        clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
+                 <&clks IMX27_CLK_PER1_GATE>;
+        clock-names = "ipg", "per";
+    };
-- 
2.7.4


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* [PATCH V2 3/3] dt-bindings: timer: Convert i.MX SYSCTR to json-schema
From: Anson Huang @ 2020-05-19  3:55 UTC (permalink / raw)
  To: daniel.lezcano, tglx, robh+dt, shawnguo, s.hauer, kernel,
	festevam, ping.bai, aisheng.dong, linux-kernel, devicetree,
	linux-arm-kernel
  Cc: Linux-imx
In-Reply-To: <1589860547-3207-1-git-send-email-Anson.Huang@nxp.com>

Convert the i.MX SYSCTR binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
No changes.
---
 .../devicetree/bindings/timer/nxp,sysctr-timer.txt | 25 ----------
 .../bindings/timer/nxp,sysctr-timer.yaml           | 54 ++++++++++++++++++++++
 2 files changed, 54 insertions(+), 25 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
deleted file mode 100644
index d576599..0000000
--- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-NXP System Counter Module(sys_ctr)
-
-The system counter(sys_ctr) is a programmable system counter which provides
-a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in
-applications where the counter is always powered and support multiple,
-unrelated clocks. The compare frame inside can be used for timer purpose.
-
-Required properties:
-
-- compatible :      should be "nxp,sysctr-timer"
-- reg :             Specifies the base physical address and size of the comapre
-                    frame and the counter control, read & compare.
-- interrupts :      should be the first compare frames' interrupt
-- clocks : 	    Specifies the counter clock.
-- clock-names: 	    Specifies the clock's name of this module
-
-Example:
-
-	system_counter: timer@306a0000 {
-		compatible = "nxp,sysctr-timer";
-		reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */
-		clocks = <&clk_8m>;
-		clock-names = "per";
-		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-	};
diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
new file mode 100644
index 0000000..830211c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP System Counter Module(sys_ctr)
+
+maintainers:
+  - Bai Ping <ping.bai@nxp.com>
+
+description: |
+  The system counter(sys_ctr) is a programmable system counter
+  which provides a shared time base to Cortex A15, A7, A53, A73,
+  etc. it is intended for use in applications where the counter
+  is always powered and support multiple, unrelated clocks. The
+  compare frame inside can be used for timer purpose.
+
+properties:
+  compatible:
+    const: nxp,sysctr-timer
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: per
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    timer@306a0000 {
+        compatible = "nxp,sysctr-timer";
+        reg = <0x306a0000 0x20000>;
+        clocks = <&clk_8m>;
+        clock-names = "per";
+        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+     };
-- 
2.7.4


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* [PATCH V2 2/3] dt-bindings: timer: Convert i.MX TPM to json-schema
From: Anson Huang @ 2020-05-19  3:55 UTC (permalink / raw)
  To: daniel.lezcano, tglx, robh+dt, shawnguo, s.hauer, kernel,
	festevam, ping.bai, aisheng.dong, linux-kernel, devicetree,
	linux-arm-kernel
  Cc: Linux-imx
In-Reply-To: <1589860547-3207-1-git-send-email-Anson.Huang@nxp.com>

Convert the i.MX TPM binding to DT schema format using json-schema.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Changes since V1:
	- remove unnecessary maxItems for clocks/clock-names.
---
 .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 ----------
 .../devicetree/bindings/timer/nxp,tpm-timer.yaml   | 61 ++++++++++++++++++++++
 2 files changed, 61 insertions(+), 28 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
deleted file mode 100644
index f82087b..0000000
--- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-NXP Low Power Timer/Pulse Width Modulation Module (TPM)
-
-The Timer/PWM Module (TPM) supports input capture, output compare,
-and the generation of PWM signals to control electric motor and power
-management applications. The counter, compare and capture registers
-are clocked by an asynchronous clock that can remain enabled in low
-power modes. TPM can support global counter bus where one TPM drives
-the counter bus for the others, provided bit width is the same.
-
-Required properties:
-
-- compatible :	should be "fsl,imx7ulp-tpm"
-- reg :		Specifies base physical address and size of the register sets
-		for the clock event device and clock source device.
-- interrupts :	Should be the clock event device interrupt.
-- clocks :	The clocks provided by the SoC to drive the timer, must contain
-		an entry for each entry in clock-names.
-- clock-names : Must include the following entries: "ipg" and "per".
-
-Example:
-tpm5: tpm@40260000 {
-	compatible = "fsl,imx7ulp-tpm";
-	reg = <0x40260000 0x1000>;
-	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-	clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
-		 <&clks IMX7ULP_CLK_LPTPM5>;
-	clock-names = "ipg", "per";
-};
diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
new file mode 100644
index 0000000..edd9585
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+maintainers:
+  - Dong Aisheng <aisheng.dong@nxp.com>
+
+description: |
+  The Timer/PWM Module (TPM) supports input capture, output compare,
+  and the generation of PWM signals to control electric motor and power
+  management applications. The counter, compare and capture registers
+  are clocked by an asynchronous clock that can remain enabled in low
+  power modes. TPM can support global counter bus where one TPM drives
+  the counter bus for the others, provided bit width is the same.
+
+properties:
+  compatible:
+    const: fsl,imx7ulp-tpm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: SoC TPM ipg clock
+      - description: SoC TPM per clock
+
+  clock-names:
+    items:
+      - const: ipg
+      - const: per
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx7ulp-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    timer@40260000 {
+        compatible = "fsl,imx7ulp-tpm";
+        reg = <0x40260000 0x1000>;
+        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+                 <&pcc2 IMX7ULP_CLK_LPTPM5>;
+        clock-names = "ipg", "per";
+    };
-- 
2.7.4


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* Re: [RFC] dt-bindings: mailbox: add doorbell support to ARM MHU
From: Viresh Kumar @ 2020-05-19  4:39 UTC (permalink / raw)
  To: Jassi Brar
  Cc: Devicetree List, Arnd Bergmann, Linux Kernel Mailing List,
	Bjorn Andersson, Rob Herring, Sudeep Holla, Frank Rowand,
	linux-arm-kernel
In-Reply-To: <CABb+yY0vihfQSi=067AUNZd8sHACJ_4CKvFvsoCfweVuL=RD0g@mail.gmail.com>

On 18-05-20, 19:53, Jassi Brar wrote:
> That is a client/protocol property and has nothing to do with the
> controller dt node.

That's what I am concerned about, i.e. different ways of passing the
doorbell number via DT.

-- 
viresh

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* RE: [PATCH V2 1/3] dt-bindings: timer: Convert i.MX GPT to json-schema
From: Aisheng Dong @ 2020-05-19  5:08 UTC (permalink / raw)
  To: Anson Huang, daniel.lezcano@linaro.org, tglx@linutronix.de,
	robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, Jacky Bai,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
  Cc: dl-linux-imx
In-Reply-To: <1589860547-3207-2-git-send-email-Anson.Huang@nxp.com>

> From: Anson Huang <Anson.Huang@nxp.com>
> Sent: Tuesday, May 19, 2020 11:56 AM
> 
> Convert the i.MX GPT binding to DT schema format using json-schema.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng
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* [GIT PULL] Qualcomm ARM64 defconfig updates for v5.8
From: Bjorn Andersson @ 2020-05-19  5:25 UTC (permalink / raw)
  To: arm, soc
  Cc: Arnd Bergmann, linux-arm-msm, Alex Elder, Robert Foss, Vinod Koul,
	Andy Gross, Kevin Hilman, Olof Johansson, linux-arm-kernel

The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:

  Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-defconfig-for-5.8

for you to fetch changes up to 5ef3c35809ec74ab41a5cf93a5b6d60167661113:

  arm64: defconfig: enable Qualcomm IPA and RMNet modules (2020-05-18 16:36:30 -0700)

----------------------------------------------------------------
Qualcomm ARM64 defconfig updates for v5.8

This enables SM8250 GCC clock driver, SC7180 GCC clock driver and SC7180
TLMM pinctrl driver, the IPA and RMNET drivers, CCI, camera subsystem
and camera clock drivers and removes the now depricated GLINK_SSR entry.

----------------------------------------------------------------
Alex Elder (1):
      arm64: defconfig: enable Qualcomm IPA and RMNet modules

Bjorn Andersson (2):
      arm64: defconfig: Remove QCOM_GLINK_SSR
      arm64: defconfig: Enable Qualcomm SC7180 pinctrl and gcc

Robert Foss (1):
      arm64: defconfig: Enable Qualcomm CAMCC, CAMSS and CCI drivers

Vinod Koul (1):
      arm64: defconfig: Enable SM8250 GCC driver

 arch/arm64/configs/defconfig | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

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* [GIT PULL] Qualcomm ARM64 DT updates for v5.8
From: Bjorn Andersson @ 2020-05-19  5:25 UTC (permalink / raw)
  To: arm, soc
  Cc: Maulik Shah, Ulf Hansson, Craig Tatlor, Sandeep Maheswaram,
	Rajeshwari, Amit Kucheria, Matthias Kaehlcke, Sai Prakash Ranjan,
	Arnd Bergmann, Jonathan Marek, Kevin Hilman, Evan Green,
	Andy Gross, Sibi Sankar, Alex Elder, Bryan O'Donoghue,
	Mike Leach, Alexey Minnekhanov, Stephan Gerhold, linux-arm-msm,
	Sharat Masetty, Sivaprakash Murugesan, Michael Srba,
	linux-arm-kernel, Krishna Manikandan, Loic Poulain,
	Rajendra Nayak, Douglas Anderson, Robert Foss, Olof Johansson

The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:

  Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-for-5.8

for you to fetch changes up to 7d2f29e49477aa51339e719cf73f0945c39c8a9e:

  arm64: dts: qcom: sc7180: Correct the pdc interrupt ranges (2020-05-18 20:08:35 -0700)

----------------------------------------------------------------
Qualcomm ARM64 DT updates for v5.8

For SDM845 this defines the IPA network accelerator and the CCI camera
control bus, it defines the required UFS reset and adds WiFi for the
Lenovo Yoga C630 and defines GPIO pin names and adds OV8856 and OC7251
camera nodes for DB845c.

For SC7180 it adds GPU support, defines the modem remoteproc, adds the
IPA network accelerator, Coresight and ETM support, adds cpuidle low
power states and updates the CPUs' compatible.

For SM8250 it adds regulators from the PM8150, PM8150L and PM8009 and
adds voltage corners, it defines the nodes for UFS PHY and controller
and finally corrects a typo in the PDC node to make SPMI functional.

For MSM8916 I2C1 and I2C5 are defined, a node for the CCI camera control
interface bus is added and Coresight is disabled by default to match
some product configurations. The Samsung A3U gained display support and
Samsung A5U gained touchscreen support.

MSM8996 now property describes the power supply chain for the GPU, the
CCI camera control interface bus is added and the DB820c has the
regulators of the secondary PMIC defined.

For QCS404 USB PHYs and controllers are defined and wired up for the
EVB.

SDM630/SDM660 platform support is added and the Xiaomi Redmi Note 7
defined.

It also contains a number of changes throughout to improve DT binding
compliance.

----------------------------------------------------------------
Alex Elder (2):
      arm64: dts: sdm845: add IPA iommus property
      arm64: dts: qcom: sc7180: add IPA information

Alexey Minnekhanov (2):
      dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs
      arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender)

Amit Kucheria (5):
      dt-bindings: arm: cpus: Add kryo468 compatible
      arm64: dts: qcom: sc7180: Fix cpu compatible
      arm64: dts: qcom: msm8916: remove unit name for thermal trip points
      arm64: dts: qcom: msm8996: remove unit name for thermal trip points
      arm64: dts: qcom: msm8998: remove unit name for thermal trip points

Bjorn Andersson (9):
      arm64: dts: qcom: qcs404: Add USB devices and PHYs
      arm64: dts: qcom: sm8250: Add rpmhpd node
      arm64: dts: qcom: sm8250: Fix PDC compatible and reg
      arm64: dts: qcom: db820c: Add pmi8994 RPM regulators
      arm64: dts: qcom: db820c: Fix invalid pm8994 supplies
      arm64: dts: qcom: c630: Add WiFi node
      arm64: dts: qcom: c630: Specify UFS device reset
      arm64: dts: qcom: msm8996: Make GPU node control GPU_GX GDSC
      arm64: dts: qcom: sc7180: Fix ETMv4 power management patch

Bryan O'Donoghue (7):
      arm64: dts: qcom: qcs404-evb: Define VBUS pins
      arm64: dts: qcom: qcs404-evb: Define USB ID pin
      arm64: dts: qcom: qcs404-evb: Describe external VBUS regulator
      arm64: dts: qcom: qcs404-evb: Raise vreg_l12_3p3 minimum voltage
      arm64: dts: qcom: qcs404-evb: Enable USB controllers
      arm64: dts: qcom: sm8250-mtp: Add pm8150, pm8150l and pm8009
      arm64: dts: qcom: sm8250: Add UFS controller and PHY

Craig Tatlor (1):
      arm64: dts: qcom: Add SDM660 SoC support

Douglas Anderson (3):
      arm64: dts: qcom: sc7180: Swap order of gpucc and sdhc_2
      arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on cheza
      arm64: dts: qcom: sc7180: Add "no-map" to cmd_db reserved area

Evan Green (1):
      arm64: dts: qcom: sc7180: Include interconnect definitions

Jonathan Marek (1):
      arm64: dts: qcom: fix pm8150 gpio interrupts

Krishna Manikandan (1):
      arm64: dts: qcom: sc7180: modify assigned clocks for sc7180 target

Loic Poulain (4):
      arm64: dts: qcom: msm8916: Add i2c-qcom-cci node
      arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes
      arm64: dts: msm8996: Fix CSI IRQ types
      arch: arm64: dts: msm8996: Add CCI node

Matthias Kaehlcke (1):
      arm64: dts: qcom: sc7180: Add interconnect paths for the video codec

Maulik Shah (2):
      arm64: dts: qcom: sc7180: Add cpuidle low power states
      arm64: dts: qcom: sc7180: Correct the pdc interrupt ranges

Michael Srba (2):
      arm64: dts: qcom: msm8916: Disable coresight by default
      arm64: dts: qcom: msm8916-samsung-a3u: add nodes for display panel

Mike Leach (1):
      arm64: dts: qcom: msm8916: Add CTI options

Rajendra Nayak (1):
      arm64: dts: qcom: db820c: Add vdd_gfx and tie it into mmcc

Rajeshwari (1):
      arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node

Robert Foss (3):
      arm64: dts: qcom: sdm845: Add i2c-qcom-cci node
      arm64: dts: qcom: sdm845-db845c: Add pm_8998 gpio names
      arm64: dts: qcom: sdm845-db845c: Add ov8856 & ov7251 camera nodes

Sai Prakash Ranjan (2):
      arm64: dts: qcom: sc7180: Add Coresight support
      arm64: dts: qcom: sc7180: Support ETMv4 power management

Sandeep Maheswaram (3):
      arm64: dts: qcom: sdm845: Add generic QUSB2 V2 Phy compatible
      arm64: dts: qcom: sc7180: Add generic QUSB2 V2 Phy compatible
      arm64: dts: qcom: sc7180: Update QUSB2 V2 Phy params for SC7180 IDP device

Sharat Masetty (2):
      dt-bindings: arm-smmu: Add sc7180 compatible string
      arm64: dts: qcom: sc7180: Add A618 gpu dt blob

Sibi Sankar (4):
      arm64: dts: qcom: sdm845: Add SoC compatible to MTP
      arm64: dts: qcom: sc7180: Update reserved memory map
      arm64: dts: qcom: sc7180: Add Q6V5 MSS node
      arm64: dts: qcom: sc7180: Update Q6V5 MSS node

Sivaprakash Murugesan (1):
      arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on address

Stephan Gerhold (7):
      arm64: dts: qcom: msm8916: Add blsp_i2c1
      arm64: dts: qcom: msm8916: Add blsp_i2c5
      arm64: dts: qcom: msm8916-samsung-a2015: Add touchscreen regulator
      arm64: dts: qcom: msm8916-samsung-a5u: Add touchscreen
      arm64: dts: qcom: msm8916: avoid using _ in node names
      arm64: dts: qcom: msm8916: move gpu opp table to gpu node
      arm64: dts: qcom: apq8016-sbc: merge -pins.dtsi into main .dtsi

Ulf Hansson (2):
      arm64: dts: qcom: msm8916: Conform to the domain-idle-state binding
      arm64: dts: qcom: msm8916: Conform to the nodename pattern PSCI subnodes

 Documentation/devicetree/bindings/arm/cpus.yaml    |   1 +
 Documentation/devicetree/bindings/arm/qcom.yaml    |   7 +
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   1 +
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 .../arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi |  74 --
 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi |  89 --
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi          | 257 +++++-
 arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi       |  53 +-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts          | 112 ++-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi              | 474 +++++-----
 .../boot/dts/qcom/msm8916-longcheer-l8150.dts      |  25 +-
 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi         | 221 +++--
 .../dts/qcom/msm8916-samsung-a2015-common.dtsi     |  98 ++-
 .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts      |  54 ++
 .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts      |  35 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi              | 228 ++++-
 arch/arm64/boot/dts/qcom/msm8996.dtsi              |  87 +-
 arch/arm64/boot/dts/qcom/msm8998.dtsi              |  38 +-
 arch/arm64/boot/dts/qcom/pm8150.dtsi               |  14 +-
 arch/arm64/boot/dts/qcom/pm8150b.dtsi              |  14 +-
 arch/arm64/boot/dts/qcom/pm8150l.dtsi              |  14 +-
 arch/arm64/boot/dts/qcom/pmi8994.dtsi              |   6 +
 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi           |  85 +-
 arch/arm64/boot/dts/qcom/qcs404.dtsi               | 100 +++
 arch/arm64/boot/dts/qcom/sc7180-idp.dts            |  66 +-
 arch/arm64/boot/dts/qcom/sc7180.dtsi               | 955 +++++++++++++++++++--
 .../arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts |  46 +
 arch/arm64/boot/dts/qcom/sdm660.dtsi               | 372 ++++++++
 arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi         |   2 +
 arch/arm64/boot/dts/qcom/sdm845-db845c.dts         | 210 +++++
 arch/arm64/boot/dts/qcom/sdm845-mtp.dts            |   2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi               |  98 ++-
 .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts      |  13 +
 arch/arm64/boot/dts/qcom/sm8250-mtp.dts            | 351 ++++++++
 arch/arm64/boot/dts/qcom/sm8250.dtsi               | 126 ++-
 35 files changed, 3528 insertions(+), 801 deletions(-)
 delete mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
 delete mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660.dtsi

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