Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / mirror / Atom feed
* Re: [PATCHv2 0/7] Support inhibiting input devices
From: Andrzej Pietrasiewicz @ 2020-05-22 15:35 UTC (permalink / raw)
  To: Dmitry Torokhov, Peter Hutterer
  Cc: Nick Dyer, linux-iio, Benjamin Tissoires, platform-driver-x86,
	ibm-acpi-devel, Laxman Dewangan, Peter Meerwald-Stadler, kernel,
	Fabio Estevam, linux-samsung-soc, Krzysztof Kozlowski,
	Jonathan Hunter, linux-acpi, Kukjin Kim, NXP Linux Team,
	linux-input, Len Brown, Peter Hutterer, Michael Hennerich,
	Sascha Hauer, Sylvain Lemieux, Henrique de Moraes Holschuh,
	Vladimir Zapolskiy, Hans de Goede, Lars-Peter Clausen,
	linux-tegra, linux-arm-kernel, Barry Song, Ferruh Yigit, patches,
	Rafael J . Wysocki, Thierry Reding, Sangwon Jee,
	Pengutronix Kernel Team, Hartmut Knaack, Shawn Guo,
	Jonathan Cameron
In-Reply-To: <20200518024034.GL89269@dtor-ws>

Hi Hans, hi Dmitry,

W dniu 18.05.2020 o 04:40, Dmitry Torokhov pisze:
> Hi Hans, Peter,
> 
> On Mon, May 18, 2020 at 08:55:10AM +1000, Peter Hutterer wrote:
>> On Fri, May 15, 2020 at 08:19:10PM +0200, Hans de Goede wrote:
>>> Hi Andrezj,
>>>

<snip>

>>
>>> I also noticed that you keep the device open (do not call the
>>> input_device's close callback) when inhibited and just throw away
>>> any events generated. This seems inefficient and may lead to
>>> the internal state getting out of sync. What if a key is pressed
>>> while inhibited and then the device is uninhibited while the key
>>> is still pressed?  Now the press event is lost and userspace
>>> querying the current state will see the pressed key as being
>>> released.
> 
> This is a good point. We should look into signalling that some events
> have been dropped (via EV_SYN/SYN_DROPPED) so that clients are aware of
> it.
> 

It seems to me that the situation Hans envisions is not possible,
or will not be possible with a simple change. Let me explain.

For a start, let's recall that the input core prevents consecutive
events of the same kind (type _and_ code _and_ value) from being
delivered to handlers. The decision is made in input_get_disposition().
For EV_KEY it is:

		if (is_event_supported(code, dev->keybit, KEY_MAX)) {

			/* auto-repeat bypasses state updates */
			if (value == 2) {
				disposition = INPUT_PASS_TO_HANDLERS;
				break;
			}

			if (!!test_bit(code, dev->key) != !!value) {

				__change_bit(code, dev->key);
				disposition = INPUT_PASS_TO_HANDLERS;
			}
		}

Let's now focus on value != 2 (events other than auto-repeat).
The disposition changes from the default INPUT_IGNORE_EVENT to
INPUT_PASS_TO_HANDLERS only when the event in question changes
the current state: either by releasing a pressed key, or by
pressing a released key. Subsequent releases of a released key
or subsequent presses of a pressed key will be ignored.

What Hans points out is the possibility of uninhibiting a device
while its key is pressed and then releasing the key. First of all,
during inhibiting input_dev_release_keys() is called, so input_dev's
internal state will be cleared of all pressed keys. Then the device
- after being uninhibited - all of a sudden produces a key release
event. It will be ignored as per the "subsequent releases of a
released key" case, so the handlers will not be passed an unmatched
key release event. Assuming that passing an unmatched key release
event was Hans's concern, in this case it seems impossible.

Now, the value of 2 (auto-repeat) needs some attention. There are two
cases to consider: the device uses input core's software repeat or it
uses its own (hardware) repeat.

Let's consider the first case. The timer which generates auto-repeat
is only started on a key press event and only stopped on a key release
event. As such, if any auto-repeat was in progress when inhibiting
happened, it must have been stopped as per input_dev_release_keys().
Then the key is pressed and held after the device has been inhibited,
and the device is being uninhibited. Since it uses software auto-repeat,
no events will be reported by the device until the key is released,
and, as explained above, the release event will be ignored.

Let's consider the second case. The key is pressed and held after the
device has been inhibited and the device is being uninhibited. The worst
thing that can happen is unmatched key repeat events will start coming
from the device. We must prevent them from reaching the handlers and
ignore them instead. So I suggest something on the lines of:

if (is_event_supported(code, dev->keybit, KEY_MAX)) {

			/* auto-repeat bypasses state updates */
-			if (value == 2) {
+			if (value == 2 && test_bit(code, dev->key)) {
				disposition = INPUT_PASS_TO_HANDLERS;
				break;
			}

The intended meaning is "ignore key repeat events if the key is not
pressed".

With this small change I believe it is not possible to have neither
unmatched release nor unmatched repeat being delivered to handlers.

Regards,

Andrzej

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v5 06/11] net: ethernet: mtk-star-emac: new driver
From: Bartosz Golaszewski @ 2020-05-22 15:35 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Edwin Peer, linux-devicetree, Stephane Le Provost, Arnd Bergmann,
	netdev, Bartosz Golaszewski, Sean Wang, LKML, Pedro Tsai,
	David S . Miller, Fabien Parent, Rob Herring, linux-mediatek,
	Andrew Perepech, John Crispin, Jakub Kicinski, Mark Lee, arm-soc,
	Heiner Kallweit
In-Reply-To: <5627e304-3463-9229-fa86-d7d31cad7a61@gmail.com>

pt., 22 maj 2020 o 17:06 Matthias Brugger <matthias.bgg@gmail.com> napisał(a):
>
>
>
> On 22/05/2020 14:06, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > This adds the driver for the MediaTek STAR Ethernet MAC currently used
> > on the MT8* SoC family. For now we only support full-duplex.
>
> MT85** SoC family, AFAIU it's not used on MT81** devices. Correct?
>

It's used on MT81**, MT83** and MT85**. What's wrong with the
description anyway?

Bart

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [v4,7/7] thermal: mediatek: use spinlock to protect PTPCORESEL
From: Daniel Lezcano @ 2020-05-22 15:36 UTC (permalink / raw)
  To: Michael Kao, Matthias Brugger, Zhang Rui, Eduardo Valentin,
	Rob Herring, Mark Rutland, hsinyi, linux-pm, srv_heupstream
  Cc: devicetree, linux-mediatek, linux-kernel, linux-arm-kernel
In-Reply-To: <20200323121537.22697-8-michael.kao@mediatek.com>

On 23/03/2020 13:15, Michael Kao wrote:
> From: "michael.kao" <michael.kao@mediatek.com>
> 
> The driver of thermal and svs will use the
> same register for the project which should select
> bank before reading sensor value.

Here there is a design problem AFAICT. The sensor should not be using
external locks.



> Signed-off-by: Michael Kao <michael.kao@mediatek.com>
> ---
>  drivers/thermal/mtk_thermal.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
> index 9eaca432920e..594ad4f0f8cd 100644
> --- a/drivers/thermal/mtk_thermal.c
> +++ b/drivers/thermal/mtk_thermal.c
> @@ -22,6 +22,7 @@
>  #include <linux/thermal.h>
>  #include <linux/reset.h>
>  #include <linux/types.h>
> +#include <linux/power/mtk_svs.h>
>  
>  /* AUXADC Registers */
>  #define AUXADC_CON1_SET_V	0x008
> @@ -262,7 +263,7 @@ struct mtk_thermal {
>  	struct clk *clk_peri_therm;
>  	struct clk *clk_auxadc;
>  	/* lock: for getting and putting banks */
> -	struct mutex lock;
> +	unsigned long flags;
>  
>  	/* Calibration values */
>  	s32 adc_ge;
> @@ -561,7 +562,7 @@ static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
>  	u32 val;
>  
>  	if (mt->conf->need_switch_bank) {
> -		mutex_lock(&mt->lock);
> +		mt->flags = claim_mtk_svs_lock();
>  
>  		val = readl(mt->thermal_base + PTPCORESEL);
>  		val &= ~0xf;
> @@ -581,7 +582,7 @@ static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
>  	struct mtk_thermal *mt = bank->mt;
>  
>  	if (mt->conf->need_switch_bank)
> -		mutex_unlock(&mt->lock);
> +		release_mtk_svs_lock(mt->flags);
>  }
>  
>  /**
> @@ -938,8 +939,6 @@ static int mtk_thermal_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	mutex_init(&mt->lock);
> -
>  	mt->dev = &pdev->dev;
>  
>  	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
> 


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v8 3/3] PM / AVS: SVS: Introduce SVS engine
From: Matthias Brugger @ 2020-05-22 15:38 UTC (permalink / raw)
  To: Roger Lu, Enric Balletbo Serra
  Cc: Mark Rutland, Nicolas Boichat, Nishanth Menon, Kevin Hilman,
	Stephen Boyd, Linux PM list, Angus Lin, Xiaoqing Liu,
	linux-kernel, Fan Chen, devicetree@vger.kernel.org, Rob Herring,
	moderated list:ARM/Mediatek SoC support, HenryC Chen,
	Charles Yang, YT Lee, Linux ARM
In-Reply-To: <1590140434.4392.22.camel@mtksdaap41>



On 22/05/2020 11:40, Roger Lu wrote:
> 
> Hi Enric,
> 
> On Tue, 2020-05-19 at 17:30 +0200, Enric Balletbo Serra wrote:
>> Hi Roger,
>>
>> Thank you for your patch. I have the feeling that this driver is
>> complex and difficult to follow and I am wondering if it wouldn't be
>> better if you can send a version that simply adds basic functionality
>> for now. Some comments below.
> 
> Thanks for the advices. I'll submit SVS v9 with basic functionality
> patch + step by step functionalities' patches. 
> 
>>
>> Missatge de Roger Lu <roger.lu@mediatek.com> del dia dl., 18 de maig
>> 2020 a les 11:25:
>>>
>>> The SVS (Smart Voltage Scaling) engine is a piece
>>> of hardware which is used to calculate optimized
>>> voltage values of several power domains,
>>> e.g. CPU/GPU/CCI, according to chip process corner,
>>> temperatures, and other factors. Then DVFS driver
>>> could apply those optimized voltage values to reduce
>>> power consumption.
>>>
>>> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
>>> ---
>>>  drivers/power/avs/Kconfig     |   10 +
>>>  drivers/power/avs/Makefile    |    1 +
>>>  drivers/power/avs/mtk_svs.c   | 2119 +++++++++++++++++++++++++++++++++
>>>  include/linux/power/mtk_svs.h |   23 +
>>>  4 files changed, 2153 insertions(+)
>>>  create mode 100644 drivers/power/avs/mtk_svs.c
>>>  create mode 100644 include/linux/power/mtk_svs.h
>>>
>>> diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
>>> index cdb4237bfd02..67089ac6040e 100644
>>> --- a/drivers/power/avs/Kconfig
>>> +++ b/drivers/power/avs/Kconfig
>>> @@ -35,3 +35,13 @@ config ROCKCHIP_IODOMAIN
>>>           Say y here to enable support io domains on Rockchip SoCs. It is
>>>           necessary for the io domain setting of the SoC to match the
>>>           voltage supplied by the regulators.
>>> +
>>> +config MTK_SVS
>>> +       bool "MediaTek Smart Voltage Scaling(SVS)"
>>
>> Can't be this a module? Why? In such case, you should use tristate option
> 
> Generally, MTK_SVS is needed in MTK SoC(mt81xx) products. So, we don't provide
> module option in config. If, somehow, SVS isn't needed, we suggest
> CONFIG_MTK_SVS=n to be set.
> 

The question here is if it needs to be probed before we probe the modules. If
not, we should add a Kconfig option for MT81xx SoCs to select MTK_SVS.

>>
>>> +       depends on POWER_AVS && MTK_EFUSE && NVMEM
>>> +       help
>>> +         The SVS engine is a piece of hardware which is used to calculate
>>> +         optimized voltage values of several power domains, e.g.
>>> +         CPU clusters/GPU/CCI, according to chip process corner, temperatures,
>>> +         and other factors. Then DVFS driver could apply those optimized voltage
>>> +         values to reduce power consumption.
>>> diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
>>> index 9007d05853e2..231adf078582 100644
>>> --- a/drivers/power/avs/Makefile
>>> +++ b/drivers/power/avs/Makefile
>>> @@ -2,3 +2,4 @@
>>>  obj-$(CONFIG_POWER_AVS_OMAP)           += smartreflex.o
>>>  obj-$(CONFIG_QCOM_CPR)                 += qcom-cpr.o
>>>  obj-$(CONFIG_ROCKCHIP_IODOMAIN)                += rockchip-io-domain.o
>>> +obj-$(CONFIG_MTK_SVS)                  += mtk_svs.o
>>
>> Will this driver be SoC specific or the idea is to support different
>> SoCs? If the answer to the first question is yes, please name the file
>> with the SoC prefix (i.e mt8183_svs). However, If the answer to the
>> second question is yes, make sure you prefix common
>> functions/structs/defines with a generic prefix mtk_svs but use the
>> SoC prefix for the ones you expect will be different between SoC, i.e
>> mt8183_svs_. This helps the readability of the driver. Also, try to
>> avoid too generic names.
> 
> MTK_SVS is designed for supporting different MTK SoCs.Therefore, the answer is second
> question and thanks for the heads-up.
> 
>>
>>> diff --git a/drivers/power/avs/mtk_svs.c b/drivers/power/avs/mtk_svs.c
>>> new file mode 100644
>>> index 000000000000..a4083b3ef175
>>> --- /dev/null
>>> +++ b/drivers/power/avs/mtk_svs.c
>>> @@ -0,0 +1,2119 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>
>> I suspect you want this only GPLv2 compliant. Use GPL-2.0-only
> 
> OK. I'll use GPL-2.0-only.Thanks.
> 
>>
>>> +/*
>>> + * Copyright (C) 2020 MediaTek Inc.
>>> + */
>>> +
>>> +#define pr_fmt(fmt)    "[mtk_svs] " fmt
>>
>> I don't see any reason to use pr_fmt in this driver. Use dev_*
>> functions instead and remove the above.
> 
> Ok. I will remove it. Thanks.
> 
>>
>>> +
>>> +#include <linux/bits.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/completion.h>
>>> +#include <linux/init.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/kthread.h>
>>> +#include <linux/module.h>
>>> +#include <linux/mutex.h>
>>> +#include <linux/nvmem-consumer.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_irq.h>
>>> +#include <linux/of_platform.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/pm_domain.h>
>>> +#include <linux/pm_opp.h>
>>> +#include <linux/pm_qos.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/power/mtk_svs.h>
>>> +#include <linux/proc_fs.h>
>>> +#include <linux/regulator/consumer.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/seq_file.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/spinlock.h>
>>> +#include <linux/thermal.h>
>>> +#include <linux/uaccess.h>
>>> +
>>> +/* svs 1-line sw id */
>>> +#define SVS_CPU_LITTLE                 BIT(0)
>>> +#define SVS_CPU_BIG                    BIT(1)
>>> +#define SVS_CCI                                BIT(2)
>>> +#define SVS_GPU                                BIT(3)
>>> +
>>> +/* svs bank mode support */
>>> +#define SVSB_MODE_ALL_DISABLE          (0)
>>
>> nit: SVS_BMODE_?
> 
> Oh. If we add bank wording like SVS_Bxxx, it might cause some confusion when B combines
> with other words. So, I'll keep SVSB for SVS Bank representation.
> E.g: SVS_BDC_SIGNED_BIT might lead to be explained differently ("SVS bank + DC_SIGNED_BIT" or "SVS + BDC_SIGNED_BIT")
>      - "SVS bank + DC_SIGNED_BIT" is what we want for naming SVS_BDC_SIGNED_BIT but it might be misunderstood.
> 
>>
>>> +#define SVSB_MODE_INIT01               BIT(1)
>>> +#define SVSB_MODE_INIT02               BIT(2)
>>> +#define SVSB_MODE_MON                  BIT(3)
>>> +
>>> +/* svs bank init01 condition */
>>> +#define SVSB_INIT01_VOLT_IGNORE                BIT(1)
>>> +#define SVSB_INIT01_VOLT_INC_ONLY      BIT(2)
>>> +
>>> +/* svs bank common setting */
>>> +#define HIGH_TEMP_MAX                  (U32_MAX)
>>
>> nit: SVS_*
> 
> ok. I will add SVS or SVSB when it refers to SVS BANK.
> 
>>
>>> +#define RUNCONFIG_DEFAULT              (0x80000000)
>>
>> Btw, there is any public datasheet where I can see those addresses and
>> registers and bit fields?
> 
> Excuse us, there is no public datasheet. We can reply it on patchwork. Thanks.
> 
>>
>>> +#define DC_SIGNED_BIT                  (0x8000)
>>> +#define INTEN_INIT0x                   (0x00005f01)
>>> +#define INTEN_MONVOPEN                 (0x00ff0000)
>>> +#define SVSEN_OFF                      (0x0)
>>> +#define SVSEN_MASK                     (0x7)
>>> +#define SVSEN_INIT01                   (0x1)
>>> +#define SVSEN_INIT02                   (0x5)
>>> +#define SVSEN_MON                      (0x2)
>>> +#define INTSTS_MONVOP                  (0x00ff0000)
>>> +#define INTSTS_COMPLETE                        (0x1)
>>> +#define INTSTS_CLEAN                   (0x00ffffff)
>>> +
>>> +#define proc_fops_rw(name) \
>>> +       static int name ## _proc_open(struct inode *inode,      \
>>> +                                     struct file *file)        \
>>> +       {                                                       \
>>> +               return single_open(file, name ## _proc_show,    \
>>> +                                  PDE_DATA(inode));            \
>>> +       }                                                       \
>>> +       static const struct proc_ops name ## _proc_fops = {     \
>>> +               .proc_open      = name ## _proc_open,           \
>>> +               .proc_read      = seq_read,                     \
>>> +               .proc_lseek     = seq_lseek,                    \
>>> +               .proc_release   = single_release,               \
>>> +               .proc_write     = name ## _proc_write,          \
>>> +       }
>>> +
>>> +#define proc_fops_ro(name) \
>>> +       static int name ## _proc_open(struct inode *inode,      \
>>> +                                     struct file *file)        \
>>> +       {                                                       \
>>> +               return single_open(file, name ## _proc_show,    \
>>> +                                  PDE_DATA(inode));            \
>>> +       }                                                       \
>>> +       static const struct proc_ops name ## _proc_fops = {     \
>>> +               .proc_open      = name ## _proc_open,           \
>>> +               .proc_read      = seq_read,                     \
>>> +               .proc_lseek     = seq_lseek,                    \
>>> +               .proc_release   = single_release,               \
>>> +       }
>>> +
>>> +#define proc_entry(name)       {__stringify(name), &name ## _proc_fops}
>>> +
>>
>> /proc is usually the old way of exporting files to userspace, so
>> unless you have a really good reason use sysfs instead, or even
>> better, if it is only for debug purposes use debugfs. Also, you should
>> document the entries in Documentation.
> 
> Ok. I'll change it to debugfs and could you give us an example about entries in documentation?
> We can follow them. Thanks.
> 
>>
>>> +static DEFINE_SPINLOCK(mtk_svs_lock);
>>> +struct mtk_svs;
>>> +
>>> +enum svsb_phase {
>>
>> nit: mtk_svs_bphase?
> 
> ditto
> 
>>
>>> +       SVSB_PHASE_INIT01 = 0,
>>
>> nit: SVS_BPHASE_?
> 
> ditto
> 
>>
>>> +       SVSB_PHASE_INIT02,
>>> +       SVSB_PHASE_MON,
>>> +       SVSB_PHASE_ERROR,
>>> +};
>>> +
>>> +enum reg_index {
>>
>> nit: svs_reg_index?
> 
> OK. Thanks.
> 
>>
>>> +       TEMPMONCTL0 = 0,
>>> +       TEMPMONCTL1,
>>> +       TEMPMONCTL2,
>>> +       TEMPMONINT,
>>> +       TEMPMONINTSTS,
>>> +       TEMPMONIDET0,
>>> +       TEMPMONIDET1,
>>> +       TEMPMONIDET2,
>>> +       TEMPH2NTHRE,
>>> +       TEMPHTHRE,
>>> +       TEMPCTHRE,
>>> +       TEMPOFFSETH,
>>> +       TEMPOFFSETL,
>>> +       TEMPMSRCTL0,
>>> +       TEMPMSRCTL1,
>>> +       TEMPAHBPOLL,
>>> +       TEMPAHBTO,
>>> +       TEMPADCPNP0,
>>> +       TEMPADCPNP1,
>>> +       TEMPADCPNP2,
>>> +       TEMPADCMUX,
>>> +       TEMPADCEXT,
>>> +       TEMPADCEXT1,
>>> +       TEMPADCEN,
>>> +       TEMPPNPMUXADDR,
>>> +       TEMPADCMUXADDR,
>>> +       TEMPADCEXTADDR,
>>> +       TEMPADCEXT1ADDR,
>>> +       TEMPADCENADDR,
>>> +       TEMPADCVALIDADDR,
>>> +       TEMPADCVOLTADDR,
>>> +       TEMPRDCTRL,
>>> +       TEMPADCVALIDMASK,
>>> +       TEMPADCVOLTAGESHIFT,
>>> +       TEMPADCWRITECTRL,
>>> +       TEMPMSR0,
>>> +       TEMPMSR1,
>>> +       TEMPMSR2,
>>> +       TEMPADCHADDR,
>>> +       TEMPIMMD0,
>>> +       TEMPIMMD1,
>>> +       TEMPIMMD2,
>>> +       TEMPMONIDET3,
>>> +       TEMPADCPNP3,
>>> +       TEMPMSR3,
>>> +       TEMPIMMD3,
>>> +       TEMPPROTCTL,
>>> +       TEMPPROTTA,
>>> +       TEMPPROTTB,
>>> +       TEMPPROTTC,
>>> +       TEMPSPARE0,
>>> +       TEMPSPARE1,
>>> +       TEMPSPARE2,
>>> +       TEMPSPARE3,
>>> +       TEMPMSR0_1,
>>> +       TEMPMSR1_1,
>>> +       TEMPMSR2_1,
>>> +       TEMPMSR3_1,
>>> +       DESCHAR,
>>> +       TEMPCHAR,
>>> +       DETCHAR,
>>> +       AGECHAR,
>>> +       DCCONFIG,
>>> +       AGECONFIG,
>>> +       FREQPCT30,
>>> +       FREQPCT74,
>>> +       LIMITVALS,
>>> +       VBOOT,
>>> +       DETWINDOW,
>>> +       CONFIG,
>>> +       TSCALCS,
>>> +       RUNCONFIG,
>>> +       SVSEN,
>>> +       INIT2VALS,
>>> +       DCVALUES,
>>> +       AGEVALUES,
>>> +       VOP30,
>>> +       VOP74,
>>> +       TEMP,
>>> +       INTSTS,
>>> +       INTSTSRAW,
>>> +       INTEN,
>>> +       CHKINT,
>>> +       CHKSHIFT,
>>> +       STATUS,
>>> +       VDESIGN30,
>>> +       VDESIGN74,
>>> +       DVT30,
>>> +       DVT74,
>>> +       AGECOUNT,
>>> +       SMSTATE0,
>>> +       SMSTATE1,
>>> +       CTL0,
>>> +       DESDETSEC,
>>> +       TEMPAGESEC,
>>> +       CTRLSPARE0,
>>> +       CTRLSPARE1,
>>> +       CTRLSPARE2,
>>> +       CTRLSPARE3,
>>> +       CORESEL,
>>> +       THERMINTST,
>>> +       INTST,
>>> +       THSTAGE0ST,
>>> +       THSTAGE1ST,
>>> +       THSTAGE2ST,
>>> +       THAHBST0,
>>> +       THAHBST1,
>>> +       SPARE0,
>>> +       SPARE1,
>>> +       SPARE2,
>>> +       SPARE3,
>>> +       THSLPEVEB,
>>> +       reg_num,
>>> +};
>>> +
>>> +static const u32 svs_regs_v2[] = {
>>
>> Is this SoC specific or shared between SoCs?
> 
> Shared between SoCs. Some SVS in MTK SoCs use v2 register map.
> 

And which silicon uses v1 then? Is v2 a MediaTek internal naming you want to keep?

>>
>>> +       [TEMPMONCTL0]           = 0x000,
>>> +       [TEMPMONCTL1]           = 0x004,
>>> +       [TEMPMONCTL2]           = 0x008,
>>> +       [TEMPMONINT]            = 0x00c,
>>> +       [TEMPMONINTSTS]         = 0x010,
>>> +       [TEMPMONIDET0]          = 0x014,
>>> +       [TEMPMONIDET1]          = 0x018,
>>> +       [TEMPMONIDET2]          = 0x01c,
>>> +       [TEMPH2NTHRE]           = 0x024,
>>> +       [TEMPHTHRE]             = 0x028,
>>> +       [TEMPCTHRE]             = 0x02c,
>>> +       [TEMPOFFSETH]           = 0x030,
>>> +       [TEMPOFFSETL]           = 0x034,
>>> +       [TEMPMSRCTL0]           = 0x038,
>>> +       [TEMPMSRCTL1]           = 0x03c,
>>> +       [TEMPAHBPOLL]           = 0x040,
>>> +       [TEMPAHBTO]             = 0x044,
>>> +       [TEMPADCPNP0]           = 0x048,
>>> +       [TEMPADCPNP1]           = 0x04c,
>>> +       [TEMPADCPNP2]           = 0x050,
>>> +       [TEMPADCMUX]            = 0x054,
>>> +       [TEMPADCEXT]            = 0x058,
>>> +       [TEMPADCEXT1]           = 0x05c,
>>> +       [TEMPADCEN]             = 0x060,
>>> +       [TEMPPNPMUXADDR]        = 0x064,
>>> +       [TEMPADCMUXADDR]        = 0x068,
>>> +       [TEMPADCEXTADDR]        = 0x06c,
>>> +       [TEMPADCEXT1ADDR]       = 0x070,
>>> +       [TEMPADCENADDR]         = 0x074,
>>> +       [TEMPADCVALIDADDR]      = 0x078,
>>> +       [TEMPADCVOLTADDR]       = 0x07c,
>>> +       [TEMPRDCTRL]            = 0x080,
>>> +       [TEMPADCVALIDMASK]      = 0x084,
>>> +       [TEMPADCVOLTAGESHIFT]   = 0x088,
>>> +       [TEMPADCWRITECTRL]      = 0x08c,
>>> +       [TEMPMSR0]              = 0x090,
>>> +       [TEMPMSR1]              = 0x094,
>>> +       [TEMPMSR2]              = 0x098,
>>> +       [TEMPADCHADDR]          = 0x09c,
>>> +       [TEMPIMMD0]             = 0x0a0,
>>> +       [TEMPIMMD1]             = 0x0a4,
>>> +       [TEMPIMMD2]             = 0x0a8,
>>> +       [TEMPMONIDET3]          = 0x0b0,
>>> +       [TEMPADCPNP3]           = 0x0b4,
>>> +       [TEMPMSR3]              = 0x0b8,
>>> +       [TEMPIMMD3]             = 0x0bc,
>>> +       [TEMPPROTCTL]           = 0x0c0,
>>> +       [TEMPPROTTA]            = 0x0c4,
>>> +       [TEMPPROTTB]            = 0x0c8,
>>> +       [TEMPPROTTC]            = 0x0cc,
>>> +       [TEMPSPARE0]            = 0x0f0,
>>> +       [TEMPSPARE1]            = 0x0f4,
>>> +       [TEMPSPARE2]            = 0x0f8,
>>> +       [TEMPSPARE3]            = 0x0fc,
>>> +       [TEMPMSR0_1]            = 0x190,
>>> +       [TEMPMSR1_1]            = 0x194,
>>> +       [TEMPMSR2_1]            = 0x198,
>>> +       [TEMPMSR3_1]            = 0x1b8,
>>> +       [DESCHAR]               = 0xc00,
>>> +       [TEMPCHAR]              = 0xc04,
>>> +       [DETCHAR]               = 0xc08,
>>> +       [AGECHAR]               = 0xc0c,
>>> +       [DCCONFIG]              = 0xc10,
>>> +       [AGECONFIG]             = 0xc14,
>>> +       [FREQPCT30]             = 0xc18,
>>> +       [FREQPCT74]             = 0xc1c,
>>> +       [LIMITVALS]             = 0xc20,
>>> +       [VBOOT]                 = 0xc24,
>>> +       [DETWINDOW]             = 0xc28,
>>> +       [CONFIG]                = 0xc2c,
>>> +       [TSCALCS]               = 0xc30,
>>> +       [RUNCONFIG]             = 0xc34,
>>> +       [SVSEN]                 = 0xc38,
>>> +       [INIT2VALS]             = 0xc3c,
>>> +       [DCVALUES]              = 0xc40,
>>> +       [AGEVALUES]             = 0xc44,
>>> +       [VOP30]                 = 0xc48,
>>> +       [VOP74]                 = 0xc4c,
>>> +       [TEMP]                  = 0xc50,
>>> +       [INTSTS]                = 0xc54,
>>> +       [INTSTSRAW]             = 0xc58,
>>> +       [INTEN]                 = 0xc5c,
>>> +       [CHKINT]                = 0xc60,
>>> +       [CHKSHIFT]              = 0xc64,
>>> +       [STATUS]                = 0xc68,
>>> +       [VDESIGN30]             = 0xc6c,
>>> +       [VDESIGN74]             = 0xc70,
>>> +       [DVT30]                 = 0xc74,
>>> +       [DVT74]                 = 0xc78,
>>> +       [AGECOUNT]              = 0xc7c,
>>> +       [SMSTATE0]              = 0xc80,
>>> +       [SMSTATE1]              = 0xc84,
>>> +       [CTL0]                  = 0xc88,
>>> +       [DESDETSEC]             = 0xce0,
>>> +       [TEMPAGESEC]            = 0xce4,
>>> +       [CTRLSPARE0]            = 0xcf0,
>>> +       [CTRLSPARE1]            = 0xcf4,
>>> +       [CTRLSPARE2]            = 0xcf8,
>>> +       [CTRLSPARE3]            = 0xcfc,
>>> +       [CORESEL]               = 0xf00,
>>> +       [THERMINTST]            = 0xf04,
>>> +       [INTST]                 = 0xf08,
>>> +       [THSTAGE0ST]            = 0xf0c,
>>> +       [THSTAGE1ST]            = 0xf10,
>>> +       [THSTAGE2ST]            = 0xf14,
>>> +       [THAHBST0]              = 0xf18,
>>> +       [THAHBST1]              = 0xf1c,
>>> +       [SPARE0]                = 0xf20,
>>> +       [SPARE1]                = 0xf24,
>>> +       [SPARE2]                = 0xf28,
>>> +       [SPARE3]                = 0xf2c,
>>> +       [THSLPEVEB]             = 0xf30,
>>> +};
>>> +
>>> +struct thermal_parameter {
>>
>> In general, not only in this struct, would be good have some
>> documentation to have a better undestanding of the fields. That makes
>> the job of the reviewer a bit easier.
> 
> Ok. Could you share a documentation example to us? We'll share the
> information as much as we can. Thanks a lot.
> 

you should find that in all drivers, eg:
https://elixir.bootlin.com/linux/latest/source/drivers/soc/mediatek/mtk-scpsys.c#L111


Regards,
Matthias

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 09/12] dt-bindings: arm: fsl: Add msi-map device-tree binding for fsl-mc bus
From: Laurentiu Tudor @ 2020-05-22 15:38 UTC (permalink / raw)
  To: Rob Herring, Robin Murphy
  Cc: devicetree, Catalin Marinas, Will Deacon, PCI, Hanjun Guo,
	Rafael J. Wysocki, Makarand Pawagi, linux-acpi, Linux IOMMU,
	Marc Zyngier, Sudeep Holla, Bjorn Helgaas, Diana Craciun,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_JsqKVyqc9QZhGD7FeNLpJ=x3oLzmY0zADBa+6ZaE46dN39w@mail.gmail.com>

On 5/22/2020 5:02 PM, Rob Herring wrote:
> On Fri, May 22, 2020 at 3:42 AM Robin Murphy <robin.murphy@arm.com> wrote:
>>
>> On 2020-05-22 00:10, Rob Herring wrote:
>>> On Thu, May 21, 2020 at 7:00 AM Lorenzo Pieralisi
>>> <lorenzo.pieralisi@arm.com> wrote:
>>>>
>>>> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>>>
>>>> The existing bindings cannot be used to specify the relationship
>>>> between fsl-mc devices and GIC ITSes.
>>>>
>>>> Add a generic binding for mapping fsl-mc devices to GIC ITSes, using
>>>> msi-map property.
>>>>
>>>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>> ---
>>>>   .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 30 +++++++++++++++++--
>>>>   1 file changed, 27 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
>>>> index 9134e9bcca56..b0813b2d0493 100644
>>>> --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
>>>> +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
>>>> @@ -18,9 +18,9 @@ same hardware "isolation context" and a 10-bit value called an ICID
>>>>   the requester.
>>>>
>>>>   The generic 'iommus' property is insufficient to describe the relationship
>>>> -between ICIDs and IOMMUs, so an iommu-map property is used to define
>>>> -the set of possible ICIDs under a root DPRC and how they map to
>>>> -an IOMMU.
>>>> +between ICIDs and IOMMUs, so the iommu-map and msi-map properties are used
>>>> +to define the set of possible ICIDs under a root DPRC and how they map to
>>>> +an IOMMU and a GIC ITS respectively.
>>>>
>>>>   For generic IOMMU bindings, see
>>>>   Documentation/devicetree/bindings/iommu/iommu.txt.
>>>> @@ -28,6 +28,9 @@ Documentation/devicetree/bindings/iommu/iommu.txt.
>>>>   For arm-smmu binding, see:
>>>>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
>>>>
>>>> +For GICv3 and GIC ITS bindings, see:
>>>> +Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
>>>> +
>>>>   Required properties:
>>>>
>>>>       - compatible
>>>> @@ -119,6 +122,15 @@ Optional properties:
>>>>     associated with the listed IOMMU, with the iommu-specifier
>>>>     (i - icid-base + iommu-base).
>>>>
>>>> +- msi-map: Maps an ICID to a GIC ITS and associated iommu-specifier
>>>> +  data.
>>>> +
>>>> +  The property is an arbitrary number of tuples of
>>>> +  (icid-base,iommu,iommu-base,length).
>>>
>>> I'm confused because the example has GIC ITS phandle, not an IOMMU.
>>>
>>> What is an iommu-base?
>>
>> Right, I was already halfway through writing a reply to say that all the
>> copy-pasted "iommu" references here should be using the terminology from
>> the pci-msi.txt binding instead.
>>
>>>> +
>>>> +  Any ICID in the interval [icid-base, icid-base + length) is
>>>> +  associated with the listed GIC ITS, with the iommu-specifier
>>>> +  (i - icid-base + iommu-base).
>>>>   Example:
>>>>
>>>>           smmu: iommu@5000000 {
>>>> @@ -128,6 +140,16 @@ Example:
>>>>                  ...
>>>>           };
>>>>
>>>> +       gic: interrupt-controller@6000000 {
>>>> +               compatible = "arm,gic-v3";
>>>> +               ...
>>>> +               its: gic-its@6020000 {
>>>> +                       compatible = "arm,gic-v3-its";
>>>> +                       msi-controller;
>>>> +                       ...
>>>> +               };
>>>> +       };
>>>> +
>>>>           fsl_mc: fsl-mc@80c000000 {
>>>>                   compatible = "fsl,qoriq-mc";
>>>>                   reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
>>>> @@ -135,6 +157,8 @@ Example:
>>>>                   msi-parent = <&its>;
>>
>> Side note: is it right to keep msi-parent here? It rather implies that
>> the MC itself has a 'native' Device ID rather than an ICID, which I
>> believe is not strictly true. Plus it's extra-confusing that it doesn't
>> specify an ID either way, since that makes it look like the legacy PCI
>> case that gets treated implicitly as an identity msi-map, which makes no
>> sense at all to combine with an actual msi-map.
> 
> No, it doesn't make sense from a binding perspective.
> 
>>
>>>>                   /* define map for ICIDs 23-64 */
>>>>                   iommu-map = <23 &smmu 23 41>;
>>>> +                /* define msi map for ICIDs 23-64 */
>>>> +                msi-map = <23 &its 23 41>;
>>>
>>> Seeing 23 twice is odd. The numbers to the right of 'its' should be an
>>> ITS number space.
>>
>> On about 99% of systems the values in the SMMU Stream ID and ITS Device
>> ID spaces are going to be the same. Nobody's going to bother carrying
>> *two* sets of sideband data across the interconnect if they don't have to ;)
> 
> I'm referring to the 23 on the left and right, not between the msi and
> iommu. If the left and right are the same, then what are we remapping
> exactly?
> 

I also insisted a lot on keeping things simple and don't do any kind of
translation but Robin convinced me that this is not such a great idea.
The truth is that the hardware can be configured in such a way that the
assumption that icid -> streamid mapping is 1:1 no longer holds.
It just happens that we currently setup the hw to have 1:1 mappings.

P.S. No idea why, but somehow I got dropped from the thread. Weird.

---
Best Regards, Laurentiu

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers
From: Catalin Marinas @ 2020-05-22 15:42 UTC (permalink / raw)
  To: Zhenyu Ye
  Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
	yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
	suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
	prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
	linux-kernel, maz, akpm
In-Reply-To: <20200423135656.2712-6-yezhenyu2@huawei.com>

On Thu, Apr 23, 2020 at 09:56:55PM +0800, Zhenyu Ye wrote:
> diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c
> index 3d7c01e76efc..3eff199d3507 100644
> --- a/mm/pgtable-generic.c
> +++ b/mm/pgtable-generic.c
> @@ -101,6 +101,28 @@ pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long address,
>  
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  
> +#ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> +
> +#define FLUSH_Pxx_TLB_RANGE(_pxx)					\
> +void flush_##_pxx##_tlb_range(struct vm_area_struct *vma,		\
> +			      unsigned long addr, unsigned long end)	\
> +{									\
> +		struct mmu_gather tlb;					\
> +									\
> +		tlb_gather_mmu(&tlb, vma->vm_mm, addr, end);		\
> +		tlb_start_vma(&tlb, vma);				\
> +		tlb_flush_##_pxx##_range(&tlb, addr, end - addr);	\
> +		tlb_end_vma(&tlb, vma);					\
> +		tlb_finish_mmu(&tlb, addr, end);			\
> +}

I may have confused myself (flush_p??_tlb_* vs. tlb_flush_p??_*) but do
actually need this whole tlb_gather thing here? IIUC (by grep'ing),
flush_p?d_tlb_range() is only called on huge pages, so we should know
the level already.

-- 
Catalin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [PATCH] arm64: dts: rockchip: rename and label gpio-led subnodes part 2
From: Johan Jonker @ 2020-05-22 15:46 UTC (permalink / raw)
  To: heiko; +Cc: devicetree, robh+dt, linux-kernel, linux-arm-kernel,
	linux-rockchip

Current dts files with 'gpio-led' nodes were manually verified.
In order to automate this process leds-gpio.txt
has been converted to yaml. With this conversion a check
for pattern properties was added. In part 2 rename and label
gpio-led subnodes that passed the regex, but still don't have
the preferred form. Any pin subnode that ends with '-gpio'
in the pinctrl node generates a warning.

Fix with help of the following rules:

1: Add nodename in the preferred form.

2: Always add a label that ends with '_led' to prevent conflicts
   with other labels such as 'power' and 'mmc'

3: If leds need pinctrl add a label that ends with '_led_pin'
   also to prevent conflicts with other labels.

patternProperties:
  # The first form is preferred, but fall back to just 'led'
  # anywhere in the node name to at least catch some child nodes.
  "(^led-[0-9a-f]$|led)":

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/leds/
leds-gpio.yaml

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/
schemas/gpio/gpio.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts  |  6 +++---
 arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi        |  8 ++++----
 arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 10 +++++-----
 arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi     |  6 +++---
 arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts  |  6 +++---
 arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi        |  6 +++---
 arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi      | 14 +++++++-------
 arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi   | 10 +++++-----
 8 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
index cbde279ae..e8774347b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -25,9 +25,9 @@
 	};
 
 	leds {
-		pinctrl-0 = <&led_pins_module>, <&led_sd_haikou>;
+		pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
 
-		sd-card-led {
+		sd_card_led: led-3 {
 			label = "sd_card_led";
 			gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
@@ -118,7 +118,7 @@
 	};
 
 	leds {
-		led_sd_haikou: led-sd-gpio {
+		sd_card_led_pin: sd-card-led-pin {
 			rockchip,pins =
 				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
index e17311e09..eeef64e35 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
@@ -76,16 +76,16 @@
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_module>;
+		pinctrl-0 = <&module_led_pins>;
 
-		module_led1 {
+		module_led1: led-1 {
 			label = "module_led1";
 			gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 			panic-indicator;
 		};
 
-		module_led2 {
+		module_led2: led-2 {
 			label = "module_led2";
 			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
@@ -270,7 +270,7 @@
 
 &pinctrl {
 	leds {
-		led_pins_module: led-module-gpio {
+		module_led_pins: module-led-pins {
 			rockchip,pins =
 				<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
 				<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
index e87a04477..e36837c04 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
@@ -141,15 +141,15 @@
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>;
+		pinctrl-0 = <&sys_led_pin>, <&user_led_pin>;
 
-		sys-led {
+		sys_led: led-0 {
 			label = "sys_led";
 			linux,default-trigger = "heartbeat";
 			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
 		};
 
-		user-led {
+		user_led: led-1 {
 			label = "user_led";
 			default-state = "off";
 			gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
@@ -586,11 +586,11 @@
 	};
 
 	leds {
-		sys_led_gpio: sys_led-gpio {
+		sys_led_pin: sys-led-pin {
 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		user_led_gpio: user_led-gpio {
+		user_led_pin: user-led-pin {
 			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index c88018a0e..b24d54570 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -117,9 +117,9 @@
 	leds: gpio-leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&leds_gpio>;
+		pinctrl-0 = <&status_led_pin>;
 
-		status {
+		status_led: led-0 {
 			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
 			label = "status_led";
 			linux,default-trigger = "heartbeat";
@@ -520,7 +520,7 @@
 	};
 
 	gpio-leds {
-		leds_gpio: leds-gpio {
+		status_led_pin: status-led-pin {
 			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index d80d6b726..a8d363568 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -15,9 +15,9 @@
 	};
 
 	leds {
-		pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
+		pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
 
-		sd-card-led {
+		sd_card_led: led-1 {
 			label = "sd_card_led";
 			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
@@ -179,7 +179,7 @@
 	};
 
 	leds {
-		led_sd_haikou: led-sd-gpio {
+		sd_card_led_pin: sd-card-led-pin {
 			rockchip,pins =
 			  <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 07694b196..ae31299cb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -11,9 +11,9 @@
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&led_pin_module>;
+		pinctrl-0 = <&module_led_pin>;
 
-		module-led {
+		module_led: led-0 {
 			label = "module_led";
 			gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
@@ -450,7 +450,7 @@
 	};
 
 	leds {
-		led_pin_module: led-module-gpio {
+		module_led_pin: module-led-pin {
 			rockchip,pins =
 			  <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
index 9f225e9c3..cec70f2bf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
@@ -61,23 +61,23 @@
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>, <&yellow_led_gpio>;
+		pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>;
 
-		work-led {
+		work_led: led-0 {
 			label = "green:work";
 			gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
 
-		diy-led {
+		diy_led: led-1 {
 			label = "red:diy";
 			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 			linux,default-trigger = "mmc1";
 		};
 
-		yellow-led {
+		yellow_led: led-2 {
 			label = "yellow:yellow-led";
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
@@ -595,15 +595,15 @@
 	};
 
 	leds {
-		diy_led_gpio: diy_led-gpio {
+		diy_led_pin: diy-led-pin {
 			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		work_led_gpio: work_led-gpio {
+		work_led_pin: work-led-pin {
 			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		yellow_led_gpio: yellow_led-gpio {
+		yellow_led_pin: yellow-led-pin {
 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
index 6788ab28f..c39d0f411 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
@@ -39,15 +39,15 @@
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
-		pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+		pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
 
-		work-led {
+		work_led: led-0 {
 			label = "work";
 			default-state = "on";
 			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
 		};
 
-		diy-led {
+		diy_led: led-1 {
 			label = "diy";
 			default-state = "off";
 			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
@@ -588,11 +588,11 @@
 	};
 
 	leds {
-		work_led_gpio: work_led-gpio {
+		work_led_pin: work-led-pin {
 			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		diy_led_gpio: diy_led-gpio {
+		diy_led_pin: diy-led-pin {
 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
-- 
2.11.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related

* Re: [PATCH v2 3/6] arm64: Add tlbi_user_level TLB invalidation helper
From: Catalin Marinas @ 2020-05-22 15:49 UTC (permalink / raw)
  To: Zhenyu Ye
  Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
	yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
	suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
	prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
	linux-kernel, maz, akpm
In-Reply-To: <20200423135656.2712-4-yezhenyu2@huawei.com>

On Thu, Apr 23, 2020 at 09:56:53PM +0800, Zhenyu Ye wrote:
> @@ -190,8 +196,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
>  	unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
>  
>  	dsb(ishst);
> -	__tlbi(vale1is, addr);
> -	__tlbi_user(vale1is, addr);
> +	__tlbi_level(vale1is, addr, 0);
> +	__tlbi_user_level(vale1is, addr, 0);
>  }

This one remains with a level 0 throughout the series. Is this
intentional? If we can't guarantee the level here, better to use the
non-level __tlbi().

-- 
Catalin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v2 1/6] arm64: Detect the ARMv8.4 TTL feature
From: Catalin Marinas @ 2020-05-22 15:50 UTC (permalink / raw)
  To: Zhenyu Ye
  Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
	yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
	suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
	prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
	linux-kernel, maz, akpm
In-Reply-To: <20200423135656.2712-2-yezhenyu2@huawei.com>

On Thu, Apr 23, 2020 at 09:56:51PM +0800, Zhenyu Ye wrote:
> From: Marc Zyngier <maz@kernel.org>
> 
> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> feature allows TLBs to be issued with a level allowing for quicker
> invalidation.
> 
> The TTL field indicates the level of page table walk
> holding the leaf entry for the address being invalidated.
> 
> Let's detect the feature for now. Further patches will implement
> its actual usage.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper
From: Catalin Marinas @ 2020-05-22 15:50 UTC (permalink / raw)
  To: Zhenyu Ye
  Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
	yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
	suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
	prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
	linux-kernel, maz, akpm
In-Reply-To: <20200423135656.2712-3-yezhenyu2@huawei.com>

On Thu, Apr 23, 2020 at 09:56:52PM +0800, Zhenyu Ye wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index bc3949064725..5f9f189bc6d2 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -10,6 +10,7 @@
>  
>  #ifndef __ASSEMBLY__
>  
> +#include <linux/bitfield.h>
>  #include <linux/mm_types.h>
>  #include <linux/sched.h>
>  #include <asm/cputype.h>
> @@ -59,6 +60,35 @@
>  		__ta;						\
>  	})
>  
> +#define TLBI_TTL_MASK	GENMASK_ULL(47, 44)
> +
> +#define __tlbi_level(op, addr, level)					\
> +	do {								\

Nitpick: move "do {" on the same line as __tlbi_level() to reduce the
indentation levels of the whole block.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v2 4/6] tlb: mmu_gather: add tlb_flush_*_range APIs
From: Catalin Marinas @ 2020-05-22 15:50 UTC (permalink / raw)
  To: Zhenyu Ye
  Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
	yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
	suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
	prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
	linux-kernel, maz, akpm
In-Reply-To: <20200423135656.2712-5-yezhenyu2@huawei.com>

On Thu, Apr 23, 2020 at 09:56:54PM +0800, Zhenyu Ye wrote:
> From: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> 
> tlb_flush_{pte|pmd|pud|p4d}_range() adjust the tlb->start and
> tlb->end, then set corresponding cleared_*.
> 
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 09/29] arm64: use asm-generic/cacheflush.h
From: Catalin Marinas @ 2020-05-22 15:54 UTC (permalink / raw)
  To: Christoph Hellwig
  Cc: linux-ia64, linux-sh, Roman Zippel, linux-mips, linux-mm,
	sparclinux, linux-riscv, linux-arch, linux-c6x-dev, linux-hexagon,
	x86, linux-xtensa, Arnd Bergmann, Jessica Yu, linux-um,
	linux-m68k, openrisc, linux-arm-kernel, Michal Simek,
	linux-kernel, linux-alpha, linux-fsdevel, Andrew Morton,
	linuxppc-dev
In-Reply-To: <20200515143646.3857579-10-hch@lst.de>

On Fri, May 15, 2020 at 04:36:26PM +0200, Christoph Hellwig wrote:
> ARM64 needs almost no cache flushing routines of its own.  Rely on
> asm-generic/cacheflush.h for the defaults.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
From: Rob Herring @ 2020-05-22 15:54 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: devicetree, Lorenzo Pieralisi, Arnd Bergmann, PCI,
	linux-kernel@vger.kernel.org, Tom Joseph, Greg Kroah-Hartman,
	Bjorn Helgaas, linux-omap,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20200522033631.32574-4-kishon@ti.com>

On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
> for adding PCIe support in TI's J721E SoC.

Looking more closely I don't think cdns_pcie_ep_assert_intx is okay
with this and never can be given the PCI_COMMAND and PCI_STATUS
registers are in the same word (IIRC, that's the main reason 32-bit
config space accesses are broken). So this isn't going to work at
least for EP accesses. And maybe you need a custom .raise_irq() hook
to minimize any problems (such as making the RMW atomic at least from
the endpoint's perspective).

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v4 3/8] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
From: dillon min @ 2020-05-22 15:59 UTC (permalink / raw)
  To: Mark Brown
  Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	p.zabel, Dave Airlie, Michael Turquette, linux-clk, linux-kernel,
	open list:DRM PANEL DRIVERS, linux-spi, Stephen Boyd, Rob Herring,
	thierry.reding, Maxime Coquelin, Daniel Vetter, Sam Ravnborg,
	linux-stm32, Linux ARM, Alexandre Torgue
In-Reply-To: <CAL9mu0LAnT+AfjpGs0O-MD2HYrpnQRmrj6qXtJQrJi9kbQLPUw@mail.gmail.com>

On Fri, May 22, 2020 at 10:57 PM dillon min <dillon.minfei@gmail.com> wrote:
>
> hi Mark,
>
> Thanks for reviewing.
>
> On Fri, May 22, 2020 at 7:36 PM Mark Brown <broonie@kernel.org> wrote:
> >
> > On Mon, May 18, 2020 at 07:09:20PM +0800, dillon.minfei@gmail.com wrote:
> >
> > > 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is
> > > null, we must add dummy data sent out before read data.
> > > so, add stm32f4_spi_tx_dummy() to handle this situation.
> >
> > There are flags SPI_CONTROLLER_MUST_TX and SPI_CONTROLLER_MUST_RX flags
> > that the driver can set if it needs to, no need to open code this in the
> > driver.
>
> Yes, after check SPI_CONTROLLER_MUST_TX in drivers/spi/spi.c , it's
> indeed to meet
> this situation,  i will try it and sumbmit a new patch.
>
> thanks.
>
> best regards
>
> Dillon

Hi Mark,

There might be a conflict with 'SPI_CONTROLLER_MUST_TX' and 'SPI_3WIRE' mode,
i need to know the SPI_3WIRE direction,  currently i get this
information from 'struct spi_device'
and 'struct spi_transfer'
if ((spi_device->mode & SPI_3WIRE) && (spi_transfer->tx_buf == NULL)
&& (spi_transfer->rx_buf != NULL))
    this is a SPI_3WIRE_RX transfer
if ((spi_device->mode & SPI_3WIRE) && (spi_transfer->tx_buf != NULL)
&& (spi_transfer->rx_buf == NULL))
    this is a SPI_3WIRE_TX transfer

but, after spi-core create a dummy tx_buf or rx_buf, then i can't get
the correct spi_3wire direction.
actually, this dummy tx_buf is useless for SPI_3WIRE. it's has meaning
for SPI_SIMPLE_RX mode,
simulate SPI_FULL_DUMPLEX

how do you think?

thanks

best regards

Dillon

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 5/5] crypto: stm32/crc: protect from concurrent accesses
From: Ard Biesheuvel @ 2020-05-22 16:11 UTC (permalink / raw)
  To: Nicolas Toromanoff
  Cc: Alexandre Torgue, Linux Kernel Mailing List, David S . Miller,
	Linux Crypto Mailing List, Maxime Coquelin, linux-stm32,
	Linux ARM, Herbert Xu
In-Reply-To: <20200512141113.18972-6-nicolas.toromanoff@st.com>

On Tue, 12 May 2020 at 16:13, Nicolas Toromanoff
<nicolas.toromanoff@st.com> wrote:
>
> Protect STM32 CRC device from concurrent accesses.
>
> As we create a spinlocked section that increase with buffer size,
> we provide a module parameter to release the pressure by splitting
> critical section in chunks.
>
> Size of each chunk is defined in burst_size module parameter.
> By default burst_size=0, i.e. don't split incoming buffer.
>
> Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

Would you mind explaining the usage model here? It looks like you are
sharing a CRC hardware accelerator with a synchronous interface
between different users by using spinlocks? You are aware that this
will tie up the waiting CPUs completely during this time, right? So it
would be much better to use a mutex here. Or perhaps it would make
more sense to fall back to a s/w based CRC routine if the h/w is tied
up working for another task?

Using spinlocks for this is really not acceptable.



> ---
>  drivers/crypto/stm32/stm32-crc32.c | 47 ++++++++++++++++++++++++++++--
>  1 file changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/stm32/stm32-crc32.c b/drivers/crypto/stm32/stm32-crc32.c
> index 413415c216ef..3ba41148c2a4 100644
> --- a/drivers/crypto/stm32/stm32-crc32.c
> +++ b/drivers/crypto/stm32/stm32-crc32.c
> @@ -35,11 +35,16 @@
>
>  #define CRC_AUTOSUSPEND_DELAY  50
>
> +static unsigned int burst_size;
> +module_param(burst_size, uint, 0644);
> +MODULE_PARM_DESC(burst_size, "Select burst byte size (0 unlimited)");
> +
>  struct stm32_crc {
>         struct list_head list;
>         struct device    *dev;
>         void __iomem     *regs;
>         struct clk       *clk;
> +       spinlock_t       lock;
>  };
>
>  struct stm32_crc_list {
> @@ -109,6 +114,7 @@ static int stm32_crc_init(struct shash_desc *desc)
>         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
>         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
>         struct stm32_crc *crc;
> +       unsigned long flags;
>
>         crc = stm32_crc_get_next_crc();
>         if (!crc)
> @@ -116,6 +122,8 @@ static int stm32_crc_init(struct shash_desc *desc)
>
>         pm_runtime_get_sync(crc->dev);
>
> +       spin_lock_irqsave(&crc->lock, flags);
> +
>         /* Reset, set key, poly and configure in bit reverse mode */
>         writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
>         writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
> @@ -125,18 +133,21 @@ static int stm32_crc_init(struct shash_desc *desc)
>         /* Store partial result */
>         ctx->partial = readl_relaxed(crc->regs + CRC_DR);
>
> +       spin_unlock_irqrestore(&crc->lock, flags);
> +
>         pm_runtime_mark_last_busy(crc->dev);
>         pm_runtime_put_autosuspend(crc->dev);
>
>         return 0;
>  }
>
> -static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
> -                           unsigned int length)
> +static int burst_update(struct shash_desc *desc, const u8 *d8,
> +                       size_t length)
>  {
>         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
>         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
>         struct stm32_crc *crc;
> +       unsigned long flags;
>
>         crc = stm32_crc_get_next_crc();
>         if (!crc)
> @@ -144,6 +155,8 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
>
>         pm_runtime_get_sync(crc->dev);
>
> +       spin_lock_irqsave(&crc->lock, flags);
> +
>         /*
>          * Restore previously calculated CRC for this context as init value
>          * Restore polynomial configuration
> @@ -182,12 +195,40 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
>         /* Store partial result */
>         ctx->partial = readl_relaxed(crc->regs + CRC_DR);
>
> +       spin_unlock_irqrestore(&crc->lock, flags);
> +
>         pm_runtime_mark_last_busy(crc->dev);
>         pm_runtime_put_autosuspend(crc->dev);
>
>         return 0;
>  }
>
> +static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
> +                           unsigned int length)
> +{
> +       const unsigned int burst_sz = burst_size;
> +       unsigned int rem_sz;
> +       const u8 *cur;
> +       size_t size;
> +       int ret;
> +
> +       if (!burst_sz)
> +               return burst_update(desc, d8, length);
> +
> +       /* Digest first bytes not 32bit aligned at first pass in the loop */
> +       size = min(length,
> +                  burst_sz + (unsigned int)d8 - ALIGN_DOWN((unsigned int)d8,
> +                                                           sizeof(u32)));
> +       for (rem_sz = length, cur = d8; rem_sz;
> +            rem_sz -= size, cur += size, size = min(rem_sz, burst_sz)) {
> +               ret = burst_update(desc, cur, size);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +}
> +
>  static int stm32_crc_final(struct shash_desc *desc, u8 *out)
>  {
>         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
> @@ -300,6 +341,8 @@ static int stm32_crc_probe(struct platform_device *pdev)
>         pm_runtime_irq_safe(dev);
>         pm_runtime_enable(dev);
>
> +       spin_lock_init(&crc->lock);
> +
>         platform_set_drvdata(pdev, crc);
>
>         spin_lock(&crc_list.lock);
> --
> 2.17.1
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [GIT PULL] arm64 fixes for 5.7-rc7
From: Catalin Marinas @ 2020-05-22 16:28 UTC (permalink / raw)
  To: Linus Torvalds; +Cc: Will Deacon, linux-kernel, linux-arm-kernel

Hi Linus,

Please pull the arm64 fixes below. Thanks.

The following changes since commit d51c214541c5154dda3037289ee895ea3ded5ebd:

  arm64: fix the flush_icache_range arguments in machine_kexec (2020-05-11 12:02:14 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

for you to fetch changes up to 8cfb347ad0cffdbfc69c82506fb3be9429563211:

  arm64: Add get_user() type annotation on the !access_ok() path (2020-05-22 16:59:49 +0100)

----------------------------------------------------------------
- Bring the PTRACE_SYSEMU semantics in line with the man page.
- Annotate variable assignment in get_user() with the type to avoid
  sparse warnings.

----------------------------------------------------------------
Al Viro (1):
      arm64: Add get_user() type annotation on the !access_ok() path

Keno Fischer (1):
      arm64: Fix PTRACE_SYSEMU semantics

 arch/arm64/include/asm/uaccess.h | 2 +-
 arch/arm64/kernel/ptrace.c       | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

-- 
Catalin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v4 3/8] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
From: Mark Brown @ 2020-05-22 16:29 UTC (permalink / raw)
  To: dillon min
  Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	p.zabel, Dave Airlie, Michael Turquette, linux-clk, linux-kernel,
	open list:DRM PANEL DRIVERS, linux-spi, Stephen Boyd, Rob Herring,
	thierry.reding, Maxime Coquelin, Daniel Vetter, Sam Ravnborg,
	linux-stm32, Linux ARM, Alexandre Torgue
In-Reply-To: <CAL9mu0JZ4Qy+m2oF9TSTRqA_mM0J89huCt3t_Gs7qHa=3LxhBw@mail.gmail.com>


[-- Attachment #1.1: Type: text/plain, Size: 446 bytes --]

On Fri, May 22, 2020 at 11:59:25PM +0800, dillon min wrote:

> but, after spi-core create a dummy tx_buf or rx_buf, then i can't get
> the correct spi_3wire direction.
> actually, this dummy tx_buf is useless for SPI_3WIRE. it's has meaning
> for SPI_SIMPLE_RX mode,
> simulate SPI_FULL_DUMPLEX

Oh, that's annoying.  I think the fix here is in the core, it should
ignore MUST_TX and MUST_RX in 3WIRE mode since they clearly make no
sense there.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [GIT PULL] arm64 fixes for 5.7-rc7
From: pr-tracker-bot @ 2020-05-22 16:40 UTC (permalink / raw)
  To: Catalin Marinas
  Cc: Will Deacon, Linus Torvalds, linux-kernel, linux-arm-kernel
In-Reply-To: <20200522162815.GA20565@gaia>

The pull request you sent on Fri, 22 May 2020 17:28:17 +0100:

> git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4286d192c803571e8ca43b0f1f8ea04d663a278a

Thank you!

-- 
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/prtracker

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup
From: Rob Herring @ 2020-05-22 16:45 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: devicetree, Lorenzo Pieralisi, Arnd Bergmann, Greg Kroah-Hartman,
	linux-kernel@vger.kernel.org, Tom Joseph, PCI, Bjorn Helgaas,
	linux-omap,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <3f9cf6e5-94f8-4c54-aaee-c181b0e79f1f@ti.com>

On Thu, May 21, 2020 at 5:35 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi Rob,
>
> On 5/21/2020 3:04 AM, Rob Herring wrote:
> > On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote:
> >> Cadence driver uses "mem" memory resource to obtain the offset of
> >> configuration space address region, memory space address region and
> >> message space address region. The obtained offset is used to program
> >> the Address Translation Unit (ATU). However certain platforms like TI's
> >> J721E SoC require the absolute address to be programmed in the ATU and not
> >> just the offset.
> >
> > Once again, Cadence host binding is broken (or at least the example is).
> > The 'mem' region shouldn't even exist. It is overlapping the config
> > space and 'ranges':
> >
> >             reg = <0x0 0xfb000000  0x0 0x01000000>,
> >                   <0x0 0x41000000  0x0 0x00001000>,
> >                   <0x0 0x40000000  0x0 0x04000000>;
> >             reg-names = "reg", "cfg", "mem";
> >
> >             ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
> >                      <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
> >
> >
> > 16M of registers looks a bit odd. I guess it doesn't matter
> > unless you have a 32-bit platform and care about your virtual
> > space. Probably should have been 3 regions for LM, RP, and AT looking
> > at the driver.
>
> The "mem" region in never ioremapped. However $patch removes requiring to add
> "mem" memory resource.

I was referring to ioremapping 'reg' region.

> >
> > Whatever outbound address translation you need should be based on
> > 'ranges'.
>
> You mean we don't need to add "new *ops* for CPU addr fixup"?. The issue is
> ranges provides CPU address and PCI address. The CPU will access whatever is
> populated in ranges to access the PCI bus. However while programming the ATU,
> we cannot use the CPU address provided in ranges directly (in some platforms)
> because the controller does not see the full address and only the lower 28bits.

Okay, that is clearer as to what the difference is. I think this
should be 2 patches. One dropping 'mem' usage and using a mask and the
2nd making the mask per platform.

Really, the parent node of the PCI controller should probably have
'ranges' and you could extract a mask from that. Looks like that is
what you had for DRA7... I'm not sure if ABI stability is important
for the Cadence platform. I'd assume that's just some IP eval system
and probably not?

Why do you need an ops here? All you need is a mask value.

> This similar restriction was there with Designware (mostly an integration
> issue) and we used *ops* to fixup the address that has to be programmed in ATU.
> The Designware initially used a wrapper so that ranges property can be directly
> used [1]. However this approach was later removed in [2]
>
> [1] -> https://lore.kernel.org/patchwork/patch/468523/
> [2] -> https://lkml.org/lkml/2015/10/16/232

So while you had the data for a mask in DT, the driver now hardcodes it?

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 2/2] firmware: smccc: Add ARCH_SOC_ID support
From: Sudeep Holla @ 2020-05-22 16:54 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Mark Rutland, Francois Ozog, Lorenzo Pieralisi, Jose.Marinho,
	Greg Kroah-Hartman, linux-kernel@vger.kernel.org, harb,
	Sudeep Holla, Will Deacon, Linux ARM
In-Reply-To: <CAK8P3a1t6BrB_Gti138VDRbmaiR_TjwR9d6qMstLBFDWxZ1kjQ@mail.gmail.com>

(+ Jose (SMCCC Spec author))

On Fri, May 22, 2020 at 04:46:12PM +0200, Arnd Bergmann wrote:
> On Fri, May 22, 2020 at 2:50 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > +
> > +       soc_id_rev = res.a0;
> > +
> > +       soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
> > +       if (!soc_dev_attr)
> > +               return -ENOMEM;
> > +
> > +       sprintf(soc_id_str, "0x%04x", IMP_DEF_SOC_ID(soc_id_version));
> > +       sprintf(soc_id_rev_str, "0x%08x", soc_id_rev);
> > +       sprintf(soc_id_jep106_id_str, "0x%02x%02x",
> > +               JEP106_BANK_CONT_CODE(soc_id_version),
> > +               JEP106_ID_CODE(soc_id_version));
> > +
> > +       soc_dev_attr->soc_id = soc_id_str;
> > +       soc_dev_attr->revision = soc_id_rev_str;
> > +       soc_dev_attr->jep106_id = soc_id_jep106_id_str;
>
> Ok, let me try to understand how this maps the 64-bit ID into the
> six strings in user space:
>
> For a chip that identifies as
>
> JEP106_BANK_CONT_CODE = 12
> JEP106_ID_CODE = 34
> IMP_DEF_SOC_ID = 5678
> soc_id_rev = 9abcdef0
>
> the normal sysfs attributes contain these strings:
>
> machine = ""
> family = ""
> revision = "0x9abcdef0
> serial_number = ""
> soc_id = "0x5678"
>
> and the new attribute is
>
> jep106_identification_code = "0x1234"
>
> This still looks like a rather poorly designed interface to me, with a
> number of downsides:
>
> - Nothing in those strings identifies the numbers as using jep106
>   numbers rather than some something else that might use strings
>   with hexadecimal numbers.
>

Not sure if I understand your concerns completely here.

Anyways I wanted to clarify that the jep106 encoding is applicable only
for manufacturer's id and not for SoC ID or revision. Not sure if that
changes anything about your concerns.

> - I think we should have something unique in "family" just because
>   existing scripts can use that as the primary indentifier
>

I agree with your idea of combining attributes, not sure exactly which
ones yet.

> - It seems odd that there is no way to read the serial number through
>   the same interface and publish it the usual way.

Valid concern and I will pass this to interface authors.

>   Francois Ozog
>   recently asked for a generic way to find out a serial number for
>   inventory management, and this would be the obvious place to have it.

Agreed, but not sure what author(s) have to say. I have cc-ed one of them.

>   It can of course be added later when the next revision of the spec
>   is there, it just seems like a surprising omission.
>

Yes, definitely. Good to get feedback.

> How about making the contents:
>
> machine = "" /* could be a future addition, but board specific */
> family = "jep106:1234"

But this just indicates manufacturer id and nothing related to SoC family.
If it is jep106:043b, all it indicates is Arm Ltd and assigning it to
family doesn't sound right to me.

I had requests for both of the above during the design of interface but
I was told vendors were happy with the interface. I will let the authors
speak about that.

> revision = "0x9abcdef0
> serial_number = "0xfedcba987654321" /* to be implemented later */

Sure.

> soc_id = "jep106:1234:5678" /* duplicates family but makes it unique*/

Not sure again.
>
> That would work without any new properties, dropping the other patch,
> and be easier to use for identification from user space.
>

OK, I agree on ease part. But for me, we don't have any property in the
list to indicate the vendor/manufacturer's name. I don't see issue adding
one, name can be fixed as jep106_identification_code is too specific.

How about manufacturer with the value in the format "jep106:1234" if
it is not normal string but jep106 encoding.

--
Regards,
Sudeep

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 3/4] remoteproc: add support for a new 64-bit trace version
From: Suman Anna @ 2020-05-22 16:54 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: devicetree, Mathieu Poirier, Loic Pallardy, Lokesh Vutla,
	linux-remoteproc, Arnaud Pouliquen, linux-kernel, Clement Leger,
	Rob Herring, linux-arm-kernel
In-Reply-To: <997d6f9a-64ba-7a89-e909-9a5a474120b0@ti.com>

On 5/21/20 2:42 PM, Suman Anna wrote:
> Hi Bjorn,
> 
> On 5/21/20 1:04 PM, Bjorn Andersson wrote:
>> On Wed 25 Mar 13:47 PDT 2020, Suman Anna wrote:
>>
>>> Introduce a new trace entry resource structure that accommodates
>>> a 64-bit device address to support 64-bit processors. This is to
>>> be used using an overloaded version value of 1 in the upper 32-bits
>>> of the previous resource type field. The new resource still uses
>>> 32-bits for the length field (followed by a 32-bit reserved field,
>>> so can be updated in the future), which is a sufficiently large
>>> trace buffer size. A 32-bit padding field also had to be added
>>> to align the device address on a 64-bit boundary, and match the
>>> usage on the firmware side.
>>>
>>> The remoteproc debugfs logic also has been adjusted accordingly.
>>>
>>> Signed-off-by: Suman Anna <s-anna@ti.com>
>>> ---
>>>   drivers/remoteproc/remoteproc_core.c    | 40 ++++++++++++++++++++-----
>>>   drivers/remoteproc/remoteproc_debugfs.c | 37 ++++++++++++++++++-----
>>>   include/linux/remoteproc.h              | 26 ++++++++++++++++
>>>   3 files changed, 87 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/remoteproc/remoteproc_core.c 
>>> b/drivers/remoteproc/remoteproc_core.c
>>> index 53bc37c508c6..b9a097990862 100644
>>> --- a/drivers/remoteproc/remoteproc_core.c
>>> +++ b/drivers/remoteproc/remoteproc_core.c
>>> @@ -609,21 +609,45 @@ void rproc_vdev_release(struct kref *ref)
>>>    *
>>>    * Returns 0 on success, or an appropriate error code otherwise
>>>    */
>>> -static int rproc_handle_trace(struct rproc *rproc, struct 
>>> fw_rsc_trace *rsc,
>>> +static int rproc_handle_trace(struct rproc *rproc, void *rsc,
>>>                     int offset, int avail, u16 ver)
>>>   {
>>>       struct rproc_debug_trace *trace;
>>>       struct device *dev = &rproc->dev;
>>> +    struct fw_rsc_trace *rsc1;
>>> +    struct fw_rsc_trace2 *rsc2;
>>>       char name[15];
>>> +    size_t rsc_size;
>>> +    u32 reserved;
>>> +    u64 da;
>>> +    u32 len;
>>> +
>>> +    if (!ver) {
>>
>> This looks like a switch to me, but I also do think this looks rather
>> crude, if you spin off the tail of this function and call it from a
>> rproc_handle_trace() and rproc_handle_trace64() I believe this would be
>> cleaner.
> 
> Yeah, ok. Will refactor for this in v2.
> 
>>
>>> +        rsc1 = (struct fw_rsc_trace *)rsc;
>>> +        rsc_size = sizeof(*rsc1);
>>> +        reserved = rsc1->reserved;
>>> +        da = rsc1->da;
>>> +        len = rsc1->len;
>>> +    } else if (ver == 1) {
>>> +        rsc2 = (struct fw_rsc_trace2 *)rsc;
>>> +        rsc_size = sizeof(*rsc2);
>>> +        reserved = rsc2->reserved;
>>> +        da = rsc2->da;
>>> +        len = rsc2->len;
>>> +    } else {
>>> +        dev_err(dev, "unsupported trace rsc version %d\n", ver);
>>
>> If we use "type" to describe your 64-bit-da-trace then this sanity check
>> would have been taken care of by the core.
>>
>>> +        return -EINVAL;
>>> +    }
>>> -    if (sizeof(*rsc) > avail) {
>>> +    if (rsc_size > avail) {
>>>           dev_err(dev, "trace rsc is truncated\n");
>>>           return -EINVAL;
>>>       }
>>>       /* make sure reserved bytes are zeroes */
>>> -    if (rsc->reserved) {
>>> -        dev_err(dev, "trace rsc has non zero reserved bytes\n");
>>> +    if (reserved) {
>>> +        dev_err(dev, "trace rsc has non zero reserved bytes, value = 
>>> 0x%x\n",
>>> +            reserved);
>>>           return -EINVAL;
>>>       }
>>> @@ -632,8 +656,8 @@ static int rproc_handle_trace(struct rproc 
>>> *rproc, struct fw_rsc_trace *rsc,
>>>           return -ENOMEM;
>>>       /* set the trace buffer dma properties */
>>> -    trace->trace_mem.len = rsc->len;
>>> -    trace->trace_mem.da = rsc->da;
>>> +    trace->trace_mem.len = len;
>>> +    trace->trace_mem.da = da;
>>>       /* set pointer on rproc device */
>>>       trace->rproc = rproc;
>>> @@ -652,8 +676,8 @@ static int rproc_handle_trace(struct rproc 
>>> *rproc, struct fw_rsc_trace *rsc,
>>>       rproc->num_traces++;
>>> -    dev_dbg(dev, "%s added: da 0x%x, len 0x%x\n",
>>> -        name, rsc->da, rsc->len);
>>> +    dev_dbg(dev, "%s added: da 0x%llx, len 0x%x\n",
>>> +        name, da, len);
>>>       return 0;
>>>   }
>>> diff --git a/drivers/remoteproc/remoteproc_debugfs.c 
>>> b/drivers/remoteproc/remoteproc_debugfs.c
>>> index 3560eed7a360..ff43736db45a 100644
>>> --- a/drivers/remoteproc/remoteproc_debugfs.c
>>> +++ b/drivers/remoteproc/remoteproc_debugfs.c
>>> @@ -192,7 +192,8 @@ static int rproc_rsc_table_show(struct seq_file 
>>> *seq, void *p)
>>>       struct resource_table *table = rproc->table_ptr;
>>>       struct fw_rsc_carveout *c;
>>>       struct fw_rsc_devmem *d;
>>> -    struct fw_rsc_trace *t;
>>> +    struct fw_rsc_trace *t1;
>>> +    struct fw_rsc_trace2 *t2;
>>>       struct fw_rsc_vdev *v;
>>>       int i, j;
>>> @@ -205,6 +206,7 @@ static int rproc_rsc_table_show(struct seq_file 
>>> *seq, void *p)
>>>           int offset = table->offset[i];
>>>           struct fw_rsc_hdr *hdr = (void *)table + offset;
>>>           void *rsc = (void *)hdr + sizeof(*hdr);
>>> +        u16 ver = hdr->st.v;
>>>           switch (hdr->st.t) {
>>>           case RSC_CARVEOUT:
>>> @@ -230,13 +232,32 @@ static int rproc_rsc_table_show(struct seq_file 
>>> *seq, void *p)
>>>               seq_printf(seq, "  Name %s\n\n", d->name);
>>>               break;
>>>           case RSC_TRACE:
>>> -            t = rsc;
>>> -            seq_printf(seq, "Entry %d is of type %s\n",
>>> -                   i, types[hdr->st.t]);
>>> -            seq_printf(seq, "  Device Address 0x%x\n", t->da);
>>> -            seq_printf(seq, "  Length 0x%x Bytes\n", t->len);
>>> -            seq_printf(seq, "  Reserved (should be zero) [%d]\n", 
>>> t->reserved);
>>> -            seq_printf(seq, "  Name %s\n\n", t->name);
>>> +            if (ver == 0) {
>>
>> Again, this is a switch, here in a switch. Just defining a new
>> RSC_TRACE64 type would reduce the amount of code here...
> 
> OK.
> 
>>
>>> +                t1 = rsc;
>>> +                seq_printf(seq, "Entry %d is version %d of type %s\n",
>>> +                       i, ver, types[hdr->st.t]);
>>> +                seq_printf(seq, "  Device Address 0x%x\n",
>>> +                       t1->da);
>>> +                seq_printf(seq, "  Length 0x%x Bytes\n",
>>> +                       t1->len);
>>> +                seq_printf(seq, "  Reserved (should be zero) [%d]\n",
>>> +                       t1->reserved);
>>> +                seq_printf(seq, "  Name %s\n\n", t1->name);
>>> +            } else if (ver == 1) {
>>> +                t2 = rsc;
>>> +                seq_printf(seq, "Entry %d is version %d of type %s\n",
>>> +                       i, ver, types[hdr->st.t]);
>>> +                seq_printf(seq, "  Device Address 0x%llx\n",
>>> +                       t2->da);
>>> +                seq_printf(seq, "  Length 0x%x Bytes\n",
>>> +                       t2->len);
>>> +                seq_printf(seq, "  Reserved (should be zero) [%d]\n",
>>> +                       t2->reserved);
>>> +                seq_printf(seq, "  Name %s\n\n", t2->name);
>>> +            } else {
>>> +                seq_printf(seq, "Entry %d is an unsupported version 
>>> %d of type %s\n",
>>> +                       i, ver, types[hdr->st.t]);
>>> +            }
>>>               break;
>>>           case RSC_VDEV:
>>>               v = rsc;
>>> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
>>> index 526d3cb45e37..3b3bea42f8b1 100644
>>> --- a/include/linux/remoteproc.h
>>> +++ b/include/linux/remoteproc.h
>>> @@ -243,6 +243,32 @@ struct fw_rsc_trace {
>>>       u8 name[32];
>>>   } __packed;
>>> +/**
>>> + * struct fw_rsc_trace2 - trace buffer declaration supporting 64-bits
>>> + * @padding: initial padding after type field for aligned 64-bit access
>>> + * @da: device address (64-bit)
>>> + * @len: length (in bytes)
>>> + * @reserved: reserved (must be zero)
>>> + * @name: human-readable name of the trace buffer
>>> + *
>>> + * This resource entry is an enhanced version of the fw_rsc_trace 
>>> resourec entry
>>> + * and the provides equivalent functionality but designed for 64-bit 
>>> remote
>>> + * processors.
>>> + *
>>> + * @da specifies the device address of the buffer, @len specifies
>>> + * its size, and @name may contain a human readable name of the 
>>> trace buffer.
>>> + *
>>> + * After booting the remote processor, the trace buffers are exposed 
>>> to the
>>> + * user via debugfs entries (called trace0, trace1, etc..).
>>> + */
>>> +struct fw_rsc_trace2 {
>>
>> Sounds more like fw_rsc_trace64 to me - in particular since the version
>> of trace2 is 1...
> 
> Yeah, will rename this.
> 
>>
>>> +    u32 padding;
>>> +    u64 da;
>>> +    u32 len;
>>> +    u32 reserved;
>>
>> What's the purpose of this reserved field?
> 
> Partly to make sure the entire resource is aligned on an 8-byte, and 
> partly copied over from fw_rsc_trace entry. I guess 32-bits is already 
> large enough of a size for trace entries irrespective of 32-bit or 
> 64-bit traces, so I doubt if we want to make the len field also a u64.

Looking at this again, I can drop both padding and reserved fields, if I 
move the len field before da. Any preferences/comments?

regards
Suman

> 
> regards
> Suman
> 
>>
>> Regards,
>> Bjorn
>>
>>> +    u8 name[32];
>>> +} __packed;
>>> +
>>>   /**
>>>    * struct fw_rsc_vdev_vring - vring descriptor entry
>>>    * @da: device address
>>> -- 
>>> 2.23.0
>>>
> 


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 4/4] thermal: qoriq: Add platform dependencies
From: Daniel Lezcano @ 2020-05-22 16:57 UTC (permalink / raw)
  To: Geert Uytterhoeven, Shawn Guo, Li Yang, Jens Axboe,
	Michael Turquette, Stephen Boyd, Rafael J . Wysocki, Viresh Kumar,
	Zhang Rui
  Cc: Amit Kucheria, Arnd Bergmann, linux-pm, linux-kernel, linux-ide,
	linux-clk, linux-arm-kernel
In-Reply-To: <20200507112955.23520-5-geert+renesas@glider.be>

On 07/05/2020 13:29, Geert Uytterhoeven wrote:
> The QorIQ Thermal Monitoring Unit is only present on Freescale E500MC
> and Layerscape SoCs, and on NXP i.MX8 SoCs.  Add platform dependencies
> to the QORIQ_THERMAL config symbol, to avoid asking the user about it
> when configuring a kernel without support for any of the aforementioned
> SoCs.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Applied, thanks



-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH 2/2] firmware: smccc: Add ARCH_SOC_ID support
From: Sudeep Holla @ 2020-05-22 17:13 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Mark Rutland, Francois Ozog, Lorenzo Pieralisi, Jose.Marinho,
	Greg Kroah-Hartman, linux-kernel@vger.kernel.org, harb,
	Sudeep Holla, Will Deacon, Linux ARM
In-Reply-To: <20200522165422.GA18810@bogus>

On Fri, May 22, 2020 at 05:54:22PM +0100, Sudeep Holla wrote:
> (+ Jose (SMCCC Spec author))
> 
> On Fri, May 22, 2020 at 04:46:12PM +0200, Arnd Bergmann wrote:
> > On Fri, May 22, 2020 at 2:50 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > > +
> > > +       soc_id_rev = res.a0;
> > > +
> > > +       soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
> > > +       if (!soc_dev_attr)
> > > +               return -ENOMEM;
> > > +
> > > +       sprintf(soc_id_str, "0x%04x", IMP_DEF_SOC_ID(soc_id_version));
> > > +       sprintf(soc_id_rev_str, "0x%08x", soc_id_rev);
> > > +       sprintf(soc_id_jep106_id_str, "0x%02x%02x",
> > > +               JEP106_BANK_CONT_CODE(soc_id_version),
> > > +               JEP106_ID_CODE(soc_id_version));
> > > +
> > > +       soc_dev_attr->soc_id = soc_id_str;
> > > +       soc_dev_attr->revision = soc_id_rev_str;
> > > +       soc_dev_attr->jep106_id = soc_id_jep106_id_str;
> >
> > Ok, let me try to understand how this maps the 64-bit ID into the
> > six strings in user space:
> >
> > For a chip that identifies as
> >
> > JEP106_BANK_CONT_CODE = 12
> > JEP106_ID_CODE = 34
> > IMP_DEF_SOC_ID = 5678
> > soc_id_rev = 9abcdef0
> >
> > the normal sysfs attributes contain these strings:
> >
> > machine = ""
> > family = ""
> > revision = "0x9abcdef0
> > serial_number = ""
> > soc_id = "0x5678"
> >
> > and the new attribute is
> >
> > jep106_identification_code = "0x1234"
> >
> > This still looks like a rather poorly designed interface to me, with a
> > number of downsides:
> >
> > - Nothing in those strings identifies the numbers as using jep106
> >   numbers rather than some something else that might use strings
> >   with hexadecimal numbers.
> >
> 
> Not sure if I understand your concerns completely here.
> 
> Anyways I wanted to clarify that the jep106 encoding is applicable only
> for manufacturer's id and not for SoC ID or revision. Not sure if that
> changes anything about your concerns.
> 
> > - I think we should have something unique in "family" just because
> >   existing scripts can use that as the primary indentifier
> >
> 
> I agree with your idea of combining attributes, not sure exactly which
> ones yet.
> 
> > - It seems odd that there is no way to read the serial number through
> >   the same interface and publish it the usual way.
> 
> Valid concern and I will pass this to interface authors.
> 
> >   Francois Ozog
> >   recently asked for a generic way to find out a serial number for
> >   inventory management, and this would be the obvious place to have it.
> 
> Agreed, but not sure what author(s) have to say. I have cc-ed one of them.
> 
> >   It can of course be added later when the next revision of the spec
> >   is there, it just seems like a surprising omission.
> >
> 
> Yes, definitely. Good to get feedback.
> 
> > How about making the contents:
> >
> > machine = "" /* could be a future addition, but board specific */
[...]
> > serial_number = "0xfedcba987654321" /* to be implemented later */

OK more thoughts and few points I missed earlier. The SoC infrastructure
is more wider than the SoC itself IMO. The machine and serial_number
are beyond the SoC and this SMCCC SOC_ID confined itself to SoC for
simple reason that it is part of SoC vendor firmware which could be
used across various machines/boards/platforms.

I wonder now that rather than adding this as a SoC sysfs driver on it's
own, does it make sense to keep it as library which existing drivers
can use. Or we need to standardise the machine level interface that may
like outside SoC firmware and use both to have a generic SoC sysfs driver.

Sorry, I am just writing as I am thinking and may be talking garbage.

-- 
Regards,
Sudeep

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [RFC] Use SMMU HTTU for DMA dirty page tracking
From: Jean-Philippe Brucker @ 2020-05-22 17:14 UTC (permalink / raw)
  To: Xiang Zheng
  Cc: Suzuki K Poulose, maz, iommu, wangzhou1, James Morse,
	julien.thierry.kdev, prime.zeng, Wang Haibin, Will Deacon, kvmarm,
	linux-arm-kernel
In-Reply-To: <b926ec0b-fe87-0792-c41d-acad56c656a4@huawei.com>

Hi,

On Tue, May 19, 2020 at 05:42:55PM +0800, Xiang Zheng wrote:
> Hi all,
> 
> Is there any plan for enabling SMMU HTTU?

Not outside of SVA, as far as I know.

> I have seen the patch locates in the SVA series patch, which adds
> support for HTTU:
>     https://www.spinics.net/lists/arm-kernel/msg798694.html
> 
> HTTU reduces the number of access faults on SMMU fault queue
> (permission faults also benifit from it).
> 
> Besides reducing the faults, HTTU also helps to track dirty pages for
> device DMA. Is it feasible to utilize HTTU to get dirty pages on device
> DMA during VFIO live migration?

As you know there is a VFIO interface for this under discussion:
https://lore.kernel.org/kvm/1589781397-28368-1-git-send-email-kwankhede@nvidia.com/
It doesn't implement an internal API to communicate with the IOMMU driver
about dirty pages.

> If SMMU can track dirty pages, devices are not required to implement
> additional dirty pages tracking to support VFIO live migration.

It seems feasible, though tracking it in the device might be more
efficient. I might have misunderstood but I think for live migration of
the Intel NIC they trap guest accesses to the device and introspect its
state to figure out which pages it is accessing.

With HTTU I suppose (without much knowledge about live migration) that
you'd need several new interfaces to the IOMMU drivers:

* A way for VFIO to query HTTU support in the SMMU. There are some
  discussions about communicating more IOMMU capabilities through VFIO but
  no implementation yet. When HTTU isn't supported the DIRTY_PAGES bitmap
  would report all pages as they do now.

* VFIO_IOMMU_DIRTY_PAGES_FLAG_START/STOP would clear the dirty bit
  for all VFIO mappings (which is going to take some time). There is a
  walker in io-pgtable for iova_to_phys() which could be extended. I
  suppose it's also possible to atomically switch the HA and HD bits in
  context descriptors.

* VFIO_IOMMU_DIRTY_PAGES_FLAG_GET_BITMAP would query the dirty bit for all
  VFIO mappings.

Thanks,
Jean

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* Re: [PATCH] thermal: imx8mm: Add get_trend ops
From: Daniel Lezcano @ 2020-05-22 17:33 UTC (permalink / raw)
  To: Anson Huang, rui.zhang, amit.kucheria, shawnguo, s.hauer, kernel,
	festevam, linux-pm, linux-arm-kernel, linux-kernel
  Cc: Linux-imx
In-Reply-To: <1589338689-15700-1-git-send-email-Anson.Huang@nxp.com>

On 13/05/2020 04:58, Anson Huang wrote:
> Add get_trend ops for i.MX8MM thermal to apply fast cooling
> mechanism, when temperature exceeds passive trip point, the
> highest cooling action will be applied, and when temperature
> drops to lower than the margin below passive trip point, the
> lowest cooling action will be applied.

You are not describing what is the goal of this change.

IIUC, the resulting change will be an on/off action. The thermal zone is
mitigated with the highest cooling effect, so the lowest OPP, then the
temperature trend is stable until it goes below the trip - margin where
the mitigation is stopped.

Except, I'm missing something, setting a trip point with a 10000
hysteresis and a cooling map min/max set to the highest opp will result
on the same.


> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
>  drivers/thermal/imx8mm_thermal.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c
> index e6061e2..8f6a0b8 100644
> --- a/drivers/thermal/imx8mm_thermal.c
> +++ b/drivers/thermal/imx8mm_thermal.c
> @@ -38,6 +38,8 @@
>  #define TMU_VER1		0x1
>  #define TMU_VER2		0x2
>  
> +#define IMX_TEMP_COOL_MARGIN	10000
> +
>  struct thermal_soc_data {
>  	u32 num_sensors;
>  	u32 version;
> @@ -103,8 +105,33 @@ static int tmu_get_temp(void *data, int *temp)
>  	return tmu->socdata->get_temp(data, temp);
>  }
>  
> +static int tmu_get_trend(void *p, int trip, enum thermal_trend *trend)
> +{
> +	struct tmu_sensor *sensor = p;
> +	int trip_temp, temp, ret;
> +
> +	if (!sensor->tzd)
> +		return -EINVAL;
> +
> +	ret = sensor->tzd->ops->get_trip_temp(sensor->tzd, trip, &trip_temp);
> +	if (ret)
> +		return ret;
> +
> +	temp = READ_ONCE(sensor->tzd->temperature);
> +
> +	if (temp > trip_temp)
> +		*trend = THERMAL_TREND_RAISE_FULL;
> +	else if (temp < (trip_temp - IMX_TEMP_COOL_MARGIN))
> +		*trend = THERMAL_TREND_DROP_FULL;
> +	else
> +		*trend = THERMAL_TREND_STABLE;
> +
> +	return 0;
> +}
> +
>  static struct thermal_zone_of_device_ops tmu_tz_ops = {
>  	.get_temp = tmu_get_temp,
> +	.get_trend = tmu_get_trend,
>  };
>  
>  static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable)
> 


-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply


This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox