* Re: [PATCH 3/5] arm: decompressor: define a new zImage tag
From: Russell King - ARM Linux admin @ 2020-06-01 14:55 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Kees Cook, Bartlomiej Zolnierkiewicz, Masahiro Yamada,
Nick Desaulniers, linux-kernel, AKASHI Takahiro, Ben Dooks,
Thomas Gleixner, Enrico Weigelt, Ingo Molnar, linux-arm-kernel,
Marek Szyprowski
In-Reply-To: <20200601142754.26139-4-l.stelmach@samsung.com>
On Mon, Jun 01, 2020 at 04:27:52PM +0200, Łukasz Stelmach wrote:
> Add DCSZ tag which holds dynamic memory (stack, bss, malloc pool)
> requirements of the decompressor code.
Why do we need to know the stack and BSS size, when the userspace
kexec tool doesn't need to know this to perform the same function.
>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
> ---
> arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
> arch/arm/include/asm/image.h | 13 +++++++++++++
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
> index 308e9cd6a897..dcfdb3209c90 100644
> --- a/arch/arm/boot/compressed/vmlinux.lds.S
> +++ b/arch/arm/boot/compressed/vmlinux.lds.S
> @@ -39,6 +39,11 @@ SECTIONS
> LONG(ARM_ZIMAGE_MAGIC3)
> LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start))
> LONG(ZIMAGE_MAGIC(_kernel_bss_size))
> + LONG(ZIMAGE_MAGIC(5))
> + LONG(ARM_ZIMAGE_MAGIC4)
> + LONG(ZIMAGE_MAGIC(_end - __bss_start))
> + LONG(ZIMAGE_MAGIC(_stack_end - _stack_start))
> + LONG(ZIMAGE_MAGIC(_malloc_size))
> LONG(0)
> _table_end = .;
> }
> @@ -108,10 +113,12 @@ SECTIONS
> . = BSS_START;
> __bss_start = .;
> .bss : { *(.bss) }
> + . = ALIGN(8); /* the stack must be 64-bit aligned and adjoin bss */
> _end = .;
>
> - . = ALIGN(8); /* the stack must be 64-bit aligned */
> + _stack_start = .;
> .stack : { *(.stack) }
> + _stack_end = .;
>
> PROVIDE(__pecoff_data_size = ALIGN(512) - ADDR(.data));
> PROVIDE(__pecoff_end = ALIGN(512));
> diff --git a/arch/arm/include/asm/image.h b/arch/arm/include/asm/image.h
> index d5c18a0f6a34..624438740f23 100644
> --- a/arch/arm/include/asm/image.h
> +++ b/arch/arm/include/asm/image.h
> @@ -15,6 +15,7 @@
> #define ARM_ZIMAGE_MAGIC1 ZIMAGE_MAGIC(0x016f2818)
> #define ARM_ZIMAGE_MAGIC2 (0x45454545)
> #define ARM_ZIMAGE_MAGIC3 ZIMAGE_MAGIC(0x5a534c4b)
> +#define ARM_ZIMAGE_MAGIC4 ZIMAGE_MAGIC(0x5a534344)
>
> #ifndef __ASSEMBLY__
>
> @@ -43,6 +44,18 @@ struct arm_zimage_tag {
> } u;
> };
>
> +struct arm_zimage_tag_dc {
> + struct tag_header hdr;
> + union {
> +#define ZIMAGE_TAG_DECOMP_SIZE ARM_ZIMAGE_MAGIC4
> + struct zimage_decomp_size {
> + __le32 bss_size;
> + __le32 stack_size;
> + __le32 malloc_size;
> + } decomp_size;
> + } u;
> +};
> +
> #endif /* __ASSEMBLY__ */
>
> #endif /* __ASM_IMAGE_H */
> --
> 2.26.2
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC for 0.8m (est. 1762m) line in suburbia: sync at 13.1Mbps down 424kbps up
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
From: Parthiban @ 2020-06-01 14:55 UTC (permalink / raw)
To: Marco Felsch
Cc: devicetree, Parthiban, shawnguo, s.hauer, linux-kernel, robh+dt,
linux-imx, kernel, festevam, linux-arm-kernel
In-Reply-To: <20200427061844.i5hb2xatq2ntdqbe@pengutronix.de>
On 4/27/20 8:18 AM, Marco Felsch wrote:
> Hi Parthiban,
>
> a few more minor comments..
>
> On 20-04-08 20:43, Parthiban Nallathambi wrote:
>
> ...
>
>> diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> new file mode 100644
>> index 000000000000..f0a514187c21
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> @@ -0,0 +1,247 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Linumiz
>> + * Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/pwm/pwm.h>
>> +
>> +/ {
>> + model = "MYiR MYS-6ULX Single Board Computer";
>> + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull";
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + regulators: regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + vdd_5v: regulator@0 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_5V";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_3v3: regulator@1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + vin-supply = <&vdd_5v>;
>> + };
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet1>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy0>;
>> + phy-supply = <&vdd_3v3>;
>> + status = "okay";
>> +
>> + mdio: mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + reg = <0>;
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + interrupt-parent = <&gpio5>;
>> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
>> + clock-names = "rmii-ref";
>> + status = "okay";
>
> Status not needed here.
Thanks, removed it.
>
>> + };
>> + };
>> +};
>> +
>> +&gpmi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpmi_nand>;
>> + nand-on-flash-bbt;
>> + status = "disabled";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + wakeup-source;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "disabled";
>
> Status not needed here.
Removed, thanks.
>
> Regards,
> Marco
>
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_enet1: enet1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>> + >;
>> + };
>> +
>> + pinctrl_gpmi_nand: gpminandgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
>> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
>> + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
>> + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>> + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
>> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
>> + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
>> + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
>> + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
>> + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
>> + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
>> + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
>> + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
>> + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
>> + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> + >;
>> + };
>> +};
>> --
>> 2.11.0
>>
--
Thanks,
Parthiban N
+4915163761545
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^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
From: Parthiban @ 2020-06-01 14:54 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree, Parthiban, s.hauer, linux-kernel, robh+dt, linux-imx,
kernel, festevam, linux-arm-kernel
In-Reply-To: <20200426133300.GE30501@dragon>
On 4/26/20 3:33 PM, Shawn Guo wrote:
> On Wed, Apr 08, 2020 at 08:43:51PM +0200, Parthiban Nallathambi wrote:
>> Add support for the MYiR imx6ULL based single board computer
>> equipped with on board 256MB NAND & RAM. The board also
>> provides expansion header for expansion board, but this
>> commit adds only support for SBC.
>>
>> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/imx6ull-myir-mys-6ulx-nand.dts | 19 ++
>> arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi | 247 +++++++++++++++++++++++
>> 3 files changed, 267 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6ull-myir-mys-6ulx-nand.dts
>> create mode 100644 arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index e8dd99201397..eab86051d782 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -612,6 +612,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>> imx6ull-14x14-evk.dtb \
>> imx6ull-colibri-eval-v3.dtb \
>> imx6ull-colibri-wifi-eval-v3.dtb \
>> + imx6ull-myir-mys-6ulx-nand.dtb \
>> imx6ull-opos6uldev.dtb \
>> imx6ull-phytec-segin-ff-rdk-nand.dtb \
>> imx6ull-phytec-segin-ff-rdk-emmc.dtb \
>> diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-nand.dts b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-nand.dts
>> new file mode 100644
>> index 000000000000..6eaba8a8d7a9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-nand.dts
>> @@ -0,0 +1,19 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Linumiz
>> + * Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include "imx6ull.dtsi"
>> +#include "imx6ull-myir-mys-6ulx.dtsi"
>> +
>> +/ {
>> + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
>> + compatible = "myir,imx6ul-mys-6ulx-nand", "myir,imx6ul-mys-6ulx",
>> + "fsl,imx6ull";
>
> Any new compatible needs to be documented.
Sure, thanks.
>
>> +};
>> +
>> +&gpmi {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> new file mode 100644
>> index 000000000000..f0a514187c21
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> @@ -0,0 +1,247 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Linumiz
>> + * Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/pwm/pwm.h>
>> +
>> +/ {
>> + model = "MYiR MYS-6ULX Single Board Computer";
>> + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull";
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + regulators: regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>
> Drop the container node and put fixed regulator nodes directly under
> root. Suggest to use name schema below:
>
> regulator-xxx {
> ...
> };
Fixed in v2. thanks
>
> Shawn
>
>> +
>> + vdd_5v: regulator@0 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_5V";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_3v3: regulator@1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + vin-supply = <&vdd_5v>;
>> + };
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet1>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy0>;
>> + phy-supply = <&vdd_3v3>;
>> + status = "okay";
>> +
>> + mdio: mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + reg = <0>;
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + interrupt-parent = <&gpio5>;
>> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
>> + clock-names = "rmii-ref";
>> + status = "okay";
>> + };
>> + };
>> +};
>> +
>> +&gpmi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpmi_nand>;
>> + nand-on-flash-bbt;
>> + status = "disabled";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + wakeup-source;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "disabled";
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_enet1: enet1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>> + >;
>> + };
>> +
>> + pinctrl_gpmi_nand: gpminandgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
>> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
>> + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
>> + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>> + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
>> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
>> + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
>> + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
>> + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
>> + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
>> + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
>> + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
>> + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
>> + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
>> + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> + >;
>> + };
>> +};
>> --
>> 2.11.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Thanks,
Parthiban N
+4915163761545
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^ permalink raw reply
* Re: [PATCH 1/5] arm: decompressor: set malloc pool size for the decompressor
From: Russell King - ARM Linux admin @ 2020-06-01 14:46 UTC (permalink / raw)
To: Łukasz Stelmach
Cc: Kees Cook, Bartlomiej Zolnierkiewicz, Masahiro Yamada,
Nick Desaulniers, linux-kernel, AKASHI Takahiro, Ben Dooks,
Thomas Gleixner, Enrico Weigelt, Ingo Molnar, linux-arm-kernel,
Marek Szyprowski
In-Reply-To: <20200601142754.26139-2-l.stelmach@samsung.com>
On Mon, Jun 01, 2020 at 04:27:50PM +0200, Łukasz Stelmach wrote:
> Move the definition of malloc pool size of the decompressor to
> a single place. This value will be exposed later for kexec_file loader.
>
> Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
> ---
> arch/arm/boot/compressed/Makefile | 2 ++
> arch/arm/boot/compressed/head.S | 6 ++++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index 9c11e7490292..b3594cd1588c 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -125,6 +125,8 @@ KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \
> sed -n -e 's/^\([^ ]*\) [AB] __bss_start$$/-0x\1/p' \
> -e 's/^\([^ ]*\) [AB] __bss_stop$$/+0x\1/p') )) )
> LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
> +# malloc pool size
> +LDFLAGS_vmlinux += --defsym _malloc_size=0x10000
> # Supply ZRELADDR to the decompressor via a linker symbol.
> ifneq ($(CONFIG_AUTO_ZRELADDR),y)
> LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index e8e1c866e413..dcc1afa60fb9 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -309,7 +309,8 @@ restart: adr r0, LC0
> #ifndef CONFIG_ZBOOT_ROM
> /* malloc space is above the relocated stack (64k max) */
> add sp, sp, r0
> - add r10, sp, #0x10000
> + ldr r10, =_malloc_size
> + add r10, r10, sp
This says "locate _malloc_size in a literal pool somewhere, and load it
using a PC-relative offset". Are you sure that the literal pool is
sensibly located?
Would it be better to use a definition for this?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC for 0.8m (est. 1762m) line in suburbia: sync at 13.1Mbps down 424kbps up
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^ permalink raw reply
* [RFC PATCH v4 2/2] arm64: tlb: Use the TLBI RANGE feature in arm64
From: Zhenyu Ye @ 2020-06-01 14:47 UTC (permalink / raw)
To: catalin.marinas, will, suzuki.poulose, maz, steven.price,
guohanjun, olof
Cc: linux-arch, yezhenyu2, linux-kernel, xiexiangyou, zhangshaokun,
linux-mm, arm, prime.zeng, kuhn.chenqun, linux-arm-kernel
In-Reply-To: <20200601144713.2222-1-yezhenyu2@huawei.com>
Add __TLBI_VADDR_RANGE macro and rewrite __flush_tlb_range().
In this patch, we only use the TLBI RANGE feature if the stride == PAGE_SIZE,
because when stride > PAGE_SIZE, usually only a small number of pages need
to be flushed and classic tlbi intructions are more effective.
We can also use 'end - start < threshold number' to decide which way
to go, however, different hardware may have different thresholds, so
I'm not sure if this is feasible.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 98 +++++++++++++++++++++++++++----
1 file changed, 86 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..818f27c82024 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -50,6 +50,16 @@
__tlbi(op, (arg) | USER_ASID_FLAG); \
} while (0)
+#define __tlbi_last_level(op1, op2, arg, last_level) do { \
+ if (last_level) { \
+ __tlbi(op1, arg); \
+ __tlbi_user(op1, arg); \
+ } else { \
+ __tlbi(op2, arg); \
+ __tlbi_user(op2, arg); \
+ } \
+} while (0)
+
/* This macro creates a properly formatted VA operand for the TLBI */
#define __TLBI_VADDR(addr, asid) \
({ \
@@ -59,6 +69,47 @@
__ta; \
})
+/*
+ * __TG defines translation granule of the system, which is decided by
+ * PAGE_SHIFT. Used by TTL.
+ * - 4KB : 1
+ * - 16KB : 2
+ * - 64KB : 3
+ */
+#define __TG ((PAGE_SHIFT - 12) / 2 + 1)
+
+/*
+ * This macro creates a properly formatted VA operand for the TLBI RANGE.
+ * The value bit assignments are:
+ *
+ * +----------+------+-------+-------+-------+----------------------+
+ * | ASID | TG | SCALE | NUM | TTL | BADDR |
+ * +-----------------+-------+-------+-------+----------------------+
+ * |63 48|47 46|45 44|43 39|38 37|36 0|
+ *
+ * The address range is determined by below formula:
+ * [BADDR, BADDR + (NUM + 1) * 2^(5*SCALE + 1) * PAGESIZE)
+ *
+ */
+#define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \
+ ({ \
+ unsigned long __ta = (addr) >> PAGE_SHIFT; \
+ __ta &= GENMASK_ULL(36, 0); \
+ __ta |= (unsigned long)(ttl) << 37; \
+ __ta |= (unsigned long)(num) << 39; \
+ __ta |= (unsigned long)(scale) << 44; \
+ __ta |= (unsigned long)(__TG) << 46; \
+ __ta |= (unsigned long)(asid) << 48; \
+ __ta; \
+ })
+
+/* This macro defines the range pages of the TLBI RANGE. */
+#define __TLBI_RANGE_SIZES(num, scale) ((num + 1) << (5 * scale + 1) << PAGE_SHIFT)
+
+#define TLB_RANGE_MASK_SHIFT 5
+#define TLB_RANGE_MASK GENMASK_ULL(TLB_RANGE_MASK_SHIFT - 1, 0)
+
+
/*
* TLB Invalidation
* ================
@@ -181,32 +232,55 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end,
unsigned long stride, bool last_level)
{
+ int num = 0;
+ int scale = 0;
unsigned long asid = ASID(vma->vm_mm);
unsigned long addr;
+ unsigned long range_pages;
start = round_down(start, stride);
end = round_up(end, stride);
+ range_pages = (end - start) >> PAGE_SHIFT;
if ((end - start) >= (MAX_TLBI_OPS * stride)) {
flush_tlb_mm(vma->vm_mm);
return;
}
- /* Convert the stride into units of 4k */
- stride >>= 12;
+ dsb(ishst);
- start = __TLBI_VADDR(start, asid);
- end = __TLBI_VADDR(end, asid);
+ /*
+ * The minimum size of TLB RANGE is 2 pages;
+ * Use normal TLB instruction to handle odd pages.
+ * If the stride != PAGE_SIZE, this will never happen.
+ */
+ if (range_pages % 2 == 1) {
+ addr = __TLBI_VADDR(start, asid);
+ __tlbi_last_level(vale1is, vae1is, addr, last_level);
+ start += 1 << PAGE_SHIFT;
+ range_pages >>= 1;
+ }
- dsb(ishst);
- for (addr = start; addr < end; addr += stride) {
- if (last_level) {
- __tlbi(vale1is, addr);
- __tlbi_user(vale1is, addr);
- } else {
- __tlbi(vae1is, addr);
- __tlbi_user(vae1is, addr);
+ while (range_pages > 0) {
+ if (cpus_have_const_cap(ARM64_HAS_TLBI_RANGE) &&
+ stride == PAGE_SIZE) {
+ num = (range_pages & TLB_RANGE_MASK) - 1;
+ if (num >= 0) {
+ addr = __TLBI_VADDR_RANGE(start, asid, scale,
+ num, 0);
+ __tlbi_last_level(rvale1is, rvae1is, addr,
+ last_level);
+ start += __TLBI_RANGE_SIZES(num, scale);
+ }
+ scale++;
+ range_pages >>= TLB_RANGE_MASK_SHIFT;
+ continue;
}
+
+ addr = __TLBI_VADDR(start, asid);
+ __tlbi_last_level(vale1is, vae1is, addr, last_level);
+ start += stride;
+ range_pages -= stride >> 12;
}
dsb(ish);
}
--
2.19.1
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^ permalink raw reply related
* [RFC PATCH v3 0/2] arm64: tlb: add support for TLBI RANGE instructions
From: Zhenyu Ye @ 2020-06-01 14:47 UTC (permalink / raw)
To: catalin.marinas, will, suzuki.poulose, maz, steven.price,
guohanjun, olof
Cc: linux-arch, yezhenyu2, linux-kernel, xiexiangyou, zhangshaokun,
linux-mm, arm, prime.zeng, kuhn.chenqun, linux-arm-kernel
ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
range of input addresses. This series add support for this feature.
--
ChangeList:
v4:
combine the __flush_tlb_range() and the __directly into the same function
with a single loop for both.
v3:
rebase this series on Linux 5.7-rc1.
v2:
Link: https://lkml.org/lkml/2019/11/11/348
Zhenyu Ye (2):
arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature
arm64: tlb: Use the TLBI RANGE feature in arm64
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/sysreg.h | 4 ++
arch/arm64/include/asm/tlbflush.h | 108 +++++++++++++++++++++++++++++-
arch/arm64/kernel/cpufeature.c | 11 +++
4 files changed, 124 insertions(+), 2 deletions(-)
--
2.19.1
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^ permalink raw reply
* [RFC PATCH v4 1/2] arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature
From: Zhenyu Ye @ 2020-06-01 14:47 UTC (permalink / raw)
To: catalin.marinas, will, suzuki.poulose, maz, steven.price,
guohanjun, olof
Cc: linux-arch, yezhenyu2, linux-kernel, xiexiangyou, zhangshaokun,
linux-mm, arm, prime.zeng, kuhn.chenqun, linux-arm-kernel
In-Reply-To: <20200601144713.2222-1-yezhenyu2@huawei.com>
ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
range of input addresses. This patch detect this feature.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 4 ++++
arch/arm64/kernel/cpufeature.c | 11 +++++++++++
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8eb5a088ae65..950095a72617 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -61,7 +61,8 @@
#define ARM64_HAS_AMU_EXTN 51
#define ARM64_HAS_ADDRESS_AUTH 52
#define ARM64_HAS_GENERIC_AUTH 53
+#define ARM64_HAS_TLBI_RANGE 54
-#define ARM64_NCAPS 54
+#define ARM64_NCAPS 55
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c4ac0ac25a00..4cc3efd633bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -594,6 +594,7 @@
/* id_aa64isar0 */
#define ID_AA64ISAR0_RNDR_SHIFT 60
+#define ID_AA64ISAR0_TLBI_RANGE_SHIFT 56
#define ID_AA64ISAR0_TS_SHIFT 52
#define ID_AA64ISAR0_FHM_SHIFT 48
#define ID_AA64ISAR0_DP_SHIFT 44
@@ -607,6 +608,9 @@
#define ID_AA64ISAR0_SHA1_SHIFT 8
#define ID_AA64ISAR0_AES_SHIFT 4
+#define ID_AA64ISAR0_TLBI_RANGE_NI 0x0
+#define ID_AA64ISAR0_TLBI_RANGE 0x2
+
/* id_aa64isar1 */
#define ID_AA64ISAR1_I8MM_SHIFT 52
#define ID_AA64ISAR1_DGH_SHIFT 48
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9fac745aa7bb..31bcfd0722b5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -124,6 +124,7 @@ static bool __system_matches_cap(unsigned int n);
*/
static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLBI_RANGE_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
@@ -1779,6 +1780,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.min_field_value = 1,
},
#endif
+ {
+ .desc = "TLB range maintenance instruction",
+ .capability = ARM64_HAS_TLBI_RANGE,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cpuid_feature,
+ .sys_reg = SYS_ID_AA64ISAR0_EL1,
+ .field_pos = ID_AA64ISAR0_TLBI_RANGE_SHIFT,
+ .sign = FTR_UNSIGNED,
+ .min_field_value = ID_AA64ISAR0_TLBI_RANGE,
+ },
{},
};
--
2.19.1
_______________________________________________
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^ permalink raw reply related
* Re: [PATCH v4 11/26] arm64: mte: Add PROT_MTE support to mmap() and mprotect()
From: Catalin Marinas @ 2020-06-01 14:45 UTC (permalink / raw)
To: Dave Martin
Cc: linux-arch, Vincenzo Frascino, Will Deacon, Szabolcs Nagy,
Andrey Konovalov, Kevin Brodsky, linux-mm, Linux ARM, nd,
Peter Collingbourne, Evgenii Stepanov
In-Reply-To: <20200601085536.GV5031@arm.com>
On Mon, Jun 01, 2020 at 09:55:38AM +0100, Dave P Martin wrote:
> On Thu, May 28, 2020 at 05:34:13PM +0100, Catalin Marinas wrote:
> > On Thu, May 28, 2020 at 12:05:09PM +0100, Szabolcs Nagy wrote:
> > > The 05/28/2020 10:14, Catalin Marinas wrote:
> > > > On Wed, May 27, 2020 at 11:57:39AM -0700, Peter Collingbourne wrote:
> > > > > Should the userspace stack always be mapped as if with PROT_MTE if the
> > > > > hardware supports it? Such a change would be invisible to non-MTE
> > > > > aware userspace since it would already need to opt in to tag checking
> > > > > via prctl. This would let userspace avoid a complex stack
> > > > > initialization sequence when running with stack tagging enabled on the
> > > > > main thread.
> > > >
> > > > I don't think the stack initialisation is that difficult. On program
> > > > startup (can be the dynamic loader). Something like (untested):
> > > >
> > > > register unsigned long stack asm ("sp");
> > > > unsigned long page_sz = sysconf(_SC_PAGESIZE);
> > > >
> > > > mprotect((void *)(stack & ~(page_sz - 1)), page_sz,
> > > > PROT_READ | PROT_WRITE | PROT_MTE | PROT_GROWSDOWN);
> > > >
> > > > (the essential part it PROT_GROWSDOWN so that you don't have to specify
> > > > a stack lower limit)
> > >
> > > does this work even if the currently mapped stack is more than page_sz?
> > > determining the mapped main stack area is i think non-trivial to do in
> > > userspace (requires parsing /proc/self/maps or similar).
> >
> > Because of PROT_GROWSDOWN, the kernel adjusts the start of the range
> > down automatically. It is potentially problematic if the top of the
> > stack is more than a page away and you want the whole stack coloured. I
> > haven't run a test but my reading of the kernel code is that the stack
> > vma would be split in this scenario, so the range beyond sp+page_sz
> > won't have PROT_MTE set.
> >
> > My assumption is that if you do this during program start, the stack is
> > smaller than a page. Alternatively, could we use argv or envp to
> > determine the top of the user stack (the bottom is taken care of by the
> > kernel)?
>
> I don't think you can easily know when the stack ends, but perhaps it
> doesn't matter.
>
> From memory, the initial stack looks like:
>
> argv/env strings
> AT_NULL
> auxv
> NULL
> env
> NULL
> argv
> argc <--- sp
>
> If we don't care about tagging the strings correctly, we could step to
> the end of auxv and tag down from there.
>
> If we do care about tagging the strings, there's probably no good way
> to find the end of the string area, other than looking up sp in
> /proc/self/maps. I'm not sure we should trust all past and future
> kernels to spit out the strings in a predictable order.
I don't think we care about tagging whatever the kernel places on the
stack since the argv/envp pointers are untagged. An mprotect(PROT_MTE)
may or may not cover the environment but it shouldn't matter as the
kernel clears the tags on the corresponding pages anyway.
AFAIK stack tagging works by colouring a stack frame on function entry
and clearing the tags on return. We would only hit a problem if the
function issuing mprotect(sp, PROT_MTE) on and its callers already
assumed a PROT_MTE stack. Without PROT_MTE, an STG would be
write-ignore, so subsequently turning it on would lead to a mismatch
between the pointer and the allocation tags.
So PROT_MTE turning on should happen very early in the user process
startup code before any code with stack tagging enabled. Whether you
reach the top of the stack with such mprotect() doesn't really matter
since up to that point there should not be any use of stack tagging. If
that's not possible, for example the glibc code setting up the stack was
compiled to stack tagging itself, the kernel would have to enable it
when the user process starts. However, I'd only do this based on some
ELF note.
--
Catalin
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^ permalink raw reply
* [PATCH 5/5] arm: kexec_file: load zImage or uImage, initrd and dtb
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20200601142754.26139-1-l.stelmach@samsung.com>
This is kexec_file_load implementation for ARM. It loads zImage and
initrd from file descripters and resuses DTB.
Most code is derived from arm64 kexec_file_load implementation
and from kexec-tools.
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
arch/arm/Kconfig | 15 ++
arch/arm/include/asm/image.h | 26 ++++
arch/arm/include/asm/kexec.h | 14 ++
arch/arm/kernel/Makefile | 5 +-
arch/arm/kernel/kexec_uimage.c | 80 ++++++++++
arch/arm/kernel/kexec_zimage.c | 199 +++++++++++++++++++++++++
arch/arm/kernel/machine_kexec.c | 11 +-
arch/arm/kernel/machine_kexec_file.c | 209 +++++++++++++++++++++++++++
8 files changed, 554 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/kernel/kexec_uimage.c
create mode 100644 arch/arm/kernel/kexec_zimage.c
create mode 100644 arch/arm/kernel/machine_kexec_file.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c77c93c485a0..6adb849cb304 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1917,6 +1917,21 @@ config KEXEC
is properly shutdown, so do not be surprised if this code does not
initially work for you.
+config KEXEC_FILE
+ bool "Kexec file based system call (EXPERIMENTAL)"
+ depends on (!SMP || PM_SLEEP_SMP)
+ depends on USE_OF
+ select KEXEC_CORE
+ select CRC32
+ help
+ This is new version of kexec system call. This system call is
+ file based and takes file descriptors as system call argument
+ for kernel and initramfs as opposed to list of segments as
+ accepted by previous system call.
+
+ The kernel to be loaded MUST support Flattened Device Tree
+ (selected with CONFIG_USE_OF).
+
config ATAGS_PROC
bool "Export atags in procfs"
depends on ATAGS && KEXEC
diff --git a/arch/arm/include/asm/image.h b/arch/arm/include/asm/image.h
index 624438740f23..95f23837b04f 100644
--- a/arch/arm/include/asm/image.h
+++ b/arch/arm/include/asm/image.h
@@ -8,8 +8,13 @@
(((x) >> 8) & 0x0000ff00) | \
(((x) << 8) & 0x00ff0000) | \
(((x) << 24) & 0xff000000))
+#define UIMAGE_MAGIC(x) (x)
#else
#define ZIMAGE_MAGIC(x) (x)
+#define UIMAGE_MAGIC(x) ((((x) >> 24) & 0x000000ff) | \
+ (((x) >> 8) & 0x0000ff00) | \
+ (((x) << 8) & 0x00ff0000) | \
+ (((x) << 24) & 0xff000000))
#endif
#define ARM_ZIMAGE_MAGIC1 ZIMAGE_MAGIC(0x016f2818)
@@ -17,6 +22,12 @@
#define ARM_ZIMAGE_MAGIC3 ZIMAGE_MAGIC(0x5a534c4b)
#define ARM_ZIMAGE_MAGIC4 ZIMAGE_MAGIC(0x5a534344)
+#define ARM_UIMAGE_MAGIC UIMAGE_MAGIC(0x27051956)
+#define ARM_UIMAGE_NAME_LEN 32
+#define ARM_UIMAGE_TYPE_KERNEL 2
+#define ARM_UIMAGE_TYPE_KERNEL_NOLOAD 14
+#define ARM_UIMAGE_ARCH_ARM 2
+
#ifndef __ASSEMBLY__
#include <linux/types.h>
@@ -33,6 +44,21 @@ struct arm_zimage_header {
__le32 extension_tag_offset;
};
+struct arm_uimage_header {
+ __be32 magic;
+ __be32 hdr_crc;
+ __be32 time;
+ __be32 size;
+ __be32 load;
+ __be32 entry;
+ __be32 crc;
+ __u8 os;
+ __u8 arch;
+ __u8 type;
+ __u8 comp;
+ __u8 name[ARM_UIMAGE_NAME_LEN];
+};
+
struct arm_zimage_tag {
struct tag_header hdr;
union {
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index 22751b5b5735..fda35afa7195 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -83,6 +83,20 @@ static inline struct page *boot_pfn_to_page(unsigned long boot_pfn)
}
#define boot_pfn_to_page boot_pfn_to_page
+#ifdef CONFIG_KEXEC_FILE
+
+extern const struct kexec_file_ops kexec_zimage_ops;
+extern const struct kexec_file_ops kexec_uimage_ops;
+
+struct kimage;
+
+extern int load_other_segments(struct kimage *image,
+ unsigned long kernel_load_addr, unsigned long kernel_size,
+ char *initrd, unsigned long initrd_len,
+ unsigned long initrd_offset, char *cmdline);
+
+#endif /* CONFIG_KEXEC_FILE */
+
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_KEXEC */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 89e5d864e923..466c683bb551 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -3,6 +3,7 @@
# Makefile for the linux kernel.
#
+CFLAGS_kexec_zimage.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
@@ -56,7 +57,9 @@ obj-$(CONFIG_FUNCTION_TRACER) += entry-ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o patch.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o patch.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o
-obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
+obj-$(CONFIG_KEXEC_CORE) += machine_kexec.o relocate_kernel.o
+obj-$(CONFIG_KEXEC_FILE) += machine_kexec_file.o kexec_zimage.o \
+ kexec_uimage.o
# Main staffs in KPROBES are in arch/arm/probes/ .
obj-$(CONFIG_KPROBES) += patch.o insn.o
obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
diff --git a/arch/arm/kernel/kexec_uimage.c b/arch/arm/kernel/kexec_uimage.c
new file mode 100644
index 000000000000..47033574e24e
--- /dev/null
+++ b/arch/arm/kernel/kexec_uimage.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Kexec uImage loader
+ *
+ * Copyright (C) 2020 Samsung Electronics
+ * Author: Łukasz Stelmach <l.stelmach@samsung.com>
+ */
+
+#define pr_fmt(fmt) "kexec_file(uImage): " fmt
+
+#include <asm/image.h>
+#include <linux/crc32.h>
+#include <linux/err.h>
+#include <linux/kexec.h>
+
+#define crc32_ones(crc, buf, len) \
+ (crc32(crc ^ 0xffffffff, buf, len) ^ 0xffffffff)
+
+static int uimage_probe(const char *uimage_buf, unsigned long uimage_len)
+{
+ const struct arm_uimage_header *h =
+ (struct arm_uimage_header *) uimage_buf;
+ struct arm_uimage_header uhdr;
+ unsigned long zoff = sizeof(struct arm_uimage_header);
+ uint32_t crc;
+
+ if (h->magic != ARM_UIMAGE_MAGIC)
+ return -EINVAL;
+
+ if (h->type != ARM_UIMAGE_TYPE_KERNEL &&
+ h->type != ARM_UIMAGE_TYPE_KERNEL_NOLOAD){
+ pr_debug("Invalid image type: %d\n", h->type);
+ return -EINVAL;
+ }
+
+ if (h->arch != ARM_UIMAGE_ARCH_ARM) {
+ pr_debug("Invalidy image arch: %d\n", h->arch);
+ return -EINVAL;
+ }
+
+ memcpy((char *)&uhdr, h, sizeof(uhdr));
+ crc = be32_to_cpu(uhdr.hdr_crc);
+ uhdr.hdr_crc = 0;
+
+ if (crc32_ones(0, (char *)&uhdr, sizeof(uhdr)) != crc) {
+ pr_debug("Corrupt header, CRC do not match\n");
+ return -EINVAL;
+ }
+
+ crc = be32_to_cpu(uhdr.crc);
+ if (crc32_ones(0, uimage_buf + zoff, uimage_len - zoff) != crc) {
+ pr_debug("Corrupt zImage, CRC do not match\n");
+ return -EINVAL;
+ }
+
+ return kexec_zimage_ops.probe(uimage_buf + zoff,
+ uimage_len - zoff);
+}
+
+static void *uimage_load(struct kimage *image,
+ char *uimage, unsigned long uimage_len,
+ char *initrd, unsigned long initrd_len,
+ char *cmdline, unsigned long cmdline_len)
+{
+ const struct arm_uimage_header *h =
+ (struct arm_uimage_header *) uimage;
+ unsigned long zimage_offset = sizeof(struct arm_uimage_header);
+
+ pr_debug("Loading uImage");
+ return kexec_zimage_ops.load(image,
+ uimage + zimage_offset,
+ uimage_len - zimage_offset,
+ initrd, initrd_len,
+ cmdline, cmdline_len);
+}
+
+const struct kexec_file_ops kexec_uimage_ops = {
+ .probe = uimage_probe,
+ .load = uimage_load,
+};
diff --git a/arch/arm/kernel/kexec_zimage.c b/arch/arm/kernel/kexec_zimage.c
new file mode 100644
index 000000000000..d09795fc9072
--- /dev/null
+++ b/arch/arm/kernel/kexec_zimage.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Kexec zImage loader
+ *
+ * Copyright (C) 2020 Samsung Electronics
+ * Author: Łukasz Stelmach <l.stelmach@samsung.com>
+ */
+
+#define pr_fmt(fmt) "kexec_file(zImage): " fmt
+
+#include <asm/image.h>
+#include <asm/unaligned.h>
+#include <linux/err.h>
+#include <linux/kexec.h>
+#include <linux/memblock.h>
+
+#define byte_size(t) ((t)->hdr.size << 2)
+
+static const void *find_extension_tag(const char *buf,
+ unsigned long len,
+ uint32_t tag_id)
+{
+ const struct arm_zimage_header *h = (const struct arm_zimage_header *)buf;
+ const struct arm_zimage_tag *tag;
+ uint32_t offset, size;
+ uint32_t max = len - sizeof(struct tag_header);
+
+ if (len < sizeof(*h) ||
+ h->magic != ARM_ZIMAGE_MAGIC1 ||
+ h->magic2 != ARM_ZIMAGE_MAGIC2)
+ return NULL;
+
+ for (offset = h->extension_tag_offset;
+ (tag = (void *)(buf + offset)) != NULL &&
+ offset < max &&
+ (size = le32_to_cpu(byte_size(tag))) != 0 &&
+ offset + size < len;
+ offset += size) {
+ pr_debug(" offset 0x%08x tag 0x%08x size %u\n",
+ offset, le32_to_cpu(tag->hdr.tag), size);
+ if (tag->hdr.tag == tag_id)
+ return tag;
+ }
+
+ return NULL;
+}
+
+static int zimage_probe(const char *kernel_buf, unsigned long kernel_len)
+{
+ const struct arm_zimage_header *h =
+ (struct arm_zimage_header *)(kernel_buf);
+
+ if (!h || (kernel_len < sizeof(*h)))
+ return -EINVAL;
+
+ if ((h->magic != ARM_ZIMAGE_MAGIC1) ||
+ (h->magic2 != ARM_ZIMAGE_MAGIC2))
+ return -EINVAL;
+
+ return 0;
+}
+
+
+#if defined(DEBUG)
+#define debug_offsets() ({ \
+ pr_debug("Image offsets:\n"); \
+ pr_debug(" kernel 0x%08lx 0x%08lx\n", kernel_offset, kernel_len); \
+ pr_debug(" zimage 0x%08lx 0x%08lx\n", zimage_offset, zimage_len); \
+ pr_debug(" initrd 0x%08lx 0x%08lx\n", initrd_offset, initrd_len); \
+})
+#else
+#define debug_offsets()
+#endif
+
+static void *zimage_load(struct kimage *image,
+ char *zimage, unsigned long zimage_len,
+ char *initrd, unsigned long initrd_len,
+ char *cmdline, unsigned long cmdline_len)
+{
+ struct arm_zimage_header *h;
+ struct kexec_buf kbuf;
+ struct kexec_segment *zimage_segment;
+ const struct arm_zimage_tag *klsz_tag;
+ const struct arm_zimage_tag_dc *dcsz_tag;
+ int ret = -EINVAL;
+
+ unsigned long zimage_mem = 0x20000; /* malloc 64kB + stack 4 kB + some bss */
+ unsigned long kernel_len = zimage_len * 4; /* 4:1 compression */
+ unsigned long kernel_offset = memblock_start_of_DRAM() +
+ ALIGN(TEXT_OFFSET, PAGE_SIZE);
+ unsigned long zimage_offset = kernel_offset +
+ ALIGN(kernel_len, PAGE_SIZE);
+ unsigned long initrd_offset = zimage_offset +
+ ALIGN(zimage_len + zimage_mem, PAGE_SIZE);
+
+ if (image->type == KEXEC_TYPE_CRASH) {
+ kernel_offset += crashk_res.start;
+ zimage_offset += crashk_res.start;
+ initrd_offset += crashk_res.start;
+ }
+ debug_offsets();
+
+ h = (struct arm_zimage_header *)zimage;
+
+ klsz_tag = find_extension_tag(zimage, zimage_len, ZIMAGE_TAG_KRNL_SIZE);
+ if (klsz_tag) {
+ uint32_t *p = (void *)zimage +
+ le32_to_cpu(klsz_tag->u.krnl_size.size_ptr);
+ uint32_t edata_size = le32_to_cpu(get_unaligned(p));
+ uint32_t bss_size = le32_to_cpu(klsz_tag->u.krnl_size.bss_size);
+
+ kernel_len = edata_size + bss_size;
+
+ pr_debug("Decompressed kernel sizes:\n");
+ pr_debug(" text+data 0x%08lx bss 0x%08lx total 0x%08lx\n",
+ (unsigned long)edata_size,
+ (unsigned long)bss_size,
+ (unsigned long)kernel_len);
+
+ zimage_offset = kernel_offset + ALIGN(edata_size, PAGE_SIZE);
+ initrd_offset = zimage_offset +
+ max(ALIGN(zimage_len + 0x20000, PAGE_SIZE),
+ ALIGN((unsigned long)bss_size, PAGE_SIZE));
+ debug_offsets();
+ }
+
+ dcsz_tag = find_extension_tag(zimage, zimage_len,
+ ZIMAGE_TAG_DECOMP_SIZE);
+ if (dcsz_tag) {
+ uint32_t bss_size = le32_to_cpu(dcsz_tag->u.decomp_size.bss_size);
+ uint32_t stack_size = le32_to_cpu(dcsz_tag->u.decomp_size.stack_size);
+ uint32_t malloc_size = le32_to_cpu(dcsz_tag->u.decomp_size.malloc_size);
+
+ zimage_mem = bss_size + stack_size + malloc_size;
+
+ pr_debug("Decompressor memory requirements:\n");
+ pr_debug(" bss 0x%08lx stack 0x%08lx malloc 0x%08lx total 0x%08lx\n",
+ (unsigned long)bss_size,
+ (unsigned long)stack_size,
+ (unsigned long)malloc_size,
+ zimage_mem);
+
+ initrd_offset = max(ALIGN(zimage_offset + zimage_len +
+ bss_size + stack_size +
+ malloc_size, PAGE_SIZE),
+ ALIGN(kernel_offset + kernel_len, PAGE_SIZE));
+ debug_offsets();
+ }
+
+ /*
+ * zImage MUST be loaded into the first 128 MiB of physical
+ * memory for proper memory detection. Should the uncompressed
+ * kernel be larger than 128 MiB, zImage relocation becomes
+ * unavoidable and it is best to rely on the relocation code.
+ */
+ if (((zimage_offset - kernel_offset) + PAGE_SIZE + 0x8000) >= SZ_128M) {
+ pr_debug("The kernel is too big (%ld MiB) to avoid "
+ "zImage relocation. Loading zimage at 0x%08lx\n",
+ ((zimage_offset - kernel_offset) >> 20),
+ kernel_offset);
+ zimage_offset = kernel_offset;
+ }
+
+ kbuf.image = image;
+ kbuf.top_down = false;
+
+ kbuf.buf_min = zimage_offset;
+ kbuf.buf_max = ULONG_MAX;
+ kbuf.buffer = zimage;
+ kbuf.bufsz = zimage_len;
+ kbuf.buf_align = PAGE_SIZE;
+
+ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN;
+ kbuf.memsz = zimage_len;
+
+ ret = kexec_add_buffer(&kbuf);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pr_debug("Loaded zImage at 0x%lx bufsz=0x%lx memsz=0x%lx\n",
+ kbuf.mem, kbuf.bufsz, kbuf.memsz);
+
+ initrd_offset += kbuf.mem - zimage_offset;
+ debug_offsets();
+
+ zimage_segment = &image->segment[image->nr_segments - 1];
+ image->start = zimage_segment->mem;
+
+ ret = load_other_segments(image,
+ zimage_segment->mem, zimage_segment->memsz,
+ initrd, initrd_len, initrd_offset,
+ cmdline);
+ return ERR_PTR(ret);
+}
+
+const struct kexec_file_ops kexec_zimage_ops = {
+ .probe = zimage_probe,
+ .load = zimage_load,
+};
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index c10a2dfd53d1..2e4780efabb4 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -93,10 +93,13 @@ int machine_kexec_prepare(struct kimage *image)
current_segment->memsz))
return -EINVAL;
- err = get_user(header, (__be32*)current_segment->buf);
- if (err)
- return err;
-
+ if (image->file_mode) {
+ header = *(__be32 *)current_segment->buf;
+ } else {
+ err = get_user(header, (__be32 *)current_segment->buf);
+ if (err)
+ return err;
+ }
if (header == cpu_to_be32(OF_DT_HEADER))
image->arch.kernel_r2 = current_segment->mem;
}
diff --git a/arch/arm/kernel/machine_kexec_file.c b/arch/arm/kernel/machine_kexec_file.c
new file mode 100644
index 000000000000..ead680f1e795
--- /dev/null
+++ b/arch/arm/kernel/machine_kexec_file.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * kexec_file for arm
+ *
+ * Copyright (C) 2018 Linaro Limited
+ * Copyright (C) 2020 Samsung Electronics
+ * Authors:
+ * AKASHI Takahiro <takahiro.akashi@linaro.org>
+ * Łukasz Stelmach <l.stelmach@samsung.com>
+ *
+ */
+
+#define pr_fmt(fmt) "kexec_file: " fmt
+
+#include <linux/kexec.h>
+#include <linux/libfdt.h>
+#include <linux/of_fdt.h>
+#include <linux/random.h>
+
+/* relevant device tree properties */
+#define FDT_PROP_INITRD_START "linux,initrd-start"
+#define FDT_PROP_INITRD_END "linux,initrd-end"
+#define FDT_PROP_BOOTARGS "bootargs"
+#define FDT_PROP_RNG_SEED "rng-seed"
+
+static int setup_dtb(struct kimage *image,
+ unsigned long initrd_load_addr, unsigned long initrd_len,
+ char *cmdline, void *dtb)
+{
+ int off, ret;
+
+ ret = fdt_path_offset(dtb, "/chosen");
+ if (ret < 0)
+ goto out;
+
+ off = ret;
+
+ /* add bootargs */
+ if (cmdline) {
+ ret = fdt_setprop_string(dtb, off, FDT_PROP_BOOTARGS, cmdline);
+ if (ret)
+ goto out;
+ } else {
+ ret = fdt_delprop(dtb, off, FDT_PROP_BOOTARGS);
+ if (ret && (ret != -FDT_ERR_NOTFOUND))
+ goto out;
+ }
+
+ /* add initrd-* */
+ if (initrd_load_addr) {
+ ret = fdt_setprop_u64(dtb, off, FDT_PROP_INITRD_START,
+ initrd_load_addr);
+ if (ret)
+ goto out;
+
+ ret = fdt_setprop_u64(dtb, off, FDT_PROP_INITRD_END,
+ initrd_load_addr + initrd_len);
+ if (ret)
+ goto out;
+ } else {
+ ret = fdt_delprop(dtb, off, FDT_PROP_INITRD_START);
+ if (ret && (ret != -FDT_ERR_NOTFOUND))
+ goto out;
+
+ ret = fdt_delprop(dtb, off, FDT_PROP_INITRD_END);
+ if (ret && (ret != -FDT_ERR_NOTFOUND))
+ goto out;
+ }
+
+ /* add rng-seed */
+ if (rng_is_initialized()) {
+ char seed[128];
+ get_random_bytes(seed, sizeof(seed));
+
+ ret = fdt_setprop(dtb, off, FDT_PROP_RNG_SEED,
+ seed, sizeof(seed));
+ if (ret)
+ goto out;
+ } else {
+ pr_notice("RNG is not initialised: omitting \"%s\" property\n",
+ FDT_PROP_RNG_SEED);
+ ret = 0;
+ }
+
+out:
+ if (ret)
+ return (ret == -FDT_ERR_NOSPACE) ? -ENOMEM : -EINVAL;
+
+ return 0;
+}
+/*
+ * More space needed so that we can add initrd, bootargs and kaslr-seed.
+ */
+#define DTB_EXTRA_SPACE 0x1000
+
+static int create_dtb(struct kimage *image,
+ unsigned long initrd_load_addr, unsigned long initrd_len,
+ char *cmdline, void **dtb)
+{
+ void *buf;
+ size_t buf_size;
+ size_t cmdline_len;
+ int ret;
+
+ cmdline_len = cmdline ? strlen(cmdline) : 0;
+ buf_size = fdt_totalsize(initial_boot_params)
+ + cmdline_len + DTB_EXTRA_SPACE;
+
+ for (;;) {
+ buf = vmalloc(buf_size);
+ if (!buf)
+ return -ENOMEM;
+
+ /* duplicate a device tree blob */
+ ret = fdt_open_into(initial_boot_params, buf, buf_size);
+ if (ret)
+ return -EINVAL;
+
+ ret = setup_dtb(image, initrd_load_addr, initrd_len,
+ cmdline, buf);
+ if (ret) {
+ vfree(buf);
+ if (ret == -ENOMEM) {
+ /* unlikely, but just in case */
+ buf_size += DTB_EXTRA_SPACE;
+ continue;
+ } else {
+ return ret;
+ }
+ }
+
+ /* trim it */
+ fdt_pack(buf);
+ *dtb = buf;
+
+ return 0;
+ }
+}
+
+int load_other_segments(struct kimage *image,
+ unsigned long zimage_load_addr,
+ unsigned long zimage_len,
+ char *initrd,
+ unsigned long initrd_len,
+ unsigned long initrd_offset,
+ char *cmdline)
+{
+ struct kexec_buf kbuf;
+ void *dtb = NULL;
+ unsigned long initrd_load_addr = 0;
+ unsigned long dtb_len;
+ int ret = 0;
+
+ kbuf.image = image;
+ /* not allocate anything below the kernel */
+ kbuf.buf_min = initrd_offset;
+ if (initrd) {
+ kbuf.buffer = initrd;
+ kbuf.bufsz = initrd_len;
+ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN;
+ kbuf.memsz = initrd_len;
+ kbuf.buf_align = PAGE_SIZE;
+ kbuf.buf_max = ULONG_MAX;
+ kbuf.top_down = false;
+
+ ret = kexec_add_buffer(&kbuf);
+ if (ret)
+ goto out_err;
+
+ pr_debug("Loaded initrd at 0x%lx bufsz=0x%lx memsz=0x%lx\n",
+ kbuf.mem, kbuf.bufsz, kbuf.memsz);
+
+ initrd_load_addr = kbuf.mem;
+ kbuf.buf_min = initrd_load_addr + kbuf.memsz;
+ }
+
+ /* load dtb */
+ ret = create_dtb(image, initrd_load_addr, initrd_len, cmdline, &dtb);
+ if (ret) {
+ pr_err("Preparing for new dtb failed\n");
+ goto out_err;
+ }
+
+ dtb_len = fdt_totalsize(dtb);
+ kbuf.buffer = dtb;
+ kbuf.bufsz = dtb_len;
+ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN;
+ kbuf.memsz = dtb_len;
+ kbuf.buf_align = PAGE_SIZE;
+ kbuf.buf_max = ULONG_MAX;
+ kbuf.top_down = false;
+
+ ret = kexec_add_buffer(&kbuf);
+ if (ret)
+ goto out_err;
+
+ pr_debug("Loaded dtb at 0x%lx bufsz=0x%lx memsz=0x%lx\n",
+ kbuf.mem, kbuf.bufsz, kbuf.memsz);
+ return 0;
+out_err:
+ vfree(dtb);
+ return ret;
+}
+
+const struct kexec_file_ops * const kexec_file_loaders[] = {
+ &kexec_uimage_ops,
+ &kexec_zimage_ops,
+ NULL
+};
--
2.26.2
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^ permalink raw reply related
* [PATCH 4/5] arm: Add kexec_image_info
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20200601142754.26139-1-l.stelmach@samsung.com>
Add kexec_image_info to print detailed information about a kexec image.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
arch/arm/kernel/machine_kexec.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 76300f3813e8..c10a2dfd53d1 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -31,6 +31,32 @@ extern unsigned long kexec_boot_atags;
static atomic_t waiting_for_crash_ipi;
+/**
+ * kexec_image_info - For debugging output.
+ */
+#define kexec_image_info(_i) _kexec_image_info(__func__, __LINE__, _i)
+static void _kexec_image_info(const char *func, int line,
+ const struct kimage *kimage)
+{
+ unsigned long i;
+
+ pr_debug("%s:%d:\n", func, line);
+ pr_debug(" kexec kimage info:\n");
+ pr_debug(" type: %d\n", kimage->type);
+ pr_debug(" start: %lx\n", kimage->start);
+ pr_debug(" head: %lx\n", kimage->head);
+ pr_debug(" nr_segments: %lu\n", kimage->nr_segments);
+
+ for (i = 0; i < kimage->nr_segments; i++) {
+ pr_debug(" segment[%lu]: %08lx - %08lx, 0x%x bytes, %lu pages\n",
+ i,
+ kimage->segment[i].mem,
+ kimage->segment[i].mem + kimage->segment[i].memsz,
+ kimage->segment[i].memsz,
+ kimage->segment[i].memsz / PAGE_SIZE);
+ }
+}
+
/*
* Provide a dummy crash_notes definition while crash dump arrives to arm.
* This prevents breakage of crash_notes attribute in kernel/ksysfs.c.
@@ -42,6 +68,8 @@ int machine_kexec_prepare(struct kimage *image)
__be32 header;
int i, err;
+ kexec_image_info(image);
+
image->arch.kernel_r2 = image->start - KEXEC_ARM_ZIMAGE_OFFSET
+ KEXEC_ARM_ATAGS_OFFSET;
--
2.26.2
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^ permalink raw reply related
* [PATCH 2/5] arm: add image header definitions
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20200601142754.26139-1-l.stelmach@samsung.com>
This structure will be used later by kexec_file loader.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
arch/arm/boot/compressed/head.S | 3 +-
arch/arm/boot/compressed/vmlinux.lds.S | 13 ++-----
arch/arm/include/asm/image.h | 48 ++++++++++++++++++++++++++
3 files changed, 53 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/include/asm/image.h
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index dcc1afa60fb9..97e4cfcfc197 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -7,6 +7,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <asm/image.h>
#include <asm/v7m.h>
#include "efi-header.S"
@@ -211,7 +212,7 @@ start:
.word _magic_start @ absolute load/run zImage address
.word _magic_end @ zImage end address
.word 0x04030201 @ endianness flag
- .word 0x45454545 @ another magic number to indicate
+ .word ARM_ZIMAGE_MAGIC2 @ another magic number to indicate
.word _magic_table @ additional data table
__EFI_HEADER
diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
index f82b5962d97e..308e9cd6a897 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -3,14 +3,7 @@
* Copyright (C) 2000 Russell King
*/
-#ifdef CONFIG_CPU_ENDIAN_BE8
-#define ZIMAGE_MAGIC(x) ( (((x) >> 24) & 0x000000ff) | \
- (((x) >> 8) & 0x0000ff00) | \
- (((x) << 8) & 0x00ff0000) | \
- (((x) << 24) & 0xff000000) )
-#else
-#define ZIMAGE_MAGIC(x) (x)
-#endif
+#include <asm/image.h>
OUTPUT_ARCH(arm)
ENTRY(_start)
@@ -43,7 +36,7 @@ SECTIONS
.table : ALIGN(4) {
_table_start = .;
LONG(ZIMAGE_MAGIC(4))
- LONG(ZIMAGE_MAGIC(0x5a534c4b))
+ LONG(ARM_ZIMAGE_MAGIC3)
LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start))
LONG(ZIMAGE_MAGIC(_kernel_bss_size))
LONG(0)
@@ -107,7 +100,7 @@ SECTIONS
_edata_real = .;
}
- _magic_sig = ZIMAGE_MAGIC(0x016f2818);
+ _magic_sig = ARM_ZIMAGE_MAGIC1;
_magic_start = ZIMAGE_MAGIC(_start);
_magic_end = ZIMAGE_MAGIC(_edata);
_magic_table = ZIMAGE_MAGIC(_table_start - _start);
diff --git a/arch/arm/include/asm/image.h b/arch/arm/include/asm/image.h
new file mode 100644
index 000000000000..d5c18a0f6a34
--- /dev/null
+++ b/arch/arm/include/asm/image.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_IMAGE_H
+#define __ASM_IMAGE_H
+
+#ifdef CONFIG_CPU_ENDIAN_BE8
+#define ZIMAGE_MAGIC(x) ((((x) >> 24) & 0x000000ff) | \
+ (((x) >> 8) & 0x0000ff00) | \
+ (((x) << 8) & 0x00ff0000) | \
+ (((x) << 24) & 0xff000000))
+#else
+#define ZIMAGE_MAGIC(x) (x)
+#endif
+
+#define ARM_ZIMAGE_MAGIC1 ZIMAGE_MAGIC(0x016f2818)
+#define ARM_ZIMAGE_MAGIC2 (0x45454545)
+#define ARM_ZIMAGE_MAGIC3 ZIMAGE_MAGIC(0x5a534c4b)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/setup.h>
+
+/* ARM zImage header format */
+struct arm_zimage_header {
+ __le32 code[9];
+ __le32 magic;
+ __le32 start;
+ __le32 end;
+ __le32 endian;
+ __le32 magic2;
+ __le32 extension_tag_offset;
+};
+
+struct arm_zimage_tag {
+ struct tag_header hdr;
+ union {
+#define ZIMAGE_TAG_KRNL_SIZE ARM_ZIMAGE_MAGIC3
+ struct zimage_krnl_size {
+ __le32 size_ptr;
+ __le32 bss_size;
+ } krnl_size;
+ } u;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_IMAGE_H */
--
2.26.2
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^ permalink raw reply related
* [PATCH 3/5] arm: decompressor: define a new zImage tag
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20200601142754.26139-1-l.stelmach@samsung.com>
Add DCSZ tag which holds dynamic memory (stack, bss, malloc pool)
requirements of the decompressor code.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
arch/arm/include/asm/image.h | 13 +++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
index 308e9cd6a897..dcfdb3209c90 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -39,6 +39,11 @@ SECTIONS
LONG(ARM_ZIMAGE_MAGIC3)
LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start))
LONG(ZIMAGE_MAGIC(_kernel_bss_size))
+ LONG(ZIMAGE_MAGIC(5))
+ LONG(ARM_ZIMAGE_MAGIC4)
+ LONG(ZIMAGE_MAGIC(_end - __bss_start))
+ LONG(ZIMAGE_MAGIC(_stack_end - _stack_start))
+ LONG(ZIMAGE_MAGIC(_malloc_size))
LONG(0)
_table_end = .;
}
@@ -108,10 +113,12 @@ SECTIONS
. = BSS_START;
__bss_start = .;
.bss : { *(.bss) }
+ . = ALIGN(8); /* the stack must be 64-bit aligned and adjoin bss */
_end = .;
- . = ALIGN(8); /* the stack must be 64-bit aligned */
+ _stack_start = .;
.stack : { *(.stack) }
+ _stack_end = .;
PROVIDE(__pecoff_data_size = ALIGN(512) - ADDR(.data));
PROVIDE(__pecoff_end = ALIGN(512));
diff --git a/arch/arm/include/asm/image.h b/arch/arm/include/asm/image.h
index d5c18a0f6a34..624438740f23 100644
--- a/arch/arm/include/asm/image.h
+++ b/arch/arm/include/asm/image.h
@@ -15,6 +15,7 @@
#define ARM_ZIMAGE_MAGIC1 ZIMAGE_MAGIC(0x016f2818)
#define ARM_ZIMAGE_MAGIC2 (0x45454545)
#define ARM_ZIMAGE_MAGIC3 ZIMAGE_MAGIC(0x5a534c4b)
+#define ARM_ZIMAGE_MAGIC4 ZIMAGE_MAGIC(0x5a534344)
#ifndef __ASSEMBLY__
@@ -43,6 +44,18 @@ struct arm_zimage_tag {
} u;
};
+struct arm_zimage_tag_dc {
+ struct tag_header hdr;
+ union {
+#define ZIMAGE_TAG_DECOMP_SIZE ARM_ZIMAGE_MAGIC4
+ struct zimage_decomp_size {
+ __le32 bss_size;
+ __le32 stack_size;
+ __le32 malloc_size;
+ } decomp_size;
+ } u;
+};
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_IMAGE_H */
--
2.26.2
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^ permalink raw reply related
* [PATCH 1/5] arm: decompressor: set malloc pool size for the decompressor
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <20200601142754.26139-1-l.stelmach@samsung.com>
Move the definition of malloc pool size of the decompressor to
a single place. This value will be exposed later for kexec_file loader.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
arch/arm/boot/compressed/Makefile | 2 ++
arch/arm/boot/compressed/head.S | 6 ++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 9c11e7490292..b3594cd1588c 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -125,6 +125,8 @@ KBSS_SZ = $(shell echo $$(($$($(NM) $(obj)/../../../../vmlinux | \
sed -n -e 's/^\([^ ]*\) [AB] __bss_start$$/-0x\1/p' \
-e 's/^\([^ ]*\) [AB] __bss_stop$$/+0x\1/p') )) )
LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
+# malloc pool size
+LDFLAGS_vmlinux += --defsym _malloc_size=0x10000
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index e8e1c866e413..dcc1afa60fb9 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -309,7 +309,8 @@ restart: adr r0, LC0
#ifndef CONFIG_ZBOOT_ROM
/* malloc space is above the relocated stack (64k max) */
add sp, sp, r0
- add r10, sp, #0x10000
+ ldr r10, =_malloc_size
+ add r10, r10, sp
#else
/*
* With ZBOOT_ROM the bss/stack is non relocatable,
@@ -623,7 +624,8 @@ not_relocated: mov r0, #0
*/
mov r0, r4
mov r1, sp @ malloc space above stack
- add r2, sp, #0x10000 @ 64k max
+ ldr r2, =_malloc_size @ 64k max
+ add r2, r2, sp
mov r3, r7
bl decompress_kernel
--
2.26.2
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^ permalink raw reply related
* [PATCH 0/5] kexec_file_load() for arm
From: Łukasz Stelmach @ 2020-06-01 14:27 UTC (permalink / raw)
To: Russell King, Masahiro Yamada, Nick Desaulniers, Thomas Gleixner,
Enrico Weigelt, Kees Cook, Ingo Molnar, Ben Dooks,
linux-arm-kernel, linux-kernel
Cc: AKASHI Takahiro, Marek Szyprowski, Łukasz Stelmach,
Bartlomiej Zolnierkiewicz
In-Reply-To: <CGME20200601142806eucas1p2680c5625411e7a695d8469760a926520@eucas1p2.samsung.com>
The following series of patches provides implementation of the
kexec_file_load() system call form the arm architecture. zImage and uImage
(legacy format) files are supported. Like on arm64, there is no
possibility of loading a new DTB and the currently loaded is reused.
Łukasz Stelmach (5):
arm: decompressor: set malloc pool size for the decompressor
arm: add image header definitions
arm: decompressor: define a new zImage tag
arm: Add kexec_image_info
arm: kexec_file: load zImage or uImage, initrd and dtb
arch/arm/Kconfig | 15 ++
arch/arm/boot/compressed/Makefile | 2 +
arch/arm/boot/compressed/head.S | 9 +-
arch/arm/boot/compressed/vmlinux.lds.S | 22 +--
arch/arm/include/asm/image.h | 87 ++++++++++
arch/arm/include/asm/kexec.h | 14 ++
arch/arm/kernel/Makefile | 5 +-
arch/arm/kernel/kexec_uimage.c | 80 ++++++++++
arch/arm/kernel/kexec_zimage.c | 199 +++++++++++++++++++++++
arch/arm/kernel/machine_kexec.c | 39 ++++-
arch/arm/kernel/machine_kexec_file.c | 209 +++++++++++++++++++++++++
11 files changed, 662 insertions(+), 19 deletions(-)
create mode 100644 arch/arm/include/asm/image.h
create mode 100644 arch/arm/kernel/kexec_uimage.c
create mode 100644 arch/arm/kernel/kexec_zimage.c
create mode 100644 arch/arm/kernel/machine_kexec_file.c
--
2.26.2
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^ permalink raw reply
* Re: [PATCH v2 2/6] prctl.2: Add PR_SPEC_INDIRECT_BRANCH for SPECULATION_CTRL prctls
From: Dave Martin @ 2020-06-01 13:51 UTC (permalink / raw)
To: Michael Kerrisk (man-pages)
Cc: linux-arch, linux-man, Thomas Gleixner, Tim Chen,
linux-arm-kernel
In-Reply-To: <CAKgNAkhwYASEM+wqaDZQ-ftcB3jnsVN2cXq4E_1ep1rqv+4aLw@mail.gmail.com>
On Thu, May 28, 2020 at 09:01:59AM +0200, Michael Kerrisk (man-pages) wrote:
> Hi Dave,
>
> On Wed, 27 May 2020 at 23:18, Dave Martin <Dave.Martin@arm.com> wrote:
> >
> > Add the PR_SPEC_INDIRECT_BRANCH "misfeature" added in Linux 4.20
> > for PR_SET_SPECULATION_CTRL and PR_GET_SPECULATION_CTRL.
> >
> > Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> > Cc: Tim Chen <tim.c.chen@linux.intel.com>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
>
> I had also applied this patch from the email you sent earlier. I've
> pushed those changes to master now.
Thanks for this.
Do you publish a "development" branch somewhere, or similar?
If possible, it's nice to have git rebase work out which patches to drop
for me rather than me doing it by hand.
Don't bother if publishing an extra branch doesn't fit with your
workflow, though.
Cheers
---Dave
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^ permalink raw reply
* Re: [PATCH v4 06/11] thermal: Add mode helpers
From: Guenter Roeck @ 2020-06-01 13:40 UTC (permalink / raw)
To: Andrzej Pietrasiewicz
Cc: Emmanuel Grumbach, Heiko Stuebner, Kalle Valo, linux-wireless,
Peter Kaestle, platform-driver-x86, Vishal Kulkarni, Luca Coelho,
Miquel Raynal, Shawn Guo, kernel, Fabio Estevam, Amit Kucheria,
linux-rockchip, Chunyan Zhang, Daniel Lezcano, linux-acpi,
linux-arm-kernel, Darren Hart, Zhang Rui, Gayatri Kammela,
NXP Linux Team, Johannes Berg, linux-pm, Sascha Hauer,
Intel Linux Wireless, Ido Schimmel, Niklas Söderlund,
Jiri Pirko, Orson Zhai, Thomas Gleixner, Allison Randal,
Support Opensource, netdev, Rafael J . Wysocki, Sebastian Reichel,
linux-renesas-soc, Bartlomiej Zolnierkiewicz,
Pengutronix Kernel Team, Baolin Wang, Len Brown, Enrico Weigelt,
David S . Miller, Andy Shevchenko
In-Reply-To: <526286da-70d2-7c55-3c41-15fd2c969a39@collabora.com>
On 6/1/20 4:16 AM, Andrzej Pietrasiewicz wrote:
> Hi Guenter,
>
> W dniu 29.05.2020 o 17:52, Guenter Roeck pisze:
>> On Thu, May 28, 2020 at 09:20:46PM +0200, Andrzej Pietrasiewicz wrote:
>>> Prepare for making the drivers not access tzd's private members.
>>>
>>> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
>
> <snip>
>
>>> +
>> Nit: unnecessary empty line.
>>
>>> + return ret;
>
> <snip>
>
>>> + return thermal_zone_device_set_mode(tz, THERMAL_DEVICE_ENABLED);
>>> +}
>>> +EXPORT_SYMBOL(thermal_zone_device_enable);
>>
>> Other exports in thermal/ use EXPORT_SYMBOL_GPL.
>
> Other than that does it look good to you?
Yes, it does.
> I can send a v5 where the two above will be corrected, but did you have
> a chance to review patches 7-11?
>
Not yet. I got distracted, sorry. Hopefully I'll get to it
today or tomorrow.
Guenter
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^ permalink raw reply
* Re: [PATCH v2 5/6] mm: tlb: Provide flush_*_tlb_range wrappers
From: Zhenyu Ye @ 2020-06-01 13:36 UTC (permalink / raw)
To: Catalin Marinas
Cc: mark.rutland, peterz, linux-mm, guohanjun, will, linux-arch,
yuzhao, aneesh.kumar, steven.price, arm, Dave.Martin, arnd,
suzuki.poulose, npiggin, zhangshaokun, broonie, rostedt,
prime.zeng, kuhn.chenqun, tglx, linux-arm-kernel, xiexiangyou,
linux-kernel, maz, akpm
In-Reply-To: <20200601115644.GA23419@gaia>
On 2020/6/1 19:56, Catalin Marinas wrote:
> Hi Zhenyu,
>
> On Sat, May 30, 2020 at 06:24:21PM +0800, Zhenyu Ye wrote:
>> On 2020/5/26 22:52, Catalin Marinas wrote:
>>> On Mon, May 25, 2020 at 03:19:42PM +0800, Zhenyu Ye wrote:
>>>> tlb_flush_##_pxx##_range() is used to set tlb->cleared_*,
>>>> flush_##_pxx##_tlb_range() will actually flush the TLB entry.
>>>>
>>>> In arch64, tlb_flush_p?d_range() is defined as:
>>>>
>>>> #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
>>>> #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
>>>
>>> Currently, flush_p??_tlb_range() are generic and defined as above. I
>>> think in the generic code they can remain an alias for
>>> flush_tlb_range().
>>>
>>> On arm64, we can redefine them as:
>>>
>>> #define flush_pte_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 3)
>>> #define flush_pmd_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 2)
>>> #define flush_pud_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 1)
>>> #define flush_p4d_tlb_range(vma, addr, end) __flush_tlb_range(vma, addr, end, 0)
>>>
>>> (unless the compiler optimises away all the mmu_gather stuff in your
>>> macro above but they don't look trivial to me)
>>
>> I changed generic code before considering that other structures may also
>> use this feature, such as Power9. And Peter may want to replace all
>> flush_tlb_range() by tlb_flush() in the future, see [1] for details.
>>
>> If only enable this feature on aarch64, your codes are better.
>>
>> [1] https://lore.kernel.org/linux-arm-kernel/20200402163849.GM20713@hirez.programming.kicks-ass.net/
>
> But we change the semantics slightly if we implement these as
> mmu_gather. For example, tlb_end_vma() -> tlb_flush_mmu_tlbonly() ends
> up calling mmu_notifier_invalidate_range() which it didn't before. I
> think we end up invoking the notifier unnecessarily in some cases (see
> the comment in __split_huge_pmd()) or we end up calling the notifier
> twice (e.g. pmdp_huge_clear_flush_notify()).
>
Yes, so only enable this feature on aarch64 may be better.
I will change this in V4 of this series. [the v3 only has some minor
changes and can be ignored :)]
>>> Also, I don't see the new flush_pte_* and flush_p4d_* macros used
>>> anywhere and I don't think they are needed. The pte equivalent is
>>> flush_tlb_page() (we need to make sure it's not used on a pmd in the
>>> hugetlb context).
>>
>> flush_tlb_page() is used to flush only one page. If we add the
>> flush_pte_tlb_range(), then we can use it to flush a range of pages in
>> the future.
>
> If we know flush_tlb_page() is only called on a small page, could we add
> TTL information here as well?
>
Yes, we could. I will add this in flush_tlb_page().
>> But flush_pte_* and flush_p4d_* macros are really not used anywhere. I
>> will remove them in next version of series, and add them if someone
>> needs.
>
> I think it makes sense.
>
Thanks,
Zhenyu
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^ permalink raw reply
* Re: [PATCH 2/2] coresight: tmc: Add shutdown callback for TMC ETR/ETF
From: Mike Leach @ 2020-06-01 13:35 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mathieu Poirier, Suzuki K Poulose, linux-arm-msm, Coresight ML,
Linux Kernel Mailing List, Stephen Boyd, linux-arm-kernel
In-Reply-To: <28123d1e19f235f97555ee36a5ed8b52d20cbdea.1590947174.git.saiprakash.ranjan@codeaurora.org>
Hi,
On Mon, 1 Jun 2020 at 09:02, Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Implement a shutdown callback to ensure ETR/ETF hardware is
> properly shutdown in reboot/shutdown path. This is required
> for ETR/ETF which has SMMU address translation enabled like
> on SC7180 SoC and few others. If the hardware is still accessing
> memory after SMMU translation is disabled as part of SMMU
> shutdown callback in system reboot or shutdown path, then
> IOVAs(I/O virtual address) which it was using will go on the bus
> as the physical addresses which might result in unknown crashes
> (NoC/interconnect errors). So we make sure from this shutdown
> callback that the ETR/ETF is shutdown before SMMU translation is
> disabled and device_link in SMMU driver will take care of ordering
> of shutdown callbacks such that SMMU shutdown callback is not
> called before any of its consumer shutdown callbacks.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> .../hwtracing/coresight/coresight-tmc-etf.c | 4 +--
> .../hwtracing/coresight/coresight-tmc-etr.c | 2 +-
> drivers/hwtracing/coresight/coresight-tmc.c | 29 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tmc.h | 3 ++
> 4 files changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 36cce2bfb744..cba3e7592820 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -85,7 +85,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> CS_LOCK(drvdata->base);
> }
>
> -static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> +void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
> {
> __tmc_etb_disable_hw(drvdata);
> coresight_disclaim_device(drvdata->base);
> @@ -118,7 +118,7 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
> return 0;
> }
>
> -static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
> +void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
> {
> CS_UNLOCK(drvdata->base);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 625882bc8b08..b29c2db94d96 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1110,7 +1110,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
>
> }
>
> -static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> +void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> {
> __tmc_etr_disable_hw(drvdata);
> /* Disable CATU device if this ETR is connected to one */
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index 5a271ebc4585..7e687a356fe0 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -540,6 +540,34 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> return ret;
> }
>
> +static void tmc_shutdown(struct amba_device *adev)
> +{
> + struct tmc_drvdata *drvdata = amba_get_drvdata(adev);
> +
Take drvdata->spinlock here? The tmc_xxx_disable_hw functions are
normally called with the spinlock claimed.
> + if (!drvdata->enable)
As per previous patch drvdata->mode can be used here.
Regards
Mike
> + goto out;
> +
> + /*
> + * We do not care about the active trace sessions here
> + * since the system is going down unlike remove callback,
> + * just make sure that the hardware is shutdown.
> + */
> + switch (drvdata->config_type) {
> + case TMC_CONFIG_TYPE_ETB:
> + tmc_etb_disable_hw(drvdata);
> + break;
> + case TMC_CONFIG_TYPE_ETF:
> + tmc_etf_disable_hw(drvdata);
> + break;
> + case TMC_CONFIG_TYPE_ETR:
> + tmc_etr_disable_hw(drvdata);
> + }
> +
> +out:
> + misc_deregister(&drvdata->miscdev);
> + coresight_unregister(drvdata->csdev);
> +}
> +
> static const struct amba_id tmc_ids[] = {
> CS_AMBA_ID(0x000bb961),
> /* Coresight SoC 600 TMC-ETR/ETS */
> @@ -558,6 +586,7 @@ static struct amba_driver tmc_driver = {
> .suppress_bind_attrs = true,
> },
> .probe = tmc_probe,
> + .shutdown = tmc_shutdown,
> .id_table = tmc_ids,
> };
> builtin_amba_driver(tmc_driver);
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index d156860495c7..f4f56c474e58 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -262,6 +262,8 @@ u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
> /* ETB/ETF functions */
> int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
> int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
> +void tmc_etb_disable_hw(struct tmc_drvdata *drvdata);
> +void tmc_etf_disable_hw(struct tmc_drvdata *drvdata);
> extern const struct coresight_ops tmc_etb_cs_ops;
> extern const struct coresight_ops tmc_etf_cs_ops;
>
> @@ -270,6 +272,7 @@ ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
> /* ETR functions */
> int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
> int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
> +void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
> extern const struct coresight_ops tmc_etr_cs_ops;
> ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
> loff_t pos, size_t len, char **bufpp);
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
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^ permalink raw reply
* Re: [PATCH 1/2] coresight: tmc: Add enable flag to indicate the status of ETR/ETF
From: Mike Leach @ 2020-06-01 13:27 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mathieu Poirier, Suzuki K Poulose, linux-arm-msm, Coresight ML,
Linux Kernel Mailing List, Stephen Boyd, linux-arm-kernel
In-Reply-To: <6e62147c36c76b9485d14960dced4f6acda17591.1590947174.git.saiprakash.ranjan@codeaurora.org>
Hi,
On Mon, 1 Jun 2020 at 09:02, Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Add a flag to check whether TMC ETR/ETF is enabled or not.
> This is later used in shutdown callback to determine if
> we require to disable ETR/ETF.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
> drivers/hwtracing/coresight/coresight-tmc.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
> index 39fba1d16e6e..5a271ebc4585 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
> @@ -62,11 +62,13 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
>
> void tmc_enable_hw(struct tmc_drvdata *drvdata)
> {
> + drvdata->enable = true;
> writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
> }
>
> void tmc_disable_hw(struct tmc_drvdata *drvdata)
> {
> + drvdata->enable = false;
> writel_relaxed(0x0, drvdata->base + TMC_CTL);
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 71de978575f3..d156860495c7 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -184,6 +184,7 @@ struct etr_buf {
> * @idr_mutex: Access serialisation for idr.
> * @sysfs_buf: SYSFS buffer for ETR.
> * @perf_buf: PERF buffer for ETR.
> + * @enable: Indicates whether ETR/ETF is enabled.
> */
> struct tmc_drvdata {
> void __iomem *base;
> @@ -207,6 +208,7 @@ struct tmc_drvdata {
> struct mutex idr_mutex;
> struct etr_buf *sysfs_buf;
> struct etr_buf *perf_buf;
> + bool enable;
Is this flag needed?
For TMC, drvdata->mode indicates if the device is in use.
Regards
Mike
> };
>
> struct etr_buf_operations {
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
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^ permalink raw reply
* Re: [trivial PATCH] video: fbdev: Use IS_BUILTIN
From: Bartlomiej Zolnierkiewicz @ 2020-06-01 13:25 UTC (permalink / raw)
To: Joe Perches
Cc: linux-fbdev, linux-samsung-soc, linux-kernel, dri-devel,
linux-omap, linux-arm-kernel
In-Reply-To: <b1cf967015c5beafa475aaa30d8e21a58caff870.camel@perches.com>
On 5/5/20 1:29 AM, Joe Perches wrote:
> IS_BUILTIN can be use to replace various initializations
> like #if CONFIG_<FOO> int val = 1; #else int val = 0; #endif
> so do so.
>
> Signed-off-by: Joe Perches <joe@perches.com>
Applied to drm-misc-next tree (patch should show up in v5.9), thanks.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> ---
> drivers/video/fbdev/aty/aty128fb.c | 6 +-----
> drivers/video/fbdev/aty/atyfb_base.c | 7 +------
> drivers/video/fbdev/aty/radeon_base.c | 6 +-----
> drivers/video/fbdev/nvidia/nvidia.c | 6 +-----
> drivers/video/fbdev/omap/omapfb_main.c | 6 +-----
> drivers/video/fbdev/riva/fbdev.c | 6 +-----
> drivers/video/fbdev/s3c2410fb.c | 6 +-----
> 7 files changed, 7 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/video/fbdev/aty/aty128fb.c b/drivers/video/fbdev/aty/aty128fb.c
> index d05d4195acad..6fae6ad6cb77 100644
> --- a/drivers/video/fbdev/aty/aty128fb.c
> +++ b/drivers/video/fbdev/aty/aty128fb.c
> @@ -384,11 +384,7 @@ static int default_lcd_on = 1;
> static bool mtrr = true;
>
> #ifdef CONFIG_FB_ATY128_BACKLIGHT
> -#ifdef CONFIG_PMAC_BACKLIGHT
> -static int backlight = 1;
> -#else
> -static int backlight = 0;
> -#endif
> +static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
> #endif
>
> /* PLL constants */
> diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c
> index 49d192869cf5..23a29d61c2a2 100644
> --- a/drivers/video/fbdev/aty/atyfb_base.c
> +++ b/drivers/video/fbdev/aty/atyfb_base.c
> @@ -317,12 +317,7 @@ static int mclk;
> static int xclk;
> static int comp_sync = -1;
> static char *mode;
> -
> -#ifdef CONFIG_PMAC_BACKLIGHT
> -static int backlight = 1;
> -#else
> -static int backlight = 0;
> -#endif
> +static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
>
> #ifdef CONFIG_PPC
> static int default_vmode = VMODE_CHOOSE;
> diff --git a/drivers/video/fbdev/aty/radeon_base.c b/drivers/video/fbdev/aty/radeon_base.c
> index e116a3f9ad56..3fe509cb9b87 100644
> --- a/drivers/video/fbdev/aty/radeon_base.c
> +++ b/drivers/video/fbdev/aty/radeon_base.c
> @@ -269,11 +269,7 @@ static bool force_measure_pll = 0;
> static bool nomtrr = 0;
> static bool force_sleep;
> static bool ignore_devlist;
> -#ifdef CONFIG_PMAC_BACKLIGHT
> -static int backlight = 1;
> -#else
> -static int backlight = 0;
> -#endif
> +static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
>
> /* Note about this function: we have some rare cases where we must not schedule,
> * this typically happen with our special "wake up early" hook which allows us to
> diff --git a/drivers/video/fbdev/nvidia/nvidia.c b/drivers/video/fbdev/nvidia/nvidia.c
> index c24de9107958..c6820e21875d 100644
> --- a/drivers/video/fbdev/nvidia/nvidia.c
> +++ b/drivers/video/fbdev/nvidia/nvidia.c
> @@ -74,11 +74,7 @@ static int vram = 0;
> static int bpp = 8;
> static int reverse_i2c;
> static bool nomtrr = false;
> -#ifdef CONFIG_PMAC_BACKLIGHT
> -static int backlight = 1;
> -#else
> -static int backlight = 0;
> -#endif
> +static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
>
> static char *mode_option = NULL;
>
> diff --git a/drivers/video/fbdev/omap/omapfb_main.c b/drivers/video/fbdev/omap/omapfb_main.c
> index 1a9d6242916e..0cbcc74fa943 100644
> --- a/drivers/video/fbdev/omap/omapfb_main.c
> +++ b/drivers/video/fbdev/omap/omapfb_main.c
> @@ -34,11 +34,7 @@ static unsigned long def_vyres;
> static unsigned int def_rotate;
> static unsigned int def_mirror;
>
> -#ifdef CONFIG_FB_OMAP_MANUAL_UPDATE
> -static bool manual_update = 1;
> -#else
> -static bool manual_update;
> -#endif
> +static bool manual_update = IS_BUILTIN(CONFIG_FB_OMAP_MANUAL_UPDATE);
>
> static struct platform_device *fbdev_pdev;
> static struct lcd_panel *fbdev_panel;
> diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c
> index 764ec3285e62..9b3493846f4d 100644
> --- a/drivers/video/fbdev/riva/fbdev.c
> +++ b/drivers/video/fbdev/riva/fbdev.c
> @@ -202,11 +202,7 @@ static int flatpanel = -1; /* Autodetect later */
> static int forceCRTC = -1;
> static bool noaccel = 0;
> static bool nomtrr = 0;
> -#ifdef CONFIG_PMAC_BACKLIGHT
> -static int backlight = 1;
> -#else
> -static int backlight = 0;
> -#endif
> +static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
>
> static char *mode_option = NULL;
> static bool strictmode = 0;
> diff --git a/drivers/video/fbdev/s3c2410fb.c b/drivers/video/fbdev/s3c2410fb.c
> index 2fb15a540167..6f8fa501583f 100644
> --- a/drivers/video/fbdev/s3c2410fb.c
> +++ b/drivers/video/fbdev/s3c2410fb.c
> @@ -44,11 +44,7 @@
> #include "s3c2410fb.h"
>
> /* Debugging stuff */
> -#ifdef CONFIG_FB_S3C2410_DEBUG
> -static int debug = 1;
> -#else
> -static int debug;
> -#endif
> +static int debug = IS_BUILTIN(CONFIG_FB_S3C2410_DEBUG);
>
> #define dprintk(msg...) \
> do { \
>
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^ permalink raw reply
* Re: [PATCH] iommu/arm-smmu-v3: expose numa_node attribute to users in sysfs
From: Robin Murphy @ 2020-06-01 13:13 UTC (permalink / raw)
To: Barry Song, will, hch, m.szyprowski, iommu; +Cc: linuxarm, linux-arm-kernel
In-Reply-To: <20200530091505.56664-1-song.bao.hua@hisilicon.com>
On 2020-05-30 10:15, Barry Song wrote:
> As tests show the latency of dma_unmap can increase dramatically while
> calling them cross NUMA nodes, especially cross CPU packages, eg.
> 300ns vs 800ns while waiting for the completion of CMD_SYNC in an
> empty command queue. The large latency causing by remote node will
> in turn make contention of the command queue more serious, and enlarge
> the latency of DMA users within local NUMA nodes.
>
> Users might intend to enforce NUMA locality with the consideration of
> the position of SMMU. The patch provides minor benefit by presenting
> this information to users directly, as they might want to know it without
> checking hardware spec at all.
Hmm, given that dev-to_node() is a standard driver model thing, is there
not already some generic device property that can expose it - and if
not, should there be? Presumably if userspace cares enough to want to
know whereabouts in the system an IOMMU is, it probably also cares where
the actual endpoint devices are too.
At the very least, it doesn't seem right for it to be specific to one
single IOMMU driver.
Robin.
> Signed-off-by: Barry Song <song.bao.hua@hisilicon.com>
> ---
> drivers/iommu/arm-smmu-v3.c | 40 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 82508730feb7..754c4d59498b 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -4021,6 +4021,44 @@ err_reset_pci_ops: __maybe_unused;
> return err;
> }
>
> +static ssize_t numa_node_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "%d\n", dev_to_node(dev));
> +}
> +static DEVICE_ATTR_RO(numa_node);
> +
> +static umode_t arm_smmu_numa_attr_visible(struct kobject *kobj, struct attribute *a,
> + int n)
> +{
> + struct device *dev = container_of(kobj, typeof(*dev), kobj);
> +
> + if (!IS_ENABLED(CONFIG_NUMA))
> + return 0;
> +
> + if (a == &dev_attr_numa_node.attr &&
> + dev_to_node(dev) == NUMA_NO_NODE)
> + return 0;
> +
> + return a->mode;
> +}
> +
> +static struct attribute *arm_smmu_dev_attrs[] = {
> + &dev_attr_numa_node.attr,
> + NULL
> +};
> +
> +static struct attribute_group arm_smmu_dev_attrs_group = {
> + .attrs = arm_smmu_dev_attrs,
> + .is_visible = arm_smmu_numa_attr_visible,
> +};
> +
> +
> +static const struct attribute_group *arm_smmu_dev_attrs_groups[] = {
> + &arm_smmu_dev_attrs_group,
> + NULL,
> +};
> +
> static int arm_smmu_device_probe(struct platform_device *pdev)
> {
> int irq, ret;
> @@ -4097,7 +4135,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
> return ret;
>
> /* And we're up. Go go go! */
> - ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
> + ret = iommu_device_sysfs_add(&smmu->iommu, dev, arm_smmu_dev_attrs_groups,
> "smmu3.%pa", &ioaddr);
> if (ret)
> return ret;
>
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^ permalink raw reply
* [PATCH] PCI: aardvark: Indicate error in 'val' when config read fails
From: Pali Rohár @ 2020-06-01 13:03 UTC (permalink / raw)
To: Bjorn Helgaas, Thomas Petazzoni, Lorenzo Pieralisi, Andrew Murray,
Marek Behún, Remi Pommarel, Tomasz Maciej Nowak, Xogium
Cc: linux-pci, linux-kernel, linux-arm-kernel
Most callers of config read do not check for return value. But most of the
ones that do, checks for error indication in 'val' variable.
This patch updates error handling in advk_pcie_rd_conf() function. If PIO
transfer fails then 'val' variable is set to 0xffffffff which indicates
failture.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 53a4cfd7d377..783a7f1f2c44 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -691,8 +691,10 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
advk_writel(pcie, 1, PIO_START);
ret = advk_pcie_wait_pio(pcie);
- if (ret < 0)
+ if (ret < 0) {
+ *val = 0xffffffff;
return PCIBIOS_SET_FAILED;
+ }
advk_pcie_check_pio_status(pcie);
--
2.20.1
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^ permalink raw reply related
* RE: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for platform devices
From: Shameerali Kolothum Thodi @ 2020-06-01 12:42 UTC (permalink / raw)
To: Jean-Philippe Brucker, iommu@lists.linux-foundation.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, linux-mm@kvack.org
Cc: fenghua.yu@intel.com, kevin.tian@intel.com, will@kernel.org,
catalin.marinas@arm.com, felix.kuehling@amd.com,
hch@infradead.org, jgg@ziepe.ca, zhangfei.gao@linaro.org,
robin.murphy@arm.com, christian.koenig@amd.com
In-Reply-To: <20200519175502.2504091-22-jean-philippe@linaro.org>
Hi Jean,
> -----Original Message-----
> From: iommu [mailto:iommu-bounces@lists.linux-foundation.org] On Behalf Of
> Jean-Philippe Brucker
> Sent: 19 May 2020 18:55
> To: iommu@lists.linux-foundation.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-pci@vger.kernel.org;
> linux-mm@kvack.org
> Cc: fenghua.yu@intel.com; kevin.tian@intel.com; jgg@ziepe.ca;
> catalin.marinas@arm.com; robin.murphy@arm.com; hch@infradead.org;
> zhangfei.gao@linaro.org; Jean-Philippe Brucker <jean-philippe@linaro.org>;
> felix.kuehling@amd.com; will@kernel.org; christian.koenig@amd.com
> Subject: [PATCH v7 21/24] iommu/arm-smmu-v3: Add stall support for platform
> devices
>
> The SMMU provides a Stall model for handling page faults in platform
> devices. It is similar to PCI PRI, but doesn't require devices to have
> their own translation cache. Instead, faulting transactions are parked
> and the OS is given a chance to fix the page tables and retry the
> transaction.
>
> Enable stall for devices that support it (opt-in by firmware). When an
> event corresponds to a translation error, call the IOMMU fault handler.
> If the fault is recoverable, it will call us back to terminate or
> continue the stall.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
> ---
> drivers/iommu/Kconfig | 1 +
> include/linux/iommu.h | 2 +
> drivers/iommu/arm-smmu-v3.c | 284
> ++++++++++++++++++++++++++++++++++--
> drivers/iommu/of_iommu.c | 5 +-
> 4 files changed, 281 insertions(+), 11 deletions(-)
>
[...]
> +static int arm_smmu_page_response(struct device *dev,
> + struct iommu_fault_event *unused,
> + struct iommu_page_response *resp)
> +{
> + struct arm_smmu_cmdq_ent cmd = {0};
> + struct arm_smmu_master *master = dev_iommu_priv_get(dev);
> + int sid = master->streams[0].id;
> +
> + if (master->stall_enabled) {
> + cmd.opcode = CMDQ_OP_RESUME;
> + cmd.resume.sid = sid;
> + cmd.resume.stag = resp->grpid;
> + switch (resp->code) {
> + case IOMMU_PAGE_RESP_INVALID:
> + case IOMMU_PAGE_RESP_FAILURE:
> + cmd.resume.resp = CMDQ_RESUME_0_RESP_ABORT;
> + break;
> + case IOMMU_PAGE_RESP_SUCCESS:
> + cmd.resume.resp = CMDQ_RESUME_0_RESP_RETRY;
> + break;
> + default:
> + return -EINVAL;
> + }
> + } else {
> + /* TODO: insert PRI response here */
> + return -ENODEV;
> + }
> +
> + arm_smmu_cmdq_issue_cmd(master->smmu, &cmd);
> + /*
> + * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP.
> + * RESUME consumption guarantees that the stalled transaction will be
> + * terminated... at some point in the future. PRI_RESP is fire and
> + * forget.
> + */
> +
> + return 0;
> +}
> +
> /* Context descriptor manipulation functions */
> static void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16
> asid)
> {
> @@ -1762,8 +1846,7 @@ static int arm_smmu_write_ctx_desc(struct
> arm_smmu_domain *smmu_domain,
> FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) |
> CTXDESC_CD_0_V;
>
> - /* STALL_MODEL==0b10 && CD.S==0 is ILLEGAL */
> - if (smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
> + if (smmu_domain->stall_enabled)
> val |= CTXDESC_CD_0_S;
> }
>
> @@ -2171,7 +2254,7 @@ static void arm_smmu_write_strtab_ent(struct
> arm_smmu_master *master, u32 sid,
> FIELD_PREP(STRTAB_STE_1_STRW, strw));
>
> if (smmu->features & ARM_SMMU_FEAT_STALLS &&
> - !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
> + !master->stall_enabled)
> dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
>
> val |= (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK)
> |
> @@ -2248,7 +2331,6 @@ static int arm_smmu_init_l2_strtab(struct
> arm_smmu_device *smmu, u32 sid)
> return 0;
> }
>
> -__maybe_unused
> static struct arm_smmu_master *
> arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid)
> {
> @@ -2275,23 +2357,123 @@ arm_smmu_find_master(struct
> arm_smmu_device *smmu, u32 sid)
> }
>
> /* IRQ and event handlers */
> +static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt)
> +{
> + int ret;
> + u32 perm = 0;
> + struct arm_smmu_master *master;
> + bool ssid_valid = evt[0] & EVTQ_0_SSV;
> + u8 type = FIELD_GET(EVTQ_0_ID, evt[0]);
> + u32 sid = FIELD_GET(EVTQ_0_SID, evt[0]);
> + struct iommu_fault_event fault_evt = { };
> + struct iommu_fault *flt = &fault_evt.fault;
> +
> + /* Stage-2 is always pinned at the moment */
> + if (evt[1] & EVTQ_1_S2)
> + return -EFAULT;
> +
> + master = arm_smmu_find_master(smmu, sid);
> + if (!master)
> + return -EINVAL;
> +
> + if (evt[1] & EVTQ_1_READ)
> + perm |= IOMMU_FAULT_PERM_READ;
> + else
> + perm |= IOMMU_FAULT_PERM_WRITE;
> +
> + if (evt[1] & EVTQ_1_EXEC)
> + perm |= IOMMU_FAULT_PERM_EXEC;
> +
> + if (evt[1] & EVTQ_1_PRIV)
> + perm |= IOMMU_FAULT_PERM_PRIV;
> +
> + if (evt[1] & EVTQ_1_STALL) {
> + flt->type = IOMMU_FAULT_PAGE_REQ;
> + flt->prm = (struct iommu_fault_page_request) {
> + .flags = IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE,
> + .pasid = FIELD_GET(EVTQ_0_SSID, evt[0]),
> + .grpid = FIELD_GET(EVTQ_1_STAG, evt[1]),
> + .perm = perm,
> + .addr = FIELD_GET(EVTQ_2_ADDR, evt[2]),
> + };
> +
> + if (ssid_valid)
> + flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
Do we need to set this for STALL mode only support? I had an issue with this
being set on a vSVA POC based on our D06 zip device(which is a "fake " pci dev
that supports STALL mode but no PRI). The issue is, CMDQ_OP_RESUME doesn't
have any ssid or SSV params and works on sid and stag only. Hence, it is difficult for
Qemu SMMUv3 to populate this fields while preparing a page response. I can see
that this flag is being checked in iopf_handle_single() (patch 04/24) as well. For POC,
I used a temp fix[1] to work around this. Please let me know your thoughts.
Thanks,
Shameer
1. https://github.com/hisilicon/kernel-dev/commit/99ff96146e924055f38d97a5897e4becfa378d15
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^ permalink raw reply
* RE: [PATCH 2/4] firmware: imx: add resource management api
From: Peng Fan @ 2020-06-01 12:40 UTC (permalink / raw)
To: Aisheng Dong, shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: festevam@gmail.com, Joakim Zhang, linux@rempel-privat.de,
linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de,
Leonard Crestez, Daniel Baluta, linux-kernel@vger.kernel.org,
dl-linux-imx
In-Reply-To: <AM6PR04MB4966A484AA8E480D7E479F9E80D00@AM6PR04MB4966.eurprd04.prod.outlook.com>
> Subject: RE: [PATCH 2/4] firmware: imx: add resource management api
>
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Friday, April 24, 2020 9:12 AM
> > >
> > > > From: Peng Fan <peng.fan@nxp.com>
> > > > Sent: Thursday, April 23, 2020 6:57 PM
> > > > > > From: Peng Fan <peng.fan@nxp.com>
> > > > > > Sent: Thursday, April 23, 2020 3:00 PM
> > > > > >
> > > > > > Add resource management API, when we have multiple partition
> > > > > > running together, resources not owned to current partition
> > > > > > should not be
> > > used.
> > > > > >
> > > > > > Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > >
> > > > > Right now I'm still not quite understand if we really need this.
> > > > > As current resource is bound to power domains, if it's not owned
> > > > > by one specific SW execution environment, power on will also fail.
> > > > > Can you clarify if any exceptions?
> > > >
> > > > There will be lots of failures when boot Linux domu if no check.
> > > >
> > >
> > > What kind of features did you mean?
> > > Could you clarify a bit more? I'd like to understand this issue better.
> >
> > When supporting hypervisor with dual Linux running, 1st Linux and the
> > 2nd Linux will have their own dedicated resources.
> >
> > If no resource check, that means 1st/2nd Linux will register all the
> > resources, then both will see fail logs when register resources not owned to
> itself.
> >
> > Same to partitioned m4 case.
> >
> > Would it be better without the failure log?
> >
>
> Is it power up failure?
> If yes, it's expected because we actually use power up to check if resources
> are owned by this partition. It functions the same as calling resource check
> API.
> That's current design.
>
> Or it's other failures? Log?
Sorry for long late reply.
Part of my XEN DomU log, there are lots of failure log. I think better not
have such logs by add a resource own check.
[ 2.034774] imx6q-pcie 5f000000.pcie: IO 0x6ff80000..0x6ff8ffff -> 0x00000000
[ 2.034801] imx6q-pcie 5f000000.pcie: MEM 0x60000000..0x6fefffff -> 0x60000000
[ 2.035072] sdhc1: failed to power up resource 249 ret -13
[ 2.035619] sdhc2: failed to power up resource 250 ret -13
[ 2.036126] enet0: failed to power up resource 251 ret -13
[ 2.036584] enet1: failed to power up resource 252 ret -13
[ 2.037040] mlb0: failed to power up resource 253 ret -13
[ 2.037495] nand: failed to power up resource 265 ret -13
[ 2.037951] nand: failed to power up resource 265 ret -13
[ 2.038416] pwm0: failed to power up resource 191 ret -13
[ 2.038868] pwm1: failed to power up resource 192 ret -13
[ 2.039320] pwm2: failed to power up resource 193 ret -13
[ 2.039786] pwm3: failed to power up resource 194 ret -13
[ 2.040239] pwm4: failed to power up resource 195 ret -13
[ 2.040692] pwm5: failed to power up resource 196 ret -13
[ 2.041142] pwm6: failed to power up resource 197 ret -13
[ 2.041596] pwm7: failed to power up resource 198 ret -13
[ 2.042073] amix: failed to power up resource 458 ret -13
[ 2.042558] lpspi0: failed to power up resource 53 ret -13
[ 2.043033] lpspi1: failed to power up resource 54 ret -13
[ 2.043501] lpspi2: failed to power up resource 55 ret -13
[ 2.043992] lpspi3: failed to power up resource 56 ret -13
[ 2.044460] lpuart0: failed to power up resource 57 ret -13
[ 2.044935] lpuart2: failed to power up resource 59 ret -13
[ 2.045409] lpuart3: failed to power up resource 60 ret -13
[ 2.055014] sim0: failed to power up resource 62 ret -13
[ 2.055510] adc0: failed to power up resource 101 ret -13
[ 2.056467] lpi2c0: failed to power up resource 96 ret -13
[ 2.056946] lpi2c1: failed to power up resource 97 ret -13
[ 2.057424] lpi2c2: failed to power up resource 98 ret -13
[ 2.057898] lpi2c3: failed to power up resource 99 ret -13
[ 2.058371] can0: failed to power up resource 105 ret -13
[ 2.059289] can1: failed to power up resource 106 ret -13
[ 2.059801] can2: failed to power up resource 107 ret -13
[ 2.060281] nand: failed to power up resource 265 ret -13
[ 2.062764] dpu-core 56180000.dpu: driver probed
Thanks,
Peng.
>
> Regards
> Aisheng
>
> > Thanks,
> > Peng.
> >
> >
> > >
> > > Regards
> > > Aisheng
> > >
> > > > Thanks,
> > > > Peng.
> > > >
> > > > >
> > > > > Regards
> > > > > Aisheng
> > > > >
> > > > > > ---
> > > > > > drivers/firmware/imx/Makefile | 2 +-
> > > > > > drivers/firmware/imx/rm.c | 40
> > > +++++++++++++++++++++
> > > > > > include/linux/firmware/imx/sci.h | 1 +
> > > > > > include/linux/firmware/imx/svc/rm.h | 69
> > > > > > +++++++++++++++++++++++++++++++++++++
> > > > > > 4 files changed, 111 insertions(+), 1 deletion(-) create
> > > > > > mode
> > > > > > 100644 drivers/firmware/imx/rm.c create mode 100644
> > > > > > include/linux/firmware/imx/svc/rm.h
> > > > > >
> > > > > > diff --git a/drivers/firmware/imx/Makefile
> > > > > > b/drivers/firmware/imx/Makefile index
> > > > > > 08bc9ddfbdfb..17ea3613e142
> > > > > > 100644
> > > > > > --- a/drivers/firmware/imx/Makefile
> > > > > > +++ b/drivers/firmware/imx/Makefile
> > > > > > @@ -1,4 +1,4 @@
> > > > > > # SPDX-License-Identifier: GPL-2.0
> > > > > > obj-$(CONFIG_IMX_DSP) += imx-dsp.o
> > > > > > -obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o
> > > > > > +obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o
> rm.o
> > > > > > obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
> > > > > > diff --git a/drivers/firmware/imx/rm.c
> > > > > > b/drivers/firmware/imx/rm.c new file mode 100644 index
> > > > > > 000000000000..7b0334de5486
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/firmware/imx/rm.c
> > > > > > @@ -0,0 +1,40 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > > +/*
> > > > > > + * Copyright 2020 NXP
> > > > > > + *
> > > > > > + * File containing client-side RPC functions for the RM service.
> > > > > > +These
> > > > > > + * function are ported to clients that communicate to the SC.
> > > > > > + */
> > > > > > +
> > > > > > +#include <linux/firmware/imx/svc/rm.h>
> > > > > > +
> > > > > > +struct imx_sc_msg_rm_rsrc_owned {
> > > > > > + struct imx_sc_rpc_msg hdr;
> > > > > > + u16 resource;
> > > > > > +} __packed __aligned(4);
> > > > > > +
> > > > > > +/*
> > > > > > + * This function check @resource is owned by current
> > > > > > +partition or not
> > > > > > + *
> > > > > > + * @param[in] ipc IPC handle
> > > > > > + * @param[in] resource resource the control is
> associated
> > > with
> > > > > > + *
> > > > > > + * @return Returns 0 for success and < 0 for errors.
> > > > > > + */
> > > > > > +bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16
> > > > > > +resource) {
> > > > > > + struct imx_sc_msg_rm_rsrc_owned msg;
> > > > > > + struct imx_sc_rpc_msg *hdr = &msg.hdr;
> > > > > > +
> > > > > > + hdr->ver = IMX_SC_RPC_VERSION;
> > > > > > + hdr->svc = IMX_SC_RPC_SVC_RM;
> > > > > > + hdr->func = IMX_SC_RM_FUNC_IS_RESOURCE_OWNED;
> > > > > > + hdr->size = 2;
> > > > > > +
> > > > > > + msg.resource = resource;
> > > > > > +
> > > > > > + imx_scu_call_rpc(ipc, &msg, true);
> > > > > > +
> > > > > > + return hdr->func;
> > > > > > +}
> > > > > > +EXPORT_SYMBOL(imx_sc_rm_is_resource_owned);
> > > > > > diff --git a/include/linux/firmware/imx/sci.h
> > > > > > b/include/linux/firmware/imx/sci.h
> > > > > > index 17ba4e405129..b5c5a56f29be 100644
> > > > > > --- a/include/linux/firmware/imx/sci.h
> > > > > > +++ b/include/linux/firmware/imx/sci.h
> > > > > > @@ -15,6 +15,7 @@
> > > > > >
> > > > > > #include <linux/firmware/imx/svc/misc.h> #include
> > > > > > <linux/firmware/imx/svc/pm.h>
> > > > > > +#include <linux/firmware/imx/svc/rm.h>
> > > > > >
> > > > > > int imx_scu_enable_general_irq_channel(struct device *dev);
> > > > > > int imx_scu_irq_register_notifier(struct notifier_block *nb);
> > > > > > diff --git a/include/linux/firmware/imx/svc/rm.h
> > > > > > b/include/linux/firmware/imx/svc/rm.h
> > > > > > new file mode 100644
> > > > > > index 000000000000..fc6ea62d9d0e
> > > > > > --- /dev/null
> > > > > > +++ b/include/linux/firmware/imx/svc/rm.h
> > > > > > @@ -0,0 +1,69 @@
> > > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > > +/*
> > > > > > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > > > > > + * Copyright 2017-2019 NXP
> > > > > > + *
> > > > > > + * Header file containing the public API for the System
> > > > > > +Controller
> > > > > > +(SC)
> > > > > > + * Power Management (PM) function. This includes functions
> > > > > > +for power state
> > > > > > + * control, clock control, reset control, and wake-up event control.
> > > > > > + *
> > > > > > + * RM_SVC (SVC) Resource Management Service
> > > > > > + *
> > > > > > + * Module for the Resource Management (RM) service.
> > > > > > + */
> > > > > > +
> > > > > > +#ifndef _SC_RM_API_H
> > > > > > +#define _SC_RM_API_H
> > > > > > +
> > > > > > +#include <linux/firmware/imx/sci.h>
> > > > > > +
> > > > > > +/*
> > > > > > + * This type is used to indicate RPC RM function calls.
> > > > > > + */
> > > > > > +enum imx_sc_rm_func {
> > > > > > + IMX_SC_RM_FUNC_UNKNOWN = 0,
> > > > > > + IMX_SC_RM_FUNC_PARTITION_ALLOC = 1,
> > > > > > + IMX_SC_RM_FUNC_SET_CONFIDENTIAL = 31,
> > > > > > + IMX_SC_RM_FUNC_PARTITION_FREE = 2,
> > > > > > + IMX_SC_RM_FUNC_GET_DID = 26,
> > > > > > + IMX_SC_RM_FUNC_PARTITION_STATIC = 3,
> > > > > > + IMX_SC_RM_FUNC_PARTITION_LOCK = 4,
> > > > > > + IMX_SC_RM_FUNC_GET_PARTITION = 5,
> > > > > > + IMX_SC_RM_FUNC_SET_PARENT = 6,
> > > > > > + IMX_SC_RM_FUNC_MOVE_ALL = 7,
> > > > > > + IMX_SC_RM_FUNC_ASSIGN_RESOURCE = 8,
> > > > > > + IMX_SC_RM_FUNC_SET_RESOURCE_MOVABLE = 9,
> > > > > > + IMX_SC_RM_FUNC_SET_SUBSYS_RSRC_MOVABLE = 28,
> > > > > > + IMX_SC_RM_FUNC_SET_MASTER_ATTRIBUTES = 10,
> > > > > > + IMX_SC_RM_FUNC_SET_MASTER_SID = 11,
> > > > > > + IMX_SC_RM_FUNC_SET_PERIPHERAL_PERMISSIONS = 12,
> > > > > > + IMX_SC_RM_FUNC_IS_RESOURCE_OWNED = 13,
> > > > > > + IMX_SC_RM_FUNC_GET_RESOURCE_OWNER = 33,
> > > > > > + IMX_SC_RM_FUNC_IS_RESOURCE_MASTER = 14,
> > > > > > + IMX_SC_RM_FUNC_IS_RESOURCE_PERIPHERAL = 15,
> > > > > > + IMX_SC_RM_FUNC_GET_RESOURCE_INFO = 16,
> > > > > > + IMX_SC_RM_FUNC_MEMREG_ALLOC = 17,
> > > > > > + IMX_SC_RM_FUNC_MEMREG_SPLIT = 29,
> > > > > > + IMX_SC_RM_FUNC_MEMREG_FRAG = 32,
> > > > > > + IMX_SC_RM_FUNC_MEMREG_FREE = 18,
> > > > > > + IMX_SC_RM_FUNC_FIND_MEMREG = 30,
> > > > > > + IMX_SC_RM_FUNC_ASSIGN_MEMREG = 19,
> > > > > > + IMX_SC_RM_FUNC_SET_MEMREG_PERMISSIONS = 20,
> > > > > > + IMX_SC_RM_FUNC_IS_MEMREG_OWNED = 21,
> > > > > > + IMX_SC_RM_FUNC_GET_MEMREG_INFO = 22,
> > > > > > + IMX_SC_RM_FUNC_ASSIGN_PAD = 23,
> > > > > > + IMX_SC_RM_FUNC_SET_PAD_MOVABLE = 24,
> > > > > > + IMX_SC_RM_FUNC_IS_PAD_OWNED = 25,
> > > > > > + IMX_SC_RM_FUNC_DUMP = 27,
> > > > > > +};
> > > > > > +
> > > > > > +#if IS_ENABLED(CONFIG_IMX_SCU) bool
> > > > > > +imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16
> > > > > > +resource); #else static inline bool
> > > > > > +imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16
> resource) {
> > > > > > + return true;
> > > > > > +}
> > > > > > +#endif
> > > > > > +#endif
> > > > > > --
> > > > > > 2.16.4
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* Re: [PATCH v4 18/26] arm64: mte: Add PTRACE_{PEEK,POKE}MTETAGS support
From: Catalin Marinas @ 2020-06-01 12:07 UTC (permalink / raw)
To: Luis Machado
Cc: linux-arch, Omair Javaid, Szabolcs Nagy, Andrey Konovalov,
Kevin Brodsky, Peter Collingbourne, linux-mm, Alan Hayward,
Vincenzo Frascino, Will Deacon, Dave P Martin, linux-arm-kernel
In-Reply-To: <a6fb329c-b4ad-9ffa-5344-601348978c34@linaro.org>
On Fri, May 29, 2020 at 06:25:14PM -0300, Luis Machado wrote:
> I have a question about siginfo MTE information. I suppose SEGV_MTESERR will
> be the most useful setting for debugging, right? Does si_addr contain the
> tagged pointer with the logical tag, a zero-tagged memory address or a
> tagged pointer with the allocation tag?
The si_addr is zero-tagged currently. We were planning to expose the tag
in FAR_EL1 as a separate siginfo field. See these discussions:
https://lore.kernel.org/linux-arm-kernel/20200513180914.50892-1-pcc@google.com/
https://lore.kernel.org/linux-arm-kernel/20200521022943.195898-1-pcc@google.com/
In theory, we could add the tag to si_addr for SEGV_MTESERR, it
shouldn't break the existing ABI (well, it depends on how you look at
it).
> From the debugger user's perspective, one would want to see both the logical
> tag and the allocation tag. And it would be handy to have both available in
> siginfo. Does that make sense?
The debugger can access the allocation tag via PTRACE_PEEKMTETAGS. I
don't think the kernel should provide this in siginfo. Also, the signal
handler can do an LDG and read the allocation tag directly, no need for
it to be in siginfo.
> Also, when would we see SEGV_MTEAERR, for example? That would provide no
> additional information about a particular memory address, which is not that
> useful for the debugger.
Yeah, we can't really do much here since the hardware doesn't provide us
such information. The async mode is only useful as a general test to see
if your program has MTE faults but for actual debugging you'd have to
switch to synchronous. For glibc at least, I think the mode can be
driven by an environment variable.
--
Catalin
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