* Re: [PATCH] dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
From: Lee Jones @ 2023-01-25 15:08 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, David Airlie, Daniel Vetter,
Bartosz Golaszewski, Jean Delvare, Guenter Roeck, Thomas Gleixner,
Marc Zyngier, Jassi Brar, Mauro Carvalho Chehab, Ulf Hansson,
Richard Weinberger, Vignesh Raghavendra, Sebastian Reichel,
Mark Brown, Rafael J. Wysocki, Daniel Lezcano, Greg Kroah-Hartman,
linux-arm-kernel, dri-devel, linux-gpio, linux-hwmon, linux-media,
openbmc, linux-mmc, linux-mtd, linux-pm, alsa-devel, linux-spi,
linux-usb
In-Reply-To: <20230124230228.372305-1-robh@kernel.org>
On Tue, 24 Jan 2023, Rob Herring wrote:
> Just as unevaluatedProperties or additionalProperties are required at
> the top level of schemas, they should (and will) also be required for
> child node schemas. That ensures only documented properties are
> present.
>
> Add unevaluatedProperties or additionalProperties as appropriate, and
> then add any missing properties flagged by the addition.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> To: David Airlie <airlied@gmail.com>
> To: Daniel Vetter <daniel@ffwll.ch>
> To: Bartosz Golaszewski <brgl@bgdev.pl>
> To: Jean Delvare <jdelvare@suse.com>
> To: Guenter Roeck <linux@roeck-us.net>
> To: Thomas Gleixner <tglx@linutronix.de>
> To: Marc Zyngier <maz@kernel.org>
> To: Jassi Brar <jassisinghbrar@gmail.com>
> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> To: Lee Jones <lee@kernel.org>
> To: Ulf Hansson <ulf.hansson@linaro.org>
> To: Richard Weinberger <richard@nod.at>
> To: Vignesh Raghavendra <vigneshr@ti.com>
> To: Sebastian Reichel <sre@kernel.org>
> To: Mark Brown <broonie@kernel.org>
> To: "Rafael J. Wysocki" <rafael@kernel.org>
> To: Daniel Lezcano <daniel.lezcano@linaro.org>
> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-gpio@vger.kernel.org
> Cc: linux-hwmon@vger.kernel.org
> Cc: linux-media@vger.kernel.org
> Cc: openbmc@lists.ozlabs.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-mtd@lists.infradead.org
> Cc: linux-pm@vger.kernel.org
> Cc: alsa-devel@alsa-project.org
> Cc: linux-spi@vger.kernel.org
> Cc: linux-usb@vger.kernel.org
> ---
> .../devicetree/bindings/arm/arm,vexpress-juno.yaml | 1 +
> .../bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml | 5 +++--
> .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 4 ++++
> .../bindings/bus/allwinner,sun50i-a64-de2.yaml | 1 +
> .../bindings/bus/allwinner,sun8i-a23-rsb.yaml | 1 +
> .../bus/intel,ixp4xx-expansion-bus-controller.yaml | 6 ++++++
> Documentation/devicetree/bindings/bus/palmbus.yaml | 1 +
> .../devicetree/bindings/display/msm/qcom,mdss.yaml | 5 +++++
> Documentation/devicetree/bindings/example-schema.yaml | 2 ++
> .../devicetree/bindings/gpio/x-powers,axp209-gpio.yaml | 1 +
> .../devicetree/bindings/hwmon/adi,ltc2992.yaml | 1 +
> .../bindings/interrupt-controller/arm,gic-v3.yaml | 2 ++
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 1 +
> .../devicetree/bindings/media/i2c/maxim,max9286.yaml | 7 +++++++
> .../bindings/memory-controllers/arm,pl35x-smc.yaml | 1 +
> .../bindings/memory-controllers/exynos-srom.yaml | 1 +
> .../memory-controllers/nvidia,tegra124-emc.yaml | 1 +
> .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 1 +
> .../devicetree/bindings/mfd/mediatek,mt6370.yaml | 2 ++
> .../devicetree/bindings/mmc/aspeed,sdhci.yaml | 1 +
> Documentation/devicetree/bindings/mtd/mtd.yaml | 1 +
> .../devicetree/bindings/power/supply/ti,lp8727.yaml | 1 +
> .../devicetree/bindings/soc/imx/fsl,imx93-src.yaml | 3 ++-
> .../bindings/soc/microchip/atmel,at91rm9200-tcb.yaml | 1 +
> Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 1 +
> .../devicetree/bindings/sound/marvell,mmp-sspa.yaml | 1 +
> .../devicetree/bindings/sound/qcom,wcd934x.yaml | 1 +
> .../devicetree/bindings/sound/samsung,odroid.yaml | 2 ++
> .../devicetree/bindings/soundwire/qcom,soundwire.yaml | 1 +
> .../bindings/spi/allwinner,sun4i-a10-spi.yaml | 1 +
> .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
> .../devicetree/bindings/spi/spi-controller.yaml | 1 +
> .../sram/allwinner,sun4i-a10-system-control.yaml | 10 +++++-----
> Documentation/devicetree/bindings/sram/qcom,ocmem.yaml | 1 +
> .../devicetree/bindings/thermal/thermal-zones.yaml | 1 +
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
> 36 files changed, 65 insertions(+), 8 deletions(-)
Acked-by: Lee Jones <lee@kernel.org>
--
Lee Jones [李琼斯]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
From: Lee Jones @ 2023-01-25 15:10 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, David Airlie, Daniel Vetter,
Bartosz Golaszewski, Jean Delvare, Guenter Roeck, Thomas Gleixner,
Marc Zyngier, Jassi Brar, Mauro Carvalho Chehab, Ulf Hansson,
Richard Weinberger, Vignesh Raghavendra, Sebastian Reichel,
Mark Brown, Rafael J. Wysocki, Daniel Lezcano, Greg Kroah-Hartman,
linux-arm-kernel, dri-devel, linux-gpio, linux-hwmon, linux-media,
openbmc, linux-mmc, linux-mtd, linux-pm, alsa-devel, linux-spi,
linux-usb
In-Reply-To: <20230124230048.371144-1-robh@kernel.org>
On Tue, 24 Jan 2023, Rob Herring wrote:
> Just as unevaluatedProperties or additionalProperties are required at
> the top level of schemas, they should (and will) also be required for
> child node schemas. That ensures only documented properties are
> present.
>
> Add unevaluatedProperties or additionalProperties as appropriate, and
> then add any missing properties flagged by the addition.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> To: David Airlie <airlied@gmail.com>
> To: Daniel Vetter <daniel@ffwll.ch>
> To: Bartosz Golaszewski <brgl@bgdev.pl>
> To: Jean Delvare <jdelvare@suse.com>
> To: Guenter Roeck <linux@roeck-us.net>
> To: Thomas Gleixner <tglx@linutronix.de>
> To: Marc Zyngier <maz@kernel.org>
> To: Jassi Brar <jassisinghbrar@gmail.com>
> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> To: Lee Jones <lee@kernel.org>
> To: Ulf Hansson <ulf.hansson@linaro.org>
> To: Richard Weinberger <richard@nod.at>
> To: Vignesh Raghavendra <vigneshr@ti.com>
> To: Sebastian Reichel <sre@kernel.org>
> To: Mark Brown <broonie@kernel.org>
> To: "Rafael J. Wysocki" <rafael@kernel.org>
> To: Daniel Lezcano <daniel.lezcano@linaro.org>
> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-gpio@vger.kernel.org
> Cc: linux-hwmon@vger.kernel.org
> Cc: linux-media@vger.kernel.org
> Cc: openbmc@lists.ozlabs.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-mtd@lists.infradead.org
> Cc: linux-pm@vger.kernel.org
> Cc: alsa-devel@alsa-project.org
> Cc: linux-spi@vger.kernel.org
> Cc: linux-usb@vger.kernel.org
> ---
> .../devicetree/bindings/arm/arm,vexpress-juno.yaml | 1 +
> .../bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml | 5 +++--
> .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 4 ++++
> .../bindings/bus/allwinner,sun50i-a64-de2.yaml | 1 +
> .../bindings/bus/allwinner,sun8i-a23-rsb.yaml | 1 +
> .../bus/intel,ixp4xx-expansion-bus-controller.yaml | 6 ++++++
> Documentation/devicetree/bindings/bus/palmbus.yaml | 1 +
> .../devicetree/bindings/display/msm/qcom,mdss.yaml | 5 +++++
> Documentation/devicetree/bindings/example-schema.yaml | 2 ++
> .../devicetree/bindings/gpio/x-powers,axp209-gpio.yaml | 1 +
> .../devicetree/bindings/hwmon/adi,ltc2992.yaml | 1 +
> .../bindings/interrupt-controller/arm,gic-v3.yaml | 2 ++
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 1 +
> .../devicetree/bindings/media/i2c/maxim,max9286.yaml | 7 +++++++
> .../bindings/memory-controllers/arm,pl35x-smc.yaml | 1 +
> .../bindings/memory-controllers/exynos-srom.yaml | 1 +
> .../memory-controllers/nvidia,tegra124-emc.yaml | 1 +
> .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 1 +
> .../devicetree/bindings/mfd/mediatek,mt6370.yaml | 2 ++
> .../devicetree/bindings/mmc/aspeed,sdhci.yaml | 1 +
> Documentation/devicetree/bindings/mtd/mtd.yaml | 1 +
> .../devicetree/bindings/power/supply/ti,lp8727.yaml | 1 +
> .../devicetree/bindings/soc/imx/fsl,imx93-src.yaml | 3 ++-
> .../bindings/soc/microchip/atmel,at91rm9200-tcb.yaml | 1 +
> Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 1 +
> .../devicetree/bindings/sound/marvell,mmp-sspa.yaml | 1 +
> .../devicetree/bindings/sound/qcom,wcd934x.yaml | 1 +
> .../devicetree/bindings/sound/samsung,odroid.yaml | 2 ++
> .../devicetree/bindings/soundwire/qcom,soundwire.yaml | 1 +
> .../bindings/spi/allwinner,sun4i-a10-spi.yaml | 1 +
> .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
> .../devicetree/bindings/spi/spi-controller.yaml | 1 +
> .../sram/allwinner,sun4i-a10-system-control.yaml | 10 +++++-----
> Documentation/devicetree/bindings/sram/qcom,ocmem.yaml | 1 +
> .../devicetree/bindings/thermal/thermal-zones.yaml | 1 +
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
> 36 files changed, 65 insertions(+), 8 deletions(-)
Is this the same as the patch I just reviewed?
--
Lee Jones [李琼斯]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v7 0/5] PWM and keyboard backlight driver for ARM Macs
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein
Hi,
This is the resend of the v7 of the patch series to add PWM and keyboard
backlight driver for ARM macs. No significant changes this time.
Changes in v1:
Addressing the review comments.
Changes in v2:
Added the reviewed-by and acked-by tags.
Addressing a review comment.
Changes in v3 and v4:
Addressing the review comments.
Changes in v5:
Added t600x device tree changes
v1: https://www.spinics.net/lists/linux-pwm/msg19500.html
v2: https://www.spinics.net/lists/linux-pwm/msg19562.html
v3: https://www.spinics.net/lists/linux-pwm/msg19901.html
v4: https://www.spinics.net/lists/linux-pwm/msg20093.html
v5: https://www.spinics.net/lists/linux-pwm/msg20150.html
v6: https://www.spinics.net/lists/linux-pwm/msg20190.html
Sasha Finkelstein (5):
dt-bindings: pwm: Add Apple PWM controller
pwm: Add Apple PWM controller
arm64: dts: apple: t8103: Add PWM controller
arm64: dts: apple: t600x: Add PWM controller
MAINTAINERS: Add entries for Apple PWM driver
.../bindings/pwm/apple,s5l-fpwm.yaml | 51 ++++++
MAINTAINERS | 2 +
arch/arm64/boot/dts/apple/t600x-die0.dtsi | 9 +
.../arm64/boot/dts/apple/t600x-j314-j316.dtsi | 18 ++
arch/arm64/boot/dts/apple/t8103-j293.dts | 17 ++
arch/arm64/boot/dts/apple/t8103-j313.dts | 17 ++
arch/arm64/boot/dts/apple/t8103.dtsi | 9 +
drivers/pwm/Kconfig | 12 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-apple.c | 159 ++++++++++++++++++
10 files changed, 295 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
create mode 100644 drivers/pwm/pwm-apple.c
--
2.37.1 (Apple Git-137.1)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v7 1/5] dt-bindings: pwm: Add Apple PWM controller
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein, Krzysztof Kozlowski
In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com>
Apple SoCs such as the M1 contain a PWM controller used
among other things to control the keyboard backlight.
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sven Peter <sven@svenpeter.dev>
---
.../bindings/pwm/apple,s5l-fpwm.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
new file mode 100644
index 000000000000..142157bff0cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/apple,s5l-fpwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple FPWM controller
+
+maintainers:
+ - asahi@lists.linux.dev
+ - Sasha Finkelstein <fnkl.kernel@gmail.com>
+
+description: PWM controller used for keyboard backlight on ARM Macs
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apple,t8103-fpwm
+ - apple,t6000-fpwm
+ - apple,t8112-fpwm
+ - const: apple,s5l-fpwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm@235044000 {
+ compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
+ reg = <0x35044000 0x4000>;
+ power-domains = <&ps_fpwm1>;
+ clocks = <&clkref>;
+ #pwm-cells = <2>;
+ };
--
2.37.1 (Apple Git-137.1)
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v7 2/5] pwm: Add Apple PWM controller
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein
In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com>
Adds the Apple PWM controller driver.
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Acked-by: Sven Peter <sven@svenpeter.dev>
---
drivers/pwm/Kconfig | 12 +++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-apple.c | 159 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 172 insertions(+)
create mode 100644 drivers/pwm/pwm-apple.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index dae023d783a2..8df861b1f4a3 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -51,6 +51,18 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_APPLE
+ tristate "Apple SoC PWM support"
+ depends on ARCH_APPLE || COMPILE_TEST
+ help
+ Generic PWM framework driver for PWM controller present on
+ Apple SoCs
+
+ Say Y here if you have an ARM Apple laptop, otherwise say N
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-apple.
+
config PWM_ATMEL
tristate "Atmel PWM support"
depends on ARCH_AT91 || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 7bf1a29f02b8..19899b912e00 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
diff --git a/drivers/pwm/pwm-apple.c b/drivers/pwm/pwm-apple.c
new file mode 100644
index 000000000000..551e07d49bf7
--- /dev/null
+++ b/drivers/pwm/pwm-apple.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Driver for the Apple SoC PWM controller
+ *
+ * Copyright The Asahi Linux Contributors
+ *
+ * Limitations:
+ * - The writes to cycle registers are shadowed until a write to
+ * the control register.
+ * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
+ * is a constant off signal.
+ * - When APPLE_PWM_CTRL is set to 0, the output is constant low
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/math64.h>
+
+#define APPLE_PWM_CTRL 0x00
+#define APPLE_PWM_ON_CYCLES 0x1c
+#define APPLE_PWM_OFF_CYCLES 0x18
+
+#define APPLE_PWM_CTRL_ENABLE BIT(0)
+#define APPLE_PWM_CTRL_MODE BIT(2)
+#define APPLE_PWM_CTRL_UPDATE BIT(5)
+#define APPLE_PWM_CTRL_TRIGGER BIT(9)
+#define APPLE_PWM_CTRL_INVERT BIT(10)
+#define APPLE_PWM_CTRL_OUTPUT_ENABLE BIT(14)
+
+struct apple_pwm {
+ struct pwm_chip chip;
+ void __iomem *base;
+ u64 clkrate;
+};
+
+static inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip)
+{
+ return container_of(chip, struct apple_pwm, chip);
+}
+
+static int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct apple_pwm *fpwm;
+
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ fpwm = to_apple_pwm(chip);
+ if (state->enabled) {
+ u64 on_cycles, off_cycles;
+
+ on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
+ state->duty_cycle, NSEC_PER_SEC);
+ if (on_cycles > 0xFFFFFFFF)
+ return -ERANGE;
+
+ off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
+ state->period, NSEC_PER_SEC) - on_cycles;
+ if (off_cycles > 0xFFFFFFFF)
+ return -ERANGE;
+
+ writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES);
+ writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES);
+ writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE,
+ fpwm->base + APPLE_PWM_CTRL);
+ } else {
+ writel(0, fpwm->base + APPLE_PWM_CTRL);
+ }
+ return 0;
+}
+
+static int apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct apple_pwm *fpwm;
+ u32 on_cycles, off_cycles, ctrl;
+
+ fpwm = to_apple_pwm(chip);
+
+ ctrl = readl(fpwm->base + APPLE_PWM_CTRL);
+ on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES);
+ off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES);
+
+ state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE);
+ state->polarity = PWM_POLARITY_NORMAL;
+ // on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow
+ state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
+ state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *
+ NSEC_PER_SEC, fpwm->clkrate);
+
+ return 0;
+}
+
+static const struct pwm_ops apple_pwm_ops = {
+ .apply = apple_pwm_apply,
+ .get_state = apple_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static int apple_pwm_probe(struct platform_device *pdev)
+{
+ struct apple_pwm *fpwm;
+ struct clk *clk;
+ int ret;
+
+ fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL);
+ if (!fpwm)
+ return -ENOMEM;
+
+ fpwm->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(fpwm->base))
+ return PTR_ERR(fpwm->base);
+
+ clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock");
+
+ /*
+ * Uses the 24MHz system clock on all existing devices, can only
+ * happen if the device tree is broken
+ *
+ * This check is done to prevent an overflow in .apply
+ */
+ fpwm->clkrate = clk_get_rate(clk);
+ if (fpwm->clkrate > NSEC_PER_SEC)
+ return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range");
+
+ fpwm->chip.dev = &pdev->dev;
+ fpwm->chip.npwm = 1;
+ fpwm->chip.ops = &apple_pwm_ops;
+
+ ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip");
+
+ return 0;
+}
+
+static const struct of_device_id apple_pwm_of_match[] = {
+ { .compatible = "apple,s5l-fpwm" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, apple_pwm_of_match);
+
+static struct platform_driver apple_pwm_driver = {
+ .probe = apple_pwm_probe,
+ .driver = {
+ .name = "apple-pwm",
+ .of_match_table = apple_pwm_of_match,
+ },
+};
+module_platform_driver(apple_pwm_driver);
+
+MODULE_DESCRIPTION("Apple SoC PWM driver");
+MODULE_LICENSE("Dual MIT/GPL");
--
2.37.1 (Apple Git-137.1)
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^ permalink raw reply related
* [PATCH v7 3/5] arm64: dts: apple: t8103: Add PWM controller
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein
In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com>
Adds PWM controller and keyboard backlight bindings for M1 MacBooks
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Acked-by: Sven Peter <sven@svenpeter.dev>
---
arch/arm64/boot/dts/apple/t8103-j293.dts | 17 +++++++++++++++++
arch/arm64/boot/dts/apple/t8103-j313.dts | 17 +++++++++++++++++
arch/arm64/boot/dts/apple/t8103.dtsi | 9 +++++++++
3 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts
index 151074109a11..7381dccc1613 100644
--- a/arch/arm64/boot/dts/apple/t8103-j293.dts
+++ b/arch/arm64/boot/dts/apple/t8103-j293.dts
@@ -11,10 +11,23 @@
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
+#include <dt-bindings/leds/common.h>
/ {
compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Pro (13-inch, M1, 2020)";
+
+ led-controller {
+ compatible = "pwm-leds";
+ led-0 {
+ pwms = <&fpwm1 0 40000>;
+ label = "kbd_backlight";
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <255>;
+ default-state = "keep";
+ };
+ };
};
&bluetooth0 {
@@ -47,3 +60,7 @@ &i2c2 {
&i2c4 {
status = "okay";
};
+
+&fpwm1 {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts
index bc1f865aa790..1e26aa1ef525 100644
--- a/arch/arm64/boot/dts/apple/t8103-j313.dts
+++ b/arch/arm64/boot/dts/apple/t8103-j313.dts
@@ -11,10 +11,23 @@
#include "t8103.dtsi"
#include "t8103-jxxx.dtsi"
+#include <dt-bindings/leds/common.h>
/ {
compatible = "apple,j313", "apple,t8103", "apple,arm-platform";
model = "Apple MacBook Air (M1, 2020)";
+
+ led-controller {
+ compatible = "pwm-leds";
+ led-0 {
+ pwms = <&fpwm1 0 40000>;
+ label = "kbd_backlight";
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <255>;
+ default-state = "keep";
+ };
+ };
};
&bluetooth0 {
@@ -39,3 +52,7 @@ &pcie0_dart_2 {
/delete-node/ &port01;
/delete-node/ &port02;
+
+&fpwm1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 9859219699f4..5300fd115561 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -432,6 +432,15 @@ i2c4: i2c@235020000 {
status = "disabled"; /* only used in J293 */
};
+ fpwm1: pwm@235044000 {
+ compatible = "apple,t8103-fpwm", "apple,s5l-fpwm";
+ reg = <0x2 0x35044000 0x0 0x4000>;
+ power-domains = <&ps_fpwm1>;
+ clocks = <&clkref>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
serial0: serial@235200000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x35200000 0x0 0x1000>;
--
2.37.1 (Apple Git-137.1)
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^ permalink raw reply related
* [PATCH v7 4/5] arm64: dts: apple: t600x: Add PWM controller
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein, Sasha Finkelstein
In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com>
From: Sasha Finkelstein <7d578vix8hzw@opayq.net>
Adds PWM controller and keyboard backlight bindings for M1 Pro/Max MacBook Pros
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Acked-by: Hector Martin <marcan@marcan.st>
---
arch/arm64/boot/dts/apple/t600x-die0.dtsi | 9 +++++++++
arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 18 ++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
index 1c41954e3899..9157ae2a9f7f 100644
--- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
@@ -71,6 +71,15 @@ sio_dart_1: iommu@39b008000 {
power-domains = <&ps_sio_cpu>;
};
+ fpwm0: pwm@39b030000 {
+ compatible = "apple,t6000-fpwm", "apple,s5l-fpwm";
+ reg = <0x3 0x9b030000 0x0 0x4000>;
+ power-domains = <&ps_fpwm0>;
+ clocks = <&clkref>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
i2c0: i2c@39b040000 {
compatible = "apple,t6000-i2c", "apple,i2c";
reg = <0x3 0x9b040000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
index 34906d522f0a..96de7165df6d 100644
--- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
@@ -9,6 +9,8 @@
* Copyright The Asahi Linux Contributors
*/
+#include <dt-bindings/leds/common.h>
+
/ {
aliases {
serial0 = &serial0;
@@ -34,6 +36,18 @@ memory@10000000000 {
device_type = "memory";
reg = <0x100 0 0x2 0>; /* To be filled by loader */
};
+
+ led-controller {
+ compatible = "pwm-leds";
+ led-0 {
+ pwms = <&fpwm0 0 40000>;
+ label = "kbd_backlight";
+ function = LED_FUNCTION_KBD_BACKLIGHT;
+ color = <LED_COLOR_ID_WHITE>;
+ max-brightness = <255>;
+ default-state = "keep";
+ };
+ };
};
&serial0 {
@@ -110,5 +124,9 @@ &pcie0_dart_3 {
status = "disabled";
};
+&fpwm0 {
+ status = "okay";
+};
+
/delete-node/ &port02;
/delete-node/ &port03;
--
2.37.1 (Apple Git-137.1)
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^ permalink raw reply related
* [PATCH v7 5/5] MAINTAINERS: Add entries for Apple PWM driver
From: Sasha Finkelstein @ 2023-01-25 15:10 UTC (permalink / raw)
To: u.kleine-koenig, thierry.reding, robh+dt, krzysztof.kozlowski+dt
Cc: marcan, sven, alyssa, asahi, linux-arm-kernel, linux-pwm,
devicetree, linux-kernel, Sasha Finkelstein
In-Reply-To: <20230125151041.55483-1-fnkl.kernel@gmail.com>
Add the MAINTAINERS entries for the driver
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Acked-by: Sven Peter <sven@svenpeter.dev>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f86d02cb427..75bda5ab704d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1970,6 +1970,7 @@ F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml
F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
F: Documentation/devicetree/bindings/power/apple*
+F: Documentation/devicetree/bindings/pwm/pwm-apple.yaml
F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
F: arch/arm64/boot/dts/apple/
F: drivers/bluetooth/hci_bcm4377.c
@@ -1985,6 +1986,7 @@ F: drivers/mailbox/apple-mailbox.c
F: drivers/nvme/host/apple.c
F: drivers/nvmem/apple-efuses.c
F: drivers/pinctrl/pinctrl-apple-gpio.c
+F: drivers/pwm/pwm-apple.c
F: drivers/soc/apple/*
F: drivers/watchdog/apple_wdt.c
F: include/dt-bindings/interrupt-controller/apple-aic.h
--
2.37.1 (Apple Git-137.1)
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^ permalink raw reply related
* Re: [PATCH v11 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes
From: Balsam CHIHI @ 2023-01-25 15:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: daniel.lezcano, rafael, amitk, rui.zhang, matthias.bgg, robh+dt,
krzysztof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel, linux-pm,
linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
khilman, james.lo, rex-bc.chen
In-Reply-To: <80ce4ea3-6ebd-c249-45bd-a2f04343690b@collabora.com>
On Tue, Jan 24, 2023 at 4:37 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 24/01/23 14:17, bchihi@baylibre.com ha scritto:
> > From: Balsam CHIHI <bchihi@baylibre.com>
> >
> > Add thermal zones and thermal nodes for the mt8195.
> >
> > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
>
> You should change the commit title to reflect the same syntax that you can find
> in a `git log --oneline arch/arm64/boot/dts/mediatek/`.
>
> arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes
>
> or
>
> arm64: dts: mt8195: Add thermal zones and thermal nodes
>
Hi Angelo,
Thank you for the review.
Should I resend with the fix?
Or you would fix it when applying it like Matthias did for "[PATCH v11
3/6] arm64/dts/mt8195: Add efuse node to mt8195"?
Best regards,
Balsam
>
> ...otherwise:
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
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^ permalink raw reply
* Re: [V1,0/2] Add jpeg enc & dec device node for MT8195
From: Matthias Brugger @ 2023-01-25 15:22 UTC (permalink / raw)
To: Irui Wang, Hans Verkuil, Rob Herring, Krzysztof Kozlowski,
Mauro Carvalho Chehab, angelogioacchino.delregno,
nicolas.dufresne, kyrie wu
Cc: Project_Global_Chrome_Upstream_Group, devicetree, linux-media,
linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
xia.jiang, maoguang.meng
In-Reply-To: <20230112084503.4277-1-irui.wang@mediatek.com>
Applied, thanks!
On 12/01/2023 09:45, Irui Wang wrote:
> From: kyrie wu <kyrie.wu@mediatek.com>
>
> This series add jpeg enc and dec device node to dts file
> for the purpose of supporting multi hardwares jpeg
> enc & dec of MT8195.
>
> This series has been tested with MT8195 Gstreamer.
> Encoding and decoding worked for this chip.
>
> Patches 1 Adds jpeg encoder device node for mt8195.
>
> Patches 2 Adds jpeg decoder device node for mt8195.
>
> kyrie wu (2):
> arm64: dts: mt8195: add jpeg encode device node
> arm64: dts: mt8195: add jpeg decode device node
>
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 100 +++++++++++++++++++++++
> 1 file changed, 100 insertions(+)
>
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^ permalink raw reply
* Re: [PATCH v4 6/6] arch_topology: Build cacheinfo from primary CPU
From: Geert Uytterhoeven @ 2023-01-25 15:28 UTC (permalink / raw)
To: Sudeep Holla
Cc: Conor Dooley, Pierre Gondois, linux-kernel, Palmer Dabbelt,
Catalin Marinas, Will Deacon, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Rafael J. Wysocki, Len Brown, Greg Kroah-Hartman,
Gavin Shan, linux-arm-kernel, linux-riscv, linux-acpi
In-Reply-To: <20230125145423.pid3hsstswzuez73@bogus>
Hi Sudeep,
On Wed, Jan 25, 2023 at 3:54 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
> On Tue, Jan 24, 2023 at 02:55:41PM +0000, Sudeep Holla wrote:
> > Geert, can you please try with the patch Conor pointed out and see if
> > that helps to fix the allocation failures[1]
> >
>
> Sorry for the nag, but did you get the chance to test -next with [1]
> and see if it fixes the cacheinfo memory failure you were observing ?
> [1] https://lore.kernel.org/all/20230103035316.3841303-1-leyfoon.tan@starfivetech.com/
After applying that patch, the issue is gone.
Thanks, sending my Tb!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH] dt-bindings: firmware: arm,scmi: Restrict protocol child node properties
From: Cristian Marussi @ 2023-01-25 15:40 UTC (permalink / raw)
To: Sudeep Holla
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-kernel, devicetree,
linux-kernel
In-Reply-To: <20230125141113.kkbowopusikuogx6@bogus>
On Wed, Jan 25, 2023 at 02:11:13PM +0000, Sudeep Holla wrote:
> On Wed, Jan 25, 2023 at 01:43:48PM +0000, Cristian Marussi wrote:
> > so now that the catch-all protocol@ patternProperty is gone in favour
> > of the 'protocol-node' definition and $refs, does that mean that any
> > current and future SCMI officially published protocol <N> has to be
> > added to the above explicit protocol list, even though it does not
> > have any special additional required property beside reg ?
> > (like protocol@18 above...)
> >
>
> If there are no consumers, should we just not add and deal with it
> entirely within the kernel. I know we rely today on presence of node
> before we initialise, but hey we have exception for system power protocol
> for other reasons, why not add this one too.
>
> In short we shouldn't have to add a node if there are no consumers. It
> was one of the topic of discussion initially when SCMI binding was added
> and they exist only for the consumers otherwise we don't need it as
> everything is discoverable from the interface.
>
I'm fine with that, just wanted to understand/clarify the rule here.
Thanks,
Cristian
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^ permalink raw reply
* Re: [PATCH 04/10] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
From: Kathiravan Thirumoorthy @ 2023-01-25 15:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <ccddc46f-b007-4e0c-9c1f-df2c13d459eb@linaro.org>
On 1/25/2023 4:43 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
> Thank you for your patch. There is something to discuss/improve.
Thanks for taking time to review the patch.
>
>> + clocks:
>> + items:
>> + - description: Board XO clock source
>> + - description: Sleep clock source
>> + - description: PCIE 2lane PHY pipe clock source
>> + - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
>> + - description: USB PCIE wrapper pipe clock source
>> +
>> + clock-names:
>> + items:
>> + - const: xo
>> + - const: sleep_clk
>> + - const: pcie_2lane_phy_pipe_clk
>> + - const: pcie_2lane_phy_pipe_clk_x1
>> + - const: usb_pcie_wrapper_pipe_clk
>> +
>> +required:
>> + - compatible
> clocks are required
Ack.
>
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + clock-controller@1800000 {
>> + compatible = "qcom,ipq5332-gcc";
>> + reg = <0x01800000 0x80000>;
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5332.h b/include/dt-bindings/clock/qcom,gcc-ipq5332.h
>> new file mode 100644
>> index 000000000000..a305c648b724
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gcc-ipq5332.h
> Filename should match bindings/compatible.
Ack.
>
>
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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* Re: [PATCH 01/10] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
From: Kathiravan Thirumoorthy @ 2023-01-25 15:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <50ec54ba-3468-3448-3fab-f28e97549ad2@linaro.org>
On 1/25/2023 4:40 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Add device tree bindings for IPQ5332 TLMM block.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> .../pinctrl/qcom,ipq5332-pinctrl.yaml | 134 ++++++++++++++++++
>> 1 file changed, 134 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..d101ee04b8b7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml
> Name matching compatible, please.
Sure, will rename it accordingly.
>
>> @@ -0,0 +1,134 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm IPQ5332 TLMM pin controller
>> +
>> +maintainers:
>> + - Bjorn Andersson <andersson@kernel.org>
>> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> +
>> +description: |
>> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
>> +
>> +allOf:
>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,ipq5332-tlmm
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts: true
> missing maxItems
>
> Rebase your patches on latest next and use the latest bindings and
> drivers as starting point.
Changes are based on v6.2-rc1. I see the maxItems changes in
linux-next. Will update this in V2.
>> + interrupt-controller: true
>> + "#interrupt-cells": true
>> + gpio-controller: true
>> + "#gpio-cells": true
>> + gpio-ranges: true
>> + wakeup-parent: true
>> +
>> + gpio-reserved-ranges:
>> + minItems: 1
>> + maxItems: 27
>> +
>> + gpio-line-names:
>> + maxItems: 53
> You have 54 GPIOs.
Sorry, GPIO ranges are from 0-52, will update it in all places in V2.
>
>> +
>> +patternProperties:
>> + "-state$":
>> + oneOf:
>> + - $ref: "#/$defs/qcom-ipq5332-tlmm-state"
>> + - patternProperties:
>> + "-pins$":
>> + $ref: "#/$defs/qcom-ipq5332-tlmm-state"
>> + additionalProperties: false
>> +
>> +$defs:
>> + qcom-ipq5332-tlmm-state:
>> + type: object
>> + description:
>> + Pinctrl node's client devices use subnodes for desired pin configuration.
>> + Client device subnodes use below standard properties.
>> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
>> +
>> + properties:
>> + pins:
>> + description:
>> + List of gpio pins affected by the properties specified in this
>> + subnode.
>> + items:
>> + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
>> + minItems: 1
>> + maxItems: 36
>> +
>> + function:
>> + description:
>> + Specify the alternative function to be configured for the specified
>> + pins.
>> +
>> + enum: [ PTA_0, PTA_2, PTA_1, atest_char, atest_char0, atest_char1,
> 1. lowercase only
>
> 2. order all these by name
Ack.
>
>
>> + atest_char2, atest_char3, atest_tic, audio_pri, audio_pri0,
>> + audio_pri1, audio_sec, audio_sec0, audio_sec1, blsp0_i2c,
>> + blsp0_spi, blsp0_uart0, blsp0_uart1, blsp1_i2c0, blsp1_i2c1,
>> + blsp1_spi0, blsp1_spi1, blsp1_uart0, blsp1_uart1, blsp1_uart2,
>> + blsp2_i2c0, blsp2_i2c1, blsp2_spi, blsp2_spi0, blsp2_spi1,
>> + core_voltage, cri_trng0, cri_trng1, cri_trng2, cri_trng3,
>> + cxc_clk, cxc_data, dbg_out, gcc_plltest, gcc_tlmm, gpio,
>> + lock_det, mac0, mac1, mdc0, mdc1, mdio0, mdio1, pc, pcie0_clk,
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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^ permalink raw reply
* Re: [PATCH 05/10] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
From: Kathiravan Thirumoorthy @ 2023-01-25 15:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <4dc231f5-fad4-6093-851d-afcc0f68e045@linaro.org>
On 1/25/2023 4:44 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Add support for the global clock controller found on IPQ5332 SoC.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> drivers/clk/qcom/Kconfig | 7 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-ipq5332.c | 3954 ++++++++++++++++++++++++++++++++
>> 3 files changed, 3962 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 70d43f0a8919..1d300c89ecfc 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -141,6 +141,13 @@ config IPQ_GCC_4019
>> Say Y if you want to use peripheral devices such as UART, SPI,
>> i2c, USB, SD/eMMC, etc.
>>
>> +config IPQ_GCC_5332
>> + tristate "IPQ5332 Global Clock Controller"
> depends on ARM64 || COMPILE_TEST
Ack.
>
>
>
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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^ permalink raw reply
* Re: [PATCH 06/10] dt-bindings: qcom: add ipq5332 boards
From: Kathiravan Thirumoorthy @ 2023-01-25 15:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <2c04c2f8-801e-37d3-f705-7a5953265a9d@linaro.org>
On 1/25/2023 4:45 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Document the new ipq5332 SoC/board device tree bindings
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 27063a045bd0..a3568c7d3cc9 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -30,6 +30,7 @@ description: |
>> apq8084
>> apq8096
>> ipq4018
>> + ipq5332
>> ipq6018
>> ipq8074
>> mdm9615
>> @@ -82,6 +83,7 @@ description: |
>> hk10-c2
>> idp
>> liquid
>> + mi01.2
> Is "01.2" board version or name of board?
It is the name of the board, not the version.
>
>
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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^ permalink raw reply
* Re: [PATCH 07/10] dt-bindings: firmware: document IPQ5332 SCM
From: Kathiravan Thirumoorthy @ 2023-01-25 15:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <455eb061-ed59-2783-b8d6-7276e7103d3f@linaro.org>
On 1/25/2023 4:46 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Document the compatible for IPQ5332 SCM.
> Subject:
> dt-bindings: firmware: qcom,scm:
Thanks for the review, will fix it in V2.
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
>
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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^ permalink raw reply
* [PATCH] pwm: imx27: fix race condition .apply,.get_state
From: Leif Middelschulte @ 2023-01-25 16:01 UTC (permalink / raw)
To: Thierry Reding, Uwe Kleine-König, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: Leif Middelschulte, linux-pwm, linux-arm-kernel, linux-kernel
From: Leif Middelschulte <Leif.Middelschulte@klsmartin.com>
A race condition might occur, ultimately leading to switching off the
PWM that is supposed to be turned on.
The condition is more likely, if `CONFIG_PWM_DEBUG` is set and the PWM
has been enabled before Linux is booted.
After writing some value to the register linked to the duty cycle
(`MX3_PWMSAR`), the related debug function
(`core.c:pwm_apply_state_debug`) reads back (`.get_state`)
a wrong value (`0`) as the configured duty cycle. This value is stored
as part of a temporary state variable that it subsequently reapplies
to the PWM for testing purposes. Which, effectively, turns off the PWM.
This patch postpones the return of the `.apply` function until either
the written value can be read back as expected or the operation times
out.
Signed-off-by: Leif Middelschulte <Leif.Middelschulte@klsmartin.com>
---
drivers/pwm/pwm-imx27.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c
index 29a3089c534c..9b473fe10cb9 100644
--- a/drivers/pwm/pwm-imx27.c
+++ b/drivers/pwm/pwm-imx27.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -223,7 +224,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
unsigned long long c;
unsigned long long clkrate;
int ret;
- u32 cr;
+ u32 cr, val;
pwm_get_state(pwm, &cstate);
@@ -290,6 +291,18 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (!state->enabled)
pwm_imx27_clk_disable_unprepare(imx);
+ /*
+ * According to imx pwm RM the value can be:
+ * - written at any time
+ * - only be read, if the pwm is enabled
+ * Yet it returns a wrong value (i.e. within `pwm_imx27_get_state`) if it is subsequently read (while enabled).
+ * Apparently it takes the value some cycles to propagate.
+ * Wait a bit to make sure the right value can be read by other functions, before returning.
+ */
+ ret = readl_relaxed_poll_timeout(imx->mmio_base + MX3_PWMSAR, val, val == duty_cycles, 20000, 300000);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.39.1
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^ permalink raw reply related
* Re: [RESEND PATCH v11 13/18] drm: exynos: dsi: Add Exynos based host irq hooks
From: Jagan Teki @ 2023-01-25 16:02 UTC (permalink / raw)
To: Marek Vasut
Cc: Andrzej Hajda, Inki Dae, Marek Szyprowski, Joonyoung Shim,
Seung-Woo Kim, Kyungmin Park, Frieder Schrempf, Fancy Fang,
Tim Harvey, Michael Nazzareno Trimarchi, Adam Ford,
Neil Armstrong, Robert Foss, Laurent Pinchart, Tommaso Merciai,
Matteo Lisi, dri-devel, linux-samsung-soc, linux-arm-kernel,
NXP Linux Team, linux-amarula
In-Reply-To: <fb7dfb89-42d6-139e-7ff1-4985838e222f@denx.de>
On Wed, Jan 25, 2023 at 2:42 AM Marek Vasut <marex@denx.de> wrote:
>
> On 1/24/23 22:01, Jagan Teki wrote:
> > On Wed, Jan 25, 2023 at 2:18 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 1/23/23 16:12, Jagan Teki wrote:
> >>> Enable and disable of te_gpio's are Exynos platform specific
> >>> irq handling, so add the exynos based irq operations and hook
> >>> them for exynos plat_data.
> >>
> >> If this is just an optional generic GPIO IRQ, why not keep it in the
> >> core code ? TE (tearing enable?) should be available on MX8M too.
> >
> > So far the discussion (since from initial versions) with Marek
> > Szyprowski, seems to be available in Exynos. So, I keep it separate
> > from the DSIM core.
>
> Isn't TE a generic GPIO IRQ ? If so, it is available also on i.MX8M .
I didn't find this in the DSIM part in i.MX8M Manual nor in the i.MX
8/RT MIPI DSI/CSI-2 or bsp kernel [1], did you find anywhere in i.MX8M
part? Look like TE GPIO means tearing effect signal handle on the
panel side.
from, Documentation/devicetree/bindings/display/panel/panel-common.yaml
te-gpios:
maxItems: 1
description:
GPIO spec for the tearing effect synchronization signal.
The tearing effect signal is active high. Active low signals can be
supported by inverting the GPIO specifier polarity flag.
Maybe Exynos hack this gpio on the host side instead of on the panel
side for some reason, not sure about it - Marek Szypeowski any
comments please?
[1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0
Thanks,
Jagan.
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* Re: [PATCH 09/10] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
From: Kathiravan Thirumoorthy @ 2023-01-25 16:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <35bb0017-7ffc-d128-17be-4b9c14aace26@linaro.org>
On 1/25/2023 4:52 PM, Krzysztof Kozlowski wrote:
> On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> Add initial device tree support for the Qualcomm IPQ5332 SoC and
>> MI01.2 board.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 71 +++++
>> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 273 ++++++++++++++++++++
>> 3 files changed, 345 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..fbd5bc583a9b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
>> new file mode 100644
>> index 000000000000..7984d8f824ce
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
>> @@ -0,0 +1,71 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> A bit odd license (accepting GPLv3...), especially that DTSI is only
> BSD. Was it really intended?
No, it is not intentional. Will change it to BSD-3-Clause in V2.
>
>> +/*
>> + * IPQ5332 AP-MI01.2 board device tree source
>> + *
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq5332.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ5332/AP-MI01.2";
> Just to be clear - you indicated in bindings that "AP" is the foundry
> ID. This is correct, right? Then I am not sure if it should be in model
> name.
Okay, will change the model to "Qualcomm Technologies, Inc. IPQ5332
MI01.2". I see all other IPQ DTS carries the same naming convention. May
be those also should be fixed.
>
>> + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
>> +
>> + aliases {
>> + serial0 = &blsp1_uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> + };
>> +};
>> +
>> +&blsp1_uart0 {
>> + pinctrl-0 = <&serial_0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&sdhc {
>> + pinctrl-0 = <&sdc_default_state>;
>> + pinctrl-names = "default";
>> + non-removable;
>> + status = "okay";
>> +};
>> +
>> +&sleep_clk {
>> + clock-frequency = <32000>;
>> +};
>> +
>> +&xo_board {
>> + clock-frequency = <24000000>;
>> +};
>> +
>> +/* PINCTRL */
>> +
>> +&tlmm {
>> + sdc_default_state: sdc-default-state {
>> + clk-pins {
>> + pins = "gpio13";
>> + function = "sdc_clk";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> +
>> + cmd-pins {
>> + pins = "gpio12";
>> + function = "sdc_cmd";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> +
>> + data-pins {
>> + pins = "gpio8", "gpio9", "gpio10", "gpio11";
>> + function = "sdc_data";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> new file mode 100644
>> index 000000000000..d04244a3cd3a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -0,0 +1,273 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * IPQ5332 device tree source
>> + *
>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-ipq5332.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clocks {
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + xo_board: xo-board-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + CPU1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x1>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + CPU2: cpu@2 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x2>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + CPU3: cpu@3 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x3>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + };
>> +
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <0x2>;
> This is just "2", not hex.
Ack.
>
>> + };
>> + };
>> +
>> + firmware {
>> + scm {
>> + compatible = "qcom,scm-ipq5332", "qcom,scm";
>> + };
>> + };
>> +
>> + memory@40000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0x40000000 0x0 0x0>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a53-pmu";
>> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + tz: memory@4a600000 {
>> + no-map;
>> + reg = <0x0 0x4a600000 0x0 0x200000>;
>> + };
>> + };
>> +
>> + soc@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0 0xffffffff>;
>> + compatible = "simple-bus";
>> +
>> + tlmm: pinctrl@1000000 {
>> + compatible = "qcom,ipq5332-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 53>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + serial_0_pins: serial0-state {
>> + pins = "gpio18", "gpio19";
>> + function = "blsp0_uart0";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + gcc: clock-controller@1800000 {
>> + compatible = "qcom,ipq5332-gcc";
>> + reg = <0x01800000 0x80000>;
>> + #clock-cells = <0x1>;
>> + #reset-cells = <0x1>;
>> + #power-domain-cells = <1>;
>> + clock-names = "xo",
>> + "sleep_clk",
>> + "pcie_2lane_phy_pipe_clk",
>> + "pcie_2lane_phy_pipe_clk_x1",
>> + "usb_pcie_wrapper_pipe_clk";
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <0>,
>> + <0>,
>> + <0>;
>> + };
>> +
>> + sdhc: mmc@7804000 {
>> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
>> +
>> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> + <&gcc GCC_SDCC1_APPS_CLK>,
>> + <&xo_board>;
>> + clock-names = "iface", "core", "xo";
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + max-frequency = <192000000>;
>> + bus-width = <4>;
> Aren't these five properties of the board? Do you fix the exact eMMC
> module inside the SoC?
Okay, will cross check this and update it.
>
>> + status = "disabled";
>> + };
>> +
>> + blsp1_uart0: serial@78af000 {
>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> + reg = <0x078af000 0x200>;
>> + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + status = "disabled";
>> + };
>> +
>> + intc: interrupt-controller@b000000 {
>> + compatible = "qcom,msm-qgic2";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-controller;
>> + #interrupt-cells = <0x3>;
>> + reg = <0x0b000000 0x1000>, /* GICD */
>> + <0x0b002000 0x1000>, /* GICC */
>> + <0x0b001000 0x1000>, /* GICH */
>> + <0x0b004000 0x1000>; /* GICV */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + ranges = <0 0x0b00c000 0x3000>;
>> +
>> + v2m0: v2m@0 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x0 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m1: v2m@1 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00001000 0xffd>;
>> + msi-controller;
>> + };
>> +
>> + v2m2: v2m@2 {
>> + compatible = "arm,gic-v2m-frame";
>> + reg = <0x00002000 0xffd>;
>> + msi-controller;
>> + };
>> + };
>> +
>> + timer@b120000 {
>> + compatible = "arm,armv7-timer-mem";
>> + reg = <0x0b120000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + frame@b120000 {
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b121000 0x1000>,
>> + <0x0b122000 0x1000>;
>> + };
>> +
>> + frame@b123000 {
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b123000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@b124000 {
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b124000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@b125000 {
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b125000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@b126000 {
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b126000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@b127000 {
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b127000 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@b128000 {
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0b128000 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> +
> Drop blank line.
Ack.
>
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +};
> Best regards,
> Krzysztof
Thanks,
Kathiravan T.
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* [PATCH 1/2] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
From: Jagan Teki @ 2023-01-25 16:10 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Manoj Sai
From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
---
.../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
index 3e6578f27ec0..170af01371ff 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
@@ -21,6 +21,13 @@ chosen: chosen {
stdout-path = "serial2:1500000n8";
};
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -83,6 +90,29 @@ &combphy1 {
status = "okay";
};
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "input";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_rgmii_bus
+ &gmac1m0_clkinout>;
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x46>;
+ rx_delay = <0x2e>;
+ status = "okay";
+};
+
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
@@ -105,7 +135,70 @@ &hdmi_sound {
status = "okay";
};
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible="ethernet-phy-ieee802.3-c22";
+ reg= <0x0>;
+ };
+};
+
&pinctrl {
+ gmac1 {
+ gmac1m0_miim: gmac1m0-miim {
+ rockchip,pins =
+ /* gmac1_mdcm0 */
+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_mdiom0 */
+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
+ };
+
+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0m0 */
+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_rxd1m0 */
+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_rxdvcrsm0 */
+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
+ };
+
+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0m0 */
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_txd1m0 */
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_txenm0 */
+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
+ };
+
+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclkm0 */
+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_txclkm0 */
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
+ };
+
+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2m0 */
+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_rxd3m0 */
+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_txd2m0 */
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
+ /* gmac1_txd3m0 */
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
+ };
+
+ gmac1m0_clkinout: gmac1m0-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinoutm0 */
+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
+ };
+ };
+
leds {
pi_nled_activity: pi-nled-activity {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.25.1
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* [PATCH 2/2] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for Radxa CM3
From: Jagan Teki @ 2023-01-25 16:10 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
In-Reply-To: <20230125161023.12115-1-jagan@amarulasolutions.com>
Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
Add nodes for enabling it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
.../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
index 23a85a13311a..3de3a4f38756 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
@@ -66,6 +66,15 @@ vcca_1v8: vcca-1v8-regulator {
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_p>;
};
+
+ sdio_pwrseq: pwrseq-sdio {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk817 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on_h>;
+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
};
&cpu0 {
@@ -287,6 +296,20 @@ regulator-state-mem {
};
&pinctrl {
+ bluetooth {
+ bt_host_wake_h: bt-host-wake-h {
+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on_h: bt-reg-on-h {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h: bt-wake-host-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -298,6 +321,16 @@ user_led2: user-led2 {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wifi {
+ wifi_reg_on_h: wifi-reg-on-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake_h: wifi-host-wake-h {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pmu_io_domains {
@@ -318,6 +351,34 @@ &saradc {
status = "okay";
};
+&sdmmc1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm43455-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_h>;
+ };
+};
+
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
@@ -330,6 +391,25 @@ &sdhci {
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk817 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
+ vbat-supply = <&vcc_3v3>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
&usb2phy0 {
status = "okay";
};
--
2.25.1
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^ permalink raw reply related
* Re: [PATCH 01/10] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
From: Krzysztof Kozlowski @ 2023-01-25 16:20 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, agross, andersson, konrad.dybcio,
robh+dt, krzysztof.kozlowski+dt, mturquette, sboyd, ulf.hansson,
linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, dmitry.baryshkov, nfraprado, broonie, robimarko,
quic_gurus, bhupesh.sharma, linux-arm-msm, devicetree,
linux-kernel, linux-clk, linux-mmc, linux-gpio, linux-arm-kernel
In-Reply-To: <0b28f4a3-c445-7473-501b-39cbcfdb9889@quicinc.com>
On 25/01/2023 16:49, Kathiravan Thirumoorthy wrote:
>>
>>> @@ -0,0 +1,134 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-pinctrl.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Qualcomm IPQ5332 TLMM pin controller
>>> +
>>> +maintainers:
>>> + - Bjorn Andersson <andersson@kernel.org>
>>> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> +
>>> +description: |
>>> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
>>> +
>>> +allOf:
>>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>>> +
>>> +properties:
>>> + compatible:
>>> + const: qcom,ipq5332-tlmm
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + interrupts: true
>> missing maxItems
>>
>> Rebase your patches on latest next and use the latest bindings and
>> drivers as starting point.
>
>
> Changes are based on v6.2-rc1. I see the maxItems changes in
> linux-next. Will update this in V2.
Your patches cannot be based on v6.2-rc1. They won't even apply. You
miss entire development of last month.
>
>
>>> + interrupt-controller: true
>>> + "#interrupt-cells": true
>>> + gpio-controller: true
>>> + "#gpio-cells": true
>>> + gpio-ranges: true
>>> + wakeup-parent: true
>>> +
>>> + gpio-reserved-ranges:
>>> + minItems: 1
>>> + maxItems: 27
>>> +
>>> + gpio-line-names:
>>> + maxItems: 53
>> You have 54 GPIOs.
>
>
> Sorry, GPIO ranges are from 0-52, will update it in all places in V2.
Ah, then the gpio pattern needs a fix.
Best regards,
Krzysztof
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* Re: [PATCH] dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
From: Jassi Brar @ 2023-01-25 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, David Airlie, Daniel Vetter,
Bartosz Golaszewski, Jean Delvare, Guenter Roeck, Thomas Gleixner,
Marc Zyngier, Mauro Carvalho Chehab, Lee Jones, Ulf Hansson,
Richard Weinberger, Vignesh Raghavendra, Sebastian Reichel,
Mark Brown, Rafael J. Wysocki, Daniel Lezcano, Greg Kroah-Hartman,
linux-arm-kernel, dri-devel, linux-gpio, linux-hwmon, linux-media,
openbmc, linux-mmc, linux-mtd, linux-pm, alsa-devel, linux-spi,
linux-usb
In-Reply-To: <20230124230048.371144-1-robh@kernel.org>
On Tue, Jan 24, 2023 at 5:00 PM Rob Herring <robh@kernel.org> wrote:
>
> Just as unevaluatedProperties or additionalProperties are required at
> the top level of schemas, they should (and will) also be required for
> child node schemas. That ensures only documented properties are
> present.
>
> Add unevaluatedProperties or additionalProperties as appropriate, and
> then add any missing properties flagged by the addition.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
For the mailbox change,
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
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* Re: [PATCH v7 4/6] arm64: head: avoid cache invalidation when entering with the MMU on
From: Nathan Chancellor @ 2023-01-25 16:32 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: linux-efi, linux-arm-kernel, Will Deacon, Catalin Marinas,
Marc Zyngier, Mark Rutland, llvm
In-Reply-To: <20230111102236.1430401-5-ardb@kernel.org>
Hi Ard,
On Wed, Jan 11, 2023 at 11:22:34AM +0100, Ard Biesheuvel wrote:
> If we enter with the MMU on, there is no need for explicit cache
> invalidation for stores to memory, as they will be coherent with the
> caches.
>
> Let's take advantage of this, and create the ID map with the MMU still
> enabled if that is how we entered, and avoid any cache invalidation
> calls in that case.
>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> ---
> arch/arm64/kernel/head.S | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index c3b898efd3b5288d..d75f419206451d07 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -89,9 +89,9 @@
> SYM_CODE_START(primary_entry)
> bl record_mmu_state
> bl preserve_boot_args
> + bl create_idmap
> bl init_kernel_el // w0=cpu_boot_mode
> mov x20, x0
> - bl create_idmap
>
> /*
> * The following calls CPU setup code, see arch/arm64/mm/proc.S for
> @@ -377,12 +377,13 @@ SYM_FUNC_START_LOCAL(create_idmap)
> * accesses (MMU disabled), invalidate those tables again to
> * remove any speculatively loaded cache lines.
> */
> + cbnz x19, 0f // skip cache invalidation if MMU is on
> dmb sy
>
> adrp x0, init_idmap_pg_dir
> adrp x1, init_idmap_pg_end
> bl dcache_inval_poc
> - ret x28
> +0: ret x28
> SYM_FUNC_END(create_idmap)
>
> SYM_FUNC_START_LOCAL(create_kernel_mapping)
> --
> 2.39.0
>
Our CI started reporting a boot failure in QEMU with defconfig +
CONFIG_CPU_BIG_ENDIAN=y after this patch as commit 32b135a7fafe ("arm64:
head: avoid cache invalidation when entering with the MMU on") in the
arm64 tree (and now next-20230125).
https://github.com/ClangBuiltLinux/continuous-integration2/actions/runs/4001750912/jobs/6868612292
$ timeout --foreground 3m qemu-system-aarch64 \
-cpu max,pauth-impdef=true \
-machine virt,gic-version=max,virtualization=true \
-kernel Image.gz \
-append "console=ttyAMA0 earlycon" \
-display none \
-initrd rootfs.cpio
-m 512m \
-nodefaults \
-no-reboot \
-serial mon:stdio
qemu-system-aarch64: terminating on signal 15 from pid 389 (timeout)
defconfig is fine at the same change.
There is no output, which makes sense since this is pretty early in
boot. We are not booting via EFI, in case that matters. This does not
appear to be a toolchain problem, as I can reproduce it with the
kernel.org GCC toolchains.
If there is any more information I can provide or patches I can test, I
am more than happy to do so.
Cheers,
Nathan
# bad: [2e84eedb182e43a9113c2c83cc3373c2ae99ce19] Merge branch 'for-next/core' into for-kernelci
# good: [2241ab53cbb5cdb08a6b2d4688feb13971058f65] Linux 6.2-rc5
git bisect start '2e84eedb182e43a9113c2c83cc3373c2ae99ce19' 'v6.2-rc5'
# good: [3eb1b41fba97a1586e3ecca8c10547071f541567] kselftest/arm64: Add coverage of SME 2 and 2.1 hwcaps
git bisect good 3eb1b41fba97a1586e3ecca8c10547071f541567
# good: [daac835347a52d9d141be281e4657cc08a360e97] kselftest/arm64: Correct buffer size for SME ZA storage
git bisect good daac835347a52d9d141be281e4657cc08a360e97
# good: [baaf553d3bc330697c68a00f96cf11f4edfeac7e] arm64: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS
git bisect good baaf553d3bc330697c68a00f96cf11f4edfeac7e
# good: [4f2c9bf16a4bc209a674e7b76d8e829b917c7f84] arm64: Add compat hwcap SSBS
git bisect good 4f2c9bf16a4bc209a674e7b76d8e829b917c7f84
# good: [1abf363d085cf6133ef44900334ddd0f61dc3276] KVM: arm64: Use symbolic definition for ISR_EL1.A
git bisect good 1abf363d085cf6133ef44900334ddd0f61dc3276
# bad: [61786170383093908e9f5f8fd8c5c3ff0c3bbe03] efi: arm64: enter with MMU and caches enabled
git bisect bad 61786170383093908e9f5f8fd8c5c3ff0c3bbe03
# good: [9d7c13e5dde31270eb48a34204a2e06b1a719546] arm64: head: record the MMU state at primary entry
git bisect good 9d7c13e5dde31270eb48a34204a2e06b1a719546
# bad: [3dcf60bbfd284e5ebfa40c56172222425d10abf0] arm64: head: Clean the ID map and the HYP text to the PoC if needed
git bisect bad 3dcf60bbfd284e5ebfa40c56172222425d10abf0
# bad: [32b135a7fafebe7843abe5425159fa081ae56b7c] arm64: head: avoid cache invalidation when entering with the MMU on
git bisect bad 32b135a7fafebe7843abe5425159fa081ae56b7c
# first bad commit: [32b135a7fafebe7843abe5425159fa081ae56b7c] arm64: head: avoid cache invalidation when entering with the MMU on
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